diff options
Diffstat (limited to 'debian/patches/features/arm64/arm64-dts-rockchip-Add-NOR-flash-to-ODROID-M1.patch')
| -rw-r--r-- | debian/patches/features/arm64/arm64-dts-rockchip-Add-NOR-flash-to-ODROID-M1.patch | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/debian/patches/features/arm64/arm64-dts-rockchip-Add-NOR-flash-to-ODROID-M1.patch b/debian/patches/features/arm64/arm64-dts-rockchip-Add-NOR-flash-to-ODROID-M1.patch new file mode 100644 index 000000000..ebc21afec --- /dev/null +++ b/debian/patches/features/arm64/arm64-dts-rockchip-Add-NOR-flash-to-ODROID-M1.patch @@ -0,0 +1,100 @@ +From: Aurelien Jarno <aurelien@aurel32.net> +Date: Fri, 30 Sep 2022 07:12:37 +0200 +Subject: [04/13] arm64: dts: rockchip: Add NOR flash to ODROID-M1 +Origin: https://git.kernel.org/linus/9f96204b7dcf94d03cad41194447c665d10675b7 + +Enable the Rockchip Serial Flash Controller for the ODROID-M1 and add +the corresponding SPI NOR flash entry. The SFC is used in dual I/O mode +and not quad I/O mode, as the FSPI_D2 pin is shared with the EMMC_RSTn +pin. + +The partitions addresses and sizes are taken from the ODROID-M1 +Partition Table page on the ODROID wiki. + +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> +Tested-by: Dan Johansen <strit@manjaro.org> +Link: https://lore.kernel.org/r/20220930051246.391614-5-aurelien@aurel32.net +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + .../boot/dts/rockchip/rk3568-odroid-m1.dts | 58 +++++++++++++++++++ + 1 file changed, 58 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +index 112c65af3f55..94e839c9afab 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +@@ -351,6 +351,20 @@ rgmii_phy0: ethernet-phy@0 { + }; + + &pinctrl { ++ fspi { ++ fspi_dual_io_pins: fspi-dual-io-pins { ++ rockchip,pins = ++ /* fspi_clk */ ++ <1 RK_PD0 1 &pcfg_pull_none>, ++ /* fspi_cs0n */ ++ <1 RK_PD3 1 &pcfg_pull_none>, ++ /* fspi_d0 */ ++ <1 RK_PD1 1 &pcfg_pull_none>, ++ /* fspi_d1 */ ++ <1 RK_PD2 1 &pcfg_pull_none>; ++ }; ++ }; ++ + leds { + led_power_pin: led-power-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +@@ -409,6 +423,50 @@ &sdmmc0 { + status = "okay"; + }; + ++&sfc { ++ /* Dual I/O mode as the D2 pin conflicts with the eMMC */ ++ pinctrl-0 = <&fspi_dual_io_pins>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <100000000>; ++ spi-rx-bus-width = <2>; ++ spi-tx-bus-width = <1>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "SPL"; ++ reg = <0x0 0xe0000>; ++ }; ++ partition@e0000 { ++ label = "U-Boot Env"; ++ reg = <0xe0000 0x20000>; ++ }; ++ partition@100000 { ++ label = "U-Boot"; ++ reg = <0x100000 0x200000>; ++ }; ++ partition@300000 { ++ label = "splash"; ++ reg = <0x300000 0x100000>; ++ }; ++ partition@400000 { ++ label = "Filesystem"; ++ reg = <0x400000 0xc00000>; ++ }; ++ }; ++ }; ++}; ++ + &tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; +-- +2.35.1 + |