diff options
Diffstat (limited to 'debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch')
| -rw-r--r-- | debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch new file mode 100644 index 000000000..1a8063e0f --- /dev/null +++ b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch @@ -0,0 +1,82 @@ +From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> +Date: Sat, 12 Nov 2022 17:04:01 +0100 +Subject: arm64: dts: rockchip: Enable PCIe 2 on SOQuartz CM4IO +Origin: https://git.kernel.org/linus/3736aa7ecc4cd9b4abce30052bad00aba4f0362f + +This patch enables the PCIe2 on the CM4IO board when paired with +a SOQuartz CM4 System-on-Module board. combphy2 also needs to be +enabled in this case to make the PHY work for this. + +Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> +Link: https://lore.kernel.org/r/20221112160404.70868-5-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + .../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 11 +++++++++++ + arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 15 +++++++++++++++ + 2 files changed, 26 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts +index e00568a6be5c..263ce40770dd 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts +@@ -30,6 +30,12 @@ + }; + }; + ++/* phy for pcie */ ++&combphy2 { ++ phy-supply = <&vcc3v3_sys>; ++ status = "okay"; ++}; ++ + &gmac1 { + status = "okay"; + }; +@@ -105,6 +111,11 @@ + status = "okay"; + }; + ++&pcie2x1 { ++ vpcie3v3-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ + &rgmii_phy1 { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +index 1b975822effa..ce7165d7f1a1 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +@@ -487,6 +487,12 @@ + }; + }; + ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_reset_h>; ++ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; ++}; ++ + &pinctrl { + bt { + bt_enable_h: bt-enable-h { +@@ -512,6 +518,15 @@ + }; + }; + ++ pcie { ++ pcie_clkreq_h: pcie-clkreq-h { ++ rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ pcie_reset_h: pcie-reset-h { ++ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; +-- +2.39.0 + |