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-rw-r--r--drivers/net/ethernet/dec/Kconfig20
-rw-r--r--drivers/net/ethernet/dec/Makefile6
-rw-r--r--drivers/net/ethernet/dec/tulip/21142.c257
-rw-r--r--drivers/net/ethernet/dec/tulip/Kconfig154
-rw-r--r--drivers/net/ethernet/dec/tulip/Makefile19
-rw-r--r--drivers/net/ethernet/dec/tulip/de2104x.c2197
-rw-r--r--drivers/net/ethernet/dec/tulip/dmfe.c2218
-rw-r--r--drivers/net/ethernet/dec/tulip/eeprom.c381
-rw-r--r--drivers/net/ethernet/dec/tulip/interrupt.c822
-rw-r--r--drivers/net/ethernet/dec/tulip/media.c547
-rw-r--r--drivers/net/ethernet/dec/tulip/pnic.c170
-rw-r--r--drivers/net/ethernet/dec/tulip/pnic2.c403
-rw-r--r--drivers/net/ethernet/dec/tulip/timer.c176
-rw-r--r--drivers/net/ethernet/dec/tulip/tulip.h569
-rw-r--r--drivers/net/ethernet/dec/tulip/tulip_core.c1934
-rw-r--r--drivers/net/ethernet/dec/tulip/uli526x.c1801
-rw-r--r--drivers/net/ethernet/dec/tulip/winbond-840.c1629
-rw-r--r--drivers/net/ethernet/dec/tulip/xircom_cb.c1172
18 files changed, 14475 insertions, 0 deletions
diff --git a/drivers/net/ethernet/dec/Kconfig b/drivers/net/ethernet/dec/Kconfig
new file mode 100644
index 000000000..9e5e5f10b
--- /dev/null
+++ b/drivers/net/ethernet/dec/Kconfig
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Digital Equipment Inc network device configuration
+#
+
+config NET_VENDOR_DEC
+ bool "Digital Equipment devices"
+ default y
+ depends on PCI || EISA || CARDBUS
+ help
+ If you have a network (Ethernet) card belonging to this class, say Y.
+
+ Note that the answer to this question doesn't directly affect the
+ kernel: saying N will just cause the configurator to skip all
+ the questions about DEC cards. If you say Y, you will be asked for
+ your specific card in the following questions.
+
+if NET_VENDOR_DEC
+source "drivers/net/ethernet/dec/tulip/Kconfig"
+endif # NET_VENDOR_DEC
diff --git a/drivers/net/ethernet/dec/Makefile b/drivers/net/ethernet/dec/Makefile
new file mode 100644
index 000000000..e8aa12c84
--- /dev/null
+++ b/drivers/net/ethernet/dec/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Makefile for the Digital Equipment Inc. network device drivers.
+#
+
+obj-$(CONFIG_NET_TULIP) += tulip/
diff --git a/drivers/net/ethernet/dec/tulip/21142.c b/drivers/net/ethernet/dec/tulip/21142.c
new file mode 100644
index 000000000..369858272
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/21142.c
@@ -0,0 +1,257 @@
+/*
+ drivers/net/ethernet/dec/tulip/21142.c
+
+ Copyright 2000,2001 The Linux Kernel Team
+ Written/copyright 1994-2001 by Donald Becker.
+
+ This software may be used and distributed according to the terms
+ of the GNU General Public License, incorporated herein by reference.
+
+ DC21143 manual "21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
+ Hardware Reference Manual" is currently available at :
+ http://developer.intel.com/design/network/manuals/278074.htm
+
+ Please submit bugs to http://bugzilla.kernel.org/ .
+*/
+
+#include <linux/delay.h>
+#include "tulip.h"
+
+
+static u16 t21142_csr13[] = { 0x0001, 0x0009, 0x0009, 0x0000, 0x0001, };
+u16 t21142_csr14[] = { 0xFFFF, 0x0705, 0x0705, 0x0000, 0x7F3D, };
+static u16 t21142_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
+
+
+/* Handle the 21143 uniquely: do autoselect with NWay, not the EEPROM list
+ of available transceivers. */
+void t21142_media_task(struct work_struct *work)
+{
+ struct tulip_private *tp =
+ container_of(work, struct tulip_private, media_work);
+ struct net_device *dev = tp->dev;
+ void __iomem *ioaddr = tp->base_addr;
+ int csr12 = ioread32(ioaddr + CSR12);
+ int next_tick = 60*HZ;
+ int new_csr6 = 0;
+ int csr14 = ioread32(ioaddr + CSR14);
+
+ /* CSR12[LS10,LS100] are not reliable during autonegotiation */
+ if ((csr14 & 0x80) && (csr12 & 0x7000) != 0x5000)
+ csr12 |= 6;
+ if (tulip_debug > 2)
+ dev_info(&dev->dev, "21143 negotiation status %08x, %s\n",
+ csr12, medianame[dev->if_port]);
+ if (tulip_media_cap[dev->if_port] & MediaIsMII) {
+ if (tulip_check_duplex(dev) < 0) {
+ netif_carrier_off(dev);
+ next_tick = 3*HZ;
+ } else {
+ netif_carrier_on(dev);
+ next_tick = 60*HZ;
+ }
+ } else if (tp->nwayset) {
+ /* Don't screw up a negotiated session! */
+ if (tulip_debug > 1)
+ dev_info(&dev->dev,
+ "Using NWay-set %s media, csr12 %08x\n",
+ medianame[dev->if_port], csr12);
+ } else if (tp->medialock) {
+ ;
+ } else if (dev->if_port == 3) {
+ if (csr12 & 2) { /* No 100mbps link beat, revert to 10mbps. */
+ if (tulip_debug > 1)
+ dev_info(&dev->dev,
+ "No 21143 100baseTx link beat, %08x, trying NWay\n",
+ csr12);
+ t21142_start_nway(dev);
+ next_tick = 3*HZ;
+ }
+ } else if ((csr12 & 0x7000) != 0x5000) {
+ /* Negotiation failed. Search media types. */
+ if (tulip_debug > 1)
+ dev_info(&dev->dev,
+ "21143 negotiation failed, status %08x\n",
+ csr12);
+ if (!(csr12 & 4)) { /* 10mbps link beat good. */
+ new_csr6 = 0x82420000;
+ dev->if_port = 0;
+ iowrite32(0, ioaddr + CSR13);
+ iowrite32(0x0003FFFF, ioaddr + CSR14);
+ iowrite16(t21142_csr15[dev->if_port], ioaddr + CSR15);
+ iowrite32(t21142_csr13[dev->if_port], ioaddr + CSR13);
+ } else {
+ /* Select 100mbps port to check for link beat. */
+ new_csr6 = 0x83860000;
+ dev->if_port = 3;
+ iowrite32(0, ioaddr + CSR13);
+ iowrite32(0x0003FFFF, ioaddr + CSR14);
+ iowrite16(8, ioaddr + CSR15);
+ iowrite32(1, ioaddr + CSR13);
+ }
+ if (tulip_debug > 1)
+ dev_info(&dev->dev, "Testing new 21143 media %s\n",
+ medianame[dev->if_port]);
+ if (new_csr6 != (tp->csr6 & ~0x00D5)) {
+ tp->csr6 &= 0x00D5;
+ tp->csr6 |= new_csr6;
+ iowrite32(0x0301, ioaddr + CSR12);
+ tulip_restart_rxtx(tp);
+ }
+ next_tick = 3*HZ;
+ }
+
+ /* mod_timer synchronizes us with potential add_timer calls
+ * from interrupts.
+ */
+ mod_timer(&tp->timer, RUN_AT(next_tick));
+}
+
+
+void t21142_start_nway(struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+ int csr14 = ((tp->sym_advertise & 0x0780) << 9) |
+ ((tp->sym_advertise & 0x0020) << 1) | 0xffbf;
+
+ dev->if_port = 0;
+ tp->nway = tp->mediasense = 1;
+ tp->nwayset = tp->lpar = 0;
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "Restarting 21143 autonegotiation, csr14=%08x\n",
+ csr14);
+ iowrite32(0x0001, ioaddr + CSR13);
+ udelay(100);
+ iowrite32(csr14, ioaddr + CSR14);
+ tp->csr6 = 0x82420000 | (tp->sym_advertise & 0x0040 ? FullDuplex : 0);
+ iowrite32(tp->csr6, ioaddr + CSR6);
+ if (tp->mtable && tp->mtable->csr15dir) {
+ iowrite32(tp->mtable->csr15dir, ioaddr + CSR15);
+ iowrite32(tp->mtable->csr15val, ioaddr + CSR15);
+ } else
+ iowrite16(0x0008, ioaddr + CSR15);
+ iowrite32(0x1301, ioaddr + CSR12); /* Trigger NWAY. */
+}
+
+
+
+void t21142_lnk_change(struct net_device *dev, int csr5)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+ int csr12 = ioread32(ioaddr + CSR12);
+ int csr14 = ioread32(ioaddr + CSR14);
+
+ /* CSR12[LS10,LS100] are not reliable during autonegotiation */
+ if ((csr14 & 0x80) && (csr12 & 0x7000) != 0x5000)
+ csr12 |= 6;
+ if (tulip_debug > 1)
+ dev_info(&dev->dev,
+ "21143 link status interrupt %08x, CSR5 %x, %08x\n",
+ csr12, csr5, csr14);
+
+ /* If NWay finished and we have a negotiated partner capability. */
+ if (tp->nway && !tp->nwayset && (csr12 & 0x7000) == 0x5000) {
+ int setup_done = 0;
+ int negotiated = tp->sym_advertise & (csr12 >> 16);
+ tp->lpar = csr12 >> 16;
+ tp->nwayset = 1;
+ /* If partner cannot negotiate, it is 10Mbps Half Duplex */
+ if (!(csr12 & 0x8000)) dev->if_port = 0;
+ else if (negotiated & 0x0100) dev->if_port = 5;
+ else if (negotiated & 0x0080) dev->if_port = 3;
+ else if (negotiated & 0x0040) dev->if_port = 4;
+ else if (negotiated & 0x0020) dev->if_port = 0;
+ else {
+ tp->nwayset = 0;
+ if ((csr12 & 2) == 0 && (tp->sym_advertise & 0x0180))
+ dev->if_port = 3;
+ }
+ tp->full_duplex = (tulip_media_cap[dev->if_port] & MediaAlwaysFD) ? 1:0;
+
+ if (tulip_debug > 1) {
+ if (tp->nwayset)
+ dev_info(&dev->dev,
+ "Switching to %s based on link negotiation %04x & %04x = %04x\n",
+ medianame[dev->if_port],
+ tp->sym_advertise, tp->lpar,
+ negotiated);
+ else
+ dev_info(&dev->dev,
+ "Autonegotiation failed, using %s, link beat status %04x\n",
+ medianame[dev->if_port], csr12);
+ }
+
+ if (tp->mtable) {
+ int i;
+ for (i = 0; i < tp->mtable->leafcount; i++)
+ if (tp->mtable->mleaf[i].media == dev->if_port) {
+ int startup = ! ((tp->chip_id == DC21143 && (tp->revision == 48 || tp->revision == 65)));
+ tp->cur_index = i;
+ tulip_select_media(dev, startup);
+ setup_done = 1;
+ break;
+ }
+ }
+ if ( ! setup_done) {
+ tp->csr6 = (dev->if_port & 1 ? 0x838E0000 : 0x82420000) | (tp->csr6 & 0x20ff);
+ if (tp->full_duplex)
+ tp->csr6 |= 0x0200;
+ iowrite32(1, ioaddr + CSR13);
+ }
+#if 0 /* Restart shouldn't be needed. */
+ iowrite32(tp->csr6 | RxOn, ioaddr + CSR6);
+ if (tulip_debug > 2)
+ netdev_dbg(dev, " Restarting Tx and Rx, CSR5 is %08x\n",
+ ioread32(ioaddr + CSR5));
+#endif
+ tulip_start_rxtx(tp);
+ if (tulip_debug > 2)
+ netdev_dbg(dev, " Setting CSR6 %08x/%x CSR12 %08x\n",
+ tp->csr6, ioread32(ioaddr + CSR6),
+ ioread32(ioaddr + CSR12));
+ } else if ((tp->nwayset && (csr5 & 0x08000000) &&
+ (dev->if_port == 3 || dev->if_port == 5) &&
+ (csr12 & 2) == 2) ||
+ (tp->nway && (csr5 & (TPLnkFail)))) {
+ /* Link blew? Maybe restart NWay. */
+ del_timer_sync(&tp->timer);
+ t21142_start_nway(dev);
+ tp->timer.expires = RUN_AT(3*HZ);
+ add_timer(&tp->timer);
+ } else if (dev->if_port == 3 || dev->if_port == 5) {
+ if (tulip_debug > 1)
+ dev_info(&dev->dev, "21143 %s link beat %s\n",
+ medianame[dev->if_port],
+ (csr12 & 2) ? "failed" : "good");
+ if ((csr12 & 2) && ! tp->medialock) {
+ del_timer_sync(&tp->timer);
+ t21142_start_nway(dev);
+ tp->timer.expires = RUN_AT(3*HZ);
+ add_timer(&tp->timer);
+ } else if (dev->if_port == 5)
+ iowrite32(csr14 & ~0x080, ioaddr + CSR14);
+ } else if (dev->if_port == 0 || dev->if_port == 4) {
+ if ((csr12 & 4) == 0)
+ dev_info(&dev->dev, "21143 10baseT link beat good\n");
+ } else if (!(csr12 & 4)) { /* 10mbps link beat good. */
+ if (tulip_debug)
+ dev_info(&dev->dev, "21143 10mbps sensed media\n");
+ dev->if_port = 0;
+ } else if (tp->nwayset) {
+ if (tulip_debug)
+ dev_info(&dev->dev, "21143 using NWay-set %s, csr6 %08x\n",
+ medianame[dev->if_port], tp->csr6);
+ } else { /* 100mbps link beat good. */
+ if (tulip_debug)
+ dev_info(&dev->dev, "21143 100baseTx sensed media\n");
+ dev->if_port = 3;
+ tp->csr6 = 0x838E0000 | (tp->csr6 & 0x20ff);
+ iowrite32(0x0003FF7F, ioaddr + CSR14);
+ iowrite32(0x0301, ioaddr + CSR12);
+ tulip_restart_rxtx(tp);
+ }
+}
+
+
diff --git a/drivers/net/ethernet/dec/tulip/Kconfig b/drivers/net/ethernet/dec/tulip/Kconfig
new file mode 100644
index 000000000..078a12f07
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/Kconfig
@@ -0,0 +1,154 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Tulip family network device configuration
+#
+
+config NET_TULIP
+ bool "DEC - Tulip devices"
+ depends on (PCI || EISA || CARDBUS)
+ help
+ This selects the "Tulip" family of EISA/PCI network cards.
+
+if NET_TULIP
+
+config DE2104X
+ tristate "Early DECchip Tulip (dc2104x) PCI support"
+ depends on PCI
+ select CRC32
+ help
+ This driver is developed for the SMC EtherPower series Ethernet
+ cards and also works with cards based on the DECchip
+ 21040 (Tulip series) chips. Some LinkSys PCI cards are
+ of this type. (If your card is NOT SMC EtherPower 10/100 PCI
+ (smc9332dst), you can also try the driver for "Generic DECchip"
+ cards, below. However, most people with a network card of this type
+ will say Y here.)
+
+ To compile this driver as a module, choose M here. The module will
+ be called de2104x.
+
+config DE2104X_DSL
+ int "Descriptor Skip Length in 32 bit longwords"
+ depends on DE2104X
+ range 0 31
+ default 0
+ help
+ Setting this value allows to align ring buffer descriptors into their
+ own cache lines. Value of 4 corresponds to the typical 32 byte line
+ (the descriptor is 16 bytes). This is necessary on systems that lack
+ cache coherence, an example is PowerMac 5500. Otherwise 0 is safe.
+ Default is 0, and range is 0 to 31.
+
+config TULIP
+ tristate "DECchip Tulip (dc2114x) PCI support"
+ depends on PCI
+ select CRC32
+ help
+ This driver is developed for the SMC EtherPower series Ethernet
+ cards and also works with cards based on the DECchip
+ 21140 (Tulip series) chips. Some LinkSys PCI cards are
+ of this type. (If your card is NOT SMC EtherPower 10/100 PCI
+ (smc9332dst), you can also try the driver for "Generic DECchip"
+ cards, above. However, most people with a network card of this type
+ will say Y here.)
+
+ To compile this driver as a module, choose M here. The module will
+ be called tulip.
+
+config TULIP_MWI
+ bool "New bus configuration"
+ depends on TULIP
+ help
+ This configures your Tulip card specifically for the card and
+ system cache line size type you are using.
+
+ This is experimental code, not yet tested on many boards.
+
+ If unsure, say N.
+
+config TULIP_MMIO
+ bool "Use PCI shared mem for NIC registers"
+ depends on TULIP
+ help
+ Use PCI shared memory for the NIC registers, rather than going through
+ the Tulip's PIO (programmed I/O ports). Faster, but could produce
+ obscure bugs if your mainboard has memory controller timing issues.
+ If in doubt, say N.
+
+config TULIP_NAPI
+ bool "Use RX polling (NAPI)"
+ depends on TULIP
+ help
+ NAPI is a new driver API designed to reduce CPU and interrupt load
+ when the driver is receiving lots of packets from the card. It is
+ still somewhat experimental and thus not yet enabled by default.
+
+ If your estimated Rx load is 10kpps or more, or if the card will be
+ deployed on potentially unfriendly networks (e.g. in a firewall),
+ then say Y here.
+
+ If in doubt, say N.
+
+config TULIP_NAPI_HW_MITIGATION
+ bool "Use Interrupt Mitigation"
+ depends on TULIP_NAPI
+ help
+ Use HW to reduce RX interrupts. Not strictly necessary since NAPI
+ reduces RX interrupts by itself. Interrupt mitigation reduces RX
+ interrupts even at low levels of traffic at the cost of a small
+ latency.
+
+ If in doubt, say Y.
+
+config TULIP_DM910X
+ def_bool y
+ depends on TULIP && SPARC
+
+config WINBOND_840
+ tristate "Winbond W89c840 Ethernet support"
+ depends on PCI
+ select CRC32
+ select MII
+ help
+ This driver is for the Winbond W89c840 chip. It also works with
+ the TX9882 chip on the Compex RL100-ATX board.
+ More specific information and updates are available from
+ <http://www.scyld.com/network/drivers.html>.
+
+config DM9102
+ tristate "Davicom DM910x/DM980x support"
+ depends on PCI
+ select CRC32
+ help
+ This driver is for DM9102(A)/DM9132/DM9801 compatible PCI cards from
+ Davicom (<http://www.davicom.com.tw/>). If you have such a network
+ (Ethernet) card, say Y. Some information is contained in the file
+ <file:Documentation/networking/device_drivers/ethernet/dec/dmfe.rst>.
+
+ To compile this driver as a module, choose M here. The module will
+ be called dmfe.
+
+config ULI526X
+ tristate "ULi M526x controller support"
+ depends on PCI
+ select CRC32
+ help
+ This driver is for ULi M5261/M5263 10/100M Ethernet Controller
+ (<http://www.nvidia.com/page/uli_drivers.html>).
+
+ To compile this driver as a module, choose M here. The module will
+ be called uli526x.
+
+config PCMCIA_XIRCOM
+ tristate "Xircom CardBus support"
+ depends on CARDBUS
+ help
+ This driver is for the Digital "Tulip" Ethernet CardBus adapters.
+ It should work with most DEC 21*4*-based chips/ethercards, as well
+ as with work-alike chips from Lite-On (PNIC) and Macronix (MXIC) and
+ ASIX.
+
+ To compile this driver as a module, choose M here. The module will
+ be called xircom_cb. If unsure, say N.
+
+endif # NET_TULIP
diff --git a/drivers/net/ethernet/dec/tulip/Makefile b/drivers/net/ethernet/dec/tulip/Makefile
new file mode 100644
index 000000000..d4f1d21d2
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/Makefile
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the Linux "Tulip" family network device drivers.
+#
+
+ccflags-$(CONFIG_NET_TULIP) := -DDEBUG
+
+obj-$(CONFIG_PCMCIA_XIRCOM) += xircom_cb.o
+obj-$(CONFIG_DM9102) += dmfe.o
+obj-$(CONFIG_WINBOND_840) += winbond-840.o
+obj-$(CONFIG_DE2104X) += de2104x.o
+obj-$(CONFIG_TULIP) += tulip.o
+obj-$(CONFIG_ULI526X) += uli526x.o
+
+# Declare multi-part drivers.
+
+tulip-objs := eeprom.o interrupt.o media.o \
+ timer.o tulip_core.o \
+ 21142.o pnic.o pnic2.o
diff --git a/drivers/net/ethernet/dec/tulip/de2104x.c b/drivers/net/ethernet/dec/tulip/de2104x.c
new file mode 100644
index 000000000..cd3dc4b89
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/de2104x.c
@@ -0,0 +1,2197 @@
+/* de2104x.c: A Linux PCI Ethernet driver for Intel/Digital 21040/1 chips. */
+/*
+ Copyright 2001,2003 Jeff Garzik <jgarzik@pobox.com>
+
+ Copyright 1994, 1995 Digital Equipment Corporation. [de4x5.c]
+ Written/copyright 1994-2001 by Donald Becker. [tulip.c]
+
+ This software may be used and distributed according to the terms of
+ the GNU General Public License (GPL), incorporated herein by reference.
+ Drivers based on or derived from this code fall under the GPL and must
+ retain the authorship, copyright and license notice. This file is not
+ a complete program and may only be used when the entire operating
+ system is licensed under the GPL.
+
+ See the file COPYING in this distribution for more information.
+
+ TODO, in rough priority order:
+ * Support forcing media type with a module parameter,
+ like dl2k.c/sundance.c
+ * Constants (module parms?) for Rx work limit
+ * Complete reset on PciErr
+ * Jumbo frames / dev->change_mtu
+ * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
+ * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
+ * Implement Tx software interrupt mitigation via
+ Tx descriptor bit
+
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#define DRV_NAME "de2104x"
+#define DRV_RELDATE "Mar 17, 2004"
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/ethtool.h>
+#include <linux/compiler.h>
+#include <linux/rtnetlink.h>
+#include <linux/crc32.h>
+#include <linux/slab.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <linux/uaccess.h>
+#include <asm/unaligned.h>
+
+MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
+MODULE_DESCRIPTION("Intel/Digital 21040/1 series PCI Ethernet driver");
+MODULE_LICENSE("GPL");
+
+static int debug = -1;
+module_param (debug, int, 0);
+MODULE_PARM_DESC (debug, "de2104x bitmapped message enable number");
+
+/* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
+#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
+ defined(CONFIG_SPARC) || defined(__ia64__) || \
+ defined(__sh__) || defined(__mips__)
+static int rx_copybreak = 1518;
+#else
+static int rx_copybreak = 100;
+#endif
+module_param (rx_copybreak, int, 0);
+MODULE_PARM_DESC (rx_copybreak, "de2104x Breakpoint at which Rx packets are copied");
+
+#define DE_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
+ NETIF_MSG_PROBE | \
+ NETIF_MSG_LINK | \
+ NETIF_MSG_IFDOWN | \
+ NETIF_MSG_IFUP | \
+ NETIF_MSG_RX_ERR | \
+ NETIF_MSG_TX_ERR)
+
+/* Descriptor skip length in 32 bit longwords. */
+#ifndef CONFIG_DE2104X_DSL
+#define DSL 0
+#else
+#define DSL CONFIG_DE2104X_DSL
+#endif
+
+#define DE_RX_RING_SIZE 128
+#define DE_TX_RING_SIZE 64
+#define DE_RING_BYTES \
+ ((sizeof(struct de_desc) * DE_RX_RING_SIZE) + \
+ (sizeof(struct de_desc) * DE_TX_RING_SIZE))
+#define NEXT_TX(N) (((N) + 1) & (DE_TX_RING_SIZE - 1))
+#define NEXT_RX(N) (((N) + 1) & (DE_RX_RING_SIZE - 1))
+#define TX_BUFFS_AVAIL(CP) \
+ (((CP)->tx_tail <= (CP)->tx_head) ? \
+ (CP)->tx_tail + (DE_TX_RING_SIZE - 1) - (CP)->tx_head : \
+ (CP)->tx_tail - (CP)->tx_head - 1)
+
+#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
+#define RX_OFFSET 2
+
+#define DE_SETUP_SKB ((struct sk_buff *) 1)
+#define DE_DUMMY_SKB ((struct sk_buff *) 2)
+#define DE_SETUP_FRAME_WORDS 96
+#define DE_EEPROM_WORDS 256
+#define DE_EEPROM_SIZE (DE_EEPROM_WORDS * sizeof(u16))
+#define DE_MAX_MEDIA 5
+
+#define DE_MEDIA_TP_AUTO 0
+#define DE_MEDIA_BNC 1
+#define DE_MEDIA_AUI 2
+#define DE_MEDIA_TP 3
+#define DE_MEDIA_TP_FD 4
+#define DE_MEDIA_INVALID DE_MAX_MEDIA
+#define DE_MEDIA_FIRST 0
+#define DE_MEDIA_LAST (DE_MAX_MEDIA - 1)
+#define DE_AUI_BNC (SUPPORTED_AUI | SUPPORTED_BNC)
+
+#define DE_TIMER_LINK (60 * HZ)
+#define DE_TIMER_NO_LINK (5 * HZ)
+
+#define DE_NUM_REGS 16
+#define DE_REGS_SIZE (DE_NUM_REGS * sizeof(u32))
+#define DE_REGS_VER 1
+
+/* Time in jiffies before concluding the transmitter is hung. */
+#define TX_TIMEOUT (6*HZ)
+
+/* This is a mysterious value that can be written to CSR11 in the 21040 (only)
+ to support a pre-NWay full-duplex signaling mechanism using short frames.
+ No one knows what it should be, but if left at its default value some
+ 10base2(!) packets trigger a full-duplex-request interrupt. */
+#define FULL_DUPLEX_MAGIC 0x6969
+
+enum {
+ /* NIC registers */
+ BusMode = 0x00,
+ TxPoll = 0x08,
+ RxPoll = 0x10,
+ RxRingAddr = 0x18,
+ TxRingAddr = 0x20,
+ MacStatus = 0x28,
+ MacMode = 0x30,
+ IntrMask = 0x38,
+ RxMissed = 0x40,
+ ROMCmd = 0x48,
+ CSR11 = 0x58,
+ SIAStatus = 0x60,
+ CSR13 = 0x68,
+ CSR14 = 0x70,
+ CSR15 = 0x78,
+ PCIPM = 0x40,
+
+ /* BusMode bits */
+ CmdReset = (1 << 0),
+ CacheAlign16 = 0x00008000,
+ BurstLen4 = 0x00000400,
+ DescSkipLen = (DSL << 2),
+
+ /* Rx/TxPoll bits */
+ NormalTxPoll = (1 << 0),
+ NormalRxPoll = (1 << 0),
+
+ /* Tx/Rx descriptor status bits */
+ DescOwn = (1 << 31),
+ RxError = (1 << 15),
+ RxErrLong = (1 << 7),
+ RxErrCRC = (1 << 1),
+ RxErrFIFO = (1 << 0),
+ RxErrRunt = (1 << 11),
+ RxErrFrame = (1 << 14),
+ RingEnd = (1 << 25),
+ FirstFrag = (1 << 29),
+ LastFrag = (1 << 30),
+ TxError = (1 << 15),
+ TxFIFOUnder = (1 << 1),
+ TxLinkFail = (1 << 2) | (1 << 10) | (1 << 11),
+ TxMaxCol = (1 << 8),
+ TxOWC = (1 << 9),
+ TxJabber = (1 << 14),
+ SetupFrame = (1 << 27),
+ TxSwInt = (1 << 31),
+
+ /* MacStatus bits */
+ IntrOK = (1 << 16),
+ IntrErr = (1 << 15),
+ RxIntr = (1 << 6),
+ RxEmpty = (1 << 7),
+ TxIntr = (1 << 0),
+ TxEmpty = (1 << 2),
+ PciErr = (1 << 13),
+ TxState = (1 << 22) | (1 << 21) | (1 << 20),
+ RxState = (1 << 19) | (1 << 18) | (1 << 17),
+ LinkFail = (1 << 12),
+ LinkPass = (1 << 4),
+ RxStopped = (1 << 8),
+ TxStopped = (1 << 1),
+
+ /* MacMode bits */
+ TxEnable = (1 << 13),
+ RxEnable = (1 << 1),
+ RxTx = TxEnable | RxEnable,
+ FullDuplex = (1 << 9),
+ AcceptAllMulticast = (1 << 7),
+ AcceptAllPhys = (1 << 6),
+ BOCnt = (1 << 5),
+ MacModeClear = (1<<12) | (1<<11) | (1<<10) | (1<<8) | (1<<3) |
+ RxTx | BOCnt | AcceptAllPhys | AcceptAllMulticast,
+
+ /* ROMCmd bits */
+ EE_SHIFT_CLK = 0x02, /* EEPROM shift clock. */
+ EE_CS = 0x01, /* EEPROM chip select. */
+ EE_DATA_WRITE = 0x04, /* Data from the Tulip to EEPROM. */
+ EE_WRITE_0 = 0x01,
+ EE_WRITE_1 = 0x05,
+ EE_DATA_READ = 0x08, /* Data from the EEPROM chip. */
+ EE_ENB = (0x4800 | EE_CS),
+
+ /* The EEPROM commands include the alway-set leading bit. */
+ EE_READ_CMD = 6,
+
+ /* RxMissed bits */
+ RxMissedOver = (1 << 16),
+ RxMissedMask = 0xffff,
+
+ /* SROM-related bits */
+ SROMC0InfoLeaf = 27,
+ MediaBlockMask = 0x3f,
+ MediaCustomCSRs = (1 << 6),
+
+ /* PCIPM bits */
+ PM_Sleep = (1 << 31),
+ PM_Snooze = (1 << 30),
+ PM_Mask = PM_Sleep | PM_Snooze,
+
+ /* SIAStatus bits */
+ NWayState = (1 << 14) | (1 << 13) | (1 << 12),
+ NWayRestart = (1 << 12),
+ NonselPortActive = (1 << 9),
+ SelPortActive = (1 << 8),
+ LinkFailStatus = (1 << 2),
+ NetCxnErr = (1 << 1),
+};
+
+static const u32 de_intr_mask =
+ IntrOK | IntrErr | RxIntr | RxEmpty | TxIntr | TxEmpty |
+ LinkPass | LinkFail | PciErr;
+
+/*
+ * Set the programmable burst length to 4 longwords for all:
+ * DMA errors result without these values. Cache align 16 long.
+ */
+static const u32 de_bus_mode = CacheAlign16 | BurstLen4 | DescSkipLen;
+
+struct de_srom_media_block {
+ u8 opts;
+ u16 csr13;
+ u16 csr14;
+ u16 csr15;
+} __packed;
+
+struct de_srom_info_leaf {
+ u16 default_media;
+ u8 n_blocks;
+ u8 unused;
+} __packed;
+
+struct de_desc {
+ __le32 opts1;
+ __le32 opts2;
+ __le32 addr1;
+ __le32 addr2;
+#if DSL
+ __le32 skip[DSL];
+#endif
+};
+
+struct media_info {
+ u16 type; /* DE_MEDIA_xxx */
+ u16 csr13;
+ u16 csr14;
+ u16 csr15;
+};
+
+struct ring_info {
+ struct sk_buff *skb;
+ dma_addr_t mapping;
+};
+
+struct de_private {
+ unsigned tx_head;
+ unsigned tx_tail;
+ unsigned rx_tail;
+
+ void __iomem *regs;
+ struct net_device *dev;
+ spinlock_t lock;
+
+ struct de_desc *rx_ring;
+ struct de_desc *tx_ring;
+ struct ring_info tx_skb[DE_TX_RING_SIZE];
+ struct ring_info rx_skb[DE_RX_RING_SIZE];
+ unsigned rx_buf_sz;
+ dma_addr_t ring_dma;
+
+ u32 msg_enable;
+
+ struct pci_dev *pdev;
+
+ u16 setup_frame[DE_SETUP_FRAME_WORDS];
+
+ u32 media_type;
+ u32 media_supported;
+ u32 media_advertise;
+ struct media_info media[DE_MAX_MEDIA];
+ struct timer_list media_timer;
+
+ u8 *ee_data;
+ unsigned board_idx;
+ unsigned de21040 : 1;
+ unsigned media_lock : 1;
+};
+
+
+static void de_set_rx_mode (struct net_device *dev);
+static void de_tx (struct de_private *de);
+static void de_clean_rings (struct de_private *de);
+static void de_media_interrupt (struct de_private *de, u32 status);
+static void de21040_media_timer (struct timer_list *t);
+static void de21041_media_timer (struct timer_list *t);
+static unsigned int de_ok_to_advertise (struct de_private *de, u32 new_media);
+
+
+static const struct pci_device_id de_pci_tbl[] = {
+ { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
+ { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
+ { },
+};
+MODULE_DEVICE_TABLE(pci, de_pci_tbl);
+
+static const char * const media_name[DE_MAX_MEDIA] = {
+ "10baseT auto",
+ "BNC",
+ "AUI",
+ "10baseT-HD",
+ "10baseT-FD"
+};
+
+/* 21040 transceiver register settings:
+ * TP AUTO(unused), BNC(unused), AUI, TP, TP FD*/
+static u16 t21040_csr13[] = { 0, 0, 0x8F09, 0x8F01, 0x8F01, };
+static u16 t21040_csr14[] = { 0, 0, 0x0705, 0xFFFF, 0xFFFD, };
+static u16 t21040_csr15[] = { 0, 0, 0x0006, 0x0000, 0x0000, };
+
+/* 21041 transceiver register settings: TP AUTO, BNC, AUI, TP, TP FD*/
+static u16 t21041_csr13[] = { 0xEF01, 0xEF09, 0xEF09, 0xEF01, 0xEF09, };
+static u16 t21041_csr14[] = { 0xFFFF, 0xF7FD, 0xF7FD, 0x7F3F, 0x7F3D, };
+/* If on-chip autonegotiation is broken, use half-duplex (FF3F) instead */
+static u16 t21041_csr14_brk[] = { 0xFF3F, 0xF7FD, 0xF7FD, 0x7F3F, 0x7F3D, };
+static u16 t21041_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
+
+
+#define dr32(reg) ioread32(de->regs + (reg))
+#define dw32(reg, val) iowrite32((val), de->regs + (reg))
+
+
+static void de_rx_err_acct (struct de_private *de, unsigned rx_tail,
+ u32 status, u32 len)
+{
+ netif_dbg(de, rx_err, de->dev,
+ "rx err, slot %d status 0x%x len %d\n",
+ rx_tail, status, len);
+
+ if ((status & 0x38000300) != 0x0300) {
+ /* Ingore earlier buffers. */
+ if ((status & 0xffff) != 0x7fff) {
+ netif_warn(de, rx_err, de->dev,
+ "Oversized Ethernet frame spanned multiple buffers, status %08x!\n",
+ status);
+ de->dev->stats.rx_length_errors++;
+ }
+ } else if (status & RxError) {
+ /* There was a fatal error. */
+ de->dev->stats.rx_errors++; /* end of a packet.*/
+ if (status & 0x0890) de->dev->stats.rx_length_errors++;
+ if (status & RxErrCRC) de->dev->stats.rx_crc_errors++;
+ if (status & RxErrFIFO) de->dev->stats.rx_fifo_errors++;
+ }
+}
+
+static void de_rx (struct de_private *de)
+{
+ unsigned rx_tail = de->rx_tail;
+ unsigned rx_work = DE_RX_RING_SIZE;
+ unsigned drop = 0;
+ int rc;
+
+ while (--rx_work) {
+ u32 status, len;
+ dma_addr_t mapping;
+ struct sk_buff *skb, *copy_skb;
+ unsigned copying_skb, buflen;
+
+ skb = de->rx_skb[rx_tail].skb;
+ BUG_ON(!skb);
+ rmb();
+ status = le32_to_cpu(de->rx_ring[rx_tail].opts1);
+ if (status & DescOwn)
+ break;
+
+ /* the length is actually a 15 bit value here according
+ * to Table 4-1 in the DE2104x spec so mask is 0x7fff
+ */
+ len = ((status >> 16) & 0x7fff) - 4;
+ mapping = de->rx_skb[rx_tail].mapping;
+
+ if (unlikely(drop)) {
+ de->dev->stats.rx_dropped++;
+ goto rx_next;
+ }
+
+ if (unlikely((status & 0x38008300) != 0x0300)) {
+ de_rx_err_acct(de, rx_tail, status, len);
+ goto rx_next;
+ }
+
+ copying_skb = (len <= rx_copybreak);
+
+ netif_dbg(de, rx_status, de->dev,
+ "rx slot %d status 0x%x len %d copying? %d\n",
+ rx_tail, status, len, copying_skb);
+
+ buflen = copying_skb ? (len + RX_OFFSET) : de->rx_buf_sz;
+ copy_skb = netdev_alloc_skb(de->dev, buflen);
+ if (unlikely(!copy_skb)) {
+ de->dev->stats.rx_dropped++;
+ drop = 1;
+ rx_work = 100;
+ goto rx_next;
+ }
+
+ if (!copying_skb) {
+ dma_unmap_single(&de->pdev->dev, mapping, buflen,
+ DMA_FROM_DEVICE);
+ skb_put(skb, len);
+
+ mapping =
+ de->rx_skb[rx_tail].mapping =
+ dma_map_single(&de->pdev->dev, copy_skb->data,
+ buflen, DMA_FROM_DEVICE);
+ de->rx_skb[rx_tail].skb = copy_skb;
+ } else {
+ dma_sync_single_for_cpu(&de->pdev->dev, mapping, len,
+ DMA_FROM_DEVICE);
+ skb_reserve(copy_skb, RX_OFFSET);
+ skb_copy_from_linear_data(skb, skb_put(copy_skb, len),
+ len);
+ dma_sync_single_for_device(&de->pdev->dev, mapping,
+ len, DMA_FROM_DEVICE);
+
+ /* We'll reuse the original ring buffer. */
+ skb = copy_skb;
+ }
+
+ skb->protocol = eth_type_trans (skb, de->dev);
+
+ de->dev->stats.rx_packets++;
+ de->dev->stats.rx_bytes += skb->len;
+ rc = netif_rx (skb);
+ if (rc == NET_RX_DROP)
+ drop = 1;
+
+rx_next:
+ if (rx_tail == (DE_RX_RING_SIZE - 1))
+ de->rx_ring[rx_tail].opts2 =
+ cpu_to_le32(RingEnd | de->rx_buf_sz);
+ else
+ de->rx_ring[rx_tail].opts2 = cpu_to_le32(de->rx_buf_sz);
+ de->rx_ring[rx_tail].addr1 = cpu_to_le32(mapping);
+ wmb();
+ de->rx_ring[rx_tail].opts1 = cpu_to_le32(DescOwn);
+ rx_tail = NEXT_RX(rx_tail);
+ }
+
+ if (!rx_work)
+ netdev_warn(de->dev, "rx work limit reached\n");
+
+ de->rx_tail = rx_tail;
+}
+
+static irqreturn_t de_interrupt (int irq, void *dev_instance)
+{
+ struct net_device *dev = dev_instance;
+ struct de_private *de = netdev_priv(dev);
+ u32 status;
+
+ status = dr32(MacStatus);
+ if ((!(status & (IntrOK|IntrErr))) || (status == 0xFFFF))
+ return IRQ_NONE;
+
+ netif_dbg(de, intr, dev, "intr, status %08x mode %08x desc %u/%u/%u\n",
+ status, dr32(MacMode),
+ de->rx_tail, de->tx_head, de->tx_tail);
+
+ dw32(MacStatus, status);
+
+ if (status & (RxIntr | RxEmpty)) {
+ de_rx(de);
+ if (status & RxEmpty)
+ dw32(RxPoll, NormalRxPoll);
+ }
+
+ spin_lock(&de->lock);
+
+ if (status & (TxIntr | TxEmpty))
+ de_tx(de);
+
+ if (status & (LinkPass | LinkFail))
+ de_media_interrupt(de, status);
+
+ spin_unlock(&de->lock);
+
+ if (status & PciErr) {
+ u16 pci_status;
+
+ pci_read_config_word(de->pdev, PCI_STATUS, &pci_status);
+ pci_write_config_word(de->pdev, PCI_STATUS, pci_status);
+ netdev_err(de->dev,
+ "PCI bus error, status=%08x, PCI status=%04x\n",
+ status, pci_status);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void de_tx (struct de_private *de)
+{
+ unsigned tx_head = de->tx_head;
+ unsigned tx_tail = de->tx_tail;
+
+ while (tx_tail != tx_head) {
+ struct sk_buff *skb;
+ u32 status;
+
+ rmb();
+ status = le32_to_cpu(de->tx_ring[tx_tail].opts1);
+ if (status & DescOwn)
+ break;
+
+ skb = de->tx_skb[tx_tail].skb;
+ BUG_ON(!skb);
+ if (unlikely(skb == DE_DUMMY_SKB))
+ goto next;
+
+ if (unlikely(skb == DE_SETUP_SKB)) {
+ dma_unmap_single(&de->pdev->dev,
+ de->tx_skb[tx_tail].mapping,
+ sizeof(de->setup_frame),
+ DMA_TO_DEVICE);
+ goto next;
+ }
+
+ dma_unmap_single(&de->pdev->dev, de->tx_skb[tx_tail].mapping,
+ skb->len, DMA_TO_DEVICE);
+
+ if (status & LastFrag) {
+ if (status & TxError) {
+ netif_dbg(de, tx_err, de->dev,
+ "tx err, status 0x%x\n",
+ status);
+ de->dev->stats.tx_errors++;
+ if (status & TxOWC)
+ de->dev->stats.tx_window_errors++;
+ if (status & TxMaxCol)
+ de->dev->stats.tx_aborted_errors++;
+ if (status & TxLinkFail)
+ de->dev->stats.tx_carrier_errors++;
+ if (status & TxFIFOUnder)
+ de->dev->stats.tx_fifo_errors++;
+ } else {
+ de->dev->stats.tx_packets++;
+ de->dev->stats.tx_bytes += skb->len;
+ netif_dbg(de, tx_done, de->dev,
+ "tx done, slot %d\n", tx_tail);
+ }
+ dev_consume_skb_irq(skb);
+ }
+
+next:
+ de->tx_skb[tx_tail].skb = NULL;
+
+ tx_tail = NEXT_TX(tx_tail);
+ }
+
+ de->tx_tail = tx_tail;
+
+ if (netif_queue_stopped(de->dev) && (TX_BUFFS_AVAIL(de) > (DE_TX_RING_SIZE / 4)))
+ netif_wake_queue(de->dev);
+}
+
+static netdev_tx_t de_start_xmit (struct sk_buff *skb,
+ struct net_device *dev)
+{
+ struct de_private *de = netdev_priv(dev);
+ unsigned int entry, tx_free;
+ u32 mapping, len, flags = FirstFrag | LastFrag;
+ struct de_desc *txd;
+
+ spin_lock_irq(&de->lock);
+
+ tx_free = TX_BUFFS_AVAIL(de);
+ if (tx_free == 0) {
+ netif_stop_queue(dev);
+ spin_unlock_irq(&de->lock);
+ return NETDEV_TX_BUSY;
+ }
+ tx_free--;
+
+ entry = de->tx_head;
+
+ txd = &de->tx_ring[entry];
+
+ len = skb->len;
+ mapping = dma_map_single(&de->pdev->dev, skb->data, len,
+ DMA_TO_DEVICE);
+ if (entry == (DE_TX_RING_SIZE - 1))
+ flags |= RingEnd;
+ if (!tx_free || (tx_free == (DE_TX_RING_SIZE / 2)))
+ flags |= TxSwInt;
+ flags |= len;
+ txd->opts2 = cpu_to_le32(flags);
+ txd->addr1 = cpu_to_le32(mapping);
+
+ de->tx_skb[entry].skb = skb;
+ de->tx_skb[entry].mapping = mapping;
+ wmb();
+
+ txd->opts1 = cpu_to_le32(DescOwn);
+ wmb();
+
+ de->tx_head = NEXT_TX(entry);
+ netif_dbg(de, tx_queued, dev, "tx queued, slot %d, skblen %d\n",
+ entry, skb->len);
+
+ if (tx_free == 0)
+ netif_stop_queue(dev);
+
+ spin_unlock_irq(&de->lock);
+
+ /* Trigger an immediate transmit demand. */
+ dw32(TxPoll, NormalTxPoll);
+
+ return NETDEV_TX_OK;
+}
+
+/* Set or clear the multicast filter for this adaptor.
+ Note that we only use exclusion around actually queueing the
+ new frame, not around filling de->setup_frame. This is non-deterministic
+ when re-entered but still correct. */
+
+static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
+{
+ struct de_private *de = netdev_priv(dev);
+ u16 hash_table[32];
+ struct netdev_hw_addr *ha;
+ const u16 *eaddrs;
+ int i;
+
+ memset(hash_table, 0, sizeof(hash_table));
+ __set_bit_le(255, hash_table); /* Broadcast entry */
+ /* This should work on big-endian machines as well. */
+ netdev_for_each_mc_addr(ha, dev) {
+ int index = ether_crc_le(ETH_ALEN, ha->addr) & 0x1ff;
+
+ __set_bit_le(index, hash_table);
+ }
+
+ for (i = 0; i < 32; i++) {
+ *setup_frm++ = hash_table[i];
+ *setup_frm++ = hash_table[i];
+ }
+ setup_frm = &de->setup_frame[13*6];
+
+ /* Fill the final entry with our physical address. */
+ eaddrs = (const u16 *)dev->dev_addr;
+ *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
+ *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
+ *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
+}
+
+static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
+{
+ struct de_private *de = netdev_priv(dev);
+ struct netdev_hw_addr *ha;
+ const u16 *eaddrs;
+
+ /* We have <= 14 addresses so we can use the wonderful
+ 16 address perfect filtering of the Tulip. */
+ netdev_for_each_mc_addr(ha, dev) {
+ eaddrs = (u16 *) ha->addr;
+ *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
+ *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
+ *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
+ }
+ /* Fill the unused entries with the broadcast address. */
+ memset(setup_frm, 0xff, (15 - netdev_mc_count(dev)) * 12);
+ setup_frm = &de->setup_frame[15*6];
+
+ /* Fill the final entry with our physical address. */
+ eaddrs = (const u16 *)dev->dev_addr;
+ *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
+ *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
+ *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
+}
+
+
+static void __de_set_rx_mode (struct net_device *dev)
+{
+ struct de_private *de = netdev_priv(dev);
+ u32 macmode;
+ unsigned int entry;
+ u32 mapping;
+ struct de_desc *txd;
+ struct de_desc *dummy_txd = NULL;
+
+ macmode = dr32(MacMode) & ~(AcceptAllMulticast | AcceptAllPhys);
+
+ if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
+ macmode |= AcceptAllMulticast | AcceptAllPhys;
+ goto out;
+ }
+
+ if ((netdev_mc_count(dev) > 1000) || (dev->flags & IFF_ALLMULTI)) {
+ /* Too many to filter well -- accept all multicasts. */
+ macmode |= AcceptAllMulticast;
+ goto out;
+ }
+
+ /* Note that only the low-address shortword of setup_frame is valid!
+ The values are doubled for big-endian architectures. */
+ if (netdev_mc_count(dev) > 14) /* Must use a multicast hash table. */
+ build_setup_frame_hash (de->setup_frame, dev);
+ else
+ build_setup_frame_perfect (de->setup_frame, dev);
+
+ /*
+ * Now add this frame to the Tx list.
+ */
+
+ entry = de->tx_head;
+
+ /* Avoid a chip errata by prefixing a dummy entry. */
+ if (entry != 0) {
+ de->tx_skb[entry].skb = DE_DUMMY_SKB;
+
+ dummy_txd = &de->tx_ring[entry];
+ dummy_txd->opts2 = (entry == (DE_TX_RING_SIZE - 1)) ?
+ cpu_to_le32(RingEnd) : 0;
+ dummy_txd->addr1 = 0;
+
+ /* Must set DescOwned later to avoid race with chip */
+
+ entry = NEXT_TX(entry);
+ }
+
+ de->tx_skb[entry].skb = DE_SETUP_SKB;
+ de->tx_skb[entry].mapping = mapping =
+ dma_map_single(&de->pdev->dev, de->setup_frame,
+ sizeof(de->setup_frame), DMA_TO_DEVICE);
+
+ /* Put the setup frame on the Tx list. */
+ txd = &de->tx_ring[entry];
+ if (entry == (DE_TX_RING_SIZE - 1))
+ txd->opts2 = cpu_to_le32(SetupFrame | RingEnd | sizeof (de->setup_frame));
+ else
+ txd->opts2 = cpu_to_le32(SetupFrame | sizeof (de->setup_frame));
+ txd->addr1 = cpu_to_le32(mapping);
+ wmb();
+
+ txd->opts1 = cpu_to_le32(DescOwn);
+ wmb();
+
+ if (dummy_txd) {
+ dummy_txd->opts1 = cpu_to_le32(DescOwn);
+ wmb();
+ }
+
+ de->tx_head = NEXT_TX(entry);
+
+ if (TX_BUFFS_AVAIL(de) == 0)
+ netif_stop_queue(dev);
+
+ /* Trigger an immediate transmit demand. */
+ dw32(TxPoll, NormalTxPoll);
+
+out:
+ if (macmode != dr32(MacMode))
+ dw32(MacMode, macmode);
+}
+
+static void de_set_rx_mode (struct net_device *dev)
+{
+ unsigned long flags;
+ struct de_private *de = netdev_priv(dev);
+
+ spin_lock_irqsave (&de->lock, flags);
+ __de_set_rx_mode(dev);
+ spin_unlock_irqrestore (&de->lock, flags);
+}
+
+static inline void de_rx_missed(struct de_private *de, u32 rx_missed)
+{
+ if (unlikely(rx_missed & RxMissedOver))
+ de->dev->stats.rx_missed_errors += RxMissedMask;
+ else
+ de->dev->stats.rx_missed_errors += (rx_missed & RxMissedMask);
+}
+
+static void __de_get_stats(struct de_private *de)
+{
+ u32 tmp = dr32(RxMissed); /* self-clearing */
+
+ de_rx_missed(de, tmp);
+}
+
+static struct net_device_stats *de_get_stats(struct net_device *dev)
+{
+ struct de_private *de = netdev_priv(dev);
+
+ /* The chip only need report frame silently dropped. */
+ spin_lock_irq(&de->lock);
+ if (netif_running(dev) && netif_device_present(dev))
+ __de_get_stats(de);
+ spin_unlock_irq(&de->lock);
+
+ return &dev->stats;
+}
+
+static inline int de_is_running (struct de_private *de)
+{
+ return (dr32(MacStatus) & (RxState | TxState)) ? 1 : 0;
+}
+
+static void de_stop_rxtx (struct de_private *de)
+{
+ u32 macmode;
+ unsigned int i = 1300/100;
+
+ macmode = dr32(MacMode);
+ if (macmode & RxTx) {
+ dw32(MacMode, macmode & ~RxTx);
+ dr32(MacMode);
+ }
+
+ /* wait until in-flight frame completes.
+ * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
+ * Typically expect this loop to end in < 50 us on 100BT.
+ */
+ while (--i) {
+ if (!de_is_running(de))
+ return;
+ udelay(100);
+ }
+
+ netdev_warn(de->dev, "timeout expired, stopping DMA\n");
+}
+
+static inline void de_start_rxtx (struct de_private *de)
+{
+ u32 macmode;
+
+ macmode = dr32(MacMode);
+ if ((macmode & RxTx) != RxTx) {
+ dw32(MacMode, macmode | RxTx);
+ dr32(MacMode);
+ }
+}
+
+static void de_stop_hw (struct de_private *de)
+{
+
+ udelay(5);
+ dw32(IntrMask, 0);
+
+ de_stop_rxtx(de);
+
+ dw32(MacStatus, dr32(MacStatus));
+
+ udelay(10);
+
+ de->rx_tail = 0;
+ de->tx_head = de->tx_tail = 0;
+}
+
+static void de_link_up(struct de_private *de)
+{
+ if (!netif_carrier_ok(de->dev)) {
+ netif_carrier_on(de->dev);
+ netif_info(de, link, de->dev, "link up, media %s\n",
+ media_name[de->media_type]);
+ }
+}
+
+static void de_link_down(struct de_private *de)
+{
+ if (netif_carrier_ok(de->dev)) {
+ netif_carrier_off(de->dev);
+ netif_info(de, link, de->dev, "link down\n");
+ }
+}
+
+static void de_set_media (struct de_private *de)
+{
+ unsigned media = de->media_type;
+ u32 macmode = dr32(MacMode);
+
+ if (de_is_running(de))
+ netdev_warn(de->dev, "chip is running while changing media!\n");
+
+ if (de->de21040)
+ dw32(CSR11, FULL_DUPLEX_MAGIC);
+ dw32(CSR13, 0); /* Reset phy */
+ dw32(CSR14, de->media[media].csr14);
+ dw32(CSR15, de->media[media].csr15);
+ dw32(CSR13, de->media[media].csr13);
+
+ /* must delay 10ms before writing to other registers,
+ * especially CSR6
+ */
+ mdelay(10);
+
+ if (media == DE_MEDIA_TP_FD)
+ macmode |= FullDuplex;
+ else
+ macmode &= ~FullDuplex;
+
+ netif_info(de, link, de->dev, "set link %s\n", media_name[media]);
+ netif_info(de, hw, de->dev, "mode 0x%x, sia 0x%x,0x%x,0x%x,0x%x\n",
+ dr32(MacMode), dr32(SIAStatus),
+ dr32(CSR13), dr32(CSR14), dr32(CSR15));
+ netif_info(de, hw, de->dev, "set mode 0x%x, set sia 0x%x,0x%x,0x%x\n",
+ macmode, de->media[media].csr13,
+ de->media[media].csr14, de->media[media].csr15);
+ if (macmode != dr32(MacMode))
+ dw32(MacMode, macmode);
+}
+
+static void de_next_media (struct de_private *de, const u32 *media,
+ unsigned int n_media)
+{
+ unsigned int i;
+
+ for (i = 0; i < n_media; i++) {
+ if (de_ok_to_advertise(de, media[i])) {
+ de->media_type = media[i];
+ return;
+ }
+ }
+}
+
+static void de21040_media_timer (struct timer_list *t)
+{
+ struct de_private *de = from_timer(de, t, media_timer);
+ struct net_device *dev = de->dev;
+ u32 status = dr32(SIAStatus);
+ unsigned int carrier;
+ unsigned long flags;
+
+ carrier = (status & NetCxnErr) ? 0 : 1;
+
+ if (carrier) {
+ if (de->media_type != DE_MEDIA_AUI && (status & LinkFailStatus))
+ goto no_link_yet;
+
+ de->media_timer.expires = jiffies + DE_TIMER_LINK;
+ add_timer(&de->media_timer);
+ if (!netif_carrier_ok(dev))
+ de_link_up(de);
+ else
+ netif_info(de, timer, dev, "%s link ok, status %x\n",
+ media_name[de->media_type], status);
+ return;
+ }
+
+ de_link_down(de);
+
+ if (de->media_lock)
+ return;
+
+ if (de->media_type == DE_MEDIA_AUI) {
+ static const u32 next_state = DE_MEDIA_TP;
+ de_next_media(de, &next_state, 1);
+ } else {
+ static const u32 next_state = DE_MEDIA_AUI;
+ de_next_media(de, &next_state, 1);
+ }
+
+ spin_lock_irqsave(&de->lock, flags);
+ de_stop_rxtx(de);
+ spin_unlock_irqrestore(&de->lock, flags);
+ de_set_media(de);
+ de_start_rxtx(de);
+
+no_link_yet:
+ de->media_timer.expires = jiffies + DE_TIMER_NO_LINK;
+ add_timer(&de->media_timer);
+
+ netif_info(de, timer, dev, "no link, trying media %s, status %x\n",
+ media_name[de->media_type], status);
+}
+
+static unsigned int de_ok_to_advertise (struct de_private *de, u32 new_media)
+{
+ switch (new_media) {
+ case DE_MEDIA_TP_AUTO:
+ if (!(de->media_advertise & ADVERTISED_Autoneg))
+ return 0;
+ if (!(de->media_advertise & (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full)))
+ return 0;
+ break;
+ case DE_MEDIA_BNC:
+ if (!(de->media_advertise & ADVERTISED_BNC))
+ return 0;
+ break;
+ case DE_MEDIA_AUI:
+ if (!(de->media_advertise & ADVERTISED_AUI))
+ return 0;
+ break;
+ case DE_MEDIA_TP:
+ if (!(de->media_advertise & ADVERTISED_10baseT_Half))
+ return 0;
+ break;
+ case DE_MEDIA_TP_FD:
+ if (!(de->media_advertise & ADVERTISED_10baseT_Full))
+ return 0;
+ break;
+ }
+
+ return 1;
+}
+
+static void de21041_media_timer (struct timer_list *t)
+{
+ struct de_private *de = from_timer(de, t, media_timer);
+ struct net_device *dev = de->dev;
+ u32 status = dr32(SIAStatus);
+ unsigned int carrier;
+ unsigned long flags;
+
+ /* clear port active bits */
+ dw32(SIAStatus, NonselPortActive | SelPortActive);
+
+ carrier = (status & NetCxnErr) ? 0 : 1;
+
+ if (carrier) {
+ if ((de->media_type == DE_MEDIA_TP_AUTO ||
+ de->media_type == DE_MEDIA_TP ||
+ de->media_type == DE_MEDIA_TP_FD) &&
+ (status & LinkFailStatus))
+ goto no_link_yet;
+
+ de->media_timer.expires = jiffies + DE_TIMER_LINK;
+ add_timer(&de->media_timer);
+ if (!netif_carrier_ok(dev))
+ de_link_up(de);
+ else
+ netif_info(de, timer, dev,
+ "%s link ok, mode %x status %x\n",
+ media_name[de->media_type],
+ dr32(MacMode), status);
+ return;
+ }
+
+ de_link_down(de);
+
+ /* if media type locked, don't switch media */
+ if (de->media_lock)
+ goto set_media;
+
+ /* if activity detected, use that as hint for new media type */
+ if (status & NonselPortActive) {
+ unsigned int have_media = 1;
+
+ /* if AUI/BNC selected, then activity is on TP port */
+ if (de->media_type == DE_MEDIA_AUI ||
+ de->media_type == DE_MEDIA_BNC) {
+ if (de_ok_to_advertise(de, DE_MEDIA_TP_AUTO))
+ de->media_type = DE_MEDIA_TP_AUTO;
+ else
+ have_media = 0;
+ }
+
+ /* TP selected. If there is only TP and BNC, then it's BNC */
+ else if (((de->media_supported & DE_AUI_BNC) == SUPPORTED_BNC) &&
+ de_ok_to_advertise(de, DE_MEDIA_BNC))
+ de->media_type = DE_MEDIA_BNC;
+
+ /* TP selected. If there is only TP and AUI, then it's AUI */
+ else if (((de->media_supported & DE_AUI_BNC) == SUPPORTED_AUI) &&
+ de_ok_to_advertise(de, DE_MEDIA_AUI))
+ de->media_type = DE_MEDIA_AUI;
+
+ /* otherwise, ignore the hint */
+ else
+ have_media = 0;
+
+ if (have_media)
+ goto set_media;
+ }
+
+ /*
+ * Absent or ambiguous activity hint, move to next advertised
+ * media state. If de->media_type is left unchanged, this
+ * simply resets the PHY and reloads the current media settings.
+ */
+ if (de->media_type == DE_MEDIA_AUI) {
+ static const u32 next_states[] = {
+ DE_MEDIA_BNC, DE_MEDIA_TP_AUTO
+ };
+ de_next_media(de, next_states, ARRAY_SIZE(next_states));
+ } else if (de->media_type == DE_MEDIA_BNC) {
+ static const u32 next_states[] = {
+ DE_MEDIA_TP_AUTO, DE_MEDIA_AUI
+ };
+ de_next_media(de, next_states, ARRAY_SIZE(next_states));
+ } else {
+ static const u32 next_states[] = {
+ DE_MEDIA_AUI, DE_MEDIA_BNC, DE_MEDIA_TP_AUTO
+ };
+ de_next_media(de, next_states, ARRAY_SIZE(next_states));
+ }
+
+set_media:
+ spin_lock_irqsave(&de->lock, flags);
+ de_stop_rxtx(de);
+ spin_unlock_irqrestore(&de->lock, flags);
+ de_set_media(de);
+ de_start_rxtx(de);
+
+no_link_yet:
+ de->media_timer.expires = jiffies + DE_TIMER_NO_LINK;
+ add_timer(&de->media_timer);
+
+ netif_info(de, timer, dev, "no link, trying media %s, status %x\n",
+ media_name[de->media_type], status);
+}
+
+static void de_media_interrupt (struct de_private *de, u32 status)
+{
+ if (status & LinkPass) {
+ /* Ignore if current media is AUI or BNC and we can't use TP */
+ if ((de->media_type == DE_MEDIA_AUI ||
+ de->media_type == DE_MEDIA_BNC) &&
+ (de->media_lock ||
+ !de_ok_to_advertise(de, DE_MEDIA_TP_AUTO)))
+ return;
+ /* If current media is not TP, change it to TP */
+ if ((de->media_type == DE_MEDIA_AUI ||
+ de->media_type == DE_MEDIA_BNC)) {
+ de->media_type = DE_MEDIA_TP_AUTO;
+ de_stop_rxtx(de);
+ de_set_media(de);
+ de_start_rxtx(de);
+ }
+ de_link_up(de);
+ mod_timer(&de->media_timer, jiffies + DE_TIMER_LINK);
+ return;
+ }
+
+ BUG_ON(!(status & LinkFail));
+ /* Mark the link as down only if current media is TP */
+ if (netif_carrier_ok(de->dev) && de->media_type != DE_MEDIA_AUI &&
+ de->media_type != DE_MEDIA_BNC) {
+ de_link_down(de);
+ mod_timer(&de->media_timer, jiffies + DE_TIMER_NO_LINK);
+ }
+}
+
+static int de_reset_mac (struct de_private *de)
+{
+ u32 status, tmp;
+
+ /*
+ * Reset MAC. de4x5.c and tulip.c examined for "advice"
+ * in this area.
+ */
+
+ if (dr32(BusMode) == 0xffffffff)
+ return -EBUSY;
+
+ /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
+ dw32 (BusMode, CmdReset);
+ mdelay (1);
+
+ dw32 (BusMode, de_bus_mode);
+ mdelay (1);
+
+ for (tmp = 0; tmp < 5; tmp++) {
+ dr32 (BusMode);
+ mdelay (1);
+ }
+
+ mdelay (1);
+
+ status = dr32(MacStatus);
+ if (status & (RxState | TxState))
+ return -EBUSY;
+ if (status == 0xffffffff)
+ return -ENODEV;
+ return 0;
+}
+
+static void de_adapter_wake (struct de_private *de)
+{
+ u32 pmctl;
+
+ if (de->de21040)
+ return;
+
+ pci_read_config_dword(de->pdev, PCIPM, &pmctl);
+ if (pmctl & PM_Mask) {
+ pmctl &= ~PM_Mask;
+ pci_write_config_dword(de->pdev, PCIPM, pmctl);
+
+ /* de4x5.c delays, so we do too */
+ msleep(10);
+ }
+}
+
+static void de_adapter_sleep (struct de_private *de)
+{
+ u32 pmctl;
+
+ if (de->de21040)
+ return;
+
+ dw32(CSR13, 0); /* Reset phy */
+ pci_read_config_dword(de->pdev, PCIPM, &pmctl);
+ pmctl |= PM_Sleep;
+ pci_write_config_dword(de->pdev, PCIPM, pmctl);
+}
+
+static int de_init_hw (struct de_private *de)
+{
+ struct net_device *dev = de->dev;
+ u32 macmode;
+ int rc;
+
+ de_adapter_wake(de);
+
+ macmode = dr32(MacMode) & ~MacModeClear;
+
+ rc = de_reset_mac(de);
+ if (rc)
+ return rc;
+
+ de_set_media(de); /* reset phy */
+
+ dw32(RxRingAddr, de->ring_dma);
+ dw32(TxRingAddr, de->ring_dma + (sizeof(struct de_desc) * DE_RX_RING_SIZE));
+
+ dw32(MacMode, RxTx | macmode);
+
+ dr32(RxMissed); /* self-clearing */
+
+ dw32(IntrMask, de_intr_mask);
+
+ de_set_rx_mode(dev);
+
+ return 0;
+}
+
+static int de_refill_rx (struct de_private *de)
+{
+ unsigned i;
+
+ for (i = 0; i < DE_RX_RING_SIZE; i++) {
+ struct sk_buff *skb;
+
+ skb = netdev_alloc_skb(de->dev, de->rx_buf_sz);
+ if (!skb)
+ goto err_out;
+
+ de->rx_skb[i].mapping = dma_map_single(&de->pdev->dev,
+ skb->data,
+ de->rx_buf_sz,
+ DMA_FROM_DEVICE);
+ de->rx_skb[i].skb = skb;
+
+ de->rx_ring[i].opts1 = cpu_to_le32(DescOwn);
+ if (i == (DE_RX_RING_SIZE - 1))
+ de->rx_ring[i].opts2 =
+ cpu_to_le32(RingEnd | de->rx_buf_sz);
+ else
+ de->rx_ring[i].opts2 = cpu_to_le32(de->rx_buf_sz);
+ de->rx_ring[i].addr1 = cpu_to_le32(de->rx_skb[i].mapping);
+ de->rx_ring[i].addr2 = 0;
+ }
+
+ return 0;
+
+err_out:
+ de_clean_rings(de);
+ return -ENOMEM;
+}
+
+static int de_init_rings (struct de_private *de)
+{
+ memset(de->tx_ring, 0, sizeof(struct de_desc) * DE_TX_RING_SIZE);
+ de->tx_ring[DE_TX_RING_SIZE - 1].opts2 = cpu_to_le32(RingEnd);
+
+ de->rx_tail = 0;
+ de->tx_head = de->tx_tail = 0;
+
+ return de_refill_rx (de);
+}
+
+static int de_alloc_rings (struct de_private *de)
+{
+ de->rx_ring = dma_alloc_coherent(&de->pdev->dev, DE_RING_BYTES,
+ &de->ring_dma, GFP_KERNEL);
+ if (!de->rx_ring)
+ return -ENOMEM;
+ de->tx_ring = &de->rx_ring[DE_RX_RING_SIZE];
+ return de_init_rings(de);
+}
+
+static void de_clean_rings (struct de_private *de)
+{
+ unsigned i;
+
+ memset(de->rx_ring, 0, sizeof(struct de_desc) * DE_RX_RING_SIZE);
+ de->rx_ring[DE_RX_RING_SIZE - 1].opts2 = cpu_to_le32(RingEnd);
+ wmb();
+ memset(de->tx_ring, 0, sizeof(struct de_desc) * DE_TX_RING_SIZE);
+ de->tx_ring[DE_TX_RING_SIZE - 1].opts2 = cpu_to_le32(RingEnd);
+ wmb();
+
+ for (i = 0; i < DE_RX_RING_SIZE; i++) {
+ if (de->rx_skb[i].skb) {
+ dma_unmap_single(&de->pdev->dev,
+ de->rx_skb[i].mapping, de->rx_buf_sz,
+ DMA_FROM_DEVICE);
+ dev_kfree_skb(de->rx_skb[i].skb);
+ }
+ }
+
+ for (i = 0; i < DE_TX_RING_SIZE; i++) {
+ struct sk_buff *skb = de->tx_skb[i].skb;
+ if ((skb) && (skb != DE_DUMMY_SKB)) {
+ if (skb != DE_SETUP_SKB) {
+ de->dev->stats.tx_dropped++;
+ dma_unmap_single(&de->pdev->dev,
+ de->tx_skb[i].mapping,
+ skb->len, DMA_TO_DEVICE);
+ dev_kfree_skb(skb);
+ } else {
+ dma_unmap_single(&de->pdev->dev,
+ de->tx_skb[i].mapping,
+ sizeof(de->setup_frame),
+ DMA_TO_DEVICE);
+ }
+ }
+ }
+
+ memset(&de->rx_skb, 0, sizeof(struct ring_info) * DE_RX_RING_SIZE);
+ memset(&de->tx_skb, 0, sizeof(struct ring_info) * DE_TX_RING_SIZE);
+}
+
+static void de_free_rings (struct de_private *de)
+{
+ de_clean_rings(de);
+ dma_free_coherent(&de->pdev->dev, DE_RING_BYTES, de->rx_ring,
+ de->ring_dma);
+ de->rx_ring = NULL;
+ de->tx_ring = NULL;
+}
+
+static int de_open (struct net_device *dev)
+{
+ struct de_private *de = netdev_priv(dev);
+ const int irq = de->pdev->irq;
+ int rc;
+
+ netif_dbg(de, ifup, dev, "enabling interface\n");
+
+ de->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
+
+ rc = de_alloc_rings(de);
+ if (rc) {
+ netdev_err(dev, "ring allocation failure, err=%d\n", rc);
+ return rc;
+ }
+
+ dw32(IntrMask, 0);
+
+ rc = request_irq(irq, de_interrupt, IRQF_SHARED, dev->name, dev);
+ if (rc) {
+ netdev_err(dev, "IRQ %d request failure, err=%d\n", irq, rc);
+ goto err_out_free;
+ }
+
+ rc = de_init_hw(de);
+ if (rc) {
+ netdev_err(dev, "h/w init failure, err=%d\n", rc);
+ goto err_out_free_irq;
+ }
+
+ netif_start_queue(dev);
+ mod_timer(&de->media_timer, jiffies + DE_TIMER_NO_LINK);
+
+ return 0;
+
+err_out_free_irq:
+ free_irq(irq, dev);
+err_out_free:
+ de_free_rings(de);
+ return rc;
+}
+
+static int de_close (struct net_device *dev)
+{
+ struct de_private *de = netdev_priv(dev);
+ unsigned long flags;
+
+ netif_dbg(de, ifdown, dev, "disabling interface\n");
+
+ del_timer_sync(&de->media_timer);
+
+ spin_lock_irqsave(&de->lock, flags);
+ de_stop_hw(de);
+ netif_stop_queue(dev);
+ netif_carrier_off(dev);
+ spin_unlock_irqrestore(&de->lock, flags);
+
+ free_irq(de->pdev->irq, dev);
+
+ de_free_rings(de);
+ de_adapter_sleep(de);
+ return 0;
+}
+
+static void de_tx_timeout (struct net_device *dev, unsigned int txqueue)
+{
+ struct de_private *de = netdev_priv(dev);
+ const int irq = de->pdev->irq;
+
+ netdev_dbg(dev, "NIC status %08x mode %08x sia %08x desc %u/%u/%u\n",
+ dr32(MacStatus), dr32(MacMode), dr32(SIAStatus),
+ de->rx_tail, de->tx_head, de->tx_tail);
+
+ del_timer_sync(&de->media_timer);
+
+ disable_irq(irq);
+ spin_lock_irq(&de->lock);
+
+ de_stop_hw(de);
+ netif_stop_queue(dev);
+ netif_carrier_off(dev);
+
+ spin_unlock_irq(&de->lock);
+ enable_irq(irq);
+
+ /* Update the error counts. */
+ __de_get_stats(de);
+
+ synchronize_irq(irq);
+ de_clean_rings(de);
+
+ de_init_rings(de);
+
+ de_init_hw(de);
+
+ netif_wake_queue(dev);
+}
+
+static void __de_get_regs(struct de_private *de, u8 *buf)
+{
+ int i;
+ u32 *rbuf = (u32 *)buf;
+
+ /* read all CSRs */
+ for (i = 0; i < DE_NUM_REGS; i++)
+ rbuf[i] = dr32(i * 8);
+
+ /* handle self-clearing RxMissed counter, CSR8 */
+ de_rx_missed(de, rbuf[8]);
+}
+
+static void __de_get_link_ksettings(struct de_private *de,
+ struct ethtool_link_ksettings *cmd)
+{
+ ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
+ de->media_supported);
+ cmd->base.phy_address = 0;
+ ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
+ de->media_advertise);
+
+ switch (de->media_type) {
+ case DE_MEDIA_AUI:
+ cmd->base.port = PORT_AUI;
+ break;
+ case DE_MEDIA_BNC:
+ cmd->base.port = PORT_BNC;
+ break;
+ default:
+ cmd->base.port = PORT_TP;
+ break;
+ }
+
+ cmd->base.speed = 10;
+
+ if (dr32(MacMode) & FullDuplex)
+ cmd->base.duplex = DUPLEX_FULL;
+ else
+ cmd->base.duplex = DUPLEX_HALF;
+
+ if (de->media_lock)
+ cmd->base.autoneg = AUTONEG_DISABLE;
+ else
+ cmd->base.autoneg = AUTONEG_ENABLE;
+
+ /* ignore maxtxpkt, maxrxpkt for now */
+}
+
+static int __de_set_link_ksettings(struct de_private *de,
+ const struct ethtool_link_ksettings *cmd)
+{
+ u32 new_media;
+ unsigned int media_lock;
+ u8 duplex = cmd->base.duplex;
+ u8 port = cmd->base.port;
+ u8 autoneg = cmd->base.autoneg;
+ u32 advertising;
+
+ ethtool_convert_link_mode_to_legacy_u32(&advertising,
+ cmd->link_modes.advertising);
+
+ if (cmd->base.speed != 10)
+ return -EINVAL;
+ if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
+ return -EINVAL;
+ if (port != PORT_TP && port != PORT_AUI && port != PORT_BNC)
+ return -EINVAL;
+ if (de->de21040 && port == PORT_BNC)
+ return -EINVAL;
+ if (autoneg != AUTONEG_DISABLE && autoneg != AUTONEG_ENABLE)
+ return -EINVAL;
+ if (advertising & ~de->media_supported)
+ return -EINVAL;
+ if (autoneg == AUTONEG_ENABLE &&
+ (!(advertising & ADVERTISED_Autoneg)))
+ return -EINVAL;
+
+ switch (port) {
+ case PORT_AUI:
+ new_media = DE_MEDIA_AUI;
+ if (!(advertising & ADVERTISED_AUI))
+ return -EINVAL;
+ break;
+ case PORT_BNC:
+ new_media = DE_MEDIA_BNC;
+ if (!(advertising & ADVERTISED_BNC))
+ return -EINVAL;
+ break;
+ default:
+ if (autoneg == AUTONEG_ENABLE)
+ new_media = DE_MEDIA_TP_AUTO;
+ else if (duplex == DUPLEX_FULL)
+ new_media = DE_MEDIA_TP_FD;
+ else
+ new_media = DE_MEDIA_TP;
+ if (!(advertising & ADVERTISED_TP))
+ return -EINVAL;
+ if (!(advertising & (ADVERTISED_10baseT_Full |
+ ADVERTISED_10baseT_Half)))
+ return -EINVAL;
+ break;
+ }
+
+ media_lock = (autoneg == AUTONEG_ENABLE) ? 0 : 1;
+
+ if ((new_media == de->media_type) &&
+ (media_lock == de->media_lock) &&
+ (advertising == de->media_advertise))
+ return 0; /* nothing to change */
+
+ de_link_down(de);
+ mod_timer(&de->media_timer, jiffies + DE_TIMER_NO_LINK);
+ de_stop_rxtx(de);
+
+ de->media_type = new_media;
+ de->media_lock = media_lock;
+ de->media_advertise = advertising;
+ de_set_media(de);
+ if (netif_running(de->dev))
+ de_start_rxtx(de);
+
+ return 0;
+}
+
+static void de_get_drvinfo (struct net_device *dev,struct ethtool_drvinfo *info)
+{
+ struct de_private *de = netdev_priv(dev);
+
+ strscpy(info->driver, DRV_NAME, sizeof(info->driver));
+ strscpy(info->bus_info, pci_name(de->pdev), sizeof(info->bus_info));
+}
+
+static int de_get_regs_len(struct net_device *dev)
+{
+ return DE_REGS_SIZE;
+}
+
+static int de_get_link_ksettings(struct net_device *dev,
+ struct ethtool_link_ksettings *cmd)
+{
+ struct de_private *de = netdev_priv(dev);
+
+ spin_lock_irq(&de->lock);
+ __de_get_link_ksettings(de, cmd);
+ spin_unlock_irq(&de->lock);
+
+ return 0;
+}
+
+static int de_set_link_ksettings(struct net_device *dev,
+ const struct ethtool_link_ksettings *cmd)
+{
+ struct de_private *de = netdev_priv(dev);
+ int rc;
+
+ spin_lock_irq(&de->lock);
+ rc = __de_set_link_ksettings(de, cmd);
+ spin_unlock_irq(&de->lock);
+
+ return rc;
+}
+
+static u32 de_get_msglevel(struct net_device *dev)
+{
+ struct de_private *de = netdev_priv(dev);
+
+ return de->msg_enable;
+}
+
+static void de_set_msglevel(struct net_device *dev, u32 msglvl)
+{
+ struct de_private *de = netdev_priv(dev);
+
+ de->msg_enable = msglvl;
+}
+
+static int de_get_eeprom(struct net_device *dev,
+ struct ethtool_eeprom *eeprom, u8 *data)
+{
+ struct de_private *de = netdev_priv(dev);
+
+ if (!de->ee_data)
+ return -EOPNOTSUPP;
+ if ((eeprom->offset != 0) || (eeprom->magic != 0) ||
+ (eeprom->len != DE_EEPROM_SIZE))
+ return -EINVAL;
+ memcpy(data, de->ee_data, eeprom->len);
+
+ return 0;
+}
+
+static int de_nway_reset(struct net_device *dev)
+{
+ struct de_private *de = netdev_priv(dev);
+ u32 status;
+
+ if (de->media_type != DE_MEDIA_TP_AUTO)
+ return -EINVAL;
+ if (netif_carrier_ok(de->dev))
+ de_link_down(de);
+
+ status = dr32(SIAStatus);
+ dw32(SIAStatus, (status & ~NWayState) | NWayRestart);
+ netif_info(de, link, dev, "link nway restart, status %x,%x\n",
+ status, dr32(SIAStatus));
+ return 0;
+}
+
+static void de_get_regs(struct net_device *dev, struct ethtool_regs *regs,
+ void *data)
+{
+ struct de_private *de = netdev_priv(dev);
+
+ regs->version = (DE_REGS_VER << 2) | de->de21040;
+
+ spin_lock_irq(&de->lock);
+ __de_get_regs(de, data);
+ spin_unlock_irq(&de->lock);
+}
+
+static const struct ethtool_ops de_ethtool_ops = {
+ .get_link = ethtool_op_get_link,
+ .get_drvinfo = de_get_drvinfo,
+ .get_regs_len = de_get_regs_len,
+ .get_msglevel = de_get_msglevel,
+ .set_msglevel = de_set_msglevel,
+ .get_eeprom = de_get_eeprom,
+ .nway_reset = de_nway_reset,
+ .get_regs = de_get_regs,
+ .get_link_ksettings = de_get_link_ksettings,
+ .set_link_ksettings = de_set_link_ksettings,
+};
+
+static void de21040_get_mac_address(struct de_private *de)
+{
+ u8 addr[ETH_ALEN];
+ unsigned i;
+
+ dw32 (ROMCmd, 0); /* Reset the pointer with a dummy write. */
+ udelay(5);
+
+ for (i = 0; i < 6; i++) {
+ int value, boguscnt = 100000;
+ do {
+ value = dr32(ROMCmd);
+ rmb();
+ } while (value < 0 && --boguscnt > 0);
+ addr[i] = value;
+ udelay(1);
+ if (boguscnt <= 0)
+ pr_warn("timeout reading 21040 MAC address byte %u\n",
+ i);
+ }
+ eth_hw_addr_set(de->dev, addr);
+}
+
+static void de21040_get_media_info(struct de_private *de)
+{
+ unsigned int i;
+
+ de->media_type = DE_MEDIA_TP;
+ de->media_supported |= SUPPORTED_TP | SUPPORTED_10baseT_Full |
+ SUPPORTED_10baseT_Half | SUPPORTED_AUI;
+ de->media_advertise = de->media_supported;
+
+ for (i = 0; i < DE_MAX_MEDIA; i++) {
+ switch (i) {
+ case DE_MEDIA_AUI:
+ case DE_MEDIA_TP:
+ case DE_MEDIA_TP_FD:
+ de->media[i].type = i;
+ de->media[i].csr13 = t21040_csr13[i];
+ de->media[i].csr14 = t21040_csr14[i];
+ de->media[i].csr15 = t21040_csr15[i];
+ break;
+ default:
+ de->media[i].type = DE_MEDIA_INVALID;
+ break;
+ }
+ }
+}
+
+/* Note: this routine returns extra data bits for size detection. */
+static unsigned tulip_read_eeprom(void __iomem *regs, int location,
+ int addr_len)
+{
+ int i;
+ unsigned retval = 0;
+ void __iomem *ee_addr = regs + ROMCmd;
+ int read_cmd = location | (EE_READ_CMD << addr_len);
+
+ writel(EE_ENB & ~EE_CS, ee_addr);
+ writel(EE_ENB, ee_addr);
+
+ /* Shift the read command bits out. */
+ for (i = 4 + addr_len; i >= 0; i--) {
+ short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
+ writel(EE_ENB | dataval, ee_addr);
+ readl(ee_addr);
+ writel(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
+ readl(ee_addr);
+ retval = (retval << 1) | ((readl(ee_addr) & EE_DATA_READ) ? 1 : 0);
+ }
+ writel(EE_ENB, ee_addr);
+ readl(ee_addr);
+
+ for (i = 16; i > 0; i--) {
+ writel(EE_ENB | EE_SHIFT_CLK, ee_addr);
+ readl(ee_addr);
+ retval = (retval << 1) | ((readl(ee_addr) & EE_DATA_READ) ? 1 : 0);
+ writel(EE_ENB, ee_addr);
+ readl(ee_addr);
+ }
+
+ /* Terminate the EEPROM access. */
+ writel(EE_ENB & ~EE_CS, ee_addr);
+ return retval;
+}
+
+static void de21041_get_srom_info(struct de_private *de)
+{
+ unsigned i, sa_offset = 0, ofs;
+ u8 ee_data[DE_EEPROM_SIZE + 6] = {};
+ unsigned ee_addr_size = tulip_read_eeprom(de->regs, 0xff, 8) & 0x40000 ? 8 : 6;
+ struct de_srom_info_leaf *il;
+ void *bufp;
+
+ /* download entire eeprom */
+ for (i = 0; i < DE_EEPROM_WORDS; i++)
+ ((__le16 *)ee_data)[i] =
+ cpu_to_le16(tulip_read_eeprom(de->regs, i, ee_addr_size));
+
+ /* DEC now has a specification but early board makers
+ just put the address in the first EEPROM locations. */
+ /* This does memcmp(eedata, eedata+16, 8) */
+
+#ifndef CONFIG_MIPS_COBALT
+
+ for (i = 0; i < 8; i ++)
+ if (ee_data[i] != ee_data[16+i])
+ sa_offset = 20;
+
+#endif
+
+ /* store MAC address */
+ eth_hw_addr_set(de->dev, &ee_data[sa_offset]);
+
+ /* get offset of controller 0 info leaf. ignore 2nd byte. */
+ ofs = ee_data[SROMC0InfoLeaf];
+ if (ofs >= (sizeof(ee_data) - sizeof(struct de_srom_info_leaf) - sizeof(struct de_srom_media_block)))
+ goto bad_srom;
+
+ /* get pointer to info leaf */
+ il = (struct de_srom_info_leaf *) &ee_data[ofs];
+
+ /* paranoia checks */
+ if (il->n_blocks == 0)
+ goto bad_srom;
+ if ((sizeof(ee_data) - ofs) <
+ (sizeof(struct de_srom_info_leaf) + (sizeof(struct de_srom_media_block) * il->n_blocks)))
+ goto bad_srom;
+
+ /* get default media type */
+ switch (get_unaligned(&il->default_media)) {
+ case 0x0001: de->media_type = DE_MEDIA_BNC; break;
+ case 0x0002: de->media_type = DE_MEDIA_AUI; break;
+ case 0x0204: de->media_type = DE_MEDIA_TP_FD; break;
+ default: de->media_type = DE_MEDIA_TP_AUTO; break;
+ }
+
+ if (netif_msg_probe(de))
+ pr_info("de%d: SROM leaf offset %u, default media %s\n",
+ de->board_idx, ofs, media_name[de->media_type]);
+
+ /* init SIA register values to defaults */
+ for (i = 0; i < DE_MAX_MEDIA; i++) {
+ de->media[i].type = DE_MEDIA_INVALID;
+ de->media[i].csr13 = 0xffff;
+ de->media[i].csr14 = 0xffff;
+ de->media[i].csr15 = 0xffff;
+ }
+
+ /* parse media blocks to see what medias are supported,
+ * and if any custom CSR values are provided
+ */
+ bufp = ((void *)il) + sizeof(*il);
+ for (i = 0; i < il->n_blocks; i++) {
+ struct de_srom_media_block *ib = bufp;
+ unsigned idx;
+
+ /* index based on media type in media block */
+ switch(ib->opts & MediaBlockMask) {
+ case 0: /* 10baseT */
+ de->media_supported |= SUPPORTED_TP | SUPPORTED_10baseT_Half
+ | SUPPORTED_Autoneg;
+ idx = DE_MEDIA_TP;
+ de->media[DE_MEDIA_TP_AUTO].type = DE_MEDIA_TP_AUTO;
+ break;
+ case 1: /* BNC */
+ de->media_supported |= SUPPORTED_BNC;
+ idx = DE_MEDIA_BNC;
+ break;
+ case 2: /* AUI */
+ de->media_supported |= SUPPORTED_AUI;
+ idx = DE_MEDIA_AUI;
+ break;
+ case 4: /* 10baseT-FD */
+ de->media_supported |= SUPPORTED_TP | SUPPORTED_10baseT_Full
+ | SUPPORTED_Autoneg;
+ idx = DE_MEDIA_TP_FD;
+ de->media[DE_MEDIA_TP_AUTO].type = DE_MEDIA_TP_AUTO;
+ break;
+ default:
+ goto bad_srom;
+ }
+
+ de->media[idx].type = idx;
+
+ if (netif_msg_probe(de))
+ pr_info("de%d: media block #%u: %s",
+ de->board_idx, i,
+ media_name[de->media[idx].type]);
+
+ bufp += sizeof (ib->opts);
+
+ if (ib->opts & MediaCustomCSRs) {
+ de->media[idx].csr13 = get_unaligned(&ib->csr13);
+ de->media[idx].csr14 = get_unaligned(&ib->csr14);
+ de->media[idx].csr15 = get_unaligned(&ib->csr15);
+ bufp += sizeof(ib->csr13) + sizeof(ib->csr14) +
+ sizeof(ib->csr15);
+
+ if (netif_msg_probe(de))
+ pr_cont(" (%x,%x,%x)\n",
+ de->media[idx].csr13,
+ de->media[idx].csr14,
+ de->media[idx].csr15);
+
+ } else {
+ if (netif_msg_probe(de))
+ pr_cont("\n");
+ }
+
+ if (bufp > ((void *)&ee_data[DE_EEPROM_SIZE - 3]))
+ break;
+ }
+
+ de->media_advertise = de->media_supported;
+
+fill_defaults:
+ /* fill in defaults, for cases where custom CSRs not used */
+ for (i = 0; i < DE_MAX_MEDIA; i++) {
+ if (de->media[i].csr13 == 0xffff)
+ de->media[i].csr13 = t21041_csr13[i];
+ if (de->media[i].csr14 == 0xffff) {
+ /* autonegotiation is broken at least on some chip
+ revisions - rev. 0x21 works, 0x11 does not */
+ if (de->pdev->revision < 0x20)
+ de->media[i].csr14 = t21041_csr14_brk[i];
+ else
+ de->media[i].csr14 = t21041_csr14[i];
+ }
+ if (de->media[i].csr15 == 0xffff)
+ de->media[i].csr15 = t21041_csr15[i];
+ }
+
+ de->ee_data = kmemdup(&ee_data[0], DE_EEPROM_SIZE, GFP_KERNEL);
+
+ return;
+
+bad_srom:
+ /* for error cases, it's ok to assume we support all these */
+ for (i = 0; i < DE_MAX_MEDIA; i++)
+ de->media[i].type = i;
+ de->media_supported =
+ SUPPORTED_10baseT_Half |
+ SUPPORTED_10baseT_Full |
+ SUPPORTED_Autoneg |
+ SUPPORTED_TP |
+ SUPPORTED_AUI |
+ SUPPORTED_BNC;
+ goto fill_defaults;
+}
+
+static const struct net_device_ops de_netdev_ops = {
+ .ndo_open = de_open,
+ .ndo_stop = de_close,
+ .ndo_set_rx_mode = de_set_rx_mode,
+ .ndo_start_xmit = de_start_xmit,
+ .ndo_get_stats = de_get_stats,
+ .ndo_tx_timeout = de_tx_timeout,
+ .ndo_set_mac_address = eth_mac_addr,
+ .ndo_validate_addr = eth_validate_addr,
+};
+
+static int de_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+ struct net_device *dev;
+ struct de_private *de;
+ int rc;
+ void __iomem *regs;
+ unsigned long pciaddr;
+ static int board_idx = -1;
+
+ board_idx++;
+
+ /* allocate a new ethernet device structure, and fill in defaults */
+ dev = alloc_etherdev(sizeof(struct de_private));
+ if (!dev)
+ return -ENOMEM;
+
+ dev->netdev_ops = &de_netdev_ops;
+ SET_NETDEV_DEV(dev, &pdev->dev);
+ dev->ethtool_ops = &de_ethtool_ops;
+ dev->watchdog_timeo = TX_TIMEOUT;
+
+ de = netdev_priv(dev);
+ de->de21040 = ent->driver_data == 0 ? 1 : 0;
+ de->pdev = pdev;
+ de->dev = dev;
+ de->msg_enable = (debug < 0 ? DE_DEF_MSG_ENABLE : debug);
+ de->board_idx = board_idx;
+ spin_lock_init (&de->lock);
+ timer_setup(&de->media_timer,
+ de->de21040 ? de21040_media_timer : de21041_media_timer,
+ 0);
+
+ netif_carrier_off(dev);
+
+ /* wake up device, assign resources */
+ rc = pci_enable_device(pdev);
+ if (rc)
+ goto err_out_free;
+
+ /* reserve PCI resources to ensure driver atomicity */
+ rc = pci_request_regions(pdev, DRV_NAME);
+ if (rc)
+ goto err_out_disable;
+
+ /* check for invalid IRQ value */
+ if (pdev->irq < 2) {
+ rc = -EIO;
+ pr_err("invalid irq (%d) for pci dev %s\n",
+ pdev->irq, pci_name(pdev));
+ goto err_out_res;
+ }
+
+ /* obtain and check validity of PCI I/O address */
+ pciaddr = pci_resource_start(pdev, 1);
+ if (!pciaddr) {
+ rc = -EIO;
+ pr_err("no MMIO resource for pci dev %s\n", pci_name(pdev));
+ goto err_out_res;
+ }
+ if (pci_resource_len(pdev, 1) < DE_REGS_SIZE) {
+ rc = -EIO;
+ pr_err("MMIO resource (%llx) too small on pci dev %s\n",
+ (unsigned long long)pci_resource_len(pdev, 1),
+ pci_name(pdev));
+ goto err_out_res;
+ }
+
+ /* remap CSR registers */
+ regs = ioremap(pciaddr, DE_REGS_SIZE);
+ if (!regs) {
+ rc = -EIO;
+ pr_err("Cannot map PCI MMIO (%llx@%lx) on pci dev %s\n",
+ (unsigned long long)pci_resource_len(pdev, 1),
+ pciaddr, pci_name(pdev));
+ goto err_out_res;
+ }
+ de->regs = regs;
+
+ de_adapter_wake(de);
+
+ /* make sure hardware is not running */
+ rc = de_reset_mac(de);
+ if (rc) {
+ pr_err("Cannot reset MAC, pci dev %s\n", pci_name(pdev));
+ goto err_out_iomap;
+ }
+
+ /* get MAC address, initialize default media type and
+ * get list of supported media
+ */
+ if (de->de21040) {
+ de21040_get_mac_address(de);
+ de21040_get_media_info(de);
+ } else {
+ de21041_get_srom_info(de);
+ }
+
+ /* register new network interface with kernel */
+ rc = register_netdev(dev);
+ if (rc)
+ goto err_out_iomap;
+
+ /* print info about board and interface just registered */
+ netdev_info(dev, "%s at %p, %pM, IRQ %d\n",
+ de->de21040 ? "21040" : "21041",
+ regs, dev->dev_addr, pdev->irq);
+
+ pci_set_drvdata(pdev, dev);
+
+ /* enable busmastering */
+ pci_set_master(pdev);
+
+ /* put adapter to sleep */
+ de_adapter_sleep(de);
+
+ return 0;
+
+err_out_iomap:
+ kfree(de->ee_data);
+ iounmap(regs);
+err_out_res:
+ pci_release_regions(pdev);
+err_out_disable:
+ pci_disable_device(pdev);
+err_out_free:
+ free_netdev(dev);
+ return rc;
+}
+
+static void de_remove_one(struct pci_dev *pdev)
+{
+ struct net_device *dev = pci_get_drvdata(pdev);
+ struct de_private *de = netdev_priv(dev);
+
+ BUG_ON(!dev);
+ unregister_netdev(dev);
+ kfree(de->ee_data);
+ iounmap(de->regs);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ free_netdev(dev);
+}
+
+static int __maybe_unused de_suspend(struct device *dev_d)
+{
+ struct pci_dev *pdev = to_pci_dev(dev_d);
+ struct net_device *dev = pci_get_drvdata(pdev);
+ struct de_private *de = netdev_priv(dev);
+
+ rtnl_lock();
+ if (netif_running (dev)) {
+ const int irq = pdev->irq;
+
+ del_timer_sync(&de->media_timer);
+
+ disable_irq(irq);
+ spin_lock_irq(&de->lock);
+
+ de_stop_hw(de);
+ netif_stop_queue(dev);
+ netif_device_detach(dev);
+ netif_carrier_off(dev);
+
+ spin_unlock_irq(&de->lock);
+ enable_irq(irq);
+
+ /* Update the error counts. */
+ __de_get_stats(de);
+
+ synchronize_irq(irq);
+ de_clean_rings(de);
+
+ de_adapter_sleep(de);
+ } else {
+ netif_device_detach(dev);
+ }
+ rtnl_unlock();
+ return 0;
+}
+
+static int __maybe_unused de_resume(struct device *dev_d)
+{
+ struct pci_dev *pdev = to_pci_dev(dev_d);
+ struct net_device *dev = pci_get_drvdata(pdev);
+ struct de_private *de = netdev_priv(dev);
+
+ rtnl_lock();
+ if (netif_device_present(dev))
+ goto out;
+ if (!netif_running(dev))
+ goto out_attach;
+ pci_set_master(pdev);
+ de_init_rings(de);
+ de_init_hw(de);
+out_attach:
+ netif_device_attach(dev);
+out:
+ rtnl_unlock();
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(de_pm_ops, de_suspend, de_resume);
+
+static void de_shutdown(struct pci_dev *pdev)
+{
+ struct net_device *dev = pci_get_drvdata(pdev);
+
+ rtnl_lock();
+ dev_close(dev);
+ rtnl_unlock();
+}
+
+static struct pci_driver de_driver = {
+ .name = DRV_NAME,
+ .id_table = de_pci_tbl,
+ .probe = de_init_one,
+ .remove = de_remove_one,
+ .shutdown = de_shutdown,
+ .driver.pm = &de_pm_ops,
+};
+
+module_pci_driver(de_driver);
diff --git a/drivers/net/ethernet/dec/tulip/dmfe.c b/drivers/net/ethernet/dec/tulip/dmfe.c
new file mode 100644
index 000000000..3188ba7b4
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/dmfe.c
@@ -0,0 +1,2218 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
+ ethernet driver for Linux.
+ Copyright (C) 1997 Sten Wang
+
+
+ DAVICOM Web-Site: www.davicom.com.tw
+
+ Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
+ Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
+
+ (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
+
+ Marcelo Tosatti <marcelo@conectiva.com.br> :
+ Made it compile in 2.3 (device to net_device)
+
+ Alan Cox <alan@lxorguk.ukuu.org.uk> :
+ Cleaned up for kernel merge.
+ Removed the back compatibility support
+ Reformatted, fixing spelling etc as I went
+ Removed IRQ 0-15 assumption
+
+ Jeff Garzik <jgarzik@pobox.com> :
+ Updated to use new PCI driver API.
+ Resource usage cleanups.
+ Report driver version to user.
+
+ Tobias Ringstrom <tori@unhappy.mine.nu> :
+ Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
+ Andrew Morton and Frank Davis for the SMP safety fixes.
+
+ Vojtech Pavlik <vojtech@suse.cz> :
+ Cleaned up pointer arithmetics.
+ Fixed a lot of 64bit issues.
+ Cleaned up printk()s a bit.
+ Fixed some obvious big endian problems.
+
+ Tobias Ringstrom <tori@unhappy.mine.nu> :
+ Use time_after for jiffies calculation. Added ethtool
+ support. Updated PCI resource allocation. Do not
+ forget to unmap PCI mapped skbs.
+
+ Alan Cox <alan@lxorguk.ukuu.org.uk>
+ Added new PCI identifiers provided by Clear Zhang at ALi
+ for their 1563 ethernet device.
+
+ TODO
+
+ Check on 64 bit boxes.
+ Check and fix on big endian boxes.
+
+ Test and make sure PCI latency is now correct for all cases.
+*/
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#define DRV_NAME "dmfe"
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/ptrace.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/skbuff.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/crc32.h>
+#include <linux/bitops.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/dma.h>
+#include <linux/uaccess.h>
+#include <asm/irq.h>
+
+#ifdef CONFIG_TULIP_DM910X
+#include <linux/of.h>
+#endif
+
+
+/* Board/System/Debug information/definition ---------------- */
+#define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
+#define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
+#define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
+#define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
+
+#define DM9102_IO_SIZE 0x80
+#define DM9102A_IO_SIZE 0x100
+#define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
+#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
+#define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
+#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
+#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
+#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
+#define TX_BUF_ALLOC 0x600
+#define RX_ALLOC_SIZE 0x620
+#define DM910X_RESET 1
+#define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
+#define CR6_DEFAULT 0x00080000 /* HD */
+#define CR7_DEFAULT 0x180c1
+#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
+#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
+#define MAX_PACKET_SIZE 1514
+#define DMFE_MAX_MULTICAST 14
+#define RX_COPY_SIZE 100
+#define MAX_CHECK_PACKET 0x8000
+#define DM9801_NOISE_FLOOR 8
+#define DM9802_NOISE_FLOOR 5
+
+#define DMFE_WOL_LINKCHANGE 0x20000000
+#define DMFE_WOL_SAMPLEPACKET 0x10000000
+#define DMFE_WOL_MAGICPACKET 0x08000000
+
+
+#define DMFE_10MHF 0
+#define DMFE_100MHF 1
+#define DMFE_10MFD 4
+#define DMFE_100MFD 5
+#define DMFE_AUTO 8
+#define DMFE_1M_HPNA 0x10
+
+#define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
+#define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
+#define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
+#define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
+#define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
+#define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
+
+#define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
+#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
+#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
+
+#define dw32(reg, val) iowrite32(val, ioaddr + (reg))
+#define dw16(reg, val) iowrite16(val, ioaddr + (reg))
+#define dr32(reg) ioread32(ioaddr + (reg))
+#define dr16(reg) ioread16(ioaddr + (reg))
+#define dr8(reg) ioread8(ioaddr + (reg))
+
+#define DMFE_DBUG(dbug_now, msg, value) \
+ do { \
+ if (dmfe_debug || (dbug_now)) \
+ pr_err("%s %lx\n", \
+ (msg), (long) (value)); \
+ } while (0)
+
+#define SHOW_MEDIA_TYPE(mode) \
+ pr_info("Change Speed to %sMhz %s duplex\n" , \
+ (mode & 1) ? "100":"10", \
+ (mode & 4) ? "full":"half");
+
+
+/* CR9 definition: SROM/MII */
+#define CR9_SROM_READ 0x4800
+#define CR9_SRCS 0x1
+#define CR9_SRCLK 0x2
+#define CR9_CRDOUT 0x8
+#define SROM_DATA_0 0x0
+#define SROM_DATA_1 0x4
+#define PHY_DATA_1 0x20000
+#define PHY_DATA_0 0x00000
+#define MDCLKH 0x10000
+
+#define PHY_POWER_DOWN 0x800
+
+#define SROM_V41_CODE 0x14
+
+#define __CHK_IO_SIZE(pci_id, dev_rev) \
+ (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
+ DM9102A_IO_SIZE: DM9102_IO_SIZE)
+
+#define CHK_IO_SIZE(pci_dev) \
+ (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
+ (pci_dev)->revision))
+
+/* Structure/enum declaration ------------------------------- */
+struct tx_desc {
+ __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
+ char *tx_buf_ptr; /* Data for us */
+ struct tx_desc *next_tx_desc;
+} __attribute__(( aligned(32) ));
+
+struct rx_desc {
+ __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
+ struct sk_buff *rx_skb_ptr; /* Data for us */
+ struct rx_desc *next_rx_desc;
+} __attribute__(( aligned(32) ));
+
+struct dmfe_board_info {
+ u32 chip_id; /* Chip vendor/Device ID */
+ u8 chip_revision; /* Chip revision */
+ struct net_device *next_dev; /* next device */
+ struct pci_dev *pdev; /* PCI device */
+ spinlock_t lock;
+
+ void __iomem *ioaddr; /* I/O base address */
+ u32 cr0_data;
+ u32 cr5_data;
+ u32 cr6_data;
+ u32 cr7_data;
+ u32 cr15_data;
+
+ /* pointer for memory physical address */
+ dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
+ dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
+ dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
+ dma_addr_t first_tx_desc_dma;
+ dma_addr_t first_rx_desc_dma;
+
+ /* descriptor pointer */
+ unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
+ unsigned char *buf_pool_start; /* Tx buffer pool align dword */
+ unsigned char *desc_pool_ptr; /* descriptor pool memory */
+ struct tx_desc *first_tx_desc;
+ struct tx_desc *tx_insert_ptr;
+ struct tx_desc *tx_remove_ptr;
+ struct rx_desc *first_rx_desc;
+ struct rx_desc *rx_insert_ptr;
+ struct rx_desc *rx_ready_ptr; /* packet come pointer */
+ unsigned long tx_packet_cnt; /* transmitted packet count */
+ unsigned long tx_queue_cnt; /* wait to send packet count */
+ unsigned long rx_avail_cnt; /* available rx descriptor count */
+ unsigned long interval_rx_cnt; /* rx packet count a callback time */
+
+ u16 HPNA_command; /* For HPNA register 16 */
+ u16 HPNA_timer; /* For HPNA remote device check */
+ u16 dbug_cnt;
+ u16 NIC_capability; /* NIC media capability */
+ u16 PHY_reg4; /* Saved Phyxcer register 4 value */
+
+ u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
+ u8 chip_type; /* Keep DM9102A chip type */
+ u8 media_mode; /* user specify media mode */
+ u8 op_mode; /* real work media mode */
+ u8 phy_addr;
+ u8 wait_reset; /* Hardware failed, need to reset */
+ u8 dm910x_chk_mode; /* Operating mode check */
+ u8 first_in_callback; /* Flag to record state */
+ u8 wol_mode; /* user WOL settings */
+ struct timer_list timer;
+
+ /* Driver defined statistic counter */
+ unsigned long tx_fifo_underrun;
+ unsigned long tx_loss_carrier;
+ unsigned long tx_no_carrier;
+ unsigned long tx_late_collision;
+ unsigned long tx_excessive_collision;
+ unsigned long tx_jabber_timeout;
+ unsigned long reset_count;
+ unsigned long reset_cr8;
+ unsigned long reset_fatal;
+ unsigned long reset_TXtimeout;
+
+ /* NIC SROM data */
+ unsigned char srom[128];
+};
+
+enum dmfe_offsets {
+ DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
+ DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
+ DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
+ DCR15 = 0x78
+};
+
+enum dmfe_CR6_bits {
+ CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
+ CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
+ CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
+};
+
+/* Global variable declaration ----------------------------- */
+static int dmfe_debug;
+static unsigned char dmfe_media_mode = DMFE_AUTO;
+static u32 dmfe_cr6_user_set;
+
+/* For module input parameter */
+static int debug;
+static u32 cr6set;
+static unsigned char mode = 8;
+static u8 chkmode = 1;
+static u8 HPNA_mode; /* Default: Low Power/High Speed */
+static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
+static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
+static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
+static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
+ 4: TX pause packet */
+
+
+/* function declaration ------------------------------------- */
+static int dmfe_open(struct net_device *);
+static netdev_tx_t dmfe_start_xmit(struct sk_buff *, struct net_device *);
+static int dmfe_stop(struct net_device *);
+static void dmfe_set_filter_mode(struct net_device *);
+static const struct ethtool_ops netdev_ethtool_ops;
+static u16 read_srom_word(void __iomem *, int);
+static irqreturn_t dmfe_interrupt(int , void *);
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void poll_dmfe (struct net_device *dev);
+#endif
+static void dmfe_descriptor_init(struct net_device *);
+static void allocate_rx_buffer(struct net_device *);
+static void update_cr6(u32, void __iomem *);
+static void send_filter_frame(struct net_device *);
+static void dm9132_id_table(struct net_device *);
+static u16 dmfe_phy_read(void __iomem *, u8, u8, u32);
+static void dmfe_phy_write(void __iomem *, u8, u8, u16, u32);
+static void dmfe_phy_write_1bit(void __iomem *, u32);
+static u16 dmfe_phy_read_1bit(void __iomem *);
+static u8 dmfe_sense_speed(struct dmfe_board_info *);
+static void dmfe_process_mode(struct dmfe_board_info *);
+static void dmfe_timer(struct timer_list *);
+static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
+static void dmfe_rx_packet(struct net_device *, struct dmfe_board_info *);
+static void dmfe_free_tx_pkt(struct net_device *, struct dmfe_board_info *);
+static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
+static void dmfe_dynamic_reset(struct net_device *);
+static void dmfe_free_rxbuffer(struct dmfe_board_info *);
+static void dmfe_init_dm910x(struct net_device *);
+static void dmfe_parse_srom(struct dmfe_board_info *);
+static void dmfe_program_DM9801(struct dmfe_board_info *, int);
+static void dmfe_program_DM9802(struct dmfe_board_info *);
+static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
+static void dmfe_set_phyxcer(struct dmfe_board_info *);
+
+/* DM910X network board routine ---------------------------- */
+
+static const struct net_device_ops netdev_ops = {
+ .ndo_open = dmfe_open,
+ .ndo_stop = dmfe_stop,
+ .ndo_start_xmit = dmfe_start_xmit,
+ .ndo_set_rx_mode = dmfe_set_filter_mode,
+ .ndo_set_mac_address = eth_mac_addr,
+ .ndo_validate_addr = eth_validate_addr,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+ .ndo_poll_controller = poll_dmfe,
+#endif
+};
+
+/*
+ * Search DM910X board ,allocate space and register it
+ */
+
+static int dmfe_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+ struct dmfe_board_info *db; /* board information structure */
+ struct net_device *dev;
+ u32 pci_pmr;
+ int i, err;
+
+ DMFE_DBUG(0, "dmfe_init_one()", 0);
+
+ /*
+ * SPARC on-board DM910x chips should be handled by the main
+ * tulip driver, except for early DM9100s.
+ */
+#ifdef CONFIG_TULIP_DM910X
+ if ((ent->driver_data == PCI_DM9100_ID && pdev->revision >= 0x30) ||
+ ent->driver_data == PCI_DM9102_ID) {
+ struct device_node *dp = pci_device_to_OF_node(pdev);
+
+ if (dp && of_get_property(dp, "local-mac-address", NULL)) {
+ pr_info("skipping on-board DM910x (use tulip)\n");
+ return -ENODEV;
+ }
+ }
+#endif
+
+ /* Init network device */
+ dev = alloc_etherdev(sizeof(*db));
+ if (dev == NULL)
+ return -ENOMEM;
+ SET_NETDEV_DEV(dev, &pdev->dev);
+
+ if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
+ pr_warn("32-bit PCI DMA not available\n");
+ err = -ENODEV;
+ goto err_out_free;
+ }
+
+ /* Enable Master/IO access, Disable memory access */
+ err = pci_enable_device(pdev);
+ if (err)
+ goto err_out_free;
+
+ if (!pci_resource_start(pdev, 0)) {
+ pr_err("I/O base is zero\n");
+ err = -ENODEV;
+ goto err_out_disable;
+ }
+
+ if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
+ pr_err("Allocated I/O size too small\n");
+ err = -ENODEV;
+ goto err_out_disable;
+ }
+
+#if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
+
+ /* Set Latency Timer 80h */
+ /* FIXME: setting values > 32 breaks some SiS 559x stuff.
+ Need a PCI quirk.. */
+
+ pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
+#endif
+
+ if (pci_request_regions(pdev, DRV_NAME)) {
+ pr_err("Failed to request PCI regions\n");
+ err = -ENODEV;
+ goto err_out_disable;
+ }
+
+ /* Init system & device */
+ db = netdev_priv(dev);
+
+ /* Allocate Tx/Rx descriptor memory */
+ db->desc_pool_ptr = dma_alloc_coherent(&pdev->dev,
+ sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
+ &db->desc_pool_dma_ptr, GFP_KERNEL);
+ if (!db->desc_pool_ptr) {
+ err = -ENOMEM;
+ goto err_out_res;
+ }
+
+ db->buf_pool_ptr = dma_alloc_coherent(&pdev->dev,
+ TX_BUF_ALLOC * TX_DESC_CNT + 4,
+ &db->buf_pool_dma_ptr, GFP_KERNEL);
+ if (!db->buf_pool_ptr) {
+ err = -ENOMEM;
+ goto err_out_free_desc;
+ }
+
+ db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
+ db->first_tx_desc_dma = db->desc_pool_dma_ptr;
+ db->buf_pool_start = db->buf_pool_ptr;
+ db->buf_pool_dma_start = db->buf_pool_dma_ptr;
+
+ db->chip_id = ent->driver_data;
+ /* IO type range. */
+ db->ioaddr = pci_iomap(pdev, 0, 0);
+ if (!db->ioaddr) {
+ err = -ENOMEM;
+ goto err_out_free_buf;
+ }
+
+ db->chip_revision = pdev->revision;
+ db->wol_mode = 0;
+
+ db->pdev = pdev;
+
+ pci_set_drvdata(pdev, dev);
+ dev->netdev_ops = &netdev_ops;
+ dev->ethtool_ops = &netdev_ethtool_ops;
+ netif_carrier_off(dev);
+ spin_lock_init(&db->lock);
+
+ pci_read_config_dword(pdev, 0x50, &pci_pmr);
+ pci_pmr &= 0x70000;
+ if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
+ db->chip_type = 1; /* DM9102A E3 */
+ else
+ db->chip_type = 0;
+
+ /* read 64 word srom data */
+ for (i = 0; i < 64; i++) {
+ ((__le16 *) db->srom)[i] =
+ cpu_to_le16(read_srom_word(db->ioaddr, i));
+ }
+
+ /* Set Node address */
+ eth_hw_addr_set(dev, &db->srom[20]);
+
+ err = register_netdev (dev);
+ if (err)
+ goto err_out_unmap;
+
+ dev_info(&dev->dev, "Davicom DM%04lx at pci%s, %pM, irq %d\n",
+ ent->driver_data >> 16,
+ pci_name(pdev), dev->dev_addr, pdev->irq);
+
+ pci_set_master(pdev);
+
+ return 0;
+
+err_out_unmap:
+ pci_iounmap(pdev, db->ioaddr);
+err_out_free_buf:
+ dma_free_coherent(&pdev->dev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
+ db->buf_pool_ptr, db->buf_pool_dma_ptr);
+err_out_free_desc:
+ dma_free_coherent(&pdev->dev,
+ sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
+ db->desc_pool_ptr, db->desc_pool_dma_ptr);
+err_out_res:
+ pci_release_regions(pdev);
+err_out_disable:
+ pci_disable_device(pdev);
+err_out_free:
+ free_netdev(dev);
+
+ return err;
+}
+
+
+static void dmfe_remove_one(struct pci_dev *pdev)
+{
+ struct net_device *dev = pci_get_drvdata(pdev);
+ struct dmfe_board_info *db = netdev_priv(dev);
+
+ DMFE_DBUG(0, "dmfe_remove_one()", 0);
+
+ if (dev) {
+
+ unregister_netdev(dev);
+ pci_iounmap(db->pdev, db->ioaddr);
+ dma_free_coherent(&db->pdev->dev,
+ sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
+ db->desc_pool_ptr, db->desc_pool_dma_ptr);
+ dma_free_coherent(&db->pdev->dev,
+ TX_BUF_ALLOC * TX_DESC_CNT + 4,
+ db->buf_pool_ptr, db->buf_pool_dma_ptr);
+ pci_release_regions(pdev);
+ free_netdev(dev); /* free board information */
+ }
+
+ DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
+}
+
+
+/*
+ * Open the interface.
+ * The interface is opened whenever "ifconfig" actives it.
+ */
+
+static int dmfe_open(struct net_device *dev)
+{
+ struct dmfe_board_info *db = netdev_priv(dev);
+ const int irq = db->pdev->irq;
+ int ret;
+
+ DMFE_DBUG(0, "dmfe_open", 0);
+
+ ret = request_irq(irq, dmfe_interrupt, IRQF_SHARED, dev->name, dev);
+ if (ret)
+ return ret;
+
+ /* system variable init */
+ db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
+ db->tx_packet_cnt = 0;
+ db->tx_queue_cnt = 0;
+ db->rx_avail_cnt = 0;
+ db->wait_reset = 0;
+
+ db->first_in_callback = 0;
+ db->NIC_capability = 0xf; /* All capability*/
+ db->PHY_reg4 = 0x1e0;
+
+ /* CR6 operation mode decision */
+ if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
+ (db->chip_revision >= 0x30) ) {
+ db->cr6_data |= DMFE_TXTH_256;
+ db->cr0_data = CR0_DEFAULT;
+ db->dm910x_chk_mode=4; /* Enter the normal mode */
+ } else {
+ db->cr6_data |= CR6_SFT; /* Store & Forward mode */
+ db->cr0_data = 0;
+ db->dm910x_chk_mode = 1; /* Enter the check mode */
+ }
+
+ /* Initialize DM910X board */
+ dmfe_init_dm910x(dev);
+
+ /* Active System Interface */
+ netif_wake_queue(dev);
+
+ /* set and active a timer process */
+ timer_setup(&db->timer, dmfe_timer, 0);
+ db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
+ add_timer(&db->timer);
+
+ return 0;
+}
+
+
+/* Initialize DM910X board
+ * Reset DM910X board
+ * Initialize TX/Rx descriptor chain structure
+ * Send the set-up frame
+ * Enable Tx/Rx machine
+ */
+
+static void dmfe_init_dm910x(struct net_device *dev)
+{
+ struct dmfe_board_info *db = netdev_priv(dev);
+ void __iomem *ioaddr = db->ioaddr;
+
+ DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
+
+ /* Reset DM910x MAC controller */
+ dw32(DCR0, DM910X_RESET); /* RESET MAC */
+ udelay(100);
+ dw32(DCR0, db->cr0_data);
+ udelay(5);
+
+ /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
+ db->phy_addr = 1;
+
+ /* Parser SROM and media mode */
+ dmfe_parse_srom(db);
+ db->media_mode = dmfe_media_mode;
+
+ /* RESET Phyxcer Chip by GPR port bit 7 */
+ dw32(DCR12, 0x180); /* Let bit 7 output port */
+ if (db->chip_id == PCI_DM9009_ID) {
+ dw32(DCR12, 0x80); /* Issue RESET signal */
+ mdelay(300); /* Delay 300 ms */
+ }
+ dw32(DCR12, 0x0); /* Clear RESET signal */
+
+ /* Process Phyxcer Media Mode */
+ if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
+ dmfe_set_phyxcer(db);
+
+ /* Media Mode Process */
+ if ( !(db->media_mode & DMFE_AUTO) )
+ db->op_mode = db->media_mode; /* Force Mode */
+
+ /* Initialize Transmit/Receive descriptor and CR3/4 */
+ dmfe_descriptor_init(dev);
+
+ /* Init CR6 to program DM910x operation */
+ update_cr6(db->cr6_data, ioaddr);
+
+ /* Send setup frame */
+ if (db->chip_id == PCI_DM9132_ID)
+ dm9132_id_table(dev); /* DM9132 */
+ else
+ send_filter_frame(dev); /* DM9102/DM9102A */
+
+ /* Init CR7, interrupt active bit */
+ db->cr7_data = CR7_DEFAULT;
+ dw32(DCR7, db->cr7_data);
+
+ /* Init CR15, Tx jabber and Rx watchdog timer */
+ dw32(DCR15, db->cr15_data);
+
+ /* Enable DM910X Tx/Rx function */
+ db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
+ update_cr6(db->cr6_data, ioaddr);
+}
+
+
+/*
+ * Hardware start transmission.
+ * Send a packet to media from the upper layer.
+ */
+
+static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ struct dmfe_board_info *db = netdev_priv(dev);
+ void __iomem *ioaddr = db->ioaddr;
+ struct tx_desc *txptr;
+ unsigned long flags;
+
+ DMFE_DBUG(0, "dmfe_start_xmit", 0);
+
+ /* Too large packet check */
+ if (skb->len > MAX_PACKET_SIZE) {
+ pr_err("big packet = %d\n", (u16)skb->len);
+ dev_kfree_skb_any(skb);
+ return NETDEV_TX_OK;
+ }
+
+ /* Resource flag check */
+ netif_stop_queue(dev);
+
+ spin_lock_irqsave(&db->lock, flags);
+
+ /* No Tx resource check, it never happen nromally */
+ if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
+ spin_unlock_irqrestore(&db->lock, flags);
+ pr_err("No Tx resource %ld\n", db->tx_queue_cnt);
+ return NETDEV_TX_BUSY;
+ }
+
+ /* Disable NIC interrupt */
+ dw32(DCR7, 0);
+
+ /* transmit this packet */
+ txptr = db->tx_insert_ptr;
+ skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
+ txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
+
+ /* Point to next transmit free descriptor */
+ db->tx_insert_ptr = txptr->next_tx_desc;
+
+ /* Transmit Packet Process */
+ if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
+ txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
+ db->tx_packet_cnt++; /* Ready to send */
+ dw32(DCR1, 0x1); /* Issue Tx polling */
+ netif_trans_update(dev); /* saved time stamp */
+ } else {
+ db->tx_queue_cnt++; /* queue TX packet */
+ dw32(DCR1, 0x1); /* Issue Tx polling */
+ }
+
+ /* Tx resource check */
+ if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
+ netif_wake_queue(dev);
+
+ /* Restore CR7 to enable interrupt */
+ spin_unlock_irqrestore(&db->lock, flags);
+ dw32(DCR7, db->cr7_data);
+
+ /* free this SKB */
+ dev_consume_skb_any(skb);
+
+ return NETDEV_TX_OK;
+}
+
+
+/*
+ * Stop the interface.
+ * The interface is stopped when it is brought.
+ */
+
+static int dmfe_stop(struct net_device *dev)
+{
+ struct dmfe_board_info *db = netdev_priv(dev);
+ void __iomem *ioaddr = db->ioaddr;
+
+ DMFE_DBUG(0, "dmfe_stop", 0);
+
+ /* disable system */
+ netif_stop_queue(dev);
+
+ /* deleted timer */
+ del_timer_sync(&db->timer);
+
+ /* Reset & stop DM910X board */
+ dw32(DCR0, DM910X_RESET);
+ udelay(100);
+ dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
+
+ /* free interrupt */
+ free_irq(db->pdev->irq, dev);
+
+ /* free allocated rx buffer */
+ dmfe_free_rxbuffer(db);
+
+#if 0
+ /* show statistic counter */
+ printk("FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
+ db->tx_fifo_underrun, db->tx_excessive_collision,
+ db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
+ db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
+ db->reset_fatal, db->reset_TXtimeout);
+#endif
+
+ return 0;
+}
+
+
+/*
+ * DM9102 insterrupt handler
+ * receive the packet to upper layer, free the transmitted packet
+ */
+
+static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
+{
+ struct net_device *dev = dev_id;
+ struct dmfe_board_info *db = netdev_priv(dev);
+ void __iomem *ioaddr = db->ioaddr;
+ unsigned long flags;
+
+ DMFE_DBUG(0, "dmfe_interrupt()", 0);
+
+ spin_lock_irqsave(&db->lock, flags);
+
+ /* Got DM910X status */
+ db->cr5_data = dr32(DCR5);
+ dw32(DCR5, db->cr5_data);
+ if ( !(db->cr5_data & 0xc1) ) {
+ spin_unlock_irqrestore(&db->lock, flags);
+ return IRQ_HANDLED;
+ }
+
+ /* Disable all interrupt in CR7 to solve the interrupt edge problem */
+ dw32(DCR7, 0);
+
+ /* Check system status */
+ if (db->cr5_data & 0x2000) {
+ /* system bus error happen */
+ DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
+ db->reset_fatal++;
+ db->wait_reset = 1; /* Need to RESET */
+ spin_unlock_irqrestore(&db->lock, flags);
+ return IRQ_HANDLED;
+ }
+
+ /* Received the coming packet */
+ if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
+ dmfe_rx_packet(dev, db);
+
+ /* reallocate rx descriptor buffer */
+ if (db->rx_avail_cnt<RX_DESC_CNT)
+ allocate_rx_buffer(dev);
+
+ /* Free the transmitted descriptor */
+ if ( db->cr5_data & 0x01)
+ dmfe_free_tx_pkt(dev, db);
+
+ /* Mode Check */
+ if (db->dm910x_chk_mode & 0x2) {
+ db->dm910x_chk_mode = 0x4;
+ db->cr6_data |= 0x100;
+ update_cr6(db->cr6_data, ioaddr);
+ }
+
+ /* Restore CR7 to enable interrupt mask */
+ dw32(DCR7, db->cr7_data);
+
+ spin_unlock_irqrestore(&db->lock, flags);
+ return IRQ_HANDLED;
+}
+
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+/*
+ * Polling 'interrupt' - used by things like netconsole to send skbs
+ * without having to re-enable interrupts. It's not called while
+ * the interrupt routine is executing.
+ */
+
+static void poll_dmfe (struct net_device *dev)
+{
+ struct dmfe_board_info *db = netdev_priv(dev);
+ const int irq = db->pdev->irq;
+
+ /* disable_irq here is not very nice, but with the lockless
+ interrupt handler we have no other choice. */
+ disable_irq(irq);
+ dmfe_interrupt (irq, dev);
+ enable_irq(irq);
+}
+#endif
+
+/*
+ * Free TX resource after TX complete
+ */
+
+static void dmfe_free_tx_pkt(struct net_device *dev, struct dmfe_board_info *db)
+{
+ struct tx_desc *txptr;
+ void __iomem *ioaddr = db->ioaddr;
+ u32 tdes0;
+
+ txptr = db->tx_remove_ptr;
+ while(db->tx_packet_cnt) {
+ tdes0 = le32_to_cpu(txptr->tdes0);
+ if (tdes0 & 0x80000000)
+ break;
+
+ /* A packet sent completed */
+ db->tx_packet_cnt--;
+ dev->stats.tx_packets++;
+
+ /* Transmit statistic counter */
+ if ( tdes0 != 0x7fffffff ) {
+ dev->stats.collisions += (tdes0 >> 3) & 0xf;
+ dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
+ if (tdes0 & TDES0_ERR_MASK) {
+ dev->stats.tx_errors++;
+
+ if (tdes0 & 0x0002) { /* UnderRun */
+ db->tx_fifo_underrun++;
+ if ( !(db->cr6_data & CR6_SFT) ) {
+ db->cr6_data = db->cr6_data | CR6_SFT;
+ update_cr6(db->cr6_data, ioaddr);
+ }
+ }
+ if (tdes0 & 0x0100)
+ db->tx_excessive_collision++;
+ if (tdes0 & 0x0200)
+ db->tx_late_collision++;
+ if (tdes0 & 0x0400)
+ db->tx_no_carrier++;
+ if (tdes0 & 0x0800)
+ db->tx_loss_carrier++;
+ if (tdes0 & 0x4000)
+ db->tx_jabber_timeout++;
+ }
+ }
+
+ txptr = txptr->next_tx_desc;
+ }/* End of while */
+
+ /* Update TX remove pointer to next */
+ db->tx_remove_ptr = txptr;
+
+ /* Send the Tx packet in queue */
+ if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
+ txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
+ db->tx_packet_cnt++; /* Ready to send */
+ db->tx_queue_cnt--;
+ dw32(DCR1, 0x1); /* Issue Tx polling */
+ netif_trans_update(dev); /* saved time stamp */
+ }
+
+ /* Resource available check */
+ if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
+ netif_wake_queue(dev); /* Active upper layer, send again */
+}
+
+
+/*
+ * Calculate the CRC valude of the Rx packet
+ * flag = 1 : return the reverse CRC (for the received packet CRC)
+ * 0 : return the normal CRC (for Hash Table index)
+ */
+
+static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
+{
+ u32 crc = crc32(~0, Data, Len);
+ if (flag) crc = ~crc;
+ return crc;
+}
+
+
+/*
+ * Receive the come packet and pass to upper layer
+ */
+
+static void dmfe_rx_packet(struct net_device *dev, struct dmfe_board_info *db)
+{
+ struct rx_desc *rxptr;
+ struct sk_buff *skb, *newskb;
+ int rxlen;
+ u32 rdes0;
+
+ rxptr = db->rx_ready_ptr;
+
+ while(db->rx_avail_cnt) {
+ rdes0 = le32_to_cpu(rxptr->rdes0);
+ if (rdes0 & 0x80000000) /* packet owner check */
+ break;
+
+ db->rx_avail_cnt--;
+ db->interval_rx_cnt++;
+
+ dma_unmap_single(&db->pdev->dev, le32_to_cpu(rxptr->rdes2),
+ RX_ALLOC_SIZE, DMA_FROM_DEVICE);
+
+ if ( (rdes0 & 0x300) != 0x300) {
+ /* A packet without First/Last flag */
+ /* reuse this SKB */
+ DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
+ dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
+ } else {
+ /* A packet with First/Last flag */
+ rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
+
+ /* error summary bit check */
+ if (rdes0 & 0x8000) {
+ /* This is a error packet */
+ dev->stats.rx_errors++;
+ if (rdes0 & 1)
+ dev->stats.rx_fifo_errors++;
+ if (rdes0 & 2)
+ dev->stats.rx_crc_errors++;
+ if (rdes0 & 0x80)
+ dev->stats.rx_length_errors++;
+ }
+
+ if ( !(rdes0 & 0x8000) ||
+ ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
+ skb = rxptr->rx_skb_ptr;
+
+ /* Received Packet CRC check need or not */
+ if ( (db->dm910x_chk_mode & 1) &&
+ (cal_CRC(skb->data, rxlen, 1) !=
+ (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
+ /* Found a error received packet */
+ dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
+ db->dm910x_chk_mode = 3;
+ } else {
+ /* Good packet, send to upper layer */
+ /* Shorst packet used new SKB */
+ if ((rxlen < RX_COPY_SIZE) &&
+ ((newskb = netdev_alloc_skb(dev, rxlen + 2))
+ != NULL)) {
+
+ skb = newskb;
+ /* size less than COPY_SIZE, allocate a rxlen SKB */
+ skb_reserve(skb, 2); /* 16byte align */
+ skb_copy_from_linear_data(rxptr->rx_skb_ptr,
+ skb_put(skb, rxlen),
+ rxlen);
+ dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
+ } else
+ skb_put(skb, rxlen);
+
+ skb->protocol = eth_type_trans(skb, dev);
+ netif_rx(skb);
+ dev->stats.rx_packets++;
+ dev->stats.rx_bytes += rxlen;
+ }
+ } else {
+ /* Reuse SKB buffer when the packet is error */
+ DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
+ dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
+ }
+ }
+
+ rxptr = rxptr->next_rx_desc;
+ }
+
+ db->rx_ready_ptr = rxptr;
+}
+
+/*
+ * Set DM910X multicast address
+ */
+
+static void dmfe_set_filter_mode(struct net_device *dev)
+{
+ struct dmfe_board_info *db = netdev_priv(dev);
+ unsigned long flags;
+ int mc_count = netdev_mc_count(dev);
+
+ DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
+ spin_lock_irqsave(&db->lock, flags);
+
+ if (dev->flags & IFF_PROMISC) {
+ DMFE_DBUG(0, "Enable PROM Mode", 0);
+ db->cr6_data |= CR6_PM | CR6_PBF;
+ update_cr6(db->cr6_data, db->ioaddr);
+ spin_unlock_irqrestore(&db->lock, flags);
+ return;
+ }
+
+ if (dev->flags & IFF_ALLMULTI || mc_count > DMFE_MAX_MULTICAST) {
+ DMFE_DBUG(0, "Pass all multicast address", mc_count);
+ db->cr6_data &= ~(CR6_PM | CR6_PBF);
+ db->cr6_data |= CR6_PAM;
+ spin_unlock_irqrestore(&db->lock, flags);
+ return;
+ }
+
+ DMFE_DBUG(0, "Set multicast address", mc_count);
+ if (db->chip_id == PCI_DM9132_ID)
+ dm9132_id_table(dev); /* DM9132 */
+ else
+ send_filter_frame(dev); /* DM9102/DM9102A */
+ spin_unlock_irqrestore(&db->lock, flags);
+}
+
+/*
+ * Ethtool interace
+ */
+
+static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
+ struct ethtool_drvinfo *info)
+{
+ struct dmfe_board_info *np = netdev_priv(dev);
+
+ strscpy(info->driver, DRV_NAME, sizeof(info->driver));
+ strscpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
+}
+
+static int dmfe_ethtool_set_wol(struct net_device *dev,
+ struct ethtool_wolinfo *wolinfo)
+{
+ struct dmfe_board_info *db = netdev_priv(dev);
+
+ if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
+ WAKE_ARP | WAKE_MAGICSECURE))
+ return -EOPNOTSUPP;
+
+ db->wol_mode = wolinfo->wolopts;
+ return 0;
+}
+
+static void dmfe_ethtool_get_wol(struct net_device *dev,
+ struct ethtool_wolinfo *wolinfo)
+{
+ struct dmfe_board_info *db = netdev_priv(dev);
+
+ wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
+ wolinfo->wolopts = db->wol_mode;
+}
+
+
+static const struct ethtool_ops netdev_ethtool_ops = {
+ .get_drvinfo = dmfe_ethtool_get_drvinfo,
+ .get_link = ethtool_op_get_link,
+ .set_wol = dmfe_ethtool_set_wol,
+ .get_wol = dmfe_ethtool_get_wol,
+};
+
+/*
+ * A periodic timer routine
+ * Dynamic media sense, allocate Rx buffer...
+ */
+
+static void dmfe_timer(struct timer_list *t)
+{
+ struct dmfe_board_info *db = from_timer(db, t, timer);
+ struct net_device *dev = pci_get_drvdata(db->pdev);
+ void __iomem *ioaddr = db->ioaddr;
+ u32 tmp_cr8;
+ unsigned char tmp_cr12;
+ unsigned long flags;
+
+ int link_ok, link_ok_phy;
+
+ DMFE_DBUG(0, "dmfe_timer()", 0);
+ spin_lock_irqsave(&db->lock, flags);
+
+ /* Media mode process when Link OK before enter this route */
+ if (db->first_in_callback == 0) {
+ db->first_in_callback = 1;
+ if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
+ db->cr6_data &= ~0x40000;
+ update_cr6(db->cr6_data, ioaddr);
+ dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
+ db->cr6_data |= 0x40000;
+ update_cr6(db->cr6_data, ioaddr);
+ db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
+ add_timer(&db->timer);
+ spin_unlock_irqrestore(&db->lock, flags);
+ return;
+ }
+ }
+
+
+ /* Operating Mode Check */
+ if ( (db->dm910x_chk_mode & 0x1) &&
+ (dev->stats.rx_packets > MAX_CHECK_PACKET) )
+ db->dm910x_chk_mode = 0x4;
+
+ /* Dynamic reset DM910X : system error or transmit time-out */
+ tmp_cr8 = dr32(DCR8);
+ if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
+ db->reset_cr8++;
+ db->wait_reset = 1;
+ }
+ db->interval_rx_cnt = 0;
+
+ /* TX polling kick monitor */
+ if ( db->tx_packet_cnt &&
+ time_after(jiffies, dev_trans_start(dev) + DMFE_TX_KICK) ) {
+ dw32(DCR1, 0x1); /* Tx polling again */
+
+ /* TX Timeout */
+ if (time_after(jiffies, dev_trans_start(dev) + DMFE_TX_TIMEOUT) ) {
+ db->reset_TXtimeout++;
+ db->wait_reset = 1;
+ dev_warn(&dev->dev, "Tx timeout - resetting\n");
+ }
+ }
+
+ if (db->wait_reset) {
+ DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
+ db->reset_count++;
+ dmfe_dynamic_reset(dev);
+ db->first_in_callback = 0;
+ db->timer.expires = DMFE_TIMER_WUT;
+ add_timer(&db->timer);
+ spin_unlock_irqrestore(&db->lock, flags);
+ return;
+ }
+
+ /* Link status check, Dynamic media type change */
+ if (db->chip_id == PCI_DM9132_ID)
+ tmp_cr12 = dr8(DCR9 + 3); /* DM9132 */
+ else
+ tmp_cr12 = dr8(DCR12); /* DM9102/DM9102A */
+
+ if ( ((db->chip_id == PCI_DM9102_ID) &&
+ (db->chip_revision == 0x30)) ||
+ ((db->chip_id == PCI_DM9132_ID) &&
+ (db->chip_revision == 0x10)) ) {
+ /* DM9102A Chip */
+ if (tmp_cr12 & 2)
+ link_ok = 0;
+ else
+ link_ok = 1;
+ }
+ else
+ /*0x43 is used instead of 0x3 because bit 6 should represent
+ link status of external PHY */
+ link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
+
+
+ /* If chip reports that link is failed it could be because external
+ PHY link status pin is not connected correctly to chip
+ To be sure ask PHY too.
+ */
+
+ /* need a dummy read because of PHY's register latch*/
+ dmfe_phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
+ link_ok_phy = (dmfe_phy_read (db->ioaddr,
+ db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
+
+ if (link_ok_phy != link_ok) {
+ DMFE_DBUG (0, "PHY and chip report different link status", 0);
+ link_ok = link_ok | link_ok_phy;
+ }
+
+ if ( !link_ok && netif_carrier_ok(dev)) {
+ /* Link Failed */
+ DMFE_DBUG(0, "Link Failed", tmp_cr12);
+ netif_carrier_off(dev);
+
+ /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
+ /* AUTO or force 1M Homerun/Longrun don't need */
+ if ( !(db->media_mode & 0x38) )
+ dmfe_phy_write(db->ioaddr, db->phy_addr,
+ 0, 0x1000, db->chip_id);
+
+ /* AUTO mode, if INT phyxcer link failed, select EXT device */
+ if (db->media_mode & DMFE_AUTO) {
+ /* 10/100M link failed, used 1M Home-Net */
+ db->cr6_data|=0x00040000; /* bit18=1, MII */
+ db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
+ update_cr6(db->cr6_data, ioaddr);
+ }
+ } else if (!netif_carrier_ok(dev)) {
+
+ DMFE_DBUG(0, "Link link OK", tmp_cr12);
+
+ /* Auto Sense Speed */
+ if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
+ netif_carrier_on(dev);
+ SHOW_MEDIA_TYPE(db->op_mode);
+ }
+
+ dmfe_process_mode(db);
+ }
+
+ /* HPNA remote command check */
+ if (db->HPNA_command & 0xf00) {
+ db->HPNA_timer--;
+ if (!db->HPNA_timer)
+ dmfe_HPNA_remote_cmd_chk(db);
+ }
+
+ /* Timer active again */
+ db->timer.expires = DMFE_TIMER_WUT;
+ add_timer(&db->timer);
+ spin_unlock_irqrestore(&db->lock, flags);
+}
+
+
+/*
+ * Dynamic reset the DM910X board
+ * Stop DM910X board
+ * Free Tx/Rx allocated memory
+ * Reset DM910X board
+ * Re-initialize DM910X board
+ */
+
+static void dmfe_dynamic_reset(struct net_device *dev)
+{
+ struct dmfe_board_info *db = netdev_priv(dev);
+ void __iomem *ioaddr = db->ioaddr;
+
+ DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
+
+ /* Sopt MAC controller */
+ db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
+ update_cr6(db->cr6_data, ioaddr);
+ dw32(DCR7, 0); /* Disable Interrupt */
+ dw32(DCR5, dr32(DCR5));
+
+ /* Disable upper layer interface */
+ netif_stop_queue(dev);
+
+ /* Free Rx Allocate buffer */
+ dmfe_free_rxbuffer(db);
+
+ /* system variable init */
+ db->tx_packet_cnt = 0;
+ db->tx_queue_cnt = 0;
+ db->rx_avail_cnt = 0;
+ netif_carrier_off(dev);
+ db->wait_reset = 0;
+
+ /* Re-initialize DM910X board */
+ dmfe_init_dm910x(dev);
+
+ /* Restart upper layer interface */
+ netif_wake_queue(dev);
+}
+
+
+/*
+ * free all allocated rx buffer
+ */
+
+static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
+{
+ DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
+
+ /* free allocated rx buffer */
+ while (db->rx_avail_cnt) {
+ dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
+ db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
+ db->rx_avail_cnt--;
+ }
+}
+
+
+/*
+ * Reuse the SK buffer
+ */
+
+static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
+{
+ struct rx_desc *rxptr = db->rx_insert_ptr;
+
+ if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
+ rxptr->rx_skb_ptr = skb;
+ rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb->data,
+ RX_ALLOC_SIZE, DMA_FROM_DEVICE));
+ wmb();
+ rxptr->rdes0 = cpu_to_le32(0x80000000);
+ db->rx_avail_cnt++;
+ db->rx_insert_ptr = rxptr->next_rx_desc;
+ } else
+ DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
+}
+
+
+/*
+ * Initialize transmit/Receive descriptor
+ * Using Chain structure, and allocate Tx/Rx buffer
+ */
+
+static void dmfe_descriptor_init(struct net_device *dev)
+{
+ struct dmfe_board_info *db = netdev_priv(dev);
+ void __iomem *ioaddr = db->ioaddr;
+ struct tx_desc *tmp_tx;
+ struct rx_desc *tmp_rx;
+ unsigned char *tmp_buf;
+ dma_addr_t tmp_tx_dma, tmp_rx_dma;
+ dma_addr_t tmp_buf_dma;
+ int i;
+
+ DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
+
+ /* tx descriptor start pointer */
+ db->tx_insert_ptr = db->first_tx_desc;
+ db->tx_remove_ptr = db->first_tx_desc;
+ dw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
+
+ /* rx descriptor start pointer */
+ db->first_rx_desc = (void *)db->first_tx_desc +
+ sizeof(struct tx_desc) * TX_DESC_CNT;
+
+ db->first_rx_desc_dma = db->first_tx_desc_dma +
+ sizeof(struct tx_desc) * TX_DESC_CNT;
+ db->rx_insert_ptr = db->first_rx_desc;
+ db->rx_ready_ptr = db->first_rx_desc;
+ dw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
+
+ /* Init Transmit chain */
+ tmp_buf = db->buf_pool_start;
+ tmp_buf_dma = db->buf_pool_dma_start;
+ tmp_tx_dma = db->first_tx_desc_dma;
+ for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
+ tmp_tx->tx_buf_ptr = tmp_buf;
+ tmp_tx->tdes0 = cpu_to_le32(0);
+ tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
+ tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
+ tmp_tx_dma += sizeof(struct tx_desc);
+ tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
+ tmp_tx->next_tx_desc = tmp_tx + 1;
+ tmp_buf = tmp_buf + TX_BUF_ALLOC;
+ tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
+ }
+ (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
+ tmp_tx->next_tx_desc = db->first_tx_desc;
+
+ /* Init Receive descriptor chain */
+ tmp_rx_dma=db->first_rx_desc_dma;
+ for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
+ tmp_rx->rdes0 = cpu_to_le32(0);
+ tmp_rx->rdes1 = cpu_to_le32(0x01000600);
+ tmp_rx_dma += sizeof(struct rx_desc);
+ tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
+ tmp_rx->next_rx_desc = tmp_rx + 1;
+ }
+ (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
+ tmp_rx->next_rx_desc = db->first_rx_desc;
+
+ /* pre-allocate Rx buffer */
+ allocate_rx_buffer(dev);
+}
+
+
+/*
+ * Update CR6 value
+ * Firstly stop DM910X , then written value and start
+ */
+
+static void update_cr6(u32 cr6_data, void __iomem *ioaddr)
+{
+ u32 cr6_tmp;
+
+ cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
+ dw32(DCR6, cr6_tmp);
+ udelay(5);
+ dw32(DCR6, cr6_data);
+ udelay(5);
+}
+
+
+/*
+ * Send a setup frame for DM9132
+ * This setup frame initialize DM910X address filter mode
+*/
+
+static void dm9132_id_table(struct net_device *dev)
+{
+ const u16 *addrptr = (const u16 *)dev->dev_addr;
+ struct dmfe_board_info *db = netdev_priv(dev);
+ void __iomem *ioaddr = db->ioaddr + 0xc0;
+ struct netdev_hw_addr *ha;
+ u16 i, hash_table[4];
+
+ /* Node address */
+ for (i = 0; i < 3; i++) {
+ dw16(0, addrptr[i]);
+ ioaddr += 4;
+ }
+
+ /* Clear Hash Table */
+ memset(hash_table, 0, sizeof(hash_table));
+
+ /* broadcast address */
+ hash_table[3] = 0x8000;
+
+ /* the multicast address in Hash Table : 64 bits */
+ netdev_for_each_mc_addr(ha, dev) {
+ u32 hash_val = cal_CRC((char *)ha->addr, 6, 0) & 0x3f;
+
+ hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
+ }
+
+ /* Write the hash table to MAC MD table */
+ for (i = 0; i < 4; i++, ioaddr += 4)
+ dw16(0, hash_table[i]);
+}
+
+
+/*
+ * Send a setup frame for DM9102/DM9102A
+ * This setup frame initialize DM910X address filter mode
+ */
+
+static void send_filter_frame(struct net_device *dev)
+{
+ struct dmfe_board_info *db = netdev_priv(dev);
+ struct netdev_hw_addr *ha;
+ struct tx_desc *txptr;
+ const u16 * addrptr;
+ u32 * suptr;
+ int i;
+
+ DMFE_DBUG(0, "send_filter_frame()", 0);
+
+ txptr = db->tx_insert_ptr;
+ suptr = (u32 *) txptr->tx_buf_ptr;
+
+ /* Node address */
+ addrptr = (const u16 *) dev->dev_addr;
+ *suptr++ = addrptr[0];
+ *suptr++ = addrptr[1];
+ *suptr++ = addrptr[2];
+
+ /* broadcast address */
+ *suptr++ = 0xffff;
+ *suptr++ = 0xffff;
+ *suptr++ = 0xffff;
+
+ /* fit the multicast address */
+ netdev_for_each_mc_addr(ha, dev) {
+ addrptr = (u16 *) ha->addr;
+ *suptr++ = addrptr[0];
+ *suptr++ = addrptr[1];
+ *suptr++ = addrptr[2];
+ }
+
+ for (i = netdev_mc_count(dev); i < 14; i++) {
+ *suptr++ = 0xffff;
+ *suptr++ = 0xffff;
+ *suptr++ = 0xffff;
+ }
+
+ /* prepare the setup frame */
+ db->tx_insert_ptr = txptr->next_tx_desc;
+ txptr->tdes1 = cpu_to_le32(0x890000c0);
+
+ /* Resource Check and Send the setup packet */
+ if (!db->tx_packet_cnt) {
+ void __iomem *ioaddr = db->ioaddr;
+
+ /* Resource Empty */
+ db->tx_packet_cnt++;
+ txptr->tdes0 = cpu_to_le32(0x80000000);
+ update_cr6(db->cr6_data | 0x2000, ioaddr);
+ dw32(DCR1, 0x1); /* Issue Tx polling */
+ update_cr6(db->cr6_data, ioaddr);
+ netif_trans_update(dev);
+ } else
+ db->tx_queue_cnt++; /* Put in TX queue */
+}
+
+
+/*
+ * Allocate rx buffer,
+ * As possible as allocate maxiumn Rx buffer
+ */
+
+static void allocate_rx_buffer(struct net_device *dev)
+{
+ struct dmfe_board_info *db = netdev_priv(dev);
+ struct rx_desc *rxptr;
+ struct sk_buff *skb;
+
+ rxptr = db->rx_insert_ptr;
+
+ while(db->rx_avail_cnt < RX_DESC_CNT) {
+ if ( ( skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE) ) == NULL )
+ break;
+ rxptr->rx_skb_ptr = skb; /* FIXME (?) */
+ rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb->data,
+ RX_ALLOC_SIZE, DMA_FROM_DEVICE));
+ wmb();
+ rxptr->rdes0 = cpu_to_le32(0x80000000);
+ rxptr = rxptr->next_rx_desc;
+ db->rx_avail_cnt++;
+ }
+
+ db->rx_insert_ptr = rxptr;
+}
+
+static void srom_clk_write(void __iomem *ioaddr, u32 data)
+{
+ static const u32 cmd[] = {
+ CR9_SROM_READ | CR9_SRCS,
+ CR9_SROM_READ | CR9_SRCS | CR9_SRCLK,
+ CR9_SROM_READ | CR9_SRCS
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(cmd); i++) {
+ dw32(DCR9, data | cmd[i]);
+ udelay(5);
+ }
+}
+
+/*
+ * Read one word data from the serial ROM
+ */
+static u16 read_srom_word(void __iomem *ioaddr, int offset)
+{
+ u16 srom_data;
+ int i;
+
+ dw32(DCR9, CR9_SROM_READ);
+ udelay(5);
+ dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
+ udelay(5);
+
+ /* Send the Read Command 110b */
+ srom_clk_write(ioaddr, SROM_DATA_1);
+ srom_clk_write(ioaddr, SROM_DATA_1);
+ srom_clk_write(ioaddr, SROM_DATA_0);
+
+ /* Send the offset */
+ for (i = 5; i >= 0; i--) {
+ srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
+ srom_clk_write(ioaddr, srom_data);
+ }
+
+ dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
+ udelay(5);
+
+ for (i = 16; i > 0; i--) {
+ dw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
+ udelay(5);
+ srom_data = (srom_data << 1) |
+ ((dr32(DCR9) & CR9_CRDOUT) ? 1 : 0);
+ dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
+ udelay(5);
+ }
+
+ dw32(DCR9, CR9_SROM_READ);
+ udelay(5);
+ return srom_data;
+}
+
+
+/*
+ * Auto sense the media mode
+ */
+
+static u8 dmfe_sense_speed(struct dmfe_board_info *db)
+{
+ void __iomem *ioaddr = db->ioaddr;
+ u8 ErrFlag = 0;
+ u16 phy_mode;
+
+ /* CR6 bit18=0, select 10/100M */
+ update_cr6(db->cr6_data & ~0x40000, ioaddr);
+
+ phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
+ phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
+
+ if ( (phy_mode & 0x24) == 0x24 ) {
+ if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
+ phy_mode = dmfe_phy_read(db->ioaddr,
+ db->phy_addr, 7, db->chip_id) & 0xf000;
+ else /* DM9102/DM9102A */
+ phy_mode = dmfe_phy_read(db->ioaddr,
+ db->phy_addr, 17, db->chip_id) & 0xf000;
+ switch (phy_mode) {
+ case 0x1000: db->op_mode = DMFE_10MHF; break;
+ case 0x2000: db->op_mode = DMFE_10MFD; break;
+ case 0x4000: db->op_mode = DMFE_100MHF; break;
+ case 0x8000: db->op_mode = DMFE_100MFD; break;
+ default: db->op_mode = DMFE_10MHF;
+ ErrFlag = 1;
+ break;
+ }
+ } else {
+ db->op_mode = DMFE_10MHF;
+ DMFE_DBUG(0, "Link Failed :", phy_mode);
+ ErrFlag = 1;
+ }
+
+ return ErrFlag;
+}
+
+
+/*
+ * Set 10/100 phyxcer capability
+ * AUTO mode : phyxcer register4 is NIC capability
+ * Force mode: phyxcer register4 is the force media
+ */
+
+static void dmfe_set_phyxcer(struct dmfe_board_info *db)
+{
+ void __iomem *ioaddr = db->ioaddr;
+ u16 phy_reg;
+
+ /* Select 10/100M phyxcer */
+ db->cr6_data &= ~0x40000;
+ update_cr6(db->cr6_data, ioaddr);
+
+ /* DM9009 Chip: Phyxcer reg18 bit12=0 */
+ if (db->chip_id == PCI_DM9009_ID) {
+ phy_reg = dmfe_phy_read(db->ioaddr,
+ db->phy_addr, 18, db->chip_id) & ~0x1000;
+
+ dmfe_phy_write(db->ioaddr,
+ db->phy_addr, 18, phy_reg, db->chip_id);
+ }
+
+ /* Phyxcer capability setting */
+ phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
+
+ if (db->media_mode & DMFE_AUTO) {
+ /* AUTO Mode */
+ phy_reg |= db->PHY_reg4;
+ } else {
+ /* Force Mode */
+ switch(db->media_mode) {
+ case DMFE_10MHF: phy_reg |= 0x20; break;
+ case DMFE_10MFD: phy_reg |= 0x40; break;
+ case DMFE_100MHF: phy_reg |= 0x80; break;
+ case DMFE_100MFD: phy_reg |= 0x100; break;
+ }
+ if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
+ }
+
+ /* Write new capability to Phyxcer Reg4 */
+ if ( !(phy_reg & 0x01e0)) {
+ phy_reg|=db->PHY_reg4;
+ db->media_mode|=DMFE_AUTO;
+ }
+ dmfe_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
+
+ /* Restart Auto-Negotiation */
+ if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
+ dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
+ if ( !db->chip_type )
+ dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
+}
+
+
+/*
+ * Process op-mode
+ * AUTO mode : PHY controller in Auto-negotiation Mode
+ * Force mode: PHY controller in force mode with HUB
+ * N-way force capability with SWITCH
+ */
+
+static void dmfe_process_mode(struct dmfe_board_info *db)
+{
+ u16 phy_reg;
+
+ /* Full Duplex Mode Check */
+ if (db->op_mode & 0x4)
+ db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
+ else
+ db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
+
+ /* Transciver Selection */
+ if (db->op_mode & 0x10) /* 1M HomePNA */
+ db->cr6_data |= 0x40000;/* External MII select */
+ else
+ db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
+
+ update_cr6(db->cr6_data, db->ioaddr);
+
+ /* 10/100M phyxcer force mode need */
+ if ( !(db->media_mode & 0x18)) {
+ /* Forece Mode */
+ phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
+ if ( !(phy_reg & 0x1) ) {
+ /* parter without N-Way capability */
+ phy_reg = 0x0;
+ switch(db->op_mode) {
+ case DMFE_10MHF: phy_reg = 0x0; break;
+ case DMFE_10MFD: phy_reg = 0x100; break;
+ case DMFE_100MHF: phy_reg = 0x2000; break;
+ case DMFE_100MFD: phy_reg = 0x2100; break;
+ }
+ dmfe_phy_write(db->ioaddr,
+ db->phy_addr, 0, phy_reg, db->chip_id);
+ if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
+ mdelay(20);
+ dmfe_phy_write(db->ioaddr,
+ db->phy_addr, 0, phy_reg, db->chip_id);
+ }
+ }
+}
+
+
+/*
+ * Write a word to Phy register
+ */
+
+static void dmfe_phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
+ u16 phy_data, u32 chip_id)
+{
+ u16 i;
+
+ if (chip_id == PCI_DM9132_ID) {
+ dw16(0x80 + offset * 4, phy_data);
+ } else {
+ /* DM9102/DM9102A Chip */
+
+ /* Send 33 synchronization clock to Phy controller */
+ for (i = 0; i < 35; i++)
+ dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
+
+ /* Send start command(01) to Phy */
+ dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
+ dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
+
+ /* Send write command(01) to Phy */
+ dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
+ dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
+
+ /* Send Phy address */
+ for (i = 0x10; i > 0; i = i >> 1)
+ dmfe_phy_write_1bit(ioaddr,
+ phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
+
+ /* Send register address */
+ for (i = 0x10; i > 0; i = i >> 1)
+ dmfe_phy_write_1bit(ioaddr,
+ offset & i ? PHY_DATA_1 : PHY_DATA_0);
+
+ /* written trasnition */
+ dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
+ dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
+
+ /* Write a word data to PHY controller */
+ for ( i = 0x8000; i > 0; i >>= 1)
+ dmfe_phy_write_1bit(ioaddr,
+ phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
+ }
+}
+
+
+/*
+ * Read a word data from phy register
+ */
+
+static u16 dmfe_phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
+{
+ int i;
+ u16 phy_data;
+
+ if (chip_id == PCI_DM9132_ID) {
+ /* DM9132 Chip */
+ phy_data = dr16(0x80 + offset * 4);
+ } else {
+ /* DM9102/DM9102A Chip */
+
+ /* Send 33 synchronization clock to Phy controller */
+ for (i = 0; i < 35; i++)
+ dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
+
+ /* Send start command(01) to Phy */
+ dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
+ dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
+
+ /* Send read command(10) to Phy */
+ dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
+ dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
+
+ /* Send Phy address */
+ for (i = 0x10; i > 0; i = i >> 1)
+ dmfe_phy_write_1bit(ioaddr,
+ phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
+
+ /* Send register address */
+ for (i = 0x10; i > 0; i = i >> 1)
+ dmfe_phy_write_1bit(ioaddr,
+ offset & i ? PHY_DATA_1 : PHY_DATA_0);
+
+ /* Skip transition state */
+ dmfe_phy_read_1bit(ioaddr);
+
+ /* read 16bit data */
+ for (phy_data = 0, i = 0; i < 16; i++) {
+ phy_data <<= 1;
+ phy_data |= dmfe_phy_read_1bit(ioaddr);
+ }
+ }
+
+ return phy_data;
+}
+
+
+/*
+ * Write one bit data to Phy Controller
+ */
+
+static void dmfe_phy_write_1bit(void __iomem *ioaddr, u32 phy_data)
+{
+ dw32(DCR9, phy_data); /* MII Clock Low */
+ udelay(1);
+ dw32(DCR9, phy_data | MDCLKH); /* MII Clock High */
+ udelay(1);
+ dw32(DCR9, phy_data); /* MII Clock Low */
+ udelay(1);
+}
+
+
+/*
+ * Read one bit phy data from PHY controller
+ */
+
+static u16 dmfe_phy_read_1bit(void __iomem *ioaddr)
+{
+ u16 phy_data;
+
+ dw32(DCR9, 0x50000);
+ udelay(1);
+ phy_data = (dr32(DCR9) >> 19) & 0x1;
+ dw32(DCR9, 0x40000);
+ udelay(1);
+
+ return phy_data;
+}
+
+
+/*
+ * Parser SROM and media mode
+ */
+
+static void dmfe_parse_srom(struct dmfe_board_info * db)
+{
+ char * srom = db->srom;
+ int dmfe_mode, tmp_reg;
+
+ DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
+
+ /* Init CR15 */
+ db->cr15_data = CR15_DEFAULT;
+
+ /* Check SROM Version */
+ if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
+ /* SROM V4.01 */
+ /* Get NIC support media mode */
+ db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
+ db->PHY_reg4 = 0;
+ for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
+ switch( db->NIC_capability & tmp_reg ) {
+ case 0x1: db->PHY_reg4 |= 0x0020; break;
+ case 0x2: db->PHY_reg4 |= 0x0040; break;
+ case 0x4: db->PHY_reg4 |= 0x0080; break;
+ case 0x8: db->PHY_reg4 |= 0x0100; break;
+ }
+ }
+
+ /* Media Mode Force or not check */
+ dmfe_mode = (le32_to_cpup((__le32 *) (srom + 34)) &
+ le32_to_cpup((__le32 *) (srom + 36)));
+ switch(dmfe_mode) {
+ case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
+ case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
+ case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
+ case 0x100:
+ case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
+ }
+
+ /* Special Function setting */
+ /* VLAN function */
+ if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
+ db->cr15_data |= 0x40;
+
+ /* Flow Control */
+ if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
+ db->cr15_data |= 0x400;
+
+ /* TX pause packet */
+ if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
+ db->cr15_data |= 0x9800;
+ }
+
+ /* Parse HPNA parameter */
+ db->HPNA_command = 1;
+
+ /* Accept remote command or not */
+ if (HPNA_rx_cmd == 0)
+ db->HPNA_command |= 0x8000;
+
+ /* Issue remote command & operation mode */
+ if (HPNA_tx_cmd == 1)
+ switch(HPNA_mode) { /* Issue Remote Command */
+ case 0: db->HPNA_command |= 0x0904; break;
+ case 1: db->HPNA_command |= 0x0a00; break;
+ case 2: db->HPNA_command |= 0x0506; break;
+ case 3: db->HPNA_command |= 0x0602; break;
+ }
+ else
+ switch(HPNA_mode) { /* Don't Issue */
+ case 0: db->HPNA_command |= 0x0004; break;
+ case 1: db->HPNA_command |= 0x0000; break;
+ case 2: db->HPNA_command |= 0x0006; break;
+ case 3: db->HPNA_command |= 0x0002; break;
+ }
+
+ /* Check DM9801 or DM9802 present or not */
+ db->HPNA_present = 0;
+ update_cr6(db->cr6_data | 0x40000, db->ioaddr);
+ tmp_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
+ if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
+ /* DM9801 or DM9802 present */
+ db->HPNA_timer = 8;
+ if ( dmfe_phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
+ /* DM9801 HomeRun */
+ db->HPNA_present = 1;
+ dmfe_program_DM9801(db, tmp_reg);
+ } else {
+ /* DM9802 LongRun */
+ db->HPNA_present = 2;
+ dmfe_program_DM9802(db);
+ }
+ }
+
+}
+
+
+/*
+ * Init HomeRun DM9801
+ */
+
+static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
+{
+ uint reg17, reg25;
+
+ if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
+ switch(HPNA_rev) {
+ case 0xb900: /* DM9801 E3 */
+ db->HPNA_command |= 0x1000;
+ reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
+ reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
+ reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
+ break;
+ case 0xb901: /* DM9801 E4 */
+ reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
+ reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
+ reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
+ reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
+ break;
+ case 0xb902: /* DM9801 E5 */
+ case 0xb903: /* DM9801 E6 */
+ default:
+ db->HPNA_command |= 0x1000;
+ reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
+ reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
+ reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
+ reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
+ break;
+ }
+ dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
+ dmfe_phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
+ dmfe_phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
+}
+
+
+/*
+ * Init HomeRun DM9802
+ */
+
+static void dmfe_program_DM9802(struct dmfe_board_info * db)
+{
+ uint phy_reg;
+
+ if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
+ dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
+ phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
+ phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
+ dmfe_phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
+}
+
+
+/*
+ * Check remote HPNA power and speed status. If not correct,
+ * issue command again.
+*/
+
+static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
+{
+ uint phy_reg;
+
+ /* Got remote device status */
+ phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
+ switch(phy_reg) {
+ case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
+ case 0x20: phy_reg = 0x0900;break; /* LP/HS */
+ case 0x40: phy_reg = 0x0600;break; /* HP/LS */
+ case 0x60: phy_reg = 0x0500;break; /* HP/HS */
+ }
+
+ /* Check remote device status match our setting ot not */
+ if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
+ dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
+ db->chip_id);
+ db->HPNA_timer=8;
+ } else
+ db->HPNA_timer=600; /* Match, every 10 minutes, check */
+}
+
+
+
+static const struct pci_device_id dmfe_pci_tbl[] = {
+ { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
+ { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
+ { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
+ { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
+ { 0, }
+};
+MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
+
+static int __maybe_unused dmfe_suspend(struct device *dev_d)
+{
+ struct net_device *dev = dev_get_drvdata(dev_d);
+ struct dmfe_board_info *db = netdev_priv(dev);
+ void __iomem *ioaddr = db->ioaddr;
+
+ /* Disable upper layer interface */
+ netif_device_detach(dev);
+
+ /* Disable Tx/Rx */
+ db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
+ update_cr6(db->cr6_data, ioaddr);
+
+ /* Disable Interrupt */
+ dw32(DCR7, 0);
+ dw32(DCR5, dr32(DCR5));
+
+ /* Fre RX buffers */
+ dmfe_free_rxbuffer(db);
+
+ /* Enable WOL */
+ device_wakeup_enable(dev_d);
+
+ return 0;
+}
+
+static int __maybe_unused dmfe_resume(struct device *dev_d)
+{
+ struct net_device *dev = dev_get_drvdata(dev_d);
+
+ /* Re-initialize DM910X board */
+ dmfe_init_dm910x(dev);
+
+ /* Disable WOL */
+ device_wakeup_disable(dev_d);
+
+ /* Restart upper layer interface */
+ netif_device_attach(dev);
+
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(dmfe_pm_ops, dmfe_suspend, dmfe_resume);
+
+static struct pci_driver dmfe_driver = {
+ .name = "dmfe",
+ .id_table = dmfe_pci_tbl,
+ .probe = dmfe_init_one,
+ .remove = dmfe_remove_one,
+ .driver.pm = &dmfe_pm_ops,
+};
+
+MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
+MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
+MODULE_LICENSE("GPL");
+
+module_param(debug, int, 0);
+module_param(mode, byte, 0);
+module_param(cr6set, int, 0);
+module_param(chkmode, byte, 0);
+module_param(HPNA_mode, byte, 0);
+module_param(HPNA_rx_cmd, byte, 0);
+module_param(HPNA_tx_cmd, byte, 0);
+module_param(HPNA_NoiseFloor, byte, 0);
+module_param(SF_mode, byte, 0);
+MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
+MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
+ "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
+
+MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
+ "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
+
+/* Description:
+ * when user used insmod to add module, system invoked init_module()
+ * to initialize and register.
+ */
+
+static int __init dmfe_init_module(void)
+{
+ int rc;
+
+ DMFE_DBUG(0, "init_module() ", debug);
+
+ if (debug)
+ dmfe_debug = debug; /* set debug flag */
+ if (cr6set)
+ dmfe_cr6_user_set = cr6set;
+
+ switch (mode) {
+ case DMFE_10MHF:
+ case DMFE_100MHF:
+ case DMFE_10MFD:
+ case DMFE_100MFD:
+ case DMFE_1M_HPNA:
+ dmfe_media_mode = mode;
+ break;
+ default:
+ dmfe_media_mode = DMFE_AUTO;
+ break;
+ }
+
+ if (HPNA_mode > 4)
+ HPNA_mode = 0; /* Default: LP/HS */
+ if (HPNA_rx_cmd > 1)
+ HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
+ if (HPNA_tx_cmd > 1)
+ HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
+ if (HPNA_NoiseFloor > 15)
+ HPNA_NoiseFloor = 0;
+
+ rc = pci_register_driver(&dmfe_driver);
+ if (rc < 0)
+ return rc;
+
+ return 0;
+}
+
+
+/*
+ * Description:
+ * when user used rmmod to delete module, system invoked clean_module()
+ * to un-register all registered services.
+ */
+
+static void __exit dmfe_cleanup_module(void)
+{
+ DMFE_DBUG(0, "dmfe_cleanup_module() ", debug);
+ pci_unregister_driver(&dmfe_driver);
+}
+
+module_init(dmfe_init_module);
+module_exit(dmfe_cleanup_module);
diff --git a/drivers/net/ethernet/dec/tulip/eeprom.c b/drivers/net/ethernet/dec/tulip/eeprom.c
new file mode 100644
index 000000000..d5657ff15
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/eeprom.c
@@ -0,0 +1,381 @@
+/*
+ drivers/net/ethernet/dec/tulip/eeprom.c
+
+ Copyright 2000,2001 The Linux Kernel Team
+ Written/copyright 1994-2001 by Donald Becker.
+
+ This software may be used and distributed according to the terms
+ of the GNU General Public License, incorporated herein by reference.
+
+ Please submit bug reports to http://bugzilla.kernel.org/.
+*/
+
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include "tulip.h"
+#include <asm/unaligned.h>
+
+
+
+/* Serial EEPROM section. */
+/* The main routine to parse the very complicated SROM structure.
+ Search www.digital.com for "21X4 SROM" to get details.
+ This code is very complex, and will require changes to support
+ additional cards, so I'll be verbose about what is going on.
+ */
+
+/* Known cards that have old-style EEPROMs. */
+static struct eeprom_fixup eeprom_fixups[] = {
+ {"Asante", 0, 0, 0x94, {0x1e00, 0x0000, 0x0800, 0x0100, 0x018c,
+ 0x0000, 0x0000, 0xe078, 0x0001, 0x0050, 0x0018 }},
+ {"SMC9332DST", 0, 0, 0xC0, { 0x1e00, 0x0000, 0x0800, 0x041f,
+ 0x0000, 0x009E, /* 10baseT */
+ 0x0004, 0x009E, /* 10baseT-FD */
+ 0x0903, 0x006D, /* 100baseTx */
+ 0x0905, 0x006D, /* 100baseTx-FD */ }},
+ {"Cogent EM100", 0, 0, 0x92, { 0x1e00, 0x0000, 0x0800, 0x063f,
+ 0x0107, 0x8021, /* 100baseFx */
+ 0x0108, 0x8021, /* 100baseFx-FD */
+ 0x0100, 0x009E, /* 10baseT */
+ 0x0104, 0x009E, /* 10baseT-FD */
+ 0x0103, 0x006D, /* 100baseTx */
+ 0x0105, 0x006D, /* 100baseTx-FD */ }},
+ {"Maxtech NX-110", 0, 0, 0xE8, { 0x1e00, 0x0000, 0x0800, 0x0513,
+ 0x1001, 0x009E, /* 10base2, CSR12 0x10*/
+ 0x0000, 0x009E, /* 10baseT */
+ 0x0004, 0x009E, /* 10baseT-FD */
+ 0x0303, 0x006D, /* 100baseTx, CSR12 0x03 */
+ 0x0305, 0x006D, /* 100baseTx-FD CSR12 0x03 */}},
+ {"Accton EN1207", 0, 0, 0xE8, { 0x1e00, 0x0000, 0x0800, 0x051F,
+ 0x1B01, 0x0000, /* 10base2, CSR12 0x1B */
+ 0x0B00, 0x009E, /* 10baseT, CSR12 0x0B */
+ 0x0B04, 0x009E, /* 10baseT-FD,CSR12 0x0B */
+ 0x1B03, 0x006D, /* 100baseTx, CSR12 0x1B */
+ 0x1B05, 0x006D, /* 100baseTx-FD CSR12 0x1B */
+ }},
+ {"NetWinder", 0x00, 0x10, 0x57,
+ /* Default media = MII
+ * MII block, reset sequence (3) = 0x0821 0x0000 0x0001, capabilities 0x01e1
+ */
+ { 0x1e00, 0x0000, 0x000b, 0x8f01, 0x0103, 0x0300, 0x0821, 0x000, 0x0001, 0x0000, 0x01e1 }
+ },
+ {"Cobalt Microserver", 0, 0x10, 0xE0, {0x1e00, /* 0 == controller #, 1e == offset */
+ 0x0000, /* 0 == high offset, 0 == gap */
+ 0x0800, /* Default Autoselect */
+ 0x8001, /* 1 leaf, extended type, bogus len */
+ 0x0003, /* Type 3 (MII), PHY #0 */
+ 0x0400, /* 0 init instr, 4 reset instr */
+ 0x0801, /* Set control mode, GP0 output */
+ 0x0000, /* Drive GP0 Low (RST is active low) */
+ 0x0800, /* control mode, GP0 input (undriven) */
+ 0x0000, /* clear control mode */
+ 0x7800, /* 100TX FDX + HDX, 10bT FDX + HDX */
+ 0x01e0, /* Advertise all above */
+ 0x5000, /* FDX all above */
+ 0x1800, /* Set fast TTM in 100bt modes */
+ 0x0000, /* PHY cannot be unplugged */
+ }},
+ {NULL}};
+
+
+static const char *const block_name[] = {
+ "21140 non-MII",
+ "21140 MII PHY",
+ "21142 Serial PHY",
+ "21142 MII PHY",
+ "21143 SYM PHY",
+ "21143 reset method"
+};
+
+
+/**
+ * tulip_build_fake_mediatable - Build a fake mediatable entry.
+ * @tp: Ptr to the tulip private data.
+ *
+ * Some cards like the 3x5 HSC cards (J3514A) do not have a standard
+ * srom and can not be handled under the fixup routine. These cards
+ * still need a valid mediatable entry for correct csr12 setup and
+ * mii handling.
+ *
+ * Since this is currently a parisc-linux specific function, the
+ * #ifdef __hppa__ should completely optimize this function away for
+ * non-parisc hardware.
+ */
+static void tulip_build_fake_mediatable(struct tulip_private *tp)
+{
+#ifdef CONFIG_GSC
+ if (tp->flags & NEEDS_FAKE_MEDIA_TABLE) {
+ static unsigned char leafdata[] =
+ { 0x01, /* phy number */
+ 0x02, /* gpr setup sequence length */
+ 0x02, 0x00, /* gpr setup sequence */
+ 0x02, /* phy reset sequence length */
+ 0x01, 0x00, /* phy reset sequence */
+ 0x00, 0x78, /* media capabilities */
+ 0x00, 0xe0, /* nway advertisement */
+ 0x00, 0x05, /* fdx bit map */
+ 0x00, 0x06 /* ttm bit map */
+ };
+
+ tp->mtable = devm_kmalloc(&tp->pdev->dev, sizeof(struct mediatable) +
+ sizeof(struct medialeaf), GFP_KERNEL);
+
+ if (tp->mtable == NULL)
+ return; /* Horrible, impossible failure. */
+
+ tp->mtable->defaultmedia = 0x800;
+ tp->mtable->leafcount = 1;
+ tp->mtable->csr12dir = 0x3f; /* inputs on bit7 for hsc-pci, bit6 for pci-fx */
+ tp->mtable->has_nonmii = 0;
+ tp->mtable->has_reset = 0;
+ tp->mtable->has_mii = 1;
+ tp->mtable->csr15dir = tp->mtable->csr15val = 0;
+ tp->mtable->mleaf[0].type = 1;
+ tp->mtable->mleaf[0].media = 11;
+ tp->mtable->mleaf[0].leafdata = &leafdata[0];
+ tp->flags |= HAS_PHY_IRQ;
+ tp->csr12_shadow = -1;
+ }
+#endif
+}
+
+void tulip_parse_eeprom(struct net_device *dev)
+{
+ /*
+ dev is not registered at this point, so logging messages can't
+ use dev_<level> or netdev_<level> but dev->name is good via a
+ hack in the caller
+ */
+
+ /* The last media info list parsed, for multiport boards. */
+ static struct mediatable *last_mediatable;
+ static unsigned char *last_ee_data;
+ static int controller_index;
+ struct tulip_private *tp = netdev_priv(dev);
+ unsigned char *ee_data = tp->eeprom;
+ int i;
+
+ tp->mtable = NULL;
+ /* Detect an old-style (SA only) EEPROM layout:
+ memcmp(eedata, eedata+16, 8). */
+ for (i = 0; i < 8; i ++)
+ if (ee_data[i] != ee_data[16+i])
+ break;
+ if (i >= 8) {
+ if (ee_data[0] == 0xff) {
+ if (last_mediatable) {
+ controller_index++;
+ pr_info("%s: Controller %d of multiport board\n",
+ dev->name, controller_index);
+ tp->mtable = last_mediatable;
+ ee_data = last_ee_data;
+ goto subsequent_board;
+ } else
+ pr_info("%s: Missing EEPROM, this interface may not work correctly!\n",
+ dev->name);
+ return;
+ }
+ /* Do a fix-up based on the vendor half of the station address prefix. */
+ for (i = 0; eeprom_fixups[i].name; i++) {
+ if (dev->dev_addr[0] == eeprom_fixups[i].addr0 &&
+ dev->dev_addr[1] == eeprom_fixups[i].addr1 &&
+ dev->dev_addr[2] == eeprom_fixups[i].addr2) {
+ if (dev->dev_addr[2] == 0xE8 && ee_data[0x1a] == 0x55)
+ i++; /* An Accton EN1207, not an outlaw Maxtech. */
+ memcpy(ee_data + 26, eeprom_fixups[i].newtable,
+ sizeof(eeprom_fixups[i].newtable));
+ pr_info("%s: Old format EEPROM on '%s' board. Using substitute media control info\n",
+ dev->name, eeprom_fixups[i].name);
+ break;
+ }
+ }
+ if (eeprom_fixups[i].name == NULL) { /* No fixup found. */
+ pr_info("%s: Old style EEPROM with no media selection information\n",
+ dev->name);
+ return;
+ }
+ }
+
+ controller_index = 0;
+ if (ee_data[19] > 1) { /* Multiport board. */
+ last_ee_data = ee_data;
+ }
+subsequent_board:
+
+ if (ee_data[27] == 0) { /* No valid media table. */
+ tulip_build_fake_mediatable(tp);
+ } else {
+ unsigned char *p = (void *)ee_data + ee_data[27];
+ unsigned char csr12dir = 0;
+ int count, new_advertise = 0;
+ struct mediatable *mtable;
+ u16 media = get_u16(p);
+
+ p += 2;
+ if (tp->flags & CSR12_IN_SROM)
+ csr12dir = *p++;
+ count = *p++;
+
+ /* there is no phy information, don't even try to build mtable */
+ if (count == 0) {
+ if (tulip_debug > 0)
+ pr_warn("%s: no phy info, aborting mtable build\n",
+ dev->name);
+ return;
+ }
+
+ mtable = devm_kmalloc(&tp->pdev->dev, struct_size(mtable, mleaf, count),
+ GFP_KERNEL);
+ if (mtable == NULL)
+ return; /* Horrible, impossible failure. */
+ last_mediatable = tp->mtable = mtable;
+ mtable->defaultmedia = media;
+ mtable->leafcount = count;
+ mtable->csr12dir = csr12dir;
+ mtable->has_nonmii = mtable->has_mii = mtable->has_reset = 0;
+ mtable->csr15dir = mtable->csr15val = 0;
+
+ pr_info("%s: EEPROM default media type %s\n",
+ dev->name,
+ media & 0x0800 ? "Autosense"
+ : medianame[media & MEDIA_MASK]);
+ for (i = 0; i < count; i++) {
+ struct medialeaf *leaf = &mtable->mleaf[i];
+
+ if ((p[0] & 0x80) == 0) { /* 21140 Compact block. */
+ leaf->type = 0;
+ leaf->media = p[0] & 0x3f;
+ leaf->leafdata = p;
+ if ((p[2] & 0x61) == 0x01) /* Bogus, but Znyx boards do it. */
+ mtable->has_mii = 1;
+ p += 4;
+ } else {
+ leaf->type = p[1];
+ if (p[1] == 0x05) {
+ mtable->has_reset = i;
+ leaf->media = p[2] & 0x0f;
+ } else if (tp->chip_id == DM910X && p[1] == 0x80) {
+ /* Hack to ignore Davicom delay period block */
+ mtable->leafcount--;
+ count--;
+ i--;
+ leaf->leafdata = p + 2;
+ p += (p[0] & 0x3f) + 1;
+ continue;
+ } else if (p[1] & 1) {
+ int gpr_len, reset_len;
+
+ mtable->has_mii = 1;
+ leaf->media = 11;
+ gpr_len=p[3]*2;
+ reset_len=p[4+gpr_len]*2;
+ new_advertise |= get_u16(&p[7+gpr_len+reset_len]);
+ } else {
+ mtable->has_nonmii = 1;
+ leaf->media = p[2] & MEDIA_MASK;
+ /* Davicom's media number for 100BaseTX is strange */
+ if (tp->chip_id == DM910X && leaf->media == 1)
+ leaf->media = 3;
+ switch (leaf->media) {
+ case 0: new_advertise |= 0x0020; break;
+ case 4: new_advertise |= 0x0040; break;
+ case 3: new_advertise |= 0x0080; break;
+ case 5: new_advertise |= 0x0100; break;
+ case 6: new_advertise |= 0x0200; break;
+ }
+ if (p[1] == 2 && leaf->media == 0) {
+ if (p[2] & 0x40) {
+ u32 base15 = get_unaligned((u16*)&p[7]);
+ mtable->csr15dir =
+ (get_unaligned((u16*)&p[9])<<16) + base15;
+ mtable->csr15val =
+ (get_unaligned((u16*)&p[11])<<16) + base15;
+ } else {
+ mtable->csr15dir = get_unaligned((u16*)&p[3])<<16;
+ mtable->csr15val = get_unaligned((u16*)&p[5])<<16;
+ }
+ }
+ }
+ leaf->leafdata = p + 2;
+ p += (p[0] & 0x3f) + 1;
+ }
+ if (tulip_debug > 1 && leaf->media == 11) {
+ unsigned char *bp = leaf->leafdata;
+ pr_info("%s: MII interface PHY %d, setup/reset sequences %d/%d long, capabilities %02x %02x\n",
+ dev->name,
+ bp[0], bp[1], bp[2 + bp[1]*2],
+ bp[5 + bp[2 + bp[1]*2]*2],
+ bp[4 + bp[2 + bp[1]*2]*2]);
+ }
+ pr_info("%s: Index #%d - Media %s (#%d) described by a %s (%d) block\n",
+ dev->name,
+ i, medianame[leaf->media & 15], leaf->media,
+ leaf->type < ARRAY_SIZE(block_name) ? block_name[leaf->type] : "<unknown>",
+ leaf->type);
+ }
+ if (new_advertise)
+ tp->sym_advertise = new_advertise;
+ }
+}
+/* Reading a serial EEPROM is a "bit" grungy, but we work our way through:->.*/
+
+/* EEPROM_Ctrl bits. */
+#define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */
+#define EE_CS 0x01 /* EEPROM chip select. */
+#define EE_DATA_WRITE 0x04 /* Data from the Tulip to EEPROM. */
+#define EE_WRITE_0 0x01
+#define EE_WRITE_1 0x05
+#define EE_DATA_READ 0x08 /* Data from the EEPROM chip. */
+#define EE_ENB (0x4800 | EE_CS)
+
+/* Delay between EEPROM clock transitions.
+ Even at 33Mhz current PCI implementations don't overrun the EEPROM clock.
+ We add a bus turn-around to insure that this remains true. */
+#define eeprom_delay() ioread32(ee_addr)
+
+/* The EEPROM commands include the alway-set leading bit. */
+#define EE_READ_CMD (6)
+
+/* Note: this routine returns extra data bits for size detection. */
+int tulip_read_eeprom(struct net_device *dev, int location, int addr_len)
+{
+ int i;
+ unsigned retval = 0;
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ee_addr = tp->base_addr + CSR9;
+ int read_cmd = location | (EE_READ_CMD << addr_len);
+
+ /* If location is past the end of what we can address, don't
+ * read some other location (ie truncate). Just return zero.
+ */
+ if (location > (1 << addr_len) - 1)
+ return 0;
+
+ iowrite32(EE_ENB & ~EE_CS, ee_addr);
+ iowrite32(EE_ENB, ee_addr);
+
+ /* Shift the read command bits out. */
+ for (i = 4 + addr_len; i >= 0; i--) {
+ short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
+ iowrite32(EE_ENB | dataval, ee_addr);
+ eeprom_delay();
+ iowrite32(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
+ eeprom_delay();
+ retval = (retval << 1) | ((ioread32(ee_addr) & EE_DATA_READ) ? 1 : 0);
+ }
+ iowrite32(EE_ENB, ee_addr);
+ eeprom_delay();
+
+ for (i = 16; i > 0; i--) {
+ iowrite32(EE_ENB | EE_SHIFT_CLK, ee_addr);
+ eeprom_delay();
+ retval = (retval << 1) | ((ioread32(ee_addr) & EE_DATA_READ) ? 1 : 0);
+ iowrite32(EE_ENB, ee_addr);
+ eeprom_delay();
+ }
+
+ /* Terminate the EEPROM access. */
+ iowrite32(EE_ENB & ~EE_CS, ee_addr);
+ return (tp->flags & HAS_SWAPPED_SEEPROM) ? swab16(retval) : retval;
+}
+
diff --git a/drivers/net/ethernet/dec/tulip/interrupt.c b/drivers/net/ethernet/dec/tulip/interrupt.c
new file mode 100644
index 000000000..54560f9a1
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/interrupt.c
@@ -0,0 +1,822 @@
+/*
+ drivers/net/ethernet/dec/tulip/interrupt.c
+
+ Copyright 2000,2001 The Linux Kernel Team
+ Written/copyright 1994-2001 by Donald Becker.
+
+ This software may be used and distributed according to the terms
+ of the GNU General Public License, incorporated herein by reference.
+
+ Please submit bugs to http://bugzilla.kernel.org/ .
+*/
+
+#include <linux/pci.h>
+#include "tulip.h"
+#include <linux/etherdevice.h>
+
+int tulip_rx_copybreak;
+unsigned int tulip_max_interrupt_work;
+
+#ifdef CONFIG_TULIP_NAPI_HW_MITIGATION
+#define MIT_SIZE 15
+#define MIT_TABLE 15 /* We use 0 or max */
+
+static unsigned int mit_table[MIT_SIZE+1] =
+{
+ /* CRS11 21143 hardware Mitigation Control Interrupt
+ We use only RX mitigation we other techniques for
+ TX intr. mitigation.
+
+ 31 Cycle Size (timer control)
+ 30:27 TX timer in 16 * Cycle size
+ 26:24 TX No pkts before Int.
+ 23:20 RX timer in Cycle size
+ 19:17 RX No pkts before Int.
+ 16 Continues Mode (CM)
+ */
+
+ 0x0, /* IM disabled */
+ 0x80150000, /* RX time = 1, RX pkts = 2, CM = 1 */
+ 0x80150000,
+ 0x80270000,
+ 0x80370000,
+ 0x80490000,
+ 0x80590000,
+ 0x80690000,
+ 0x807B0000,
+ 0x808B0000,
+ 0x809D0000,
+ 0x80AD0000,
+ 0x80BD0000,
+ 0x80CF0000,
+ 0x80DF0000,
+// 0x80FF0000 /* RX time = 16, RX pkts = 7, CM = 1 */
+ 0x80F10000 /* RX time = 16, RX pkts = 0, CM = 1 */
+};
+#endif
+
+
+int tulip_refill_rx(struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ int entry;
+ int refilled = 0;
+
+ /* Refill the Rx ring buffers. */
+ for (; tp->cur_rx - tp->dirty_rx > 0; tp->dirty_rx++) {
+ entry = tp->dirty_rx % RX_RING_SIZE;
+ if (tp->rx_buffers[entry].skb == NULL) {
+ struct sk_buff *skb;
+ dma_addr_t mapping;
+
+ skb = tp->rx_buffers[entry].skb =
+ netdev_alloc_skb(dev, PKT_BUF_SZ);
+ if (skb == NULL)
+ break;
+
+ mapping = dma_map_single(&tp->pdev->dev, skb->data,
+ PKT_BUF_SZ, DMA_FROM_DEVICE);
+ if (dma_mapping_error(&tp->pdev->dev, mapping)) {
+ dev_kfree_skb(skb);
+ tp->rx_buffers[entry].skb = NULL;
+ break;
+ }
+
+ tp->rx_buffers[entry].mapping = mapping;
+
+ tp->rx_ring[entry].buffer1 = cpu_to_le32(mapping);
+ refilled++;
+ }
+ tp->rx_ring[entry].status = cpu_to_le32(DescOwned);
+ }
+ if(tp->chip_id == LC82C168) {
+ if(((ioread32(tp->base_addr + CSR5)>>17)&0x07) == 4) {
+ /* Rx stopped due to out of buffers,
+ * restart it
+ */
+ iowrite32(0x01, tp->base_addr + CSR2);
+ }
+ }
+ return refilled;
+}
+
+#ifdef CONFIG_TULIP_NAPI
+
+void oom_timer(struct timer_list *t)
+{
+ struct tulip_private *tp = from_timer(tp, t, oom_timer);
+
+ napi_schedule(&tp->napi);
+}
+
+int tulip_poll(struct napi_struct *napi, int budget)
+{
+ struct tulip_private *tp = container_of(napi, struct tulip_private, napi);
+ struct net_device *dev = tp->dev;
+ int entry = tp->cur_rx % RX_RING_SIZE;
+ int work_done = 0;
+#ifdef CONFIG_TULIP_NAPI_HW_MITIGATION
+ int received = 0;
+#endif
+
+#ifdef CONFIG_TULIP_NAPI_HW_MITIGATION
+
+/* that one buffer is needed for mit activation; or might be a
+ bug in the ring buffer code; check later -- JHS*/
+
+ if (budget >=RX_RING_SIZE) budget--;
+#endif
+
+ if (tulip_debug > 4)
+ netdev_dbg(dev, " In tulip_rx(), entry %d %08x\n",
+ entry, tp->rx_ring[entry].status);
+
+ do {
+ if (ioread32(tp->base_addr + CSR5) == 0xffffffff) {
+ netdev_dbg(dev, " In tulip_poll(), hardware disappeared\n");
+ break;
+ }
+ /* Acknowledge current RX interrupt sources. */
+ iowrite32((RxIntr | RxNoBuf), tp->base_addr + CSR5);
+
+
+ /* If we own the next entry, it is a new packet. Send it up. */
+ while ( ! (tp->rx_ring[entry].status & cpu_to_le32(DescOwned))) {
+ s32 status = le32_to_cpu(tp->rx_ring[entry].status);
+ short pkt_len;
+
+ if (tp->dirty_rx + RX_RING_SIZE == tp->cur_rx)
+ break;
+
+ if (tulip_debug > 5)
+ netdev_dbg(dev, "In tulip_rx(), entry %d %08x\n",
+ entry, status);
+
+ if (++work_done >= budget)
+ goto not_done;
+
+ /*
+ * Omit the four octet CRC from the length.
+ * (May not be considered valid until we have
+ * checked status for RxLengthOver2047 bits)
+ */
+ pkt_len = ((status >> 16) & 0x7ff) - 4;
+
+ /*
+ * Maximum pkt_len is 1518 (1514 + vlan header)
+ * Anything higher than this is always invalid
+ * regardless of RxLengthOver2047 bits
+ */
+
+ if ((status & (RxLengthOver2047 |
+ RxDescCRCError |
+ RxDescCollisionSeen |
+ RxDescRunt |
+ RxDescDescErr |
+ RxWholePkt)) != RxWholePkt ||
+ pkt_len > 1518) {
+ if ((status & (RxLengthOver2047 |
+ RxWholePkt)) != RxWholePkt) {
+ /* Ingore earlier buffers. */
+ if ((status & 0xffff) != 0x7fff) {
+ if (tulip_debug > 1)
+ dev_warn(&dev->dev,
+ "Oversized Ethernet frame spanned multiple buffers, status %08x!\n",
+ status);
+ dev->stats.rx_length_errors++;
+ }
+ } else {
+ /* There was a fatal error. */
+ if (tulip_debug > 2)
+ netdev_dbg(dev, "Receive error, Rx status %08x\n",
+ status);
+ dev->stats.rx_errors++; /* end of a packet.*/
+ if (pkt_len > 1518 ||
+ (status & RxDescRunt))
+ dev->stats.rx_length_errors++;
+
+ if (status & 0x0004)
+ dev->stats.rx_frame_errors++;
+ if (status & 0x0002)
+ dev->stats.rx_crc_errors++;
+ if (status & 0x0001)
+ dev->stats.rx_fifo_errors++;
+ }
+ } else {
+ struct sk_buff *skb;
+
+ /* Check if the packet is long enough to accept without copying
+ to a minimally-sized skbuff. */
+ if (pkt_len < tulip_rx_copybreak &&
+ (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
+ skb_reserve(skb, 2); /* 16 byte align the IP header */
+ dma_sync_single_for_cpu(&tp->pdev->dev,
+ tp->rx_buffers[entry].mapping,
+ pkt_len,
+ DMA_FROM_DEVICE);
+#if ! defined(__alpha__)
+ skb_copy_to_linear_data(skb, tp->rx_buffers[entry].skb->data,
+ pkt_len);
+ skb_put(skb, pkt_len);
+#else
+ skb_put_data(skb,
+ tp->rx_buffers[entry].skb->data,
+ pkt_len);
+#endif
+ dma_sync_single_for_device(&tp->pdev->dev,
+ tp->rx_buffers[entry].mapping,
+ pkt_len,
+ DMA_FROM_DEVICE);
+ } else { /* Pass up the skb already on the Rx ring. */
+ char *temp = skb_put(skb = tp->rx_buffers[entry].skb,
+ pkt_len);
+
+#ifndef final_version
+ if (tp->rx_buffers[entry].mapping !=
+ le32_to_cpu(tp->rx_ring[entry].buffer1)) {
+ dev_err(&dev->dev,
+ "Internal fault: The skbuff addresses do not match in tulip_rx: %08x vs. %08llx %p / %p\n",
+ le32_to_cpu(tp->rx_ring[entry].buffer1),
+ (unsigned long long)tp->rx_buffers[entry].mapping,
+ skb->head, temp);
+ }
+#endif
+
+ dma_unmap_single(&tp->pdev->dev,
+ tp->rx_buffers[entry].mapping,
+ PKT_BUF_SZ,
+ DMA_FROM_DEVICE);
+
+ tp->rx_buffers[entry].skb = NULL;
+ tp->rx_buffers[entry].mapping = 0;
+ }
+ skb->protocol = eth_type_trans(skb, dev);
+
+ netif_receive_skb(skb);
+
+ dev->stats.rx_packets++;
+ dev->stats.rx_bytes += pkt_len;
+ }
+#ifdef CONFIG_TULIP_NAPI_HW_MITIGATION
+ received++;
+#endif
+
+ entry = (++tp->cur_rx) % RX_RING_SIZE;
+ if (tp->cur_rx - tp->dirty_rx > RX_RING_SIZE/4)
+ tulip_refill_rx(dev);
+
+ }
+
+ /* New ack strategy... irq does not ack Rx any longer
+ hopefully this helps */
+
+ /* Really bad things can happen here... If new packet arrives
+ * and an irq arrives (tx or just due to occasionally unset
+ * mask), it will be acked by irq handler, but new thread
+ * is not scheduled. It is major hole in design.
+ * No idea how to fix this if "playing with fire" will fail
+ * tomorrow (night 011029). If it will not fail, we won
+ * finally: amount of IO did not increase at all. */
+ } while ((ioread32(tp->base_addr + CSR5) & RxIntr));
+
+ #ifdef CONFIG_TULIP_NAPI_HW_MITIGATION
+
+ /* We use this simplistic scheme for IM. It's proven by
+ real life installations. We can have IM enabled
+ continuesly but this would cause unnecessary latency.
+ Unfortunely we can't use all the NET_RX_* feedback here.
+ This would turn on IM for devices that is not contributing
+ to backlog congestion with unnecessary latency.
+
+ We monitor the device RX-ring and have:
+
+ HW Interrupt Mitigation either ON or OFF.
+
+ ON: More then 1 pkt received (per intr.) OR we are dropping
+ OFF: Only 1 pkt received
+
+ Note. We only use min and max (0, 15) settings from mit_table */
+
+
+ if( tp->flags & HAS_INTR_MITIGATION) {
+ if( received > 1 ) {
+ if( ! tp->mit_on ) {
+ tp->mit_on = 1;
+ iowrite32(mit_table[MIT_TABLE], tp->base_addr + CSR11);
+ }
+ }
+ else {
+ if( tp->mit_on ) {
+ tp->mit_on = 0;
+ iowrite32(0, tp->base_addr + CSR11);
+ }
+ }
+ }
+
+#endif /* CONFIG_TULIP_NAPI_HW_MITIGATION */
+
+ tulip_refill_rx(dev);
+
+ /* If RX ring is not full we are out of memory. */
+ if (tp->rx_buffers[tp->dirty_rx % RX_RING_SIZE].skb == NULL)
+ goto oom;
+
+ /* Remove us from polling list and enable RX intr. */
+
+ napi_complete_done(napi, work_done);
+ iowrite32(tulip_tbl[tp->chip_id].valid_intrs, tp->base_addr+CSR7);
+
+ /* The last op happens after poll completion. Which means the following:
+ * 1. it can race with disabling irqs in irq handler
+ * 2. it can race with dise/enabling irqs in other poll threads
+ * 3. if an irq raised after beginning loop, it will be immediately
+ * triggered here.
+ *
+ * Summarizing: the logic results in some redundant irqs both
+ * due to races in masking and due to too late acking of already
+ * processed irqs. But it must not result in losing events.
+ */
+
+ return work_done;
+
+ not_done:
+ if (tp->cur_rx - tp->dirty_rx > RX_RING_SIZE/2 ||
+ tp->rx_buffers[tp->dirty_rx % RX_RING_SIZE].skb == NULL)
+ tulip_refill_rx(dev);
+
+ if (tp->rx_buffers[tp->dirty_rx % RX_RING_SIZE].skb == NULL)
+ goto oom;
+
+ return work_done;
+
+ oom: /* Executed with RX ints disabled */
+
+ /* Start timer, stop polling, but do not enable rx interrupts. */
+ mod_timer(&tp->oom_timer, jiffies+1);
+
+ /* Think: timer_pending() was an explicit signature of bug.
+ * Timer can be pending now but fired and completed
+ * before we did napi_complete(). See? We would lose it. */
+
+ /* remove ourselves from the polling list */
+ napi_complete_done(napi, work_done);
+
+ return work_done;
+}
+
+#else /* CONFIG_TULIP_NAPI */
+
+static int tulip_rx(struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ int entry = tp->cur_rx % RX_RING_SIZE;
+ int rx_work_limit = tp->dirty_rx + RX_RING_SIZE - tp->cur_rx;
+ int received = 0;
+
+ if (tulip_debug > 4)
+ netdev_dbg(dev, "In tulip_rx(), entry %d %08x\n",
+ entry, tp->rx_ring[entry].status);
+ /* If we own the next entry, it is a new packet. Send it up. */
+ while ( ! (tp->rx_ring[entry].status & cpu_to_le32(DescOwned))) {
+ s32 status = le32_to_cpu(tp->rx_ring[entry].status);
+ short pkt_len;
+
+ if (tulip_debug > 5)
+ netdev_dbg(dev, "In tulip_rx(), entry %d %08x\n",
+ entry, status);
+ if (--rx_work_limit < 0)
+ break;
+
+ /*
+ Omit the four octet CRC from the length.
+ (May not be considered valid until we have
+ checked status for RxLengthOver2047 bits)
+ */
+ pkt_len = ((status >> 16) & 0x7ff) - 4;
+ /*
+ Maximum pkt_len is 1518 (1514 + vlan header)
+ Anything higher than this is always invalid
+ regardless of RxLengthOver2047 bits
+ */
+
+ if ((status & (RxLengthOver2047 |
+ RxDescCRCError |
+ RxDescCollisionSeen |
+ RxDescRunt |
+ RxDescDescErr |
+ RxWholePkt)) != RxWholePkt ||
+ pkt_len > 1518) {
+ if ((status & (RxLengthOver2047 |
+ RxWholePkt)) != RxWholePkt) {
+ /* Ingore earlier buffers. */
+ if ((status & 0xffff) != 0x7fff) {
+ if (tulip_debug > 1)
+ netdev_warn(dev,
+ "Oversized Ethernet frame spanned multiple buffers, status %08x!\n",
+ status);
+ dev->stats.rx_length_errors++;
+ }
+ } else {
+ /* There was a fatal error. */
+ if (tulip_debug > 2)
+ netdev_dbg(dev, "Receive error, Rx status %08x\n",
+ status);
+ dev->stats.rx_errors++; /* end of a packet.*/
+ if (pkt_len > 1518 ||
+ (status & RxDescRunt))
+ dev->stats.rx_length_errors++;
+ if (status & 0x0004)
+ dev->stats.rx_frame_errors++;
+ if (status & 0x0002)
+ dev->stats.rx_crc_errors++;
+ if (status & 0x0001)
+ dev->stats.rx_fifo_errors++;
+ }
+ } else {
+ struct sk_buff *skb;
+
+ /* Check if the packet is long enough to accept without copying
+ to a minimally-sized skbuff. */
+ if (pkt_len < tulip_rx_copybreak &&
+ (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
+ skb_reserve(skb, 2); /* 16 byte align the IP header */
+ dma_sync_single_for_cpu(&tp->pdev->dev,
+ tp->rx_buffers[entry].mapping,
+ pkt_len,
+ DMA_FROM_DEVICE);
+#if ! defined(__alpha__)
+ skb_copy_to_linear_data(skb, tp->rx_buffers[entry].skb->data,
+ pkt_len);
+ skb_put(skb, pkt_len);
+#else
+ skb_put_data(skb,
+ tp->rx_buffers[entry].skb->data,
+ pkt_len);
+#endif
+ dma_sync_single_for_device(&tp->pdev->dev,
+ tp->rx_buffers[entry].mapping,
+ pkt_len,
+ DMA_FROM_DEVICE);
+ } else { /* Pass up the skb already on the Rx ring. */
+ char *temp = skb_put(skb = tp->rx_buffers[entry].skb,
+ pkt_len);
+
+#ifndef final_version
+ if (tp->rx_buffers[entry].mapping !=
+ le32_to_cpu(tp->rx_ring[entry].buffer1)) {
+ dev_err(&dev->dev,
+ "Internal fault: The skbuff addresses do not match in tulip_rx: %08x vs. %Lx %p / %p\n",
+ le32_to_cpu(tp->rx_ring[entry].buffer1),
+ (long long)tp->rx_buffers[entry].mapping,
+ skb->head, temp);
+ }
+#endif
+
+ dma_unmap_single(&tp->pdev->dev,
+ tp->rx_buffers[entry].mapping,
+ PKT_BUF_SZ, DMA_FROM_DEVICE);
+
+ tp->rx_buffers[entry].skb = NULL;
+ tp->rx_buffers[entry].mapping = 0;
+ }
+ skb->protocol = eth_type_trans(skb, dev);
+
+ netif_rx(skb);
+
+ dev->stats.rx_packets++;
+ dev->stats.rx_bytes += pkt_len;
+ }
+ received++;
+ entry = (++tp->cur_rx) % RX_RING_SIZE;
+ }
+ return received;
+}
+#endif /* CONFIG_TULIP_NAPI */
+
+static inline unsigned int phy_interrupt (struct net_device *dev)
+{
+#ifdef __hppa__
+ struct tulip_private *tp = netdev_priv(dev);
+ int csr12 = ioread32(tp->base_addr + CSR12) & 0xff;
+
+ if (csr12 != tp->csr12_shadow) {
+ /* ack interrupt */
+ iowrite32(csr12 | 0x02, tp->base_addr + CSR12);
+ tp->csr12_shadow = csr12;
+ /* do link change stuff */
+ spin_lock(&tp->lock);
+ tulip_check_duplex(dev);
+ spin_unlock(&tp->lock);
+ /* clear irq ack bit */
+ iowrite32(csr12 & ~0x02, tp->base_addr + CSR12);
+
+ return 1;
+ }
+#endif
+
+ return 0;
+}
+
+/* The interrupt handler does all of the Rx thread work and cleans up
+ after the Tx thread. */
+irqreturn_t tulip_interrupt(int irq, void *dev_instance)
+{
+ struct net_device *dev = (struct net_device *)dev_instance;
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+ int csr5;
+ int missed;
+ int rx = 0;
+ int tx = 0;
+ int oi = 0;
+ int maxrx = RX_RING_SIZE;
+ int maxtx = TX_RING_SIZE;
+ int maxoi = TX_RING_SIZE;
+#ifdef CONFIG_TULIP_NAPI
+ int rxd = 0;
+#else
+ int entry;
+#endif
+ unsigned int work_count = tulip_max_interrupt_work;
+ unsigned int handled = 0;
+
+ /* Let's see whether the interrupt really is for us */
+ csr5 = ioread32(ioaddr + CSR5);
+
+ if (tp->flags & HAS_PHY_IRQ)
+ handled = phy_interrupt (dev);
+
+ if ((csr5 & (NormalIntr|AbnormalIntr)) == 0)
+ return IRQ_RETVAL(handled);
+
+ tp->nir++;
+
+ do {
+
+#ifdef CONFIG_TULIP_NAPI
+
+ if (!rxd && (csr5 & (RxIntr | RxNoBuf))) {
+ rxd++;
+ /* Mask RX intrs and add the device to poll list. */
+ iowrite32(tulip_tbl[tp->chip_id].valid_intrs&~RxPollInt, ioaddr + CSR7);
+ napi_schedule(&tp->napi);
+
+ if (!(csr5&~(AbnormalIntr|NormalIntr|RxPollInt|TPLnkPass)))
+ break;
+ }
+
+ /* Acknowledge the interrupt sources we handle here ASAP
+ the poll function does Rx and RxNoBuf acking */
+
+ iowrite32(csr5 & 0x0001ff3f, ioaddr + CSR5);
+
+#else
+ /* Acknowledge all of the current interrupt sources ASAP. */
+ iowrite32(csr5 & 0x0001ffff, ioaddr + CSR5);
+
+
+ if (csr5 & (RxIntr | RxNoBuf)) {
+ rx += tulip_rx(dev);
+ tulip_refill_rx(dev);
+ }
+
+#endif /* CONFIG_TULIP_NAPI */
+
+ if (tulip_debug > 4)
+ netdev_dbg(dev, "interrupt csr5=%#8.8x new csr5=%#8.8x\n",
+ csr5, ioread32(ioaddr + CSR5));
+
+
+ if (csr5 & (TxNoBuf | TxDied | TxIntr | TimerInt)) {
+ unsigned int dirty_tx;
+
+ spin_lock(&tp->lock);
+
+ for (dirty_tx = tp->dirty_tx; tp->cur_tx - dirty_tx > 0;
+ dirty_tx++) {
+ int entry = dirty_tx % TX_RING_SIZE;
+ int status = le32_to_cpu(tp->tx_ring[entry].status);
+
+ if (status < 0)
+ break; /* It still has not been Txed */
+
+ /* Check for Rx filter setup frames. */
+ if (tp->tx_buffers[entry].skb == NULL) {
+ /* test because dummy frames not mapped */
+ if (tp->tx_buffers[entry].mapping)
+ dma_unmap_single(&tp->pdev->dev,
+ tp->tx_buffers[entry].mapping,
+ sizeof(tp->setup_frame),
+ DMA_TO_DEVICE);
+ continue;
+ }
+
+ if (status & 0x8000) {
+ /* There was an major error, log it. */
+#ifndef final_version
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "Transmit error, Tx status %08x\n",
+ status);
+#endif
+ dev->stats.tx_errors++;
+ if (status & 0x4104)
+ dev->stats.tx_aborted_errors++;
+ if (status & 0x0C00)
+ dev->stats.tx_carrier_errors++;
+ if (status & 0x0200)
+ dev->stats.tx_window_errors++;
+ if (status & 0x0002)
+ dev->stats.tx_fifo_errors++;
+ if ((status & 0x0080) && tp->full_duplex == 0)
+ dev->stats.tx_heartbeat_errors++;
+ } else {
+ dev->stats.tx_bytes +=
+ tp->tx_buffers[entry].skb->len;
+ dev->stats.collisions += (status >> 3) & 15;
+ dev->stats.tx_packets++;
+ }
+
+ dma_unmap_single(&tp->pdev->dev,
+ tp->tx_buffers[entry].mapping,
+ tp->tx_buffers[entry].skb->len,
+ DMA_TO_DEVICE);
+
+ /* Free the original skb. */
+ dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
+ tp->tx_buffers[entry].skb = NULL;
+ tp->tx_buffers[entry].mapping = 0;
+ tx++;
+ }
+
+#ifndef final_version
+ if (tp->cur_tx - dirty_tx > TX_RING_SIZE) {
+ dev_err(&dev->dev,
+ "Out-of-sync dirty pointer, %d vs. %d\n",
+ dirty_tx, tp->cur_tx);
+ dirty_tx += TX_RING_SIZE;
+ }
+#endif
+
+ if (tp->cur_tx - dirty_tx < TX_RING_SIZE - 2)
+ netif_wake_queue(dev);
+
+ tp->dirty_tx = dirty_tx;
+ if (csr5 & TxDied) {
+ if (tulip_debug > 2)
+ dev_warn(&dev->dev,
+ "The transmitter stopped. CSR5 is %x, CSR6 %x, new CSR6 %x\n",
+ csr5, ioread32(ioaddr + CSR6),
+ tp->csr6);
+ tulip_restart_rxtx(tp);
+ }
+ spin_unlock(&tp->lock);
+ }
+
+ /* Log errors. */
+ if (csr5 & AbnormalIntr) { /* Abnormal error summary bit. */
+ if (csr5 == 0xffffffff)
+ break;
+ if (csr5 & TxJabber)
+ dev->stats.tx_errors++;
+ if (csr5 & TxFIFOUnderflow) {
+ if ((tp->csr6 & 0xC000) != 0xC000)
+ tp->csr6 += 0x4000; /* Bump up the Tx threshold */
+ else
+ tp->csr6 |= 0x00200000; /* Store-n-forward. */
+ /* Restart the transmit process. */
+ tulip_restart_rxtx(tp);
+ iowrite32(0, ioaddr + CSR1);
+ }
+ if (csr5 & (RxDied | RxNoBuf)) {
+ if (tp->flags & COMET_MAC_ADDR) {
+ iowrite32(tp->mc_filter[0], ioaddr + 0xAC);
+ iowrite32(tp->mc_filter[1], ioaddr + 0xB0);
+ }
+ }
+ if (csr5 & RxDied) { /* Missed a Rx frame. */
+ dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
+ dev->stats.rx_errors++;
+ tulip_start_rxtx(tp);
+ }
+ /*
+ * NB: t21142_lnk_change() does a del_timer_sync(), so be careful if this
+ * call is ever done under the spinlock
+ */
+ if (csr5 & (TPLnkPass | TPLnkFail | 0x08000000)) {
+ if (tp->link_change)
+ (tp->link_change)(dev, csr5);
+ }
+ if (csr5 & SystemError) {
+ int error = (csr5 >> 23) & 7;
+ /* oops, we hit a PCI error. The code produced corresponds
+ * to the reason:
+ * 0 - parity error
+ * 1 - master abort
+ * 2 - target abort
+ * Note that on parity error, we should do a software reset
+ * of the chip to get it back into a sane state (according
+ * to the 21142/3 docs that is).
+ * -- rmk
+ */
+ dev_err(&dev->dev,
+ "(%lu) System Error occurred (%d)\n",
+ tp->nir, error);
+ }
+ /* Clear all error sources, included undocumented ones! */
+ iowrite32(0x0800f7ba, ioaddr + CSR5);
+ oi++;
+ }
+ if (csr5 & TimerInt) {
+
+ if (tulip_debug > 2)
+ dev_err(&dev->dev,
+ "Re-enabling interrupts, %08x\n",
+ csr5);
+ iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
+ tp->ttimer = 0;
+ oi++;
+ }
+ if (tx > maxtx || rx > maxrx || oi > maxoi) {
+ if (tulip_debug > 1)
+ dev_warn(&dev->dev, "Too much work during an interrupt, csr5=0x%08x. (%lu) (%d,%d,%d)\n",
+ csr5, tp->nir, tx, rx, oi);
+
+ /* Acknowledge all interrupt sources. */
+ iowrite32(0x8001ffff, ioaddr + CSR5);
+ if (tp->flags & HAS_INTR_MITIGATION) {
+ /* Josip Loncaric at ICASE did extensive experimentation
+ to develop a good interrupt mitigation setting.*/
+ iowrite32(0x8b240000, ioaddr + CSR11);
+ } else if (tp->chip_id == LC82C168) {
+ /* the LC82C168 doesn't have a hw timer.*/
+ iowrite32(0x00, ioaddr + CSR7);
+ mod_timer(&tp->timer, RUN_AT(HZ/50));
+ } else {
+ /* Mask all interrupting sources, set timer to
+ re-enable. */
+ iowrite32(((~csr5) & 0x0001ebef) | AbnormalIntr | TimerInt, ioaddr + CSR7);
+ iowrite32(0x0012, ioaddr + CSR11);
+ }
+ break;
+ }
+
+ work_count--;
+ if (work_count == 0)
+ break;
+
+ csr5 = ioread32(ioaddr + CSR5);
+
+#ifdef CONFIG_TULIP_NAPI
+ if (rxd)
+ csr5 &= ~RxPollInt;
+ } while ((csr5 & (TxNoBuf |
+ TxDied |
+ TxIntr |
+ TimerInt |
+ /* Abnormal intr. */
+ RxDied |
+ TxFIFOUnderflow |
+ TxJabber |
+ TPLnkFail |
+ SystemError )) != 0);
+#else
+ } while ((csr5 & (NormalIntr|AbnormalIntr)) != 0);
+
+ tulip_refill_rx(dev);
+
+ /* check if the card is in suspend mode */
+ entry = tp->dirty_rx % RX_RING_SIZE;
+ if (tp->rx_buffers[entry].skb == NULL) {
+ if (tulip_debug > 1)
+ dev_warn(&dev->dev,
+ "in rx suspend mode: (%lu) (tp->cur_rx = %u, ttimer = %d, rx = %d) go/stay in suspend mode\n",
+ tp->nir, tp->cur_rx, tp->ttimer, rx);
+ if (tp->chip_id == LC82C168) {
+ iowrite32(0x00, ioaddr + CSR7);
+ mod_timer(&tp->timer, RUN_AT(HZ/50));
+ } else {
+ if (tp->ttimer == 0 || (ioread32(ioaddr + CSR11) & 0xffff) == 0) {
+ if (tulip_debug > 1)
+ dev_warn(&dev->dev,
+ "in rx suspend mode: (%lu) set timer\n",
+ tp->nir);
+ iowrite32(tulip_tbl[tp->chip_id].valid_intrs | TimerInt,
+ ioaddr + CSR7);
+ iowrite32(TimerInt, ioaddr + CSR5);
+ iowrite32(12, ioaddr + CSR11);
+ tp->ttimer = 1;
+ }
+ }
+ }
+#endif /* CONFIG_TULIP_NAPI */
+
+ if ((missed = ioread32(ioaddr + CSR8) & 0x1ffff)) {
+ dev->stats.rx_dropped += missed & 0x10000 ? 0x10000 : missed;
+ }
+
+ if (tulip_debug > 4)
+ netdev_dbg(dev, "exiting interrupt, csr5=%#04x\n",
+ ioread32(ioaddr + CSR5));
+
+ return IRQ_HANDLED;
+}
diff --git a/drivers/net/ethernet/dec/tulip/media.c b/drivers/net/ethernet/dec/tulip/media.c
new file mode 100644
index 000000000..55d6fc99f
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/media.c
@@ -0,0 +1,547 @@
+/*
+ drivers/net/ethernet/dec/tulip/media.c
+
+ Copyright 2000,2001 The Linux Kernel Team
+ Written/copyright 1994-2001 by Donald Becker.
+
+ This software may be used and distributed according to the terms
+ of the GNU General Public License, incorporated herein by reference.
+
+ Please submit bugs to http://bugzilla.kernel.org/ .
+*/
+
+#include <linux/kernel.h>
+#include <linux/mii.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include "tulip.h"
+
+
+/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
+ met by back-to-back PCI I/O cycles, but we insert a delay to avoid
+ "overclocking" issues or future 66Mhz PCI. */
+#define mdio_delay() ioread32(mdio_addr)
+
+/* Read and write the MII registers using software-generated serial
+ MDIO protocol. It is just different enough from the EEPROM protocol
+ to not share code. The maxium data clock rate is 2.5 Mhz. */
+#define MDIO_SHIFT_CLK 0x10000
+#define MDIO_DATA_WRITE0 0x00000
+#define MDIO_DATA_WRITE1 0x20000
+#define MDIO_ENB 0x00000 /* Ignore the 0x02000 databook setting. */
+#define MDIO_ENB_IN 0x40000
+#define MDIO_DATA_READ 0x80000
+
+static const unsigned char comet_miireg2offset[32] = {
+ 0xB4, 0xB8, 0xBC, 0xC0, 0xC4, 0xC8, 0xCC, 0, 0,0,0,0, 0,0,0,0,
+ 0,0xD0,0,0, 0,0,0,0, 0,0,0,0, 0, 0xD4, 0xD8, 0xDC, };
+
+
+/* MII transceiver control section.
+ Read and write the MII registers using software-generated serial
+ MDIO protocol.
+ See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management functions")
+ or DP83840A data sheet for more details.
+ */
+
+int tulip_mdio_read(struct net_device *dev, int phy_id, int location)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ int i;
+ int read_cmd = (0xf6 << 10) | ((phy_id & 0x1f) << 5) | location;
+ int retval = 0;
+ void __iomem *ioaddr = tp->base_addr;
+ void __iomem *mdio_addr = ioaddr + CSR9;
+ unsigned long flags;
+
+ if (location & ~0x1f)
+ return 0xffff;
+
+ if (tp->chip_id == COMET && phy_id == 30) {
+ if (comet_miireg2offset[location])
+ return ioread32(ioaddr + comet_miireg2offset[location]);
+ return 0xffff;
+ }
+
+ spin_lock_irqsave(&tp->mii_lock, flags);
+ if (tp->chip_id == LC82C168) {
+ iowrite32(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0);
+ ioread32(ioaddr + 0xA0);
+ ioread32(ioaddr + 0xA0);
+ for (i = 1000; i >= 0; --i) {
+ barrier();
+ if ( ! ((retval = ioread32(ioaddr + 0xA0)) & 0x80000000))
+ break;
+ }
+ spin_unlock_irqrestore(&tp->mii_lock, flags);
+ return retval & 0xffff;
+ }
+
+ /* Establish sync by sending at least 32 logic ones. */
+ for (i = 32; i >= 0; i--) {
+ iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
+ mdio_delay();
+ iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
+ mdio_delay();
+ }
+ /* Shift the read command bits out. */
+ for (i = 15; i >= 0; i--) {
+ int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
+
+ iowrite32(MDIO_ENB | dataval, mdio_addr);
+ mdio_delay();
+ iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
+ mdio_delay();
+ }
+ /* Read the two transition, 16 data, and wire-idle bits. */
+ for (i = 19; i > 0; i--) {
+ iowrite32(MDIO_ENB_IN, mdio_addr);
+ mdio_delay();
+ retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
+ iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
+ mdio_delay();
+ }
+
+ spin_unlock_irqrestore(&tp->mii_lock, flags);
+ return (retval>>1) & 0xffff;
+}
+
+void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int val)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ int i;
+ int cmd = (0x5002 << 16) | ((phy_id & 0x1f) << 23) | (location<<18) | (val & 0xffff);
+ void __iomem *ioaddr = tp->base_addr;
+ void __iomem *mdio_addr = ioaddr + CSR9;
+ unsigned long flags;
+
+ if (location & ~0x1f)
+ return;
+
+ if (tp->chip_id == COMET && phy_id == 30) {
+ if (comet_miireg2offset[location])
+ iowrite32(val, ioaddr + comet_miireg2offset[location]);
+ return;
+ }
+
+ spin_lock_irqsave(&tp->mii_lock, flags);
+ if (tp->chip_id == LC82C168) {
+ iowrite32(cmd, ioaddr + 0xA0);
+ for (i = 1000; i >= 0; --i) {
+ barrier();
+ if ( ! (ioread32(ioaddr + 0xA0) & 0x80000000))
+ break;
+ }
+ spin_unlock_irqrestore(&tp->mii_lock, flags);
+ return;
+ }
+
+ /* Establish sync by sending 32 logic ones. */
+ for (i = 32; i >= 0; i--) {
+ iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
+ mdio_delay();
+ iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
+ mdio_delay();
+ }
+ /* Shift the command bits out. */
+ for (i = 31; i >= 0; i--) {
+ int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
+ iowrite32(MDIO_ENB | dataval, mdio_addr);
+ mdio_delay();
+ iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
+ mdio_delay();
+ }
+ /* Clear out extra bits. */
+ for (i = 2; i > 0; i--) {
+ iowrite32(MDIO_ENB_IN, mdio_addr);
+ mdio_delay();
+ iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
+ mdio_delay();
+ }
+
+ spin_unlock_irqrestore(&tp->mii_lock, flags);
+}
+
+
+/* Set up the transceiver control registers for the selected media type. */
+void tulip_select_media(struct net_device *dev, int startup)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+ struct mediatable *mtable = tp->mtable;
+ u32 new_csr6;
+ int i;
+
+ if (mtable) {
+ struct medialeaf *mleaf = &mtable->mleaf[tp->cur_index];
+ unsigned char *p = mleaf->leafdata;
+ switch (mleaf->type) {
+ case 0: /* 21140 non-MII xcvr. */
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "Using a 21140 non-MII transceiver with control setting %02x\n",
+ p[1]);
+ dev->if_port = p[0];
+ if (startup)
+ iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
+ iowrite32(p[1], ioaddr + CSR12);
+ new_csr6 = 0x02000000 | ((p[2] & 0x71) << 18);
+ break;
+ case 2: case 4: {
+ u16 setup[5];
+ u32 csr13val, csr14val, csr15dir, csr15val;
+ for (i = 0; i < 5; i++)
+ setup[i] = get_u16(&p[i*2 + 1]);
+
+ dev->if_port = p[0] & MEDIA_MASK;
+ if (tulip_media_cap[dev->if_port] & MediaAlwaysFD)
+ tp->full_duplex = 1;
+
+ if (startup && mtable->has_reset) {
+ struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
+ unsigned char *rst = rleaf->leafdata;
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "Resetting the transceiver\n");
+ for (i = 0; i < rst[0]; i++)
+ iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
+ }
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "21143 non-MII %s transceiver control %04x/%04x\n",
+ medianame[dev->if_port],
+ setup[0], setup[1]);
+ if (p[0] & 0x40) { /* SIA (CSR13-15) setup values are provided. */
+ csr13val = setup[0];
+ csr14val = setup[1];
+ csr15dir = (setup[3]<<16) | setup[2];
+ csr15val = (setup[4]<<16) | setup[2];
+ iowrite32(0, ioaddr + CSR13);
+ iowrite32(csr14val, ioaddr + CSR14);
+ iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
+ iowrite32(csr15val, ioaddr + CSR15); /* Data */
+ iowrite32(csr13val, ioaddr + CSR13);
+ } else {
+ csr13val = 1;
+ csr14val = 0;
+ csr15dir = (setup[0]<<16) | 0x0008;
+ csr15val = (setup[1]<<16) | 0x0008;
+ if (dev->if_port <= 4)
+ csr14val = t21142_csr14[dev->if_port];
+ if (startup) {
+ iowrite32(0, ioaddr + CSR13);
+ iowrite32(csr14val, ioaddr + CSR14);
+ }
+ iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
+ iowrite32(csr15val, ioaddr + CSR15); /* Data */
+ if (startup) iowrite32(csr13val, ioaddr + CSR13);
+ }
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "Setting CSR15 to %08x/%08x\n",
+ csr15dir, csr15val);
+ if (mleaf->type == 4)
+ new_csr6 = 0x82020000 | ((setup[2] & 0x71) << 18);
+ else
+ new_csr6 = 0x82420000;
+ break;
+ }
+ case 1: case 3: {
+ int phy_num = p[0];
+ int init_length = p[1];
+ u16 *misc_info, tmp_info;
+
+ dev->if_port = 11;
+ new_csr6 = 0x020E0000;
+ if (mleaf->type == 3) { /* 21142 */
+ u16 *init_sequence = (u16*)(p+2);
+ u16 *reset_sequence = &((u16*)(p+3))[init_length];
+ int reset_length = p[2 + init_length*2];
+ misc_info = reset_sequence + reset_length;
+ if (startup) {
+ int timeout = 10; /* max 1 ms */
+ for (i = 0; i < reset_length; i++)
+ iowrite32(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15);
+
+ /* flush posted writes */
+ ioread32(ioaddr + CSR15);
+
+ /* Sect 3.10.3 in DP83840A.pdf (p39) */
+ udelay(500);
+
+ /* Section 4.2 in DP83840A.pdf (p43) */
+ /* and IEEE 802.3 "22.2.4.1.1 Reset" */
+ while (timeout-- &&
+ (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
+ udelay(100);
+ }
+ for (i = 0; i < init_length; i++)
+ iowrite32(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15);
+
+ ioread32(ioaddr + CSR15); /* flush posted writes */
+ } else {
+ u8 *init_sequence = p + 2;
+ u8 *reset_sequence = p + 3 + init_length;
+ int reset_length = p[2 + init_length];
+ misc_info = (u16*)(reset_sequence + reset_length);
+ if (startup) {
+ int timeout = 10; /* max 1 ms */
+ iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
+ for (i = 0; i < reset_length; i++)
+ iowrite32(reset_sequence[i], ioaddr + CSR12);
+
+ /* flush posted writes */
+ ioread32(ioaddr + CSR12);
+
+ /* Sect 3.10.3 in DP83840A.pdf (p39) */
+ udelay(500);
+
+ /* Section 4.2 in DP83840A.pdf (p43) */
+ /* and IEEE 802.3 "22.2.4.1.1 Reset" */
+ while (timeout-- &&
+ (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
+ udelay(100);
+ }
+ for (i = 0; i < init_length; i++)
+ iowrite32(init_sequence[i], ioaddr + CSR12);
+
+ ioread32(ioaddr + CSR12); /* flush posted writes */
+ }
+
+ tmp_info = get_u16(&misc_info[1]);
+ if (tmp_info)
+ tp->advertising[phy_num] = tmp_info | 1;
+ if (tmp_info && startup < 2) {
+ if (tp->mii_advertise == 0)
+ tp->mii_advertise = tp->advertising[phy_num];
+ if (tulip_debug > 1)
+ netdev_dbg(dev, " Advertising %04x on MII %d\n",
+ tp->mii_advertise,
+ tp->phys[phy_num]);
+ tulip_mdio_write(dev, tp->phys[phy_num], 4, tp->mii_advertise);
+ }
+ break;
+ }
+ case 5: case 6: {
+ new_csr6 = 0; /* FIXME */
+
+ if (startup && mtable->has_reset) {
+ struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
+ unsigned char *rst = rleaf->leafdata;
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "Resetting the transceiver\n");
+ for (i = 0; i < rst[0]; i++)
+ iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
+ }
+
+ break;
+ }
+ default:
+ netdev_dbg(dev, " Invalid media table selection %d\n",
+ mleaf->type);
+ new_csr6 = 0x020E0000;
+ }
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "Using media type %s, CSR12 is %02x\n",
+ medianame[dev->if_port],
+ ioread32(ioaddr + CSR12) & 0xff);
+ } else if (tp->chip_id == LC82C168) {
+ if (startup && ! tp->medialock)
+ dev->if_port = tp->mii_cnt ? 11 : 0;
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "PNIC PHY status is %3.3x, media %s\n",
+ ioread32(ioaddr + 0xB8),
+ medianame[dev->if_port]);
+ if (tp->mii_cnt) {
+ new_csr6 = 0x810C0000;
+ iowrite32(0x0001, ioaddr + CSR15);
+ iowrite32(0x0201B07A, ioaddr + 0xB8);
+ } else if (startup) {
+ /* Start with 10mbps to do autonegotiation. */
+ iowrite32(0x32, ioaddr + CSR12);
+ new_csr6 = 0x00420000;
+ iowrite32(0x0001B078, ioaddr + 0xB8);
+ iowrite32(0x0201B078, ioaddr + 0xB8);
+ } else if (dev->if_port == 3 || dev->if_port == 5) {
+ iowrite32(0x33, ioaddr + CSR12);
+ new_csr6 = 0x01860000;
+ /* Trigger autonegotiation. */
+ iowrite32(0x0001F868, ioaddr + 0xB8);
+ } else {
+ iowrite32(0x32, ioaddr + CSR12);
+ new_csr6 = 0x00420000;
+ iowrite32(0x1F078, ioaddr + 0xB8);
+ }
+ } else { /* Unknown chip type with no media table. */
+ if (tp->default_port == 0)
+ dev->if_port = tp->mii_cnt ? 11 : 3;
+ if (tulip_media_cap[dev->if_port] & MediaIsMII) {
+ new_csr6 = 0x020E0000;
+ } else if (tulip_media_cap[dev->if_port] & MediaIsFx) {
+ new_csr6 = 0x02860000;
+ } else
+ new_csr6 = 0x03860000;
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "No media description table, assuming %s transceiver, CSR12 %02x\n",
+ medianame[dev->if_port],
+ ioread32(ioaddr + CSR12));
+ }
+
+ tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0);
+
+ mdelay(1);
+}
+
+/*
+ Check the MII negotiated duplex and change the CSR6 setting if
+ required.
+ Return 0 if everything is OK.
+ Return < 0 if the transceiver is missing or has no link beat.
+ */
+int tulip_check_duplex(struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ unsigned int bmsr, lpa, negotiated, new_csr6;
+
+ bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
+ lpa = tulip_mdio_read(dev, tp->phys[0], MII_LPA);
+ if (tulip_debug > 1)
+ dev_info(&dev->dev, "MII status %04x, Link partner report %04x\n",
+ bmsr, lpa);
+ if (bmsr == 0xffff)
+ return -2;
+ if ((bmsr & BMSR_LSTATUS) == 0) {
+ int new_bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
+ if ((new_bmsr & BMSR_LSTATUS) == 0) {
+ if (tulip_debug > 1)
+ dev_info(&dev->dev,
+ "No link beat on the MII interface, status %04x\n",
+ new_bmsr);
+ return -1;
+ }
+ }
+ negotiated = lpa & tp->advertising[0];
+ tp->full_duplex = mii_duplex(tp->full_duplex_lock, negotiated);
+
+ new_csr6 = tp->csr6;
+
+ if (negotiated & LPA_100) new_csr6 &= ~TxThreshold;
+ else new_csr6 |= TxThreshold;
+ if (tp->full_duplex) new_csr6 |= FullDuplex;
+ else new_csr6 &= ~FullDuplex;
+
+ if (new_csr6 != tp->csr6) {
+ tp->csr6 = new_csr6;
+ tulip_restart_rxtx(tp);
+
+ if (tulip_debug > 0)
+ dev_info(&dev->dev,
+ "Setting %s-duplex based on MII#%d link partner capability of %04x\n",
+ tp->full_duplex ? "full" : "half",
+ tp->phys[0], lpa);
+ return 1;
+ }
+
+ return 0;
+}
+
+void tulip_find_mii(struct net_device *dev, int board_idx)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ int phyn, phy_idx = 0;
+ int mii_reg0;
+ int mii_advert;
+ unsigned int to_advert, new_bmcr, ane_switch;
+
+ /* Find the connected MII xcvrs.
+ Doing this in open() would allow detecting external xcvrs later,
+ but takes much time. */
+ for (phyn = 1; phyn <= 32 && phy_idx < ARRAY_SIZE(tp->phys); phyn++) {
+ int phy = phyn & 0x1f;
+ int mii_status = tulip_mdio_read (dev, phy, MII_BMSR);
+ if ((mii_status & 0x8301) == 0x8001 ||
+ ((mii_status & BMSR_100BASE4) == 0 &&
+ (mii_status & 0x7800) != 0)) {
+ /* preserve Becker logic, gain indentation level */
+ } else {
+ continue;
+ }
+
+ mii_reg0 = tulip_mdio_read (dev, phy, MII_BMCR);
+ mii_advert = tulip_mdio_read (dev, phy, MII_ADVERTISE);
+ ane_switch = 0;
+
+ /* if not advertising at all, gen an
+ * advertising value from the capability
+ * bits in BMSR
+ */
+ if ((mii_advert & ADVERTISE_ALL) == 0) {
+ unsigned int tmpadv = tulip_mdio_read (dev, phy, MII_BMSR);
+ mii_advert = ((tmpadv >> 6) & 0x3e0) | 1;
+ }
+
+ if (tp->mii_advertise) {
+ tp->advertising[phy_idx] =
+ to_advert = tp->mii_advertise;
+ } else if (tp->advertising[phy_idx]) {
+ to_advert = tp->advertising[phy_idx];
+ } else {
+ tp->advertising[phy_idx] =
+ tp->mii_advertise =
+ to_advert = mii_advert;
+ }
+
+ tp->phys[phy_idx++] = phy;
+
+ pr_info("tulip%d: MII transceiver #%d config %04x status %04x advertising %04x\n",
+ board_idx, phy, mii_reg0, mii_status, mii_advert);
+
+ /* Fixup for DLink with miswired PHY. */
+ if (mii_advert != to_advert) {
+ pr_debug("tulip%d: Advertising %04x on PHY %d, previously advertising %04x\n",
+ board_idx, to_advert, phy, mii_advert);
+ tulip_mdio_write (dev, phy, 4, to_advert);
+ }
+
+ /* Enable autonegotiation: some boards default to off. */
+ if (tp->default_port == 0) {
+ new_bmcr = mii_reg0 | BMCR_ANENABLE;
+ if (new_bmcr != mii_reg0) {
+ new_bmcr |= BMCR_ANRESTART;
+ ane_switch = 1;
+ }
+ }
+ /* ...or disable nway, if forcing media */
+ else {
+ new_bmcr = mii_reg0 & ~BMCR_ANENABLE;
+ if (new_bmcr != mii_reg0)
+ ane_switch = 1;
+ }
+
+ /* clear out bits we never want at this point */
+ new_bmcr &= ~(BMCR_CTST | BMCR_FULLDPLX | BMCR_ISOLATE |
+ BMCR_PDOWN | BMCR_SPEED100 | BMCR_LOOPBACK |
+ BMCR_RESET);
+
+ if (tp->full_duplex)
+ new_bmcr |= BMCR_FULLDPLX;
+ if (tulip_media_cap[tp->default_port] & MediaIs100)
+ new_bmcr |= BMCR_SPEED100;
+
+ if (new_bmcr != mii_reg0) {
+ /* some phys need the ANE switch to
+ * happen before forced media settings
+ * will "take." However, we write the
+ * same value twice in order not to
+ * confuse the sane phys.
+ */
+ if (ane_switch) {
+ tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
+ udelay (10);
+ }
+ tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
+ }
+ }
+ tp->mii_cnt = phy_idx;
+ if (tp->mtable && tp->mtable->has_mii && phy_idx == 0) {
+ pr_info("tulip%d: ***WARNING***: No MII transceiver found!\n",
+ board_idx);
+ tp->phys[0] = 1;
+ }
+}
diff --git a/drivers/net/ethernet/dec/tulip/pnic.c b/drivers/net/ethernet/dec/tulip/pnic.c
new file mode 100644
index 000000000..653bde48e
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/pnic.c
@@ -0,0 +1,170 @@
+/*
+ drivers/net/ethernet/dec/tulip/pnic.c
+
+ Copyright 2000,2001 The Linux Kernel Team
+ Written/copyright 1994-2001 by Donald Becker.
+
+ This software may be used and distributed according to the terms
+ of the GNU General Public License, incorporated herein by reference.
+
+ Please submit bugs to http://bugzilla.kernel.org/ .
+*/
+
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/jiffies.h>
+#include "tulip.h"
+
+
+void pnic_do_nway(struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+ u32 phy_reg = ioread32(ioaddr + 0xB8);
+ u32 new_csr6;
+
+ if (phy_reg & 0x78000000) { /* Ignore baseT4 */
+ if (phy_reg & 0x20000000) dev->if_port = 5;
+ else if (phy_reg & 0x40000000) dev->if_port = 3;
+ else if (phy_reg & 0x10000000) dev->if_port = 4;
+ else if (phy_reg & 0x08000000) dev->if_port = 0;
+ tp->nwayset = 1;
+ new_csr6 = (dev->if_port & 1) ? 0x01860000 : 0x00420000;
+ iowrite32(0x32 | (dev->if_port & 1), ioaddr + CSR12);
+ if (dev->if_port & 1)
+ iowrite32(0x1F868, ioaddr + 0xB8);
+ if (phy_reg & 0x30000000) {
+ tp->full_duplex = 1;
+ new_csr6 |= 0x00000200;
+ }
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "PNIC autonegotiated status %08x, %s\n",
+ phy_reg, medianame[dev->if_port]);
+ if (tp->csr6 != new_csr6) {
+ tp->csr6 = new_csr6;
+ /* Restart Tx */
+ tulip_restart_rxtx(tp);
+ netif_trans_update(dev);
+ }
+ }
+}
+
+void pnic_lnk_change(struct net_device *dev, int csr5)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+ int phy_reg = ioread32(ioaddr + 0xB8);
+
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "PNIC link changed state %08x, CSR5 %08x\n",
+ phy_reg, csr5);
+ if (ioread32(ioaddr + CSR5) & TPLnkFail) {
+ iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkFail) | TPLnkPass, ioaddr + CSR7);
+ /* If we use an external MII, then we mustn't use the
+ * internal negotiation.
+ */
+ if (tulip_media_cap[dev->if_port] & MediaIsMII)
+ return;
+ if (! tp->nwayset || time_after(jiffies, dev_trans_start(dev) + 1*HZ)) {
+ tp->csr6 = 0x00420000 | (tp->csr6 & 0x0000fdff);
+ iowrite32(tp->csr6, ioaddr + CSR6);
+ iowrite32(0x30, ioaddr + CSR12);
+ iowrite32(0x0201F078, ioaddr + 0xB8); /* Turn on autonegotiation. */
+ netif_trans_update(dev);
+ }
+ } else if (ioread32(ioaddr + CSR5) & TPLnkPass) {
+ if (tulip_media_cap[dev->if_port] & MediaIsMII) {
+ spin_lock(&tp->lock);
+ tulip_check_duplex(dev);
+ spin_unlock(&tp->lock);
+ } else {
+ pnic_do_nway(dev);
+ }
+ iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkPass) | TPLnkFail, ioaddr + CSR7);
+ }
+}
+
+void pnic_timer(struct timer_list *t)
+{
+ struct tulip_private *tp = from_timer(tp, t, timer);
+ struct net_device *dev = tp->dev;
+ void __iomem *ioaddr = tp->base_addr;
+ int next_tick = 60*HZ;
+
+ if(!ioread32(ioaddr + CSR7)) {
+ /* the timer was called due to a work overflow
+ * in the interrupt handler. Skip the connection
+ * checks, the nic is definitively speaking with
+ * his link partner.
+ */
+ goto too_good_connection;
+ }
+
+ if (tulip_media_cap[dev->if_port] & MediaIsMII) {
+ spin_lock_irq(&tp->lock);
+ if (tulip_check_duplex(dev) > 0)
+ next_tick = 3*HZ;
+ spin_unlock_irq(&tp->lock);
+ } else {
+ int csr12 = ioread32(ioaddr + CSR12);
+ int new_csr6 = tp->csr6 & ~0x40C40200;
+ int phy_reg = ioread32(ioaddr + 0xB8);
+ int csr5 = ioread32(ioaddr + CSR5);
+
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "PNIC timer PHY status %08x, %s CSR5 %08x\n",
+ phy_reg, medianame[dev->if_port], csr5);
+ if (phy_reg & 0x04000000) { /* Remote link fault */
+ iowrite32(0x0201F078, ioaddr + 0xB8);
+ next_tick = 1*HZ;
+ tp->nwayset = 0;
+ } else if (phy_reg & 0x78000000) { /* Ignore baseT4 */
+ pnic_do_nway(dev);
+ next_tick = 60*HZ;
+ } else if (csr5 & TPLnkFail) { /* 100baseTx link beat */
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "%s link beat failed, CSR12 %04x, CSR5 %08x, PHY %03x\n",
+ medianame[dev->if_port],
+ csr12,
+ ioread32(ioaddr + CSR5),
+ ioread32(ioaddr + 0xB8));
+ next_tick = 3*HZ;
+ if (tp->medialock) {
+ } else if (tp->nwayset && (dev->if_port & 1)) {
+ next_tick = 1*HZ;
+ } else if (dev->if_port == 0) {
+ dev->if_port = 3;
+ iowrite32(0x33, ioaddr + CSR12);
+ new_csr6 = 0x01860000;
+ iowrite32(0x1F868, ioaddr + 0xB8);
+ } else {
+ dev->if_port = 0;
+ iowrite32(0x32, ioaddr + CSR12);
+ new_csr6 = 0x00420000;
+ iowrite32(0x1F078, ioaddr + 0xB8);
+ }
+ if (tp->csr6 != new_csr6) {
+ tp->csr6 = new_csr6;
+ /* Restart Tx */
+ tulip_restart_rxtx(tp);
+ netif_trans_update(dev);
+ if (tulip_debug > 1)
+ dev_info(&dev->dev,
+ "Changing PNIC configuration to %s %s-duplex, CSR6 %08x\n",
+ medianame[dev->if_port],
+ tp->full_duplex ? "full" : "half",
+ new_csr6);
+ }
+ }
+ }
+too_good_connection:
+ mod_timer(&tp->timer, RUN_AT(next_tick));
+ if(!ioread32(ioaddr + CSR7)) {
+ if (tulip_debug > 1)
+ dev_info(&dev->dev, "sw timer wakeup\n");
+ disable_irq(dev->irq);
+ tulip_refill_rx(dev);
+ enable_irq(dev->irq);
+ iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
+ }
+}
diff --git a/drivers/net/ethernet/dec/tulip/pnic2.c b/drivers/net/ethernet/dec/tulip/pnic2.c
new file mode 100644
index 000000000..72a09156b
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/pnic2.c
@@ -0,0 +1,403 @@
+/*
+ drivers/net/ethernet/dec/tulip/pnic2.c
+
+ Copyright 2000,2001 The Linux Kernel Team
+ Written/copyright 1994-2001 by Donald Becker.
+ Modified to hep support PNIC_II by Kevin B. Hendricks
+
+ This software may be used and distributed according to the terms
+ of the GNU General Public License, incorporated herein by reference.
+
+ Please submit bugs to http://bugzilla.kernel.org/ .
+*/
+
+
+/* Understanding the PNIC_II - everything is this file is based
+ * on the PNIC_II_PDF datasheet which is sorely lacking in detail
+ *
+ * As I understand things, here are the registers and bits that
+ * explain the masks and constants used in this file that are
+ * either different from the 21142/3 or important for basic operation.
+ *
+ *
+ * CSR 6 (mask = 0xfe3bd1fd of bits not to change)
+ * -----
+ * Bit 24 - SCR
+ * Bit 23 - PCS
+ * Bit 22 - TTM (Trasmit Threshold Mode)
+ * Bit 18 - Port Select
+ * Bit 13 - Start - 1, Stop - 0 Transmissions
+ * Bit 11:10 - Loop Back Operation Mode
+ * Bit 9 - Full Duplex mode (Advertise 10BaseT-FD is CSR14<7> is set)
+ * Bit 1 - Start - 1, Stop - 0 Receive
+ *
+ *
+ * CSR 14 (mask = 0xfff0ee39 of bits not to change)
+ * ------
+ * Bit 19 - PAUSE-Pause
+ * Bit 18 - Advertise T4
+ * Bit 17 - Advertise 100baseTx-FD
+ * Bit 16 - Advertise 100baseTx-HD
+ * Bit 12 - LTE - Link Test Enable
+ * Bit 7 - ANE - Auto Negotiate Enable
+ * Bit 6 - HDE - Advertise 10baseT-HD
+ * Bit 2 - Reset to Power down - kept as 1 for normal operation
+ * Bit 1 - Loop Back enable for 10baseT MCC
+ *
+ *
+ * CSR 12
+ * ------
+ * Bit 25 - Partner can do T4
+ * Bit 24 - Partner can do 100baseTx-FD
+ * Bit 23 - Partner can do 100baseTx-HD
+ * Bit 22 - Partner can do 10baseT-FD
+ * Bit 21 - Partner can do 10baseT-HD
+ * Bit 15 - LPN is 1 if all above bits are valid other wise 0
+ * Bit 14:12 - autonegotiation state (write 001 to start autonegotiate)
+ * Bit 3 - Autopolarity state
+ * Bit 2 - LS10B - link state of 10baseT 0 - good, 1 - failed
+ * Bit 1 - LS100B - link state of 100baseT 0 - good, 1 - failed
+ *
+ *
+ * Data Port Selection Info
+ *-------------------------
+ *
+ * CSR14<7> CSR6<18> CSR6<22> CSR6<23> CSR6<24> MODE/PORT
+ * 1 0 0 (X) 0 (X) 1 NWAY
+ * 0 0 1 0 (X) 0 10baseT
+ * 0 1 0 1 1 (X) 100baseT
+ *
+ *
+ */
+
+
+
+#include "tulip.h"
+#include <linux/delay.h>
+
+
+void pnic2_timer(struct timer_list *t)
+{
+ struct tulip_private *tp = from_timer(tp, t, timer);
+ struct net_device *dev = tp->dev;
+ void __iomem *ioaddr = tp->base_addr;
+ int next_tick = 60*HZ;
+
+ if (tulip_debug > 3)
+ dev_info(&dev->dev, "PNIC2 negotiation status %08x\n",
+ ioread32(ioaddr + CSR12));
+
+ if (next_tick) {
+ mod_timer(&tp->timer, RUN_AT(next_tick));
+ }
+}
+
+
+void pnic2_start_nway(struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+ int csr14;
+ int csr12;
+
+ /* set up what to advertise during the negotiation */
+
+ /* load in csr14 and mask off bits not to touch
+ * comment at top of file explains mask value
+ */
+ csr14 = (ioread32(ioaddr + CSR14) & 0xfff0ee39);
+
+ /* bit 17 - advetise 100baseTx-FD */
+ if (tp->sym_advertise & 0x0100) csr14 |= 0x00020000;
+
+ /* bit 16 - advertise 100baseTx-HD */
+ if (tp->sym_advertise & 0x0080) csr14 |= 0x00010000;
+
+ /* bit 6 - advertise 10baseT-HD */
+ if (tp->sym_advertise & 0x0020) csr14 |= 0x00000040;
+
+ /* Now set bit 12 Link Test Enable, Bit 7 Autonegotiation Enable
+ * and bit 0 Don't PowerDown 10baseT
+ */
+ csr14 |= 0x00001184;
+
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "Restarting PNIC2 autonegotiation, csr14=%08x\n",
+ csr14);
+
+ /* tell pnic2_lnk_change we are doing an nway negotiation */
+ dev->if_port = 0;
+ tp->nway = tp->mediasense = 1;
+ tp->nwayset = tp->lpar = 0;
+
+ /* now we have to set up csr6 for NWAY state */
+
+ tp->csr6 = ioread32(ioaddr + CSR6);
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "On Entry to Nway, csr6=%08x\n", tp->csr6);
+
+ /* mask off any bits not to touch
+ * comment at top of file explains mask value
+ */
+ tp->csr6 = tp->csr6 & 0xfe3bd1fd;
+
+ /* don't forget that bit 9 is also used for advertising */
+ /* advertise 10baseT-FD for the negotiation (bit 9) */
+ if (tp->sym_advertise & 0x0040) tp->csr6 |= 0x00000200;
+
+ /* set bit 24 for nway negotiation mode ...
+ * see Data Port Selection comment at top of file
+ * and "Stop" - reset both Transmit (bit 13) and Receive (bit 1)
+ */
+ tp->csr6 |= 0x01000000;
+ iowrite32(csr14, ioaddr + CSR14);
+ iowrite32(tp->csr6, ioaddr + CSR6);
+ udelay(100);
+
+ /* all set up so now force the negotiation to begin */
+
+ /* read in current values and mask off all but the
+ * Autonegotiation bits 14:12. Writing a 001 to those bits
+ * should start the autonegotiation
+ */
+ csr12 = (ioread32(ioaddr + CSR12) & 0xffff8fff);
+ csr12 |= 0x1000;
+ iowrite32(csr12, ioaddr + CSR12);
+}
+
+
+
+void pnic2_lnk_change(struct net_device *dev, int csr5)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+ int csr14;
+
+ /* read the staus register to find out what is up */
+ int csr12 = ioread32(ioaddr + CSR12);
+
+ if (tulip_debug > 1)
+ dev_info(&dev->dev,
+ "PNIC2 link status interrupt %08x, CSR5 %x, %08x\n",
+ csr12, csr5, ioread32(ioaddr + CSR14));
+
+ /* If NWay finished and we have a negotiated partner capability.
+ * check bits 14:12 for bit pattern 101 - all is good
+ */
+ if (tp->nway && !tp->nwayset) {
+
+ /* we did an auto negotiation */
+
+ if ((csr12 & 0x7000) == 0x5000) {
+
+ /* negotiation ended successfully */
+
+ /* get the link partners reply and mask out all but
+ * bits 24-21 which show the partners capabilities
+ * and match those to what we advertised
+ *
+ * then begin to interpret the results of the negotiation.
+ * Always go in this order : (we are ignoring T4 for now)
+ * 100baseTx-FD, 100baseTx-HD, 10baseT-FD, 10baseT-HD
+ */
+
+ int negotiated = ((csr12 >> 16) & 0x01E0) & tp->sym_advertise;
+ tp->lpar = (csr12 >> 16);
+ tp->nwayset = 1;
+
+ if (negotiated & 0x0100) dev->if_port = 5;
+ else if (negotiated & 0x0080) dev->if_port = 3;
+ else if (negotiated & 0x0040) dev->if_port = 4;
+ else if (negotiated & 0x0020) dev->if_port = 0;
+ else {
+ if (tulip_debug > 1)
+ dev_info(&dev->dev,
+ "funny autonegotiate result csr12 %08x advertising %04x\n",
+ csr12, tp->sym_advertise);
+ tp->nwayset = 0;
+ /* so check if 100baseTx link state is okay */
+ if ((csr12 & 2) == 0 && (tp->sym_advertise & 0x0180))
+ dev->if_port = 3;
+ }
+
+ /* now record the duplex that was negotiated */
+ tp->full_duplex = 0;
+ if ((dev->if_port == 4) || (dev->if_port == 5))
+ tp->full_duplex = 1;
+
+ if (tulip_debug > 1) {
+ if (tp->nwayset)
+ dev_info(&dev->dev,
+ "Switching to %s based on link negotiation %04x & %04x = %04x\n",
+ medianame[dev->if_port],
+ tp->sym_advertise, tp->lpar,
+ negotiated);
+ }
+
+ /* remember to turn off bit 7 - autonegotiate
+ * enable so we can properly end nway mode and
+ * set duplex (ie. use csr6<9> again)
+ */
+ csr14 = (ioread32(ioaddr + CSR14) & 0xffffff7f);
+ iowrite32(csr14,ioaddr + CSR14);
+
+
+ /* now set the data port and operating mode
+ * (see the Data Port Selection comments at
+ * the top of the file
+ */
+
+ /* get current csr6 and mask off bits not to touch */
+ /* see comment at top of file */
+
+ tp->csr6 = (ioread32(ioaddr + CSR6) & 0xfe3bd1fd);
+
+ /* so if using if_port 3 or 5 then select the 100baseT
+ * port else select the 10baseT port.
+ * See the Data Port Selection table at the top
+ * of the file which was taken from the PNIC_II.PDF
+ * datasheet
+ */
+ if (dev->if_port & 1) tp->csr6 |= 0x01840000;
+ else tp->csr6 |= 0x00400000;
+
+ /* now set the full duplex bit appropriately */
+ if (tp->full_duplex) tp->csr6 |= 0x00000200;
+
+ iowrite32(1, ioaddr + CSR13);
+
+ if (tulip_debug > 2)
+ netdev_dbg(dev, "Setting CSR6 %08x/%x CSR12 %08x\n",
+ tp->csr6,
+ ioread32(ioaddr + CSR6),
+ ioread32(ioaddr + CSR12));
+
+ /* now the following actually writes out the
+ * new csr6 values
+ */
+ tulip_start_rxtx(tp);
+
+ return;
+
+ } else {
+ dev_info(&dev->dev,
+ "Autonegotiation failed, using %s, link beat status %04x\n",
+ medianame[dev->if_port], csr12);
+
+ /* remember to turn off bit 7 - autonegotiate
+ * enable so we don't forget
+ */
+ csr14 = (ioread32(ioaddr + CSR14) & 0xffffff7f);
+ iowrite32(csr14,ioaddr + CSR14);
+
+ /* what should we do when autonegotiate fails?
+ * should we try again or default to baseline
+ * case. I just don't know.
+ *
+ * for now default to some baseline case
+ */
+
+ dev->if_port = 0;
+ tp->nway = 0;
+ tp->nwayset = 1;
+
+ /* set to 10baseTx-HD - see Data Port Selection
+ * comment given at the top of the file
+ */
+ tp->csr6 = (ioread32(ioaddr + CSR6) & 0xfe3bd1fd);
+ tp->csr6 |= 0x00400000;
+
+ tulip_restart_rxtx(tp);
+
+ return;
+
+ }
+ }
+
+ if ((tp->nwayset && (csr5 & 0x08000000) &&
+ (dev->if_port == 3 || dev->if_port == 5) &&
+ (csr12 & 2) == 2) || (tp->nway && (csr5 & (TPLnkFail)))) {
+
+ /* Link blew? Maybe restart NWay. */
+
+ if (tulip_debug > 2)
+ netdev_dbg(dev, "Ugh! Link blew?\n");
+
+ del_timer_sync(&tp->timer);
+ pnic2_start_nway(dev);
+ tp->timer.expires = RUN_AT(3*HZ);
+ add_timer(&tp->timer);
+
+ return;
+ }
+
+
+ if (dev->if_port == 3 || dev->if_port == 5) {
+
+ /* we are at 100mb and a potential link change occurred */
+
+ if (tulip_debug > 1)
+ dev_info(&dev->dev, "PNIC2 %s link beat %s\n",
+ medianame[dev->if_port],
+ (csr12 & 2) ? "failed" : "good");
+
+ /* check 100 link beat */
+
+ tp->nway = 0;
+ tp->nwayset = 1;
+
+ /* if failed then try doing an nway to get in sync */
+ if ((csr12 & 2) && ! tp->medialock) {
+ del_timer_sync(&tp->timer);
+ pnic2_start_nway(dev);
+ tp->timer.expires = RUN_AT(3*HZ);
+ add_timer(&tp->timer);
+ }
+
+ return;
+ }
+
+ if (dev->if_port == 0 || dev->if_port == 4) {
+
+ /* we are at 10mb and a potential link change occurred */
+
+ if (tulip_debug > 1)
+ dev_info(&dev->dev, "PNIC2 %s link beat %s\n",
+ medianame[dev->if_port],
+ (csr12 & 4) ? "failed" : "good");
+
+
+ tp->nway = 0;
+ tp->nwayset = 1;
+
+ /* if failed, try doing an nway to get in sync */
+ if ((csr12 & 4) && ! tp->medialock) {
+ del_timer_sync(&tp->timer);
+ pnic2_start_nway(dev);
+ tp->timer.expires = RUN_AT(3*HZ);
+ add_timer(&tp->timer);
+ }
+
+ return;
+ }
+
+
+ if (tulip_debug > 1)
+ dev_info(&dev->dev, "PNIC2 Link Change Default?\n");
+
+ /* if all else fails default to trying 10baseT-HD */
+ dev->if_port = 0;
+
+ /* make sure autonegotiate enable is off */
+ csr14 = (ioread32(ioaddr + CSR14) & 0xffffff7f);
+ iowrite32(csr14,ioaddr + CSR14);
+
+ /* set to 10baseTx-HD - see Data Port Selection
+ * comment given at the top of the file
+ */
+ tp->csr6 = (ioread32(ioaddr + CSR6) & 0xfe3bd1fd);
+ tp->csr6 |= 0x00400000;
+
+ tulip_restart_rxtx(tp);
+}
+
diff --git a/drivers/net/ethernet/dec/tulip/timer.c b/drivers/net/ethernet/dec/tulip/timer.c
new file mode 100644
index 000000000..642e9dfc5
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/timer.c
@@ -0,0 +1,176 @@
+/*
+ drivers/net/ethernet/dec/tulip/timer.c
+
+ Copyright 2000,2001 The Linux Kernel Team
+ Written/copyright 1994-2001 by Donald Becker.
+
+ This software may be used and distributed according to the terms
+ of the GNU General Public License, incorporated herein by reference.
+
+ Please submit bugs to http://bugzilla.kernel.org/ .
+*/
+
+
+#include "tulip.h"
+
+
+void tulip_media_task(struct work_struct *work)
+{
+ struct tulip_private *tp =
+ container_of(work, struct tulip_private, media_work);
+ struct net_device *dev = tp->dev;
+ void __iomem *ioaddr = tp->base_addr;
+ u32 csr12 = ioread32(ioaddr + CSR12);
+ int next_tick = 2*HZ;
+ unsigned long flags;
+
+ if (tulip_debug > 2) {
+ netdev_dbg(dev, "Media selection tick, %s, status %08x mode %08x SIA %08x %08x %08x %08x\n",
+ medianame[dev->if_port],
+ ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR6),
+ csr12, ioread32(ioaddr + CSR13),
+ ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
+ }
+ switch (tp->chip_id) {
+ case DC21140:
+ case DC21142:
+ case MX98713:
+ case COMPEX9881:
+ case DM910X:
+ default: {
+ struct medialeaf *mleaf;
+ unsigned char *p;
+ if (tp->mtable == NULL) { /* No EEPROM info, use generic code. */
+ /* Not much that can be done.
+ Assume this a generic MII or SYM transceiver. */
+ next_tick = 60*HZ;
+ if (tulip_debug > 2)
+ netdev_dbg(dev, "network media monitor CSR6 %08x CSR12 0x%02x\n",
+ ioread32(ioaddr + CSR6),
+ csr12 & 0xff);
+ break;
+ }
+ mleaf = &tp->mtable->mleaf[tp->cur_index];
+ p = mleaf->leafdata;
+ switch (mleaf->type) {
+ case 0: case 4: {
+ /* Type 0 serial or 4 SYM transceiver. Check the link beat bit. */
+ int offset = mleaf->type == 4 ? 5 : 2;
+ s8 bitnum = p[offset];
+ if (p[offset+1] & 0x80) {
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "Transceiver monitor tick CSR12=%#02x, no media sense\n",
+ csr12);
+ if (mleaf->type == 4) {
+ if (mleaf->media == 3 && (csr12 & 0x02))
+ goto select_next_media;
+ }
+ break;
+ }
+ if (tulip_debug > 2)
+ netdev_dbg(dev, "Transceiver monitor tick: CSR12=%#02x bit %d is %d, expecting %d\n",
+ csr12, (bitnum >> 1) & 7,
+ (csr12 & (1 << ((bitnum >> 1) & 7))) != 0,
+ (bitnum >= 0));
+ /* Check that the specified bit has the proper value. */
+ if ((bitnum < 0) !=
+ ((csr12 & (1 << ((bitnum >> 1) & 7))) != 0)) {
+ if (tulip_debug > 2)
+ netdev_dbg(dev, "Link beat detected for %s\n",
+ medianame[mleaf->media & MEDIA_MASK]);
+ if ((p[2] & 0x61) == 0x01) /* Bogus Znyx board. */
+ goto actually_mii;
+ netif_carrier_on(dev);
+ break;
+ }
+ netif_carrier_off(dev);
+ if (tp->medialock)
+ break;
+ select_next_media:
+ if (--tp->cur_index < 0) {
+ /* We start again, but should instead look for default. */
+ tp->cur_index = tp->mtable->leafcount - 1;
+ }
+ dev->if_port = tp->mtable->mleaf[tp->cur_index].media;
+ if (tulip_media_cap[dev->if_port] & MediaIsFD)
+ goto select_next_media; /* Skip FD entries. */
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "No link beat on media %s, trying transceiver type %s\n",
+ medianame[mleaf->media & MEDIA_MASK],
+ medianame[tp->mtable->mleaf[tp->cur_index].media]);
+ tulip_select_media(dev, 0);
+ /* Restart the transmit process. */
+ tulip_restart_rxtx(tp);
+ next_tick = (24*HZ)/10;
+ break;
+ }
+ case 1: case 3: /* 21140, 21142 MII */
+ actually_mii:
+ if (tulip_check_duplex(dev) < 0) {
+ netif_carrier_off(dev);
+ next_tick = 3*HZ;
+ } else {
+ netif_carrier_on(dev);
+ next_tick = 60*HZ;
+ }
+ break;
+ case 2: /* 21142 serial block has no link beat. */
+ default:
+ break;
+ }
+ }
+ break;
+ }
+
+
+ spin_lock_irqsave(&tp->lock, flags);
+ if (tp->timeout_recovery) {
+ tulip_tx_timeout_complete(tp, ioaddr);
+ tp->timeout_recovery = 0;
+ }
+ spin_unlock_irqrestore(&tp->lock, flags);
+
+ /* mod_timer synchronizes us with potential add_timer calls
+ * from interrupts.
+ */
+ mod_timer(&tp->timer, RUN_AT(next_tick));
+}
+
+
+void mxic_timer(struct timer_list *t)
+{
+ struct tulip_private *tp = from_timer(tp, t, timer);
+ struct net_device *dev = tp->dev;
+ void __iomem *ioaddr = tp->base_addr;
+ int next_tick = 60*HZ;
+
+ if (tulip_debug > 3) {
+ dev_info(&dev->dev, "MXIC negotiation status %08x\n",
+ ioread32(ioaddr + CSR12));
+ }
+ if (next_tick) {
+ mod_timer(&tp->timer, RUN_AT(next_tick));
+ }
+}
+
+
+void comet_timer(struct timer_list *t)
+{
+ struct tulip_private *tp = from_timer(tp, t, timer);
+ struct net_device *dev = tp->dev;
+ int next_tick = 2*HZ;
+
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "Comet link status %04x partner capability %04x\n",
+ tulip_mdio_read(dev, tp->phys[0], 1),
+ tulip_mdio_read(dev, tp->phys[0], 5));
+ /* mod_timer synchronizes us with potential add_timer calls
+ * from interrupts.
+ */
+ if (tulip_check_duplex(dev) < 0)
+ { netif_carrier_off(dev); }
+ else
+ { netif_carrier_on(dev); }
+ mod_timer(&tp->timer, RUN_AT(next_tick));
+}
+
diff --git a/drivers/net/ethernet/dec/tulip/tulip.h b/drivers/net/ethernet/dec/tulip/tulip.h
new file mode 100644
index 000000000..0ed598dc7
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/tulip.h
@@ -0,0 +1,569 @@
+/*
+ drivers/net/ethernet/dec/tulip/tulip.h
+
+ Copyright 2000,2001 The Linux Kernel Team
+ Written/copyright 1994-2001 by Donald Becker.
+
+ This software may be used and distributed according to the terms
+ of the GNU General Public License, incorporated herein by reference.
+
+ Please submit bugs to http://bugzilla.kernel.org/ .
+*/
+
+#ifndef __NET_TULIP_H__
+#define __NET_TULIP_H__
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/netdevice.h>
+#include <linux/ethtool.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/unaligned.h>
+
+
+
+/* undefine, or define to various debugging levels (>4 == obscene levels) */
+#define TULIP_DEBUG 1
+
+#ifdef CONFIG_TULIP_MMIO
+#define TULIP_BAR 1 /* CBMA */
+#else
+#define TULIP_BAR 0 /* CBIO */
+#endif
+
+
+
+struct tulip_chip_table {
+ char *chip_name;
+ int io_size;
+ int valid_intrs; /* CSR7 interrupt enable settings */
+ int flags;
+ void (*media_timer) (struct timer_list *);
+ work_func_t media_task;
+};
+
+
+enum tbl_flag {
+ HAS_MII = 0x00001,
+ HAS_MEDIA_TABLE = 0x00002,
+ CSR12_IN_SROM = 0x00004,
+ ALWAYS_CHECK_MII = 0x00008,
+ HAS_ACPI = 0x00010,
+ MC_HASH_ONLY = 0x00020, /* Hash-only multicast filter. */
+ HAS_PNICNWAY = 0x00080,
+ HAS_NWAY = 0x00040, /* Uses internal NWay xcvr. */
+ HAS_INTR_MITIGATION = 0x00100,
+ IS_ASIX = 0x00200,
+ HAS_8023X = 0x00400,
+ COMET_MAC_ADDR = 0x00800,
+ HAS_PCI_MWI = 0x01000,
+ HAS_PHY_IRQ = 0x02000,
+ HAS_SWAPPED_SEEPROM = 0x04000,
+ NEEDS_FAKE_MEDIA_TABLE = 0x08000,
+ COMET_PM = 0x10000,
+};
+
+
+/* chip types. careful! order is VERY IMPORTANT here, as these
+ * are used throughout the driver as indices into arrays */
+/* Note 21142 == 21143. */
+enum chips {
+ DC21040 = 0,
+ DC21041 = 1,
+ DC21140 = 2,
+ DC21142 = 3, DC21143 = 3,
+ LC82C168,
+ MX98713,
+ MX98715,
+ MX98725,
+ AX88140,
+ PNIC2,
+ COMET,
+ COMPEX9881,
+ I21145,
+ DM910X,
+ CONEXANT,
+};
+
+
+enum MediaIs {
+ MediaIsFD = 1,
+ MediaAlwaysFD = 2,
+ MediaIsMII = 4,
+ MediaIsFx = 8,
+ MediaIs100 = 16
+};
+
+
+/* Offsets to the Command and Status Registers, "CSRs". All accesses
+ must be longword instructions and quadword aligned. */
+enum tulip_offsets {
+ CSR0 = 0,
+ CSR1 = 0x08,
+ CSR2 = 0x10,
+ CSR3 = 0x18,
+ CSR4 = 0x20,
+ CSR5 = 0x28,
+ CSR6 = 0x30,
+ CSR7 = 0x38,
+ CSR8 = 0x40,
+ CSR9 = 0x48,
+ CSR10 = 0x50,
+ CSR11 = 0x58,
+ CSR12 = 0x60,
+ CSR13 = 0x68,
+ CSR14 = 0x70,
+ CSR15 = 0x78,
+ CSR18 = 0x88,
+ CSR19 = 0x8c,
+ CSR20 = 0x90,
+ CSR27 = 0xAC,
+ CSR28 = 0xB0,
+};
+
+/* register offset and bits for CFDD PCI config reg */
+enum pci_cfg_driver_reg {
+ CFDD = 0x40,
+ CFDD_Sleep = (1 << 31),
+ CFDD_Snooze = (1 << 30),
+};
+
+#define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)
+
+/* The bits in the CSR5 status registers, mostly interrupt sources. */
+enum status_bits {
+ TimerInt = 0x800,
+ SystemError = 0x2000,
+ TPLnkFail = 0x1000,
+ TPLnkPass = 0x10,
+ NormalIntr = 0x10000,
+ AbnormalIntr = 0x8000,
+ RxJabber = 0x200,
+ RxDied = 0x100,
+ RxNoBuf = 0x80,
+ RxIntr = 0x40,
+ TxFIFOUnderflow = 0x20,
+ RxErrIntr = 0x10,
+ TxJabber = 0x08,
+ TxNoBuf = 0x04,
+ TxDied = 0x02,
+ TxIntr = 0x01,
+};
+
+/* bit mask for CSR5 TX/RX process state */
+#define CSR5_TS 0x00700000
+#define CSR5_RS 0x000e0000
+
+enum tulip_mode_bits {
+ TxThreshold = (1 << 22),
+ FullDuplex = (1 << 9),
+ TxOn = 0x2000,
+ AcceptBroadcast = 0x0100,
+ AcceptAllMulticast = 0x0080,
+ AcceptAllPhys = 0x0040,
+ AcceptRunt = 0x0008,
+ RxOn = 0x0002,
+ RxTx = (TxOn | RxOn),
+};
+
+
+enum tulip_busconfig_bits {
+ MWI = (1 << 24),
+ MRL = (1 << 23),
+ MRM = (1 << 21),
+ CALShift = 14,
+ BurstLenShift = 8,
+};
+
+
+/* The Tulip Rx and Tx buffer descriptors. */
+struct tulip_rx_desc {
+ __le32 status;
+ __le32 length;
+ __le32 buffer1;
+ __le32 buffer2;
+};
+
+
+struct tulip_tx_desc {
+ __le32 status;
+ __le32 length;
+ __le32 buffer1;
+ __le32 buffer2; /* We use only buffer 1. */
+};
+
+
+enum desc_status_bits {
+ DescOwned = 0x80000000,
+ DescWholePkt = 0x60000000,
+ DescEndPkt = 0x40000000,
+ DescStartPkt = 0x20000000,
+ DescEndRing = 0x02000000,
+ DescUseLink = 0x01000000,
+
+ /*
+ * Error summary flag is logical or of 'CRC Error', 'Collision Seen',
+ * 'Frame Too Long', 'Runt' and 'Descriptor Error' flags generated
+ * within tulip chip.
+ */
+ RxDescErrorSummary = 0x8000,
+ RxDescCRCError = 0x0002,
+ RxDescCollisionSeen = 0x0040,
+
+ /*
+ * 'Frame Too Long' flag is set if packet length including CRC exceeds
+ * 1518. However, a full sized VLAN tagged frame is 1522 bytes
+ * including CRC.
+ *
+ * The tulip chip does not block oversized frames, and if this flag is
+ * set on a receive descriptor it does not indicate the frame has been
+ * truncated. The receive descriptor also includes the actual length.
+ * Therefore we can safety ignore this flag and check the length
+ * ourselves.
+ */
+ RxDescFrameTooLong = 0x0080,
+ RxDescRunt = 0x0800,
+ RxDescDescErr = 0x4000,
+ RxWholePkt = 0x00000300,
+ /*
+ * Top three bits of 14 bit frame length (status bits 27-29) should
+ * never be set as that would make frame over 2047 bytes. The Receive
+ * Watchdog flag (bit 4) may indicate the length is over 2048 and the
+ * length field is invalid.
+ */
+ RxLengthOver2047 = 0x38000010
+};
+
+
+enum t21143_csr6_bits {
+ csr6_sc = (1<<31),
+ csr6_ra = (1<<30),
+ csr6_ign_dest_msb = (1<<26),
+ csr6_mbo = (1<<25),
+ csr6_scr = (1<<24), /* scramble mode flag: can't be set */
+ csr6_pcs = (1<<23), /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
+ csr6_ttm = (1<<22), /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
+ csr6_sf = (1<<21), /* Store and forward. If set ignores TR bits */
+ csr6_hbd = (1<<19), /* Heart beat disable. Disables SQE function in 10baseT */
+ csr6_ps = (1<<18), /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
+ csr6_ca = (1<<17), /* Collision Offset Enable. If set uses special algorithm in low collision situations */
+ csr6_trh = (1<<15), /* Transmit Threshold high bit */
+ csr6_trl = (1<<14), /* Transmit Threshold low bit */
+
+ /***************************************************************
+ * This table shows transmit threshold values based on media *
+ * and these two registers (from PNIC1 & 2 docs) Note: this is *
+ * all meaningless if sf is set. *
+ ***************************************************************/
+
+ /***********************************
+ * (trh,trl) * 100BaseTX * 10BaseT *
+ ***********************************
+ * (0,0) * 128 * 72 *
+ * (0,1) * 256 * 96 *
+ * (1,0) * 512 * 128 *
+ * (1,1) * 1024 * 160 *
+ ***********************************/
+
+ csr6_fc = (1<<12), /* Forces a collision in next transmission (for testing in loopback mode) */
+ csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
+ csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
+ /* set both and you get (PHY) loopback */
+ csr6_fd = (1<<9), /* Full duplex mode, disables hearbeat, no loopback */
+ csr6_pm = (1<<7), /* Pass All Multicast */
+ csr6_pr = (1<<6), /* Promiscuous mode */
+ csr6_sb = (1<<5), /* Start(1)/Stop(0) backoff counter */
+ csr6_if = (1<<4), /* Inverse Filtering, rejects only addresses in address table: can't be set */
+ csr6_pb = (1<<3), /* Pass Bad Frames, (1) causes even bad frames to be passed on */
+ csr6_ho = (1<<2), /* Hash-only filtering mode: can't be set */
+ csr6_hp = (1<<0), /* Hash/Perfect Receive Filtering Mode: can't be set */
+
+ csr6_mask_capture = (csr6_sc | csr6_ca),
+ csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
+ csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
+ csr6_mask_hdcaptt = (csr6_mask_hdcap | csr6_trh | csr6_trl),
+ csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
+ csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
+ csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
+ csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
+};
+
+enum tulip_comet_csr13_bits {
+/* The LINKOFFE and LINKONE work in conjunction with LSCE, i.e. they
+ * determine which link status transition wakes up if LSCE is
+ * enabled */
+ comet_csr13_linkoffe = (1 << 17),
+ comet_csr13_linkone = (1 << 16),
+ comet_csr13_wfre = (1 << 10),
+ comet_csr13_mpre = (1 << 9),
+ comet_csr13_lsce = (1 << 8),
+ comet_csr13_wfr = (1 << 2),
+ comet_csr13_mpr = (1 << 1),
+ comet_csr13_lsc = (1 << 0),
+};
+
+enum tulip_comet_csr18_bits {
+ comet_csr18_pmes_sticky = (1 << 24),
+ comet_csr18_pm_mode = (1 << 19),
+ comet_csr18_apm_mode = (1 << 18),
+ comet_csr18_d3a = (1 << 7)
+};
+
+enum tulip_comet_csr20_bits {
+ comet_csr20_pmes = (1 << 15),
+};
+
+/* Keep the ring sizes a power of two for efficiency.
+ Making the Tx ring too large decreases the effectiveness of channel
+ bonding and packet priority.
+ There are no ill effects from too-large receive rings. */
+
+#define TX_RING_SIZE 32
+#define RX_RING_SIZE 128
+#define MEDIA_MASK 31
+
+/* The receiver on the DC21143 rev 65 can fail to close the last
+ * receive descriptor in certain circumstances (see errata) when
+ * using MWI. This can only occur if the receive buffer ends on
+ * a cache line boundary, so the "+ 4" below ensures it doesn't.
+ */
+#define PKT_BUF_SZ (1536 + 4) /* Size of each temporary Rx buffer. */
+
+#define TULIP_MIN_CACHE_LINE 8 /* in units of 32-bit words */
+
+#if defined(__sparc__) || defined(__hppa__)
+/* The UltraSparc PCI controllers will disconnect at every 64-byte
+ * crossing anyways so it makes no sense to tell Tulip to burst
+ * any more than that.
+ */
+#define TULIP_MAX_CACHE_LINE 16 /* in units of 32-bit words */
+#else
+#define TULIP_MAX_CACHE_LINE 32 /* in units of 32-bit words */
+#endif
+
+
+/* Ring-wrap flag in length field, use for last ring entry.
+ 0x01000000 means chain on buffer2 address,
+ 0x02000000 means use the ring start address in CSR2/3.
+ Note: Some work-alike chips do not function correctly in chained mode.
+ The ASIX chip works only in chained mode.
+ Thus we indicates ring mode, but always write the 'next' field for
+ chained mode as well.
+*/
+#define DESC_RING_WRAP 0x02000000
+
+
+#define EEPROM_SIZE 512 /* 2 << EEPROM_ADDRLEN */
+
+
+#define RUN_AT(x) (jiffies + (x))
+
+#define get_u16(ptr) get_unaligned_le16((ptr))
+
+struct medialeaf {
+ u8 type;
+ u8 media;
+ unsigned char *leafdata;
+};
+
+
+struct mediatable {
+ u16 defaultmedia;
+ u8 leafcount;
+ u8 csr12dir; /* General purpose pin directions. */
+ unsigned has_mii:1;
+ unsigned has_nonmii:1;
+ unsigned has_reset:6;
+ u32 csr15dir;
+ u32 csr15val; /* 21143 NWay setting. */
+ struct medialeaf mleaf[];
+};
+
+
+struct mediainfo {
+ struct mediainfo *next;
+ int info_type;
+ int index;
+ unsigned char *info;
+};
+
+struct ring_info {
+ struct sk_buff *skb;
+ dma_addr_t mapping;
+};
+
+
+struct tulip_private {
+ const char *product_name;
+ struct net_device *next_module;
+ struct tulip_rx_desc *rx_ring;
+ struct tulip_tx_desc *tx_ring;
+ dma_addr_t rx_ring_dma;
+ dma_addr_t tx_ring_dma;
+ /* The saved address of a sent-in-place packet/buffer, for skfree(). */
+ struct ring_info tx_buffers[TX_RING_SIZE];
+ /* The addresses of receive-in-place skbuffs. */
+ struct ring_info rx_buffers[RX_RING_SIZE];
+ u16 setup_frame[96]; /* Pseudo-Tx frame to init address table. */
+ int chip_id;
+ int revision;
+ int flags;
+ struct napi_struct napi;
+ struct timer_list timer; /* Media selection timer. */
+ struct timer_list oom_timer; /* Out of memory timer. */
+ u32 mc_filter[2];
+ spinlock_t lock;
+ spinlock_t mii_lock;
+ unsigned int cur_rx, cur_tx; /* The next free ring entry */
+ unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
+
+#ifdef CONFIG_TULIP_NAPI_HW_MITIGATION
+ int mit_on;
+#endif
+ unsigned int full_duplex:1; /* Full-duplex operation requested. */
+ unsigned int full_duplex_lock:1;
+ unsigned int fake_addr:1; /* Multiport board faked address. */
+ unsigned int default_port:4; /* Last dev->if_port value. */
+ unsigned int media2:4; /* Secondary monitored media port. */
+ unsigned int medialock:1; /* Don't sense media type. */
+ unsigned int mediasense:1; /* Media sensing in progress. */
+ unsigned int nway:1, nwayset:1; /* 21143 internal NWay. */
+ unsigned int timeout_recovery:1;
+ unsigned int csr0; /* CSR0 setting. */
+ unsigned int csr6; /* Current CSR6 control settings. */
+ unsigned char eeprom[EEPROM_SIZE]; /* Serial EEPROM contents. */
+ void (*link_change) (struct net_device * dev, int csr5);
+ struct ethtool_wolinfo wolinfo; /* WOL settings */
+ u16 sym_advertise, mii_advertise; /* NWay capabilities advertised. */
+ u16 lpar; /* 21143 Link partner ability. */
+ u16 advertising[4];
+ signed char phys[4], mii_cnt; /* MII device addresses. */
+ struct mediatable *mtable;
+ int cur_index; /* Current media index. */
+ int saved_if_port;
+ struct pci_dev *pdev;
+ int ttimer;
+ int susp_rx;
+ unsigned long nir;
+ void __iomem *base_addr;
+ int csr12_shadow;
+ int pad0; /* Used for 8-byte alignment */
+ struct work_struct media_work;
+ struct net_device *dev;
+};
+
+
+struct eeprom_fixup {
+ char *name;
+ unsigned char addr0;
+ unsigned char addr1;
+ unsigned char addr2;
+ u16 newtable[32]; /* Max length below. */
+};
+
+
+/* 21142.c */
+extern u16 t21142_csr14[];
+void t21142_media_task(struct work_struct *work);
+void t21142_start_nway(struct net_device *dev);
+void t21142_lnk_change(struct net_device *dev, int csr5);
+
+
+/* PNIC2.c */
+void pnic2_lnk_change(struct net_device *dev, int csr5);
+void pnic2_timer(struct timer_list *t);
+void pnic2_start_nway(struct net_device *dev);
+
+/* eeprom.c */
+void tulip_parse_eeprom(struct net_device *dev);
+int tulip_read_eeprom(struct net_device *dev, int location, int addr_len);
+
+/* interrupt.c */
+extern unsigned int tulip_max_interrupt_work;
+extern int tulip_rx_copybreak;
+irqreturn_t tulip_interrupt(int irq, void *dev_instance);
+int tulip_refill_rx(struct net_device *dev);
+#ifdef CONFIG_TULIP_NAPI
+int tulip_poll(struct napi_struct *napi, int budget);
+#endif
+
+
+/* media.c */
+int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
+void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
+void tulip_select_media(struct net_device *dev, int startup);
+int tulip_check_duplex(struct net_device *dev);
+void tulip_find_mii (struct net_device *dev, int board_idx);
+
+/* pnic.c */
+void pnic_do_nway(struct net_device *dev);
+void pnic_lnk_change(struct net_device *dev, int csr5);
+void pnic_timer(struct timer_list *t);
+
+/* timer.c */
+void tulip_media_task(struct work_struct *work);
+void mxic_timer(struct timer_list *t);
+void comet_timer(struct timer_list *t);
+
+/* tulip_core.c */
+extern int tulip_debug;
+extern const char * const medianame[];
+extern const char tulip_media_cap[];
+extern const struct tulip_chip_table tulip_tbl[];
+void oom_timer(struct timer_list *t);
+extern u8 t21040_csr13[];
+
+static inline void tulip_start_rxtx(struct tulip_private *tp)
+{
+ void __iomem *ioaddr = tp->base_addr;
+ iowrite32(tp->csr6 | RxTx, ioaddr + CSR6);
+ barrier();
+ (void) ioread32(ioaddr + CSR6); /* mmio sync */
+}
+
+static inline void tulip_stop_rxtx(struct tulip_private *tp)
+{
+ void __iomem *ioaddr = tp->base_addr;
+ u32 csr6 = ioread32(ioaddr + CSR6);
+
+ if (csr6 & RxTx) {
+ unsigned i=1300/10;
+ iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
+ barrier();
+ /* wait until in-flight frame completes.
+ * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
+ * Typically expect this loop to end in < 50 us on 100BT.
+ */
+ while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
+ udelay(10);
+
+ if (!i)
+ netdev_dbg(tp->dev, "tulip_stop_rxtx() failed (CSR5 0x%x CSR6 0x%x)\n",
+ ioread32(ioaddr + CSR5),
+ ioread32(ioaddr + CSR6));
+ }
+}
+
+static inline void tulip_restart_rxtx(struct tulip_private *tp)
+{
+ tulip_stop_rxtx(tp);
+ udelay(5);
+ tulip_start_rxtx(tp);
+}
+
+static inline void tulip_tx_timeout_complete(struct tulip_private *tp, void __iomem *ioaddr)
+{
+ /* Stop and restart the chip's Tx processes. */
+ tulip_restart_rxtx(tp);
+ /* Trigger an immediate transmit demand. */
+ iowrite32(0, ioaddr + CSR1);
+
+ tp->dev->stats.tx_errors++;
+}
+
+#endif /* __NET_TULIP_H__ */
diff --git a/drivers/net/ethernet/dec/tulip/tulip_core.c b/drivers/net/ethernet/dec/tulip/tulip_core.c
new file mode 100644
index 000000000..ecfad43df
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/tulip_core.c
@@ -0,0 +1,1934 @@
+/* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux.
+
+ Copyright 2000,2001 The Linux Kernel Team
+ Written/copyright 1994-2001 by Donald Becker.
+
+ This software may be used and distributed according to the terms
+ of the GNU General Public License, incorporated herein by reference.
+
+ Please submit bugs to http://bugzilla.kernel.org/ .
+*/
+
+#define pr_fmt(fmt) "tulip: " fmt
+
+#define DRV_NAME "tulip"
+
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include "tulip.h"
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/mii.h>
+#include <linux/crc32.h>
+#include <asm/unaligned.h>
+#include <linux/uaccess.h>
+
+#ifdef CONFIG_SPARC
+#include <asm/prom.h>
+#endif
+
+/* A few user-configurable values. */
+
+/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
+static unsigned int max_interrupt_work = 25;
+
+#define MAX_UNITS 8
+/* Used to pass the full-duplex flag, etc. */
+static int full_duplex[MAX_UNITS];
+static int options[MAX_UNITS];
+static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
+
+/* The possible media types that can be set in options[] are: */
+const char * const medianame[32] = {
+ "10baseT", "10base2", "AUI", "100baseTx",
+ "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
+ "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
+ "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
+ "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
+ "","","","", "","","","", "","","","Transceiver reset",
+};
+
+/* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
+#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
+ defined(CONFIG_SPARC) || defined(__ia64__) || \
+ defined(__sh__) || defined(__mips__)
+static int rx_copybreak = 1518;
+#else
+static int rx_copybreak = 100;
+#endif
+
+/*
+ Set the bus performance register.
+ Typical: Set 16 longword cache alignment, no burst limit.
+ Cache alignment bits 15:14 Burst length 13:8
+ 0000 No alignment 0x00000000 unlimited 0800 8 longwords
+ 4000 8 longwords 0100 1 longword 1000 16 longwords
+ 8000 16 longwords 0200 2 longwords 2000 32 longwords
+ C000 32 longwords 0400 4 longwords
+ Warning: many older 486 systems are broken and require setting 0x00A04800
+ 8 longword cache alignment, 8 longword burst.
+ ToDo: Non-Intel setting could be better.
+*/
+
+#if defined(__alpha__) || defined(__ia64__)
+static int csr0 = 0x01A00000 | 0xE000;
+#elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
+static int csr0 = 0x01A00000 | 0x8000;
+#elif defined(CONFIG_SPARC) || defined(__hppa__)
+/* The UltraSparc PCI controllers will disconnect at every 64-byte
+ * crossing anyways so it makes no sense to tell Tulip to burst
+ * any more than that.
+ */
+static int csr0 = 0x01A00000 | 0x9000;
+#elif defined(__arm__) || defined(__sh__)
+static int csr0 = 0x01A00000 | 0x4800;
+#elif defined(__mips__)
+static int csr0 = 0x00200000 | 0x4000;
+#else
+static int csr0;
+#endif
+
+/* Operational parameters that usually are not changed. */
+/* Time in jiffies before concluding the transmitter is hung. */
+#define TX_TIMEOUT (4*HZ)
+
+
+MODULE_AUTHOR("The Linux Kernel Team");
+MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
+MODULE_LICENSE("GPL");
+module_param(tulip_debug, int, 0);
+module_param(max_interrupt_work, int, 0);
+module_param(rx_copybreak, int, 0);
+module_param(csr0, int, 0);
+module_param_array(options, int, NULL, 0);
+module_param_array(full_duplex, int, NULL, 0);
+
+#ifdef TULIP_DEBUG
+int tulip_debug = TULIP_DEBUG;
+#else
+int tulip_debug = 1;
+#endif
+
+static void tulip_timer(struct timer_list *t)
+{
+ struct tulip_private *tp = from_timer(tp, t, timer);
+ struct net_device *dev = tp->dev;
+
+ if (netif_running(dev))
+ schedule_work(&tp->media_work);
+}
+
+/*
+ * This table use during operation for capabilities and media timer.
+ *
+ * It is indexed via the values in 'enum chips'
+ */
+
+const struct tulip_chip_table tulip_tbl[] = {
+ { }, /* placeholder for array, slot unused currently */
+ { }, /* placeholder for array, slot unused currently */
+
+ /* DC21140 */
+ { "Digital DS21140 Tulip", 128, 0x0001ebef,
+ HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
+ tulip_media_task },
+
+ /* DC21142, DC21143 */
+ { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
+ HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
+ | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
+
+ /* LC82C168 */
+ { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
+ HAS_MII | HAS_PNICNWAY, pnic_timer, },
+
+ /* MX98713 */
+ { "Macronix 98713 PMAC", 128, 0x0001ebef,
+ HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
+
+ /* MX98715 */
+ { "Macronix 98715 PMAC", 256, 0x0001ebef,
+ HAS_MEDIA_TABLE, mxic_timer, },
+
+ /* MX98725 */
+ { "Macronix 98725 PMAC", 256, 0x0001ebef,
+ HAS_MEDIA_TABLE, mxic_timer, },
+
+ /* AX88140 */
+ { "ASIX AX88140", 128, 0x0001fbff,
+ HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
+ | IS_ASIX, tulip_timer, tulip_media_task },
+
+ /* PNIC2 */
+ { "Lite-On PNIC-II", 256, 0x0801fbff,
+ HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
+
+ /* COMET */
+ { "ADMtek Comet", 256, 0x0001abef,
+ HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
+
+ /* COMPEX9881 */
+ { "Compex 9881 PMAC", 128, 0x0001ebef,
+ HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
+
+ /* I21145 */
+ { "Intel DS21145 Tulip", 128, 0x0801fbff,
+ HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
+ | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
+
+ /* DM910X */
+#ifdef CONFIG_TULIP_DM910X
+ { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
+ HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
+ tulip_timer, tulip_media_task },
+#else
+ { NULL },
+#endif
+
+ /* RS7112 */
+ { "Conexant LANfinity", 256, 0x0001ebef,
+ HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
+
+};
+
+
+static const struct pci_device_id tulip_pci_tbl[] = {
+ { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
+ { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
+ { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
+ { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
+ { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
+/* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
+ { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
+ { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
+ { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
+ { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
+#ifdef CONFIG_TULIP_DM910X
+ { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
+ { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
+#endif
+ { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
+ { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
+ { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
+ { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
+ { 0x1414, 0x0001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Microsoft MN-120 */
+ { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
+ { } /* terminate list */
+};
+MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
+
+
+/* A full-duplex map for media types. */
+const char tulip_media_cap[32] =
+{0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
+
+static void tulip_tx_timeout(struct net_device *dev, unsigned int txqueue);
+static void tulip_init_ring(struct net_device *dev);
+static void tulip_free_ring(struct net_device *dev);
+static netdev_tx_t tulip_start_xmit(struct sk_buff *skb,
+ struct net_device *dev);
+static int tulip_open(struct net_device *dev);
+static int tulip_close(struct net_device *dev);
+static void tulip_up(struct net_device *dev);
+static void tulip_down(struct net_device *dev);
+static struct net_device_stats *tulip_get_stats(struct net_device *dev);
+static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
+static void set_rx_mode(struct net_device *dev);
+static void tulip_set_wolopts(struct pci_dev *pdev, u32 wolopts);
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void poll_tulip(struct net_device *dev);
+#endif
+
+static void tulip_set_power_state (struct tulip_private *tp,
+ int sleep, int snooze)
+{
+ if (tp->flags & HAS_ACPI) {
+ u32 tmp, newtmp;
+ pci_read_config_dword (tp->pdev, CFDD, &tmp);
+ newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
+ if (sleep)
+ newtmp |= CFDD_Sleep;
+ else if (snooze)
+ newtmp |= CFDD_Snooze;
+ if (tmp != newtmp)
+ pci_write_config_dword (tp->pdev, CFDD, newtmp);
+ }
+
+}
+
+
+static void tulip_up(struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+ int next_tick = 3*HZ;
+ u32 reg;
+ int i;
+
+#ifdef CONFIG_TULIP_NAPI
+ napi_enable(&tp->napi);
+#endif
+
+ /* Wake the chip from sleep/snooze mode. */
+ tulip_set_power_state (tp, 0, 0);
+
+ /* Disable all WOL events */
+ pci_enable_wake(tp->pdev, PCI_D3hot, 0);
+ pci_enable_wake(tp->pdev, PCI_D3cold, 0);
+ tulip_set_wolopts(tp->pdev, 0);
+
+ /* On some chip revs we must set the MII/SYM port before the reset!? */
+ if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
+ iowrite32(0x00040000, ioaddr + CSR6);
+
+ /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
+ iowrite32(0x00000001, ioaddr + CSR0);
+ pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
+ udelay(100);
+
+ /* Deassert reset.
+ Wait the specified 50 PCI cycles after a reset by initializing
+ Tx and Rx queues and the address filter list. */
+ iowrite32(tp->csr0, ioaddr + CSR0);
+ pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
+ udelay(100);
+
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "tulip_up(), irq==%d\n", tp->pdev->irq);
+
+ iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
+ iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
+ tp->cur_rx = tp->cur_tx = 0;
+ tp->dirty_rx = tp->dirty_tx = 0;
+
+ if (tp->flags & MC_HASH_ONLY) {
+ u32 addr_low = get_unaligned_le32(dev->dev_addr);
+ u32 addr_high = get_unaligned_le16(dev->dev_addr + 4);
+ if (tp->chip_id == AX88140) {
+ iowrite32(0, ioaddr + CSR13);
+ iowrite32(addr_low, ioaddr + CSR14);
+ iowrite32(1, ioaddr + CSR13);
+ iowrite32(addr_high, ioaddr + CSR14);
+ } else if (tp->flags & COMET_MAC_ADDR) {
+ iowrite32(addr_low, ioaddr + 0xA4);
+ iowrite32(addr_high, ioaddr + 0xA8);
+ iowrite32(0, ioaddr + CSR27);
+ iowrite32(0, ioaddr + CSR28);
+ }
+ } else {
+ /* This is set_rx_mode(), but without starting the transmitter. */
+ const u16 *eaddrs = (const u16 *)dev->dev_addr;
+ u16 *setup_frm = &tp->setup_frame[15*6];
+ dma_addr_t mapping;
+
+ /* 21140 bug: you must add the broadcast address. */
+ memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
+ /* Fill the final entry of the table with our physical address. */
+ *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
+ *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
+ *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
+
+ mapping = dma_map_single(&tp->pdev->dev, tp->setup_frame,
+ sizeof(tp->setup_frame),
+ DMA_TO_DEVICE);
+ tp->tx_buffers[tp->cur_tx].skb = NULL;
+ tp->tx_buffers[tp->cur_tx].mapping = mapping;
+
+ /* Put the setup frame on the Tx list. */
+ tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
+ tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
+ tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
+
+ tp->cur_tx++;
+ }
+
+ tp->saved_if_port = dev->if_port;
+ if (dev->if_port == 0)
+ dev->if_port = tp->default_port;
+
+ /* Allow selecting a default media. */
+ i = 0;
+ if (tp->mtable == NULL)
+ goto media_picked;
+ if (dev->if_port) {
+ int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
+ (dev->if_port == 12 ? 0 : dev->if_port);
+ for (i = 0; i < tp->mtable->leafcount; i++)
+ if (tp->mtable->mleaf[i].media == looking_for) {
+ dev_info(&dev->dev,
+ "Using user-specified media %s\n",
+ medianame[dev->if_port]);
+ goto media_picked;
+ }
+ }
+ if ((tp->mtable->defaultmedia & 0x0800) == 0) {
+ int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
+ for (i = 0; i < tp->mtable->leafcount; i++)
+ if (tp->mtable->mleaf[i].media == looking_for) {
+ dev_info(&dev->dev,
+ "Using EEPROM-set media %s\n",
+ medianame[looking_for]);
+ goto media_picked;
+ }
+ }
+ /* Start sensing first non-full-duplex media. */
+ for (i = tp->mtable->leafcount - 1;
+ (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
+ ;
+media_picked:
+
+ tp->csr6 = 0;
+ tp->cur_index = i;
+ tp->nwayset = 0;
+
+ if (dev->if_port) {
+ if (tp->chip_id == DC21143 &&
+ (tulip_media_cap[dev->if_port] & MediaIsMII)) {
+ /* We must reset the media CSRs when we force-select MII mode. */
+ iowrite32(0x0000, ioaddr + CSR13);
+ iowrite32(0x0000, ioaddr + CSR14);
+ iowrite32(0x0008, ioaddr + CSR15);
+ }
+ tulip_select_media(dev, 1);
+ } else if (tp->chip_id == DC21142) {
+ if (tp->mii_cnt) {
+ tulip_select_media(dev, 1);
+ if (tulip_debug > 1)
+ dev_info(&dev->dev,
+ "Using MII transceiver %d, status %04x\n",
+ tp->phys[0],
+ tulip_mdio_read(dev, tp->phys[0], 1));
+ iowrite32(csr6_mask_defstate, ioaddr + CSR6);
+ tp->csr6 = csr6_mask_hdcap;
+ dev->if_port = 11;
+ iowrite32(0x0000, ioaddr + CSR13);
+ iowrite32(0x0000, ioaddr + CSR14);
+ } else
+ t21142_start_nway(dev);
+ } else if (tp->chip_id == PNIC2) {
+ /* for initial startup advertise 10/100 Full and Half */
+ tp->sym_advertise = 0x01E0;
+ /* enable autonegotiate end interrupt */
+ iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
+ iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
+ pnic2_start_nway(dev);
+ } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
+ if (tp->mii_cnt) {
+ dev->if_port = 11;
+ tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
+ iowrite32(0x0001, ioaddr + CSR15);
+ } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
+ pnic_do_nway(dev);
+ else {
+ /* Start with 10mbps to do autonegotiation. */
+ iowrite32(0x32, ioaddr + CSR12);
+ tp->csr6 = 0x00420000;
+ iowrite32(0x0001B078, ioaddr + 0xB8);
+ iowrite32(0x0201B078, ioaddr + 0xB8);
+ next_tick = 1*HZ;
+ }
+ } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881) &&
+ ! tp->medialock) {
+ dev->if_port = 0;
+ tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
+ iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
+ } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
+ /* Provided by BOLO, Macronix - 12/10/1998. */
+ dev->if_port = 0;
+ tp->csr6 = 0x01a80200;
+ iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
+ iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
+ } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
+ /* Enable automatic Tx underrun recovery. */
+ iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
+ dev->if_port = tp->mii_cnt ? 11 : 0;
+ tp->csr6 = 0x00040000;
+ } else if (tp->chip_id == AX88140) {
+ tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
+ } else
+ tulip_select_media(dev, 1);
+
+ /* Start the chip's Tx to process setup frame. */
+ tulip_stop_rxtx(tp);
+ barrier();
+ udelay(5);
+ iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
+
+ /* Enable interrupts by setting the interrupt mask. */
+ iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
+ iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
+ tulip_start_rxtx(tp);
+ iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
+
+ if (tulip_debug > 2) {
+ netdev_dbg(dev, "Done tulip_up(), CSR0 %08x, CSR5 %08x CSR6 %08x\n",
+ ioread32(ioaddr + CSR0),
+ ioread32(ioaddr + CSR5),
+ ioread32(ioaddr + CSR6));
+ }
+
+ /* Set the timer to switch to check for link beat and perhaps switch
+ to an alternate media type. */
+ tp->timer.expires = RUN_AT(next_tick);
+ add_timer(&tp->timer);
+#ifdef CONFIG_TULIP_NAPI
+ timer_setup(&tp->oom_timer, oom_timer, 0);
+#endif
+}
+
+static int
+tulip_open(struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ int retval;
+
+ tulip_init_ring (dev);
+
+ retval = request_irq(tp->pdev->irq, tulip_interrupt, IRQF_SHARED,
+ dev->name, dev);
+ if (retval)
+ goto free_ring;
+
+ tulip_up (dev);
+
+ netif_start_queue (dev);
+
+ return 0;
+
+free_ring:
+ tulip_free_ring (dev);
+ return retval;
+}
+
+
+static void tulip_tx_timeout(struct net_device *dev, unsigned int txqueue)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+ unsigned long flags;
+
+ spin_lock_irqsave (&tp->lock, flags);
+
+ if (tulip_media_cap[dev->if_port] & MediaIsMII) {
+ /* Do nothing -- the media monitor should handle this. */
+ if (tulip_debug > 1)
+ dev_warn(&dev->dev,
+ "Transmit timeout using MII device\n");
+ } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142 ||
+ tp->chip_id == MX98713 || tp->chip_id == COMPEX9881 ||
+ tp->chip_id == DM910X) {
+ dev_warn(&dev->dev,
+ "21140 transmit timed out, status %08x, SIA %08x %08x %08x %08x, resetting...\n",
+ ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
+ ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14),
+ ioread32(ioaddr + CSR15));
+ tp->timeout_recovery = 1;
+ schedule_work(&tp->media_work);
+ goto out_unlock;
+ } else if (tp->chip_id == PNIC2) {
+ dev_warn(&dev->dev,
+ "PNIC2 transmit timed out, status %08x, CSR6/7 %08x / %08x CSR12 %08x, resetting...\n",
+ (int)ioread32(ioaddr + CSR5),
+ (int)ioread32(ioaddr + CSR6),
+ (int)ioread32(ioaddr + CSR7),
+ (int)ioread32(ioaddr + CSR12));
+ } else {
+ dev_warn(&dev->dev,
+ "Transmit timed out, status %08x, CSR12 %08x, resetting...\n",
+ ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
+ dev->if_port = 0;
+ }
+
+#if defined(way_too_many_messages)
+ if (tulip_debug > 3) {
+ int i;
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
+ int j;
+ printk(KERN_DEBUG
+ "%2d: %08x %08x %08x %08x %02x %02x %02x\n",
+ i,
+ (unsigned int)tp->rx_ring[i].status,
+ (unsigned int)tp->rx_ring[i].length,
+ (unsigned int)tp->rx_ring[i].buffer1,
+ (unsigned int)tp->rx_ring[i].buffer2,
+ buf[0], buf[1], buf[2]);
+ for (j = 0; ((j < 1600) && buf[j] != 0xee); j++)
+ if (j < 100)
+ pr_cont(" %02x", buf[j]);
+ pr_cont(" j=%d\n", j);
+ }
+ printk(KERN_DEBUG " Rx ring %p: ", tp->rx_ring);
+ for (i = 0; i < RX_RING_SIZE; i++)
+ pr_cont(" %08x", (unsigned int)tp->rx_ring[i].status);
+ printk(KERN_DEBUG " Tx ring %p: ", tp->tx_ring);
+ for (i = 0; i < TX_RING_SIZE; i++)
+ pr_cont(" %08x", (unsigned int)tp->tx_ring[i].status);
+ pr_cont("\n");
+ }
+#endif
+
+ tulip_tx_timeout_complete(tp, ioaddr);
+
+out_unlock:
+ spin_unlock_irqrestore (&tp->lock, flags);
+ netif_trans_update(dev); /* prevent tx timeout */
+ netif_wake_queue (dev);
+}
+
+
+/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
+static void tulip_init_ring(struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ int i;
+
+ tp->susp_rx = 0;
+ tp->ttimer = 0;
+ tp->nir = 0;
+
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ tp->rx_ring[i].status = 0x00000000;
+ tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
+ tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
+ tp->rx_buffers[i].skb = NULL;
+ tp->rx_buffers[i].mapping = 0;
+ }
+ /* Mark the last entry as wrapping the ring. */
+ tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
+ tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
+
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ dma_addr_t mapping;
+
+ /* Note the receive buffer must be longword aligned.
+ netdev_alloc_skb() provides 16 byte alignment. But do *not*
+ use skb_reserve() to align the IP header! */
+ struct sk_buff *skb = netdev_alloc_skb(dev, PKT_BUF_SZ);
+ tp->rx_buffers[i].skb = skb;
+ if (skb == NULL)
+ break;
+ mapping = dma_map_single(&tp->pdev->dev, skb->data,
+ PKT_BUF_SZ, DMA_FROM_DEVICE);
+ tp->rx_buffers[i].mapping = mapping;
+ tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
+ tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
+ }
+ tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
+
+ /* The Tx buffer descriptor is filled in as needed, but we
+ do need to clear the ownership bit. */
+ for (i = 0; i < TX_RING_SIZE; i++) {
+ tp->tx_buffers[i].skb = NULL;
+ tp->tx_buffers[i].mapping = 0;
+ tp->tx_ring[i].status = 0x00000000;
+ tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
+ }
+ tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
+}
+
+static netdev_tx_t
+tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ int entry;
+ u32 flag;
+ dma_addr_t mapping;
+ unsigned long flags;
+
+ spin_lock_irqsave(&tp->lock, flags);
+
+ /* Calculate the next Tx descriptor entry. */
+ entry = tp->cur_tx % TX_RING_SIZE;
+
+ tp->tx_buffers[entry].skb = skb;
+ mapping = dma_map_single(&tp->pdev->dev, skb->data, skb->len,
+ DMA_TO_DEVICE);
+ tp->tx_buffers[entry].mapping = mapping;
+ tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
+
+ if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
+ flag = 0x60000000; /* No interrupt */
+ } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
+ flag = 0xe0000000; /* Tx-done intr. */
+ } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
+ flag = 0x60000000; /* No Tx-done intr. */
+ } else { /* Leave room for set_rx_mode() to fill entries. */
+ flag = 0xe0000000; /* Tx-done intr. */
+ netif_stop_queue(dev);
+ }
+ if (entry == TX_RING_SIZE-1)
+ flag = 0xe0000000 | DESC_RING_WRAP;
+
+ tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
+ /* if we were using Transmit Automatic Polling, we would need a
+ * wmb() here. */
+ tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
+ wmb();
+
+ tp->cur_tx++;
+
+ /* Trigger an immediate transmit demand. */
+ iowrite32(0, tp->base_addr + CSR1);
+
+ spin_unlock_irqrestore(&tp->lock, flags);
+
+ return NETDEV_TX_OK;
+}
+
+static void tulip_clean_tx_ring(struct tulip_private *tp)
+{
+ unsigned int dirty_tx;
+
+ for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
+ dirty_tx++) {
+ int entry = dirty_tx % TX_RING_SIZE;
+ int status = le32_to_cpu(tp->tx_ring[entry].status);
+
+ if (status < 0) {
+ tp->dev->stats.tx_errors++; /* It wasn't Txed */
+ tp->tx_ring[entry].status = 0;
+ }
+
+ /* Check for Tx filter setup frames. */
+ if (tp->tx_buffers[entry].skb == NULL) {
+ /* test because dummy frames not mapped */
+ if (tp->tx_buffers[entry].mapping)
+ dma_unmap_single(&tp->pdev->dev,
+ tp->tx_buffers[entry].mapping,
+ sizeof(tp->setup_frame),
+ DMA_TO_DEVICE);
+ continue;
+ }
+
+ dma_unmap_single(&tp->pdev->dev,
+ tp->tx_buffers[entry].mapping,
+ tp->tx_buffers[entry].skb->len,
+ DMA_TO_DEVICE);
+
+ /* Free the original skb. */
+ dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
+ tp->tx_buffers[entry].skb = NULL;
+ tp->tx_buffers[entry].mapping = 0;
+ }
+}
+
+static void tulip_down (struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+ unsigned long flags;
+
+ cancel_work_sync(&tp->media_work);
+
+#ifdef CONFIG_TULIP_NAPI
+ napi_disable(&tp->napi);
+#endif
+
+ del_timer_sync (&tp->timer);
+#ifdef CONFIG_TULIP_NAPI
+ del_timer_sync (&tp->oom_timer);
+#endif
+ spin_lock_irqsave (&tp->lock, flags);
+
+ /* Disable interrupts by clearing the interrupt mask. */
+ iowrite32 (0x00000000, ioaddr + CSR7);
+
+ /* Stop the Tx and Rx processes. */
+ tulip_stop_rxtx(tp);
+
+ /* prepare receive buffers */
+ tulip_refill_rx(dev);
+
+ /* release any unconsumed transmit buffers */
+ tulip_clean_tx_ring(tp);
+
+ if (ioread32(ioaddr + CSR6) != 0xffffffff)
+ dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
+
+ spin_unlock_irqrestore (&tp->lock, flags);
+
+ timer_setup(&tp->timer, tulip_tbl[tp->chip_id].media_timer, 0);
+
+ dev->if_port = tp->saved_if_port;
+
+ /* Leave the driver in snooze, not sleep, mode. */
+ tulip_set_power_state (tp, 0, 1);
+}
+
+static void tulip_free_ring (struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ int i;
+
+ /* Free all the skbuffs in the Rx queue. */
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ struct sk_buff *skb = tp->rx_buffers[i].skb;
+ dma_addr_t mapping = tp->rx_buffers[i].mapping;
+
+ tp->rx_buffers[i].skb = NULL;
+ tp->rx_buffers[i].mapping = 0;
+
+ tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
+ tp->rx_ring[i].length = 0;
+ /* An invalid address. */
+ tp->rx_ring[i].buffer1 = cpu_to_le32(0xBADF00D0);
+ if (skb) {
+ dma_unmap_single(&tp->pdev->dev, mapping, PKT_BUF_SZ,
+ DMA_FROM_DEVICE);
+ dev_kfree_skb (skb);
+ }
+ }
+
+ for (i = 0; i < TX_RING_SIZE; i++) {
+ struct sk_buff *skb = tp->tx_buffers[i].skb;
+
+ if (skb != NULL) {
+ dma_unmap_single(&tp->pdev->dev,
+ tp->tx_buffers[i].mapping, skb->len,
+ DMA_TO_DEVICE);
+ dev_kfree_skb (skb);
+ }
+ tp->tx_buffers[i].skb = NULL;
+ tp->tx_buffers[i].mapping = 0;
+ }
+}
+
+static int tulip_close (struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+
+ netif_stop_queue (dev);
+
+ tulip_down (dev);
+
+ if (tulip_debug > 1)
+ netdev_dbg(dev, "Shutting down ethercard, status was %02x\n",
+ ioread32 (ioaddr + CSR5));
+
+ free_irq (tp->pdev->irq, dev);
+
+ tulip_free_ring (dev);
+
+ return 0;
+}
+
+static struct net_device_stats *tulip_get_stats(struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+
+ if (netif_running(dev)) {
+ unsigned long flags;
+
+ spin_lock_irqsave (&tp->lock, flags);
+
+ dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
+
+ spin_unlock_irqrestore(&tp->lock, flags);
+ }
+
+ return &dev->stats;
+}
+
+
+static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
+{
+ struct tulip_private *np = netdev_priv(dev);
+ strscpy(info->driver, DRV_NAME, sizeof(info->driver));
+ strscpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
+}
+
+
+static int tulip_ethtool_set_wol(struct net_device *dev,
+ struct ethtool_wolinfo *wolinfo)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+
+ if (wolinfo->wolopts & (~tp->wolinfo.supported))
+ return -EOPNOTSUPP;
+
+ tp->wolinfo.wolopts = wolinfo->wolopts;
+ device_set_wakeup_enable(&tp->pdev->dev, tp->wolinfo.wolopts);
+ return 0;
+}
+
+static void tulip_ethtool_get_wol(struct net_device *dev,
+ struct ethtool_wolinfo *wolinfo)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+
+ wolinfo->supported = tp->wolinfo.supported;
+ wolinfo->wolopts = tp->wolinfo.wolopts;
+ return;
+}
+
+
+static const struct ethtool_ops ops = {
+ .get_drvinfo = tulip_get_drvinfo,
+ .set_wol = tulip_ethtool_set_wol,
+ .get_wol = tulip_ethtool_get_wol,
+};
+
+/* Provide ioctl() calls to examine the MII xcvr state. */
+static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+ struct mii_ioctl_data *data = if_mii(rq);
+ const unsigned int phy_idx = 0;
+ int phy = tp->phys[phy_idx] & 0x1f;
+ unsigned int regnum = data->reg_num;
+
+ switch (cmd) {
+ case SIOCGMIIPHY: /* Get address of MII PHY in use. */
+ if (tp->mii_cnt)
+ data->phy_id = phy;
+ else if (tp->flags & HAS_NWAY)
+ data->phy_id = 32;
+ else if (tp->chip_id == COMET)
+ data->phy_id = 1;
+ else
+ return -ENODEV;
+ fallthrough;
+
+ case SIOCGMIIREG: /* Read MII PHY register. */
+ if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
+ int csr12 = ioread32 (ioaddr + CSR12);
+ int csr14 = ioread32 (ioaddr + CSR14);
+ switch (regnum) {
+ case 0:
+ if (((csr14<<5) & 0x1000) ||
+ (dev->if_port == 5 && tp->nwayset))
+ data->val_out = 0x1000;
+ else
+ data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
+ | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
+ break;
+ case 1:
+ data->val_out =
+ 0x1848 +
+ ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
+ ((csr12&0x06) == 6 ? 0 : 4);
+ data->val_out |= 0x6048;
+ break;
+ case 4:
+ /* Advertised value, bogus 10baseTx-FD value from CSR6. */
+ data->val_out =
+ ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
+ ((csr14 >> 1) & 0x20) + 1;
+ data->val_out |= ((csr14 >> 9) & 0x03C0);
+ break;
+ case 5: data->val_out = tp->lpar; break;
+ default: data->val_out = 0; break;
+ }
+ } else {
+ data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
+ }
+ return 0;
+
+ case SIOCSMIIREG: /* Write MII PHY register. */
+ if (regnum & ~0x1f)
+ return -EINVAL;
+ if (data->phy_id == phy) {
+ u16 value = data->val_in;
+ switch (regnum) {
+ case 0: /* Check for autonegotiation on or reset. */
+ tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
+ if (tp->full_duplex_lock)
+ tp->full_duplex = (value & 0x0100) ? 1 : 0;
+ break;
+ case 4:
+ tp->advertising[phy_idx] =
+ tp->mii_advertise = data->val_in;
+ break;
+ }
+ }
+ if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
+ u16 value = data->val_in;
+ if (regnum == 0) {
+ if ((value & 0x1200) == 0x1200) {
+ if (tp->chip_id == PNIC2) {
+ pnic2_start_nway (dev);
+ } else {
+ t21142_start_nway (dev);
+ }
+ }
+ } else if (regnum == 4)
+ tp->sym_advertise = value;
+ } else {
+ tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
+ }
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ return -EOPNOTSUPP;
+}
+
+
+/* Set or clear the multicast filter for this adaptor.
+ Note that we only use exclusion around actually queueing the
+ new frame, not around filling tp->setup_frame. This is non-deterministic
+ when re-entered but still correct. */
+
+static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ u16 hash_table[32];
+ struct netdev_hw_addr *ha;
+ const u16 *eaddrs;
+ int i;
+
+ memset(hash_table, 0, sizeof(hash_table));
+ __set_bit_le(255, hash_table); /* Broadcast entry */
+ /* This should work on big-endian machines as well. */
+ netdev_for_each_mc_addr(ha, dev) {
+ int index = ether_crc_le(ETH_ALEN, ha->addr) & 0x1ff;
+
+ __set_bit_le(index, hash_table);
+ }
+ for (i = 0; i < 32; i++) {
+ *setup_frm++ = hash_table[i];
+ *setup_frm++ = hash_table[i];
+ }
+ setup_frm = &tp->setup_frame[13*6];
+
+ /* Fill the final entry with our physical address. */
+ eaddrs = (const u16 *)dev->dev_addr;
+ *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
+ *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
+ *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
+}
+
+static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ struct netdev_hw_addr *ha;
+ const u16 *eaddrs;
+
+ /* We have <= 14 addresses so we can use the wonderful
+ 16 address perfect filtering of the Tulip. */
+ netdev_for_each_mc_addr(ha, dev) {
+ eaddrs = (u16 *) ha->addr;
+ *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
+ *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
+ *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
+ }
+ /* Fill the unused entries with the broadcast address. */
+ memset(setup_frm, 0xff, (15 - netdev_mc_count(dev)) * 12);
+ setup_frm = &tp->setup_frame[15*6];
+
+ /* Fill the final entry with our physical address. */
+ eaddrs = (const u16 *)dev->dev_addr;
+ *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
+ *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
+ *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
+}
+
+
+static void set_rx_mode(struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+ int csr6;
+
+ csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
+
+ tp->csr6 &= ~0x00D5;
+ if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
+ tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
+ csr6 |= AcceptAllMulticast | AcceptAllPhys;
+ } else if ((netdev_mc_count(dev) > 1000) ||
+ (dev->flags & IFF_ALLMULTI)) {
+ /* Too many to filter well -- accept all multicasts. */
+ tp->csr6 |= AcceptAllMulticast;
+ csr6 |= AcceptAllMulticast;
+ } else if (tp->flags & MC_HASH_ONLY) {
+ /* Some work-alikes have only a 64-entry hash filter table. */
+ /* Should verify correctness on big-endian/__powerpc__ */
+ struct netdev_hw_addr *ha;
+ if (netdev_mc_count(dev) > 64) {
+ /* Arbitrary non-effective limit. */
+ tp->csr6 |= AcceptAllMulticast;
+ csr6 |= AcceptAllMulticast;
+ } else {
+ u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
+ int filterbit;
+ netdev_for_each_mc_addr(ha, dev) {
+ if (tp->flags & COMET_MAC_ADDR)
+ filterbit = ether_crc_le(ETH_ALEN,
+ ha->addr);
+ else
+ filterbit = ether_crc(ETH_ALEN,
+ ha->addr) >> 26;
+ filterbit &= 0x3f;
+ mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
+ if (tulip_debug > 2)
+ dev_info(&dev->dev,
+ "Added filter for %pM %08x bit %d\n",
+ ha->addr,
+ ether_crc(ETH_ALEN, ha->addr),
+ filterbit);
+ }
+ if (mc_filter[0] == tp->mc_filter[0] &&
+ mc_filter[1] == tp->mc_filter[1])
+ ; /* No change. */
+ else if (tp->flags & IS_ASIX) {
+ iowrite32(2, ioaddr + CSR13);
+ iowrite32(mc_filter[0], ioaddr + CSR14);
+ iowrite32(3, ioaddr + CSR13);
+ iowrite32(mc_filter[1], ioaddr + CSR14);
+ } else if (tp->flags & COMET_MAC_ADDR) {
+ iowrite32(mc_filter[0], ioaddr + CSR27);
+ iowrite32(mc_filter[1], ioaddr + CSR28);
+ }
+ tp->mc_filter[0] = mc_filter[0];
+ tp->mc_filter[1] = mc_filter[1];
+ }
+ } else {
+ unsigned long flags;
+ u32 tx_flags = 0x08000000 | 192;
+
+ /* Note that only the low-address shortword of setup_frame is valid!
+ The values are doubled for big-endian architectures. */
+ if (netdev_mc_count(dev) > 14) {
+ /* Must use a multicast hash table. */
+ build_setup_frame_hash(tp->setup_frame, dev);
+ tx_flags = 0x08400000 | 192;
+ } else {
+ build_setup_frame_perfect(tp->setup_frame, dev);
+ }
+
+ spin_lock_irqsave(&tp->lock, flags);
+
+ if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
+ /* Same setup recently queued, we need not add it. */
+ } else {
+ unsigned int entry;
+ int dummy = -1;
+
+ /* Now add this frame to the Tx list. */
+
+ entry = tp->cur_tx++ % TX_RING_SIZE;
+
+ if (entry != 0) {
+ /* Avoid a chip errata by prefixing a dummy entry. */
+ tp->tx_buffers[entry].skb = NULL;
+ tp->tx_buffers[entry].mapping = 0;
+ tp->tx_ring[entry].length =
+ (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
+ tp->tx_ring[entry].buffer1 = 0;
+ /* Must set DescOwned later to avoid race with chip */
+ dummy = entry;
+ entry = tp->cur_tx++ % TX_RING_SIZE;
+
+ }
+
+ tp->tx_buffers[entry].skb = NULL;
+ tp->tx_buffers[entry].mapping =
+ dma_map_single(&tp->pdev->dev,
+ tp->setup_frame,
+ sizeof(tp->setup_frame),
+ DMA_TO_DEVICE);
+ /* Put the setup frame on the Tx list. */
+ if (entry == TX_RING_SIZE-1)
+ tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
+ tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
+ tp->tx_ring[entry].buffer1 =
+ cpu_to_le32(tp->tx_buffers[entry].mapping);
+ tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
+ if (dummy >= 0)
+ tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
+ if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
+ netif_stop_queue(dev);
+
+ /* Trigger an immediate transmit demand. */
+ iowrite32(0, ioaddr + CSR1);
+ }
+
+ spin_unlock_irqrestore(&tp->lock, flags);
+ }
+
+ iowrite32(csr6, ioaddr + CSR6);
+}
+
+#ifdef CONFIG_TULIP_MWI
+static void tulip_mwi_config(struct pci_dev *pdev, struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ u8 cache;
+ u16 pci_command;
+ u32 csr0;
+
+ if (tulip_debug > 3)
+ netdev_dbg(dev, "tulip_mwi_config()\n");
+
+ tp->csr0 = csr0 = 0;
+
+ /* if we have any cache line size at all, we can do MRM and MWI */
+ csr0 |= MRM | MWI;
+
+ /* Enable MWI in the standard PCI command bit.
+ * Check for the case where MWI is desired but not available
+ */
+ pci_try_set_mwi(pdev);
+
+ /* read result from hardware (in case bit refused to enable) */
+ pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
+ if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
+ csr0 &= ~MWI;
+
+ /* if cache line size hardwired to zero, no MWI */
+ pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
+ if ((csr0 & MWI) && (cache == 0)) {
+ csr0 &= ~MWI;
+ pci_clear_mwi(pdev);
+ }
+
+ /* assign per-cacheline-size cache alignment and
+ * burst length values
+ */
+ switch (cache) {
+ case 8:
+ csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
+ break;
+ case 16:
+ csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
+ break;
+ case 32:
+ csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
+ break;
+ default:
+ cache = 0;
+ break;
+ }
+
+ /* if we have a good cache line size, we by now have a good
+ * csr0, so save it and exit
+ */
+ if (cache)
+ goto out;
+
+ /* we don't have a good csr0 or cache line size, disable MWI */
+ if (csr0 & MWI) {
+ pci_clear_mwi(pdev);
+ csr0 &= ~MWI;
+ }
+
+ /* sane defaults for burst length and cache alignment
+ * originally from de4x5 driver
+ */
+ csr0 |= (8 << BurstLenShift) | (1 << CALShift);
+
+out:
+ tp->csr0 = csr0;
+ if (tulip_debug > 2)
+ netdev_dbg(dev, "MWI config cacheline=%d, csr0=%08x\n",
+ cache, csr0);
+}
+#endif
+
+/*
+ * Chips that have the MRM/reserved bit quirk and the burst quirk. That
+ * is the DM910X and the on chip ULi devices
+ */
+
+static int tulip_uli_dm_quirk(struct pci_dev *pdev)
+{
+ if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
+ return 1;
+ return 0;
+}
+
+static const struct net_device_ops tulip_netdev_ops = {
+ .ndo_open = tulip_open,
+ .ndo_start_xmit = tulip_start_xmit,
+ .ndo_tx_timeout = tulip_tx_timeout,
+ .ndo_stop = tulip_close,
+ .ndo_get_stats = tulip_get_stats,
+ .ndo_eth_ioctl = private_ioctl,
+ .ndo_set_rx_mode = set_rx_mode,
+ .ndo_set_mac_address = eth_mac_addr,
+ .ndo_validate_addr = eth_validate_addr,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+ .ndo_poll_controller = poll_tulip,
+#endif
+};
+
+static const struct pci_device_id early_486_chipsets[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
+ { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
+ { },
+};
+
+static int tulip_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+ struct tulip_private *tp;
+ /* See note below on the multiport cards. */
+ static unsigned char last_phys_addr[ETH_ALEN] = {
+ 0x00, 'L', 'i', 'n', 'u', 'x'
+ };
+#if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
+ static int last_irq;
+#endif
+ int i, irq;
+ unsigned short sum;
+ unsigned char *ee_data;
+ struct net_device *dev;
+ void __iomem *ioaddr;
+ static int board_idx = -1;
+ int chip_idx = ent->driver_data;
+ const char *chip_name = tulip_tbl[chip_idx].chip_name;
+ unsigned int eeprom_missing = 0;
+ u8 addr[ETH_ALEN] __aligned(2);
+ unsigned int force_csr0 = 0;
+
+ board_idx++;
+
+ /*
+ * Lan media wire a tulip chip to a wan interface. Needs a very
+ * different driver (lmc driver)
+ */
+
+ if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
+ pr_err("skipping LMC card\n");
+ return -ENODEV;
+ } else if (pdev->subsystem_vendor == PCI_VENDOR_ID_SBE &&
+ (pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_T3E3 ||
+ pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P0 ||
+ pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P1)) {
+ pr_err("skipping SBE T3E3 port\n");
+ return -ENODEV;
+ }
+
+ /*
+ * DM910x chips should be handled by the dmfe driver, except
+ * on-board chips on SPARC systems. Also, early DM9100s need
+ * software CRC which only the dmfe driver supports.
+ */
+
+#ifdef CONFIG_TULIP_DM910X
+ if (chip_idx == DM910X) {
+ struct device_node *dp;
+
+ if (pdev->vendor == 0x1282 && pdev->device == 0x9100 &&
+ pdev->revision < 0x30) {
+ pr_info("skipping early DM9100 with Crc bug (use dmfe)\n");
+ return -ENODEV;
+ }
+
+ dp = pci_device_to_OF_node(pdev);
+ if (!(dp && of_get_property(dp, "local-mac-address", NULL))) {
+ pr_info("skipping DM910x expansion card (use dmfe)\n");
+ return -ENODEV;
+ }
+ }
+#endif
+
+ /*
+ * Looks for early PCI chipsets where people report hangs
+ * without the workarounds being on.
+ */
+
+ /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
+ aligned. Aries might need this too. The Saturn errata are not
+ pretty reading but thankfully it's an old 486 chipset.
+
+ 2. The dreaded SiS496 486 chipset. Same workaround as Intel
+ Saturn.
+ */
+
+ if (pci_dev_present(early_486_chipsets)) {
+ csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
+ force_csr0 = 1;
+ }
+
+ /* bugfix: the ASIX must have a burst limit or horrible things happen. */
+ if (chip_idx == AX88140) {
+ if ((csr0 & 0x3f00) == 0)
+ csr0 |= 0x2000;
+ }
+
+ /* PNIC doesn't have MWI/MRL/MRM... */
+ if (chip_idx == LC82C168)
+ csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
+
+ /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
+ if (tulip_uli_dm_quirk(pdev)) {
+ csr0 &= ~0x01f100ff;
+#if defined(CONFIG_SPARC)
+ csr0 = (csr0 & ~0xff00) | 0xe000;
+#endif
+ }
+ /*
+ * And back to business
+ */
+
+ i = pcim_enable_device(pdev);
+ if (i) {
+ pr_err("Cannot enable tulip board #%d, aborting\n", board_idx);
+ return i;
+ }
+
+ irq = pdev->irq;
+
+ /* alloc_etherdev ensures aligned and zeroed private structures */
+ dev = devm_alloc_etherdev(&pdev->dev, sizeof(*tp));
+ if (!dev)
+ return -ENOMEM;
+
+ SET_NETDEV_DEV(dev, &pdev->dev);
+ if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
+ pr_err("%s: I/O region (0x%llx@0x%llx) too small, aborting\n",
+ pci_name(pdev),
+ (unsigned long long)pci_resource_len (pdev, 0),
+ (unsigned long long)pci_resource_start (pdev, 0));
+ return -ENODEV;
+ }
+
+ /* grab all resources from both PIO and MMIO regions, as we
+ * don't want anyone else messing around with our hardware */
+ if (pci_request_regions(pdev, DRV_NAME))
+ return -ENODEV;
+
+ ioaddr = pcim_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
+
+ if (!ioaddr)
+ return -ENODEV;
+
+ /*
+ * initialize private data structure 'tp'
+ * it is zeroed and aligned in alloc_etherdev
+ */
+ tp = netdev_priv(dev);
+ tp->dev = dev;
+
+ tp->rx_ring = dmam_alloc_coherent(&pdev->dev,
+ sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
+ sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
+ &tp->rx_ring_dma, GFP_KERNEL);
+ if (!tp->rx_ring)
+ return -ENODEV;
+ tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
+ tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
+
+ tp->chip_id = chip_idx;
+ tp->flags = tulip_tbl[chip_idx].flags;
+
+ tp->wolinfo.supported = 0;
+ tp->wolinfo.wolopts = 0;
+ /* COMET: Enable power management only for AN983B */
+ if (chip_idx == COMET ) {
+ u32 sig;
+ pci_read_config_dword (pdev, 0x80, &sig);
+ if (sig == 0x09811317) {
+ tp->flags |= COMET_PM;
+ tp->wolinfo.supported = WAKE_PHY | WAKE_MAGIC;
+ pr_info("%s: Enabled WOL support for AN983B\n",
+ __func__);
+ }
+ }
+ tp->pdev = pdev;
+ tp->base_addr = ioaddr;
+ tp->revision = pdev->revision;
+ tp->csr0 = csr0;
+ spin_lock_init(&tp->lock);
+ spin_lock_init(&tp->mii_lock);
+ timer_setup(&tp->timer, tulip_tbl[tp->chip_id].media_timer, 0);
+
+ INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
+
+#ifdef CONFIG_TULIP_MWI
+ if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
+ tulip_mwi_config (pdev, dev);
+#endif
+
+ /* Stop the chip's Tx and Rx processes. */
+ tulip_stop_rxtx(tp);
+
+ pci_set_master(pdev);
+
+#ifdef CONFIG_GSC
+ if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
+ switch (pdev->subsystem_device) {
+ default:
+ break;
+ case 0x1061:
+ case 0x1062:
+ case 0x1063:
+ case 0x1098:
+ case 0x1099:
+ case 0x10EE:
+ tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
+ chip_name = "GSC DS21140 Tulip";
+ }
+ }
+#endif
+
+ /* Clear the missed-packet counter. */
+ ioread32(ioaddr + CSR8);
+
+ /* The station address ROM is read byte serially. The register must
+ be polled, waiting for the value to be read bit serially from the
+ EEPROM.
+ */
+ ee_data = tp->eeprom;
+ memset(ee_data, 0, sizeof(tp->eeprom));
+ sum = 0;
+ if (chip_idx == LC82C168) {
+ for (i = 0; i < 3; i++) {
+ int value, boguscnt = 100000;
+ iowrite32(0x600 | i, ioaddr + 0x98);
+ do {
+ value = ioread32(ioaddr + CSR9);
+ } while (value < 0 && --boguscnt > 0);
+ put_unaligned_le16(value, ((__le16 *)addr) + i);
+ sum += value & 0xffff;
+ }
+ eth_hw_addr_set(dev, addr);
+ } else if (chip_idx == COMET) {
+ /* No need to read the EEPROM. */
+ put_unaligned_le32(ioread32(ioaddr + 0xA4), addr);
+ put_unaligned_le16(ioread32(ioaddr + 0xA8), addr + 4);
+ eth_hw_addr_set(dev, addr);
+ for (i = 0; i < 6; i ++)
+ sum += dev->dev_addr[i];
+ } else {
+ /* A serial EEPROM interface, we read now and sort it out later. */
+ int sa_offset = 0;
+ int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
+ int ee_max_addr = ((1 << ee_addr_size) - 1) * sizeof(u16);
+
+ if (ee_max_addr > sizeof(tp->eeprom))
+ ee_max_addr = sizeof(tp->eeprom);
+
+ for (i = 0; i < ee_max_addr ; i += sizeof(u16)) {
+ u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
+ ee_data[i] = data & 0xff;
+ ee_data[i + 1] = data >> 8;
+ }
+
+ /* DEC now has a specification (see Notes) but early board makers
+ just put the address in the first EEPROM locations. */
+ /* This does memcmp(ee_data, ee_data+16, 8) */
+ for (i = 0; i < 8; i ++)
+ if (ee_data[i] != ee_data[16+i])
+ sa_offset = 20;
+ if (chip_idx == CONEXANT) {
+ /* Check that the tuple type and length is correct. */
+ if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
+ sa_offset = 0x19A;
+ } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
+ ee_data[2] == 0) {
+ sa_offset = 2; /* Grrr, damn Matrox boards. */
+ }
+#ifdef CONFIG_MIPS_COBALT
+ if ((pdev->bus->number == 0) &&
+ ((PCI_SLOT(pdev->devfn) == 7) ||
+ (PCI_SLOT(pdev->devfn) == 12))) {
+ /* Cobalt MAC address in first EEPROM locations. */
+ sa_offset = 0;
+ /* Ensure our media table fixup get's applied */
+ memcpy(ee_data + 16, ee_data, 8);
+ }
+#endif
+#ifdef CONFIG_GSC
+ /* Check to see if we have a broken srom */
+ if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
+ /* pci_vendor_id and subsystem_id are swapped */
+ ee_data[0] = ee_data[2];
+ ee_data[1] = ee_data[3];
+ ee_data[2] = 0x61;
+ ee_data[3] = 0x10;
+
+ /* HSC-PCI boards need to be byte-swaped and shifted
+ * up 1 word. This shift needs to happen at the end
+ * of the MAC first because of the 2 byte overlap.
+ */
+ for (i = 4; i >= 0; i -= 2) {
+ ee_data[17 + i + 3] = ee_data[17 + i];
+ ee_data[16 + i + 5] = ee_data[16 + i];
+ }
+ }
+#endif
+
+ for (i = 0; i < 6; i ++) {
+ addr[i] = ee_data[i + sa_offset];
+ sum += ee_data[i + sa_offset];
+ }
+ eth_hw_addr_set(dev, addr);
+ }
+ /* Lite-On boards have the address byte-swapped. */
+ if ((dev->dev_addr[0] == 0xA0 ||
+ dev->dev_addr[0] == 0xC0 ||
+ dev->dev_addr[0] == 0x02) &&
+ dev->dev_addr[1] == 0x00) {
+ for (i = 0; i < 6; i+=2) {
+ addr[i] = dev->dev_addr[i+1];
+ addr[i+1] = dev->dev_addr[i];
+ }
+ eth_hw_addr_set(dev, addr);
+ }
+
+ /* On the Zynx 315 Etherarray and other multiport boards only the
+ first Tulip has an EEPROM.
+ On Sparc systems the mac address is held in the OBP property
+ "local-mac-address".
+ The addresses of the subsequent ports are derived from the first.
+ Many PCI BIOSes also incorrectly report the IRQ line, so we correct
+ that here as well. */
+ if (sum == 0 || sum == 6*0xff) {
+#if defined(CONFIG_SPARC)
+ struct device_node *dp = pci_device_to_OF_node(pdev);
+ const unsigned char *addr2;
+ int len;
+#endif
+ eeprom_missing = 1;
+ for (i = 0; i < 5; i++)
+ addr[i] = last_phys_addr[i];
+ addr[i] = last_phys_addr[i] + 1;
+ eth_hw_addr_set(dev, addr);
+#if defined(CONFIG_SPARC)
+ addr2 = of_get_property(dp, "local-mac-address", &len);
+ if (addr2 && len == ETH_ALEN)
+ eth_hw_addr_set(dev, addr2);
+#endif
+#if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
+ if (last_irq)
+ irq = last_irq;
+#endif
+ }
+
+ for (i = 0; i < 6; i++)
+ last_phys_addr[i] = dev->dev_addr[i];
+#if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
+ last_irq = irq;
+#endif
+
+ /* The lower four bits are the media type. */
+ if (board_idx >= 0 && board_idx < MAX_UNITS) {
+ if (options[board_idx] & MEDIA_MASK)
+ tp->default_port = options[board_idx] & MEDIA_MASK;
+ if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
+ tp->full_duplex = 1;
+ if (mtu[board_idx] > 0)
+ dev->mtu = mtu[board_idx];
+ }
+ if (dev->mem_start & MEDIA_MASK)
+ tp->default_port = dev->mem_start & MEDIA_MASK;
+ if (tp->default_port) {
+ pr_info(DRV_NAME "%d: Transceiver selection forced to %s\n",
+ board_idx, medianame[tp->default_port & MEDIA_MASK]);
+ tp->medialock = 1;
+ if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
+ tp->full_duplex = 1;
+ }
+ if (tp->full_duplex)
+ tp->full_duplex_lock = 1;
+
+ if (tulip_media_cap[tp->default_port] & MediaIsMII) {
+ static const u16 media2advert[] = {
+ 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200
+ };
+ tp->mii_advertise = media2advert[tp->default_port - 9];
+ tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
+ }
+
+ if (tp->flags & HAS_MEDIA_TABLE) {
+ sprintf(dev->name, DRV_NAME "%d", board_idx); /* hack */
+ tulip_parse_eeprom(dev);
+ strcpy(dev->name, "eth%d"); /* un-hack */
+ }
+
+ if ((tp->flags & ALWAYS_CHECK_MII) ||
+ (tp->mtable && tp->mtable->has_mii) ||
+ ( ! tp->mtable && (tp->flags & HAS_MII))) {
+ if (tp->mtable && tp->mtable->has_mii) {
+ for (i = 0; i < tp->mtable->leafcount; i++)
+ if (tp->mtable->mleaf[i].media == 11) {
+ tp->cur_index = i;
+ tp->saved_if_port = dev->if_port;
+ tulip_select_media(dev, 2);
+ dev->if_port = tp->saved_if_port;
+ break;
+ }
+ }
+
+ /* Find the connected MII xcvrs.
+ Doing this in open() would allow detecting external xcvrs
+ later, but takes much time. */
+ tulip_find_mii (dev, board_idx);
+ }
+
+ /* The Tulip-specific entries in the device structure. */
+ dev->netdev_ops = &tulip_netdev_ops;
+ dev->watchdog_timeo = TX_TIMEOUT;
+#ifdef CONFIG_TULIP_NAPI
+ netif_napi_add_weight(dev, &tp->napi, tulip_poll, 16);
+#endif
+ dev->ethtool_ops = &ops;
+
+ i = register_netdev(dev);
+ if (i)
+ return i;
+
+ pci_set_drvdata(pdev, dev);
+
+ dev_info(&dev->dev,
+#ifdef CONFIG_TULIP_MMIO
+ "%s rev %d at MMIO %#llx,%s %pM, IRQ %d\n",
+#else
+ "%s rev %d at Port %#llx,%s %pM, IRQ %d\n",
+#endif
+ chip_name, pdev->revision,
+ (unsigned long long)pci_resource_start(pdev, TULIP_BAR),
+ eeprom_missing ? " EEPROM not present," : "",
+ dev->dev_addr, irq);
+
+ if (tp->chip_id == PNIC2)
+ tp->link_change = pnic2_lnk_change;
+ else if (tp->flags & HAS_NWAY)
+ tp->link_change = t21142_lnk_change;
+ else if (tp->flags & HAS_PNICNWAY)
+ tp->link_change = pnic_lnk_change;
+
+ /* Reset the xcvr interface and turn on heartbeat. */
+ switch (chip_idx) {
+ case DC21140:
+ case DM910X:
+ default:
+ if (tp->mtable)
+ iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
+ break;
+ case DC21142:
+ if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
+ iowrite32(csr6_mask_defstate, ioaddr + CSR6);
+ iowrite32(0x0000, ioaddr + CSR13);
+ iowrite32(0x0000, ioaddr + CSR14);
+ iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
+ } else
+ t21142_start_nway(dev);
+ break;
+ case PNIC2:
+ /* just do a reset for sanity sake */
+ iowrite32(0x0000, ioaddr + CSR13);
+ iowrite32(0x0000, ioaddr + CSR14);
+ break;
+ case LC82C168:
+ if ( ! tp->mii_cnt) {
+ tp->nway = 1;
+ tp->nwayset = 0;
+ iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
+ iowrite32(0x30, ioaddr + CSR12);
+ iowrite32(0x0001F078, ioaddr + CSR6);
+ iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
+ }
+ break;
+ case MX98713:
+ case COMPEX9881:
+ iowrite32(0x00000000, ioaddr + CSR6);
+ iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
+ iowrite32(0x00000001, ioaddr + CSR13);
+ break;
+ case MX98715:
+ case MX98725:
+ iowrite32(0x01a80000, ioaddr + CSR6);
+ iowrite32(0xFFFFFFFF, ioaddr + CSR14);
+ iowrite32(0x00001000, ioaddr + CSR12);
+ break;
+ case COMET:
+ /* No initialization necessary. */
+ break;
+ }
+
+ /* put the chip in snooze mode until opened */
+ tulip_set_power_state (tp, 0, 1);
+
+ return 0;
+}
+
+
+/* set the registers according to the given wolopts */
+static void tulip_set_wolopts (struct pci_dev *pdev, u32 wolopts)
+{
+ struct net_device *dev = pci_get_drvdata(pdev);
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+
+ if (tp->flags & COMET_PM) {
+ unsigned int tmp;
+
+ tmp = ioread32(ioaddr + CSR18);
+ tmp &= ~(comet_csr18_pmes_sticky | comet_csr18_apm_mode | comet_csr18_d3a);
+ tmp |= comet_csr18_pm_mode;
+ iowrite32(tmp, ioaddr + CSR18);
+
+ /* Set the Wake-up Control/Status Register to the given WOL options*/
+ tmp = ioread32(ioaddr + CSR13);
+ tmp &= ~(comet_csr13_linkoffe | comet_csr13_linkone | comet_csr13_wfre | comet_csr13_lsce | comet_csr13_mpre);
+ if (wolopts & WAKE_MAGIC)
+ tmp |= comet_csr13_mpre;
+ if (wolopts & WAKE_PHY)
+ tmp |= comet_csr13_linkoffe | comet_csr13_linkone | comet_csr13_lsce;
+ /* Clear the event flags */
+ tmp |= comet_csr13_wfr | comet_csr13_mpr | comet_csr13_lsc;
+ iowrite32(tmp, ioaddr + CSR13);
+ }
+}
+
+static int __maybe_unused tulip_suspend(struct device *dev_d)
+{
+ struct net_device *dev = dev_get_drvdata(dev_d);
+ struct tulip_private *tp = netdev_priv(dev);
+
+ if (!dev)
+ return -EINVAL;
+
+ if (!netif_running(dev))
+ goto save_state;
+
+ tulip_down(dev);
+
+ netif_device_detach(dev);
+ /* FIXME: it needlessly adds an error path. */
+ free_irq(tp->pdev->irq, dev);
+
+save_state:
+ tulip_set_wolopts(to_pci_dev(dev_d), tp->wolinfo.wolopts);
+ device_set_wakeup_enable(dev_d, !!tp->wolinfo.wolopts);
+
+ return 0;
+}
+
+static int __maybe_unused tulip_resume(struct device *dev_d)
+{
+ struct pci_dev *pdev = to_pci_dev(dev_d);
+ struct net_device *dev = dev_get_drvdata(dev_d);
+ struct tulip_private *tp = netdev_priv(dev);
+ void __iomem *ioaddr = tp->base_addr;
+ unsigned int tmp;
+ int retval = 0;
+
+ if (!dev)
+ return -EINVAL;
+
+ if (!netif_running(dev))
+ return 0;
+
+ retval = request_irq(pdev->irq, tulip_interrupt, IRQF_SHARED,
+ dev->name, dev);
+ if (retval) {
+ pr_err("request_irq failed in resume\n");
+ return retval;
+ }
+
+ if (tp->flags & COMET_PM) {
+ device_set_wakeup_enable(dev_d, 0);
+
+ /* Clear the PMES flag */
+ tmp = ioread32(ioaddr + CSR20);
+ tmp |= comet_csr20_pmes;
+ iowrite32(tmp, ioaddr + CSR20);
+
+ /* Disable all wake-up events */
+ tulip_set_wolopts(pdev, 0);
+ }
+ netif_device_attach(dev);
+
+ if (netif_running(dev))
+ tulip_up(dev);
+
+ return 0;
+}
+
+static void tulip_remove_one(struct pci_dev *pdev)
+{
+ struct net_device *dev = pci_get_drvdata (pdev);
+
+ if (!dev)
+ return;
+
+ unregister_netdev(dev);
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+/*
+ * Polling 'interrupt' - used by things like netconsole to send skbs
+ * without having to re-enable interrupts. It's not called while
+ * the interrupt routine is executing.
+ */
+
+static void poll_tulip (struct net_device *dev)
+{
+ struct tulip_private *tp = netdev_priv(dev);
+ const int irq = tp->pdev->irq;
+
+ /* disable_irq here is not very nice, but with the lockless
+ interrupt handler we have no other choice. */
+ disable_irq(irq);
+ tulip_interrupt (irq, dev);
+ enable_irq(irq);
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(tulip_pm_ops, tulip_suspend, tulip_resume);
+
+static struct pci_driver tulip_driver = {
+ .name = DRV_NAME,
+ .id_table = tulip_pci_tbl,
+ .probe = tulip_init_one,
+ .remove = tulip_remove_one,
+ .driver.pm = &tulip_pm_ops,
+};
+
+
+static int __init tulip_init (void)
+{
+ if (!csr0) {
+ pr_warn("tulip: unknown CPU architecture, using default csr0\n");
+ /* default to 8 longword cache line alignment */
+ csr0 = 0x00A00000 | 0x4800;
+ }
+
+ /* copy module parms into globals */
+ tulip_rx_copybreak = rx_copybreak;
+ tulip_max_interrupt_work = max_interrupt_work;
+
+ /* probe for and init boards */
+ return pci_register_driver(&tulip_driver);
+}
+
+
+static void __exit tulip_cleanup (void)
+{
+ pci_unregister_driver (&tulip_driver);
+}
+
+
+module_init(tulip_init);
+module_exit(tulip_cleanup);
diff --git a/drivers/net/ethernet/dec/tulip/uli526x.c b/drivers/net/ethernet/dec/tulip/uli526x.c
new file mode 100644
index 000000000..ff080ab0f
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/uli526x.c
@@ -0,0 +1,1801 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+
+
+*/
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#define DRV_NAME "uli526x"
+
+#include <linux/module.h>
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/skbuff.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/dma-mapping.h>
+#include <linux/bitops.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/dma.h>
+#include <linux/uaccess.h>
+
+#define uw32(reg, val) iowrite32(val, ioaddr + (reg))
+#define ur32(reg) ioread32(ioaddr + (reg))
+
+/* Board/System/Debug information/definition ---------------- */
+#define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
+#define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
+
+#define ULI526X_IO_SIZE 0x100
+#define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
+#define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
+#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
+#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
+#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
+#define TX_BUF_ALLOC 0x600
+#define RX_ALLOC_SIZE 0x620
+#define ULI526X_RESET 1
+#define CR0_DEFAULT 0
+#define CR6_DEFAULT 0x22200000
+#define CR7_DEFAULT 0x180c1
+#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
+#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
+#define MAX_PACKET_SIZE 1514
+#define ULI5261_MAX_MULTICAST 14
+#define RX_COPY_SIZE 100
+#define MAX_CHECK_PACKET 0x8000
+
+#define ULI526X_10MHF 0
+#define ULI526X_100MHF 1
+#define ULI526X_10MFD 4
+#define ULI526X_100MFD 5
+#define ULI526X_AUTO 8
+
+#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
+#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
+#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
+#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
+#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
+#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
+
+#define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
+#define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
+#define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
+
+#define ULI526X_DBUG(dbug_now, msg, value) \
+do { \
+ if (uli526x_debug || (dbug_now)) \
+ pr_err("%s %lx\n", (msg), (long) (value)); \
+} while (0)
+
+#define SHOW_MEDIA_TYPE(mode) \
+ pr_err("Change Speed to %sMhz %s duplex\n", \
+ mode & 1 ? "100" : "10", \
+ mode & 4 ? "full" : "half");
+
+
+/* CR9 definition: SROM/MII */
+#define CR9_SROM_READ 0x4800
+#define CR9_SRCS 0x1
+#define CR9_SRCLK 0x2
+#define CR9_CRDOUT 0x8
+#define SROM_DATA_0 0x0
+#define SROM_DATA_1 0x4
+#define PHY_DATA_1 0x20000
+#define PHY_DATA_0 0x00000
+#define MDCLKH 0x10000
+
+#define PHY_POWER_DOWN 0x800
+
+#define SROM_V41_CODE 0x14
+
+/* Structure/enum declaration ------------------------------- */
+struct tx_desc {
+ __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
+ char *tx_buf_ptr; /* Data for us */
+ struct tx_desc *next_tx_desc;
+} __attribute__(( aligned(32) ));
+
+struct rx_desc {
+ __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
+ struct sk_buff *rx_skb_ptr; /* Data for us */
+ struct rx_desc *next_rx_desc;
+} __attribute__(( aligned(32) ));
+
+struct uli526x_board_info {
+ struct uli_phy_ops {
+ void (*write)(struct uli526x_board_info *, u8, u8, u16);
+ u16 (*read)(struct uli526x_board_info *, u8, u8);
+ } phy;
+ struct net_device *next_dev; /* next device */
+ struct pci_dev *pdev; /* PCI device */
+ spinlock_t lock;
+
+ void __iomem *ioaddr; /* I/O base address */
+ u32 cr0_data;
+ u32 cr5_data;
+ u32 cr6_data;
+ u32 cr7_data;
+ u32 cr15_data;
+
+ /* pointer for memory physical address */
+ dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
+ dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
+ dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
+ dma_addr_t first_tx_desc_dma;
+ dma_addr_t first_rx_desc_dma;
+
+ /* descriptor pointer */
+ unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
+ unsigned char *buf_pool_start; /* Tx buffer pool align dword */
+ unsigned char *desc_pool_ptr; /* descriptor pool memory */
+ struct tx_desc *first_tx_desc;
+ struct tx_desc *tx_insert_ptr;
+ struct tx_desc *tx_remove_ptr;
+ struct rx_desc *first_rx_desc;
+ struct rx_desc *rx_insert_ptr;
+ struct rx_desc *rx_ready_ptr; /* packet come pointer */
+ unsigned long tx_packet_cnt; /* transmitted packet count */
+ unsigned long rx_avail_cnt; /* available rx descriptor count */
+ unsigned long interval_rx_cnt; /* rx packet count a callback time */
+
+ u16 dbug_cnt;
+ u16 NIC_capability; /* NIC media capability */
+ u16 PHY_reg4; /* Saved Phyxcer register 4 value */
+
+ u8 media_mode; /* user specify media mode */
+ u8 op_mode; /* real work media mode */
+ u8 phy_addr;
+ u8 link_failed; /* Ever link failed */
+ u8 wait_reset; /* Hardware failed, need to reset */
+ struct timer_list timer;
+
+ /* Driver defined statistic counter */
+ unsigned long tx_fifo_underrun;
+ unsigned long tx_loss_carrier;
+ unsigned long tx_no_carrier;
+ unsigned long tx_late_collision;
+ unsigned long tx_excessive_collision;
+ unsigned long tx_jabber_timeout;
+ unsigned long reset_count;
+ unsigned long reset_cr8;
+ unsigned long reset_fatal;
+ unsigned long reset_TXtimeout;
+
+ /* NIC SROM data */
+ unsigned char srom[128];
+ u8 init;
+};
+
+enum uli526x_offsets {
+ DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
+ DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
+ DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
+ DCR15 = 0x78
+};
+
+enum uli526x_CR6_bits {
+ CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
+ CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
+ CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
+};
+
+/* Global variable declaration ----------------------------- */
+static int uli526x_debug;
+static unsigned char uli526x_media_mode = ULI526X_AUTO;
+static u32 uli526x_cr6_user_set;
+
+/* For module input parameter */
+static int debug;
+static u32 cr6set;
+static int mode = 8;
+
+/* function declaration ------------------------------------- */
+static int uli526x_open(struct net_device *);
+static netdev_tx_t uli526x_start_xmit(struct sk_buff *,
+ struct net_device *);
+static int uli526x_stop(struct net_device *);
+static void uli526x_set_filter_mode(struct net_device *);
+static const struct ethtool_ops netdev_ethtool_ops;
+static u16 read_srom_word(struct uli526x_board_info *, int);
+static irqreturn_t uli526x_interrupt(int, void *);
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void uli526x_poll(struct net_device *dev);
+#endif
+static void uli526x_descriptor_init(struct net_device *, void __iomem *);
+static void allocate_rx_buffer(struct net_device *);
+static void update_cr6(u32, void __iomem *);
+static void send_filter_frame(struct net_device *, int);
+static u16 phy_readby_cr9(struct uli526x_board_info *, u8, u8);
+static u16 phy_readby_cr10(struct uli526x_board_info *, u8, u8);
+static void phy_writeby_cr9(struct uli526x_board_info *, u8, u8, u16);
+static void phy_writeby_cr10(struct uli526x_board_info *, u8, u8, u16);
+static void phy_write_1bit(struct uli526x_board_info *db, u32);
+static u16 phy_read_1bit(struct uli526x_board_info *db);
+static u8 uli526x_sense_speed(struct uli526x_board_info *);
+static void uli526x_process_mode(struct uli526x_board_info *);
+static void uli526x_timer(struct timer_list *t);
+static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
+static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
+static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
+static void uli526x_dynamic_reset(struct net_device *);
+static void uli526x_free_rxbuffer(struct uli526x_board_info *);
+static void uli526x_init(struct net_device *);
+static void uli526x_set_phyxcer(struct uli526x_board_info *);
+
+static void srom_clk_write(struct uli526x_board_info *db, u32 data)
+{
+ void __iomem *ioaddr = db->ioaddr;
+
+ uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
+ udelay(5);
+ uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
+ udelay(5);
+ uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
+ udelay(5);
+}
+
+/* ULI526X network board routine ---------------------------- */
+
+static const struct net_device_ops netdev_ops = {
+ .ndo_open = uli526x_open,
+ .ndo_stop = uli526x_stop,
+ .ndo_start_xmit = uli526x_start_xmit,
+ .ndo_set_rx_mode = uli526x_set_filter_mode,
+ .ndo_set_mac_address = eth_mac_addr,
+ .ndo_validate_addr = eth_validate_addr,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+ .ndo_poll_controller = uli526x_poll,
+#endif
+};
+
+/*
+ * Search ULI526X board, allocate space and register it
+ */
+
+static int uli526x_init_one(struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+{
+ struct uli526x_board_info *db; /* board information structure */
+ struct net_device *dev;
+ void __iomem *ioaddr;
+ u8 addr[ETH_ALEN];
+ int i, err;
+
+ ULI526X_DBUG(0, "uli526x_init_one()", 0);
+
+ /* Init network device */
+ dev = alloc_etherdev(sizeof(*db));
+ if (dev == NULL)
+ return -ENOMEM;
+ SET_NETDEV_DEV(dev, &pdev->dev);
+
+ if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
+ pr_warn("32-bit PCI DMA not available\n");
+ err = -ENODEV;
+ goto err_out_free;
+ }
+
+ /* Enable Master/IO access, Disable memory access */
+ err = pci_enable_device(pdev);
+ if (err)
+ goto err_out_free;
+
+ if (!pci_resource_start(pdev, 0)) {
+ pr_err("I/O base is zero\n");
+ err = -ENODEV;
+ goto err_out_disable;
+ }
+
+ if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
+ pr_err("Allocated I/O size too small\n");
+ err = -ENODEV;
+ goto err_out_disable;
+ }
+
+ err = pci_request_regions(pdev, DRV_NAME);
+ if (err < 0) {
+ pr_err("Failed to request PCI regions\n");
+ goto err_out_disable;
+ }
+
+ /* Init system & device */
+ db = netdev_priv(dev);
+
+ /* Allocate Tx/Rx descriptor memory */
+ err = -ENOMEM;
+
+ db->desc_pool_ptr = dma_alloc_coherent(&pdev->dev,
+ sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
+ &db->desc_pool_dma_ptr, GFP_KERNEL);
+ if (!db->desc_pool_ptr)
+ goto err_out_release;
+
+ db->buf_pool_ptr = dma_alloc_coherent(&pdev->dev,
+ TX_BUF_ALLOC * TX_DESC_CNT + 4,
+ &db->buf_pool_dma_ptr, GFP_KERNEL);
+ if (!db->buf_pool_ptr)
+ goto err_out_free_tx_desc;
+
+ db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
+ db->first_tx_desc_dma = db->desc_pool_dma_ptr;
+ db->buf_pool_start = db->buf_pool_ptr;
+ db->buf_pool_dma_start = db->buf_pool_dma_ptr;
+
+ switch (ent->driver_data) {
+ case PCI_ULI5263_ID:
+ db->phy.write = phy_writeby_cr10;
+ db->phy.read = phy_readby_cr10;
+ break;
+ default:
+ db->phy.write = phy_writeby_cr9;
+ db->phy.read = phy_readby_cr9;
+ break;
+ }
+
+ /* IO region. */
+ ioaddr = pci_iomap(pdev, 0, 0);
+ if (!ioaddr)
+ goto err_out_free_tx_buf;
+
+ db->ioaddr = ioaddr;
+ db->pdev = pdev;
+ db->init = 1;
+
+ pci_set_drvdata(pdev, dev);
+
+ /* Register some necessary functions */
+ dev->netdev_ops = &netdev_ops;
+ dev->ethtool_ops = &netdev_ethtool_ops;
+
+ spin_lock_init(&db->lock);
+
+
+ /* read 64 word srom data */
+ for (i = 0; i < 64; i++)
+ ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db, i));
+
+ /* Set Node address */
+ if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
+ {
+ uw32(DCR0, 0x10000); //Diagnosis mode
+ uw32(DCR13, 0x1c0); //Reset dianostic pointer port
+ uw32(DCR14, 0); //Clear reset port
+ uw32(DCR14, 0x10); //Reset ID Table pointer
+ uw32(DCR14, 0); //Clear reset port
+ uw32(DCR13, 0); //Clear CR13
+ uw32(DCR13, 0x1b0); //Select ID Table access port
+ //Read MAC address from CR14
+ for (i = 0; i < 6; i++)
+ addr[i] = ur32(DCR14);
+ //Read end
+ uw32(DCR13, 0); //Clear CR13
+ uw32(DCR0, 0); //Clear CR0
+ udelay(10);
+ }
+ else /*Exist SROM*/
+ {
+ for (i = 0; i < 6; i++)
+ addr[i] = db->srom[20 + i];
+ }
+ eth_hw_addr_set(dev, addr);
+
+ err = register_netdev (dev);
+ if (err)
+ goto err_out_unmap;
+
+ netdev_info(dev, "ULi M%04lx at pci%s, %pM, irq %d\n",
+ ent->driver_data >> 16, pci_name(pdev),
+ dev->dev_addr, pdev->irq);
+
+ pci_set_master(pdev);
+
+ return 0;
+
+err_out_unmap:
+ pci_iounmap(pdev, db->ioaddr);
+err_out_free_tx_buf:
+ dma_free_coherent(&pdev->dev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
+ db->buf_pool_ptr, db->buf_pool_dma_ptr);
+err_out_free_tx_desc:
+ dma_free_coherent(&pdev->dev,
+ sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
+ db->desc_pool_ptr, db->desc_pool_dma_ptr);
+err_out_release:
+ pci_release_regions(pdev);
+err_out_disable:
+ pci_disable_device(pdev);
+err_out_free:
+ free_netdev(dev);
+
+ return err;
+}
+
+
+static void uli526x_remove_one(struct pci_dev *pdev)
+{
+ struct net_device *dev = pci_get_drvdata(pdev);
+ struct uli526x_board_info *db = netdev_priv(dev);
+
+ unregister_netdev(dev);
+ pci_iounmap(pdev, db->ioaddr);
+ dma_free_coherent(&db->pdev->dev,
+ sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
+ db->desc_pool_ptr, db->desc_pool_dma_ptr);
+ dma_free_coherent(&db->pdev->dev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
+ db->buf_pool_ptr, db->buf_pool_dma_ptr);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ free_netdev(dev);
+}
+
+
+/*
+ * Open the interface.
+ * The interface is opened whenever "ifconfig" activates it.
+ */
+
+static int uli526x_open(struct net_device *dev)
+{
+ int ret;
+ struct uli526x_board_info *db = netdev_priv(dev);
+
+ ULI526X_DBUG(0, "uli526x_open", 0);
+
+ /* system variable init */
+ db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
+ db->tx_packet_cnt = 0;
+ db->rx_avail_cnt = 0;
+ db->link_failed = 1;
+ netif_carrier_off(dev);
+ db->wait_reset = 0;
+
+ db->NIC_capability = 0xf; /* All capability*/
+ db->PHY_reg4 = 0x1e0;
+
+ /* CR6 operation mode decision */
+ db->cr6_data |= ULI526X_TXTH_256;
+ db->cr0_data = CR0_DEFAULT;
+
+ /* Initialize ULI526X board */
+ uli526x_init(dev);
+
+ ret = request_irq(db->pdev->irq, uli526x_interrupt, IRQF_SHARED,
+ dev->name, dev);
+ if (ret)
+ return ret;
+
+ /* Active System Interface */
+ netif_wake_queue(dev);
+
+ /* set and active a timer process */
+ timer_setup(&db->timer, uli526x_timer, 0);
+ db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
+ add_timer(&db->timer);
+
+ return 0;
+}
+
+
+/* Initialize ULI526X board
+ * Reset ULI526X board
+ * Initialize TX/Rx descriptor chain structure
+ * Send the set-up frame
+ * Enable Tx/Rx machine
+ */
+
+static void uli526x_init(struct net_device *dev)
+{
+ struct uli526x_board_info *db = netdev_priv(dev);
+ struct uli_phy_ops *phy = &db->phy;
+ void __iomem *ioaddr = db->ioaddr;
+ u8 phy_tmp;
+ u8 timeout;
+ u16 phy_reg_reset;
+
+
+ ULI526X_DBUG(0, "uli526x_init()", 0);
+
+ /* Reset M526x MAC controller */
+ uw32(DCR0, ULI526X_RESET); /* RESET MAC */
+ udelay(100);
+ uw32(DCR0, db->cr0_data);
+ udelay(5);
+
+ /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
+ db->phy_addr = 1;
+ for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
+ u16 phy_value;
+
+ phy_value = phy->read(db, phy_tmp, 3); //peer add
+ if (phy_value != 0xffff && phy_value != 0) {
+ db->phy_addr = phy_tmp;
+ break;
+ }
+ }
+
+ if (phy_tmp == 32)
+ pr_warn("Can not find the phy address!!!\n");
+ /* Parser SROM and media mode */
+ db->media_mode = uli526x_media_mode;
+
+ /* phyxcer capability setting */
+ phy_reg_reset = phy->read(db, db->phy_addr, 0);
+ phy_reg_reset = (phy_reg_reset | 0x8000);
+ phy->write(db, db->phy_addr, 0, phy_reg_reset);
+
+ /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
+ * functions") or phy data sheet for details on phy reset
+ */
+ udelay(500);
+ timeout = 10;
+ while (timeout-- && phy->read(db, db->phy_addr, 0) & 0x8000)
+ udelay(100);
+
+ /* Process Phyxcer Media Mode */
+ uli526x_set_phyxcer(db);
+
+ /* Media Mode Process */
+ if ( !(db->media_mode & ULI526X_AUTO) )
+ db->op_mode = db->media_mode; /* Force Mode */
+
+ /* Initialize Transmit/Receive descriptor and CR3/4 */
+ uli526x_descriptor_init(dev, ioaddr);
+
+ /* Init CR6 to program M526X operation */
+ update_cr6(db->cr6_data, ioaddr);
+
+ /* Send setup frame */
+ send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */
+
+ /* Init CR7, interrupt active bit */
+ db->cr7_data = CR7_DEFAULT;
+ uw32(DCR7, db->cr7_data);
+
+ /* Init CR15, Tx jabber and Rx watchdog timer */
+ uw32(DCR15, db->cr15_data);
+
+ /* Enable ULI526X Tx/Rx function */
+ db->cr6_data |= CR6_RXSC | CR6_TXSC;
+ update_cr6(db->cr6_data, ioaddr);
+}
+
+
+/*
+ * Hardware start transmission.
+ * Send a packet to media from the upper layer.
+ */
+
+static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ struct uli526x_board_info *db = netdev_priv(dev);
+ void __iomem *ioaddr = db->ioaddr;
+ struct tx_desc *txptr;
+ unsigned long flags;
+
+ ULI526X_DBUG(0, "uli526x_start_xmit", 0);
+
+ /* Resource flag check */
+ netif_stop_queue(dev);
+
+ /* Too large packet check */
+ if (skb->len > MAX_PACKET_SIZE) {
+ netdev_err(dev, "big packet = %d\n", (u16)skb->len);
+ dev_kfree_skb_any(skb);
+ return NETDEV_TX_OK;
+ }
+
+ spin_lock_irqsave(&db->lock, flags);
+
+ /* No Tx resource check, it never happen nromally */
+ if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
+ spin_unlock_irqrestore(&db->lock, flags);
+ netdev_err(dev, "No Tx resource %ld\n", db->tx_packet_cnt);
+ return NETDEV_TX_BUSY;
+ }
+
+ /* Disable NIC interrupt */
+ uw32(DCR7, 0);
+
+ /* transmit this packet */
+ txptr = db->tx_insert_ptr;
+ skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
+ txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
+
+ /* Point to next transmit free descriptor */
+ db->tx_insert_ptr = txptr->next_tx_desc;
+
+ /* Transmit Packet Process */
+ if (db->tx_packet_cnt < TX_DESC_CNT) {
+ txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
+ db->tx_packet_cnt++; /* Ready to send */
+ uw32(DCR1, 0x1); /* Issue Tx polling */
+ netif_trans_update(dev); /* saved time stamp */
+ }
+
+ /* Tx resource check */
+ if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
+ netif_wake_queue(dev);
+
+ /* Restore CR7 to enable interrupt */
+ spin_unlock_irqrestore(&db->lock, flags);
+ uw32(DCR7, db->cr7_data);
+
+ /* free this SKB */
+ dev_consume_skb_any(skb);
+
+ return NETDEV_TX_OK;
+}
+
+
+/*
+ * Stop the interface.
+ * The interface is stopped when it is brought.
+ */
+
+static int uli526x_stop(struct net_device *dev)
+{
+ struct uli526x_board_info *db = netdev_priv(dev);
+ void __iomem *ioaddr = db->ioaddr;
+
+ /* disable system */
+ netif_stop_queue(dev);
+
+ /* deleted timer */
+ del_timer_sync(&db->timer);
+
+ /* Reset & stop ULI526X board */
+ uw32(DCR0, ULI526X_RESET);
+ udelay(5);
+ db->phy.write(db, db->phy_addr, 0, 0x8000);
+
+ /* free interrupt */
+ free_irq(db->pdev->irq, dev);
+
+ /* free allocated rx buffer */
+ uli526x_free_rxbuffer(db);
+
+ return 0;
+}
+
+
+/*
+ * M5261/M5263 insterrupt handler
+ * receive the packet to upper layer, free the transmitted packet
+ */
+
+static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
+{
+ struct net_device *dev = dev_id;
+ struct uli526x_board_info *db = netdev_priv(dev);
+ void __iomem *ioaddr = db->ioaddr;
+ unsigned long flags;
+
+ spin_lock_irqsave(&db->lock, flags);
+ uw32(DCR7, 0);
+
+ /* Got ULI526X status */
+ db->cr5_data = ur32(DCR5);
+ uw32(DCR5, db->cr5_data);
+ if ( !(db->cr5_data & 0x180c1) ) {
+ /* Restore CR7 to enable interrupt mask */
+ uw32(DCR7, db->cr7_data);
+ spin_unlock_irqrestore(&db->lock, flags);
+ return IRQ_HANDLED;
+ }
+
+ /* Check system status */
+ if (db->cr5_data & 0x2000) {
+ /* system bus error happen */
+ ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
+ db->reset_fatal++;
+ db->wait_reset = 1; /* Need to RESET */
+ spin_unlock_irqrestore(&db->lock, flags);
+ return IRQ_HANDLED;
+ }
+
+ /* Received the coming packet */
+ if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
+ uli526x_rx_packet(dev, db);
+
+ /* reallocate rx descriptor buffer */
+ if (db->rx_avail_cnt<RX_DESC_CNT)
+ allocate_rx_buffer(dev);
+
+ /* Free the transmitted descriptor */
+ if ( db->cr5_data & 0x01)
+ uli526x_free_tx_pkt(dev, db);
+
+ /* Restore CR7 to enable interrupt mask */
+ uw32(DCR7, db->cr7_data);
+
+ spin_unlock_irqrestore(&db->lock, flags);
+ return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void uli526x_poll(struct net_device *dev)
+{
+ struct uli526x_board_info *db = netdev_priv(dev);
+
+ /* ISR grabs the irqsave lock, so this should be safe */
+ uli526x_interrupt(db->pdev->irq, dev);
+}
+#endif
+
+/*
+ * Free TX resource after TX complete
+ */
+
+static void uli526x_free_tx_pkt(struct net_device *dev,
+ struct uli526x_board_info * db)
+{
+ struct tx_desc *txptr;
+ u32 tdes0;
+
+ txptr = db->tx_remove_ptr;
+ while(db->tx_packet_cnt) {
+ tdes0 = le32_to_cpu(txptr->tdes0);
+ if (tdes0 & 0x80000000)
+ break;
+
+ /* A packet sent completed */
+ db->tx_packet_cnt--;
+ dev->stats.tx_packets++;
+
+ /* Transmit statistic counter */
+ if ( tdes0 != 0x7fffffff ) {
+ dev->stats.collisions += (tdes0 >> 3) & 0xf;
+ dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
+ if (tdes0 & TDES0_ERR_MASK) {
+ dev->stats.tx_errors++;
+ if (tdes0 & 0x0002) { /* UnderRun */
+ db->tx_fifo_underrun++;
+ if ( !(db->cr6_data & CR6_SFT) ) {
+ db->cr6_data = db->cr6_data | CR6_SFT;
+ update_cr6(db->cr6_data, db->ioaddr);
+ }
+ }
+ if (tdes0 & 0x0100)
+ db->tx_excessive_collision++;
+ if (tdes0 & 0x0200)
+ db->tx_late_collision++;
+ if (tdes0 & 0x0400)
+ db->tx_no_carrier++;
+ if (tdes0 & 0x0800)
+ db->tx_loss_carrier++;
+ if (tdes0 & 0x4000)
+ db->tx_jabber_timeout++;
+ }
+ }
+
+ txptr = txptr->next_tx_desc;
+ }/* End of while */
+
+ /* Update TX remove pointer to next */
+ db->tx_remove_ptr = txptr;
+
+ /* Resource available check */
+ if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
+ netif_wake_queue(dev); /* Active upper layer, send again */
+}
+
+
+/*
+ * Receive the come packet and pass to upper layer
+ */
+
+static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
+{
+ struct rx_desc *rxptr;
+ struct sk_buff *skb;
+ int rxlen;
+ u32 rdes0;
+
+ rxptr = db->rx_ready_ptr;
+
+ while(db->rx_avail_cnt) {
+ rdes0 = le32_to_cpu(rxptr->rdes0);
+ if (rdes0 & 0x80000000) /* packet owner check */
+ {
+ break;
+ }
+
+ db->rx_avail_cnt--;
+ db->interval_rx_cnt++;
+
+ dma_unmap_single(&db->pdev->dev, le32_to_cpu(rxptr->rdes2),
+ RX_ALLOC_SIZE, DMA_FROM_DEVICE);
+ if ( (rdes0 & 0x300) != 0x300) {
+ /* A packet without First/Last flag */
+ /* reuse this SKB */
+ ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
+ uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
+ } else {
+ /* A packet with First/Last flag */
+ rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
+
+ /* error summary bit check */
+ if (rdes0 & 0x8000) {
+ /* This is a error packet */
+ dev->stats.rx_errors++;
+ if (rdes0 & 1)
+ dev->stats.rx_fifo_errors++;
+ if (rdes0 & 2)
+ dev->stats.rx_crc_errors++;
+ if (rdes0 & 0x80)
+ dev->stats.rx_length_errors++;
+ }
+
+ if ( !(rdes0 & 0x8000) ||
+ ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
+ struct sk_buff *new_skb = NULL;
+
+ skb = rxptr->rx_skb_ptr;
+
+ /* Good packet, send to upper layer */
+ /* Shorst packet used new SKB */
+ if ((rxlen < RX_COPY_SIZE) &&
+ (((new_skb = netdev_alloc_skb(dev, rxlen + 2)) != NULL))) {
+ skb = new_skb;
+ /* size less than COPY_SIZE, allocate a rxlen SKB */
+ skb_reserve(skb, 2); /* 16byte align */
+ skb_put_data(skb,
+ skb_tail_pointer(rxptr->rx_skb_ptr),
+ rxlen);
+ uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
+ } else
+ skb_put(skb, rxlen);
+
+ skb->protocol = eth_type_trans(skb, dev);
+ netif_rx(skb);
+ dev->stats.rx_packets++;
+ dev->stats.rx_bytes += rxlen;
+
+ } else {
+ /* Reuse SKB buffer when the packet is error */
+ ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
+ uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
+ }
+ }
+
+ rxptr = rxptr->next_rx_desc;
+ }
+
+ db->rx_ready_ptr = rxptr;
+}
+
+
+/*
+ * Set ULI526X multicast address
+ */
+
+static void uli526x_set_filter_mode(struct net_device * dev)
+{
+ struct uli526x_board_info *db = netdev_priv(dev);
+ unsigned long flags;
+
+ ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
+ spin_lock_irqsave(&db->lock, flags);
+
+ if (dev->flags & IFF_PROMISC) {
+ ULI526X_DBUG(0, "Enable PROM Mode", 0);
+ db->cr6_data |= CR6_PM | CR6_PBF;
+ update_cr6(db->cr6_data, db->ioaddr);
+ spin_unlock_irqrestore(&db->lock, flags);
+ return;
+ }
+
+ if (dev->flags & IFF_ALLMULTI ||
+ netdev_mc_count(dev) > ULI5261_MAX_MULTICAST) {
+ ULI526X_DBUG(0, "Pass all multicast address",
+ netdev_mc_count(dev));
+ db->cr6_data &= ~(CR6_PM | CR6_PBF);
+ db->cr6_data |= CR6_PAM;
+ spin_unlock_irqrestore(&db->lock, flags);
+ return;
+ }
+
+ ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev));
+ send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */
+ spin_unlock_irqrestore(&db->lock, flags);
+}
+
+static void
+ULi_ethtool_get_link_ksettings(struct uli526x_board_info *db,
+ struct ethtool_link_ksettings *cmd)
+{
+ u32 supported, advertising;
+
+ supported = (SUPPORTED_10baseT_Half |
+ SUPPORTED_10baseT_Full |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full |
+ SUPPORTED_Autoneg |
+ SUPPORTED_MII);
+
+ advertising = (ADVERTISED_10baseT_Half |
+ ADVERTISED_10baseT_Full |
+ ADVERTISED_100baseT_Half |
+ ADVERTISED_100baseT_Full |
+ ADVERTISED_Autoneg |
+ ADVERTISED_MII);
+
+ ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
+ supported);
+ ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
+ advertising);
+
+ cmd->base.port = PORT_MII;
+ cmd->base.phy_address = db->phy_addr;
+
+ cmd->base.speed = SPEED_10;
+ cmd->base.duplex = DUPLEX_HALF;
+
+ if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
+ {
+ cmd->base.speed = SPEED_100;
+ }
+ if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
+ {
+ cmd->base.duplex = DUPLEX_FULL;
+ }
+ if(db->link_failed)
+ {
+ cmd->base.speed = SPEED_UNKNOWN;
+ cmd->base.duplex = DUPLEX_UNKNOWN;
+ }
+
+ if (db->media_mode & ULI526X_AUTO)
+ {
+ cmd->base.autoneg = AUTONEG_ENABLE;
+ }
+}
+
+static void netdev_get_drvinfo(struct net_device *dev,
+ struct ethtool_drvinfo *info)
+{
+ struct uli526x_board_info *np = netdev_priv(dev);
+
+ strscpy(info->driver, DRV_NAME, sizeof(info->driver));
+ strscpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
+}
+
+static int netdev_get_link_ksettings(struct net_device *dev,
+ struct ethtool_link_ksettings *cmd)
+{
+ struct uli526x_board_info *np = netdev_priv(dev);
+
+ ULi_ethtool_get_link_ksettings(np, cmd);
+
+ return 0;
+}
+
+static u32 netdev_get_link(struct net_device *dev) {
+ struct uli526x_board_info *np = netdev_priv(dev);
+
+ if(np->link_failed)
+ return 0;
+ else
+ return 1;
+}
+
+static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+ wol->supported = WAKE_PHY | WAKE_MAGIC;
+ wol->wolopts = 0;
+}
+
+static const struct ethtool_ops netdev_ethtool_ops = {
+ .get_drvinfo = netdev_get_drvinfo,
+ .get_link = netdev_get_link,
+ .get_wol = uli526x_get_wol,
+ .get_link_ksettings = netdev_get_link_ksettings,
+};
+
+/*
+ * A periodic timer routine
+ * Dynamic media sense, allocate Rx buffer...
+ */
+
+static void uli526x_timer(struct timer_list *t)
+{
+ struct uli526x_board_info *db = from_timer(db, t, timer);
+ struct net_device *dev = pci_get_drvdata(db->pdev);
+ struct uli_phy_ops *phy = &db->phy;
+ void __iomem *ioaddr = db->ioaddr;
+ unsigned long flags;
+ u8 tmp_cr12 = 0;
+ u32 tmp_cr8;
+
+ //ULI526X_DBUG(0, "uli526x_timer()", 0);
+ spin_lock_irqsave(&db->lock, flags);
+
+
+ /* Dynamic reset ULI526X : system error or transmit time-out */
+ tmp_cr8 = ur32(DCR8);
+ if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
+ db->reset_cr8++;
+ db->wait_reset = 1;
+ }
+ db->interval_rx_cnt = 0;
+
+ /* TX polling kick monitor */
+ if ( db->tx_packet_cnt &&
+ time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_KICK) ) {
+ uw32(DCR1, 0x1); // Tx polling again
+
+ // TX Timeout
+ if ( time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_TIMEOUT) ) {
+ db->reset_TXtimeout++;
+ db->wait_reset = 1;
+ netdev_err(dev, " Tx timeout - resetting\n");
+ }
+ }
+
+ if (db->wait_reset) {
+ ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
+ db->reset_count++;
+ uli526x_dynamic_reset(dev);
+ db->timer.expires = ULI526X_TIMER_WUT;
+ add_timer(&db->timer);
+ spin_unlock_irqrestore(&db->lock, flags);
+ return;
+ }
+
+ /* Link status check, Dynamic media type change */
+ if ((phy->read(db, db->phy_addr, 5) & 0x01e0)!=0)
+ tmp_cr12 = 3;
+
+ if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
+ /* Link Failed */
+ ULI526X_DBUG(0, "Link Failed", tmp_cr12);
+ netif_carrier_off(dev);
+ netdev_info(dev, "NIC Link is Down\n");
+ db->link_failed = 1;
+
+ /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
+ /* AUTO don't need */
+ if ( !(db->media_mode & 0x8) )
+ phy->write(db, db->phy_addr, 0, 0x1000);
+
+ /* AUTO mode, if INT phyxcer link failed, select EXT device */
+ if (db->media_mode & ULI526X_AUTO) {
+ db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
+ update_cr6(db->cr6_data, db->ioaddr);
+ }
+ } else
+ if ((tmp_cr12 & 0x3) && db->link_failed) {
+ ULI526X_DBUG(0, "Link link OK", tmp_cr12);
+ db->link_failed = 0;
+
+ /* Auto Sense Speed */
+ if ( (db->media_mode & ULI526X_AUTO) &&
+ uli526x_sense_speed(db) )
+ db->link_failed = 1;
+ uli526x_process_mode(db);
+
+ if(db->link_failed==0)
+ {
+ netdev_info(dev, "NIC Link is Up %d Mbps %s duplex\n",
+ (db->op_mode == ULI526X_100MHF ||
+ db->op_mode == ULI526X_100MFD)
+ ? 100 : 10,
+ (db->op_mode == ULI526X_10MFD ||
+ db->op_mode == ULI526X_100MFD)
+ ? "Full" : "Half");
+ netif_carrier_on(dev);
+ }
+ /* SHOW_MEDIA_TYPE(db->op_mode); */
+ }
+ else if(!(tmp_cr12 & 0x3) && db->link_failed)
+ {
+ if(db->init==1)
+ {
+ netdev_info(dev, "NIC Link is Down\n");
+ netif_carrier_off(dev);
+ }
+ }
+ db->init = 0;
+
+ /* Timer active again */
+ db->timer.expires = ULI526X_TIMER_WUT;
+ add_timer(&db->timer);
+ spin_unlock_irqrestore(&db->lock, flags);
+}
+
+
+/*
+ * Stop ULI526X board
+ * Free Tx/Rx allocated memory
+ * Init system variable
+ */
+
+static void uli526x_reset_prepare(struct net_device *dev)
+{
+ struct uli526x_board_info *db = netdev_priv(dev);
+ void __iomem *ioaddr = db->ioaddr;
+
+ /* Sopt MAC controller */
+ db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
+ update_cr6(db->cr6_data, ioaddr);
+ uw32(DCR7, 0); /* Disable Interrupt */
+ uw32(DCR5, ur32(DCR5));
+
+ /* Disable upper layer interface */
+ netif_stop_queue(dev);
+
+ /* Free Rx Allocate buffer */
+ uli526x_free_rxbuffer(db);
+
+ /* system variable init */
+ db->tx_packet_cnt = 0;
+ db->rx_avail_cnt = 0;
+ db->link_failed = 1;
+ db->init=1;
+ db->wait_reset = 0;
+}
+
+
+/*
+ * Dynamic reset the ULI526X board
+ * Stop ULI526X board
+ * Free Tx/Rx allocated memory
+ * Reset ULI526X board
+ * Re-initialize ULI526X board
+ */
+
+static void uli526x_dynamic_reset(struct net_device *dev)
+{
+ ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
+
+ uli526x_reset_prepare(dev);
+
+ /* Re-initialize ULI526X board */
+ uli526x_init(dev);
+
+ /* Restart upper layer interface */
+ netif_wake_queue(dev);
+}
+
+/*
+ * Suspend the interface.
+ */
+
+static int __maybe_unused uli526x_suspend(struct device *dev_d)
+{
+ struct net_device *dev = dev_get_drvdata(dev_d);
+
+ ULI526X_DBUG(0, "uli526x_suspend", 0);
+
+ if (!netif_running(dev))
+ return 0;
+
+ netif_device_detach(dev);
+ uli526x_reset_prepare(dev);
+
+ device_set_wakeup_enable(dev_d, 0);
+
+ return 0;
+}
+
+/*
+ * Resume the interface.
+ */
+
+static int __maybe_unused uli526x_resume(struct device *dev_d)
+{
+ struct net_device *dev = dev_get_drvdata(dev_d);
+
+ ULI526X_DBUG(0, "uli526x_resume", 0);
+
+
+ if (!netif_running(dev))
+ return 0;
+
+ netif_device_attach(dev);
+ /* Re-initialize ULI526X board */
+ uli526x_init(dev);
+ /* Restart upper layer interface */
+ netif_wake_queue(dev);
+
+ return 0;
+}
+
+/*
+ * free all allocated rx buffer
+ */
+
+static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
+{
+ ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
+
+ /* free allocated rx buffer */
+ while (db->rx_avail_cnt) {
+ dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
+ db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
+ db->rx_avail_cnt--;
+ }
+}
+
+
+/*
+ * Reuse the SK buffer
+ */
+
+static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
+{
+ struct rx_desc *rxptr = db->rx_insert_ptr;
+
+ if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
+ rxptr->rx_skb_ptr = skb;
+ rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb_tail_pointer(skb),
+ RX_ALLOC_SIZE, DMA_FROM_DEVICE));
+ wmb();
+ rxptr->rdes0 = cpu_to_le32(0x80000000);
+ db->rx_avail_cnt++;
+ db->rx_insert_ptr = rxptr->next_rx_desc;
+ } else
+ ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
+}
+
+
+/*
+ * Initialize transmit/Receive descriptor
+ * Using Chain structure, and allocate Tx/Rx buffer
+ */
+
+static void uli526x_descriptor_init(struct net_device *dev, void __iomem *ioaddr)
+{
+ struct uli526x_board_info *db = netdev_priv(dev);
+ struct tx_desc *tmp_tx;
+ struct rx_desc *tmp_rx;
+ unsigned char *tmp_buf;
+ dma_addr_t tmp_tx_dma, tmp_rx_dma;
+ dma_addr_t tmp_buf_dma;
+ int i;
+
+ ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
+
+ /* tx descriptor start pointer */
+ db->tx_insert_ptr = db->first_tx_desc;
+ db->tx_remove_ptr = db->first_tx_desc;
+ uw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
+
+ /* rx descriptor start pointer */
+ db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
+ db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
+ db->rx_insert_ptr = db->first_rx_desc;
+ db->rx_ready_ptr = db->first_rx_desc;
+ uw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
+
+ /* Init Transmit chain */
+ tmp_buf = db->buf_pool_start;
+ tmp_buf_dma = db->buf_pool_dma_start;
+ tmp_tx_dma = db->first_tx_desc_dma;
+ for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
+ tmp_tx->tx_buf_ptr = tmp_buf;
+ tmp_tx->tdes0 = cpu_to_le32(0);
+ tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
+ tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
+ tmp_tx_dma += sizeof(struct tx_desc);
+ tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
+ tmp_tx->next_tx_desc = tmp_tx + 1;
+ tmp_buf = tmp_buf + TX_BUF_ALLOC;
+ tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
+ }
+ (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
+ tmp_tx->next_tx_desc = db->first_tx_desc;
+
+ /* Init Receive descriptor chain */
+ tmp_rx_dma=db->first_rx_desc_dma;
+ for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
+ tmp_rx->rdes0 = cpu_to_le32(0);
+ tmp_rx->rdes1 = cpu_to_le32(0x01000600);
+ tmp_rx_dma += sizeof(struct rx_desc);
+ tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
+ tmp_rx->next_rx_desc = tmp_rx + 1;
+ }
+ (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
+ tmp_rx->next_rx_desc = db->first_rx_desc;
+
+ /* pre-allocate Rx buffer */
+ allocate_rx_buffer(dev);
+}
+
+
+/*
+ * Update CR6 value
+ * Firstly stop ULI526X, then written value and start
+ */
+static void update_cr6(u32 cr6_data, void __iomem *ioaddr)
+{
+ uw32(DCR6, cr6_data);
+ udelay(5);
+}
+
+
+/*
+ * Send a setup frame for M5261/M5263
+ * This setup frame initialize ULI526X address filter mode
+ */
+
+#ifdef __BIG_ENDIAN
+#define FLT_SHIFT 16
+#else
+#define FLT_SHIFT 0
+#endif
+
+static void send_filter_frame(struct net_device *dev, int mc_cnt)
+{
+ struct uli526x_board_info *db = netdev_priv(dev);
+ void __iomem *ioaddr = db->ioaddr;
+ struct netdev_hw_addr *ha;
+ struct tx_desc *txptr;
+ const u16 * addrptr;
+ u32 * suptr;
+ int i;
+
+ ULI526X_DBUG(0, "send_filter_frame()", 0);
+
+ txptr = db->tx_insert_ptr;
+ suptr = (u32 *) txptr->tx_buf_ptr;
+
+ /* Node address */
+ addrptr = (const u16 *) dev->dev_addr;
+ *suptr++ = addrptr[0] << FLT_SHIFT;
+ *suptr++ = addrptr[1] << FLT_SHIFT;
+ *suptr++ = addrptr[2] << FLT_SHIFT;
+
+ /* broadcast address */
+ *suptr++ = 0xffff << FLT_SHIFT;
+ *suptr++ = 0xffff << FLT_SHIFT;
+ *suptr++ = 0xffff << FLT_SHIFT;
+
+ /* fit the multicast address */
+ netdev_for_each_mc_addr(ha, dev) {
+ addrptr = (u16 *) ha->addr;
+ *suptr++ = addrptr[0] << FLT_SHIFT;
+ *suptr++ = addrptr[1] << FLT_SHIFT;
+ *suptr++ = addrptr[2] << FLT_SHIFT;
+ }
+
+ for (i = netdev_mc_count(dev); i < 14; i++) {
+ *suptr++ = 0xffff << FLT_SHIFT;
+ *suptr++ = 0xffff << FLT_SHIFT;
+ *suptr++ = 0xffff << FLT_SHIFT;
+ }
+
+ /* prepare the setup frame */
+ db->tx_insert_ptr = txptr->next_tx_desc;
+ txptr->tdes1 = cpu_to_le32(0x890000c0);
+
+ /* Resource Check and Send the setup packet */
+ if (db->tx_packet_cnt < TX_DESC_CNT) {
+ /* Resource Empty */
+ db->tx_packet_cnt++;
+ txptr->tdes0 = cpu_to_le32(0x80000000);
+ update_cr6(db->cr6_data | 0x2000, ioaddr);
+ uw32(DCR1, 0x1); /* Issue Tx polling */
+ update_cr6(db->cr6_data, ioaddr);
+ netif_trans_update(dev);
+ } else
+ netdev_err(dev, "No Tx resource - Send_filter_frame!\n");
+}
+
+
+/*
+ * Allocate rx buffer,
+ * As possible as allocate maxiumn Rx buffer
+ */
+
+static void allocate_rx_buffer(struct net_device *dev)
+{
+ struct uli526x_board_info *db = netdev_priv(dev);
+ struct rx_desc *rxptr;
+ struct sk_buff *skb;
+
+ rxptr = db->rx_insert_ptr;
+
+ while(db->rx_avail_cnt < RX_DESC_CNT) {
+ skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE);
+ if (skb == NULL)
+ break;
+ rxptr->rx_skb_ptr = skb; /* FIXME (?) */
+ rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb_tail_pointer(skb),
+ RX_ALLOC_SIZE, DMA_FROM_DEVICE));
+ wmb();
+ rxptr->rdes0 = cpu_to_le32(0x80000000);
+ rxptr = rxptr->next_rx_desc;
+ db->rx_avail_cnt++;
+ }
+
+ db->rx_insert_ptr = rxptr;
+}
+
+
+/*
+ * Read one word data from the serial ROM
+ */
+
+static u16 read_srom_word(struct uli526x_board_info *db, int offset)
+{
+ void __iomem *ioaddr = db->ioaddr;
+ u16 srom_data = 0;
+ int i;
+
+ uw32(DCR9, CR9_SROM_READ);
+ uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
+
+ /* Send the Read Command 110b */
+ srom_clk_write(db, SROM_DATA_1);
+ srom_clk_write(db, SROM_DATA_1);
+ srom_clk_write(db, SROM_DATA_0);
+
+ /* Send the offset */
+ for (i = 5; i >= 0; i--) {
+ srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
+ srom_clk_write(db, srom_data);
+ }
+
+ uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
+
+ for (i = 16; i > 0; i--) {
+ uw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
+ udelay(5);
+ srom_data = (srom_data << 1) |
+ ((ur32(DCR9) & CR9_CRDOUT) ? 1 : 0);
+ uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
+ udelay(5);
+ }
+
+ uw32(DCR9, CR9_SROM_READ);
+ return srom_data;
+}
+
+
+/*
+ * Auto sense the media mode
+ */
+
+static u8 uli526x_sense_speed(struct uli526x_board_info * db)
+{
+ struct uli_phy_ops *phy = &db->phy;
+ u8 ErrFlag = 0;
+ u16 phy_mode;
+
+ phy_mode = phy->read(db, db->phy_addr, 1);
+ phy_mode = phy->read(db, db->phy_addr, 1);
+
+ if ( (phy_mode & 0x24) == 0x24 ) {
+
+ phy_mode = ((phy->read(db, db->phy_addr, 5) & 0x01e0)<<7);
+ if(phy_mode&0x8000)
+ phy_mode = 0x8000;
+ else if(phy_mode&0x4000)
+ phy_mode = 0x4000;
+ else if(phy_mode&0x2000)
+ phy_mode = 0x2000;
+ else
+ phy_mode = 0x1000;
+
+ switch (phy_mode) {
+ case 0x1000: db->op_mode = ULI526X_10MHF; break;
+ case 0x2000: db->op_mode = ULI526X_10MFD; break;
+ case 0x4000: db->op_mode = ULI526X_100MHF; break;
+ case 0x8000: db->op_mode = ULI526X_100MFD; break;
+ default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
+ }
+ } else {
+ db->op_mode = ULI526X_10MHF;
+ ULI526X_DBUG(0, "Link Failed :", phy_mode);
+ ErrFlag = 1;
+ }
+
+ return ErrFlag;
+}
+
+
+/*
+ * Set 10/100 phyxcer capability
+ * AUTO mode : phyxcer register4 is NIC capability
+ * Force mode: phyxcer register4 is the force media
+ */
+
+static void uli526x_set_phyxcer(struct uli526x_board_info *db)
+{
+ struct uli_phy_ops *phy = &db->phy;
+ u16 phy_reg;
+
+ /* Phyxcer capability setting */
+ phy_reg = phy->read(db, db->phy_addr, 4) & ~0x01e0;
+
+ if (db->media_mode & ULI526X_AUTO) {
+ /* AUTO Mode */
+ phy_reg |= db->PHY_reg4;
+ } else {
+ /* Force Mode */
+ switch(db->media_mode) {
+ case ULI526X_10MHF: phy_reg |= 0x20; break;
+ case ULI526X_10MFD: phy_reg |= 0x40; break;
+ case ULI526X_100MHF: phy_reg |= 0x80; break;
+ case ULI526X_100MFD: phy_reg |= 0x100; break;
+ }
+
+ }
+
+ /* Write new capability to Phyxcer Reg4 */
+ if ( !(phy_reg & 0x01e0)) {
+ phy_reg|=db->PHY_reg4;
+ db->media_mode|=ULI526X_AUTO;
+ }
+ phy->write(db, db->phy_addr, 4, phy_reg);
+
+ /* Restart Auto-Negotiation */
+ phy->write(db, db->phy_addr, 0, 0x1200);
+ udelay(50);
+}
+
+
+/*
+ * Process op-mode
+ AUTO mode : PHY controller in Auto-negotiation Mode
+ * Force mode: PHY controller in force mode with HUB
+ * N-way force capability with SWITCH
+ */
+
+static void uli526x_process_mode(struct uli526x_board_info *db)
+{
+ struct uli_phy_ops *phy = &db->phy;
+ u16 phy_reg;
+
+ /* Full Duplex Mode Check */
+ if (db->op_mode & 0x4)
+ db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
+ else
+ db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
+
+ update_cr6(db->cr6_data, db->ioaddr);
+
+ /* 10/100M phyxcer force mode need */
+ if (!(db->media_mode & 0x8)) {
+ /* Forece Mode */
+ phy_reg = phy->read(db, db->phy_addr, 6);
+ if (!(phy_reg & 0x1)) {
+ /* parter without N-Way capability */
+ phy_reg = 0x0;
+ switch(db->op_mode) {
+ case ULI526X_10MHF: phy_reg = 0x0; break;
+ case ULI526X_10MFD: phy_reg = 0x100; break;
+ case ULI526X_100MHF: phy_reg = 0x2000; break;
+ case ULI526X_100MFD: phy_reg = 0x2100; break;
+ }
+ phy->write(db, db->phy_addr, 0, phy_reg);
+ }
+ }
+}
+
+
+/* M5261/M5263 Chip */
+static void phy_writeby_cr9(struct uli526x_board_info *db, u8 phy_addr,
+ u8 offset, u16 phy_data)
+{
+ u16 i;
+
+ /* Send 33 synchronization clock to Phy controller */
+ for (i = 0; i < 35; i++)
+ phy_write_1bit(db, PHY_DATA_1);
+
+ /* Send start command(01) to Phy */
+ phy_write_1bit(db, PHY_DATA_0);
+ phy_write_1bit(db, PHY_DATA_1);
+
+ /* Send write command(01) to Phy */
+ phy_write_1bit(db, PHY_DATA_0);
+ phy_write_1bit(db, PHY_DATA_1);
+
+ /* Send Phy address */
+ for (i = 0x10; i > 0; i = i >> 1)
+ phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
+
+ /* Send register address */
+ for (i = 0x10; i > 0; i = i >> 1)
+ phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
+
+ /* written trasnition */
+ phy_write_1bit(db, PHY_DATA_1);
+ phy_write_1bit(db, PHY_DATA_0);
+
+ /* Write a word data to PHY controller */
+ for (i = 0x8000; i > 0; i >>= 1)
+ phy_write_1bit(db, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
+}
+
+static u16 phy_readby_cr9(struct uli526x_board_info *db, u8 phy_addr, u8 offset)
+{
+ u16 phy_data;
+ int i;
+
+ /* Send 33 synchronization clock to Phy controller */
+ for (i = 0; i < 35; i++)
+ phy_write_1bit(db, PHY_DATA_1);
+
+ /* Send start command(01) to Phy */
+ phy_write_1bit(db, PHY_DATA_0);
+ phy_write_1bit(db, PHY_DATA_1);
+
+ /* Send read command(10) to Phy */
+ phy_write_1bit(db, PHY_DATA_1);
+ phy_write_1bit(db, PHY_DATA_0);
+
+ /* Send Phy address */
+ for (i = 0x10; i > 0; i = i >> 1)
+ phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
+
+ /* Send register address */
+ for (i = 0x10; i > 0; i = i >> 1)
+ phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
+
+ /* Skip transition state */
+ phy_read_1bit(db);
+
+ /* read 16bit data */
+ for (phy_data = 0, i = 0; i < 16; i++) {
+ phy_data <<= 1;
+ phy_data |= phy_read_1bit(db);
+ }
+
+ return phy_data;
+}
+
+static u16 phy_readby_cr10(struct uli526x_board_info *db, u8 phy_addr,
+ u8 offset)
+{
+ void __iomem *ioaddr = db->ioaddr;
+ u32 cr10_value = phy_addr;
+
+ cr10_value = (cr10_value << 5) + offset;
+ cr10_value = (cr10_value << 16) + 0x08000000;
+ uw32(DCR10, cr10_value);
+ udelay(1);
+ while (1) {
+ cr10_value = ur32(DCR10);
+ if (cr10_value & 0x10000000)
+ break;
+ }
+ return cr10_value & 0x0ffff;
+}
+
+static void phy_writeby_cr10(struct uli526x_board_info *db, u8 phy_addr,
+ u8 offset, u16 phy_data)
+{
+ void __iomem *ioaddr = db->ioaddr;
+ u32 cr10_value = phy_addr;
+
+ cr10_value = (cr10_value << 5) + offset;
+ cr10_value = (cr10_value << 16) + 0x04000000 + phy_data;
+ uw32(DCR10, cr10_value);
+ udelay(1);
+}
+/*
+ * Write one bit data to Phy Controller
+ */
+
+static void phy_write_1bit(struct uli526x_board_info *db, u32 data)
+{
+ void __iomem *ioaddr = db->ioaddr;
+
+ uw32(DCR9, data); /* MII Clock Low */
+ udelay(1);
+ uw32(DCR9, data | MDCLKH); /* MII Clock High */
+ udelay(1);
+ uw32(DCR9, data); /* MII Clock Low */
+ udelay(1);
+}
+
+
+/*
+ * Read one bit phy data from PHY controller
+ */
+
+static u16 phy_read_1bit(struct uli526x_board_info *db)
+{
+ void __iomem *ioaddr = db->ioaddr;
+ u16 phy_data;
+
+ uw32(DCR9, 0x50000);
+ udelay(1);
+ phy_data = (ur32(DCR9) >> 19) & 0x1;
+ uw32(DCR9, 0x40000);
+ udelay(1);
+
+ return phy_data;
+}
+
+
+static const struct pci_device_id uli526x_pci_tbl[] = {
+ { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
+ { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
+ { 0, }
+};
+MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
+
+static SIMPLE_DEV_PM_OPS(uli526x_pm_ops, uli526x_suspend, uli526x_resume);
+
+static struct pci_driver uli526x_driver = {
+ .name = "uli526x",
+ .id_table = uli526x_pci_tbl,
+ .probe = uli526x_init_one,
+ .remove = uli526x_remove_one,
+ .driver.pm = &uli526x_pm_ops,
+};
+
+MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
+MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
+MODULE_LICENSE("GPL");
+
+module_param(debug, int, 0644);
+module_param(mode, int, 0);
+module_param(cr6set, int, 0);
+MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
+MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
+
+/* Description:
+ * when user used insmod to add module, system invoked init_module()
+ * to register the services.
+ */
+
+static int __init uli526x_init_module(void)
+{
+
+ ULI526X_DBUG(0, "init_module() ", debug);
+
+ if (debug)
+ uli526x_debug = debug; /* set debug flag */
+ if (cr6set)
+ uli526x_cr6_user_set = cr6set;
+
+ switch (mode) {
+ case ULI526X_10MHF:
+ case ULI526X_100MHF:
+ case ULI526X_10MFD:
+ case ULI526X_100MFD:
+ uli526x_media_mode = mode;
+ break;
+ default:
+ uli526x_media_mode = ULI526X_AUTO;
+ break;
+ }
+
+ return pci_register_driver(&uli526x_driver);
+}
+
+
+/*
+ * Description:
+ * when user used rmmod to delete module, system invoked clean_module()
+ * to un-register all registered services.
+ */
+
+static void __exit uli526x_cleanup_module(void)
+{
+ ULI526X_DBUG(0, "uli526x_cleanup_module() ", debug);
+ pci_unregister_driver(&uli526x_driver);
+}
+
+module_init(uli526x_init_module);
+module_exit(uli526x_cleanup_module);
diff --git a/drivers/net/ethernet/dec/tulip/winbond-840.c b/drivers/net/ethernet/dec/tulip/winbond-840.c
new file mode 100644
index 000000000..37fba39c0
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/winbond-840.c
@@ -0,0 +1,1629 @@
+/* winbond-840.c: A Linux PCI network adapter device driver. */
+/*
+ Written 1998-2001 by Donald Becker.
+
+ This software may be used and distributed according to the terms of
+ the GNU General Public License (GPL), incorporated herein by reference.
+ Drivers based on or derived from this code fall under the GPL and must
+ retain the authorship, copyright and license notice. This file is not
+ a complete program and may only be used when the entire operating
+ system is licensed under the GPL.
+
+ The author may be reached as becker@scyld.com, or C/O
+ Scyld Computing Corporation
+ 410 Severn Ave., Suite 210
+ Annapolis MD 21403
+
+ Support and updates available at
+ http://www.scyld.com/network/drivers.html
+
+ Do not remove the copyright information.
+ Do not change the version information unless an improvement has been made.
+ Merely removing my name, as Compex has done in the past, does not count
+ as an improvement.
+
+ Changelog:
+ * ported to 2.4
+ ???
+ * spin lock update, memory barriers, new style dma mappings
+ limit each tx buffer to < 1024 bytes
+ remove DescIntr from Rx descriptors (that's an Tx flag)
+ remove next pointer from Tx descriptors
+ synchronize tx_q_bytes
+ software reset in tx_timeout
+ Copyright (C) 2000 Manfred Spraul
+ * further cleanups
+ power management.
+ support for big endian descriptors
+ Copyright (C) 2001 Manfred Spraul
+ * ethtool support (jgarzik)
+ * Replace some MII-related magic numbers with constants (jgarzik)
+
+ TODO:
+ * enable pci_power_off
+ * Wake-On-LAN
+*/
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#define DRV_NAME "winbond-840"
+
+/* Automatically extracted configuration info:
+probe-func: winbond840_probe
+config-in: tristate 'Winbond W89c840 Ethernet support' CONFIG_WINBOND_840
+
+c-help-name: Winbond W89c840 PCI Ethernet support
+c-help-symbol: CONFIG_WINBOND_840
+c-help: This driver is for the Winbond W89c840 chip. It also works with
+c-help: the TX9882 chip on the Compex RL100-ATX board.
+c-help: More specific information and updates are available from
+c-help: http://www.scyld.com/network/drivers.html
+*/
+
+/* The user-configurable values.
+ These may be modified when a driver module is loaded.*/
+
+static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
+static int max_interrupt_work = 20;
+/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
+ The '840 uses a 64 element hash table based on the Ethernet CRC. */
+static int multicast_filter_limit = 32;
+
+/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
+ Setting to > 1518 effectively disables this feature. */
+static int rx_copybreak;
+
+/* Used to pass the media type, etc.
+ Both 'options[]' and 'full_duplex[]' should exist for driver
+ interoperability.
+ The media type is usually passed in 'options[]'.
+*/
+#define MAX_UNITS 8 /* More are supported, limit only on options */
+static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
+static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
+
+/* Operational parameters that are set at compile time. */
+
+/* Keep the ring sizes a power of two for compile efficiency.
+ The compiler will convert <unsigned>'%'<2^N> into a bit mask.
+ Making the Tx ring too large decreases the effectiveness of channel
+ bonding and packet priority.
+ There are no ill effects from too-large receive rings. */
+#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
+#define TX_QUEUE_LEN_RESTART 5
+
+#define TX_BUFLIMIT (1024-128)
+
+/* The presumed FIFO size for working around the Tx-FIFO-overflow bug.
+ To avoid overflowing we don't queue again until we have room for a
+ full-size packet.
+ */
+#define TX_FIFO_SIZE (2048)
+#define TX_BUG_FIFO_LIMIT (TX_FIFO_SIZE-1514-16)
+
+
+/* Operational parameters that usually are not changed. */
+/* Time in jiffies before concluding the transmitter is hung. */
+#define TX_TIMEOUT (2*HZ)
+
+/* Include files, designed to support most kernel versions 2.0.0 and later. */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/dma-mapping.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#include <linux/rtnetlink.h>
+#include <linux/crc32.h>
+#include <linux/bitops.h>
+#include <linux/uaccess.h>
+#include <asm/processor.h> /* Processor type for cache alignment. */
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include "tulip.h"
+
+#undef PKT_BUF_SZ /* tulip.h also defines this */
+#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
+
+MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
+MODULE_DESCRIPTION("Winbond W89c840 Ethernet driver");
+MODULE_LICENSE("GPL");
+
+module_param(max_interrupt_work, int, 0);
+module_param(debug, int, 0);
+module_param(rx_copybreak, int, 0);
+module_param(multicast_filter_limit, int, 0);
+module_param_array(options, int, NULL, 0);
+module_param_array(full_duplex, int, NULL, 0);
+MODULE_PARM_DESC(max_interrupt_work, "winbond-840 maximum events handled per interrupt");
+MODULE_PARM_DESC(debug, "winbond-840 debug level (0-6)");
+MODULE_PARM_DESC(rx_copybreak, "winbond-840 copy breakpoint for copy-only-tiny-frames");
+MODULE_PARM_DESC(multicast_filter_limit, "winbond-840 maximum number of filtered multicast addresses");
+MODULE_PARM_DESC(options, "winbond-840: Bits 0-3: media type, bit 17: full duplex");
+MODULE_PARM_DESC(full_duplex, "winbond-840 full duplex setting(s) (1)");
+
+/*
+ Theory of Operation
+
+I. Board Compatibility
+
+This driver is for the Winbond w89c840 chip.
+
+II. Board-specific settings
+
+None.
+
+III. Driver operation
+
+This chip is very similar to the Digital 21*4* "Tulip" family. The first
+twelve registers and the descriptor format are nearly identical. Read a
+Tulip manual for operational details.
+
+A significant difference is that the multicast filter and station address are
+stored in registers rather than loaded through a pseudo-transmit packet.
+
+Unlike the Tulip, transmit buffers are limited to 1KB. To transmit a
+full-sized packet we must use both data buffers in a descriptor. Thus the
+driver uses ring mode where descriptors are implicitly sequential in memory,
+rather than using the second descriptor address as a chain pointer to
+subsequent descriptors.
+
+IV. Notes
+
+If you are going to almost clone a Tulip, why not go all the way and avoid
+the need for a new driver?
+
+IVb. References
+
+http://www.scyld.com/expert/100mbps.html
+http://www.scyld.com/expert/NWay.html
+http://www.winbond.com.tw/
+
+IVc. Errata
+
+A horrible bug exists in the transmit FIFO. Apparently the chip doesn't
+correctly detect a full FIFO, and queuing more than 2048 bytes may result in
+silent data corruption.
+
+Test with 'ping -s 10000' on a fast computer.
+
+*/
+
+
+
+/*
+ PCI probe table.
+*/
+enum chip_capability_flags {
+ CanHaveMII=1, HasBrokenTx=2, AlwaysFDX=4, FDXOnNoMII=8,
+};
+
+static const struct pci_device_id w840_pci_tbl[] = {
+ { 0x1050, 0x0840, PCI_ANY_ID, 0x8153, 0, 0, 0 },
+ { 0x1050, 0x0840, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
+ { 0x11f6, 0x2011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
+ { }
+};
+MODULE_DEVICE_TABLE(pci, w840_pci_tbl);
+
+enum {
+ netdev_res_size = 128, /* size of PCI BAR resource */
+};
+
+struct pci_id_info {
+ const char *name;
+ int drv_flags; /* Driver use, intended as capability flags. */
+};
+
+static const struct pci_id_info pci_id_tbl[] = {
+ { /* Sometime a Level-One switch card. */
+ "Winbond W89c840", CanHaveMII | HasBrokenTx | FDXOnNoMII},
+ { "Winbond W89c840", CanHaveMII | HasBrokenTx},
+ { "Compex RL100-ATX", CanHaveMII | HasBrokenTx},
+ { } /* terminate list. */
+};
+
+/* This driver was written to use PCI memory space, however some x86 systems
+ work only with I/O space accesses. See CONFIG_TULIP_MMIO in .config
+*/
+
+/* Offsets to the Command and Status Registers, "CSRs".
+ While similar to the Tulip, these registers are longword aligned.
+ Note: It's not useful to define symbolic names for every register bit in
+ the device. The name can only partially document the semantics and make
+ the driver longer and more difficult to read.
+*/
+enum w840_offsets {
+ PCIBusCfg=0x00, TxStartDemand=0x04, RxStartDemand=0x08,
+ RxRingPtr=0x0C, TxRingPtr=0x10,
+ IntrStatus=0x14, NetworkConfig=0x18, IntrEnable=0x1C,
+ RxMissed=0x20, EECtrl=0x24, MIICtrl=0x24, BootRom=0x28, GPTimer=0x2C,
+ CurRxDescAddr=0x30, CurRxBufAddr=0x34, /* Debug use */
+ MulticastFilter0=0x38, MulticastFilter1=0x3C, StationAddr=0x40,
+ CurTxDescAddr=0x4C, CurTxBufAddr=0x50,
+};
+
+/* Bits in the NetworkConfig register. */
+enum rx_mode_bits {
+ AcceptErr=0x80,
+ RxAcceptBroadcast=0x20, AcceptMulticast=0x10,
+ RxAcceptAllPhys=0x08, AcceptMyPhys=0x02,
+};
+
+enum mii_reg_bits {
+ MDIO_ShiftClk=0x10000, MDIO_DataIn=0x80000, MDIO_DataOut=0x20000,
+ MDIO_EnbOutput=0x40000, MDIO_EnbIn = 0x00000,
+};
+
+/* The Tulip Rx and Tx buffer descriptors. */
+struct w840_rx_desc {
+ s32 status;
+ s32 length;
+ u32 buffer1;
+ u32 buffer2;
+};
+
+struct w840_tx_desc {
+ s32 status;
+ s32 length;
+ u32 buffer1, buffer2;
+};
+
+#define MII_CNT 1 /* winbond only supports one MII */
+struct netdev_private {
+ struct w840_rx_desc *rx_ring;
+ dma_addr_t rx_addr[RX_RING_SIZE];
+ struct w840_tx_desc *tx_ring;
+ dma_addr_t tx_addr[TX_RING_SIZE];
+ dma_addr_t ring_dma_addr;
+ /* The addresses of receive-in-place skbuffs. */
+ struct sk_buff* rx_skbuff[RX_RING_SIZE];
+ /* The saved address of a sent-in-place packet/buffer, for later free(). */
+ struct sk_buff* tx_skbuff[TX_RING_SIZE];
+ struct net_device_stats stats;
+ struct timer_list timer; /* Media monitoring timer. */
+ /* Frequently used values: keep some adjacent for cache effect. */
+ spinlock_t lock;
+ int chip_id, drv_flags;
+ struct pci_dev *pci_dev;
+ int csr6;
+ struct w840_rx_desc *rx_head_desc;
+ unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
+ unsigned int rx_buf_sz; /* Based on MTU+slack. */
+ unsigned int cur_tx, dirty_tx;
+ unsigned int tx_q_bytes;
+ unsigned int tx_full; /* The Tx queue is full. */
+ /* MII transceiver section. */
+ int mii_cnt; /* MII device addresses. */
+ unsigned char phys[MII_CNT]; /* MII device addresses, but only the first is used */
+ u32 mii;
+ struct mii_if_info mii_if;
+ void __iomem *base_addr;
+};
+
+static int eeprom_read(void __iomem *ioaddr, int location);
+static int mdio_read(struct net_device *dev, int phy_id, int location);
+static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
+static int netdev_open(struct net_device *dev);
+static int update_link(struct net_device *dev);
+static void netdev_timer(struct timer_list *t);
+static void init_rxtx_rings(struct net_device *dev);
+static void free_rxtx_rings(struct netdev_private *np);
+static void init_registers(struct net_device *dev);
+static void tx_timeout(struct net_device *dev, unsigned int txqueue);
+static int alloc_ringdesc(struct net_device *dev);
+static void free_ringdesc(struct netdev_private *np);
+static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
+static irqreturn_t intr_handler(int irq, void *dev_instance);
+static void netdev_error(struct net_device *dev, int intr_status);
+static int netdev_rx(struct net_device *dev);
+static u32 __set_rx_mode(struct net_device *dev);
+static void set_rx_mode(struct net_device *dev);
+static struct net_device_stats *get_stats(struct net_device *dev);
+static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
+static const struct ethtool_ops netdev_ethtool_ops;
+static int netdev_close(struct net_device *dev);
+
+static const struct net_device_ops netdev_ops = {
+ .ndo_open = netdev_open,
+ .ndo_stop = netdev_close,
+ .ndo_start_xmit = start_tx,
+ .ndo_get_stats = get_stats,
+ .ndo_set_rx_mode = set_rx_mode,
+ .ndo_eth_ioctl = netdev_ioctl,
+ .ndo_tx_timeout = tx_timeout,
+ .ndo_set_mac_address = eth_mac_addr,
+ .ndo_validate_addr = eth_validate_addr,
+};
+
+static int w840_probe1(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+ struct net_device *dev;
+ struct netdev_private *np;
+ static int find_cnt;
+ int chip_idx = ent->driver_data;
+ int irq;
+ int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
+ __le16 addr[ETH_ALEN / 2];
+ void __iomem *ioaddr;
+
+ i = pcim_enable_device(pdev);
+ if (i) return i;
+
+ pci_set_master(pdev);
+
+ irq = pdev->irq;
+
+ if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
+ pr_warn("Device %s disabled due to DMA limitations\n",
+ pci_name(pdev));
+ return -EIO;
+ }
+ dev = alloc_etherdev(sizeof(*np));
+ if (!dev)
+ return -ENOMEM;
+ SET_NETDEV_DEV(dev, &pdev->dev);
+
+ if (pci_request_regions(pdev, DRV_NAME))
+ goto err_out_netdev;
+
+ ioaddr = pci_iomap(pdev, TULIP_BAR, netdev_res_size);
+ if (!ioaddr)
+ goto err_out_netdev;
+
+ for (i = 0; i < 3; i++)
+ addr[i] = cpu_to_le16(eeprom_read(ioaddr, i));
+ eth_hw_addr_set(dev, (u8 *)addr);
+
+ /* Reset the chip to erase previous misconfiguration.
+ No hold time required! */
+ iowrite32(0x00000001, ioaddr + PCIBusCfg);
+
+ np = netdev_priv(dev);
+ np->pci_dev = pdev;
+ np->chip_id = chip_idx;
+ np->drv_flags = pci_id_tbl[chip_idx].drv_flags;
+ spin_lock_init(&np->lock);
+ np->mii_if.dev = dev;
+ np->mii_if.mdio_read = mdio_read;
+ np->mii_if.mdio_write = mdio_write;
+ np->base_addr = ioaddr;
+
+ pci_set_drvdata(pdev, dev);
+
+ if (dev->mem_start)
+ option = dev->mem_start;
+
+ /* The lower four bits are the media type. */
+ if (option > 0) {
+ if (option & 0x200)
+ np->mii_if.full_duplex = 1;
+ if (option & 15)
+ dev_info(&dev->dev,
+ "ignoring user supplied media type %d",
+ option & 15);
+ }
+ if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
+ np->mii_if.full_duplex = 1;
+
+ if (np->mii_if.full_duplex)
+ np->mii_if.force_media = 1;
+
+ /* The chip-specific entries in the device structure. */
+ dev->netdev_ops = &netdev_ops;
+ dev->ethtool_ops = &netdev_ethtool_ops;
+ dev->watchdog_timeo = TX_TIMEOUT;
+
+ i = register_netdev(dev);
+ if (i)
+ goto err_out_cleardev;
+
+ dev_info(&dev->dev, "%s at %p, %pM, IRQ %d\n",
+ pci_id_tbl[chip_idx].name, ioaddr, dev->dev_addr, irq);
+
+ if (np->drv_flags & CanHaveMII) {
+ int phy, phy_idx = 0;
+ for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
+ int mii_status = mdio_read(dev, phy, MII_BMSR);
+ if (mii_status != 0xffff && mii_status != 0x0000) {
+ np->phys[phy_idx++] = phy;
+ np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
+ np->mii = (mdio_read(dev, phy, MII_PHYSID1) << 16)+
+ mdio_read(dev, phy, MII_PHYSID2);
+ dev_info(&dev->dev,
+ "MII PHY %08xh found at address %d, status 0x%04x advertising %04x\n",
+ np->mii, phy, mii_status,
+ np->mii_if.advertising);
+ }
+ }
+ np->mii_cnt = phy_idx;
+ np->mii_if.phy_id = np->phys[0];
+ if (phy_idx == 0) {
+ dev_warn(&dev->dev,
+ "MII PHY not found -- this device may not operate correctly\n");
+ }
+ }
+
+ find_cnt++;
+ return 0;
+
+err_out_cleardev:
+ pci_iounmap(pdev, ioaddr);
+err_out_netdev:
+ free_netdev (dev);
+ return -ENODEV;
+}
+
+
+/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. These are
+ often serial bit streams generated by the host processor.
+ The example below is for the common 93c46 EEPROM, 64 16 bit words. */
+
+/* Delay between EEPROM clock transitions.
+ No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
+ a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
+ made udelay() unreliable.
+*/
+#define eeprom_delay(ee_addr) ioread32(ee_addr)
+
+enum EEPROM_Ctrl_Bits {
+ EE_ShiftClk=0x02, EE_Write0=0x801, EE_Write1=0x805,
+ EE_ChipSelect=0x801, EE_DataIn=0x08,
+};
+
+/* The EEPROM commands include the alway-set leading bit. */
+enum EEPROM_Cmds {
+ EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
+};
+
+static int eeprom_read(void __iomem *addr, int location)
+{
+ int i;
+ int retval = 0;
+ void __iomem *ee_addr = addr + EECtrl;
+ int read_cmd = location | EE_ReadCmd;
+ iowrite32(EE_ChipSelect, ee_addr);
+
+ /* Shift the read command bits out. */
+ for (i = 10; i >= 0; i--) {
+ short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
+ iowrite32(dataval, ee_addr);
+ eeprom_delay(ee_addr);
+ iowrite32(dataval | EE_ShiftClk, ee_addr);
+ eeprom_delay(ee_addr);
+ }
+ iowrite32(EE_ChipSelect, ee_addr);
+ eeprom_delay(ee_addr);
+
+ for (i = 16; i > 0; i--) {
+ iowrite32(EE_ChipSelect | EE_ShiftClk, ee_addr);
+ eeprom_delay(ee_addr);
+ retval = (retval << 1) | ((ioread32(ee_addr) & EE_DataIn) ? 1 : 0);
+ iowrite32(EE_ChipSelect, ee_addr);
+ eeprom_delay(ee_addr);
+ }
+
+ /* Terminate the EEPROM access. */
+ iowrite32(0, ee_addr);
+ return retval;
+}
+
+/* MII transceiver control section.
+ Read and write the MII registers using software-generated serial
+ MDIO protocol. See the MII specifications or DP83840A data sheet
+ for details.
+
+ The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
+ met by back-to-back 33Mhz PCI cycles. */
+#define mdio_delay(mdio_addr) ioread32(mdio_addr)
+
+/* Set iff a MII transceiver on any interface requires mdio preamble.
+ This only set with older transceivers, so the extra
+ code size of a per-interface flag is not worthwhile. */
+static char mii_preamble_required = 1;
+
+#define MDIO_WRITE0 (MDIO_EnbOutput)
+#define MDIO_WRITE1 (MDIO_DataOut | MDIO_EnbOutput)
+
+/* Generate the preamble required for initial synchronization and
+ a few older transceivers. */
+static void mdio_sync(void __iomem *mdio_addr)
+{
+ int bits = 32;
+
+ /* Establish sync by sending at least 32 logic ones. */
+ while (--bits >= 0) {
+ iowrite32(MDIO_WRITE1, mdio_addr);
+ mdio_delay(mdio_addr);
+ iowrite32(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
+ mdio_delay(mdio_addr);
+ }
+}
+
+static int mdio_read(struct net_device *dev, int phy_id, int location)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *mdio_addr = np->base_addr + MIICtrl;
+ int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
+ int i, retval = 0;
+
+ if (mii_preamble_required)
+ mdio_sync(mdio_addr);
+
+ /* Shift the read command bits out. */
+ for (i = 15; i >= 0; i--) {
+ int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
+
+ iowrite32(dataval, mdio_addr);
+ mdio_delay(mdio_addr);
+ iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
+ mdio_delay(mdio_addr);
+ }
+ /* Read the two transition, 16 data, and wire-idle bits. */
+ for (i = 20; i > 0; i--) {
+ iowrite32(MDIO_EnbIn, mdio_addr);
+ mdio_delay(mdio_addr);
+ retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DataIn) ? 1 : 0);
+ iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
+ mdio_delay(mdio_addr);
+ }
+ return (retval>>1) & 0xffff;
+}
+
+static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *mdio_addr = np->base_addr + MIICtrl;
+ int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
+ int i;
+
+ if (location == 4 && phy_id == np->phys[0])
+ np->mii_if.advertising = value;
+
+ if (mii_preamble_required)
+ mdio_sync(mdio_addr);
+
+ /* Shift the command bits out. */
+ for (i = 31; i >= 0; i--) {
+ int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
+
+ iowrite32(dataval, mdio_addr);
+ mdio_delay(mdio_addr);
+ iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
+ mdio_delay(mdio_addr);
+ }
+ /* Clear out extra bits. */
+ for (i = 2; i > 0; i--) {
+ iowrite32(MDIO_EnbIn, mdio_addr);
+ mdio_delay(mdio_addr);
+ iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
+ mdio_delay(mdio_addr);
+ }
+}
+
+
+static int netdev_open(struct net_device *dev)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->base_addr;
+ const int irq = np->pci_dev->irq;
+ int i;
+
+ iowrite32(0x00000001, ioaddr + PCIBusCfg); /* Reset */
+
+ netif_device_detach(dev);
+ i = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
+ if (i)
+ goto out_err;
+
+ if (debug > 1)
+ netdev_dbg(dev, "%s() irq %d\n", __func__, irq);
+
+ i = alloc_ringdesc(dev);
+ if (i)
+ goto out_err;
+
+ spin_lock_irq(&np->lock);
+ netif_device_attach(dev);
+ init_registers(dev);
+ spin_unlock_irq(&np->lock);
+
+ netif_start_queue(dev);
+ if (debug > 2)
+ netdev_dbg(dev, "Done %s()\n", __func__);
+
+ /* Set the timer to check for link beat. */
+ timer_setup(&np->timer, netdev_timer, 0);
+ np->timer.expires = jiffies + 1*HZ;
+ add_timer(&np->timer);
+ return 0;
+out_err:
+ netif_device_attach(dev);
+ return i;
+}
+
+#define MII_DAVICOM_DM9101 0x0181b800
+
+static int update_link(struct net_device *dev)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ int duplex, fasteth, result, mii_reg;
+
+ /* BSMR */
+ mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
+
+ if (mii_reg == 0xffff)
+ return np->csr6;
+ /* reread: the link status bit is sticky */
+ mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
+ if (!(mii_reg & 0x4)) {
+ if (netif_carrier_ok(dev)) {
+ if (debug)
+ dev_info(&dev->dev,
+ "MII #%d reports no link. Disabling watchdog\n",
+ np->phys[0]);
+ netif_carrier_off(dev);
+ }
+ return np->csr6;
+ }
+ if (!netif_carrier_ok(dev)) {
+ if (debug)
+ dev_info(&dev->dev,
+ "MII #%d link is back. Enabling watchdog\n",
+ np->phys[0]);
+ netif_carrier_on(dev);
+ }
+
+ if ((np->mii & ~0xf) == MII_DAVICOM_DM9101) {
+ /* If the link partner doesn't support autonegotiation
+ * the MII detects it's abilities with the "parallel detection".
+ * Some MIIs update the LPA register to the result of the parallel
+ * detection, some don't.
+ * The Davicom PHY [at least 0181b800] doesn't.
+ * Instead bit 9 and 13 of the BMCR are updated to the result
+ * of the negotiation..
+ */
+ mii_reg = mdio_read(dev, np->phys[0], MII_BMCR);
+ duplex = mii_reg & BMCR_FULLDPLX;
+ fasteth = mii_reg & BMCR_SPEED100;
+ } else {
+ int negotiated;
+ mii_reg = mdio_read(dev, np->phys[0], MII_LPA);
+ negotiated = mii_reg & np->mii_if.advertising;
+
+ duplex = (negotiated & LPA_100FULL) || ((negotiated & 0x02C0) == LPA_10FULL);
+ fasteth = negotiated & 0x380;
+ }
+ duplex |= np->mii_if.force_media;
+ /* remove fastether and fullduplex */
+ result = np->csr6 & ~0x20000200;
+ if (duplex)
+ result |= 0x200;
+ if (fasteth)
+ result |= 0x20000000;
+ if (result != np->csr6 && debug)
+ dev_info(&dev->dev,
+ "Setting %dMBit-%s-duplex based on MII#%d\n",
+ fasteth ? 100 : 10, duplex ? "full" : "half",
+ np->phys[0]);
+ return result;
+}
+
+#define RXTX_TIMEOUT 2000
+static inline void update_csr6(struct net_device *dev, int new)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->base_addr;
+ int limit = RXTX_TIMEOUT;
+
+ if (!netif_device_present(dev))
+ new = 0;
+ if (new==np->csr6)
+ return;
+ /* stop both Tx and Rx processes */
+ iowrite32(np->csr6 & ~0x2002, ioaddr + NetworkConfig);
+ /* wait until they have really stopped */
+ for (;;) {
+ int csr5 = ioread32(ioaddr + IntrStatus);
+ int t;
+
+ t = (csr5 >> 17) & 0x07;
+ if (t==0||t==1) {
+ /* rx stopped */
+ t = (csr5 >> 20) & 0x07;
+ if (t==0||t==1)
+ break;
+ }
+
+ limit--;
+ if(!limit) {
+ dev_info(&dev->dev,
+ "couldn't stop rxtx, IntrStatus %xh\n", csr5);
+ break;
+ }
+ udelay(1);
+ }
+ np->csr6 = new;
+ /* and restart them with the new configuration */
+ iowrite32(np->csr6, ioaddr + NetworkConfig);
+ if (new & 0x200)
+ np->mii_if.full_duplex = 1;
+}
+
+static void netdev_timer(struct timer_list *t)
+{
+ struct netdev_private *np = from_timer(np, t, timer);
+ struct net_device *dev = pci_get_drvdata(np->pci_dev);
+ void __iomem *ioaddr = np->base_addr;
+
+ if (debug > 2)
+ netdev_dbg(dev, "Media selection timer tick, status %08x config %08x\n",
+ ioread32(ioaddr + IntrStatus),
+ ioread32(ioaddr + NetworkConfig));
+ spin_lock_irq(&np->lock);
+ update_csr6(dev, update_link(dev));
+ spin_unlock_irq(&np->lock);
+ np->timer.expires = jiffies + 10*HZ;
+ add_timer(&np->timer);
+}
+
+static void init_rxtx_rings(struct net_device *dev)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ int i;
+
+ np->rx_head_desc = &np->rx_ring[0];
+ np->tx_ring = (struct w840_tx_desc*)&np->rx_ring[RX_RING_SIZE];
+
+ /* Initial all Rx descriptors. */
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ np->rx_ring[i].length = np->rx_buf_sz;
+ np->rx_ring[i].status = 0;
+ np->rx_skbuff[i] = NULL;
+ }
+ /* Mark the last entry as wrapping the ring. */
+ np->rx_ring[i-1].length |= DescEndRing;
+
+ /* Fill in the Rx buffers. Handle allocation failure gracefully. */
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz);
+ np->rx_skbuff[i] = skb;
+ if (skb == NULL)
+ break;
+ np->rx_addr[i] = dma_map_single(&np->pci_dev->dev, skb->data,
+ np->rx_buf_sz,
+ DMA_FROM_DEVICE);
+
+ np->rx_ring[i].buffer1 = np->rx_addr[i];
+ np->rx_ring[i].status = DescOwned;
+ }
+
+ np->cur_rx = 0;
+ np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
+
+ /* Initialize the Tx descriptors */
+ for (i = 0; i < TX_RING_SIZE; i++) {
+ np->tx_skbuff[i] = NULL;
+ np->tx_ring[i].status = 0;
+ }
+ np->tx_full = 0;
+ np->tx_q_bytes = np->dirty_tx = np->cur_tx = 0;
+
+ iowrite32(np->ring_dma_addr, np->base_addr + RxRingPtr);
+ iowrite32(np->ring_dma_addr+sizeof(struct w840_rx_desc)*RX_RING_SIZE,
+ np->base_addr + TxRingPtr);
+
+}
+
+static void free_rxtx_rings(struct netdev_private* np)
+{
+ int i;
+ /* Free all the skbuffs in the Rx queue. */
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ np->rx_ring[i].status = 0;
+ if (np->rx_skbuff[i]) {
+ dma_unmap_single(&np->pci_dev->dev, np->rx_addr[i],
+ np->rx_skbuff[i]->len,
+ DMA_FROM_DEVICE);
+ dev_kfree_skb(np->rx_skbuff[i]);
+ }
+ np->rx_skbuff[i] = NULL;
+ }
+ for (i = 0; i < TX_RING_SIZE; i++) {
+ if (np->tx_skbuff[i]) {
+ dma_unmap_single(&np->pci_dev->dev, np->tx_addr[i],
+ np->tx_skbuff[i]->len, DMA_TO_DEVICE);
+ dev_kfree_skb(np->tx_skbuff[i]);
+ }
+ np->tx_skbuff[i] = NULL;
+ }
+}
+
+static void init_registers(struct net_device *dev)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->base_addr;
+ int i;
+
+ for (i = 0; i < 6; i++)
+ iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
+
+ /* Initialize other registers. */
+#ifdef __BIG_ENDIAN
+ i = (1<<20); /* Big-endian descriptors */
+#else
+ i = 0;
+#endif
+ i |= (0x04<<2); /* skip length 4 u32 */
+ i |= 0x02; /* give Rx priority */
+
+ /* Configure the PCI bus bursts and FIFO thresholds.
+ 486: Set 8 longword cache alignment, 8 longword burst.
+ 586: Set 16 longword cache alignment, no burst limit.
+ Cache alignment bits 15:14 Burst length 13:8
+ 0000 <not allowed> 0000 align to cache 0800 8 longwords
+ 4000 8 longwords 0100 1 longword 1000 16 longwords
+ 8000 16 longwords 0200 2 longwords 2000 32 longwords
+ C000 32 longwords 0400 4 longwords */
+
+#if defined (__i386__) && !defined(MODULE) && !defined(CONFIG_UML)
+ /* When not a module we can work around broken '486 PCI boards. */
+ if (boot_cpu_data.x86 <= 4) {
+ i |= 0x4800;
+ dev_info(&dev->dev,
+ "This is a 386/486 PCI system, setting cache alignment to 8 longwords\n");
+ } else {
+ i |= 0xE000;
+ }
+#elif defined(__powerpc__) || defined(__i386__) || defined(__alpha__) || defined(__ia64__) || defined(__x86_64__)
+ i |= 0xE000;
+#elif defined(CONFIG_SPARC) || defined (CONFIG_PARISC) || defined(CONFIG_ARM)
+ i |= 0x4800;
+#else
+ dev_warn(&dev->dev, "unknown CPU architecture, using default csr0 setting\n");
+ i |= 0x4800;
+#endif
+ iowrite32(i, ioaddr + PCIBusCfg);
+
+ np->csr6 = 0;
+ /* 128 byte Tx threshold;
+ Transmit on; Receive on; */
+ update_csr6(dev, 0x00022002 | update_link(dev) | __set_rx_mode(dev));
+
+ /* Clear and Enable interrupts by setting the interrupt mask. */
+ iowrite32(0x1A0F5, ioaddr + IntrStatus);
+ iowrite32(0x1A0F5, ioaddr + IntrEnable);
+
+ iowrite32(0, ioaddr + RxStartDemand);
+}
+
+static void tx_timeout(struct net_device *dev, unsigned int txqueue)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->base_addr;
+ const int irq = np->pci_dev->irq;
+
+ dev_warn(&dev->dev, "Transmit timed out, status %08x, resetting...\n",
+ ioread32(ioaddr + IntrStatus));
+
+ {
+ int i;
+ printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
+ for (i = 0; i < RX_RING_SIZE; i++)
+ printk(KERN_CONT " %08x", (unsigned int)np->rx_ring[i].status);
+ printk(KERN_CONT "\n");
+ printk(KERN_DEBUG " Tx ring %p: ", np->tx_ring);
+ for (i = 0; i < TX_RING_SIZE; i++)
+ printk(KERN_CONT " %08x", np->tx_ring[i].status);
+ printk(KERN_CONT "\n");
+ }
+ printk(KERN_DEBUG "Tx cur %d Tx dirty %d Tx Full %d, q bytes %d\n",
+ np->cur_tx, np->dirty_tx, np->tx_full, np->tx_q_bytes);
+ printk(KERN_DEBUG "Tx Descriptor addr %xh\n", ioread32(ioaddr+0x4C));
+
+ disable_irq(irq);
+ spin_lock_irq(&np->lock);
+ /*
+ * Under high load dirty_tx and the internal tx descriptor pointer
+ * come out of sync, thus perform a software reset and reinitialize
+ * everything.
+ */
+
+ iowrite32(1, np->base_addr+PCIBusCfg);
+ udelay(1);
+
+ free_rxtx_rings(np);
+ init_rxtx_rings(dev);
+ init_registers(dev);
+ spin_unlock_irq(&np->lock);
+ enable_irq(irq);
+
+ netif_wake_queue(dev);
+ netif_trans_update(dev); /* prevent tx timeout */
+ np->stats.tx_errors++;
+}
+
+/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
+static int alloc_ringdesc(struct net_device *dev)
+{
+ struct netdev_private *np = netdev_priv(dev);
+
+ np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
+
+ np->rx_ring = dma_alloc_coherent(&np->pci_dev->dev,
+ sizeof(struct w840_rx_desc) * RX_RING_SIZE +
+ sizeof(struct w840_tx_desc) * TX_RING_SIZE,
+ &np->ring_dma_addr, GFP_KERNEL);
+ if(!np->rx_ring)
+ return -ENOMEM;
+ init_rxtx_rings(dev);
+ return 0;
+}
+
+static void free_ringdesc(struct netdev_private *np)
+{
+ dma_free_coherent(&np->pci_dev->dev,
+ sizeof(struct w840_rx_desc) * RX_RING_SIZE +
+ sizeof(struct w840_tx_desc) * TX_RING_SIZE,
+ np->rx_ring, np->ring_dma_addr);
+
+}
+
+static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ unsigned entry;
+
+ /* Caution: the write order is important here, set the field
+ with the "ownership" bits last. */
+
+ /* Calculate the next Tx descriptor entry. */
+ entry = np->cur_tx % TX_RING_SIZE;
+
+ np->tx_addr[entry] = dma_map_single(&np->pci_dev->dev, skb->data,
+ skb->len, DMA_TO_DEVICE);
+ np->tx_skbuff[entry] = skb;
+
+ np->tx_ring[entry].buffer1 = np->tx_addr[entry];
+ if (skb->len < TX_BUFLIMIT) {
+ np->tx_ring[entry].length = DescWholePkt | skb->len;
+ } else {
+ int len = skb->len - TX_BUFLIMIT;
+
+ np->tx_ring[entry].buffer2 = np->tx_addr[entry]+TX_BUFLIMIT;
+ np->tx_ring[entry].length = DescWholePkt | (len << 11) | TX_BUFLIMIT;
+ }
+ if(entry == TX_RING_SIZE-1)
+ np->tx_ring[entry].length |= DescEndRing;
+
+ /* Now acquire the irq spinlock.
+ * The difficult race is the ordering between
+ * increasing np->cur_tx and setting DescOwned:
+ * - if np->cur_tx is increased first the interrupt
+ * handler could consider the packet as transmitted
+ * since DescOwned is cleared.
+ * - If DescOwned is set first the NIC could report the
+ * packet as sent, but the interrupt handler would ignore it
+ * since the np->cur_tx was not yet increased.
+ */
+ spin_lock_irq(&np->lock);
+ np->cur_tx++;
+
+ wmb(); /* flush length, buffer1, buffer2 */
+ np->tx_ring[entry].status = DescOwned;
+ wmb(); /* flush status and kick the hardware */
+ iowrite32(0, np->base_addr + TxStartDemand);
+ np->tx_q_bytes += skb->len;
+ /* Work around horrible bug in the chip by marking the queue as full
+ when we do not have FIFO room for a maximum sized packet. */
+ if (np->cur_tx - np->dirty_tx > TX_QUEUE_LEN ||
+ ((np->drv_flags & HasBrokenTx) && np->tx_q_bytes > TX_BUG_FIFO_LIMIT)) {
+ netif_stop_queue(dev);
+ wmb();
+ np->tx_full = 1;
+ }
+ spin_unlock_irq(&np->lock);
+
+ if (debug > 4) {
+ netdev_dbg(dev, "Transmit frame #%d queued in slot %d\n",
+ np->cur_tx, entry);
+ }
+ return NETDEV_TX_OK;
+}
+
+static void netdev_tx_done(struct net_device *dev)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
+ int entry = np->dirty_tx % TX_RING_SIZE;
+ int tx_status = np->tx_ring[entry].status;
+
+ if (tx_status < 0)
+ break;
+ if (tx_status & 0x8000) { /* There was an error, log it. */
+#ifndef final_version
+ if (debug > 1)
+ netdev_dbg(dev, "Transmit error, Tx status %08x\n",
+ tx_status);
+#endif
+ np->stats.tx_errors++;
+ if (tx_status & 0x0104) np->stats.tx_aborted_errors++;
+ if (tx_status & 0x0C80) np->stats.tx_carrier_errors++;
+ if (tx_status & 0x0200) np->stats.tx_window_errors++;
+ if (tx_status & 0x0002) np->stats.tx_fifo_errors++;
+ if ((tx_status & 0x0080) && np->mii_if.full_duplex == 0)
+ np->stats.tx_heartbeat_errors++;
+ } else {
+#ifndef final_version
+ if (debug > 3)
+ netdev_dbg(dev, "Transmit slot %d ok, Tx status %08x\n",
+ entry, tx_status);
+#endif
+ np->stats.tx_bytes += np->tx_skbuff[entry]->len;
+ np->stats.collisions += (tx_status >> 3) & 15;
+ np->stats.tx_packets++;
+ }
+ /* Free the original skb. */
+ dma_unmap_single(&np->pci_dev->dev, np->tx_addr[entry],
+ np->tx_skbuff[entry]->len, DMA_TO_DEVICE);
+ np->tx_q_bytes -= np->tx_skbuff[entry]->len;
+ dev_kfree_skb_irq(np->tx_skbuff[entry]);
+ np->tx_skbuff[entry] = NULL;
+ }
+ if (np->tx_full &&
+ np->cur_tx - np->dirty_tx < TX_QUEUE_LEN_RESTART &&
+ np->tx_q_bytes < TX_BUG_FIFO_LIMIT) {
+ /* The ring is no longer full, clear tbusy. */
+ np->tx_full = 0;
+ wmb();
+ netif_wake_queue(dev);
+ }
+}
+
+/* The interrupt handler does all of the Rx thread work and cleans up
+ after the Tx thread. */
+static irqreturn_t intr_handler(int irq, void *dev_instance)
+{
+ struct net_device *dev = (struct net_device *)dev_instance;
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->base_addr;
+ int work_limit = max_interrupt_work;
+ int handled = 0;
+
+ if (!netif_device_present(dev))
+ return IRQ_NONE;
+ do {
+ u32 intr_status = ioread32(ioaddr + IntrStatus);
+
+ /* Acknowledge all of the current interrupt sources ASAP. */
+ iowrite32(intr_status & 0x001ffff, ioaddr + IntrStatus);
+
+ if (debug > 4)
+ netdev_dbg(dev, "Interrupt, status %04x\n", intr_status);
+
+ if ((intr_status & (NormalIntr|AbnormalIntr)) == 0)
+ break;
+
+ handled = 1;
+
+ if (intr_status & (RxIntr | RxNoBuf))
+ netdev_rx(dev);
+ if (intr_status & RxNoBuf)
+ iowrite32(0, ioaddr + RxStartDemand);
+
+ if (intr_status & (TxNoBuf | TxIntr) &&
+ np->cur_tx != np->dirty_tx) {
+ spin_lock(&np->lock);
+ netdev_tx_done(dev);
+ spin_unlock(&np->lock);
+ }
+
+ /* Abnormal error summary/uncommon events handlers. */
+ if (intr_status & (AbnormalIntr | TxFIFOUnderflow | SystemError |
+ TimerInt | TxDied))
+ netdev_error(dev, intr_status);
+
+ if (--work_limit < 0) {
+ dev_warn(&dev->dev,
+ "Too much work at interrupt, status=0x%04x\n",
+ intr_status);
+ /* Set the timer to re-enable the other interrupts after
+ 10*82usec ticks. */
+ spin_lock(&np->lock);
+ if (netif_device_present(dev)) {
+ iowrite32(AbnormalIntr | TimerInt, ioaddr + IntrEnable);
+ iowrite32(10, ioaddr + GPTimer);
+ }
+ spin_unlock(&np->lock);
+ break;
+ }
+ } while (1);
+
+ if (debug > 3)
+ netdev_dbg(dev, "exiting interrupt, status=%#4.4x\n",
+ ioread32(ioaddr + IntrStatus));
+ return IRQ_RETVAL(handled);
+}
+
+/* This routine is logically part of the interrupt handler, but separated
+ for clarity and better register allocation. */
+static int netdev_rx(struct net_device *dev)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ int entry = np->cur_rx % RX_RING_SIZE;
+ int work_limit = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
+
+ if (debug > 4) {
+ netdev_dbg(dev, " In netdev_rx(), entry %d status %04x\n",
+ entry, np->rx_ring[entry].status);
+ }
+
+ /* If EOP is set on the next entry, it's a new packet. Send it up. */
+ while (--work_limit >= 0) {
+ struct w840_rx_desc *desc = np->rx_head_desc;
+ s32 status = desc->status;
+
+ if (debug > 4)
+ netdev_dbg(dev, " netdev_rx() status was %08x\n",
+ status);
+ if (status < 0)
+ break;
+ if ((status & 0x38008300) != 0x0300) {
+ if ((status & 0x38000300) != 0x0300) {
+ /* Ingore earlier buffers. */
+ if ((status & 0xffff) != 0x7fff) {
+ dev_warn(&dev->dev,
+ "Oversized Ethernet frame spanned multiple buffers, entry %#x status %04x!\n",
+ np->cur_rx, status);
+ np->stats.rx_length_errors++;
+ }
+ } else if (status & 0x8000) {
+ /* There was a fatal error. */
+ if (debug > 2)
+ netdev_dbg(dev, "Receive error, Rx status %08x\n",
+ status);
+ np->stats.rx_errors++; /* end of a packet.*/
+ if (status & 0x0890) np->stats.rx_length_errors++;
+ if (status & 0x004C) np->stats.rx_frame_errors++;
+ if (status & 0x0002) np->stats.rx_crc_errors++;
+ }
+ } else {
+ struct sk_buff *skb;
+ /* Omit the four octet CRC from the length. */
+ int pkt_len = ((status >> 16) & 0x7ff) - 4;
+
+#ifndef final_version
+ if (debug > 4)
+ netdev_dbg(dev, " netdev_rx() normal Rx pkt length %d status %x\n",
+ pkt_len, status);
+#endif
+ /* Check if the packet is long enough to accept without copying
+ to a minimally-sized skbuff. */
+ if (pkt_len < rx_copybreak &&
+ (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
+ skb_reserve(skb, 2); /* 16 byte align the IP header */
+ dma_sync_single_for_cpu(&np->pci_dev->dev,
+ np->rx_addr[entry],
+ np->rx_skbuff[entry]->len,
+ DMA_FROM_DEVICE);
+ skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len);
+ skb_put(skb, pkt_len);
+ dma_sync_single_for_device(&np->pci_dev->dev,
+ np->rx_addr[entry],
+ np->rx_skbuff[entry]->len,
+ DMA_FROM_DEVICE);
+ } else {
+ dma_unmap_single(&np->pci_dev->dev,
+ np->rx_addr[entry],
+ np->rx_skbuff[entry]->len,
+ DMA_FROM_DEVICE);
+ skb_put(skb = np->rx_skbuff[entry], pkt_len);
+ np->rx_skbuff[entry] = NULL;
+ }
+#ifndef final_version /* Remove after testing. */
+ /* You will want this info for the initial debug. */
+ if (debug > 5)
+ netdev_dbg(dev, " Rx data %pM %pM %02x%02x %pI4\n",
+ &skb->data[0], &skb->data[6],
+ skb->data[12], skb->data[13],
+ &skb->data[14]);
+#endif
+ skb->protocol = eth_type_trans(skb, dev);
+ netif_rx(skb);
+ np->stats.rx_packets++;
+ np->stats.rx_bytes += pkt_len;
+ }
+ entry = (++np->cur_rx) % RX_RING_SIZE;
+ np->rx_head_desc = &np->rx_ring[entry];
+ }
+
+ /* Refill the Rx ring buffers. */
+ for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
+ struct sk_buff *skb;
+ entry = np->dirty_rx % RX_RING_SIZE;
+ if (np->rx_skbuff[entry] == NULL) {
+ skb = netdev_alloc_skb(dev, np->rx_buf_sz);
+ np->rx_skbuff[entry] = skb;
+ if (skb == NULL)
+ break; /* Better luck next round. */
+ np->rx_addr[entry] = dma_map_single(&np->pci_dev->dev,
+ skb->data,
+ np->rx_buf_sz,
+ DMA_FROM_DEVICE);
+ np->rx_ring[entry].buffer1 = np->rx_addr[entry];
+ }
+ wmb();
+ np->rx_ring[entry].status = DescOwned;
+ }
+
+ return 0;
+}
+
+static void netdev_error(struct net_device *dev, int intr_status)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->base_addr;
+
+ if (debug > 2)
+ netdev_dbg(dev, "Abnormal event, %08x\n", intr_status);
+ if (intr_status == 0xffffffff)
+ return;
+ spin_lock(&np->lock);
+ if (intr_status & TxFIFOUnderflow) {
+ int new;
+ /* Bump up the Tx threshold */
+#if 0
+ /* This causes lots of dropped packets,
+ * and under high load even tx_timeouts
+ */
+ new = np->csr6 + 0x4000;
+#else
+ new = (np->csr6 >> 14)&0x7f;
+ if (new < 64)
+ new *= 2;
+ else
+ new = 127; /* load full packet before starting */
+ new = (np->csr6 & ~(0x7F << 14)) | (new<<14);
+#endif
+ netdev_dbg(dev, "Tx underflow, new csr6 %08x\n", new);
+ update_csr6(dev, new);
+ }
+ if (intr_status & RxDied) { /* Missed a Rx frame. */
+ np->stats.rx_errors++;
+ }
+ if (intr_status & TimerInt) {
+ /* Re-enable other interrupts. */
+ if (netif_device_present(dev))
+ iowrite32(0x1A0F5, ioaddr + IntrEnable);
+ }
+ np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
+ iowrite32(0, ioaddr + RxStartDemand);
+ spin_unlock(&np->lock);
+}
+
+static struct net_device_stats *get_stats(struct net_device *dev)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->base_addr;
+
+ /* The chip only need report frame silently dropped. */
+ spin_lock_irq(&np->lock);
+ if (netif_running(dev) && netif_device_present(dev))
+ np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
+ spin_unlock_irq(&np->lock);
+
+ return &np->stats;
+}
+
+
+static u32 __set_rx_mode(struct net_device *dev)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->base_addr;
+ u32 mc_filter[2]; /* Multicast hash filter */
+ u32 rx_mode;
+
+ if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
+ memset(mc_filter, 0xff, sizeof(mc_filter));
+ rx_mode = RxAcceptBroadcast | AcceptMulticast | RxAcceptAllPhys
+ | AcceptMyPhys;
+ } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
+ (dev->flags & IFF_ALLMULTI)) {
+ /* Too many to match, or accept all multicasts. */
+ memset(mc_filter, 0xff, sizeof(mc_filter));
+ rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
+ } else {
+ struct netdev_hw_addr *ha;
+
+ memset(mc_filter, 0, sizeof(mc_filter));
+ netdev_for_each_mc_addr(ha, dev) {
+ int filbit;
+
+ filbit = (ether_crc(ETH_ALEN, ha->addr) >> 26) ^ 0x3F;
+ filbit &= 0x3f;
+ mc_filter[filbit >> 5] |= 1 << (filbit & 31);
+ }
+ rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
+ }
+ iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
+ iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
+ return rx_mode;
+}
+
+static void set_rx_mode(struct net_device *dev)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ u32 rx_mode = __set_rx_mode(dev);
+ spin_lock_irq(&np->lock);
+ update_csr6(dev, (np->csr6 & ~0x00F8) | rx_mode);
+ spin_unlock_irq(&np->lock);
+}
+
+static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
+{
+ struct netdev_private *np = netdev_priv(dev);
+
+ strscpy(info->driver, DRV_NAME, sizeof(info->driver));
+ strscpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
+}
+
+static int netdev_get_link_ksettings(struct net_device *dev,
+ struct ethtool_link_ksettings *cmd)
+{
+ struct netdev_private *np = netdev_priv(dev);
+
+ spin_lock_irq(&np->lock);
+ mii_ethtool_get_link_ksettings(&np->mii_if, cmd);
+ spin_unlock_irq(&np->lock);
+
+ return 0;
+}
+
+static int netdev_set_link_ksettings(struct net_device *dev,
+ const struct ethtool_link_ksettings *cmd)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ int rc;
+
+ spin_lock_irq(&np->lock);
+ rc = mii_ethtool_set_link_ksettings(&np->mii_if, cmd);
+ spin_unlock_irq(&np->lock);
+
+ return rc;
+}
+
+static int netdev_nway_reset(struct net_device *dev)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ return mii_nway_restart(&np->mii_if);
+}
+
+static u32 netdev_get_link(struct net_device *dev)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ return mii_link_ok(&np->mii_if);
+}
+
+static u32 netdev_get_msglevel(struct net_device *dev)
+{
+ return debug;
+}
+
+static void netdev_set_msglevel(struct net_device *dev, u32 value)
+{
+ debug = value;
+}
+
+static const struct ethtool_ops netdev_ethtool_ops = {
+ .get_drvinfo = netdev_get_drvinfo,
+ .nway_reset = netdev_nway_reset,
+ .get_link = netdev_get_link,
+ .get_msglevel = netdev_get_msglevel,
+ .set_msglevel = netdev_set_msglevel,
+ .get_link_ksettings = netdev_get_link_ksettings,
+ .set_link_ksettings = netdev_set_link_ksettings,
+};
+
+static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+ struct mii_ioctl_data *data = if_mii(rq);
+ struct netdev_private *np = netdev_priv(dev);
+
+ switch(cmd) {
+ case SIOCGMIIPHY: /* Get address of MII PHY in use. */
+ data->phy_id = ((struct netdev_private *)netdev_priv(dev))->phys[0] & 0x1f;
+ fallthrough;
+
+ case SIOCGMIIREG: /* Read MII PHY register. */
+ spin_lock_irq(&np->lock);
+ data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
+ spin_unlock_irq(&np->lock);
+ return 0;
+
+ case SIOCSMIIREG: /* Write MII PHY register. */
+ spin_lock_irq(&np->lock);
+ mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
+ spin_unlock_irq(&np->lock);
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int netdev_close(struct net_device *dev)
+{
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->base_addr;
+
+ netif_stop_queue(dev);
+
+ if (debug > 1) {
+ netdev_dbg(dev, "Shutting down ethercard, status was %08x Config %08x\n",
+ ioread32(ioaddr + IntrStatus),
+ ioread32(ioaddr + NetworkConfig));
+ netdev_dbg(dev, "Queue pointers were Tx %d / %d, Rx %d / %d\n",
+ np->cur_tx, np->dirty_tx,
+ np->cur_rx, np->dirty_rx);
+ }
+
+ /* Stop the chip's Tx and Rx processes. */
+ spin_lock_irq(&np->lock);
+ netif_device_detach(dev);
+ update_csr6(dev, 0);
+ iowrite32(0x0000, ioaddr + IntrEnable);
+ spin_unlock_irq(&np->lock);
+
+ free_irq(np->pci_dev->irq, dev);
+ wmb();
+ netif_device_attach(dev);
+
+ if (ioread32(ioaddr + NetworkConfig) != 0xffffffff)
+ np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
+
+#ifdef __i386__
+ if (debug > 2) {
+ int i;
+
+ printk(KERN_DEBUG" Tx ring at %p:\n", np->tx_ring);
+ for (i = 0; i < TX_RING_SIZE; i++)
+ printk(KERN_DEBUG " #%d desc. %04x %04x %08x\n",
+ i, np->tx_ring[i].length,
+ np->tx_ring[i].status, np->tx_ring[i].buffer1);
+ printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ printk(KERN_DEBUG " #%d desc. %04x %04x %08x\n",
+ i, np->rx_ring[i].length,
+ np->rx_ring[i].status, np->rx_ring[i].buffer1);
+ }
+ }
+#endif /* __i386__ debugging only */
+
+ del_timer_sync(&np->timer);
+
+ free_rxtx_rings(np);
+ free_ringdesc(np);
+
+ return 0;
+}
+
+static void w840_remove1(struct pci_dev *pdev)
+{
+ struct net_device *dev = pci_get_drvdata(pdev);
+
+ if (dev) {
+ struct netdev_private *np = netdev_priv(dev);
+ unregister_netdev(dev);
+ pci_iounmap(pdev, np->base_addr);
+ free_netdev(dev);
+ }
+}
+
+/*
+ * suspend/resume synchronization:
+ * - open, close, do_ioctl:
+ * rtnl_lock, & netif_device_detach after the rtnl_unlock.
+ * - get_stats:
+ * spin_lock_irq(np->lock), doesn't touch hw if not present
+ * - start_xmit:
+ * synchronize_irq + netif_tx_disable;
+ * - tx_timeout:
+ * netif_device_detach + netif_tx_disable;
+ * - set_multicast_list
+ * netif_device_detach + netif_tx_disable;
+ * - interrupt handler
+ * doesn't touch hw if not present, synchronize_irq waits for
+ * running instances of the interrupt handler.
+ *
+ * Disabling hw requires clearing csr6 & IntrEnable.
+ * update_csr6 & all function that write IntrEnable check netif_device_present
+ * before settings any bits.
+ *
+ * Detach must occur under spin_unlock_irq(), interrupts from a detached
+ * device would cause an irq storm.
+ */
+static int __maybe_unused w840_suspend(struct device *dev_d)
+{
+ struct net_device *dev = dev_get_drvdata(dev_d);
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->base_addr;
+
+ rtnl_lock();
+ if (netif_running (dev)) {
+ del_timer_sync(&np->timer);
+
+ spin_lock_irq(&np->lock);
+ netif_device_detach(dev);
+ update_csr6(dev, 0);
+ iowrite32(0, ioaddr + IntrEnable);
+ spin_unlock_irq(&np->lock);
+
+ synchronize_irq(np->pci_dev->irq);
+ netif_tx_disable(dev);
+
+ np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
+
+ /* no more hardware accesses behind this line. */
+
+ BUG_ON(np->csr6 || ioread32(ioaddr + IntrEnable));
+
+ /* pci_power_off(pdev, -1); */
+
+ free_rxtx_rings(np);
+ } else {
+ netif_device_detach(dev);
+ }
+ rtnl_unlock();
+ return 0;
+}
+
+static int __maybe_unused w840_resume(struct device *dev_d)
+{
+ struct net_device *dev = dev_get_drvdata(dev_d);
+ struct netdev_private *np = netdev_priv(dev);
+
+ rtnl_lock();
+ if (netif_device_present(dev))
+ goto out; /* device not suspended */
+ if (netif_running(dev)) {
+ spin_lock_irq(&np->lock);
+ iowrite32(1, np->base_addr+PCIBusCfg);
+ ioread32(np->base_addr+PCIBusCfg);
+ udelay(1);
+ netif_device_attach(dev);
+ init_rxtx_rings(dev);
+ init_registers(dev);
+ spin_unlock_irq(&np->lock);
+
+ netif_wake_queue(dev);
+
+ mod_timer(&np->timer, jiffies + 1*HZ);
+ } else {
+ netif_device_attach(dev);
+ }
+out:
+ rtnl_unlock();
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(w840_pm_ops, w840_suspend, w840_resume);
+
+static struct pci_driver w840_driver = {
+ .name = DRV_NAME,
+ .id_table = w840_pci_tbl,
+ .probe = w840_probe1,
+ .remove = w840_remove1,
+ .driver.pm = &w840_pm_ops,
+};
+
+module_pci_driver(w840_driver);
diff --git a/drivers/net/ethernet/dec/tulip/xircom_cb.c b/drivers/net/ethernet/dec/tulip/xircom_cb.c
new file mode 100644
index 000000000..8759f9f76
--- /dev/null
+++ b/drivers/net/ethernet/dec/tulip/xircom_cb.c
@@ -0,0 +1,1172 @@
+/*
+ * xircom_cb: A driver for the (tulip-like) Xircom Cardbus ethernet cards
+ *
+ * This software is (C) by the respective authors, and licensed under the GPL
+ * License.
+ *
+ * Written by Arjan van de Ven for Red Hat, Inc.
+ * Based on work by Jeff Garzik, Doug Ledford and Donald Becker
+ *
+ * This software may be used and distributed according to the terms
+ * of the GNU General Public License, incorporated herein by reference.
+ *
+ *
+ * $Id: xircom_cb.c,v 1.33 2001/03/19 14:02:07 arjanv Exp $
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/delay.h>
+#include <linux/bitops.h>
+
+#include <linux/uaccess.h>
+#include <asm/io.h>
+#ifdef CONFIG_NET_POLL_CONTROLLER
+#include <asm/irq.h>
+#endif
+
+MODULE_DESCRIPTION("Xircom Cardbus ethernet driver");
+MODULE_AUTHOR("Arjan van de Ven <arjanv@redhat.com>");
+MODULE_LICENSE("GPL");
+
+#define xw32(reg, val) iowrite32(val, ioaddr + (reg))
+#define xr32(reg) ioread32(ioaddr + (reg))
+#define xr8(reg) ioread8(ioaddr + (reg))
+
+/* IO registers on the card, offsets */
+#define CSR0 0x00
+#define CSR1 0x08
+#define CSR2 0x10
+#define CSR3 0x18
+#define CSR4 0x20
+#define CSR5 0x28
+#define CSR6 0x30
+#define CSR7 0x38
+#define CSR8 0x40
+#define CSR9 0x48
+#define CSR10 0x50
+#define CSR11 0x58
+#define CSR12 0x60
+#define CSR13 0x68
+#define CSR14 0x70
+#define CSR15 0x78
+#define CSR16 0x80
+
+/* PCI registers */
+#define PCI_POWERMGMT 0x40
+
+/* Offsets of the buffers within the descriptor pages, in bytes */
+
+#define NUMDESCRIPTORS 4
+
+static int bufferoffsets[NUMDESCRIPTORS] = {128,2048,4096,6144};
+
+
+struct xircom_private {
+ /* Send and receive buffers, kernel-addressable and dma addressable forms */
+
+ __le32 *rx_buffer;
+ __le32 *tx_buffer;
+
+ dma_addr_t rx_dma_handle;
+ dma_addr_t tx_dma_handle;
+
+ struct sk_buff *tx_skb[4];
+
+ void __iomem *ioaddr;
+ int open;
+
+ /* transmit_used is the rotating counter that indicates which transmit
+ descriptor has to be used next */
+ int transmit_used;
+
+ /* Spinlock to serialize register operations.
+ It must be helt while manipulating the following registers:
+ CSR0, CSR6, CSR7, CSR9, CSR10, CSR15
+ */
+ spinlock_t lock;
+
+ struct pci_dev *pdev;
+ struct net_device *dev;
+};
+
+
+/* Function prototypes */
+static int xircom_probe(struct pci_dev *pdev, const struct pci_device_id *id);
+static void xircom_remove(struct pci_dev *pdev);
+static irqreturn_t xircom_interrupt(int irq, void *dev_instance);
+static netdev_tx_t xircom_start_xmit(struct sk_buff *skb,
+ struct net_device *dev);
+static int xircom_open(struct net_device *dev);
+static int xircom_close(struct net_device *dev);
+static void xircom_up(struct xircom_private *card);
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void xircom_poll_controller(struct net_device *dev);
+#endif
+
+static void investigate_read_descriptor(struct net_device *dev,struct xircom_private *card, int descnr, unsigned int bufferoffset);
+static void investigate_write_descriptor(struct net_device *dev, struct xircom_private *card, int descnr, unsigned int bufferoffset);
+static void read_mac_address(struct xircom_private *card);
+static void transceiver_voodoo(struct xircom_private *card);
+static void initialize_card(struct xircom_private *card);
+static void trigger_transmit(struct xircom_private *card);
+static void trigger_receive(struct xircom_private *card);
+static void setup_descriptors(struct xircom_private *card);
+static void remove_descriptors(struct xircom_private *card);
+static int link_status_changed(struct xircom_private *card);
+static void activate_receiver(struct xircom_private *card);
+static void deactivate_receiver(struct xircom_private *card);
+static void activate_transmitter(struct xircom_private *card);
+static void deactivate_transmitter(struct xircom_private *card);
+static void enable_transmit_interrupt(struct xircom_private *card);
+static void enable_receive_interrupt(struct xircom_private *card);
+static void enable_link_interrupt(struct xircom_private *card);
+static void disable_all_interrupts(struct xircom_private *card);
+static int link_status(struct xircom_private *card);
+
+
+
+static const struct pci_device_id xircom_pci_table[] = {
+ { PCI_VDEVICE(XIRCOM, 0x0003), },
+ {0,},
+};
+MODULE_DEVICE_TABLE(pci, xircom_pci_table);
+
+static struct pci_driver xircom_ops = {
+ .name = "xircom_cb",
+ .id_table = xircom_pci_table,
+ .probe = xircom_probe,
+ .remove = xircom_remove,
+};
+
+
+#if defined DEBUG && DEBUG > 1
+static void print_binary(unsigned int number)
+{
+ int i,i2;
+ char buffer[64];
+ memset(buffer,0,64);
+ i2=0;
+ for (i=31;i>=0;i--) {
+ if (number & (1<<i))
+ buffer[i2++]='1';
+ else
+ buffer[i2++]='0';
+ if ((i&3)==0)
+ buffer[i2++]=' ';
+ }
+ pr_debug("%s\n",buffer);
+}
+#endif
+
+static const struct net_device_ops netdev_ops = {
+ .ndo_open = xircom_open,
+ .ndo_stop = xircom_close,
+ .ndo_start_xmit = xircom_start_xmit,
+ .ndo_set_mac_address = eth_mac_addr,
+ .ndo_validate_addr = eth_validate_addr,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+ .ndo_poll_controller = xircom_poll_controller,
+#endif
+};
+
+/* xircom_probe is the code that gets called on device insertion.
+ it sets up the hardware and registers the device to the networklayer.
+
+ TODO: Send 1 or 2 "dummy" packets here as the card seems to discard the
+ first two packets that get send, and pump hates that.
+
+ */
+static int xircom_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct device *d = &pdev->dev;
+ struct net_device *dev = NULL;
+ struct xircom_private *private;
+ unsigned long flags;
+ unsigned short tmp16;
+ int rc;
+
+ /* First do the PCI initialisation */
+
+ rc = pci_enable_device(pdev);
+ if (rc < 0)
+ goto out;
+
+ /* disable all powermanagement */
+ pci_write_config_dword(pdev, PCI_POWERMGMT, 0x0000);
+
+ pci_set_master(pdev); /* Why isn't this done by pci_enable_device ?*/
+
+ /* clear PCI status, if any */
+ pci_read_config_word (pdev,PCI_STATUS, &tmp16);
+ pci_write_config_word (pdev, PCI_STATUS,tmp16);
+
+ rc = pci_request_regions(pdev, "xircom_cb");
+ if (rc < 0) {
+ pr_err("%s: failed to allocate io-region\n", __func__);
+ goto err_disable;
+ }
+
+ rc = -ENOMEM;
+ /*
+ Before changing the hardware, allocate the memory.
+ This way, we can fail gracefully if not enough memory
+ is available.
+ */
+ dev = alloc_etherdev(sizeof(struct xircom_private));
+ if (!dev)
+ goto err_release;
+
+ private = netdev_priv(dev);
+
+ /* Allocate the send/receive buffers */
+ private->rx_buffer = dma_alloc_coherent(d, 8192,
+ &private->rx_dma_handle,
+ GFP_KERNEL);
+ if (private->rx_buffer == NULL)
+ goto rx_buf_fail;
+
+ private->tx_buffer = dma_alloc_coherent(d, 8192,
+ &private->tx_dma_handle,
+ GFP_KERNEL);
+ if (private->tx_buffer == NULL)
+ goto tx_buf_fail;
+
+ SET_NETDEV_DEV(dev, &pdev->dev);
+
+
+ private->dev = dev;
+ private->pdev = pdev;
+
+ /* IO range. */
+ private->ioaddr = pci_iomap(pdev, 0, 0);
+ if (!private->ioaddr)
+ goto reg_fail;
+
+ spin_lock_init(&private->lock);
+
+ initialize_card(private);
+ read_mac_address(private);
+ setup_descriptors(private);
+
+ dev->netdev_ops = &netdev_ops;
+ pci_set_drvdata(pdev, dev);
+
+ rc = register_netdev(dev);
+ if (rc < 0) {
+ pr_err("%s: netdevice registration failed\n", __func__);
+ goto err_unmap;
+ }
+
+ netdev_info(dev, "Xircom cardbus revision %i at irq %i\n",
+ pdev->revision, pdev->irq);
+ /* start the transmitter to get a heartbeat */
+ /* TODO: send 2 dummy packets here */
+ transceiver_voodoo(private);
+
+ spin_lock_irqsave(&private->lock,flags);
+ activate_transmitter(private);
+ activate_receiver(private);
+ spin_unlock_irqrestore(&private->lock,flags);
+
+ trigger_receive(private);
+out:
+ return rc;
+
+err_unmap:
+ pci_iounmap(pdev, private->ioaddr);
+reg_fail:
+ dma_free_coherent(d, 8192, private->tx_buffer, private->tx_dma_handle);
+tx_buf_fail:
+ dma_free_coherent(d, 8192, private->rx_buffer, private->rx_dma_handle);
+rx_buf_fail:
+ free_netdev(dev);
+err_release:
+ pci_release_regions(pdev);
+err_disable:
+ pci_disable_device(pdev);
+ goto out;
+}
+
+
+/*
+ xircom_remove is called on module-unload or on device-eject.
+ it unregisters the irq, io-region and network device.
+ Interrupts and such are already stopped in the "ifconfig ethX down"
+ code.
+ */
+static void xircom_remove(struct pci_dev *pdev)
+{
+ struct net_device *dev = pci_get_drvdata(pdev);
+ struct xircom_private *card = netdev_priv(dev);
+ struct device *d = &pdev->dev;
+
+ unregister_netdev(dev);
+ pci_iounmap(pdev, card->ioaddr);
+ dma_free_coherent(d, 8192, card->tx_buffer, card->tx_dma_handle);
+ dma_free_coherent(d, 8192, card->rx_buffer, card->rx_dma_handle);
+ free_netdev(dev);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+}
+
+static irqreturn_t xircom_interrupt(int irq, void *dev_instance)
+{
+ struct net_device *dev = (struct net_device *) dev_instance;
+ struct xircom_private *card = netdev_priv(dev);
+ void __iomem *ioaddr = card->ioaddr;
+ unsigned int status;
+ int i;
+
+ spin_lock(&card->lock);
+ status = xr32(CSR5);
+
+#if defined DEBUG && DEBUG > 1
+ print_binary(status);
+ pr_debug("tx status 0x%08x 0x%08x\n",
+ card->tx_buffer[0], card->tx_buffer[4]);
+ pr_debug("rx status 0x%08x 0x%08x\n",
+ card->rx_buffer[0], card->rx_buffer[4]);
+#endif
+ /* Handle shared irq and hotplug */
+ if (status == 0 || status == 0xffffffff) {
+ spin_unlock(&card->lock);
+ return IRQ_NONE;
+ }
+
+ if (link_status_changed(card)) {
+ int newlink;
+ netdev_dbg(dev, "Link status has changed\n");
+ newlink = link_status(card);
+ netdev_info(dev, "Link is %d mbit\n", newlink);
+ if (newlink)
+ netif_carrier_on(dev);
+ else
+ netif_carrier_off(dev);
+
+ }
+
+ /* Clear all remaining interrupts */
+ status |= 0xffffffff; /* FIXME: make this clear only the
+ real existing bits */
+ xw32(CSR5, status);
+
+
+ for (i=0;i<NUMDESCRIPTORS;i++)
+ investigate_write_descriptor(dev,card,i,bufferoffsets[i]);
+ for (i=0;i<NUMDESCRIPTORS;i++)
+ investigate_read_descriptor(dev,card,i,bufferoffsets[i]);
+
+ spin_unlock(&card->lock);
+ return IRQ_HANDLED;
+}
+
+static netdev_tx_t xircom_start_xmit(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ struct xircom_private *card;
+ unsigned long flags;
+ int nextdescriptor;
+ int desc;
+
+ card = netdev_priv(dev);
+ spin_lock_irqsave(&card->lock,flags);
+
+ /* First see if we can free some descriptors */
+ for (desc=0;desc<NUMDESCRIPTORS;desc++)
+ investigate_write_descriptor(dev,card,desc,bufferoffsets[desc]);
+
+
+ nextdescriptor = (card->transmit_used +1) % (NUMDESCRIPTORS);
+ desc = card->transmit_used;
+
+ /* only send the packet if the descriptor is free */
+ if (card->tx_buffer[4*desc]==0) {
+ /* Copy the packet data; zero the memory first as the card
+ sometimes sends more than you ask it to. */
+
+ memset(&card->tx_buffer[bufferoffsets[desc]/4],0,1536);
+ skb_copy_from_linear_data(skb,
+ &(card->tx_buffer[bufferoffsets[desc] / 4]),
+ skb->len);
+ /* FIXME: The specification tells us that the length we send HAS to be a multiple of
+ 4 bytes. */
+
+ card->tx_buffer[4*desc+1] = cpu_to_le32(skb->len);
+ if (desc == NUMDESCRIPTORS - 1) /* bit 25: last descriptor of the ring */
+ card->tx_buffer[4*desc+1] |= cpu_to_le32(1<<25);
+
+ card->tx_buffer[4*desc+1] |= cpu_to_le32(0xF0000000);
+ /* 0xF0... means want interrupts*/
+ card->tx_skb[desc] = skb;
+
+ wmb();
+ /* This gives the descriptor to the card */
+ card->tx_buffer[4*desc] = cpu_to_le32(0x80000000);
+ trigger_transmit(card);
+ if (card->tx_buffer[nextdescriptor*4] & cpu_to_le32(0x8000000)) {
+ /* next descriptor is occupied... */
+ netif_stop_queue(dev);
+ }
+ card->transmit_used = nextdescriptor;
+ spin_unlock_irqrestore(&card->lock,flags);
+ return NETDEV_TX_OK;
+ }
+
+ /* Uh oh... no free descriptor... drop the packet */
+ netif_stop_queue(dev);
+ spin_unlock_irqrestore(&card->lock,flags);
+ trigger_transmit(card);
+
+ return NETDEV_TX_BUSY;
+}
+
+
+
+
+static int xircom_open(struct net_device *dev)
+{
+ struct xircom_private *xp = netdev_priv(dev);
+ const int irq = xp->pdev->irq;
+ int retval;
+
+ netdev_info(dev, "xircom cardbus adaptor found, using irq %i\n", irq);
+ retval = request_irq(irq, xircom_interrupt, IRQF_SHARED, dev->name, dev);
+ if (retval)
+ return retval;
+
+ xircom_up(xp);
+ xp->open = 1;
+
+ return 0;
+}
+
+static int xircom_close(struct net_device *dev)
+{
+ struct xircom_private *card;
+ unsigned long flags;
+
+ card = netdev_priv(dev);
+ netif_stop_queue(dev); /* we don't want new packets */
+
+
+ spin_lock_irqsave(&card->lock,flags);
+
+ disable_all_interrupts(card);
+#if 0
+ /* We can enable this again once we send dummy packets on ifconfig ethX up */
+ deactivate_receiver(card);
+ deactivate_transmitter(card);
+#endif
+ remove_descriptors(card);
+
+ spin_unlock_irqrestore(&card->lock,flags);
+
+ card->open = 0;
+ free_irq(card->pdev->irq, dev);
+
+ return 0;
+
+}
+
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void xircom_poll_controller(struct net_device *dev)
+{
+ struct xircom_private *xp = netdev_priv(dev);
+ const int irq = xp->pdev->irq;
+
+ disable_irq(irq);
+ xircom_interrupt(irq, dev);
+ enable_irq(irq);
+}
+#endif
+
+
+static void initialize_card(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&card->lock, flags);
+
+ /* First: reset the card */
+ val = xr32(CSR0);
+ val |= 0x01; /* Software reset */
+ xw32(CSR0, val);
+
+ udelay(100); /* give the card some time to reset */
+
+ val = xr32(CSR0);
+ val &= ~0x01; /* disable Software reset */
+ xw32(CSR0, val);
+
+
+ val = 0; /* Value 0x00 is a safe and conservative value
+ for the PCI configuration settings */
+ xw32(CSR0, val);
+
+
+ disable_all_interrupts(card);
+ deactivate_receiver(card);
+ deactivate_transmitter(card);
+
+ spin_unlock_irqrestore(&card->lock, flags);
+}
+
+/*
+trigger_transmit causes the card to check for frames to be transmitted.
+This is accomplished by writing to the CSR1 port. The documentation
+claims that the act of writing is sufficient and that the value is
+ignored; I chose zero.
+*/
+static void trigger_transmit(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+
+ xw32(CSR1, 0);
+}
+
+/*
+trigger_receive causes the card to check for empty frames in the
+descriptor list in which packets can be received.
+This is accomplished by writing to the CSR2 port. The documentation
+claims that the act of writing is sufficient and that the value is
+ignored; I chose zero.
+*/
+static void trigger_receive(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+
+ xw32(CSR2, 0);
+}
+
+/*
+setup_descriptors initializes the send and receive buffers to be valid
+descriptors and programs the addresses into the card.
+*/
+static void setup_descriptors(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ u32 address;
+ int i;
+
+ BUG_ON(card->rx_buffer == NULL);
+ BUG_ON(card->tx_buffer == NULL);
+
+ /* Receive descriptors */
+ memset(card->rx_buffer, 0, 128); /* clear the descriptors */
+ for (i=0;i<NUMDESCRIPTORS;i++ ) {
+
+ /* Rx Descr0: It's empty, let the card own it, no errors -> 0x80000000 */
+ card->rx_buffer[i*4 + 0] = cpu_to_le32(0x80000000);
+ /* Rx Descr1: buffer 1 is 1536 bytes, buffer 2 is 0 bytes */
+ card->rx_buffer[i*4 + 1] = cpu_to_le32(1536);
+ if (i == NUMDESCRIPTORS - 1) /* bit 25 is "last descriptor" */
+ card->rx_buffer[i*4 + 1] |= cpu_to_le32(1 << 25);
+
+ /* Rx Descr2: address of the buffer
+ we store the buffer at the 2nd half of the page */
+
+ address = card->rx_dma_handle;
+ card->rx_buffer[i*4 + 2] = cpu_to_le32(address + bufferoffsets[i]);
+ /* Rx Desc3: address of 2nd buffer -> 0 */
+ card->rx_buffer[i*4 + 3] = 0;
+ }
+
+ wmb();
+ /* Write the receive descriptor ring address to the card */
+ address = card->rx_dma_handle;
+ xw32(CSR3, address); /* Receive descr list address */
+
+
+ /* transmit descriptors */
+ memset(card->tx_buffer, 0, 128); /* clear the descriptors */
+
+ for (i=0;i<NUMDESCRIPTORS;i++ ) {
+ /* Tx Descr0: Empty, we own it, no errors -> 0x00000000 */
+ card->tx_buffer[i*4 + 0] = 0x00000000;
+ /* Tx Descr1: buffer 1 is 1536 bytes, buffer 2 is 0 bytes */
+ card->tx_buffer[i*4 + 1] = cpu_to_le32(1536);
+ if (i == NUMDESCRIPTORS - 1) /* bit 25 is "last descriptor" */
+ card->tx_buffer[i*4 + 1] |= cpu_to_le32(1 << 25);
+
+ /* Tx Descr2: address of the buffer
+ we store the buffer at the 2nd half of the page */
+ address = card->tx_dma_handle;
+ card->tx_buffer[i*4 + 2] = cpu_to_le32(address + bufferoffsets[i]);
+ /* Tx Desc3: address of 2nd buffer -> 0 */
+ card->tx_buffer[i*4 + 3] = 0;
+ }
+
+ wmb();
+ /* wite the transmit descriptor ring to the card */
+ address = card->tx_dma_handle;
+ xw32(CSR4, address); /* xmit descr list address */
+}
+
+/*
+remove_descriptors informs the card the descriptors are no longer
+valid by setting the address in the card to 0x00.
+*/
+static void remove_descriptors(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ unsigned int val;
+
+ val = 0;
+ xw32(CSR3, val); /* Receive descriptor address */
+ xw32(CSR4, val); /* Send descriptor address */
+}
+
+/*
+link_status_changed returns 1 if the card has indicated that
+the link status has changed. The new link status has to be read from CSR12.
+
+This function also clears the status-bit.
+*/
+static int link_status_changed(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ unsigned int val;
+
+ val = xr32(CSR5); /* Status register */
+ if (!(val & (1 << 27))) /* no change */
+ return 0;
+
+ /* clear the event by writing a 1 to the bit in the
+ status register. */
+ val = (1 << 27);
+ xw32(CSR5, val);
+
+ return 1;
+}
+
+
+/*
+transmit_active returns 1 if the transmitter on the card is
+in a non-stopped state.
+*/
+static int transmit_active(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+
+ if (!(xr32(CSR5) & (7 << 20))) /* transmitter disabled */
+ return 0;
+
+ return 1;
+}
+
+/*
+receive_active returns 1 if the receiver on the card is
+in a non-stopped state.
+*/
+static int receive_active(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+
+ if (!(xr32(CSR5) & (7 << 17))) /* receiver disabled */
+ return 0;
+
+ return 1;
+}
+
+/*
+activate_receiver enables the receiver on the card.
+Before being allowed to active the receiver, the receiver
+must be completely de-activated. To achieve this,
+this code actually disables the receiver first; then it waits for the
+receiver to become inactive, then it activates the receiver and then
+it waits for the receiver to be active.
+
+must be called with the lock held and interrupts disabled.
+*/
+static void activate_receiver(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ unsigned int val;
+ int counter;
+
+ val = xr32(CSR6); /* Operation mode */
+
+ /* If the "active" bit is set and the receiver is already
+ active, no need to do the expensive thing */
+ if ((val&2) && (receive_active(card)))
+ return;
+
+
+ val = val & ~2; /* disable the receiver */
+ xw32(CSR6, val);
+
+ counter = 10;
+ while (counter > 0) {
+ if (!receive_active(card))
+ break;
+ /* wait a while */
+ udelay(50);
+ counter--;
+ if (counter <= 0)
+ netdev_err(card->dev, "Receiver failed to deactivate\n");
+ }
+
+ /* enable the receiver */
+ val = xr32(CSR6); /* Operation mode */
+ val = val | 2; /* enable the receiver */
+ xw32(CSR6, val);
+
+ /* now wait for the card to activate again */
+ counter = 10;
+ while (counter > 0) {
+ if (receive_active(card))
+ break;
+ /* wait a while */
+ udelay(50);
+ counter--;
+ if (counter <= 0)
+ netdev_err(card->dev,
+ "Receiver failed to re-activate\n");
+ }
+}
+
+/*
+deactivate_receiver disables the receiver on the card.
+To achieve this this code disables the receiver first;
+then it waits for the receiver to become inactive.
+
+must be called with the lock held and interrupts disabled.
+*/
+static void deactivate_receiver(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ unsigned int val;
+ int counter;
+
+ val = xr32(CSR6); /* Operation mode */
+ val = val & ~2; /* disable the receiver */
+ xw32(CSR6, val);
+
+ counter = 10;
+ while (counter > 0) {
+ if (!receive_active(card))
+ break;
+ /* wait a while */
+ udelay(50);
+ counter--;
+ if (counter <= 0)
+ netdev_err(card->dev, "Receiver failed to deactivate\n");
+ }
+}
+
+
+/*
+activate_transmitter enables the transmitter on the card.
+Before being allowed to active the transmitter, the transmitter
+must be completely de-activated. To achieve this,
+this code actually disables the transmitter first; then it waits for the
+transmitter to become inactive, then it activates the transmitter and then
+it waits for the transmitter to be active again.
+
+must be called with the lock held and interrupts disabled.
+*/
+static void activate_transmitter(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ unsigned int val;
+ int counter;
+
+ val = xr32(CSR6); /* Operation mode */
+
+ /* If the "active" bit is set and the receiver is already
+ active, no need to do the expensive thing */
+ if ((val&(1<<13)) && (transmit_active(card)))
+ return;
+
+ val = val & ~(1 << 13); /* disable the transmitter */
+ xw32(CSR6, val);
+
+ counter = 10;
+ while (counter > 0) {
+ if (!transmit_active(card))
+ break;
+ /* wait a while */
+ udelay(50);
+ counter--;
+ if (counter <= 0)
+ netdev_err(card->dev,
+ "Transmitter failed to deactivate\n");
+ }
+
+ /* enable the transmitter */
+ val = xr32(CSR6); /* Operation mode */
+ val = val | (1 << 13); /* enable the transmitter */
+ xw32(CSR6, val);
+
+ /* now wait for the card to activate again */
+ counter = 10;
+ while (counter > 0) {
+ if (transmit_active(card))
+ break;
+ /* wait a while */
+ udelay(50);
+ counter--;
+ if (counter <= 0)
+ netdev_err(card->dev,
+ "Transmitter failed to re-activate\n");
+ }
+}
+
+/*
+deactivate_transmitter disables the transmitter on the card.
+To achieve this this code disables the transmitter first;
+then it waits for the transmitter to become inactive.
+
+must be called with the lock held and interrupts disabled.
+*/
+static void deactivate_transmitter(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ unsigned int val;
+ int counter;
+
+ val = xr32(CSR6); /* Operation mode */
+ val = val & ~2; /* disable the transmitter */
+ xw32(CSR6, val);
+
+ counter = 20;
+ while (counter > 0) {
+ if (!transmit_active(card))
+ break;
+ /* wait a while */
+ udelay(50);
+ counter--;
+ if (counter <= 0)
+ netdev_err(card->dev,
+ "Transmitter failed to deactivate\n");
+ }
+}
+
+
+/*
+enable_transmit_interrupt enables the transmit interrupt
+
+must be called with the lock held and interrupts disabled.
+*/
+static void enable_transmit_interrupt(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ unsigned int val;
+
+ val = xr32(CSR7); /* Interrupt enable register */
+ val |= 1; /* enable the transmit interrupt */
+ xw32(CSR7, val);
+}
+
+
+/*
+enable_receive_interrupt enables the receive interrupt
+
+must be called with the lock held and interrupts disabled.
+*/
+static void enable_receive_interrupt(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ unsigned int val;
+
+ val = xr32(CSR7); /* Interrupt enable register */
+ val = val | (1 << 6); /* enable the receive interrupt */
+ xw32(CSR7, val);
+}
+
+/*
+enable_link_interrupt enables the link status change interrupt
+
+must be called with the lock held and interrupts disabled.
+*/
+static void enable_link_interrupt(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ unsigned int val;
+
+ val = xr32(CSR7); /* Interrupt enable register */
+ val = val | (1 << 27); /* enable the link status chage interrupt */
+ xw32(CSR7, val);
+}
+
+
+
+/*
+disable_all_interrupts disables all interrupts
+
+must be called with the lock held and interrupts disabled.
+*/
+static void disable_all_interrupts(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+
+ xw32(CSR7, 0);
+}
+
+/*
+enable_common_interrupts enables several weird interrupts
+
+must be called with the lock held and interrupts disabled.
+*/
+static void enable_common_interrupts(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ unsigned int val;
+
+ val = xr32(CSR7); /* Interrupt enable register */
+ val |= (1<<16); /* Normal Interrupt Summary */
+ val |= (1<<15); /* Abnormal Interrupt Summary */
+ val |= (1<<13); /* Fatal bus error */
+ val |= (1<<8); /* Receive Process Stopped */
+ val |= (1<<7); /* Receive Buffer Unavailable */
+ val |= (1<<5); /* Transmit Underflow */
+ val |= (1<<2); /* Transmit Buffer Unavailable */
+ val |= (1<<1); /* Transmit Process Stopped */
+ xw32(CSR7, val);
+}
+
+/*
+enable_promisc starts promisc mode
+
+must be called with the lock held and interrupts disabled.
+*/
+static int enable_promisc(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ unsigned int val;
+
+ val = xr32(CSR6);
+ val = val | (1 << 6);
+ xw32(CSR6, val);
+
+ return 1;
+}
+
+
+
+
+/*
+link_status() checks the links status and will return 0 for no link, 10 for 10mbit link and 100 for.. guess what.
+
+Must be called in locked state with interrupts disabled
+*/
+static int link_status(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ u8 val;
+
+ val = xr8(CSR12);
+
+ /* bit 2 is 0 for 10mbit link, 1 for not an 10mbit link */
+ if (!(val & (1 << 2)))
+ return 10;
+ /* bit 1 is 0 for 100mbit link, 1 for not an 100mbit link */
+ if (!(val & (1 << 1)))
+ return 100;
+
+ /* If we get here -> no link at all */
+
+ return 0;
+}
+
+
+
+
+
+/*
+ read_mac_address() reads the MAC address from the NIC and stores it in the "dev" structure.
+
+ This function will take the spinlock itself and can, as a result, not be called with the lock helt.
+ */
+static void read_mac_address(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ unsigned long flags;
+ u8 link;
+ int i;
+
+ spin_lock_irqsave(&card->lock, flags);
+
+ xw32(CSR9, 1 << 12); /* enable boot rom access */
+ for (i = 0x100; i < 0x1f7; i += link + 2) {
+ u8 tuple, data_id, data_count;
+
+ xw32(CSR10, i);
+ tuple = xr32(CSR9);
+ xw32(CSR10, i + 1);
+ link = xr32(CSR9);
+ xw32(CSR10, i + 2);
+ data_id = xr32(CSR9);
+ xw32(CSR10, i + 3);
+ data_count = xr32(CSR9);
+ if ((tuple == 0x22) && (data_id == 0x04) && (data_count == 0x06)) {
+ u8 addr[ETH_ALEN];
+ int j;
+
+ for (j = 0; j < 6; j++) {
+ xw32(CSR10, i + j + 4);
+ addr[j] = xr32(CSR9) & 0xff;
+ }
+ eth_hw_addr_set(card->dev, addr);
+ break;
+ } else if (link == 0) {
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&card->lock, flags);
+ pr_debug(" %pM\n", card->dev->dev_addr);
+}
+
+
+/*
+ transceiver_voodoo() enables the external UTP plug thingy.
+ it's called voodoo as I stole this code and cannot cross-reference
+ it with the specification.
+ */
+static void transceiver_voodoo(struct xircom_private *card)
+{
+ void __iomem *ioaddr = card->ioaddr;
+ unsigned long flags;
+
+ /* disable all powermanagement */
+ pci_write_config_dword(card->pdev, PCI_POWERMGMT, 0x0000);
+
+ setup_descriptors(card);
+
+ spin_lock_irqsave(&card->lock, flags);
+
+ xw32(CSR15, 0x0008);
+ udelay(25);
+ xw32(CSR15, 0xa8050000);
+ udelay(25);
+ xw32(CSR15, 0xa00f0000);
+ udelay(25);
+
+ spin_unlock_irqrestore(&card->lock, flags);
+
+ netif_start_queue(card->dev);
+}
+
+
+static void xircom_up(struct xircom_private *card)
+{
+ unsigned long flags;
+ int i;
+
+ /* disable all powermanagement */
+ pci_write_config_dword(card->pdev, PCI_POWERMGMT, 0x0000);
+
+ setup_descriptors(card);
+
+ spin_lock_irqsave(&card->lock, flags);
+
+
+ enable_link_interrupt(card);
+ enable_transmit_interrupt(card);
+ enable_receive_interrupt(card);
+ enable_common_interrupts(card);
+ enable_promisc(card);
+
+ /* The card can have received packets already, read them away now */
+ for (i=0;i<NUMDESCRIPTORS;i++)
+ investigate_read_descriptor(card->dev,card,i,bufferoffsets[i]);
+
+
+ spin_unlock_irqrestore(&card->lock, flags);
+ trigger_receive(card);
+ trigger_transmit(card);
+ netif_start_queue(card->dev);
+}
+
+/* Bufferoffset is in BYTES */
+static void
+investigate_read_descriptor(struct net_device *dev, struct xircom_private *card,
+ int descnr, unsigned int bufferoffset)
+{
+ int status;
+
+ status = le32_to_cpu(card->rx_buffer[4*descnr]);
+
+ if (status > 0) { /* packet received */
+
+ /* TODO: discard error packets */
+
+ short pkt_len = ((status >> 16) & 0x7ff) - 4;
+ /* minus 4, we don't want the CRC */
+ struct sk_buff *skb;
+
+ if (pkt_len > 1518) {
+ netdev_err(dev, "Packet length %i is bogus\n", pkt_len);
+ pkt_len = 1518;
+ }
+
+ skb = netdev_alloc_skb(dev, pkt_len + 2);
+ if (skb == NULL) {
+ dev->stats.rx_dropped++;
+ goto out;
+ }
+ skb_reserve(skb, 2);
+ skb_copy_to_linear_data(skb,
+ &card->rx_buffer[bufferoffset / 4],
+ pkt_len);
+ skb_put(skb, pkt_len);
+ skb->protocol = eth_type_trans(skb, dev);
+ netif_rx(skb);
+ dev->stats.rx_packets++;
+ dev->stats.rx_bytes += pkt_len;
+
+out:
+ /* give the buffer back to the card */
+ card->rx_buffer[4*descnr] = cpu_to_le32(0x80000000);
+ trigger_receive(card);
+ }
+}
+
+
+/* Bufferoffset is in BYTES */
+static void
+investigate_write_descriptor(struct net_device *dev,
+ struct xircom_private *card,
+ int descnr, unsigned int bufferoffset)
+{
+ int status;
+
+ status = le32_to_cpu(card->tx_buffer[4*descnr]);
+#if 0
+ if (status & 0x8000) { /* Major error */
+ pr_err("Major transmit error status %x\n", status);
+ card->tx_buffer[4*descnr] = 0;
+ netif_wake_queue (dev);
+ }
+#endif
+ if (status > 0) { /* bit 31 is 0 when done */
+ if (card->tx_skb[descnr]!=NULL) {
+ dev->stats.tx_bytes += card->tx_skb[descnr]->len;
+ dev_kfree_skb_irq(card->tx_skb[descnr]);
+ }
+ card->tx_skb[descnr] = NULL;
+ /* Bit 8 in the status field is 1 if there was a collision */
+ if (status & (1 << 8))
+ dev->stats.collisions++;
+ card->tx_buffer[4*descnr] = 0; /* descriptor is free again */
+ netif_wake_queue (dev);
+ dev->stats.tx_packets++;
+ }
+}
+
+module_pci_driver(xircom_ops);
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-05 07:14:37 +0000