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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
maintainers:
- Andrew Lunn <andrew@lunn.ch>
description: |+
This is a special case of a MDIO bus multiplexer. A memory-mapped device,
like an FPGA, is used to control which child bus is connected. The mdio-mux
node must be a child of the memory-mapped device. The driver currently only
supports devices with 8, 16 or 32-bit registers.
allOf:
- $ref: /schemas/net/mdio-mux.yaml#
properties:
compatible:
items:
- const: mdio-mux-mmioreg
- const: mdio-mux
reg:
description: Contains the offset of the register that controls the bus
multiplexer. The size field in the 'reg' property is the size of register,
and must therefore be 1, 2, or 4.
maxItems: 1
mux-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description: Contains an eight-bit mask that specifies which bits in the
register control the actual bus multiplexer. The 'reg' property of each
child mdio-mux node must be constrained by this mask.
required:
- compatible
- reg
- mux-mask
unevaluatedProperties: false
examples:
- |
mdio-mux@9 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&xmdio0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <9 1>; // BRDCFG1
mux-mask = <0x6>; // EMI2
mdio@0 { // Slot 1 XAUI (FM2)
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
phy_xgmii_slot1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <4>;
};
};
mdio@2 { // Slot 2 XAUI (FM1)
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <4>;
};
};
};
...
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