summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml
blob: 6e6e02c91780cd9b8e27dd06d0376ba67f5c318b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SPI-NAND flash controller for MediaTek ARM SoCs

maintainers:
  - Chuanhong Guo <gch981213@gmail.com>

description: |
  The Mediatek SPI-NAND flash controller is an extended version of
  the Mediatek NAND flash controller. It can perform standard SPI
  instructions with one continuous write and one read for up-to 0xa0
  bytes. It also supports typical SPI-NAND page cache operations
  in single, dual or quad IO mode with pipelined ECC encoding/decoding
  using the accompanying ECC engine. There should be only one spi
  slave device following generic spi bindings.

allOf:
  - $ref: /schemas/spi/spi-controller.yaml#

properties:
  compatible:
    enum:
      - mediatek,mt7622-snand
      - mediatek,mt7629-snand

  reg:
    items:
      - description: core registers

  interrupts:
    items:
      - description: NFI interrupt

  clocks:
    items:
      - description: clock used for the controller
      - description: clock used for the SPI bus

  clock-names:
    items:
      - const: nfi_clk
      - const: pad_clk

  nand-ecc-engine:
    description: device-tree node of the accompanying ECC engine.
    $ref: /schemas/types.yaml#/definitions/phandle

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - nand-ecc-engine

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt7622-clk.h>
    soc {
      #address-cells = <2>;
      #size-cells = <2>;
      snfi: spi@1100d000 {
        compatible = "mediatek,mt7622-snand";
        reg = <0 0x1100d000 0 0x1000>;
        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
        clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
        clock-names = "nfi_clk", "pad_clk";
        nand-ecc-engine = <&bch>;
        #address-cells = <1>;
        #size-cells = <0>;

        flash@0 {
          compatible = "spi-nand";
          reg = <0>;
          spi-tx-bus-width = <4>;
          spi-rx-bus-width = <4>;
          nand-ecc-engine = <&snfi>;
        };
      };
    };