blob: abcbbe13723fb9dd7aad384045b647300720dcc5 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spmi/mtk,spmi-mtk-pmif.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek SPMI Controller
maintainers:
- Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
description: |+
On MediaTek SoCs the PMIC is connected via SPMI and the controller allows
for multiple SoCs to control a single SPMI master.
allOf:
- $ref: "spmi.yaml"
properties:
compatible:
enum:
- mediatek,mt6873-spmi
- mediatek,mt8195-spmi
reg:
maxItems: 2
reg-names:
items:
- const: pmif
- const: spmimst
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: pmif_sys_ck
- const: pmif_tmr_ck
- const: spmimst_clk_mux
assigned-clocks:
maxItems: 1
assigned-clock-parents:
maxItems: 1
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/mt8192-clk.h>
spmi: spmi@10027000 {
compatible = "mediatek,mt6873-spmi";
reg = <0x10027000 0xe00>,
<0x10029000 0x100>;
reg-names = "pmif", "spmimst";
clocks = <&infracfg CLK_INFRA_PMIC_AP>,
<&infracfg CLK_INFRA_PMIC_TMR>,
<&topckgen CLK_TOP_SPMI_MST_SEL>;
clock-names = "pmif_sys_ck",
"pmif_tmr_ck",
"spmimst_clk_mux";
assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
};
...
|
