summaryrefslogtreecommitdiffstats
path: root/drivers/clk/ti/clk-54xx.c
blob: 74dfd5823f835b60ff7a21c040188783fc81ca5e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
// SPDX-License-Identifier: GPL-2.0-only
/*
 * OMAP5 Clock init
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 *
 * Tero Kristo (t-kristo@ti.com)
 */

#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/clk/ti.h>
#include <dt-bindings/clock/omap5.h>

#include "clock.h"

#define OMAP5_DPLL_ABE_DEFFREQ				98304000

/*
 * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
 * states it must be at 960MHz
 */
#define OMAP5_DPLL_USB_DEFFREQ				960000000

static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = {
	{ OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
	{ OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h11x2_ck" },
	{ 0 },
};

static const char * const omap5_aess_fclk_parents[] __initconst = {
	"abe_clk",
	NULL,
};

static const struct omap_clkctrl_div_data omap5_aess_fclk_data __initconst = {
	.max_div = 2,
};

static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = {
	{ 24, TI_CLK_DIVIDER, omap5_aess_fclk_parents, &omap5_aess_fclk_data },
	{ 0 },
};

static const char * const omap5_dmic_gfclk_parents[] __initconst = {
	"abe-clkctrl:0018:26",
	"pad_clks_ck",
	"slimbus_clk",
	NULL,
};

static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
	"abe_24m_fclk",
	"dss_syc_gfclk_div",
	"func_24m_clk",
	NULL,
};

static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
	{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
	{ 0 },
};

static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
	"abe-clkctrl:0028:26",
	"pad_clks_ck",
	"slimbus_clk",
	NULL,
};

static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
	{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
	{ 0 },
};

static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
	"abe-clkctrl:0030:26",
	"pad_clks_ck",
	"slimbus_clk",
	NULL,
};

static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
	{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
	{ 0 },
};

static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
	"abe-clkctrl:0038:26",
	"pad_clks_ck",
	"slimbus_clk",
	NULL,
};

static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
	{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
	{ 0 },
};

static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = {
	"dss_syc_gfclk_div",
	"sys_32k_ck",
	NULL,
};

static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
	{ OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
	{ OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
	{ OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
	{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
	{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
	{ OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
	{ OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
	{ OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
	{ OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
	{ OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
	{ OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = {
	{ OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = {
	{ OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ OMAP5_L3_MAIN_2_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
	{ OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = {
	{ OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = {
	{ OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = {
	{ OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
	{ OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
	{ OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = {
	{ OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" },
	{ OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" },
	{ OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = {
	{ OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
	{ OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
	{ 0 },
};

static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = {
	"sys_clkin",
	"sys_32k_ck",
	NULL,
};

static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const char * const omap5_gpio2_dbclk_parents[] __initconst = {
	"sys_32k_ck",
	NULL,
};

static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
	{ OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
	{ OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
	{ OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
	{ OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
	{ OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
	{ OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0030:24" },
	{ OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
	{ OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
	{ OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
	{ OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
	{ OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
	{ OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
	{ OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
	{ OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
	{ OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
	{ OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" },
	{ OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
	{ OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
	{ OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
	{ OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
	{ OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
	{ 0 },
};

static const struct
omap_clkctrl_reg_data omap5_l4_secure_clkctrl_regs[] __initconst = {
	{ OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
	{ OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
	{ OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
	{ OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
	{ OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
	{ OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
	{ OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div" },
	{ 0 },
};

static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = {
	{ OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
	{ OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
	{ 0 },
};

static const char * const omap5_dss_dss_clk_parents[] __initconst = {
	"dpll_per_h12x2_ck",
	NULL,
};

static const char * const omap5_dss_48mhz_clk_parents[] __initconst = {
	"func_48m_fclk",
	NULL,
};

static const char * const omap5_dss_sys_clk_parents[] __initconst = {
	"dss_syc_gfclk_div",
	NULL,
};

static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
	{ 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
	{ 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
	{ 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
	{ OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
	{ 0 },
};

static const char * const omap5_gpu_core_mux_parents[] __initconst = {
	"dpll_core_h14x2_ck",
	"dpll_per_h14x2_ck",
	NULL,
};

static const char * const omap5_gpu_hyd_mux_parents[] __initconst = {
	"dpll_core_h14x2_ck",
	"dpll_per_h14x2_ck",
	NULL,
};

static const char * const omap5_gpu_sys_clk_parents[] __initconst = {
	"sys_clkin",
	NULL,
};

static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = {
	.max_div = 2,
};

static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
	{ 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
	{ 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data },
	{ 0 },
};

static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
	{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24" },
	{ 0 },
};

static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
	"func_128m_clk",
	"dpll_per_m2x2_ck",
	NULL,
};

static const char * const omap5_mmc1_fclk_parents[] __initconst = {
	"l3init-clkctrl:0008:24",
	NULL,
};

static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = {
	.max_div = 2,
};

static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
	{ 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
	{ 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data },
	{ 0 },
};

static const char * const omap5_mmc2_fclk_parents[] __initconst = {
	"l3init-clkctrl:0010:24",
	NULL,
};

static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = {
	.max_div = 2,
};

static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
	{ 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data },
	{ 0 },
};

static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = {
	"l3init_60m_fclk",
	NULL,
};

static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = {
	"dpll_usb_m2_ck",
	NULL,
};

static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
	"l3init-clkctrl:0038:24",
	NULL,
};

static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
	"l3init-clkctrl:0038:25",
	NULL,
};

static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = {
	"l3init_60m_fclk",
	"xclk60mhsp1_ck",
	NULL,
};

static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = {
	"l3init_60m_fclk",
	"xclk60mhsp2_ck",
	NULL,
};

static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = {
	{ 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
	{ 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
	{ 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
	{ 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
	{ 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
	{ 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
	{ 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
	{ 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
	{ 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
	{ 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
	{ 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
	{ 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
	{ 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
	{ 0 },
};

static const char * const omap5_sata_ref_clk_parents[] __initconst = {
	"sys_clkin",
	NULL,
};

static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
	{ 0 },
};

static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = {
	"dpll_usb_clkdcoldo",
	NULL,
};

static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
	{ OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
	{ OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
	{ OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
	{ OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
	{ OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
	{ OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
	{ OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
	{ OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = {
	{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = {
	{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
	{ 0 },
};

static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = {
	{ OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
	{ OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
	{ OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
	{ OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
	{ OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
	{ OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
	{ 0 },
};

const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
	{ 0x4a004320, omap5_mpu_clkctrl_regs },
	{ 0x4a004420, omap5_dsp_clkctrl_regs },
	{ 0x4a004520, omap5_abe_clkctrl_regs },
	{ 0x4a008720, omap5_l3main1_clkctrl_regs },
	{ 0x4a008820, omap5_l3main2_clkctrl_regs },
	{ 0x4a008920, omap5_ipu_clkctrl_regs },
	{ 0x4a008a20, omap5_dma_clkctrl_regs },
	{ 0x4a008b20, omap5_emif_clkctrl_regs },
	{ 0x4a008d20, omap5_l4cfg_clkctrl_regs },
	{ 0x4a008e20, omap5_l3instr_clkctrl_regs },
	{ 0x4a009020, omap5_l4per_clkctrl_regs },
	{ 0x4a0091a0, omap5_l4_secure_clkctrl_regs },
	{ 0x4a009220, omap5_iva_clkctrl_regs },
	{ 0x4a009420, omap5_dss_clkctrl_regs },
	{ 0x4a009520, omap5_gpu_clkctrl_regs },
	{ 0x4a009620, omap5_l3init_clkctrl_regs },
	{ 0x4ae07920, omap5_wkupaon_clkctrl_regs },
	{ 0 },
};

static struct ti_dt_clk omap54xx_clks[] = {
	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
	DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
	DT_CLK(NULL, "dmic_gfclk", "abe-clkctrl:0018:24"),
	DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
	DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
	DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
	DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
	DT_CLK(NULL, "dss_sys_clk", "dss-clkctrl:0000:10"),
	DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
	DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0040:8"),
	DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0048:8"),
	DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0050:8"),
	DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0058:8"),
	DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0060:8"),
	DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00f0:8"),
	DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f8:8"),
	DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"),
	DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
	DT_CLK("40122000.mcbsp", "prcm_fck", "abe-clkctrl:0028:26"),
	DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"),
	DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
	DT_CLK("40124000.mcbsp", "prcm_fck", "abe-clkctrl:0030:26"),
	DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"),
	DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
	DT_CLK("40126000.mcbsp", "prcm_fck", "abe-clkctrl:0038:26"),
	DT_CLK(NULL, "mmc1_32khz_clk", "l3init-clkctrl:0008:8"),
	DT_CLK(NULL, "mmc1_fclk", "l3init-clkctrl:0008:25"),
	DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
	DT_CLK(NULL, "mmc2_fclk", "l3init-clkctrl:0010:25"),
	DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
	DT_CLK(NULL, "pad_fck", "pad_clks_ck"),
	DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
	DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"),
	DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"),
	DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
	DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0018:24"),
	DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0020:24"),
	DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0028:24"),
	DT_CLK(NULL, "timer5_gfclk_mux", "abe-clkctrl:0048:24"),
	DT_CLK(NULL, "timer6_gfclk_mux", "abe-clkctrl:0050:24"),
	DT_CLK(NULL, "timer7_gfclk_mux", "abe-clkctrl:0058:24"),
	DT_CLK(NULL, "timer8_gfclk_mux", "abe-clkctrl:0060:24"),
	DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0030:24"),
	DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init-clkctrl:0038:13"),
	DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init-clkctrl:0038:14"),
	DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init-clkctrl:0038:7"),
	DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init-clkctrl:0038:11"),
	DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init-clkctrl:0038:12"),
	DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init-clkctrl:0038:6"),
	DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init-clkctrl:0038:8"),
	DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init-clkctrl:0038:9"),
	DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init-clkctrl:0038:10"),
	DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init-clkctrl:00d0:8"),
	DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init-clkctrl:0048:8"),
	DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init-clkctrl:0048:9"),
	DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init-clkctrl:0048:10"),
	DT_CLK(NULL, "utmi_p1_gfclk", "l3init-clkctrl:0038:24"),
	DT_CLK(NULL, "utmi_p2_gfclk", "l3init-clkctrl:0038:25"),
	{ .node_name = NULL },
};

int __init omap5xxx_dt_clk_init(void)
{
	int rc;
	struct clk *abe_dpll_ref, *abe_dpll, *abe_dpll_byp, *sys_32k_ck, *usb_dpll;

	ti_dt_clocks_register(omap54xx_clks);

	omap2_clk_disable_autoidle_all();

	ti_clk_add_aliases();

	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);

	/*
	 * This must also be set to sys_32k_ck to match or
	 * the ABE DPLL will not lock on a warm reboot when
	 * ABE timers are used.
	 */
	abe_dpll_byp = clk_get_sys(NULL, "abe_dpll_bypass_clk_mux");
	if (!rc)
		rc = clk_set_parent(abe_dpll_byp, sys_32k_ck);

	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
	if (!rc)
		rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
	if (rc)
		pr_err("%s: failed to configure ABE DPLL!\n", __func__);

	abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
	if (!rc)
		rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2);
	if (rc)
		pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__);

	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
	rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
	if (rc)
		pr_err("%s: failed to configure USB DPLL!\n", __func__);

	usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
	rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
	if (rc)
		pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);

	return 0;
}