drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_special_regs.h


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/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_
#define ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_

/*
 *****************************************
 *   DCORE0_TPC0_CFG_SPECIAL
 *   (Prototype: SPECIAL_REGS)
 *****************************************
 */

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_0 0x400BE80

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_1 0x400BE84

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_2 0x400BE88

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_3 0x400BE8C

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_4 0x400BE90

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_5 0x400BE94

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_6 0x400BE98

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_7 0x400BE9C

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_8 0x400BEA0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_9 0x400BEA4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_10 0x400BEA8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_11 0x400BEAC

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_12 0x400BEB0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_13 0x400BEB4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_14 0x400BEB8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_15 0x400BEBC

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_16 0x400BEC0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_17 0x400BEC4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_18 0x400BEC8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_19 0x400BECC

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_20 0x400BED0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_21 0x400BED4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_22 0x400BED8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_23 0x400BEDC

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_24 0x400BEE0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_25 0x400BEE4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_26 0x400BEE8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_27 0x400BEEC

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_28 0x400BEF0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_29 0x400BEF4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_30 0x400BEF8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_31 0x400BEFC

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_DATA 0x400BF00

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_REQ 0x400BF04

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_NUMOF 0x400BF0C

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_SEL 0x400BF10

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_CTL 0x400BF14

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_MASK 0x400BF18

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x400BF1C

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_STS 0x400BF20

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_ADDR 0x400BF24

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_RM 0x400BF28

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_MASK 0x400BF40

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_ADDR 0x400BF44

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_CAUSE 0x400BF48

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0 0x400BF60

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1 0x400BF64

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2 0x400BF68

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_3 0x400BF6C

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_0 0x400BF80

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_1 0x400BF84

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_2 0x400BF88

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_3 0x400BF8C

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_4 0x400BF90

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_5 0x400BF94

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_6 0x400BF98

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_7 0x400BF9C

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_8 0x400BFA0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_9 0x400BFA4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_10 0x400BFA8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_11 0x400BFAC

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_12 0x400BFB0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_13 0x400BFB4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_14 0x400BFB8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_15 0x400BFBC

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_16 0x400BFC0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_17 0x400BFC4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_18 0x400BFC8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_19 0x400BFCC

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_20 0x400BFD0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_21 0x400BFD4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_22 0x400BFD8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_23 0x400BFDC

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_24 0x400BFE0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_25 0x400BFE4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_26 0x400BFE8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_27 0x400BFEC

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_28 0x400BFF0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_29 0x400BFF4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_30 0x400BFF8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_31 0x400BFFC

#endif /* ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ */