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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
*/
#ifndef __DTS_HI3516CV300_CLOCK_H
#define __DTS_HI3516CV300_CLOCK_H
/* hi3516CV300 core CRG */
#define HI3516CV300_APB_CLK 0
#define HI3516CV300_UART0_CLK 1
#define HI3516CV300_UART1_CLK 2
#define HI3516CV300_UART2_CLK 3
#define HI3516CV300_SPI0_CLK 4
#define HI3516CV300_SPI1_CLK 5
#define HI3516CV300_FMC_CLK 6
#define HI3516CV300_MMC0_CLK 7
#define HI3516CV300_MMC1_CLK 8
#define HI3516CV300_MMC2_CLK 9
#define HI3516CV300_MMC3_CLK 10
#define HI3516CV300_ETH_CLK 11
#define HI3516CV300_ETH_MACIF_CLK 12
#define HI3516CV300_DMAC_CLK 13
#define HI3516CV300_PWM_CLK 14
#define HI3516CV300_USB2_BUS_CLK 15
#define HI3516CV300_USB2_OHCI48M_CLK 16
#define HI3516CV300_USB2_OHCI12M_CLK 17
#define HI3516CV300_USB2_OTG_UTMI_CLK 18
#define HI3516CV300_USB2_HST_PHY_CLK 19
#define HI3516CV300_USB2_UTMI0_CLK 20
#define HI3516CV300_USB2_PHY_CLK 21
/* hi3516CV300 sysctrl CRG */
#define HI3516CV300_WDT_CLK 1
#endif /* __DTS_HI3516CV300_CLOCK_H */
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