blob: 2e9029c22f38f31ec317326b12bffeed2b29df16 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
|
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Runyang Chen <runyang.chen@mediatek.com>
*/
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186
#define _DT_BINDINGS_RESET_CONTROLLER_MT8186
/* TOPRGU resets */
#define MT8186_TOPRGU_INFRA_SW_RST 0
#define MT8186_TOPRGU_MM_SW_RST 1
#define MT8186_TOPRGU_MFG_SW_RST 2
#define MT8186_TOPRGU_VENC_SW_RST 3
#define MT8186_TOPRGU_VDEC_SW_RST 4
#define MT8186_TOPRGU_IMG_SW_RST 5
#define MT8186_TOPRGU_DDR_SW_RST 6
#define MT8186_TOPRGU_INFRA_AO_SW_RST 8
#define MT8186_TOPRGU_CONNSYS_SW_RST 9
#define MT8186_TOPRGU_APMIXED_SW_RST 10
#define MT8186_TOPRGU_PWRAP_SW_RST 11
#define MT8186_TOPRGU_CONN_MCU_SW_RST 12
#define MT8186_TOPRGU_IPNNA_SW_RST 13
#define MT8186_TOPRGU_WPE_SW_RST 14
#define MT8186_TOPRGU_ADSP_SW_RST 15
#define MT8186_TOPRGU_AUDIO_SW_RST 17
#define MT8186_TOPRGU_CAM_MAIN_SW_RST 18
#define MT8186_TOPRGU_CAM_RAWA_SW_RST 19
#define MT8186_TOPRGU_CAM_RAWB_SW_RST 20
#define MT8186_TOPRGU_IPE_SW_RST 21
#define MT8186_TOPRGU_IMG2_SW_RST 22
#define MT8186_TOPRGU_SW_RST_NUM 23
/* MMSYS resets */
#define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 19
/* INFRA resets */
#define MT8186_INFRA_THERMAL_CTRL_RST 0
#define MT8186_INFRA_PTP_CTRL_RST 1
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */
|
