summaryrefslogtreecommitdiffstats
path: root/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/instruction.json
blob: e57cd55937c65caeecc3edf4d8aae64082a4e1a3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
[
    {
        "ArchStdEvent": "SW_INCR"
    },
    {
        "ArchStdEvent": "INST_RETIRED"
    },
    {
        "ArchStdEvent": "EXC_RETURN"
    },
    {
        "ArchStdEvent": "CID_WRITE_RETIRED"
    },
    {
        "ArchStdEvent": "INST_SPEC"
    },
    {
        "ArchStdEvent": "TTBR_WRITE_RETIRED"
    },
    {
        "ArchStdEvent": "BR_RETIRED"
    },
    {
        "ArchStdEvent": "BR_MIS_PRED_RETIRED"
    },
    {
        "ArchStdEvent": "OP_RETIRED"
    },
    {
        "ArchStdEvent": "OP_SPEC"
    },
    {
        "ArchStdEvent": "LDREX_SPEC"
    },
    {
        "ArchStdEvent": "STREX_PASS_SPEC"
    },
    {
        "ArchStdEvent": "STREX_FAIL_SPEC"
    },
    {
        "ArchStdEvent": "STREX_SPEC"
    },
    {
        "ArchStdEvent": "LD_SPEC"
    },
    {
        "ArchStdEvent": "ST_SPEC"
    },
    {
        "ArchStdEvent": "DP_SPEC"
    },
    {
        "ArchStdEvent": "ASE_SPEC"
    },
    {
        "ArchStdEvent": "VFP_SPEC"
    },
    {
        "ArchStdEvent": "PC_WRITE_SPEC"
    },
    {
        "ArchStdEvent": "CRYPTO_SPEC"
    },
    {
        "ArchStdEvent": "BR_IMMED_SPEC"
    },
    {
        "ArchStdEvent": "BR_RETURN_SPEC"
    },
    {
        "ArchStdEvent": "BR_INDIRECT_SPEC"
    },
    {
        "ArchStdEvent": "ISB_SPEC"
    },
    {
        "ArchStdEvent": "DSB_SPEC"
    },
    {
        "ArchStdEvent": "DMB_SPEC"
    },
    {
        "ArchStdEvent": "RC_LD_SPEC"
    },
    {
        "ArchStdEvent": "RC_ST_SPEC"
    },
    {
        "ArchStdEvent": "ASE_INST_SPEC"
    },
    {
        "ArchStdEvent": "SVE_INST_SPEC"
    },
    {
        "ArchStdEvent": "FP_HP_SPEC"
    },
    {
        "ArchStdEvent": "FP_SP_SPEC"
    },
    {
        "ArchStdEvent": "FP_DP_SPEC"
    },
    {
        "ArchStdEvent": "SVE_PRED_SPEC"
    },
    {
        "ArchStdEvent": "SVE_PRED_EMPTY_SPEC"
    },
    {
        "ArchStdEvent": "SVE_PRED_FULL_SPEC"
    },
    {
        "ArchStdEvent": "SVE_PRED_PARTIAL_SPEC"
    },
    {
        "ArchStdEvent": "SVE_PRED_NOT_FULL_SPEC"
    },
    {
        "ArchStdEvent": "SVE_LDFF_SPEC"
    },
    {
        "ArchStdEvent": "SVE_LDFF_FAULT_SPEC"
    },
    {
        "ArchStdEvent": "FP_SCALE_OPS_SPEC"
    },
    {
        "ArchStdEvent": "FP_FIXED_OPS_SPEC"
    },
    {
        "ArchStdEvent": "ASE_SVE_INT8_SPEC"
    },
    {
        "ArchStdEvent": "ASE_SVE_INT16_SPEC"
    },
    {
        "ArchStdEvent": "ASE_SVE_INT32_SPEC"
    },
    {
        "ArchStdEvent": "ASE_SVE_INT64_SPEC"
    }
]