summaryrefslogtreecommitdiffstats
path: root/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json
blob: 85654037b768c69231c4d0e6ee47409fc3810ec9 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
[
    {
        "BriefDescription": "Cycles when divider is busy executing divide operations",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x14",
        "EventName": "ARITH.FPU_DIV_ACTIVE",
        "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Speculative and retired  branches",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x88",
        "EventName": "BR_INST_EXEC.ALL_BRANCHES",
        "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.",
        "SampleAfterValue": "200003",
        "UMask": "0xff"
    },
    {
        "BriefDescription": "Speculative and retired macro-conditional branches",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x88",
        "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
        "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.",
        "SampleAfterValue": "200003",
        "UMask": "0xc1"
    },
    {
        "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x88",
        "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
        "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.",
        "SampleAfterValue": "200003",
        "UMask": "0xc2"
    },
    {
        "BriefDescription": "Speculative and retired direct near calls",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x88",
        "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
        "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.",
        "SampleAfterValue": "200003",
        "UMask": "0xd0"
    },
    {
        "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x88",
        "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
        "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.",
        "SampleAfterValue": "200003",
        "UMask": "0xc4"
    },
    {
        "BriefDescription": "Speculative and retired indirect return branches.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x88",
        "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
        "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.",
        "SampleAfterValue": "200003",
        "UMask": "0xc8"
    },
    {
        "BriefDescription": "Not taken macro-conditional branches",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x88",
        "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
        "PublicDescription": "This event counts not taken macro-conditional branch instructions.",
        "SampleAfterValue": "200003",
        "UMask": "0x41"
    },
    {
        "BriefDescription": "Taken speculative and retired macro-conditional branches",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x88",
        "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
        "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.",
        "SampleAfterValue": "200003",
        "UMask": "0x81"
    },
    {
        "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x88",
        "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
        "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.",
        "SampleAfterValue": "200003",
        "UMask": "0x82"
    },
    {
        "BriefDescription": "Taken speculative and retired direct near calls",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x88",
        "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
        "PublicDescription": "This event counts taken speculative and retired direct near calls.",
        "SampleAfterValue": "200003",
        "UMask": "0x90"
    },
    {
        "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x88",
        "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
        "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.",
        "SampleAfterValue": "200003",
        "UMask": "0x84"
    },
    {
        "BriefDescription": "Taken speculative and retired indirect calls",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x88",
        "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
        "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.",
        "SampleAfterValue": "200003",
        "UMask": "0xa0"
    },
    {
        "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x88",
        "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
        "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.",
        "SampleAfterValue": "200003",
        "UMask": "0x88"
    },
    {
        "BriefDescription": "All (macro) branch instructions retired.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC4",
        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
        "PublicDescription": "This event counts all (macro) branch instructions retired.",
        "SampleAfterValue": "400009"
    },
    {
        "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "Errata": "BDW98",
        "EventCode": "0xC4",
        "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
        "PEBS": "2",
        "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.",
        "SampleAfterValue": "400009",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC4",
        "EventName": "BR_INST_RETIRED.CONDITIONAL",
        "PEBS": "1",
        "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired.",
        "SampleAfterValue": "400009",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Far branch instructions retired.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDW98",
        "EventCode": "0xC4",
        "EventName": "BR_INST_RETIRED.FAR_BRANCH",
        "PublicDescription": "This event counts far branch instructions retired.",
        "SampleAfterValue": "100007",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC4",
        "EventName": "BR_INST_RETIRED.NEAR_CALL",
        "PEBS": "1",
        "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired.",
        "SampleAfterValue": "100007",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC4",
        "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
        "PEBS": "1",
        "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3).",
        "SampleAfterValue": "100007",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Return instructions retired. (Precise Event - PEBS)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC4",
        "EventName": "BR_INST_RETIRED.NEAR_RETURN",
        "PEBS": "1",
        "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts return instructions retired.",
        "SampleAfterValue": "100007",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC4",
        "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
        "PEBS": "1",
        "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired.",
        "SampleAfterValue": "400009",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Not taken branch instructions retired.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC4",
        "EventName": "BR_INST_RETIRED.NOT_TAKEN",
        "PublicDescription": "This event counts not taken branch instructions retired.",
        "SampleAfterValue": "400009",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x89",
        "EventName": "BR_MISP_EXEC.ALL_BRANCHES",
        "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.",
        "SampleAfterValue": "200003",
        "UMask": "0xff"
    },
    {
        "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x89",
        "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
        "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.",
        "SampleAfterValue": "200003",
        "UMask": "0xc1"
    },
    {
        "BriefDescription": "Mispredicted indirect branches excluding calls and returns",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x89",
        "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
        "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.",
        "SampleAfterValue": "200003",
        "UMask": "0xc4"
    },
    {
        "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x89",
        "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
        "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.",
        "SampleAfterValue": "200003",
        "UMask": "0x41"
    },
    {
        "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x89",
        "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
        "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.",
        "SampleAfterValue": "200003",
        "UMask": "0x81"
    },
    {
        "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x89",
        "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
        "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.",
        "SampleAfterValue": "200003",
        "UMask": "0x84"
    },
    {
        "BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x89",
        "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
        "SampleAfterValue": "200003",
        "UMask": "0xa0"
    },
    {
        "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x89",
        "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
        "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.",
        "SampleAfterValue": "200003",
        "UMask": "0x88"
    },
    {
        "BriefDescription": "All mispredicted macro branch instructions retired.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC5",
        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
        "PublicDescription": "This event counts all mispredicted macro branch instructions retired.",
        "SampleAfterValue": "400009"
    },
    {
        "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0xC5",
        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
        "PEBS": "2",
        "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.",
        "SampleAfterValue": "400009",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC5",
        "EventName": "BR_MISP_RETIRED.CONDITIONAL",
        "PEBS": "1",
        "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired.",
        "SampleAfterValue": "400009",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC5",
        "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
        "PEBS": "1",
        "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).",
        "SampleAfterValue": "400009",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "This event counts the number of mispredicted ret instructions retired.(Precise Event)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC5",
        "EventName": "BR_MISP_RETIRED.RET",
        "PEBS": "1",
        "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retired.",
        "SampleAfterValue": "100007",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "EventCode": "0x3c",
        "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x3C",
        "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
        "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x3C",
        "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x3C",
        "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Reference cycles when the core is not in halt state.",
        "Counter": "Fixed counter 2",
        "CounterHTOff": "Fixed counter 2",
        "EventName": "CPU_CLK_UNHALTED.REF_TSC",
        "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
        "SampleAfterValue": "2000003",
        "UMask": "0x3"
    },
    {
        "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x3C",
        "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
        "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x3C",
        "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Core cycles when the thread is not in halt state",
        "Counter": "Fixed counter 1",
        "CounterHTOff": "Fixed counter 1",
        "EventName": "CPU_CLK_UNHALTED.THREAD",
        "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
        "Counter": "Fixed counter 1",
        "CounterHTOff": "Fixed counter 1",
        "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Thread cycles when thread is not in halt state",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x3C",
        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
        "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
        "SampleAfterValue": "2000003"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x3C",
        "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
        "SampleAfterValue": "2000003"
    },
    {
        "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
        "Counter": "2",
        "CounterHTOff": "2",
        "CounterMask": "8",
        "EventCode": "0xA3",
        "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
        "Counter": "2",
        "CounterHTOff": "2",
        "CounterMask": "8",
        "EventCode": "0xA3",
        "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
        "PublicDescription": "Counts number of cycles the CPU has at least one pending  demand load request missing the L1 data cache.",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "1",
        "EventCode": "0xA3",
        "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "1",
        "EventCode": "0xA3",
        "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
        "PublicDescription": "Counts number of cycles the CPU has at least one pending  demand* load request missing the L2 cache.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "2",
        "EventCode": "0xA3",
        "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
        "PublicDescription": "Counts number of cycles the CPU has at least one pending  demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "CounterMask": "2",
        "EventCode": "0xA3",
        "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "CounterMask": "4",
        "EventCode": "0xA3",
        "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
        "PublicDescription": "Counts number of cycles nothing is executed on any execution port.",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
        "Counter": "2",
        "CounterHTOff": "2",
        "CounterMask": "12",
        "EventCode": "0xA3",
        "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
        "SampleAfterValue": "2000003",
        "UMask": "0xc"
    },
    {
        "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
        "Counter": "2",
        "CounterHTOff": "2",
        "CounterMask": "12",
        "EventCode": "0xA3",
        "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
        "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.",
        "SampleAfterValue": "2000003",
        "UMask": "0xc"
    },
    {
        "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "5",
        "EventCode": "0xA3",
        "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
        "SampleAfterValue": "2000003",
        "UMask": "0x5"
    },
    {
        "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "CounterMask": "5",
        "EventCode": "0xA3",
        "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
        "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.",
        "SampleAfterValue": "2000003",
        "UMask": "0x5"
    },
    {
        "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "CounterMask": "6",
        "EventCode": "0xA3",
        "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
        "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.",
        "SampleAfterValue": "2000003",
        "UMask": "0x6"
    },
    {
        "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "6",
        "EventCode": "0xA3",
        "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
        "SampleAfterValue": "2000003",
        "UMask": "0x6"
    },
    {
        "BriefDescription": "Total execution stalls.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "4",
        "EventCode": "0xA3",
        "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x87",
        "EventName": "ILD_STALL.LCP",
        "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Instructions retired from execution.",
        "Counter": "Fixed counter 0",
        "CounterHTOff": "Fixed counter 0",
        "EventName": "INST_RETIRED.ANY",
        "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of instructions retired. General Counter   - architectural event",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM61",
        "EventCode": "0xC0",
        "EventName": "INST_RETIRED.ANY_P",
        "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).",
        "SampleAfterValue": "2000003"
    },
    {
        "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
        "Counter": "1",
        "CounterHTOff": "1",
        "Errata": "BDM11, BDM55",
        "EventCode": "0xC0",
        "EventName": "INST_RETIRED.PREC_DIST",
        "PEBS": "2",
        "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "FP operations  retired. X87 FP operations that have no exceptions:",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC0",
        "EventName": "INST_RETIRED.X87",
        "PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x0D",
        "EventName": "INT_MISC.RAT_STALL_CYCLES",
        "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "1",
        "EventCode": "0x0D",
        "EventName": "INT_MISC.RECOVERY_CYCLES",
        "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.",
        "SampleAfterValue": "2000003",
        "UMask": "0x3"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "1",
        "EventCode": "0x0D",
        "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
        "SampleAfterValue": "2000003",
        "UMask": "0x3"
    },
    {
        "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x03",
        "EventName": "LD_BLOCKS.NO_SR",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x03",
        "EventName": "LD_BLOCKS.STORE_FORWARD",
        "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "False dependencies in MOB due to partial compare",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x07",
        "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
        "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x4C",
        "EventName": "LOAD_HIT_PRE.HW_PF",
        "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x4c",
        "EventName": "LOAD_HIT_PRE.SW_PF",
        "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "4",
        "EventCode": "0xA8",
        "EventName": "LSD.CYCLES_4_UOPS",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "1",
        "EventCode": "0xA8",
        "EventName": "LSD.CYCLES_ACTIVE",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of Uops delivered by the LSD.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA8",
        "EventName": "LSD.UOPS",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of machine clears (nukes) of any type.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0xC3",
        "EventName": "MACHINE_CLEARS.COUNT",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC3",
        "EventName": "MACHINE_CLEARS.CYCLES",
        "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC3",
        "EventName": "MACHINE_CLEARS.MASKMOV",
        "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Self-modifying code (SMC) detected.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC3",
        "EventName": "MACHINE_CLEARS.SMC",
        "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x58",
        "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x58",
        "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
        "SampleAfterValue": "1000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC1",
        "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
        "SampleAfterValue": "100003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Resource-related stall cycles",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA2",
        "EventName": "RESOURCE_STALLS.ANY",
        "PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles stalled due to re-order buffer full.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA2",
        "EventName": "RESOURCE_STALLS.ROB",
        "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA2",
        "EventName": "RESOURCE_STALLS.RS",
        "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA2",
        "EventName": "RESOURCE_STALLS.SB",
        "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Count cases of saving new LBR",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xCC",
        "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
        "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.",
        "SampleAfterValue": "2000003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x5E",
        "EventName": "RS_EVENTS.EMPTY_CYCLES",
        "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0x5E",
        "EventName": "RS_EVENTS.EMPTY_END",
        "Invert": "1",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 0",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 1",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 2",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 3",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 4",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 5",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
        "SampleAfterValue": "2000003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 6",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
        "SampleAfterValue": "2000003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 7",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
        "SampleAfterValue": "2000003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Number of uops executed on the core.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB1",
        "EventName": "UOPS_EXECUTED.CORE",
        "PublicDescription": "Number of uops executed from any thread.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "1",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "2",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "3",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "CounterMask": "4",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xb1",
        "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
        "Invert": "1",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles where at least 1 uop was executed per-thread.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0xB1",
        "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles where at least 2 uops were executed per-thread.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "CounterMask": "2",
        "EventCode": "0xB1",
        "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles where at least 3 uops were executed per-thread.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "CounterMask": "3",
        "EventCode": "0xB1",
        "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "CounterMask": "4",
        "EventCode": "0xB1",
        "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0xB1",
        "EventName": "UOPS_EXECUTED.STALL_CYCLES",
        "Invert": "1",
        "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB1",
        "EventName": "UOPS_EXECUTED.THREAD",
        "PublicDescription": "Number of uops to be executed per-thread each cycle.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 0",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_0",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Cycles per core when uops are exectuted in port 0.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 1",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_1",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Cycles per core when uops are exectuted in port 1.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 2",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_2",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Cycles per core when uops are dispatched to port 2.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 3",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_3",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Cycles per core when uops are dispatched to port 3.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 4",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_4",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Cycles per core when uops are exectuted in port 4.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 5",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_5",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
        "SampleAfterValue": "2000003",
        "UMask": "0x20"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Cycles per core when uops are exectuted in port 5.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
        "SampleAfterValue": "2000003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 6",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_6",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
        "SampleAfterValue": "2000003",
        "UMask": "0x40"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Cycles per core when uops are exectuted in port 6.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
        "SampleAfterValue": "2000003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Cycles per thread when uops are executed in port 7",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_7",
        "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
        "SampleAfterValue": "2000003",
        "UMask": "0x80"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Cycles per core when uops are dispatched to port 7.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xA1",
        "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
        "SampleAfterValue": "2000003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x0E",
        "EventName": "UOPS_ISSUED.ANY",
        "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x0E",
        "EventName": "UOPS_ISSUED.FLAGS_MERGE",
        "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x0E",
        "EventName": "UOPS_ISSUED.SINGLE_MUL",
        "SampleAfterValue": "2000003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x0E",
        "EventName": "UOPS_ISSUED.SLOW_LEA",
        "SampleAfterValue": "2000003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x0E",
        "EventName": "UOPS_ISSUED.STALL_CYCLES",
        "Invert": "1",
        "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Actually retired uops. (Precise Event - PEBS)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xC2",
        "EventName": "UOPS_RETIRED.ALL",
        "PEBS": "1",
        "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retirement slots used. (Precise Event - PEBS)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xC2",
        "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
        "PEBS": "1",
        "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles without actually retired uops.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0xC2",
        "EventName": "UOPS_RETIRED.STALL_CYCLES",
        "Invert": "1",
        "PublicDescription": "This event counts cycles without actually retired uops.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles with less than 10 actually retired uops.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "CounterMask": "10",
        "EventCode": "0xC2",
        "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
        "Invert": "1",
        "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    }
]