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[
{
"BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.",
"Counter": "0,1",
"EventCode": "0xE6",
"EventName": "BACLEARS.ALL",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end.",
"Counter": "0,1",
"EventCode": "0xE6",
"EventName": "BACLEARS.COND",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end.",
"Counter": "0,1",
"EventCode": "0xE6",
"EventName": "BACLEARS.RETURN",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts all instruction fetches, including uncacheable fetches.",
"Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
"SampleAfterValue": "200003",
"UMask": "0x3"
},
{
"BriefDescription": "Counts all instruction fetches that hit the instruction cache.",
"Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.",
"Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of times the MSROM starts a flow of uops.",
"Counter": "0,1",
"EventCode": "0xE7",
"EventName": "MS_DECODED.MS_ENTRY",
"SampleAfterValue": "200003",
"UMask": "0x1"
}
]
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