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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 17:32:43 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 17:32:43 +0000 |
commit | 6bf0a5cb5034a7e684dcc3500e841785237ce2dd (patch) | |
tree | a68f146d7fa01f0134297619fbe7e33db084e0aa /js/src/jit/riscv64/extension/extension-riscv-zicsr.cc | |
parent | Initial commit. (diff) | |
download | thunderbird-upstream.tar.xz thunderbird-upstream.zip |
Adding upstream version 1:115.7.0.upstream/1%115.7.0upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'js/src/jit/riscv64/extension/extension-riscv-zicsr.cc')
-rw-r--r-- | js/src/jit/riscv64/extension/extension-riscv-zicsr.cc | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/js/src/jit/riscv64/extension/extension-riscv-zicsr.cc b/js/src/jit/riscv64/extension/extension-riscv-zicsr.cc new file mode 100644 index 0000000000..7fa87393a3 --- /dev/null +++ b/js/src/jit/riscv64/extension/extension-riscv-zicsr.cc @@ -0,0 +1,44 @@ +// Copyright 2022 the V8 project authors. All rights reserved. +// Use of this source code is governed by a BSD-style license that can be +// found in the LICENSE file. +#include "jit/riscv64/extension/extension-riscv-zicsr.h" + +#include "jit/riscv64/constant/Constant-riscv64.h" +#include "jit/riscv64/Register-riscv64.h" +#include "jit/riscv64/Assembler-riscv64.h" +#include "jit/riscv64/Architecture-riscv64.h" +namespace js { +namespace jit { + +void AssemblerRISCVZicsr::csrrw(Register rd, ControlStatusReg csr, + Register rs1) { + GenInstrCSR_ir(0b001, rd, csr, rs1); +} + +void AssemblerRISCVZicsr::csrrs(Register rd, ControlStatusReg csr, + Register rs1) { + GenInstrCSR_ir(0b010, rd, csr, rs1); +} + +void AssemblerRISCVZicsr::csrrc(Register rd, ControlStatusReg csr, + Register rs1) { + GenInstrCSR_ir(0b011, rd, csr, rs1); +} + +void AssemblerRISCVZicsr::csrrwi(Register rd, ControlStatusReg csr, + uint8_t imm5) { + GenInstrCSR_ii(0b101, rd, csr, imm5); +} + +void AssemblerRISCVZicsr::csrrsi(Register rd, ControlStatusReg csr, + uint8_t imm5) { + GenInstrCSR_ii(0b110, rd, csr, imm5); +} + +void AssemblerRISCVZicsr::csrrci(Register rd, ControlStatusReg csr, + uint8_t imm5) { + GenInstrCSR_ii(0b111, rd, csr, imm5); +} + +} // namespace jit +} // namespace js |