1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
|
; $Id: feenableexcept.asm $
;; @file
; IPRT - No-CRT feenableexcept - AMD64 & X86.
;
;
; Copyright (C) 2022 Oracle and/or its affiliates.
;
; This file is part of VirtualBox base platform packages, as
; available from https://www.virtualbox.org.
;
; This program is free software; you can redistribute it and/or
; modify it under the terms of the GNU General Public License
; as published by the Free Software Foundation, in version 3 of the
; License.
;
; This program is distributed in the hope that it will be useful, but
; WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
; General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, see <https://www.gnu.org/licenses>.
;
; The contents of this file may alternatively be used under the terms
; of the Common Development and Distribution License Version 1.0
; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
; in the VirtualBox distribution, in which case the provisions of the
; CDDL are applicable instead of those of the GPL.
;
; You may elect to license modified versions of this file under the
; terms and conditions of either the GPL or the CDDL or both.
;
; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
;
%define RT_ASM_WITH_SEH64
%include "iprt/asmdefs.mac"
%include "iprt/x86.mac"
BEGINCODE
;;
; Enables a set of exceptions (BSD/GNU extension).
;
; @returns eax = Previous enabled exceptions on success (not subject to fXcpt),
; -1 on failure.
; @param fXcpt 32-bit: [xBP+8] msc64: ecx gcc64: edi - Mask of exceptions to enable.
;
RT_NOCRT_BEGINPROC feenableexcept
push xBP
SEH64_PUSH_xBP
mov xBP, xSP
SEH64_SET_FRAME_xBP 0
sub xSP, 10h
SEH64_ALLOCATE_STACK 10h
SEH64_END_PROLOGUE
;
; Load the parameter into ecx.
;
%ifdef ASM_CALL64_GCC
mov ecx, edi
%elifdef RT_ARCH_X86
mov ecx, [xBP + xCB*2]
%endif
or eax, -1
test ecx, ~X86_FCW_XCPT_MASK
%ifndef RT_STRICT
jnz .return
%else
jz .input_ok
int3
jmp .return
.input_ok:
%endif
; Invert the mask as we're enabling the exceptions, not masking them.
not ecx
;
; Make the changes (old mask in eax).
;
; Modify the x87 mask first (ecx preserved).
fstcw [xBP - 10h]
%ifdef RT_ARCH_X86 ; Return the inverted x87 mask in 32-bit mode.
mov ax, word [xBP - 10h]
and eax, X86_FCW_XCPT_MASK
%endif
and word [xBP - 10h], cx
fldcw [xBP - 10h]
%ifdef RT_ARCH_X86
; SSE supported (ecx preserved)?
extern NAME(rtNoCrtHasSse)
call NAME(rtNoCrtHasSse)
test al, al
jz .return_ok
%endif
; Modify the SSE mask (modifies ecx).
stmxcsr [xBP - 10h]
%ifdef RT_ARCH_AMD64 ; Return the inverted MXCSR exception mask on AMD64 because windows doesn't necessarily set the x87 one.
mov eax, [xBP - 10h]
and eax, X86_MXCSR_XCPT_MASK
shr eax, X86_MXCSR_XCPT_MASK_SHIFT
%endif
rol ecx, X86_MXCSR_XCPT_MASK_SHIFT
and [xBP - 10h], ecx
ldmxcsr [xBP - 10h]
.return_ok:
not eax ; Invert it as we return the enabled rather than masked exceptions.
.return:
leave
ret
ENDPROC RT_NOCRT(feenableexcept)
|
