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.\"
.\" Copyright 2013 Samy Al Bahra.
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
.\"
.Dd May 18, 2013
.Dt CK_PR_FENCE_LOAD_ATOMIC 3
.Sh NAME
.Nm ck_pr_fence_load_atomic
.Nd enforce ordering of load operations to atomic read-modify-write operations
.Sh LIBRARY
Concurrency Kit (libck, \-lck)
.Sh SYNOPSIS
.In ck_pr.h
.Ft void
.Fn ck_pr_fence_load_atomic void
.Ft void
.Fn ck_pr_fence_strict_load_atomic void
.Sh DESCRIPTION
This function enforces the ordering of any memory load
and
.Fn ck_pr_load 3
operations with respect to store operations relative to
the invocation of the function. Any store operations that
were committed on remote processors
and received by the calling processor before the invocation of
.Fn ck_pr_fence_load_atomic
is also be made visible only after a call to
the ck_pr_fence_load family of functions.
This function always serves as an implicit compiler barrier.
On architectures with CK_MD_TSO or CK_MD_PSO specified (total store ordering
and partial store ordering respectively), this operation only serves
as a compiler barrier and no fence instructions will be emitted. To
force the unconditional emission of a load fence, use
.Fn ck_pr_fence_strict_load_atomic .
Architectures implementing CK_MD_RMO always emit a fence.
.Sh EXAMPLE
.Bd -literal -offset indent
#include <ck_pr.h>
static unsigned int a;
static unsigned int b;
void
function(void)
{
unsigned int snapshot_a, snapshot_b;
snapshot_a = ck_pr_load_uint(&a);
/*
* Guarantee that the load from "a" completes
* before the update to "b".
*/
ck_pr_fence_load_atomic();
ck_pr_fas_uint(&b, 1);
return;
}
.Ed
.Sh RETURN VALUES
This function has no return value.
.Sh SEE ALSO
.Xr ck_pr_stall 3 ,
.Xr ck_pr_fence_atomic 3 ,
.Xr ck_pr_fence_atomic_store 3 ,
.Xr ck_pr_fence_atomic_load 3 ,
.Xr ck_pr_fence_load_depends 3 ,
.Xr ck_pr_fence_load_store 3 ,
.Xr ck_pr_fence_store 3 ,
.Xr ck_pr_fence_memory 3 ,
.Xr ck_pr_barrier 3 ,
.Xr ck_pr_fas 3 ,
.Xr ck_pr_load 3 ,
.Xr ck_pr_store 3 ,
.Xr ck_pr_faa 3 ,
.Xr ck_pr_inc 3 ,
.Xr ck_pr_dec 3 ,
.Xr ck_pr_neg 3 ,
.Xr ck_pr_not 3 ,
.Xr ck_pr_add 3 ,
.Xr ck_pr_sub 3 ,
.Xr ck_pr_and 3 ,
.Xr ck_pr_or 3 ,
.Xr ck_pr_xor 3 ,
.Xr ck_pr_cas 3 ,
.Xr ck_pr_btc 3 ,
.Xr ck_pr_bts 3 ,
.Xr ck_pr_btr 3
.Pp
Additional information available at http://concurrencykit.org/
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