diff options
Diffstat (limited to 'linux/nvme.h')
| -rw-r--r-- | linux/nvme.h | 509 |
1 files changed, 484 insertions, 25 deletions
diff --git a/linux/nvme.h b/linux/nvme.h index f2c4fdb..4ad09ee 100644 --- a/linux/nvme.h +++ b/linux/nvme.h @@ -70,6 +70,7 @@ static inline uint64_t le64_to_cpu(__le64 x) #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery" #define NVME_RDMA_IP_PORT 4420 +#define NVME_DISC_IP_PORT 8009 #define NVME_NSID_ALL 0xffffffff @@ -139,6 +140,13 @@ enum { NVMF_TCP_SECTYPE_TLS = 1, /* Transport Layer Security */ }; +/* I/O Command Sets + */ +enum { + NVME_IOCS_NVM = 0x00, + NVME_IOCS_ZONED = 0x02, +}; + #define NVME_AQ_DEPTH 32 #define NVME_NR_AEN_COMMANDS 1 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) @@ -172,7 +180,8 @@ enum { NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */ NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity Buffer Size */ NVME_REG_PMRSWTP= 0x0e10, /* Persistent Memory Region Sustained Write Throughput */ - NVME_REG_PMRMSC = 0x0e14, /* Persistent Memory Region Controller Memory Space Control */ + NVME_REG_PMRMSCL= 0x0e14, /* Persistent Memory Region Controller Memory Space Control Lower */ + NVME_REG_PMRMSCU= 0x0e18, /* Persistent Memory Region Controller Memory Space Control Upper*/ NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */ }; @@ -325,7 +334,7 @@ struct nvme_id_ctrl { __u8 vwc; __le16 awun; __le16 awupf; - __u8 nvscc; + __u8 icsvscc; __u8 nwpc; __le16 acwu; __u8 rsvd534[2]; @@ -337,9 +346,10 @@ struct nvme_id_ctrl { __le32 ioccsz; __le32 iorcsz; __le16 icdoff; - __u8 ctrattr; + __u8 fcatt; __u8 msdbd; - __u8 rsvd1804[244]; + __le16 ofcs; + __u8 rsvd1806[242]; struct nvme_id_power_state psd[32]; __u8 vs[1024]; }; @@ -398,7 +408,10 @@ struct nvme_id_ns { __le16 npdg; __le16 npda; __le16 nows; - __u8 rsvd74[18]; + __le16 mssrl; + __le32 mcl; + __u8 msrc; + __u8 rsvd81[11]; __le32 anagrpid; __u8 rsvd96[3]; __u8 nsattr; @@ -411,19 +424,30 @@ struct nvme_id_ns { __u8 vs[3712]; }; +struct nvme_id_iocs { + __le64 iocs[512]; +}; + enum { NVME_ID_CNS_NS = 0x00, NVME_ID_CNS_CTRL = 0x01, NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, NVME_ID_CNS_NS_DESC_LIST = 0x03, NVME_ID_CNS_NVMSET_LIST = 0x04, + NVME_ID_CNS_CSI_ID_NS = 0x05, + NVME_ID_CNS_CSI_ID_CTRL = 0x06, + NVME_ID_CNS_CSI_NS_ACTIVE_LIST = 0x07, NVME_ID_CNS_NS_PRESENT_LIST = 0x10, NVME_ID_CNS_NS_PRESENT = 0x11, NVME_ID_CNS_CTRL_NS_LIST = 0x12, NVME_ID_CNS_CTRL_LIST = 0x13, + NVME_ID_CNS_PRIMARY_CTRL_CAPS = 0x14, NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15, NVME_ID_CNS_NS_GRANULARITY = 0x16, NVME_ID_CNS_UUID_LIST = 0x17, + NVME_ID_CNS_CSI_NS_PRESENT_LIST = 0x1a, + NVME_ID_CNS_CSI_NS_PRESENT = 0x1b, + NVME_ID_CNS_CSI = 0x1c, }; enum { @@ -468,11 +492,13 @@ struct nvme_ns_id_desc { #define NVME_NIDT_EUI64_LEN 8 #define NVME_NIDT_NGUID_LEN 16 #define NVME_NIDT_UUID_LEN 16 +#define NVME_NIDT_CSI_LEN 1 enum { NVME_NIDT_EUI64 = 0x01, NVME_NIDT_NGUID = 0x02, NVME_NIDT_UUID = 0x03, + NVME_NIDT_CSI = 0x04, }; #define NVME_MAX_NVMSET 31 @@ -627,12 +653,14 @@ enum { NVME_ST_VALID_SCT = 1 << 2, NVME_ST_VALID_SC = 1 << 3, NVME_ST_REPORTS = 20, + NVME_ST_LOG_ENTRY_SIZE = 28, + NVME_ST_LOG_HEAD_SIZE = 4, }; struct nvme_self_test_log { __u8 crnt_dev_selftest_oprn; __u8 crnt_dev_selftest_compln; - __u8 rsvd[2]; + __u8 rsvd2[2]; struct nvme_self_test_res result[20]; } __attribute__((packed)); @@ -714,6 +742,209 @@ struct nvme_ana_rsp_hdr { __le16 rsvd10[3]; }; +/* persistent event type 02h */ +struct nvme_fw_commit_event { + __le64 old_fw_rev; + __le64 new_fw_rev; + __u8 fw_commit_action; + __u8 fw_slot; + __u8 sct_fw; + __u8 sc_fw; + __le16 vndr_assign_fw_commit_rc; +} __attribute__((packed)); + +/* persistent event type 03h */ +struct nvme_time_stamp_change_event { + __le64 previous_timestamp; + __le64 ml_secs_since_reset; +}; + +/* persistent event type 04h */ +struct nvme_power_on_reset_info_list { + __le16 cid; + __u8 fw_act; + __u8 op_in_prog; + __u8 rsvd4[12]; + __le32 ctrl_power_cycle; + __le64 power_on_ml_seconds; + __le64 ctrl_time_stamp; +} __attribute__((packed)); + +/* persistent event type 05h */ +struct nvme_nss_hw_err_event { + __le16 nss_hw_err_event_code; + __u8 rsvd2[2]; + __u8 *add_hw_err_info; +}; + +/* persistent event type 06h */ +struct nvme_change_ns_event { + __le32 nsmgt_cdw10; + __u8 rsvd4[4]; + __le64 nsze; + __u8 rsvd16[8]; + __le64 nscap; + __u8 flbas; + __u8 dps; + __u8 nmic; + __u8 rsvd35; + __le32 ana_grp_id; + __le16 nvmset_id; + __le16 rsvd42; + __le32 nsid; +}; + +/* persistent event type 07h */ +struct nvme_format_nvm_start_event { + __le32 nsid; + __u8 fna; + __u8 rsvd5[3]; + __le32 format_nvm_cdw10; +}; + +/* persistent event type 08h */ +struct nvme_format_nvm_compln_event { + __le32 nsid; + __u8 smallest_fpi; + __u8 format_nvm_status; + __le16 compln_info; + __le32 status_field; +}; + +/* persistent event type 09h */ +struct nvme_sanitize_start_event { + __le32 sani_cap; + __le32 sani_cdw10; + __le32 sani_cdw11; +}; + +/* persistent event type 0Ah */ +struct nvme_sanitize_compln_event { + __le16 sani_prog; + __le16 sani_status; + __le16 cmpln_info; + __u8 rsvd6[2]; +}; + +/* persistent event type 0Dh */ +struct nvme_thermal_exc_event { + __u8 over_temp; + __u8 threshold; +}; + +/* persistent event entry head */ +struct nvme_persistent_event_entry_head { + __u8 etype; + __u8 etype_rev; + __u8 ehl; + __u8 rsvd3; + __le16 ctrl_id; + __le64 etimestamp; + __u8 rsvd14[6]; + __le16 vsil; + __le16 el; +} __attribute__((packed)); + +/* persistent event log head */ +struct nvme_persistent_event_log_head { + __u8 log_id; + __u8 rsvd1[3]; + __le32 tnev; + __le64 tll; + __u8 log_rev; + __u8 rsvd17; + __le16 head_len; + __le64 timestamp; + __u8 poh[16]; + __le64 pcc; + __le16 vid; + __le16 ssvid; + __u8 sn[20]; + __u8 mn[40]; + __u8 subnqn[256]; + __u8 rsvd372[108]; + __u8 supp_event_bm[32]; +} __attribute__((packed)); + +enum nvme_persistent_event_types { + NVME_SMART_HEALTH_EVENT = 0x01, + NVME_FW_COMMIT_EVENT = 0x02, + NVME_TIMESTAMP_EVENT = 0x03, + NVME_POWER_ON_RESET_EVENT = 0x04, + NVME_NSS_HW_ERROR_EVENT = 0x05, + NVME_CHANGE_NS_EVENT = 0x06, + NVME_FORMAT_START_EVENT = 0x07, + NVME_FORMAT_COMPLETION_EVENT = 0x08, + NVME_SANITIZE_START_EVENT = 0x09, + NVME_SANITIZE_COMPLETION_EVENT = 0x0a, + NVME_THERMAL_EXCURSION_EVENT = 0x0d +}; + +enum nvme_persistent_event_log_actions { + NVME_PEVENT_LOG_READ = 0x0, + NVME_PEVENT_LOG_EST_CTX_AND_READ = 0x1, + NVME_PEVENT_LOG_RELEASE_CTX = 0x2, +}; + +/** + * struct nvme_event_agg_log_page - is common for both + * predictable latency event aggregate log and endurance + * group event aggregate log + * @num_entries: indicates the number of entries in the list. + * @entries: indicates NVMSET ID or ENDURANCE Group ID entries + */ +struct nvme_event_agg_log_page { + __le64 num_entries; + __le16 entries[]; +}; + +struct nvme_predlat_per_nvmset_log_page { + __u8 status; + __u8 rsvd1; + __le16 event_type; + __u8 rsvd4[28]; + __le64 dtwin_rtyp; + __le64 dtwin_wtyp; + __le64 dtwin_timemax; + __le64 ndwin_timemin_high; + __le64 ndwin_timemin_low; + __u8 rsvd72[56]; + __le64 dtwin_restimate; + __le64 dtwin_westimate; + __le64 dtwin_testimate; + __u8 rsvd152[360]; +}; + +struct nvme_lba_status_range_desc { + __le64 rslba; + __le32 rnlb; + __u8 rsvd12[4]; +}; + +struct nvme_lba_status_ns_element { + __le32 neid; + __le32 nlrd; + __u8 ratype; + __u8 rsvd9[7]; +}; + +struct nvme_lba_status_hdr { + __le32 lslplen; + __le32 nlslne; + __le32 estulb; + __u8 rsvd12[2]; + __le16 lsgc; +}; + +struct nvme_resv_notif_log { + __le64 log_page_count; + __u8 resv_notif_log_type; + __u8 num_logs; + __u8 rsvd10[2]; + __le32 nsid; + __u8 rsvd16[48]; +}; + enum { NVME_SMART_CRIT_SPARE = 1 << 0, NVME_SMART_CRIT_TEMPERATURE = 1 << 1, @@ -814,6 +1045,10 @@ enum nvme_opcode { nvme_cmd_resv_report = 0x0e, nvme_cmd_resv_acquire = 0x11, nvme_cmd_resv_release = 0x15, + nvme_cmd_copy = 0x19, + nvme_zns_cmd_mgmt_send = 0x79, + nvme_zns_cmd_mgmt_recv = 0x7a, + nvme_zns_cmd_append = 0x7d, }; /* @@ -919,6 +1154,7 @@ enum { NVME_RW_DSM_LATENCY_LOW = 3 << 4, NVME_RW_DSM_SEQ_REQ = 1 << 6, NVME_RW_DSM_COMPRESSED = 1 << 7, + NVME_RW_PIREMAP = 1 << 9, NVME_RW_PRINFO_PRCHK_REF = 1 << 10, NVME_RW_PRINFO_PRCHK_APP = 1 << 11, NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, @@ -940,6 +1176,16 @@ struct nvme_dsm_range { __le64 slba; }; +struct nvme_copy_range { + __u8 rsvd0[8]; + __le64 slba; + __le16 nlb; + __u8 rsvd18[6]; + __le32 eilbrt; + __le16 elbatm; + __le16 elbat; +}; + /* Features */ struct nvme_feat_auto_pst { __le64 entries[32]; @@ -989,6 +1235,32 @@ enum { NVME_SQ_PRIO_HIGH = (1 << 1), NVME_SQ_PRIO_MEDIUM = (2 << 1), NVME_SQ_PRIO_LOW = (3 << 1), + NVME_LOG_ERROR = 0x01, + NVME_LOG_SMART = 0x02, + NVME_LOG_FW_SLOT = 0x03, + NVME_LOG_CHANGED_NS = 0x04, + NVME_LOG_CMD_EFFECTS = 0x05, + NVME_LOG_DEVICE_SELF_TEST = 0x06, + NVME_LOG_TELEMETRY_HOST = 0x07, + NVME_LOG_TELEMETRY_CTRL = 0x08, + NVME_LOG_ENDURANCE_GROUP = 0x09, + NVME_LOG_PRELAT_PER_NVMSET = 0x0a, + NVME_LOG_ANA = 0x0c, + NVME_LOG_PRELAT_EVENT_AGG = 0x0b, + NVME_LOG_PERSISTENT_EVENT = 0x0d, + NVME_LOG_LBA_STATUS = 0x0e, + NVME_LOG_ENDURANCE_GROUP_EVENT_AGG = 0x0f, + NVME_LOG_DISC = 0x70, + NVME_LOG_RESERVATION = 0x80, + NVME_LOG_SANITIZE = 0x81, + NVME_LOG_ZONE_CHANGED_LIST = 0xbf, + NVME_FWACT_REPL = (0 << 3), + NVME_FWACT_REPL_ACTV = (1 << 3), + NVME_FWACT_ACTV = (2 << 3), +}; + +enum nvme_feat { + NVME_FEAT_NONE = 0x0, NVME_FEAT_ARBITRATION = 0x01, NVME_FEAT_POWER_MGMT = 0x02, NVME_FEAT_LBA_RANGE = 0x03, @@ -1009,30 +1281,17 @@ enum { NVME_FEAT_RRL = 0x12, NVME_FEAT_PLM_CONFIG = 0x13, NVME_FEAT_PLM_WINDOW = 0x14, + NVME_LBA_STATUS_INFO = 0x15, NVME_FEAT_HOST_BEHAVIOR = 0x16, NVME_FEAT_SANITIZE = 0x17, + NVME_FEAT_ENDURANCE = 0x18, + NVME_FEAT_IOCS_PROFILE = 0x19, NVME_FEAT_SW_PROGRESS = 0x80, NVME_FEAT_HOST_ID = 0x81, NVME_FEAT_RESV_MASK = 0x82, NVME_FEAT_RESV_PERSIST = 0x83, NVME_FEAT_WRITE_PROTECT = 0x84, - NVME_LOG_ERROR = 0x01, - NVME_LOG_SMART = 0x02, - NVME_LOG_FW_SLOT = 0x03, - NVME_LOG_CHANGED_NS = 0x04, - NVME_LOG_CMD_EFFECTS = 0x05, - NVME_LOG_DEVICE_SELF_TEST = 0x06, - NVME_LOG_TELEMETRY_HOST = 0x07, - NVME_LOG_TELEMETRY_CTRL = 0x08, - NVME_LOG_ENDURANCE_GROUP = 0x09, - NVME_LOG_ANA = 0x0c, - NVME_LOG_DISC = 0x70, - NVME_LOG_RESERVATION = 0x80, - NVME_LOG_SANITIZE = 0x81, - NVME_FWACT_REPL = (0 << 3), - NVME_FWACT_REPL_ACTV = (1 << 3), - NVME_FWACT_ACTV = (2 << 3), -}; +} __attribute__ ((__packed__)); enum { NVME_NO_LOG_LSP = 0x0, @@ -1084,6 +1343,7 @@ struct nvme_sanitize_log_page { __le32 est_ovrwrt_time_with_no_deallocate; __le32 est_blk_erase_time_with_no_deallocate; __le32 est_crypto_erase_time_with_no_deallocate; + __u8 rsvd32[480]; }; /* @@ -1224,6 +1484,27 @@ struct nvme_controller_list { __le16 identifier[2047]; }; +struct nvme_primary_ctrl_caps { + __le16 cntlid; /* Controller Identifier */ + __le16 portid; /* Port Identifier */ + __u8 crt; /* Controller Resource Types */ + __u8 rsvd5[27]; + __le32 vqfrt; /* VQ Resources Flexible Total */ + __le32 vqrfa; /* VQ Resources Flexible Assigned */ + __le16 vqrfap; /* VQ Resources Flexible Allocated to Primary */ + __le16 vqprt; /* VQ Resources Private Total */ + __le16 vqfrsm; /* VQ Resources Flexible Secondary Maximum */ + __le16 vqgran; /* VQ Flexible Resource Preferred Granularity */ + __u8 rsvd48[16]; + __le32 vifrt; /* VI Resources Flexible Total */ + __le32 virfa; /* VI Resources Flexible Assigned */ + __u16 virfap; /* VI Resources Flexible Allocated to Primary */ + __u16 viprt; /* VI Resources Private Total */ + __u16 vifrsm; /* VI Resources Flexible Secondary Maximum */ + __u16 vigran; /* VI Flexible Resource Preferred Granularity */ + __u8 rsvd80[4016]; +}; + struct nvme_secondary_controller_entry { __le16 scid; /* Secondary Controller Identifier */ __le16 pcid; /* Primary Controller Identifier */ @@ -1277,6 +1558,7 @@ enum { NVME_SCT_GENERIC = 0x0, NVME_SCT_CMD_SPECIFIC = 0x1, NVME_SCT_MEDIA = 0x2, + NVME_SCT_PATH = 0x3, }; enum { @@ -1316,7 +1598,7 @@ enum { NVME_SC_NS_WRITE_PROTECTED = 0x20, NVME_SC_CMD_INTERRUPTED = 0x21, - NVME_SC_TRANSIENT_TRANSPORT = 0x22, + NVME_SC_TRANSIENT_TRANSPORT = 0x22, NVME_SC_LBA_RANGE = 0x80, NVME_SC_CAP_EXCEEDED = 0x81, @@ -1366,12 +1648,20 @@ enum { NVME_SC_ANA_ATTACH_FAIL = 0x125, /* + * Command Set Specific - Namespace Types commands: + */ + NVME_SC_IOCS_NOT_SUPPORTED = 0x129, + NVME_SC_IOCS_NOT_ENABLED = 0x12A, + NVME_SC_IOCS_COMBINATION_REJECTED = 0x12B, + NVME_SC_INVALID_IOCS = 0x12C, + + /* * I/O Command Set Specific - NVM commands: */ NVME_SC_BAD_ATTRIBUTES = 0x180, NVME_SC_INVALID_PI = 0x181, NVME_SC_READ_ONLY = 0x182, - NVME_SC_ONCS_NOT_SUPPORTED = 0x183, + NVME_SC_CMD_SIZE_LIMIT_EXCEEDED = 0x183, /* * I/O Command Set Specific - Fabrics commands: @@ -1386,6 +1676,18 @@ enum { NVME_SC_AUTH_REQUIRED = 0x191, /* + * I/O Command Set Specific - Zoned Namespace commands: + */ + NVME_SC_ZONE_BOUNDARY_ERROR = 0x1B8, + NVME_SC_ZONE_IS_FULL = 0x1B9, + NVME_SC_ZONE_IS_READ_ONLY = 0x1BA, + NVME_SC_ZONE_IS_OFFLINE = 0x1BB, + NVME_SC_ZONE_INVALID_WRITE = 0x1BC, + NVME_SC_TOO_MANY_ACTIVE_ZONES = 0x1BD, + NVME_SC_TOO_MANY_OPEN_ZONES = 0x1BE, + NVME_SC_ZONE_INVALID_STATE_TRANSITION = 0x1BF, + + /* * Media and Data Integrity Errors: */ NVME_SC_WRITE_FAULT = 0x280, @@ -1400,10 +1702,22 @@ enum { /* * Path-related Errors: */ + NVME_SC_INTERNAL_PATH_ERROR = 0x300, NVME_SC_ANA_PERSISTENT_LOSS = 0x301, NVME_SC_ANA_INACCESSIBLE = 0x302, NVME_SC_ANA_TRANSITION = 0x303, + /* + * Controller Detected Path errors + */ + NVME_SC_CTRL_PATHING_ERROR = 0x360, + + /* + * Host Detected Path Errors + */ + NVME_SC_HOST_PATHING_ERROR = 0x370, + NVME_SC_HOST_CMD_ABORT = 0x371, + NVME_SC_CRD = 0x1800, NVME_SC_DNR = 0x4000, }; @@ -1415,4 +1729,149 @@ enum { #define NVME_MINOR(ver) (((ver) >> 8) & 0xff) #define NVME_TERTIARY(ver) ((ver) & 0xff) + +/** + * struct nvme_zns_lbafe - + * zsze: + * zdes: + */ +struct nvme_zns_lbafe { + __le64 zsze; + __u8 zdes; + __u8 rsvd9[7]; +}; + +/** + * struct nvme_zns_id_ns - + * @zoc: + * @ozcs: + * @mar: + * @mor: + * @rrl: + * @frl: + * @lbafe: + * @vs: + */ +struct nvme_zns_id_ns { + __le16 zoc; + __le16 ozcs; + __le32 mar; + __le32 mor; + __le32 rrl; + __le32 frl; + __u8 rsvd20[2796]; + struct nvme_zns_lbafe lbafe[16]; + __u8 rsvd3072[768]; + __u8 vs[256]; +}; + +struct nvme_id_ctrl_nvm { + __u8 vsl; + __u8 wzsl; + __u8 wusl; + __u8 dmrl; + __u32 dmrsl; + __u64 dmsl; + __u8 rsvd16[4080]; +}; + +/** + * struct nvme_zns_id_ctrl - + * @zasl: + */ +struct nvme_zns_id_ctrl { + __u8 zasl; + __u8 rsvd1[4095]; +}; + +#define NVME_ZNS_CHANGED_ZONES_MAX 511 + +/** + * struct nvme_zns_changed_zone_log - ZNS Changed Zone List log + * @nrzid: + * @zid: + */ +struct nvme_zns_changed_zone_log { + __le16 nrzid; + __u8 rsvd2[6]; + __le64 zid[NVME_ZNS_CHANGED_ZONES_MAX]; +}; + +/** + * enum nvme_zns_zt - + */ +enum nvme_zns_zt { + NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2, +}; + +/** + * enum nvme_zns_za - + */ +enum nvme_zns_za { + NVME_ZNS_ZA_ZFC = 1 << 0, + NVME_ZNS_ZA_FZR = 1 << 1, + NVME_ZNS_ZA_RZR = 1 << 2, + NVME_ZNS_ZA_ZDEV = 1 << 7, +}; + +/** + * enum nvme_zns_zs - + */ +enum nvme_zns_zs { + NVME_ZNS_ZS_EMPTY = 0x1, + NVME_ZNS_ZS_IMPL_OPEN = 0x2, + NVME_ZNS_ZS_EXPL_OPEN = 0x3, + NVME_ZNS_ZS_CLOSED = 0x4, + NVME_ZNS_ZS_READ_ONLY = 0xd, + NVME_ZNS_ZS_FULL = 0xe, + NVME_ZNS_ZS_OFFLINE = 0xf, +}; + +/** + * struct nvme_zns_desc - + */ +struct nvme_zns_desc { + __u8 zt; + __u8 zs; + __u8 za; + __u8 rsvd3[5]; + __le64 zcap; + __le64 zslba; + __le64 wp; + __u8 rsvd32[32]; +}; + +/** + * struct nvme_zone_report - + */ +struct nvme_zone_report { + __le64 nr_zones; + __u8 resv8[56]; + struct nvme_zns_desc entries[]; +}; + +enum nvme_zns_send_action { + NVME_ZNS_ZSA_CLOSE = 0x1, + NVME_ZNS_ZSA_FINISH = 0x2, + NVME_ZNS_ZSA_OPEN = 0x3, + NVME_ZNS_ZSA_RESET = 0x4, + NVME_ZNS_ZSA_OFFLINE = 0x5, + NVME_ZNS_ZSA_SET_DESC_EXT = 0x10, +}; + +enum nvme_zns_recv_action { + NVME_ZNS_ZRA_REPORT_ZONES = 0x0, + NVME_ZNS_ZRA_EXTENDED_REPORT_ZONES = 0x1, +}; + +enum nvme_zns_report_options { + NVME_ZNS_ZRAS_REPORT_ALL = 0x0, + NVME_ZNS_ZRAS_REPORT_EMPTY = 0x1, + NVME_ZNS_ZRAS_REPORT_IMPL_OPENED = 0x2, + NVME_ZNS_ZRAS_REPORT_EXPL_OPENED = 0x3, + NVME_ZNS_ZRAS_REPORT_CLOSED = 0x4, + NVME_ZNS_ZRAS_REPORT_FULL = 0x5, + NVME_ZNS_ZRAS_REPORT_READ_ONLY = 0x6, + NVME_ZNS_ZRAS_REPORT_OFFLINE = 0x7, +}; #endif /* _LINUX_NVME_H */ |