summaryrefslogtreecommitdiffstats
path: root/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
diff options
context:
space:
mode:
authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-05-18 18:50:36 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-05-18 18:50:36 +0000
commit50ba0232fd5312410f1b65247e774244f89a628e (patch)
treefd8f2fc78e9e548af0ff9590276602ee6125be00 /arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
parentReleasing progress-linux version 6.7.12-1~progress7.99u1. (diff)
downloadlinux-50ba0232fd5312410f1b65247e774244f89a628e.tar.xz
linux-50ba0232fd5312410f1b65247e774244f89a628e.zip
Merging upstream version 6.8.9.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-am62a7-sk.dts')
-rw-r--r--arch/arm64/boot/dts/ti/k3-am62a7-sk.dts39
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
index 8f64ac2c75..7b71425862 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
@@ -274,6 +274,12 @@
AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */
>;
};
+
+ main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */
+ >;
+ };
};
&mcu_pmx0 {
@@ -407,6 +413,12 @@
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
+ interrupt-parent = <&main_gpio1>;
+ interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
"BT_EN_SOC", "MMC1_SD_EN",
@@ -434,6 +446,33 @@
DRVDD-supply = <&vcc_3v3_sys>;
DVDD-supply = <&buck5>;
};
+
+ exp2: gpio@23 {
+ compatible = "ti,tca6424";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names = "", "",
+ "", "",
+ "", "",
+ "", "",
+ "WL_LT_EN", "CSI_RSTz",
+ "", "",
+ "", "",
+ "", "",
+ "SPI0_FET_SEL", "SPI0_FET_OE",
+ "RGMII2_BRD_CONN_DET", "CSI_SEL2",
+ "CSI_EN", "AUTO_100M_1000M_CONFIG",
+ "CSI_VLDO_SEL", "SoC_WLAN_SDIO_RST";
+ };
+};
+
+&main_i2c2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c2_pins_default>;
+ clock-frequency = <400000>;
};
&sdhci1 {