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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-28 09:13:47 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-28 09:13:47 +0000
commit102b0d2daa97dae68d3eed54d8fe37a9cc38a892 (patch)
treebcf648efac40ca6139842707f0eba5a4496a6dd2 /include/drivers
parentInitial commit. (diff)
downloadarm-trusted-firmware-upstream.tar.xz
arm-trusted-firmware-upstream.zip
Adding upstream version 2.8.0+dfsg.upstream/2.8.0+dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'include/drivers')
-rw-r--r--include/drivers/allwinner/axp.h59
-rw-r--r--include/drivers/allwinner/sunxi_rsb.h20
-rw-r--r--include/drivers/amlogic/crypto/sha_dma.h36
-rw-r--r--include/drivers/amlogic/meson_console.h30
-rw-r--r--include/drivers/arm/arm_gicv3_common.h28
-rw-r--r--include/drivers/arm/cci.h125
-rw-r--r--include/drivers/arm/ccn.h113
-rw-r--r--include/drivers/arm/cryptocell/712/cc_crypto_boot_defs.h34
-rw-r--r--include/drivers/arm/cryptocell/712/cc_pal_sb_plat.h33
-rw-r--r--include/drivers/arm/cryptocell/712/cc_pal_types.h40
-rw-r--r--include/drivers/arm/cryptocell/712/cc_pal_types_plat.h25
-rw-r--r--include/drivers/arm/cryptocell/712/cc_sec_defs.h34
-rw-r--r--include/drivers/arm/cryptocell/712/crypto_driver.h35
-rw-r--r--include/drivers/arm/cryptocell/712/nvm.h55
-rw-r--r--include/drivers/arm/cryptocell/712/nvm_otp.h59
-rw-r--r--include/drivers/arm/cryptocell/712/rsa.h57
-rw-r--r--include/drivers/arm/cryptocell/712/sbrom_bsv_api.h72
-rw-r--r--include/drivers/arm/cryptocell/712/secureboot_base_func.h49
-rw-r--r--include/drivers/arm/cryptocell/712/secureboot_gen_defs.h66
-rw-r--r--include/drivers/arm/cryptocell/712/util.h72
-rw-r--r--include/drivers/arm/cryptocell/713/bsv_api.h221
-rw-r--r--include/drivers/arm/cryptocell/713/bsv_crypto_api.h76
-rw-r--r--include/drivers/arm/cryptocell/713/bsv_crypto_asym_api.h100
-rw-r--r--include/drivers/arm/cryptocell/713/bsv_crypto_defs.h94
-rw-r--r--include/drivers/arm/cryptocell/713/bsv_error.h161
-rw-r--r--include/drivers/arm/cryptocell/713/cc_address_defs.h50
-rw-r--r--include/drivers/arm/cryptocell/713/cc_boot_defs.h52
-rw-r--r--include/drivers/arm/cryptocell/713/cc_pal_types.h100
-rw-r--r--include/drivers/arm/cryptocell/713/cc_pal_types_plat.h25
-rw-r--r--include/drivers/arm/cryptocell/713/cc_pka_hw_plat_defs.h62
-rw-r--r--include/drivers/arm/cryptocell/713/cc_sec_defs.h70
-rw-r--r--include/drivers/arm/cryptocell/cc_rotpk.h13
-rw-r--r--include/drivers/arm/css/css_mhu.h19
-rw-r--r--include/drivers/arm/css/css_mhu_doorbell.h44
-rw-r--r--include/drivers/arm/css/css_scp.h52
-rw-r--r--include/drivers/arm/css/css_scpi.h109
-rw-r--r--include/drivers/arm/css/scmi.h176
-rw-r--r--include/drivers/arm/css/sds.h90
-rw-r--r--include/drivers/arm/dcc.h19
-rw-r--r--include/drivers/arm/ethosn.h62
-rw-r--r--include/drivers/arm/fvp/fvp_pwrc.h55
-rw-r--r--include/drivers/arm/gic600_multichip.h55
-rw-r--r--include/drivers/arm/gic600ae_fmu.h157
-rw-r--r--include/drivers/arm/gic_common.h99
-rw-r--r--include/drivers/arm/gicv2.h200
-rw-r--r--include/drivers/arm/gicv3.h605
-rw-r--r--include/drivers/arm/mhu.h86
-rw-r--r--include/drivers/arm/nic_400.h16
-rw-r--r--include/drivers/arm/pl011.h99
-rw-r--r--include/drivers/arm/pl061_gpio.h15
-rw-r--r--include/drivers/arm/rss_comms.h15
-rw-r--r--include/drivers/arm/sbsa.h24
-rw-r--r--include/drivers/arm/scu.h20
-rw-r--r--include/drivers/arm/smmu_v3.h71
-rw-r--r--include/drivers/arm/sp804_delay_timer.h28
-rw-r--r--include/drivers/arm/sp805.h36
-rw-r--r--include/drivers/arm/tzc380.h164
-rw-r--r--include/drivers/arm/tzc400.h160
-rw-r--r--include/drivers/arm/tzc_common.h89
-rw-r--r--include/drivers/arm/tzc_dmc500.h151
-rw-r--r--include/drivers/arm/tzc_dmc620.h104
-rw-r--r--include/drivers/auth/auth_common.h120
-rw-r--r--include/drivers/auth/auth_mod.h92
-rw-r--r--include/drivers/auth/crypto_mod.h155
-rw-r--r--include/drivers/auth/img_parser_mod.h64
-rw-r--r--include/drivers/auth/mbedtls/mbedtls_common.h12
-rw-r--r--include/drivers/auth/mbedtls/mbedtls_config.h152
-rw-r--r--include/drivers/auth/tbbr_cot_common.h29
-rw-r--r--include/drivers/brcm/chimp.h94
-rw-r--r--include/drivers/brcm/chimp_nv_defs.h419
-rw-r--r--include/drivers/brcm/dmu.h35
-rw-r--r--include/drivers/brcm/emmc/bcm_emmc.h104
-rw-r--r--include/drivers/brcm/emmc/emmc_api.h47
-rw-r--r--include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h1116
-rw-r--r--include/drivers/brcm/emmc/emmc_chal_sd.h202
-rw-r--r--include/drivers/brcm/emmc/emmc_chal_types.h20
-rw-r--r--include/drivers/brcm/emmc/emmc_csl_sd.h96
-rw-r--r--include/drivers/brcm/emmc/emmc_csl_sdcmd.h168
-rw-r--r--include/drivers/brcm/emmc/emmc_csl_sdprot.h435
-rw-r--r--include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h94
-rw-r--r--include/drivers/brcm/fru.h144
-rw-r--r--include/drivers/brcm/i2c/i2c.h161
-rw-r--r--include/drivers/brcm/i2c/i2c_regs.h271
-rw-r--r--include/drivers/brcm/iproc_gpio.h20
-rw-r--r--include/drivers/brcm/mdio/mdio.h31
-rw-r--r--include/drivers/brcm/ocotp.h27
-rw-r--r--include/drivers/brcm/scp.h14
-rw-r--r--include/drivers/brcm/sf.h90
-rw-r--r--include/drivers/brcm/sotp.h71
-rw-r--r--include/drivers/brcm/spi.h21
-rw-r--r--include/drivers/brcm/spi_flash.h18
-rw-r--r--include/drivers/brcm/usbh_xhci_regs.h4809
-rw-r--r--include/drivers/cadence/cdns_uart.h44
-rw-r--r--include/drivers/cfi/v2m_flash.h45
-rw-r--r--include/drivers/clk.h28
-rw-r--r--include/drivers/console.h83
-rw-r--r--include/drivers/console_assertions.h29
-rw-r--r--include/drivers/coreboot/cbmem_console.h25
-rw-r--r--include/drivers/delay_timer.h53
-rw-r--r--include/drivers/dw_ufs.h110
-rw-r--r--include/drivers/fwu/fwu.h16
-rw-r--r--include/drivers/fwu/fwu_metadata.h74
-rw-r--r--include/drivers/generic_delay_timer.h16
-rw-r--r--include/drivers/gpio.h40
-rw-r--r--include/drivers/io/io_block.h28
-rw-r--r--include/drivers/io/io_driver.h59
-rw-r--r--include/drivers/io/io_dummy.h12
-rw-r--r--include/drivers/io/io_encrypted.h15
-rw-r--r--include/drivers/io/io_fip.h15
-rw-r--r--include/drivers/io/io_memmap.h14
-rw-r--r--include/drivers/io/io_mtd.h70
-rw-r--r--include/drivers/io/io_semihosting.h14
-rw-r--r--include/drivers/io/io_storage.h103
-rw-r--r--include/drivers/marvell/addr_map.h21
-rw-r--r--include/drivers/marvell/amb_adec.h36
-rw-r--r--include/drivers/marvell/ap807_clocks_init.h14
-rw-r--r--include/drivers/marvell/aro.h49
-rw-r--r--include/drivers/marvell/cache_llc.h62
-rw-r--r--include/drivers/marvell/ccu.h53
-rw-r--r--include/drivers/marvell/gwin.h19
-rw-r--r--include/drivers/marvell/i2c.h20
-rw-r--r--include/drivers/marvell/io_win.h21
-rw-r--r--include/drivers/marvell/iob.h31
-rw-r--r--include/drivers/marvell/mci.h18
-rw-r--r--include/drivers/marvell/mochi/ap_setup.h18
-rw-r--r--include/drivers/marvell/mochi/cp110_setup.h66
-rw-r--r--include/drivers/marvell/thermal.h31
-rw-r--r--include/drivers/marvell/uart/a3700_console.h74
-rw-r--r--include/drivers/measured_boot/event_log/event_log.h127
-rw-r--r--include/drivers/measured_boot/event_log/tcg.h309
-rw-r--r--include/drivers/measured_boot/rss/rss_measured_boot.h55
-rw-r--r--include/drivers/mentor/mi2cv.h40
-rw-r--r--include/drivers/mmc.h272
-rw-r--r--include/drivers/nand.h67
-rw-r--r--include/drivers/nxp/auth/csf_hdr_parser/csf_hdr.h155
-rw-r--r--include/drivers/nxp/console/plat_console.h38
-rw-r--r--include/drivers/nxp/crypto/caam/caam.h53
-rw-r--r--include/drivers/nxp/crypto/caam/caam_io.h56
-rw-r--r--include/drivers/nxp/crypto/caam/hash.h85
-rw-r--r--include/drivers/nxp/crypto/caam/jobdesc.h56
-rw-r--r--include/drivers/nxp/crypto/caam/jr_driver_config.h205
-rw-r--r--include/drivers/nxp/crypto/caam/rsa.h40
-rw-r--r--include/drivers/nxp/crypto/caam/sec_hw_specific.h503
-rw-r--r--include/drivers/nxp/crypto/caam/sec_jr_driver.h178
-rw-r--r--include/drivers/nxp/csu/csu.h42
-rw-r--r--include/drivers/nxp/dcfg/dcfg.h103
-rw-r--r--include/drivers/nxp/dcfg/dcfg_lsch2.h85
-rw-r--r--include/drivers/nxp/dcfg/dcfg_lsch3.h80
-rw-r--r--include/drivers/nxp/dcfg/scfg.h65
-rw-r--r--include/drivers/nxp/ddr/ddr.h151
-rw-r--r--include/drivers/nxp/ddr/ddr_io.h38
-rw-r--r--include/drivers/nxp/ddr/dimm.h330
-rw-r--r--include/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.h173
-rw-r--r--include/drivers/nxp/ddr/immap.h125
-rw-r--r--include/drivers/nxp/ddr/opts.h119
-rw-r--r--include/drivers/nxp/ddr/regs.h109
-rw-r--r--include/drivers/nxp/ddr/utility.h24
-rw-r--r--include/drivers/nxp/flexspi/flash_info.h89
-rw-r--r--include/drivers/nxp/flexspi/fspi_api.h122
-rw-r--r--include/drivers/nxp/flexspi/xspi_error_codes.h28
-rw-r--r--include/drivers/nxp/gic/gicv2/plat_gic.h72
-rw-r--r--include/drivers/nxp/gic/gicv3/plat_gic.h120
-rw-r--r--include/drivers/nxp/gpio/nxp_gpio.h53
-rw-r--r--include/drivers/nxp/i2c/i2c.h52
-rw-r--r--include/drivers/nxp/ifc/ifc_nand.h19
-rw-r--r--include/drivers/nxp/ifc/ifc_nor.h14
-rw-r--r--include/drivers/nxp/interconnect/ls_interconnect.h19
-rw-r--r--include/drivers/nxp/pmu/pmu.h75
-rw-r--r--include/drivers/nxp/qspi/qspi.h30
-rw-r--r--include/drivers/nxp/sd/sd_mmc.h337
-rw-r--r--include/drivers/nxp/sec_mon/snvs.h86
-rw-r--r--include/drivers/nxp/sfp/fuse_prov.h83
-rw-r--r--include/drivers/nxp/sfp/sfp.h100
-rw-r--r--include/drivers/nxp/sfp/sfp_error_codes.h40
-rw-r--r--include/drivers/nxp/smmu/nxp_smmu.h30
-rw-r--r--include/drivers/nxp/timer/nxp_timer.h35
-rw-r--r--include/drivers/nxp/tzc/plat_tzc380.h47
-rw-r--r--include/drivers/nxp/tzc/plat_tzc400.h55
-rw-r--r--include/drivers/partition/efi.h37
-rw-r--r--include/drivers/partition/gpt.h52
-rw-r--r--include/drivers/partition/mbr.h29
-rw-r--r--include/drivers/partition/partition.h54
-rw-r--r--include/drivers/rambus/trng_ip_76.h18
-rw-r--r--include/drivers/raw_nand.h188
-rw-r--r--include/drivers/renesas/rcar/console/console.h25
-rw-r--r--include/drivers/rpi3/gpio/rpi3_gpio.h34
-rw-r--r--include/drivers/rpi3/mailbox/rpi3_mbox.h39
-rw-r--r--include/drivers/rpi3/rng/rpi3_rng.h12
-rw-r--r--include/drivers/rpi3/sdhost/rpi3_sdhost.h123
-rw-r--r--include/drivers/scmi-msg.h207
-rw-r--r--include/drivers/scmi.h29
-rw-r--r--include/drivers/spi_mem.h130
-rw-r--r--include/drivers/spi_nand.h49
-rw-r--r--include/drivers/spi_nor.h58
-rw-r--r--include/drivers/st/bsec.h129
-rw-r--r--include/drivers/st/bsec2_reg.h106
-rw-r--r--include/drivers/st/etzpc.h38
-rw-r--r--include/drivers/st/io_mmc.h18
-rw-r--r--include/drivers/st/regulator.h108
-rw-r--r--include/drivers/st/regulator_fixed.h12
-rw-r--r--include/drivers/st/stm32_console.h27
-rw-r--r--include/drivers/st/stm32_fmc2_nand.h12
-rw-r--r--include/drivers/st/stm32_gpio.h63
-rw-r--r--include/drivers/st/stm32_hash.h32
-rw-r--r--include/drivers/st/stm32_i2c.h321
-rw-r--r--include/drivers/st/stm32_iwdg.h19
-rw-r--r--include/drivers/st/stm32_pka.h46
-rw-r--r--include/drivers/st/stm32_qspi.h12
-rw-r--r--include/drivers/st/stm32_rng.h15
-rw-r--r--include/drivers/st/stm32_saes.h59
-rw-r--r--include/drivers/st/stm32_sdmmc2.h35
-rw-r--r--include/drivers/st/stm32_uart.h159
-rw-r--r--include/drivers/st/stm32_uart_regs.h199
-rw-r--r--include/drivers/st/stm32mp13_rcc.h1878
-rw-r--r--include/drivers/st/stm32mp15_rcc.h2328
-rw-r--r--include/drivers/st/stm32mp1_clk.h38
-rw-r--r--include/drivers/st/stm32mp1_ddr.h134
-rw-r--r--include/drivers/st/stm32mp1_ddr_helpers.h12
-rw-r--r--include/drivers/st/stm32mp1_ddr_regs.h196
-rw-r--r--include/drivers/st/stm32mp1_pwr.h32
-rw-r--r--include/drivers/st/stm32mp1_ram.h12
-rw-r--r--include/drivers/st/stm32mp1_rcc.h12
-rw-r--r--include/drivers/st/stm32mp1_usb.h16
-rw-r--r--include/drivers/st/stm32mp_clkfunc.h36
-rw-r--r--include/drivers/st/stm32mp_ddr.h69
-rw-r--r--include/drivers/st/stm32mp_ddr_test.h17
-rw-r--r--include/drivers/st/stm32mp_ddrctrl_regs.h265
-rw-r--r--include/drivers/st/stm32mp_pmic.h58
-rw-r--r--include/drivers/st/stm32mp_ram.h33
-rw-r--r--include/drivers/st/stm32mp_reset.h50
-rw-r--r--include/drivers/st/stpmic1.h198
-rw-r--r--include/drivers/synopsys/dw_mmc.h24
-rw-r--r--include/drivers/ti/uart/uart_16550.h94
-rw-r--r--include/drivers/ufs.h569
-rw-r--r--include/drivers/usb_device.h278
235 files changed, 29475 insertions, 0 deletions
diff --git a/include/drivers/allwinner/axp.h b/include/drivers/allwinner/axp.h
new file mode 100644
index 0000000..8b90c7f
--- /dev/null
+++ b/include/drivers/allwinner/axp.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AXP_H
+#define AXP_H
+
+#include <stdint.h>
+
+#define AXP20X_MODE_REG 0x3e
+#define AXP20X_MODE_I2C 0x00
+#define AXP20X_MODE_RSB 0x7c
+
+#define NA 0xff
+
+enum {
+ AXP803_CHIP_ID = 0x41,
+ AXP805_CHIP_ID = 0x40,
+};
+
+struct axp_regulator {
+ const char *dt_name;
+ uint16_t min_volt;
+ uint16_t max_volt;
+ uint16_t step;
+ unsigned char split;
+ unsigned char volt_reg;
+ unsigned char switch_reg;
+ unsigned char switch_bit;
+};
+
+extern const uint8_t axp_chip_id;
+extern const char *const axp_compatible;
+extern const struct axp_regulator axp_regulators[];
+
+/*
+ * Since the PMIC can be connected to multiple bus types,
+ * low-level read/write functions must be provided by the platform
+ */
+int axp_read(uint8_t reg);
+int axp_write(uint8_t reg, uint8_t val);
+int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask);
+#define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0)
+#define axp_setbits(reg, set_mask) axp_clrsetbits(reg, 0, set_mask)
+
+int axp_check_id(void);
+void axp_power_off(void);
+
+#if SUNXI_SETUP_REGULATORS == 1
+void axp_setup_regulators(const void *fdt);
+#else
+static inline void axp_setup_regulators(const void *fdt)
+{
+}
+#endif
+
+#endif /* AXP_H */
diff --git a/include/drivers/allwinner/sunxi_rsb.h b/include/drivers/allwinner/sunxi_rsb.h
new file mode 100644
index 0000000..3d003ce
--- /dev/null
+++ b/include/drivers/allwinner/sunxi_rsb.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_RSB_H
+#define SUNXI_RSB_H
+
+#include <stdint.h>
+
+int rsb_init_controller(void);
+int rsb_set_bus_speed(uint32_t source_freq, uint32_t bus_freq);
+int rsb_set_device_mode(uint32_t device_mode);
+int rsb_assign_runtime_address(uint16_t hw_addr, uint8_t rt_addr);
+
+int rsb_read(uint8_t rt_addr, uint8_t reg_addr);
+int rsb_write(uint8_t rt_addr, uint8_t reg_addr, uint8_t value);
+
+#endif /* SUNXI_RSB_H */
diff --git a/include/drivers/amlogic/crypto/sha_dma.h b/include/drivers/amlogic/crypto/sha_dma.h
new file mode 100644
index 0000000..52129a6
--- /dev/null
+++ b/include/drivers/amlogic/crypto/sha_dma.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2019, Remi Pommarel <repk@triplefau.lt>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef SHA_DMA_H
+#define SHA_DMA_H
+
+#define SHA256_HASHSZ 32
+#define SHA256_BLOCKSZ 0x40
+
+enum ASD_MODE {
+ ASM_INVAL,
+ ASM_SHA256,
+ ASM_SHA224,
+};
+
+struct asd_ctx {
+ uint8_t digest[SHA256_HASHSZ];
+ uint8_t block[SHA256_BLOCKSZ];
+ size_t blocksz;
+ enum ASD_MODE mode;
+ uint8_t started;
+};
+
+static inline void asd_sha_init(struct asd_ctx *ctx, enum ASD_MODE mode)
+{
+ ctx->started = 0;
+ ctx->mode = mode;
+ ctx->blocksz = 0;
+}
+
+void asd_sha_update(struct asd_ctx *ctx, void *data, size_t len);
+void asd_sha_finalize(struct asd_ctx *ctx);
+
+#endif
diff --git a/include/drivers/amlogic/meson_console.h b/include/drivers/amlogic/meson_console.h
new file mode 100644
index 0000000..8d52d79
--- /dev/null
+++ b/include/drivers/amlogic/meson_console.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MESON_CONSOLE_H
+#define MESON_CONSOLE_H
+
+#include <drivers/console.h>
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+/*
+ * Initialize a new meson console instance and register it with the console
+ * framework. The |console| pointer must point to storage that will be valid
+ * for the lifetime of the console, such as a global or static local variable.
+ * Its contents will be reinitialized from scratch.
+ *
+ * NOTE: The clock is actually fixed to 24 MHz. The argument is only there in
+ * order to make this function future-proof.
+ */
+int console_meson_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
+ console_t *console);
+
+#endif /*__ASSEMBLER__*/
+
+#endif /* MESON_CONSOLE_H */
diff --git a/include/drivers/arm/arm_gicv3_common.h b/include/drivers/arm/arm_gicv3_common.h
new file mode 100644
index 0000000..d1e93be
--- /dev/null
+++ b/include/drivers/arm/arm_gicv3_common.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef ARM_GICV3_COMMON_H
+#define ARM_GICV3_COMMON_H
+
+/*******************************************************************************
+ * GIC500/GIC600 Re-distributor interface registers & constants
+ ******************************************************************************/
+
+/* GICR_WAKER implementation-defined bit definitions */
+#define WAKER_SL_SHIFT 0
+#define WAKER_QSC_SHIFT 31
+
+#define WAKER_SL_BIT (1U << WAKER_SL_SHIFT)
+#define WAKER_QSC_BIT (1U << WAKER_QSC_SHIFT)
+
+#define IIDR_MODEL_ARM_GIC_600 U(0x0200043b)
+#define IIDR_MODEL_ARM_GIC_600AE U(0x0300043b)
+#define IIDR_MODEL_ARM_GIC_700 U(0x0400043b)
+
+#define PIDR_COMPONENT_ARM_DIST U(0x492)
+#define PIDR_COMPONENT_ARM_REDIST U(0x493)
+#define PIDR_COMPONENT_ARM_ITS U(0x494)
+
+#endif /* ARM_GICV3_COMMON_H */
diff --git a/include/drivers/arm/cci.h b/include/drivers/arm/cci.h
new file mode 100644
index 0000000..5aea95a
--- /dev/null
+++ b/include/drivers/arm/cci.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CCI_H
+#define CCI_H
+
+#include <lib/utils_def.h>
+
+/* Slave interface offsets from PERIPHBASE */
+#define SLAVE_IFACE6_OFFSET UL(0x7000)
+#define SLAVE_IFACE5_OFFSET UL(0x6000)
+#define SLAVE_IFACE4_OFFSET UL(0x5000)
+#define SLAVE_IFACE3_OFFSET UL(0x4000)
+#define SLAVE_IFACE2_OFFSET UL(0x3000)
+#define SLAVE_IFACE1_OFFSET UL(0x2000)
+#define SLAVE_IFACE0_OFFSET UL(0x1000)
+#define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \
+ (UL(0x1000) * (index)))
+
+/* Slave interface event and count register offsets from PERIPHBASE */
+#define EVENT_SELECT7_OFFSET UL(0x80000)
+#define EVENT_SELECT6_OFFSET UL(0x70000)
+#define EVENT_SELECT5_OFFSET UL(0x60000)
+#define EVENT_SELECT4_OFFSET UL(0x50000)
+#define EVENT_SELECT3_OFFSET UL(0x40000)
+#define EVENT_SELECT2_OFFSET UL(0x30000)
+#define EVENT_SELECT1_OFFSET UL(0x20000)
+#define EVENT_SELECT0_OFFSET UL(0x10000)
+#define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \
+ (UL(0x10000) * (index)))
+
+/* Control and ID register offsets */
+#define CTRL_OVERRIDE_REG U(0x0)
+#define SECURE_ACCESS_REG U(0x8)
+#define STATUS_REG U(0xc)
+#define IMPRECISE_ERR_REG U(0x10)
+#define PERFMON_CTRL_REG U(0x100)
+#define IFACE_MON_CTRL_REG U(0x104)
+
+/* Component and peripheral ID registers */
+#define PERIPHERAL_ID0 U(0xFE0)
+#define PERIPHERAL_ID1 U(0xFE4)
+#define PERIPHERAL_ID2 U(0xFE8)
+#define PERIPHERAL_ID3 U(0xFEC)
+#define PERIPHERAL_ID4 U(0xFD0)
+#define PERIPHERAL_ID5 U(0xFD4)
+#define PERIPHERAL_ID6 U(0xFD8)
+#define PERIPHERAL_ID7 U(0xFDC)
+
+#define COMPONENT_ID0 U(0xFF0)
+#define COMPONENT_ID1 U(0xFF4)
+#define COMPONENT_ID2 U(0xFF8)
+#define COMPONENT_ID3 U(0xFFC)
+#define COMPONENT_ID4 U(0x1000)
+#define COMPONENT_ID5 U(0x1004)
+#define COMPONENT_ID6 U(0x1008)
+#define COMPONENT_ID7 U(0x100C)
+
+/* Slave interface register offsets */
+#define SNOOP_CTRL_REG U(0x0)
+#define SH_OVERRIDE_REG U(0x4)
+#define READ_CHNL_QOS_VAL_OVERRIDE_REG U(0x100)
+#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG U(0x104)
+#define MAX_OT_REG U(0x110)
+
+/* Snoop Control register bit definitions */
+#define DVM_EN_BIT BIT_32(1)
+#define SNOOP_EN_BIT BIT_32(0)
+#define SUPPORT_SNOOPS BIT_32(30)
+#define SUPPORT_DVM BIT_32(31)
+
+/* Status register bit definitions */
+#define CHANGE_PENDING_BIT BIT_32(0)
+
+/* Event and count register offsets */
+#define EVENT_SELECT_REG U(0x0)
+#define EVENT_COUNT_REG U(0x4)
+#define COUNT_CNTRL_REG U(0x8)
+#define COUNT_OVERFLOW_REG U(0xC)
+
+/* Slave interface monitor registers */
+#define INT_MON_REG_SI0 U(0x90000)
+#define INT_MON_REG_SI1 U(0x90004)
+#define INT_MON_REG_SI2 U(0x90008)
+#define INT_MON_REG_SI3 U(0x9000C)
+#define INT_MON_REG_SI4 U(0x90010)
+#define INT_MON_REG_SI5 U(0x90014)
+#define INT_MON_REG_SI6 U(0x90018)
+
+/* Master interface monitor registers */
+#define INT_MON_REG_MI0 U(0x90100)
+#define INT_MON_REG_MI1 U(0x90104)
+#define INT_MON_REG_MI2 U(0x90108)
+#define INT_MON_REG_MI3 U(0x9010c)
+#define INT_MON_REG_MI4 U(0x90110)
+#define INT_MON_REG_MI5 U(0x90114)
+
+#define SLAVE_IF_UNUSED -1
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+/* Function declarations */
+
+/*
+ * The ARM CCI driver needs the following:
+ * 1. Base address of the CCI product
+ * 2. An array of map between AMBA 4 master ids and ACE/ACE lite slave
+ * interfaces.
+ * 3. Size of the array.
+ *
+ * SLAVE_IF_UNUSED should be used in the map to represent no AMBA 4 master exists
+ * for that interface.
+ */
+void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters);
+
+void cci_enable_snoop_dvm_reqs(unsigned int master_id);
+void cci_disable_snoop_dvm_reqs(unsigned int master_id);
+
+#endif /* __ASSEMBLER__ */
+#endif /* CCI_H */
diff --git a/include/drivers/arm/ccn.h b/include/drivers/arm/ccn.h
new file mode 100644
index 0000000..7f73768
--- /dev/null
+++ b/include/drivers/arm/ccn.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CCN_H
+#define CCN_H
+
+/*
+ * This macro defines the maximum number of master interfaces that reside on
+ * Request nodes which the CCN driver can accommodate. The driver APIs to add
+ * and remove Request nodes from snoop/dvm domains take a bit map of master
+ * interfaces as inputs. The largest C data type that can be used is a 64-bit
+ * unsigned integer. Hence the value of 64. The platform will have to ensure
+ * that the master interfaces are numbered from 0-63.
+ */
+#define CCN_MAX_RN_MASTERS 64
+
+/*
+ * The following constants define the various run modes that the platform can
+ * request the CCN driver to place the L3 cache in. These map to the
+ * programmable P-State values in a HN-F P-state register.
+ */
+#define CCN_L3_RUN_MODE_NOL3 0x0 /* HNF_PM_NOL3 */
+#define CCN_L3_RUN_MODE_SFONLY 0x1 /* HNF_PM_SFONLY */
+#define CCN_L3_RUN_MODE_HAM 0x2 /* HNF_PM_HALF */
+#define CCN_L3_RUN_MODE_FAM 0x3 /* HNF_PM_FULL */
+
+/* part 0 IDs for various CCN variants */
+#define CCN_502_PART0_ID 0x30
+#define CCN_504_PART0_ID 0x26
+#define CCN_505_PART0_ID 0x27
+#define CCN_508_PART0_ID 0x28
+#define CCN_512_PART0_ID 0x29
+
+/*
+ * The following macro takes the value returned from a read of a HN-F P-state
+ * status register and returns the retention state value.
+ */
+#define CCN_GET_RETENTION_STATE(pstate) ((pstate >> 4) & 0x3)
+
+/*
+ * The following macro takes the value returned from a read of a HN-F P-state
+ * status register and returns the run state value.
+ */
+#define CCN_GET_RUN_STATE(pstate) (pstate & 0xf)
+
+#ifndef __ASSEMBLER__
+#include <stdint.h>
+
+/*
+ * This structure describes some of the implementation defined attributes of the
+ * CCN IP. It is used by the platform port to specify these attributes in order
+ * to initialise the CCN driver. The attributes are described below.
+ *
+ * 1. The 'num_masters' field specifies the total number of master interfaces
+ * resident on Request nodes.
+ *
+ * 2. The 'master_to_rn_id_map' field is a ponter to an array in which each
+ * index corresponds to a master interface and its value corresponds to the
+ * Request node on which the master interface resides.
+ * This field is not simply defined as an array of size CCN_MAX_RN_MASTERS.
+ * In reality, a platform will have much fewer master * interfaces than
+ * CCN_MAX_RN_MASTERS. With an array of this size, it would also have to
+ * set the unused entries to a suitable value. Zeroing the array would not
+ * be enough since 0 is also a valid node id. Hence, such an array is not
+ * used.
+ *
+ * 3. The 'periphbase' field is the base address of the programmer's view of the
+ * CCN IP.
+ */
+typedef struct ccn_desc {
+ unsigned int num_masters;
+ const unsigned char *master_to_rn_id_map;
+ uintptr_t periphbase;
+} ccn_desc_t;
+
+/* Enum used to loop through all types of nodes in CCN*/
+typedef enum node_types {
+ NODE_TYPE_RNF = 0,
+ NODE_TYPE_RNI,
+ NODE_TYPE_RND,
+ NODE_TYPE_HNF,
+ NODE_TYPE_HNI,
+ NODE_TYPE_SN,
+ NUM_NODE_TYPES
+} node_types_t;
+
+void ccn_init(const ccn_desc_t *plat_ccn_desc);
+void ccn_enter_snoop_dvm_domain(unsigned long long master_iface_map);
+void ccn_exit_snoop_dvm_domain(unsigned long long master_iface_map);
+void ccn_enter_dvm_domain(unsigned long long master_iface_map);
+void ccn_exit_dvm_domain(unsigned long long master_iface_map);
+void ccn_set_l3_run_mode(unsigned int mode);
+void ccn_program_sys_addrmap(unsigned int sn0_id,
+ unsigned int sn1_id,
+ unsigned int sn2_id,
+ unsigned int top_addr_bit0,
+ unsigned int top_addr_bit1,
+ unsigned char three_sn_en);
+unsigned int ccn_get_l3_run_mode(void);
+int ccn_get_part0_id(uintptr_t periphbase);
+
+void ccn_write_node_reg(node_types_t node_type, unsigned int node_id,
+ unsigned int reg_offset,
+ unsigned long long val);
+unsigned long long ccn_read_node_reg(node_types_t node_type,
+ unsigned int node_id,
+ unsigned int reg_offset);
+
+#endif /* __ASSEMBLER__ */
+#endif /* CCN_H */
diff --git a/include/drivers/arm/cryptocell/712/cc_crypto_boot_defs.h b/include/drivers/arm/cryptocell/712/cc_crypto_boot_defs.h
new file mode 100644
index 0000000..2cb8938
--- /dev/null
+++ b/include/drivers/arm/cryptocell/712/cc_crypto_boot_defs.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CC_CRYPTO_BOOT_DEFS_H
+#define _CC_CRYPTO_BOOT_DEFS_H
+
+/*! @file
+@brief This file contains SBROM definitions
+*/
+
+/*! Version counters value. */
+typedef enum {
+
+ CC_SW_VERSION_COUNTER1 = 1, /*!< Counter 1 - trusted version. */
+ CC_SW_VERSION_COUNTER2, /*!< Counter 2 - non trusted version. */
+
+ CC_SW_VERSION_MAX = 0x7FFFFFFF
+
+} CCSbSwVersionId_t;
+
+/* HASH boot key definition */
+typedef enum {
+ CC_SB_HASH_BOOT_KEY_0_128B = 0, /*!< 128-bit truncated SHA256 digest of public key 0. */
+ CC_SB_HASH_BOOT_KEY_1_128B = 1, /*!< 128-bit truncated SHA256 digest of public key 1. */
+ CC_SB_HASH_BOOT_KEY_256B = 2, /*!< 256-bit SHA256 digest of public key. */
+ CC_SB_HASH_BOOT_NOT_USED = 0xFF,
+ CC_SB_HASH_MAX_NUM = 0x7FFFFFFF, /*!\internal use external 128-bit truncated SHA256 digest */
+} CCSbPubKeyIndexType_t;
+
+
+#endif
diff --git a/include/drivers/arm/cryptocell/712/cc_pal_sb_plat.h b/include/drivers/arm/cryptocell/712/cc_pal_sb_plat.h
new file mode 100644
index 0000000..212a710
--- /dev/null
+++ b/include/drivers/arm/cryptocell/712/cc_pal_sb_plat.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*!
+@file
+@brief This file contains the platform-dependent definitions that are used in the SBROM code.
+*/
+
+#ifndef _CC_PAL_SB_PLAT_H
+#define _CC_PAL_SB_PLAT_H
+
+#include "cc_pal_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*! Definition of DMA address type, can be 32 bits or 64 bits according to CryptoCell's HW. */
+typedef uint64_t CCDmaAddr_t;
+/*! Definition of CryptoCell address type, can be 32 bits or 64 bits according to platform. */
+typedef uintptr_t CCAddr_t;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/drivers/arm/cryptocell/712/cc_pal_types.h b/include/drivers/arm/cryptocell/712/cc_pal_types.h
new file mode 100644
index 0000000..8c09b23
--- /dev/null
+++ b/include/drivers/arm/cryptocell/712/cc_pal_types.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CC_PAL_TYPES_H
+#define CC_PAL_TYPES_H
+
+/*!
+@file
+@brief This file contains platform-dependent definitions and types.
+*/
+
+#include "cc_pal_types_plat.h"
+
+typedef enum {
+ CC_FALSE = 0,
+ CC_TRUE = 1
+} CCBool;
+
+#define CC_SUCCESS 0UL
+#define CC_FAIL 1UL
+
+#define CC_1K_SIZE_IN_BYTES 1024
+#define CC_BITS_IN_BYTE 8
+#define CC_BITS_IN_32BIT_WORD 32
+#define CC_32BIT_WORD_SIZE (sizeof(uint32_t))
+
+#define CC_OK CC_SUCCESS
+
+#define CC_UNUSED_PARAM(prm) ((void)prm)
+
+#define CC_MAX_UINT32_VAL (0xFFFFFFFF)
+
+#define CALC_FULL_BYTES(numBits) (((numBits) + (CC_BITS_IN_BYTE - 1))/CC_BITS_IN_BYTE)
+#define CALC_FULL_32BIT_WORDS(numBits) (((numBits) + (CC_BITS_IN_32BIT_WORD - 1))/CC_BITS_IN_32BIT_WRD)
+#define CALC_32BIT_WORDS_FROM_BYTES(sizeBytes) (((sizeBytes) + CC_32BIT_WORD_SIZE - 1)/CC_32BIT_WORD_SIZE)
+
+#endif
diff --git a/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h b/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h
new file mode 100644
index 0000000..8410024
--- /dev/null
+++ b/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*! @file
+@brief This file contains basic type definitions that are platform-dependent.
+*/
+#ifndef _CC_PAL_TYPES_PLAT_H
+#define _CC_PAL_TYPES_PLAT_H
+/* Host specific types for standard (ISO-C99) compilant platforms */
+
+#include <stddef.h>
+#include <stdint.h>
+
+typedef uint32_t CCStatus;
+
+#define CCError_t CCStatus
+#define CC_INFINITE 0xFFFFFFFF
+
+#define CEXPORT_C
+#define CIMPORT_C
+
+#endif /*_CC_PAL_TYPES_PLAT_H*/
diff --git a/include/drivers/arm/cryptocell/712/cc_sec_defs.h b/include/drivers/arm/cryptocell/712/cc_sec_defs.h
new file mode 100644
index 0000000..d419218
--- /dev/null
+++ b/include/drivers/arm/cryptocell/712/cc_sec_defs.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CC_SEC_DEFS_H
+#define _CC_SEC_DEFS_H
+
+/*!
+@file
+@brief This file contains general hash definitions and types.
+*/
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*! The hashblock size in words. */
+#define HASH_BLOCK_SIZE_IN_WORDS 16
+/*! The hash - SHA2 results in words. */
+#define HASH_RESULT_SIZE_IN_WORDS 8
+#define HASH_RESULT_SIZE_IN_BYTES 32
+
+/*! Definition for hash result array. */
+typedef uint32_t CCHashResult_t[HASH_RESULT_SIZE_IN_WORDS];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/drivers/arm/cryptocell/712/crypto_driver.h b/include/drivers/arm/cryptocell/712/crypto_driver.h
new file mode 100644
index 0000000..18104dd
--- /dev/null
+++ b/include/drivers/arm/cryptocell/712/crypto_driver.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CRYPTO_DRIVER_H
+#define _CRYPTO_DRIVER_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "cc_pal_sb_plat.h"
+#include "cc_sec_defs.h"
+
+/*----------------------------
+ PUBLIC FUNCTIONS
+-----------------------------------*/
+/*!
+ * @brief This function gives the functionality of integrated hash
+ *
+ * @param[in] hwBaseAddress - CryptoCell base address
+ * @param[out] hashResult - the HASH result.
+ *
+ */
+CCError_t SBROM_CryptoHash(unsigned long hwBaseAddress, CCDmaAddr_t inputDataAddr, uint32_t BlockSize,
+ CCHashResult_t hashResult);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/drivers/arm/cryptocell/712/nvm.h b/include/drivers/arm/cryptocell/712/nvm.h
new file mode 100644
index 0000000..a70289f
--- /dev/null
+++ b/include/drivers/arm/cryptocell/712/nvm.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _NVM__H
+#define _NVM__H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "cc_crypto_boot_defs.h"
+#include "cc_pal_types.h"
+#include "cc_sec_defs.h"
+
+/*------------------------------------
+ DEFINES
+-------------------------------------*/
+
+/**
+ * @brief This function reads the LCS from the SRAM/NVM
+ *
+ * @param[in] hwBaseAddress - CryptoCell base address
+ *
+ * @param[in/out] lcs_ptr - pointer to memory to store the LCS
+ *
+ * @return CCError_t - On success the value CC_OK is returned, and on failure -a value from NVM_error.h
+ */
+CCError_t NVM_GetLCS(unsigned long hwBaseAddress, uint32_t *lcs_ptr);
+
+/**
+ * @brief The NVM_ReadHASHPubKey function is a NVM interface function -
+ * The function retrieves the HASH of the device Public key from the SRAM/NVM
+ *
+ * @param[in] hwBaseAddress - CryptoCell base address
+ *
+ * @param[in] pubKeyIndex - Index of HASH in the OTP
+ *
+ * @param[out] PubKeyHASH - the public key HASH.
+ *
+ * @param[in] hashSizeInWords - hash size (valid values: 4W, 8W)
+ *
+ * @return CCError_t - On success the value CC_OK is returned, and on failure -a value from NVM_error.h
+ */
+
+CCError_t NVM_ReadHASHPubKey(unsigned long hwBaseAddress, CCSbPubKeyIndexType_t pubKeyIndex, CCHashResult_t PubKeyHASH, uint32_t hashSizeInWords);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/drivers/arm/cryptocell/712/nvm_otp.h b/include/drivers/arm/cryptocell/712/nvm_otp.h
new file mode 100644
index 0000000..390d62b
--- /dev/null
+++ b/include/drivers/arm/cryptocell/712/nvm_otp.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _NVM_OTP_H
+#define _NVM_OTP_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "cc_crypto_boot_defs.h"
+#include "cc_pal_types.h"
+
+/*------------------------------------
+ DEFINES
+-------------------------------------*/
+
+
+
+/**
+ * @brief The NVM_GetSwVersion function is a NVM interface function -
+ * The function retrieves the SW version from the SRAM/NVM.
+ * In case of OTP, we support up to 16 anti-rollback counters (taken from the certificate)
+ *
+ * @param[in] hwBaseAddress - CryptoCell base address
+ *
+ * @param[in] counterId - relevant only for OTP (valid values: 1,2)
+ *
+ * @param[out] swVersion - the minimum SW version
+ *
+ * @return CCError_t - On success the value CC_OK is returned, and on failure -a value from NVM_error.h
+ */
+CCError_t NVM_GetSwVersion(unsigned long hwBaseAddress, CCSbSwVersionId_t counterId, uint32_t *swVersion);
+
+
+/**
+ * @brief The NVM_SetSwVersion function is a NVM interface function -
+ * The function writes the SW version into the SRAM/NVM.
+ * In case of OTP, we support up to 16 anti-rollback counters (taken from the certificate)
+ *
+ * @param[in] hwBaseAddress - CryptoCell base address
+ *
+ * @param[in] counterId - relevant only for OTP (valid values: 1,2)
+ *
+ * @param[in] swVersion - the minimum SW version
+ *
+ * @return CCError_t - On success the value CC_OK is returned, and on failure -a value from NVM_error.h
+ */
+CCError_t NVM_SetSwVersion(unsigned long hwBaseAddress, CCSbSwVersionId_t counterId, uint32_t swVersion);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/drivers/arm/cryptocell/712/rsa.h b/include/drivers/arm/cryptocell/712/rsa.h
new file mode 100644
index 0000000..825214d
--- /dev/null
+++ b/include/drivers/arm/cryptocell/712/rsa.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RSA_H
+#define RSA_H
+
+/*
+ * All the includes that are needed for code using this module to
+ * compile correctly should be #included here.
+ */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "cc_pal_types.h"
+
+/************************ Defines ******************************/
+
+/* the modulus size in bits */
+#if (KEY_SIZE == 2048)
+#define RSA_MOD_SIZE_IN_BITS 2048UL
+#elif (KEY_SIZE == 3072)
+#define RSA_MOD_SIZE_IN_BITS 3072UL
+#else
+#error Unsupported CryptoCell key size requested
+#endif
+
+#define RSA_MOD_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_MOD_SIZE_IN_BITS))
+#define RSA_MOD_SIZE_IN_WORDS (CALC_FULL_32BIT_WORDS(RSA_MOD_SIZE_IN_BITS))
+#define RSA_MOD_SIZE_IN_256BITS (RSA_MOD_SIZE_IN_WORDS/8)
+#define RSA_EXP_SIZE_IN_BITS 17UL
+#define RSA_EXP_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_EXP_SIZE_IN_BITS))
+
+/*
+ * @brief The RSA_CalcNp calculates Np value and saves it into Np_ptr:
+ *
+ *
+
+ * @param[in] hwBaseAddress - HW base address. Relevant for HW
+ * implementation, for SW it is ignored.
+ * @N_ptr[in] - The pointer to the modulus buffer.
+ * @Np_ptr[out] - pointer to Np vector buffer. Its size must be >= 160.
+ */
+void RSA_CalcNp(unsigned long hwBaseAddress,
+ uint32_t *N_ptr,
+ uint32_t *Np_ptr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/drivers/arm/cryptocell/712/sbrom_bsv_api.h b/include/drivers/arm/cryptocell/712/sbrom_bsv_api.h
new file mode 100644
index 0000000..de83546
--- /dev/null
+++ b/include/drivers/arm/cryptocell/712/sbrom_bsv_api.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _SBROM_BSV_API_H
+#define _SBROM_BSV_API_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*! @file
+@brief This file contains all SBROM library APIs and definitions.
+*/
+#include "cc_pal_types.h"
+
+/* Life cycle state definitions */
+#define CC_BSV_CHIP_MANUFACTURE_LCS 0x0 /*!< CM lifecycle value. */
+#define CC_BSV_DEVICE_MANUFACTURE_LCS 0x1 /*!< DM lifecycle value. */
+#define CC_BSV_SECURITY_DISABLED_LCS 0x3 /*!< SD lifecycle value. */
+#define CC_BSV_SECURE_LCS 0x5 /*!< Secure lifecycle value. */
+#define CC_BSV_RMA_LCS 0x7 /*!< RMA lifecycle value. */
+
+/*----------------------------
+ PUBLIC FUNCTIONS
+-----------------------------------*/
+
+/*!
+@brief This function should be the first ARM TrustZone CryptoCell TEE SBROM library API called.
+It verifies the HW product and version numbers.
+
+@return CC_OK On success.
+@return A non-zero value from sbrom_bsv_error.h on failure.
+*/
+CCError_t CC_BsvSbromInit(
+ unsigned long hwBaseAddress /*!< [in] HW registers base address. */
+ );
+
+
+/*!
+@brief This function can be used for checking the LCS value, after CC_BsvLcsGetAndInit was called by the Boot ROM.
+
+@return CC_OK On success.
+@return A non-zero value from sbrom_bsv_error.h on failure.
+*/
+CCError_t CC_BsvLcsGet(
+ unsigned long hwBaseAddress, /*!< [in] HW registers base address. */
+ uint32_t *pLcs /*!< [out] Returned lifecycle state. */
+ );
+
+/*!
+@brief This function retrieves the HW security lifecycle state, performs validity checks,
+and additional initializations in case the LCS is RMA (sets the Kce to fixed value).
+\note Invalid LCS results in an error returned.
+In this case, the customer's code must completely disable the device.
+
+@return CC_OK On success.
+@return A non-zero value from sbrom_bsv_error.h on failure.
+*/
+CCError_t CC_BsvLcsGetAndInit(
+ unsigned long hwBaseAddress, /*!< [in] HW registers base address. */
+ uint32_t *pLcs /*!< [out] Returned lifecycle state. */
+ );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/drivers/arm/cryptocell/712/secureboot_base_func.h b/include/drivers/arm/cryptocell/712/secureboot_base_func.h
new file mode 100644
index 0000000..6db596e
--- /dev/null
+++ b/include/drivers/arm/cryptocell/712/secureboot_base_func.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _SECURE_BOOT_BASE_FUNC_H
+#define _SECURE_BOOT_BASE_FUNC_H
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "cc_pal_types.h"
+#include "secureboot_gen_defs.h"
+
+
+/*----------------------------
+ PUBLIC FUNCTIONS
+-----------------------------------*/
+
+/**
+ * @brief This function calculates the HASH over the given data and than verify
+ * RSA signature on that hashed data
+ *
+ * @param[in] hwBaseAddr - CryptoCell base address
+ * @param[in] pData - pointer to the data to be verified
+ * @param[in] pNParams - a pointer to the public key parameters
+ * @param[in] pSignature - a pointer to the signature structure
+ * @param[in] sizeOfData - size of the data to calculate the HASH on (in bytes)
+ * @param[in] RSAAlg - RSA algorithm to use
+ *
+ * @return CCError_t - On success the value CC_OK is returned,
+ * on failure - a value from BootImagesVerifier_error.h
+ */
+CCError_t CCSbVerifySignature(unsigned long hwBaseAddress,
+ uint32_t *pData,
+ CCSbNParams_t *pNParams,
+ CCSbSignature_t *pSignature,
+ uint32_t sizeOfData,
+ CCSbRsaAlg_t RSAAlg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h b/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h
new file mode 100644
index 0000000..ed1f283
--- /dev/null
+++ b/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _SECURE_BOOT_GEN_DEFS_H
+#define _SECURE_BOOT_GEN_DEFS_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*! @file
+@brief This file contains all of the definitions and structures that are used for the secure boot.
+*/
+
+#include "cc_pal_sb_plat.h"
+#include "cc_sec_defs.h"
+
+
+/* General definitions */
+/***********************/
+
+/*RSA definitions*/
+#if (KEY_SIZE == 2048)
+#define SB_RSA_MOD_SIZE_IN_WORDS 64
+#elif (KEY_SIZE == 3072)
+#define SB_RSA_MOD_SIZE_IN_WORDS 96
+#else
+#error Unsupported CryptoCell key size requested
+#endif
+
+#define SB_RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_WORDS 5
+
+
+/*! Public key data structure. */
+typedef struct {
+ uint32_t N[SB_RSA_MOD_SIZE_IN_WORDS]; /*!< N public key, big endian representation. */
+ uint32_t Np[SB_RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_WORDS]; /*!< Np (Barrett n' value). */
+} CCSbNParams_t;
+
+/*! Signature structure. */
+typedef struct {
+ uint32_t sig[SB_RSA_MOD_SIZE_IN_WORDS]; /*!< RSA PSS signature. */
+} CCSbSignature_t;
+
+
+/********* Supported algorithms definitions ***********/
+
+/*! RSA supported algorithms */
+/* Note: this applies to either 2k or 3k based on CryptoCell SBROM library
+ * version - it means 2k in version 1 and 3k in version 2 (yes, really).
+ */
+typedef enum {
+ RSA_PSS = 0x01, /*!< RSA PSS after hash SHA 256 */
+ RSA_PKCS15 = 0x02, /*!< RSA PKX15 */
+ RSA_Last = 0x7FFFFFFF
+} CCSbRsaAlg_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/drivers/arm/cryptocell/712/util.h b/include/drivers/arm/cryptocell/712/util.h
new file mode 100644
index 0000000..18fb599
--- /dev/null
+++ b/include/drivers/arm/cryptocell/712/util.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef UTIL_H
+#define UTIL_H
+
+/*
+ * All the includes that are needed for code using this module to
+ * compile correctly should be #included here.
+ */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/************************ Defines ******************************/
+
+/* invers the bytes on a word- used for output from HASH */
+#ifdef BIG__ENDIAN
+#define UTIL_INVERSE_UINT32_BYTES(val) (val)
+#else
+#define UTIL_INVERSE_UINT32_BYTES(val) \
+ (((val) >> 24) | (((val) & 0x00FF0000) >> 8) | (((val) & 0x0000FF00) << 8) | (((val) & 0x000000FF) << 24))
+#endif
+
+/* invers the bytes on a word - used for input data for HASH */
+#ifdef BIG__ENDIAN
+#define UTIL_REVERT_UINT32_BYTES(val) \
+ (((val) >> 24) | (((val) & 0x00FF0000) >> 8) | (((val) & 0x0000FF00) << 8) | (((val) & 0x000000FF) << 24))
+#else
+#define UTIL_REVERT_UINT32_BYTES(val) (val)
+#endif
+
+ /* ------------------------------------------------------------
+ **
+ * @brief This function executes a reverse bytes copying from one buffer to another buffer.
+ *
+ * @param[in] dst_ptr - The pointer to destination buffer.
+ * @param[in] src_ptr - The pointer to source buffer.
+ * @param[in] size - The size in bytes.
+ *
+ */
+
+void UTIL_ReverseMemCopy(uint8_t *dst_ptr, uint8_t *src_ptr, uint32_t size);
+
+
+ /* ------------------------------------------------------------
+ **
+ * @brief This function executes a reversed byte copy on a specified buffer.
+ *
+ * on a 6 byte byffer:
+ *
+ * buff[5] <---> buff[0]
+ * buff[4] <---> buff[1]
+ * buff[3] <---> buff[2]
+ *
+ * @param[in] dst_ptr - The counter buffer.
+ * @param[in] src_ptr - The counter size in bytes.
+ *
+ */
+void UTIL_ReverseBuff(uint8_t *buff_ptr, uint32_t size);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/drivers/arm/cryptocell/713/bsv_api.h b/include/drivers/arm/cryptocell/713/bsv_api.h
new file mode 100644
index 0000000..dc49473
--- /dev/null
+++ b/include/drivers/arm/cryptocell/713/bsv_api.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BSV_API_H
+#define _BSV_API_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*!
+@file
+@brief This file contains the Boot Services APIs and definitions.
+
+@defgroup cc_bsv_api CryptoCell Boot Services APIs and definitions
+@{
+@ingroup cc_bsv
+*/
+
+#include "cc_pal_types.h"
+#include "cc_sec_defs.h"
+#include "cc_boot_defs.h"
+
+/* Life cycle state definitions. */
+#define CC_BSV_CHIP_MANUFACTURE_LCS 0x0 /*!< The CM life-cycle state (LCS) value. */
+#define CC_BSV_DEVICE_MANUFACTURE_LCS 0x1 /*!< The DM life-cycle state (LCS) value. */
+#define CC_BSV_SECURE_LCS 0x5 /*!< The Secure life-cycle state (LCS) value. */
+#define CC_BSV_RMA_LCS 0x7 /*!< The RMA life-cycle state (LCS) value. */
+#define CC_BSV_INVALID_LCS 0xff /*!< The invalid life-cycle state (LCS) value. */
+
+/*----------------------------
+ TYPES
+-----------------------------------*/
+
+/*----------------------------
+ PUBLIC FUNCTIONS
+-----------------------------------*/
+
+
+/*!
+@brief This function verifies the product and version numbers of the HW, and initializes it.
+
+\warning This function must be the first CryptoCell-7xx SBROM library API called.
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvInit(
+ unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */
+ );
+
+/*!
+@brief This function retrieves the HW LCS and performs validity checks.
+
+If the LCS is RMA, it also sets the OTP secret keys to a fixed value.
+
+@note An error is returned if there is an invalid LCS. If this happens, your code must
+completely disable the device.
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvGetAndInitLcs(
+ unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */
+ uint32_t *pLcs /*!< [out] The value of the current LCS. */
+ );
+
+/*!
+@brief This function retrieves the LCS from the NVM manager.
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvLcsGet(
+ unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */
+ uint32_t *pLcs /*!< [out] The value of the current LCS. */
+ );
+
+/*!
+@brief This function reads software revocation counter from OTP memory, according to the provided sw version index.
+SW version is stored in NVM counter and represented by ones. Meaning seVersion=5 would be stored as binary 0b11111;
+hence:
+ the maximal of trusted is 32
+ the maximal of non-trusted is 224
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvSwVersionGet(
+ unsigned long hwBaseAddress, /*!< [in] HW registers base address. */
+ CCSbSwVersionId_t id, /*!< [in] Enumeration defining the trusted/non-trusted counter to read. */
+ uint32_t *swVersion /*!< [out] The value of the requested counter as read from OTP memory. */
+ );
+
+/*!
+@brief This function sets the NVM counter according to swVersionID (trusted/non-trusted).
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvSwVersionSet(
+ unsigned long hwBaseAddress, /*!< [in] HW registers base address. */
+ CCSbSwVersionId_t id, /*!< [in] Enumeration defining the trusted/non-trusted counter to read. */
+ uint32_t swVersion /*!< [in] New value of the counter to be programmed in OTP memory. */
+ );
+
+/*!
+@brief This function sets the "fatal error" flag in the NVM manager, to disable the use of
+any HW keys or security services.
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvFatalErrorSet(
+ unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */
+ );
+
+/*!
+@brief This function retrieves the public key hash from OTP memory, according to the provided index.
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvPubKeyHashGet(
+ unsigned long hwBaseAddress, /*!< [in] HW registers base address. */
+ CCSbPubKeyIndexType_t keyIndex, /*!< [in] Enumeration defining the key hash to retrieve: 128-bit HBK0, 128-bit HBK1, or 256-bit HBK. */
+ uint32_t *hashedPubKey, /*!< [out] A buffer to contain the public key HASH. */
+ uint32_t hashResultSizeWords /*!< [in] The size of the hash in 32-bit words:
+ - Must be 4 for 128-bit hash.
+ - Must be 8 for 256bit hash. */
+ );
+
+/*!
+@brief This function permanently sets the RMA LCS for the ICV and the OEM.
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvRMAModeEnable(
+ unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */
+ );
+
+/*!
+@brief This function is called by the ICV code, to disable the OEM code from changing the ICV RMA bit flag.
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvICVRMAFlagBitLock(
+ unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */
+ );
+
+/*!
+@brief This function locks the defined ICV class keys from further usage.
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvICVKeyLock(
+ unsigned long hwBaseAddress, /*!< [in] HW registers base address. */
+ CCBool_t isICVProvisioningKeyLock, /*!< [in] Should the provisioning key be locked. */
+ CCBool_t isICVCodeEncKeyLock /*!< [in] Should the encryption key be locked. */
+ );
+
+
+/*!
+@brief This function retrieves the value of "secure disable" bit.
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvSecureDisableGet(
+ unsigned long hwBaseAddress, /*!< [in] HW registers base address. */
+ CCBool_t *isSDEnabled /*!< [out] The value of the SD Enable bit. */
+ );
+
+
+/*!
+@brief This function derives the platform key (Kplt) from the Kpicv, and then decrypts the customer key (Kcst)
+from the EKcst (burned in the OTP). The decryption is done only in Secure and RMA LCS mode using AES-ECB.
+The customer ROM should invoke this function during early boot, prior to running any non-ROM code, only if Kcst exists.
+The resulting Kcst is saved in a HW register.
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvCustomerKeyDecrypt(
+ unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */
+ );
+#ifdef __cplusplus
+}
+#endif
+
+/*!
+@brief This function derives the unique SoC_ID for the device, as hashed (Hbk || AES_CMAC (HUK)).
+
+@note SoC_ID is required to create debug certificates.
+
+The OEM or ICV must provide a method for a developer to discover the SoC_ID of a target
+device without having to first enable debugging.
+One suggested implementation is to have the device ROM code compute the SoC_ID and place
+it in a specific location in the flash memory, from where it can be accessed by the developer.
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvSocIDCompute(
+ unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */
+ CCHashResult_t hashResult /*!< [out] The derived SoC_ID. */
+ );
+
+#endif /* _BSV_API_H */
+
+/**
+@}
+ */
+
diff --git a/include/drivers/arm/cryptocell/713/bsv_crypto_api.h b/include/drivers/arm/cryptocell/713/bsv_crypto_api.h
new file mode 100644
index 0000000..1e60579
--- /dev/null
+++ b/include/drivers/arm/cryptocell/713/bsv_crypto_api.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BSV_CRYPTO_API_H
+#define _BSV_CRYPTO_API_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*!
+@file
+@brief This file contains the cryptographic ROM APIs of the Boot Services.
+
+@defgroup cc_bsv_crypto_api CryptoCell Boot Services cryptographic ROM APIs
+@{
+@ingroup cc_bsv
+*/
+
+#include "cc_pal_types.h"
+#include "cc_sec_defs.h"
+#include "cc_address_defs.h"
+#include "bsv_crypto_defs.h"
+
+/*----------------------------
+ PUBLIC FUNCTIONS
+-----------------------------------*/
+
+/*!
+@brief This function calculates the SHA-256 digest over contiguous memory
+in an integrated operation.
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvSha256(
+ unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */
+ uint8_t *pDataIn, /*!< [in] A pointer to the input buffer to be hashed. The buffer must be contiguous. */
+ size_t dataSize, /*!< [in] The size of the data to be hashed, in bytes. */
+ CCHashResult_t hashBuff /*!< [out] A pointer to a word-aligned 32-byte buffer. */
+ );
+
+
+/*!
+@brief This function allows you to calculate SHA256 digest of an image with decryption base on AES-CTR,
+with HW or user key.
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure. (in this case, hashBuff will be returned clean, while the output data should be cleaned by the user).
+*/
+CCError_t CC_BsvCryptoImageDecrypt( unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */
+ CCBsvflowMode_t flow, /*!< [in] The supported operations are: HASH, AES to HASH, AES and HASH. */
+ CCBsvKeyType_t keyType, /*!< [in] The key type to use: Kce, Kceicv, or user key. */
+ uint8_t *pUserKey, /*!< [in] A pointer to the user key buffer in case keyType is CC_BSV_USER_KEY. */
+ size_t userKeySize, /*!< [in] The user key size in bytes (128bits) in case keyType is CC_BSV_USER_KEY. */
+ uint8_t *pIvBuf, /*!< [in] A pointer to the IV / counter buffer. */
+ uint8_t *pInputData, /*!< [in] A pointer to the input data. */
+ uint8_t *pOutputData, /*!< [out] A pointer to the output buffer. (optional – should be null in case of hash only). */
+ size_t dataSize, /*!< [in] The size of the input data in bytes. MUST be multiple of AES block size. */
+ CCHashResult_t hashBuff /*!< [out] A pointer to a word-aligned 32-byte digest output buffer. */
+ );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/**
+@}
+ */
+
diff --git a/include/drivers/arm/cryptocell/713/bsv_crypto_asym_api.h b/include/drivers/arm/cryptocell/713/bsv_crypto_asym_api.h
new file mode 100644
index 0000000..406e1ef
--- /dev/null
+++ b/include/drivers/arm/cryptocell/713/bsv_crypto_asym_api.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BSV_CRYPTO_ASYM_API_H
+#define _BSV_CRYPTO_ASYM_API_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*!
+@file
+@brief This file contains the cryptographic Asymmetric ROM APIs of the Boot Services.
+
+@defgroup cc_bsv_crypto_asym_api CryptoCell Boot Services cryptographic Asymmetric ROM APIs
+@{
+@ingroup cc_bsv
+*/
+
+#include "cc_pal_types.h"
+#include "cc_pka_hw_plat_defs.h"
+#include "cc_sec_defs.h"
+#include "bsv_crypto_api.h"
+
+/*! Defines the workspace size in bytes needed for internal Asymmetric operations. */
+#define BSV_RSA_WORKSPACE_MIN_SIZE (4*BSV_CERT_RSA_KEY_SIZE_IN_BYTES +\
+ 2*RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_BYTES)
+
+/*! Definition for the RSA public modulus array. */
+typedef uint32_t CCBsvNBuff_t[BSV_CERT_RSA_KEY_SIZE_IN_WORDS];
+
+/*! Definition for the RSA Barrett mod tag array. */
+typedef uint32_t CCBsvNpBuff_t[RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_BYTES];
+
+/*! Definition for the RSA signature array. */
+typedef uint32_t CCBsvSignature_t[BSV_CERT_RSA_KEY_SIZE_IN_WORDS];
+
+
+/*----------------------------
+ PUBLIC FUNCTIONS
+-----------------------------------*/
+
+/*!
+@brief This function performs the primitive operation of RSA, meaning exponent and modulus.
+ outBuff = (pInBuff ^ Exp) mod NBuff. ( Exp = 0x10001 )
+
+ The function supports 2k and 3K bit size of modulus, based on compile time define.
+ There are no restriction on pInBuff location, however its size must be equal to BSV_RSA_KEY_SIZE_IN_BYTES and its
+ value must be smaller than the modulus.
+
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvRsaPrimVerify (unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */
+ CCBsvNBuff_t NBuff, /*!< [in] The modulus buffer big endian format. */
+ CCBsvNpBuff_t NpBuff, /*!< [in] The barret tag buffer big endian format - optional. */
+ uint32_t *pInBuff, /*!< [in] The DataIn buffer to be encrypted. */
+ size_t inBuffSize, /*!< [in] The DataIn buffer size in bytes, must be BSV_RSA_KEY_SIZE_IN_BYTES. */
+ CCBsvSignature_t pOutBuff, /*!< [out] The encrypted buffer in big endian format. */
+ uint32_t *pWorkSpace, /*!< [in] The pointer to user allocated buffer for internal use. */
+ size_t workBufferSize /*!< [in] The size in bytes of pWorkSpace, must be at-least BSV_RSA_WORKSPACE_MIN_SIZE. */
+);
+
+
+/*!
+@brief This function performs RSA PSS verify.
+
+ The function should support 2k and 3K bit size of modulus, based on compile time define.
+
+@return \c CC_OK on success.
+@return A non-zero value from bsv_error.h on failure.
+*/
+CCError_t CC_BsvRsaPssVerify (unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */
+ CCBsvNBuff_t NBuff, /*!< [in] The modulus buffer big endian format. */
+ CCBsvNpBuff_t NpBuff, /*!< [in] The barret tag buffer big endian format - optional. */
+ CCBsvSignature_t signature, /*!< [in] The signature buffer to verify - big endian format. */
+ CCHashResult_t hashedData, /*!< [in] The data-in buffer to be verified as sha256 digest. */
+ uint32_t *pWorkSpace, /*!< [in] The pointer to user allocated buffer for internal use. */
+ size_t workBufferSize, /*!< [in] The size in bytes of pWorkSpace, must be at-least BSV_RSA_WORKSPACE_MIN_SIZE. */
+ CCBool_t *pIsVerified /*!< [out] The flag indicates whether the signature is verified or not.
+ If verified value will be CC_TRUE, otherwise CC_FALSE */
+);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/**
+@}
+ */
+
diff --git a/include/drivers/arm/cryptocell/713/bsv_crypto_defs.h b/include/drivers/arm/cryptocell/713/bsv_crypto_defs.h
new file mode 100644
index 0000000..9ea354d
--- /dev/null
+++ b/include/drivers/arm/cryptocell/713/bsv_crypto_defs.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BSV_CRYPTO_DEFS_H
+#define _BSV_CRYPTO_DEFS_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*!
+@file
+@brief This file contains the definitions of the cryptographic ROM APIs.
+
+@defgroup cc_bsv_crypto_defs CryptoCell Boot Services cryptographic ROM API definitions
+@{
+@ingroup cc_bsv
+*/
+
+/*! AES supported HW key code table. */
+typedef enum {
+
+ CC_BSV_USER_KEY = 0, /*!< Definition for a user key. */
+ CC_BSV_HUK_KEY = 1, /*!< Definition for the HW unique key. */
+ CC_BSV_RTL_KEY = 2, /*!< Definition for the RTL key. */
+ CC_BSV_SESSION_KEY = 3, /*!< Definition for the Session key. */
+ CC_BSV_CE_KEY = 4, /*!< Definition for the Kce. */
+ CC_BSV_PLT_KEY = 5, /*!< Definition for the Platform key. */
+ CC_BSV_KCST_KEY = 6, /*!< Definition for Kcst. */
+ CC_BSV_ICV_PROV_KEY = 0xd, /*!< Definition for the Kpicv. */
+ CC_BSV_ICV_CE_KEY = 0xe, /*!< Definition for the Kceicv. */
+ CC_BSV_PROV_KEY = 0xf, /*!< Definition for the Kcp. */
+ CC_BSV_END_OF_KEY_TYPE = INT32_MAX, /*!< Reserved. */
+}CCBsvKeyType_t;
+
+/*! AES directions. */
+typedef enum bsvAesDirection {
+ BSV_AES_DIRECTION_ENCRYPT = 0, /*!< Encrypt.*/
+ BSV_AES_DIRECTION_DECRYPT = 1, /*!< Decrypt.*/
+ BSV_AES_NUM_OF_ENCRYPT_MODES, /*!< The maximal number of operations. */
+ BSV_AES_DIRECTION_RESERVE32B = INT32_MAX /*!< Reserved.*/
+}bsvAesDirection_t;
+
+/*! Definitions of the cryptographic flow supported as part of the Secure Boot. */
+typedef enum {
+ CC_BSV_CRYPTO_HASH_MODE = 0, /*!< Hash mode only. */
+ CC_BSV_CRYPTO_AES_CTR_AND_HASH_MODE = 1, /*!< Data goes into the AES and Hash engines. */
+ CC_BSV_CRYPTO_AES_CTR_TO_HASH_MODE = 2 /*!< Data goes into the AES and from the AES to the Hash engine. */
+}CCBsvflowMode_t;
+
+/*! CryptoImage HW completion sequence mode */
+typedef enum
+{
+ BSV_CRYPTO_COMPLETION_NO_WAIT = 0, /*!< The driver waits only before reading the output. */
+ BSV_CRYPTO_COMPLETION_WAIT_UPON_END = 1 /*!< The driver waits after each chunk of data. */
+}bsvCryptoCompletionMode_t;
+
+
+/*! AES-CMAC result size, in words. */
+#define CC_BSV_CMAC_RESULT_SIZE_IN_WORDS 4 /* 128b */
+/*! AES-CMAC result size, in bytes. */
+#define CC_BSV_CMAC_RESULT_SIZE_IN_BYTES 16 /* 128b */
+/*! AES-CCM 128bit key size, in bytes. */
+#define CC_BSV_CCM_KEY_SIZE_BYTES 16
+/*! AES-CCM 128bit key size, in words. */
+#define CC_BSV_CCM_KEY_SIZE_WORDS 4
+/*! AES-CCM NONCE size, in bytes. */
+#define CC_BSV_CCM_NONCE_SIZE_BYTES 12
+
+
+/*! AES-CMAC result buffer. */
+typedef uint32_t CCBsvCmacResult_t[CC_BSV_CMAC_RESULT_SIZE_IN_WORDS];
+/*! AES-CCM key buffer.*/
+typedef uint32_t CCBsvCcmKey_t[CC_BSV_CCM_KEY_SIZE_WORDS];
+/*! AES-CCM nonce buffer.*/
+typedef uint8_t CCBsvCcmNonce_t[CC_BSV_CCM_NONCE_SIZE_BYTES];
+/*! AES-CCM MAC buffer.*/
+typedef uint8_t CCBsvCcmMacRes_t[CC_BSV_CMAC_RESULT_SIZE_IN_BYTES];
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/**
+@}
+ */
+
diff --git a/include/drivers/arm/cryptocell/713/bsv_error.h b/include/drivers/arm/cryptocell/713/bsv_error.h
new file mode 100644
index 0000000..4d72e60
--- /dev/null
+++ b/include/drivers/arm/cryptocell/713/bsv_error.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BSV_ERROR_H
+#define _BSV_ERROR_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*!
+@file
+@brief This file defines the error code types that are returned from the Boot Services APIs.
+
+@defgroup cc_bsv_error CryptoCell Boot Services error codes
+@{
+@ingroup cc_bsv
+*/
+
+/*! Defines the base address for Boot Services errors. */
+#define CC_BSV_BASE_ERROR 0x0B000000
+/*! Defines the base address for Boot Services cryptographic errors. */
+#define CC_BSV_CRYPTO_ERROR 0x0C000000
+
+/*! Illegal input parameter. */
+#define CC_BSV_ILLEGAL_INPUT_PARAM_ERR (CC_BSV_BASE_ERROR + 0x00000001)
+/*! Illegal HUK value. */
+#define CC_BSV_ILLEGAL_HUK_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000002)
+/*! Illegal Kcp value. */
+#define CC_BSV_ILLEGAL_KCP_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000003)
+/*! Illegal Kce value. */
+#define CC_BSV_ILLEGAL_KCE_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000004)
+/*! Illegal Kpicv value. */
+#define CC_BSV_ILLEGAL_KPICV_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000005)
+/*! Illegal Kceicv value. */
+#define CC_BSV_ILLEGAL_KCEICV_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000006)
+/*! Illegal EKcst value. */
+#define CC_BSV_ILLEGAL_EKCST_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000007)
+/*! Hash boot key not programmed in the OTP. */
+#define CC_BSV_HASH_NOT_PROGRAMMED_ERR (CC_BSV_BASE_ERROR + 0x00000008)
+/*! Illegal Hash boot key zero count in the OTP. */
+#define CC_BSV_HBK_ZERO_COUNT_ERR (CC_BSV_BASE_ERROR + 0x00000009)
+/*! Illegal LCS. */
+#define CC_BSV_ILLEGAL_LCS_ERR (CC_BSV_BASE_ERROR + 0x0000000A)
+/*! OTP write compare failure. */
+#define CC_BSV_OTP_WRITE_CMP_FAIL_ERR (CC_BSV_BASE_ERROR + 0x0000000B)
+/*! OTP access error */
+#define CC_BSV_OTP_ACCESS_ERR (CC_BSV_BASE_ERROR + 0x0000000C)
+/*! Erase key in OTP failed. */
+#define CC_BSV_ERASE_KEY_FAILED_ERR (CC_BSV_BASE_ERROR + 0x0000000D)
+/*! Illegal PIDR. */
+#define CC_BSV_ILLEGAL_PIDR_ERR (CC_BSV_BASE_ERROR + 0x0000000E)
+/*! Illegal CIDR. */
+#define CC_BSV_ILLEGAL_CIDR_ERR (CC_BSV_BASE_ERROR + 0x0000000F)
+/*! Device failed to move to fatal error state. */
+#define CC_BSV_FAILED_TO_SET_FATAL_ERR (CC_BSV_BASE_ERROR + 0x00000010)
+/*! Failed to set RMA LCS. */
+#define CC_BSV_FAILED_TO_SET_RMA_ERR (CC_BSV_BASE_ERROR + 0x00000011)
+/*! Illegal RMA indication. */
+#define CC_BSV_ILLEGAL_RMA_INDICATION_ERR (CC_BSV_BASE_ERROR + 0x00000012)
+/*! Boot Services version is not initialized. */
+#define CC_BSV_VER_IS_NOT_INITIALIZED_ERR (CC_BSV_BASE_ERROR + 0x00000013)
+/*! APB secure mode is locked. */
+#define CC_BSV_APB_SECURE_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000014)
+/*! APB privilege mode is locked. */
+#define CC_BSV_APB_PRIVILEG_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000015)
+/*! Illegal operation. */
+#define CC_BSV_ILLEGAL_OPERATION_ERR (CC_BSV_BASE_ERROR + 0x00000016)
+/*! Illegal asset size. */
+#define CC_BSV_ILLEGAL_ASSET_SIZE_ERR (CC_BSV_BASE_ERROR + 0x00000017)
+/*! Illegal asset value. */
+#define CC_BSV_ILLEGAL_ASSET_VAL_ERR (CC_BSV_BASE_ERROR + 0x00000018)
+/*! Kpicv is locked. */
+#define CC_BSV_KPICV_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000019)
+/*! Illegal SW version. */
+#define CC_BSV_ILLEGAL_SW_VERSION_ERR (CC_BSV_BASE_ERROR + 0x0000001A)
+/*! AO write operation. */
+#define CC_BSV_AO_WRITE_FAILED_ERR (CC_BSV_BASE_ERROR + 0x0000001B)
+/*! Chip state is already initialized. */
+#define CC_BSV_CHIP_INITIALIZED_ERR (CC_BSV_BASE_ERROR + 0x0000001C)
+/*! SP is not enabled. */
+#define CC_BSV_SP_NOT_ENABLED_ERR (CC_BSV_BASE_ERROR + 0x0000001D)
+/*! Production secure provisioning - header fields. */
+#define CC_BSV_PROD_PKG_HEADER_ERR (CC_BSV_BASE_ERROR + 0x0000001E)
+/*! Production secure provisioning - header MAC. */
+#define CC_BSV_PROD_PKG_HEADER_MAC_ERR (CC_BSV_BASE_ERROR + 0x0000001F)
+/*! Overrun buffer or size. */
+#define CC_BSV_OVERRUN_ERR (CC_BSV_BASE_ERROR + 0x00000020)
+/*! Kceicv is locked. */
+#define CC_BSV_KCEICV_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000021)
+/*! Chip indication is CHIP_STATE_ERROR. */
+#define CC_BSV_CHIP_INDICATION_ERR (CC_BSV_BASE_ERROR + 0x00000022)
+/*! Device is locked in fatal error state. */
+#define CC_BSV_FATAL_ERR_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000023)
+/*! Device has security disable feature enabled. */
+#define CC_BSV_SECURE_DISABLE_ERROR (CC_BSV_BASE_ERROR + 0x00000024)
+/*! Device has Kcst in disabled state */
+#define CC_BSV_KCST_DISABLE_ERROR (CC_BSV_BASE_ERROR + 0x00000025)
+
+
+/*! Illegal data-in pointer. */
+#define CC_BSV_CRYPTO_INVALID_DATA_IN_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000001)
+/*! Illegal data-out pointer. */
+#define CC_BSV_CRYPTO_INVALID_DATA_OUT_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000002)
+/*! Illegal data size. */
+#define CC_BSV_CRYPTO_INVALID_DATA_SIZE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000003)
+/*! Illegal key type. */
+#define CC_BSV_CRYPTO_INVALID_KEY_TYPE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000004)
+/*! Illegal key size. */
+#define CC_BSV_CRYPTO_INVALID_KEY_SIZE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000005)
+/*! Invalid key pointer. */
+#define CC_BSV_CRYPTO_INVALID_KEY_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000006)
+/*! Illegal key DMA type. */
+#define CC_BSV_CRYPTO_INVALID_KEY_DMA_TYPE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000007)
+/*! Illegal IV pointer. */
+#define CC_BSV_CRYPTO_INVALID_IV_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000008)
+/*! Illegal cipher mode. */
+#define CC_BSV_CRYPTO_INVALID_CIPHER_MODE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000009)
+/*! Illegal result buffer pointer. */
+#define CC_BSV_CRYPTO_INVALID_RESULT_BUFFER_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000A)
+/*! Invalid DMA type. */
+#define CC_BSV_CRYPTO_INVALID_DMA_TYPE_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000B)
+/*! Invalid in/out buffers overlapping. */
+#define CC_BSV_CRYPTO_DATA_OUT_DATA_IN_OVERLAP_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000C)
+/*! Invalid KDF label size. */
+#define CC_BSV_CRYPTO_ILLEGAL_KDF_LABEL_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000D)
+/*! Invalid KDF Context size. */
+#define CC_BSV_CRYPTO_ILLEGAL_KDF_CONTEXT_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000E)
+/*! Invalid CCM key. */
+#define CC_BSV_CCM_INVALID_KEY_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000f)
+/*! Invalid CCM Nonce. */
+#define CC_BSV_CCM_INVALID_NONCE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000010)
+/*! Invalid CCM associated data. */
+#define CC_BSV_CCM_INVALID_ASSOC_DATA_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000011)
+/*! Invalid CCM text data. */
+#define CC_BSV_CCM_INVALID_TEXT_DATA_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000012)
+/*! Invalid CCM-MAC buffer. */
+#define CC_BSV_CCM_INVALID_MAC_BUF_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000013)
+/*! CCM-MAC comparison failed. */
+#define CC_BSV_CCM_TAG_LENGTH_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000014)
+/*! CCM-MAC comparison failed. */
+#define CC_BSV_CCM_MAC_INVALID_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000015)
+/*! Illegal flow mode. */
+#define CC_BSV_CRYPTO_INVALID_FLOW_MODE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000016)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/**
+@}
+ */
+
+
+
diff --git a/include/drivers/arm/cryptocell/713/cc_address_defs.h b/include/drivers/arm/cryptocell/713/cc_address_defs.h
new file mode 100644
index 0000000..0abc15c
--- /dev/null
+++ b/include/drivers/arm/cryptocell/713/cc_address_defs.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CC_ADDRESS_DEFS_H
+#define _CC_ADDRESS_DEFS_H
+
+/*!
+@file
+@brief This file contains general definitions.
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "cc_pal_types.h"
+
+/************************ Defines ******************************/
+
+/**
+ * Address types within CC
+ */
+/*! Definition of DMA address type, can be 32 bits or 64 bits according to CryptoCell's HW. */
+typedef uint64_t CCDmaAddr_t;
+/*! Definition of CryptoCell address type, can be 32 bits or 64 bits according to platform. */
+typedef uint64_t CCAddr_t;
+/*! Definition of CC SRAM address type, can be 32 bits according to CryptoCell's HW. */
+typedef uint32_t CCSramAddr_t;
+
+/*
+ * CCSramAddr_t is being cast into pointer type which can be 64 bit.
+ */
+/*! Definition of MACRO that casts SRAM addresses to pointer types. */
+#define CCSramAddr2Ptr(sramAddr) ((uintptr_t)sramAddr)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/**
+ @}
+ */
+
+
diff --git a/include/drivers/arm/cryptocell/713/cc_boot_defs.h b/include/drivers/arm/cryptocell/713/cc_boot_defs.h
new file mode 100644
index 0000000..4d29a6d
--- /dev/null
+++ b/include/drivers/arm/cryptocell/713/cc_boot_defs.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CC_BOOT_DEFS_H
+#define _CC_BOOT_DEFS_H
+
+/*!
+ @file
+ @brief This file contains general definitions of types and enums of Boot APIs.
+ */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*! Version counters value. */
+typedef enum {
+
+ CC_SW_VERSION_TRUSTED = 0, /*!< Trusted counter. */
+ CC_SW_VERSION_NON_TRUSTED, /*!< Non trusted counter. */
+ CC_SW_VERSION_MAX = 0x7FFFFFFF /*!< Reserved */
+} CCSbSwVersionId_t;
+
+/*! The hash boot key definition. */
+typedef enum {
+ CC_SB_HASH_BOOT_KEY_0_128B = 0, /*!< Hbk0: 128-bit truncated SHA-256 digest of PubKB0. Used by ICV */
+ CC_SB_HASH_BOOT_KEY_1_128B = 1, /*!< Hbk1: 128-bit truncated SHA-256 digest of PubKB1. Used by OEM */
+ CC_SB_HASH_BOOT_KEY_256B = 2, /*!< Hbk: 256-bit SHA-256 digest of public key. */
+ CC_SB_HASH_BOOT_NOT_USED = 0xF, /*!< Hbk is not used. */
+ CC_SB_HASH_MAX_NUM = 0x7FFFFFFF, /*!< Reserved. */
+} CCSbPubKeyIndexType_t;
+
+/*! Chip state. */
+typedef enum {
+ CHIP_STATE_NOT_INITIALIZED = 0, /*! Chip is not initialized. */
+ CHIP_STATE_TEST = 1, /*! Chip is in Production state. */
+ CHIP_STATE_PRODUCTION = 2, /*! Chip is in Production state. */
+ CHIP_STATE_ERROR = 3, /*! Chip is in Error state. */
+} CCBsvChipState_t;
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_CC_BOOT_DEFS_H */
+
+/**
+@}
+ */
diff --git a/include/drivers/arm/cryptocell/713/cc_pal_types.h b/include/drivers/arm/cryptocell/713/cc_pal_types.h
new file mode 100644
index 0000000..4ab3960
--- /dev/null
+++ b/include/drivers/arm/cryptocell/713/cc_pal_types.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CC_PAL_TYPES_H
+#define CC_PAL_TYPES_H
+
+/*!
+@file
+@brief This file contains platform-dependent definitions and types of the PAL layer.
+
+@defgroup cc_pal_types CryptoCell platform-dependent PAL layer definitions and types
+@{
+@ingroup cc_pal
+
+ @{
+ @ingroup cc_pal
+ @}
+*/
+
+#include "cc_pal_types_plat.h"
+
+/*! Definition of Boolean type.*/
+typedef enum {
+ /*! Boolean false.*/
+ CC_FALSE = 0,
+ /*! Boolean true.*/
+ CC_TRUE = 1
+} CCBool_t;
+
+/*! Success. */
+#define CC_SUCCESS 0UL
+/*! Failure. */
+#define CC_FAIL 1UL
+
+/*! Success (OK). */
+#define CC_OK 0
+
+/*! This macro handles unused parameters in the code, to avoid compilation warnings. */
+#define CC_UNUSED_PARAM(prm) ((void)prm)
+
+/*! The maximal uint32 value.*/
+#define CC_MAX_UINT32_VAL (0xFFFFFFFF)
+
+
+/* Minimal and Maximal macros */
+#ifdef min
+/*! Definition for minimal calculation. */
+#define CC_MIN(a,b) min( a , b )
+#else
+/*! Definition for minimal calculation. */
+#define CC_MIN( a , b ) ( ( (a) < (b) ) ? (a) : (b) )
+#endif
+
+#ifdef max
+/*! Definition for maximal calculation. */
+#define CC_MAX(a,b) max( a , b )
+#else
+/*! Definition for maximal calculation.. */
+#define CC_MAX( a , b ) ( ( (a) > (b) ) ? (a) : (b) )
+#endif
+
+/*! This macro calculates the number of full Bytes from bits, where seven bits are one Byte. */
+#define CALC_FULL_BYTES(numBits) ((numBits)/CC_BITS_IN_BYTE + (((numBits) & (CC_BITS_IN_BYTE-1)) > 0))
+/*! This macro calculates the number of full 32-bit words from bits where 31 bits are one word. */
+#define CALC_FULL_32BIT_WORDS(numBits) ((numBits)/CC_BITS_IN_32BIT_WORD + (((numBits) & (CC_BITS_IN_32BIT_WORD-1)) > 0))
+/*! This macro calculates the number of full 32-bit words from Bytes where three Bytes are one word. */
+#define CALC_32BIT_WORDS_FROM_BYTES(sizeBytes) ((sizeBytes)/CC_32BIT_WORD_SIZE + (((sizeBytes) & (CC_32BIT_WORD_SIZE-1)) > 0))
+/*! This macro calculates the number of full 32-bit words from 64-bits dwords. */
+#define CALC_32BIT_WORDS_FROM_64BIT_DWORD(sizeWords) (sizeWords * CC_32BIT_WORD_IN_64BIT_DWORD)
+/*! This macro rounds up bits to 32-bit words. */
+#define ROUNDUP_BITS_TO_32BIT_WORD(numBits) (CALC_FULL_32BIT_WORDS(numBits) * CC_BITS_IN_32BIT_WORD)
+/*! This macro rounds up bits to Bytes. */
+#define ROUNDUP_BITS_TO_BYTES(numBits) (CALC_FULL_BYTES(numBits) * CC_BITS_IN_BYTE)
+/*! This macro rounds up bytes to 32-bit words. */
+#define ROUNDUP_BYTES_TO_32BIT_WORD(sizeBytes) (CALC_32BIT_WORDS_FROM_BYTES(sizeBytes) * CC_32BIT_WORD_SIZE)
+/*! This macro calculates the number Bytes from words. */
+#define CALC_WORDS_TO_BYTES(numwords) ((numwords)*CC_32BIT_WORD_SIZE)
+/*! Definition of 1 KB in Bytes. */
+#define CC_1K_SIZE_IN_BYTES 1024
+/*! Definition of number of bits in a Byte. */
+#define CC_BITS_IN_BYTE 8
+/*! Definition of number of bits in a 32-bits word. */
+#define CC_BITS_IN_32BIT_WORD 32
+/*! Definition of number of Bytes in a 32-bits word. */
+#define CC_32BIT_WORD_SIZE 4
+/*! Definition of number of 32-bits words in a 64-bits dword. */
+#define CC_32BIT_WORD_IN_64BIT_DWORD 2
+
+
+#endif
+
+/**
+@}
+ */
+
+
+
diff --git a/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h b/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h
new file mode 100644
index 0000000..9848472
--- /dev/null
+++ b/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*! @file
+@brief This file contains basic type definitions that are platform-dependent.
+*/
+#ifndef _CC_PAL_TYPES_PLAT_H
+#define _CC_PAL_TYPES_PLAT_H
+/* Host specific types for standard (ISO-C99) compilant platforms */
+
+#include <stddef.h>
+#include <stdint.h>
+
+typedef uint32_t CCStatus;
+
+#define CCError_t CCStatus
+#define CC_INFINITE 0xFFFFFFFF
+
+#define CEXPORT_C
+#define CIMPORT_C
+
+#endif /*_CC_PAL_TYPES_PLAT_H*/
diff --git a/include/drivers/arm/cryptocell/713/cc_pka_hw_plat_defs.h b/include/drivers/arm/cryptocell/713/cc_pka_hw_plat_defs.h
new file mode 100644
index 0000000..1a1bce0
--- /dev/null
+++ b/include/drivers/arm/cryptocell/713/cc_pka_hw_plat_defs.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CC_PKA_HW_PLAT_DEFS_H
+#define _CC_PKA_HW_PLAT_DEFS_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+#include "cc_pal_types.h"
+/*!
+@file
+@brief Contains the enums and definitions that are used in the PKA code (definitions that are platform dependent).
+*/
+
+/*! The size of the PKA engine word. */
+#define CC_PKA_WORD_SIZE_IN_BITS 128
+
+/*! The maximal supported size of modulus in RSA in bits. */
+#define CC_RSA_MAX_VALID_KEY_SIZE_VALUE_IN_BITS 4096
+/*! The maximal supported size of key-generation in RSA in bits. */
+#define CC_RSA_MAX_KEY_GENERATION_HW_SIZE_BITS 4096
+
+/*! Secure boot/debug certificate RSA public modulus key size in bits. */
+#if (KEY_SIZE == 3072)
+ #define BSV_CERT_RSA_KEY_SIZE_IN_BITS 3072
+#else
+ #define BSV_CERT_RSA_KEY_SIZE_IN_BITS 2048
+#endif
+/*! Secure boot/debug certificate RSA public modulus key size in bytes. */
+#define BSV_CERT_RSA_KEY_SIZE_IN_BYTES (BSV_CERT_RSA_KEY_SIZE_IN_BITS/CC_BITS_IN_BYTE)
+/*! Secure boot/debug certificate RSA public modulus key size in words. */
+#define BSV_CERT_RSA_KEY_SIZE_IN_WORDS (BSV_CERT_RSA_KEY_SIZE_IN_BITS/CC_BITS_IN_32BIT_WORD)
+
+/*! The maximal count of extra bits in PKA operations. */
+#define PKA_EXTRA_BITS 8
+/*! The number of memory registers in PKA operations. */
+#define PKA_MAX_COUNT_OF_PHYS_MEM_REGS 32
+
+/*! Size of buffer for Barrett modulus tag in words. */
+#define RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_WORDS 5
+/*! Size of buffer for Barrett modulus tag in bytes. */
+#define RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_BYTES (RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_WORDS*CC_32BIT_WORD_SIZE)
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //_CC_PKA_HW_PLAT_DEFS_H
+
+/**
+ @}
+ */
+
diff --git a/include/drivers/arm/cryptocell/713/cc_sec_defs.h b/include/drivers/arm/cryptocell/713/cc_sec_defs.h
new file mode 100644
index 0000000..8fb698f
--- /dev/null
+++ b/include/drivers/arm/cryptocell/713/cc_sec_defs.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CC_SEC_DEFS_H
+#define _CC_SEC_DEFS_H
+
+/*!
+@file
+@brief This file contains general definitions and types.
+*/
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "cc_pal_types.h"
+
+/*! Hashblock size in words. */
+#define HASH_BLOCK_SIZE_IN_WORDS 16
+/*! Hash - SHA2 results in words. */
+#define HASH_RESULT_SIZE_IN_WORDS 8
+/*! Hash - SHA2 results in bytes. */
+#define HASH_RESULT_SIZE_IN_BYTES 32
+
+/*! Definition for hash result array. */
+typedef uint32_t CCHashResult_t[HASH_RESULT_SIZE_IN_WORDS];
+
+/*! Definition for converting pointer to Host address. */
+#define CONVERT_TO_ADDR(ptr) (unsigned long)ptr
+
+/*! Definition for converting pointer to SRAM address. */
+#define CONVERT_TO_SRAM_ADDR(ptr) (0xFFFFFFFF & ptr)
+
+/*! The data size of the signed SW image, in bytes. */
+/*!\internal ContentCertImageRecord_t includes: HS(8W) + 64-b dstAddr(2W) + imgSize(1W) + isCodeEncUsed(1W) */
+#define SW_REC_SIGNED_DATA_SIZE_IN_BYTES 48
+
+/*! The data size of the unsigned SW image, in bytes. */
+/*!\internal CCSbSwImgAddData_t includes: 64-b srcAddr(2W)*/
+#define SW_REC_NONE_SIGNED_DATA_SIZE_IN_BYTES 8
+
+/*! The additional data size - storage address and length of the unsigned SW image, in words. */
+#define SW_REC_NONE_SIGNED_DATA_SIZE_IN_WORDS SW_REC_NONE_SIGNED_DATA_SIZE_IN_BYTES/CC_32BIT_WORD_SIZE
+
+/*! The additional data section size, in bytes. */
+#define CC_SB_MAX_SIZE_ADDITIONAL_DATA_BYTES 128
+
+/*! Indication of whether or not to load the SW image to memory. */
+#define CC_SW_COMP_NO_MEM_LOAD_INDICATION 0xFFFFFFFFFFFFFFFFUL
+
+/*! Indication of product version, stored in certificate version field. */
+#define CC_SB_CERT_VERSION_PROJ_PRD 0x713
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/**
+@}
+ */
+
+
+
diff --git a/include/drivers/arm/cryptocell/cc_rotpk.h b/include/drivers/arm/cryptocell/cc_rotpk.h
new file mode 100644
index 0000000..9398496
--- /dev/null
+++ b/include/drivers/arm/cryptocell/cc_rotpk.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CC_ROTPK_H
+#define _CC_ROTPK_H
+
+int cc_get_rotpk_hash(unsigned char *dst, unsigned int len,
+ unsigned int *flags);
+
+#endif
diff --git a/include/drivers/arm/css/css_mhu.h b/include/drivers/arm/css/css_mhu.h
new file mode 100644
index 0000000..ff04ae4
--- /dev/null
+++ b/include/drivers/arm/css/css_mhu.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CSS_MHU_H
+#define CSS_MHU_H
+
+#include <stdint.h>
+
+void mhu_secure_message_start(unsigned int slot_id);
+void mhu_secure_message_send(unsigned int slot_id);
+uint32_t mhu_secure_message_wait(void);
+void mhu_secure_message_end(unsigned int slot_id);
+
+void mhu_secure_init(void);
+
+#endif /* CSS_MHU_H */
diff --git a/include/drivers/arm/css/css_mhu_doorbell.h b/include/drivers/arm/css/css_mhu_doorbell.h
new file mode 100644
index 0000000..88302fd
--- /dev/null
+++ b/include/drivers/arm/css/css_mhu_doorbell.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CSS_MHU_DOORBELL_H
+#define CSS_MHU_DOORBELL_H
+
+#include <stdint.h>
+
+#include <lib/mmio.h>
+
+/* MHUv2 Frame Base Mask */
+#define MHU_V2_FRAME_BASE_MASK UL(~0xFFF)
+
+/* MHUv2 Control Registers Offsets */
+#define MHU_V2_MSG_NO_CAP_OFFSET UL(0xF80)
+#define MHU_V2_ACCESS_REQ_OFFSET UL(0xF88)
+#define MHU_V2_ACCESS_READY_OFFSET UL(0xF8C)
+
+#define SENDER_REG_STAT(_channel) (0x20 * (_channel))
+#define SENDER_REG_SET(_channel) ((0x20 * (_channel)) + 0xC)
+
+/* Helper macro to ring doorbell */
+#define MHU_RING_DOORBELL(addr, modify_mask, preserve_mask) do { \
+ uint32_t db = mmio_read_32(addr) & (preserve_mask); \
+ mmio_write_32(addr, db | (modify_mask)); \
+ } while (0)
+
+#define MHU_V2_ACCESS_REQUEST(addr) \
+ mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x1)
+
+#define MHU_V2_CLEAR_REQUEST(addr) \
+ mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x0)
+
+#define MHU_V2_IS_ACCESS_READY(addr) \
+ (mmio_read_32((addr) + MHU_V2_ACCESS_READY_OFFSET) & 0x1)
+
+struct scmi_channel_plat_info;
+void mhu_ring_doorbell(struct scmi_channel_plat_info *plat_info);
+void mhuv2_ring_doorbell(struct scmi_channel_plat_info *plat_info);
+
+#endif /* CSS_MHU_DOORBELL_H */
diff --git a/include/drivers/arm/css/css_scp.h b/include/drivers/arm/css/css_scp.h
new file mode 100644
index 0000000..2b506ea
--- /dev/null
+++ b/include/drivers/arm/css/css_scp.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CSS_SCP_H
+#define CSS_SCP_H
+
+#include <stdint.h>
+
+#include <platform_def.h>
+
+#include <lib/cassert.h>
+
+/* Forward declarations */
+struct psci_power_state;
+
+/* API for power management by SCP */
+int css_system_reset2(int is_vendor, int reset_type, u_register_t cookie);
+void css_scp_suspend(const struct psci_power_state *target_state);
+void css_scp_off(const struct psci_power_state *target_state);
+void css_scp_on(u_register_t mpidr);
+int css_scp_get_power_state(u_register_t mpidr, unsigned int power_level);
+void __dead2 css_scp_sys_shutdown(void);
+void __dead2 css_scp_sys_reboot(void);
+void __dead2 css_scp_system_off(int state);
+
+/* API for SCP Boot Image transfer. Return 0 on success, -1 on error */
+int css_scp_boot_image_xfer(void *image, unsigned int image_size);
+
+/*
+ * API to wait for SCP to signal till it's ready after booting the transferred
+ * image.
+ */
+int css_scp_boot_ready(void);
+
+#if CSS_LOAD_SCP_IMAGES
+
+/*
+ * All CSS platforms load SCP_BL2/SCP_BL2U just below BL2 (this is where BL31
+ * usually resides except when ARM_BL31_IN_DRAM is
+ * set). Ensure that SCP_BL2/SCP_BL2U do not overflow into fw_config.
+ */
+CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
+CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
+
+CASSERT(SCP_BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2_overflow);
+CASSERT(SCP_BL2U_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2u_overflow);
+#endif
+
+#endif /* CSS_SCP_H */
diff --git a/include/drivers/arm/css/css_scpi.h b/include/drivers/arm/css/css_scpi.h
new file mode 100644
index 0000000..68fc60a
--- /dev/null
+++ b/include/drivers/arm/css/css_scpi.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CSS_SCPI_H
+#define CSS_SCPI_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * An SCPI command consists of a header and a payload.
+ * The following structure describes the header. It is 64-bit long.
+ */
+typedef struct {
+ /* Command ID */
+ uint32_t id : 7;
+ /* Set ID. Identifies whether this is a standard or extended command. */
+ uint32_t set : 1;
+ /* Sender ID to match a reply. The value is sender specific. */
+ uint32_t sender : 8;
+ /* Size of the payload in bytes (0 - 511) */
+ uint32_t size : 9;
+ uint32_t reserved : 7;
+ /*
+ * Status indicating the success of a command.
+ * See the enum below.
+ */
+ uint32_t status;
+} scpi_cmd_t;
+
+typedef enum {
+ SCPI_SET_NORMAL = 0, /* Normal SCPI commands */
+ SCPI_SET_EXTENDED /* Extended SCPI commands */
+} scpi_set_t;
+
+enum {
+ SCP_OK = 0, /* Success */
+ SCP_E_PARAM, /* Invalid parameter(s) */
+ SCP_E_ALIGN, /* Invalid alignment */
+ SCP_E_SIZE, /* Invalid size */
+ SCP_E_HANDLER, /* Invalid handler or callback */
+ SCP_E_ACCESS, /* Invalid access or permission denied */
+ SCP_E_RANGE, /* Value out of range */
+ SCP_E_TIMEOUT, /* Time out has ocurred */
+ SCP_E_NOMEM, /* Invalid memory area or pointer */
+ SCP_E_PWRSTATE, /* Invalid power state */
+ SCP_E_SUPPORT, /* Feature not supported or disabled */
+ SCPI_E_DEVICE, /* Device error */
+ SCPI_E_BUSY, /* Device is busy */
+};
+
+typedef uint32_t scpi_status_t;
+
+typedef enum {
+ SCPI_CMD_SCP_READY = 0x01,
+ SCPI_CMD_SET_CSS_POWER_STATE = 0x03,
+ SCPI_CMD_GET_CSS_POWER_STATE = 0x04,
+ SCPI_CMD_SYS_POWER_STATE = 0x05
+} scpi_command_t;
+
+/*
+ * Macros to parse SCP response to GET_CSS_POWER_STATE command
+ *
+ * [3:0] : cluster ID
+ * [7:4] : cluster state: 0 = on; 3 = off; rest are reserved
+ * [15:8]: on/off state for individual CPUs in the cluster
+ *
+ * Payload is in little-endian
+ */
+#define CLUSTER_ID(_resp) ((_resp) & 0xf)
+#define CLUSTER_POWER_STATE(_resp) (((_resp) >> 4) & 0xf)
+
+/* Result is a bit mask of CPU on/off states in the cluster */
+#define CPU_POWER_STATE(_resp) (((_resp) >> 8) & 0xff)
+
+/*
+ * For GET_CSS_POWER_STATE, SCP returns the power states of every cluster. The
+ * size of response depends on the number of clusters in the system. The
+ * SCP-to-AP payload contains 2 bytes per cluster. Make sure the response is
+ * large enough to contain power states of a given cluster
+ */
+#define CHECK_RESPONSE(_resp, _clus) \
+ (_resp.size >= (((_clus) + 1) * 2))
+
+typedef enum {
+ scpi_power_on = 0,
+ scpi_power_retention = 1,
+ scpi_power_off = 3,
+} scpi_power_state_t;
+
+typedef enum {
+ scpi_system_shutdown = 0,
+ scpi_system_reboot = 1,
+ scpi_system_reset = 2
+} scpi_system_state_t;
+
+int scpi_wait_ready(void);
+void scpi_set_css_power_state(unsigned int mpidr,
+ scpi_power_state_t cpu_state,
+ scpi_power_state_t cluster_state,
+ scpi_power_state_t css_state);
+int scpi_get_css_power_state(unsigned int mpidr, unsigned int *cpu_state_p,
+ unsigned int *cluster_state_p);
+uint32_t scpi_sys_power_state(scpi_system_state_t system_state);
+
+#endif /* CSS_SCPI_H */
diff --git a/include/drivers/arm/css/scmi.h b/include/drivers/arm/css/scmi.h
new file mode 100644
index 0000000..9dd08e5
--- /dev/null
+++ b/include/drivers/arm/css/scmi.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SCMI_H
+#define SCMI_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+#include <lib/bakery_lock.h>
+#include <lib/psci/psci.h>
+#include <lib/spinlock.h>
+
+/* Supported SCMI Protocol Versions */
+#define SCMI_AP_CORE_PROTO_VER MAKE_SCMI_VERSION(1, 0)
+#define SCMI_PWR_DMN_PROTO_VER MAKE_SCMI_VERSION(2, 0)
+#define SCMI_SYS_PWR_PROTO_VER MAKE_SCMI_VERSION(1, 0)
+
+#define GET_SCMI_MAJOR_VER(ver) (((ver) >> 16) & 0xffff)
+#define GET_SCMI_MINOR_VER(ver) ((ver) & 0xffff)
+
+#define MAKE_SCMI_VERSION(maj, min) \
+ ((((maj) & 0xffff) << 16) | ((min) & 0xffff))
+
+/*
+ * Check that the driver's version is same or higher than the reported SCMI
+ * version. We accept lower major version numbers, as all affected protocols
+ * so far stay backwards compatible. This might need to be revisited in the
+ * future.
+ */
+#define is_scmi_version_compatible(drv, scmi) \
+ ((GET_SCMI_MAJOR_VER(drv) > GET_SCMI_MAJOR_VER(scmi)) || \
+ ((GET_SCMI_MAJOR_VER(drv) == GET_SCMI_MAJOR_VER(scmi)) && \
+ (GET_SCMI_MINOR_VER(drv) <= GET_SCMI_MINOR_VER(scmi))))
+
+/* SCMI Protocol identifiers */
+#define SCMI_PWR_DMN_PROTO_ID 0x11
+#define SCMI_SYS_PWR_PROTO_ID 0x12
+/* The AP core protocol is a CSS platform-specific extension */
+#define SCMI_AP_CORE_PROTO_ID 0x90
+
+/* Mandatory messages IDs for all SCMI protocols */
+#define SCMI_PROTO_VERSION_MSG 0x0
+#define SCMI_PROTO_ATTR_MSG 0x1
+#define SCMI_PROTO_MSG_ATTR_MSG 0x2
+
+/* SCMI power domain management protocol message IDs */
+#define SCMI_PWR_STATE_SET_MSG 0x4
+#define SCMI_PWR_STATE_GET_MSG 0x5
+
+/* SCMI system power management protocol message IDs */
+#define SCMI_SYS_PWR_STATE_SET_MSG 0x3
+#define SCMI_SYS_PWR_STATE_GET_MSG 0x4
+
+/* SCMI AP core protocol message IDs */
+#define SCMI_AP_CORE_RESET_ADDR_SET_MSG 0x3
+#define SCMI_AP_CORE_RESET_ADDR_GET_MSG 0x4
+
+/* Helper macros for system power management protocol commands */
+
+/*
+ * Macros to describe the bit-fields of the `attribute` of system power domain
+ * protocol PROTOCOL_MSG_ATTRIBUTE message.
+ */
+#define SYS_PWR_ATTR_WARM_RESET_SHIFT 31
+#define SCMI_SYS_PWR_WARM_RESET_SUPPORTED (1U << SYS_PWR_ATTR_WARM_RESET_SHIFT)
+
+#define SYS_PWR_ATTR_SUSPEND_SHIFT 30
+#define SCMI_SYS_PWR_SUSPEND_SUPPORTED (1 << SYS_PWR_ATTR_SUSPEND_SHIFT)
+
+/*
+ * Macros to describe the bit-fields of the `flags` parameter of system power
+ * domain protocol SYSTEM_POWER_STATE_SET message.
+ */
+#define SYS_PWR_SET_GRACEFUL_REQ_SHIFT 0
+#define SCMI_SYS_PWR_GRACEFUL_REQ (1 << SYS_PWR_SET_GRACEFUL_REQ_SHIFT)
+#define SCMI_SYS_PWR_FORCEFUL_REQ (0 << SYS_PWR_SET_GRACEFUL_REQ_SHIFT)
+
+/*
+ * Macros to describe the `system_state` parameter of system power
+ * domain protocol SYSTEM_POWER_STATE_SET message.
+ */
+#define SCMI_SYS_PWR_SHUTDOWN 0x0
+#define SCMI_SYS_PWR_COLD_RESET 0x1
+#define SCMI_SYS_PWR_WARM_RESET 0x2
+#define SCMI_SYS_PWR_POWER_UP 0x3
+#define SCMI_SYS_PWR_SUSPEND 0x4
+
+/*
+ * Macros to describe the bit-fields of the `attribute` of AP core protocol
+ * AP_CORE_RESET_ADDR set/get messages.
+ */
+#define SCMI_AP_CORE_LOCK_ATTR_SHIFT 0x0
+#define SCMI_AP_CORE_LOCK_ATTR (1U << SCMI_AP_CORE_LOCK_ATTR_SHIFT)
+
+/* SCMI Error code definitions */
+#define SCMI_E_QUEUED 1
+#define SCMI_E_SUCCESS 0
+#define SCMI_E_NOT_SUPPORTED -1
+#define SCMI_E_INVALID_PARAM -2
+#define SCMI_E_DENIED -3
+#define SCMI_E_NOT_FOUND -4
+#define SCMI_E_OUT_OF_RANGE -5
+#define SCMI_E_BUSY -6
+
+/*
+ * SCMI driver platform information. The details of the doorbell mechanism
+ * can be found in the SCMI specification.
+ */
+typedef struct scmi_channel_plat_info {
+ /* SCMI mailbox memory */
+ uintptr_t scmi_mbx_mem;
+ /* The door bell register address */
+ uintptr_t db_reg_addr;
+ /* The bit mask that need to be preserved when ringing doorbell */
+ uint32_t db_preserve_mask;
+ /* The bit mask that need to be set to ring doorbell */
+ uint32_t db_modify_mask;
+ /* The handler for ringing doorbell */
+ void (*ring_doorbell)(struct scmi_channel_plat_info *plat_info);
+ /* cookie is unused now. But added for future enhancements. */
+ void *cookie;
+} scmi_channel_plat_info_t;
+
+
+#if HW_ASSISTED_COHERENCY
+typedef spinlock_t scmi_lock_t;
+#else
+typedef bakery_lock_t scmi_lock_t;
+#endif
+
+/*
+ * Structure to represent an SCMI channel.
+ */
+typedef struct scmi_channel {
+ scmi_channel_plat_info_t *info;
+ /* The lock for channel access */
+ scmi_lock_t *lock;
+ /* Indicate whether the channel is initialized */
+ int is_initialized;
+} scmi_channel_t;
+
+/* External Common API */
+void *scmi_init(scmi_channel_t *ch);
+int scmi_proto_msg_attr(void *p, uint32_t proto_id, uint32_t command_id,
+ uint32_t *attr);
+int scmi_proto_version(void *p, uint32_t proto_id, uint32_t *version);
+
+/*
+ * Power domain protocol commands. Refer to the SCMI specification for more
+ * details on these commands.
+ */
+int scmi_pwr_state_set(void *p, uint32_t domain_id, uint32_t scmi_pwr_state);
+int scmi_pwr_state_get(void *p, uint32_t domain_id, uint32_t *scmi_pwr_state);
+
+/*
+ * System power management protocol commands. Refer SCMI specification for more
+ * details on these commands.
+ */
+int scmi_sys_pwr_state_set(void *p, uint32_t flags, uint32_t system_state);
+int scmi_sys_pwr_state_get(void *p, uint32_t *system_state);
+
+/* SCMI AP core configuration protocol commands. */
+int scmi_ap_core_set_reset_addr(void *p, uint64_t reset_addr, uint32_t attr);
+int scmi_ap_core_get_reset_addr(void *p, uint64_t *reset_addr, uint32_t *attr);
+
+/* API to get the platform specific SCMI channel information. */
+scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id);
+
+/* API to override default PSCI callbacks for platforms that support SCMI. */
+const plat_psci_ops_t *css_scmi_override_pm_ops(plat_psci_ops_t *ops);
+
+#endif /* SCMI_H */
diff --git a/include/drivers/arm/css/sds.h b/include/drivers/arm/css/sds.h
new file mode 100644
index 0000000..db4cbaa
--- /dev/null
+++ b/include/drivers/arm/css/sds.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SDS_H
+#define SDS_H
+
+/* SDS Structure Identifier defines */
+/* AP CPU INFO defines */
+#define SDS_AP_CPU_INFO_STRUCT_ID 1
+#define SDS_AP_CPU_INFO_PRIMARY_CPUID_OFFSET 0x0
+#define SDS_AP_CPU_INFO_PRIMARY_CPUID_SIZE 0x4
+
+/* ROM Firmware Version defines */
+#define SDS_ROM_VERSION_STRUCT_ID 2
+#define SDS_ROM_VERSION_OFFSET 0x0
+#define SDS_ROM_VERSION_SIZE 0x4
+
+/* RAM Firmware version defines */
+#define SDS_RAM_VERSION_STRUCT_ID 3
+#define SDS_RAM_VERSION_OFFSET 0x0
+#define SDS_RAM_VERSION_SIZE 0x4
+
+/* Platform Identity defines */
+#define SDS_PLATFORM_IDENTITY_STRUCT_ID 4
+#define SDS_PLATFORM_IDENTITY_ID_OFFSET 0x0
+#define SDS_PLATFORM_IDENTITY_ID_SIZE 0x4
+#define SDS_PLATFORM_IDENTITY_ID_CONFIG_SHIFT 28
+#define SDS_PLATFORM_IDENTITY_ID_CONFIG_WIDTH 4
+#define SDS_PLATFORM_IDENTITY_ID_CONFIG_MASK \
+ ((1 << SDS_PLATFORM_IDENTITY_ID_CONFIG_WIDTH) - 1)
+
+#define SDS_PLATFORM_IDENTITY_PLAT_TYPE_OFFSET 0x4
+#define SDS_PLATFORM_IDENTITY_PLAT_TYPE_SIZE 0x4
+
+/* Reset Syndrome defines */
+#define SDS_RESET_SYNDROME_STRUCT_ID 5
+#define SDS_RESET_SYNDROME_OFFSET 0
+#define SDS_RESET_SYNDROME_SIZE 4
+#define SDS_RESET_SYNDROME_POW_ON_RESET_BIT (1 << 0)
+#define SDS_RESET_SYNDROME_SCP_WD_RESET_BIT (1 << 1)
+#define SDS_RESET_SYNDROME_AP_WD_RESET_BIT (1 << 2)
+#define SDS_RESET_SYNDROME_SYS_RESET_REQ_BIT (1 << 3)
+#define SDS_RESET_SYNDROME_M3_LOCKUP_BIT (1 << 4)
+
+/* SCP Firmware Feature Availability defines */
+#define SDS_FEATURE_AVAIL_STRUCT_ID 6
+#define SDS_FEATURE_AVAIL_OFFSET 0
+#define SDS_FEATURE_AVAIL_SIZE 4
+#define SDS_FEATURE_AVAIL_SCP_RAM_READY_BIT (1 << 0)
+#define SDS_FEATURE_AVAIL_DMC_READY_BIT (1 << 1)
+#define SDS_FEATURE_AVAIL_MSG_IF_READY_BIT (1 << 2)
+
+/* SCP BL2 Image Metadata defines */
+#define SDS_SCP_IMG_STRUCT_ID 9
+#define SDS_SCP_IMG_FLAG_OFFSET 0
+#define SDS_SCP_IMG_FLAG_SIZE 4
+#define SDS_SCP_IMG_VALID_FLAG_BIT (1 << 0)
+#define SDS_SCP_IMG_ADDR_OFFSET 4
+#define SDS_SCP_IMG_ADDR_SIZE 4
+#define SDS_SCP_IMG_SIZE_OFFSET 8
+#define SDS_SCP_IMG_SIZE_SIZE 4
+
+/* SDS Driver Error Codes */
+#define SDS_OK 0
+#define SDS_ERR_FAIL -1
+#define SDS_ERR_INVALID_PARAMS -2
+#define SDS_ERR_STRUCT_NOT_FOUND -3
+#define SDS_ERR_STRUCT_NOT_FINALIZED -4
+
+#ifndef __ASSEMBLER__
+#include <stddef.h>
+#include <stdint.h>
+
+typedef enum {
+ SDS_ACCESS_MODE_NON_CACHED,
+ SDS_ACCESS_MODE_CACHED,
+} sds_access_mode_t;
+
+int sds_init(void);
+int sds_struct_exists(unsigned int structure_id);
+int sds_struct_read(uint32_t structure_id, unsigned int fld_off, void *data,
+ size_t size, sds_access_mode_t mode);
+int sds_struct_write(uint32_t structure_id, unsigned int fld_off, void *data,
+ size_t size, sds_access_mode_t mode);
+#endif /*__ASSEMBLER__ */
+
+#endif /* SDS_H */
diff --git a/include/drivers/arm/dcc.h b/include/drivers/arm/dcc.h
new file mode 100644
index 0000000..1f1fd03
--- /dev/null
+++ b/include/drivers/arm/dcc.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2021, Xilinx Inc.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DCC_H
+#define DCC_H
+
+#include <stdint.h>
+#include <drivers/console.h>
+
+/*
+ * Initialize a new dcc console instance and register it with the console
+ * framework.
+ */
+int console_dcc_register(void);
+
+#endif /* DCC */
diff --git a/include/drivers/arm/ethosn.h b/include/drivers/arm/ethosn.h
new file mode 100644
index 0000000..dbaf16c
--- /dev/null
+++ b/include/drivers/arm/ethosn.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ETHOSN_H
+#define ETHOSN_H
+
+#include <lib/smccc.h>
+
+/* Function numbers */
+#define ETHOSN_FNUM_VERSION U(0x50)
+#define ETHOSN_FNUM_IS_SEC U(0x51)
+#define ETHOSN_FNUM_HARD_RESET U(0x52)
+#define ETHOSN_FNUM_SOFT_RESET U(0x53)
+/* 0x54-0x5F reserved for future use */
+
+/* SMC64 function IDs */
+#define ETHOSN_FID_64(func_num) U(0xC2000000 | func_num)
+#define ETHOSN_FID_VERSION_64 ETHOSN_FID_64(ETHOSN_FNUM_VERSION)
+#define ETHOSN_FID_IS_SEC_64 ETHOSN_FID_64(ETHOSN_FNUM_IS_SEC)
+#define ETHOSN_FID_HARD_RESET_64 ETHOSN_FID_64(ETHOSN_FNUM_HARD_RESET)
+#define ETHOSN_FID_SOFT_RESET_64 ETHOSN_FID_64(ETHOSN_FNUM_SOFT_RESET)
+
+/* SMC32 function IDs */
+#define ETHOSN_FID_32(func_num) U(0x82000000 | func_num)
+#define ETHOSN_FID_VERSION_32 ETHOSN_FID_32(ETHOSN_FNUM_VERSION)
+#define ETHOSN_FID_IS_SEC_32 ETHOSN_FID_32(ETHOSN_FNUM_IS_SEC)
+#define ETHOSN_FID_HARD_RESET_32 ETHOSN_FID_32(ETHOSN_FNUM_HARD_RESET)
+#define ETHOSN_FID_SOFT_RESET_32 ETHOSN_FID_32(ETHOSN_FNUM_SOFT_RESET)
+
+#define ETHOSN_NUM_SMC_CALLS 8
+
+/* Macro to identify function calls */
+#define ETHOSN_FID_MASK U(0xFFF0)
+#define ETHOSN_FID_VALUE U(0x50)
+#define is_ethosn_fid(_fid) (((_fid) & ETHOSN_FID_MASK) == ETHOSN_FID_VALUE)
+
+/* Service version */
+#define ETHOSN_VERSION_MAJOR U(2)
+#define ETHOSN_VERSION_MINOR U(0)
+
+/* Return codes for function calls */
+#define ETHOSN_SUCCESS 0
+#define ETHOSN_NOT_SUPPORTED -1
+/* -2 Reserved for NOT_REQUIRED */
+/* -3 Reserved for INVALID_PARAMETER */
+#define ETHOSN_FAILURE -4
+#define ETHOSN_UNKNOWN_CORE_ADDRESS -5
+#define ETHOSN_UNKNOWN_ALLOCATOR_IDX -6
+
+uintptr_t ethosn_smc_handler(uint32_t smc_fid,
+ u_register_t core_addr,
+ u_register_t asset_alloc_idx,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags);
+
+#endif /* ETHOSN_H */
diff --git a/include/drivers/arm/fvp/fvp_pwrc.h b/include/drivers/arm/fvp/fvp_pwrc.h
new file mode 100644
index 0000000..39e2516
--- /dev/null
+++ b/include/drivers/arm/fvp/fvp_pwrc.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FVP_PWRC_H
+#define FVP_PWRC_H
+
+/* FVP Power controller register offset etc */
+#define PPOFFR_OFF U(0x0)
+#define PPONR_OFF U(0x4)
+#define PCOFFR_OFF U(0x8)
+#define PWKUPR_OFF U(0xc)
+#define PSYSR_OFF U(0x10)
+
+#define PWKUPR_WEN BIT_32(31)
+
+#define PSYSR_AFF_L2 BIT_32(31)
+#define PSYSR_AFF_L1 BIT_32(30)
+#define PSYSR_AFF_L0 BIT_32(29)
+#define PSYSR_WEN BIT_32(28)
+#define PSYSR_PC BIT_32(27)
+#define PSYSR_PP BIT_32(26)
+
+#define PSYSR_WK_SHIFT 24
+#define PSYSR_WK_WIDTH 0x2
+#define PSYSR_WK_MASK ((1U << PSYSR_WK_WIDTH) - 1U)
+#define PSYSR_WK(x) ((x) >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK
+
+#define WKUP_COLD U(0x0)
+#define WKUP_RESET U(0x1)
+#define WKUP_PPONR U(0x2)
+#define WKUP_GICREQ U(0x3)
+
+#define PSYSR_INVALID U(0xffffffff)
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+/*******************************************************************************
+ * Function & variable prototypes
+ ******************************************************************************/
+void fvp_pwrc_write_pcoffr(u_register_t mpidr);
+void fvp_pwrc_write_ppoffr(u_register_t mpidr);
+void fvp_pwrc_write_pponr(u_register_t mpidr);
+void fvp_pwrc_set_wen(u_register_t mpidr);
+void fvp_pwrc_clr_wen(u_register_t mpidr);
+unsigned int fvp_pwrc_read_psysr(u_register_t mpidr);
+unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr);
+
+#endif /*__ASSEMBLER__*/
+
+#endif /* FVP_PWRC_H */
diff --git a/include/drivers/arm/gic600_multichip.h b/include/drivers/arm/gic600_multichip.h
new file mode 100644
index 0000000..bda406b
--- /dev/null
+++ b/include/drivers/arm/gic600_multichip.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2019, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GIC600_MULTICHIP_H
+#define GIC600_MULTICHIP_H
+
+#include <stdint.h>
+
+/*
+ * GIC-600 microarchitecture supports coherent multichip environments containing
+ * up to 16 chips.
+ */
+#define GIC600_MAX_MULTICHIP 16
+
+/* SPI IDs array consist of min and max ids */
+#define GIC600_SPI_IDS_SIZE 2
+
+/*******************************************************************************
+ * GIC-600 multichip data structure describes platform specific attributes
+ * related to GIC-600 multichip. Platform port is expected to define these
+ * attributes to initialize the multichip related registers and create
+ * successful connections between the GIC-600s in a multichip system.
+ *
+ * The 'rt_owner_base' field contains the base address of the GIC Distributor
+ * which owns the routing table.
+ *
+ * The 'rt_owner' field contains the chip number which owns the routing table.
+ * Chip number or chip_id starts from 0.
+ *
+ * The 'chip_count' field contains the total number of chips in a multichip
+ * system. This should match the number of entries in 'chip_addrs' and 'spi_ids'
+ * fields.
+ *
+ * The 'chip_addrs' field contains array of chip addresses. These addresses are
+ * implementation specific values.
+ *
+ * The 'spi_ids' field contains array of minimum and maximum SPI interrupt ids
+ * that each chip owns. Note that SPI interrupt ids can range from 32 to 960 and
+ * it should be group of 32 (i.e., SPI minimum and (SPI maximum + 1) should be
+ * a multiple of 32). If a chip doesn't own any SPI interrupts a value of {0, 0}
+ * should be passed.
+ ******************************************************************************/
+struct gic600_multichip_data {
+ uintptr_t rt_owner_base;
+ unsigned int rt_owner;
+ unsigned int chip_count;
+ uint64_t chip_addrs[GIC600_MAX_MULTICHIP];
+ unsigned int spi_ids[GIC600_MAX_MULTICHIP][GIC600_SPI_IDS_SIZE];
+};
+
+void gic600_multichip_init(struct gic600_multichip_data *multichip_data);
+#endif /* GIC600_MULTICHIP_H */
diff --git a/include/drivers/arm/gic600ae_fmu.h b/include/drivers/arm/gic600ae_fmu.h
new file mode 100644
index 0000000..88b87b9
--- /dev/null
+++ b/include/drivers/arm/gic600ae_fmu.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GIC600AE_FMU_H
+#define GIC600AE_FMU_H
+
+/*******************************************************************************
+ * GIC600-AE FMU register offsets and constants
+ ******************************************************************************/
+#define GICFMU_ERRFR_LO U(0x000)
+#define GICFMU_ERRFR_HI U(0x004)
+#define GICFMU_ERRCTLR_LO U(0x008)
+#define GICFMU_ERRCTLR_HI U(0x00C)
+#define GICFMU_ERRSTATUS_LO U(0x010)
+#define GICFMU_ERRSTATUS_HI U(0x014)
+#define GICFMU_ERRGSR_LO U(0xE00)
+#define GICFMU_ERRGSR_HI U(0xE04)
+#define GICFMU_KEY U(0xEA0)
+#define GICFMU_PINGCTLR U(0xEA4)
+#define GICFMU_PINGNOW U(0xEA8)
+#define GICFMU_SMEN U(0xEB0)
+#define GICFMU_SMINJERR U(0xEB4)
+#define GICFMU_PINGMASK_LO U(0xEC0)
+#define GICFMU_PINGMASK_HI U(0xEC4)
+#define GICFMU_STATUS U(0xF00)
+#define GICFMU_ERRIDR U(0xFC8)
+
+/* ERRCTLR bits */
+#define FMU_ERRCTLR_ED_BIT BIT(0)
+#define FMU_ERRCTLR_CE_EN_BIT BIT(1)
+#define FMU_ERRCTLR_UI_BIT BIT(2)
+#define FMU_ERRCTLR_CI_BIT BIT(3)
+
+/* SMEN constants */
+#define FMU_SMEN_BLK_SHIFT U(8)
+#define FMU_SMEN_SMID_SHIFT U(24)
+#define FMU_SMEN_EN_BIT BIT(0)
+
+/* Error record IDs */
+#define FMU_BLK_GICD U(0)
+#define FMU_BLK_SPICOL U(1)
+#define FMU_BLK_WAKERQ U(2)
+#define FMU_BLK_ITS0 U(4)
+#define FMU_BLK_ITS1 U(5)
+#define FMU_BLK_ITS2 U(6)
+#define FMU_BLK_ITS3 U(7)
+#define FMU_BLK_ITS4 U(8)
+#define FMU_BLK_ITS5 U(9)
+#define FMU_BLK_ITS6 U(10)
+#define FMU_BLK_ITS7 U(11)
+#define FMU_BLK_PPI0 U(12)
+#define FMU_BLK_PPI1 U(13)
+#define FMU_BLK_PPI2 U(14)
+#define FMU_BLK_PPI3 U(15)
+#define FMU_BLK_PPI4 U(16)
+#define FMU_BLK_PPI5 U(17)
+#define FMU_BLK_PPI6 U(18)
+#define FMU_BLK_PPI7 U(19)
+#define FMU_BLK_PPI8 U(20)
+#define FMU_BLK_PPI9 U(21)
+#define FMU_BLK_PPI10 U(22)
+#define FMU_BLK_PPI11 U(23)
+#define FMU_BLK_PPI12 U(24)
+#define FMU_BLK_PPI13 U(25)
+#define FMU_BLK_PPI14 U(26)
+#define FMU_BLK_PPI15 U(27)
+#define FMU_BLK_PPI16 U(28)
+#define FMU_BLK_PPI17 U(29)
+#define FMU_BLK_PPI18 U(30)
+#define FMU_BLK_PPI19 U(31)
+#define FMU_BLK_PPI20 U(32)
+#define FMU_BLK_PPI21 U(33)
+#define FMU_BLK_PPI22 U(34)
+#define FMU_BLK_PPI23 U(35)
+#define FMU_BLK_PPI24 U(36)
+#define FMU_BLK_PPI25 U(37)
+#define FMU_BLK_PPI26 U(38)
+#define FMU_BLK_PPI27 U(39)
+#define FMU_BLK_PPI28 U(40)
+#define FMU_BLK_PPI29 U(41)
+#define FMU_BLK_PPI30 U(42)
+#define FMU_BLK_PPI31 U(43)
+#define FMU_BLK_PRESENT_MASK U(0xFFFFFFFFFFF)
+
+/* Safety Mechamism limit */
+#define FMU_SMID_GICD_MAX U(33)
+#define FMU_SMID_PPI_MAX U(12)
+#define FMU_SMID_ITS_MAX U(14)
+#define FMU_SMID_SPICOL_MAX U(5)
+#define FMU_SMID_WAKERQ_MAX U(2)
+
+/* MBIST Safety Mechanism ID */
+#define GICD_MBIST_REQ_ERROR U(23)
+#define GICD_FMU_CLKGATE_ERROR U(33)
+#define PPI_MBIST_REQ_ERROR U(10)
+#define PPI_FMU_CLKGATE_ERROR U(12)
+#define ITS_MBIST_REQ_ERROR U(13)
+#define ITS_FMU_CLKGATE_ERROR U(14)
+
+/* ERRSTATUS bits */
+#define FMU_ERRSTATUS_BLKID_SHIFT U(32)
+#define FMU_ERRSTATUS_BLKID_MASK U(0xFF)
+#define FMU_ERRSTATUS_V_BIT BIT(30)
+#define FMU_ERRSTATUS_UE_BIT BIT(29)
+#define FMU_ERRSTATUS_OV_BIT BIT(27)
+#define FMU_ERRSTATUS_CE_BITS (BIT(25) | BIT(24))
+#define FMU_ERRSTATUS_CLEAR (FMU_ERRSTATUS_V_BIT | FMU_ERRSTATUS_UE_BIT | \
+ FMU_ERRSTATUS_OV_BIT | FMU_ERRSTATUS_CE_BITS)
+#define FMU_ERRSTATUS_IERR_MASK U(0xFF)
+#define FMU_ERRSTATUS_IERR_SHIFT U(8)
+#define FMU_ERRSTATUS_SERR_MASK U(0xFF)
+
+/* PINGCTLR constants */
+#define FMU_PINGCTLR_INTDIFF_SHIFT U(16)
+#define FMU_PINGCTLR_TIMEOUTVAL_SHIFT U(4)
+#define FMU_PINGCTLR_EN_BIT BIT(0)
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+#include <arch_helpers.h>
+
+/*******************************************************************************
+ * GIC600 FMU EL3 driver API
+ ******************************************************************************/
+uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n);
+uint64_t gic_fmu_read_errctlr(uintptr_t base, unsigned int n);
+uint64_t gic_fmu_read_errstatus(uintptr_t base, unsigned int n);
+uint64_t gic_fmu_read_errgsr(uintptr_t base);
+uint32_t gic_fmu_read_pingctlr(uintptr_t base);
+uint32_t gic_fmu_read_pingnow(uintptr_t base);
+uint64_t gic_fmu_read_pingmask(uintptr_t base);
+uint32_t gic_fmu_read_status(uintptr_t base);
+uint32_t gic_fmu_read_erridr(uintptr_t base);
+void gic_fmu_write_errctlr(uintptr_t base, unsigned int n, uint64_t val);
+void gic_fmu_write_errstatus(uintptr_t base, unsigned int n, uint64_t val);
+void gic_fmu_write_pingctlr(uintptr_t base, uint32_t val);
+void gic_fmu_write_pingnow(uintptr_t base, uint32_t val);
+void gic_fmu_write_smen(uintptr_t base, uint32_t val);
+void gic_fmu_write_sminjerr(uintptr_t base, uint32_t val);
+void gic_fmu_write_pingmask(uintptr_t base, uint64_t val);
+void gic_fmu_disable_all_sm_blkid(uintptr_t base, unsigned int blkid);
+
+void gic600_fmu_init(uint64_t base, uint64_t blk_present_mask, bool errctlr_ce_en, bool errctlr_ue_en);
+void gic600_fmu_enable_ping(uint64_t base, uint64_t blk_present_mask,
+ unsigned int timeout_val, unsigned int interval_diff);
+void gic600_fmu_print_sm_info(uint64_t base, unsigned int blk, unsigned int smid);
+int gic600_fmu_probe(uint64_t base, int *probe_data);
+int gic600_fmu_ras_handler(uint64_t base, int probe_data);
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* GIC600AE_FMU_H */
diff --git a/include/drivers/arm/gic_common.h b/include/drivers/arm/gic_common.h
new file mode 100644
index 0000000..dc23721
--- /dev/null
+++ b/include/drivers/arm/gic_common.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GIC_COMMON_H
+#define GIC_COMMON_H
+
+#include <lib/utils_def.h>
+
+/*******************************************************************************
+ * GIC Distributor interface general definitions
+ ******************************************************************************/
+/* Constants to categorise interrupts */
+#define MIN_SGI_ID U(0)
+#define MIN_SEC_SGI_ID U(8)
+#define MIN_PPI_ID U(16)
+#define MIN_SPI_ID U(32)
+#define MAX_SPI_ID U(1019)
+
+#define TOTAL_SPI_INTR_NUM (MAX_SPI_ID - MIN_SPI_ID + U(1))
+#define TOTAL_PCPU_INTR_NUM (MIN_SPI_ID - MIN_SGI_ID)
+
+/* Mask for the priority field common to all GIC interfaces */
+#define GIC_PRI_MASK U(0xff)
+
+/* Mask for the configuration field common to all GIC interfaces */
+#define GIC_CFG_MASK U(0x3)
+
+/* Constant to indicate a spurious interrupt in all GIC versions */
+#define GIC_SPURIOUS_INTERRUPT U(1023)
+
+/* Interrupt configurations: 2-bit fields with LSB reserved */
+#define GIC_INTR_CFG_LEVEL (0 << 1)
+#define GIC_INTR_CFG_EDGE (1 << 1)
+
+/* Highest possible interrupt priorities */
+#define GIC_HIGHEST_SEC_PRIORITY U(0x00)
+#define GIC_HIGHEST_NS_PRIORITY U(0x80)
+
+/*******************************************************************************
+ * Common GIC Distributor interface register offsets
+ ******************************************************************************/
+#define GICD_CTLR U(0x0)
+#define GICD_TYPER U(0x4)
+#define GICD_IIDR U(0x8)
+#define GICD_IGROUPR U(0x80)
+#define GICD_ISENABLER U(0x100)
+#define GICD_ICENABLER U(0x180)
+#define GICD_ISPENDR U(0x200)
+#define GICD_ICPENDR U(0x280)
+#define GICD_ISACTIVER U(0x300)
+#define GICD_ICACTIVER U(0x380)
+#define GICD_IPRIORITYR U(0x400)
+#define GICD_ICFGR U(0xc00)
+#define GICD_NSACR U(0xe00)
+
+/* GICD_CTLR bit definitions */
+#define CTLR_ENABLE_G0_SHIFT 0
+#define CTLR_ENABLE_G0_MASK U(0x1)
+#define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT)
+
+/*******************************************************************************
+ * Common GIC Distributor interface register constants
+ ******************************************************************************/
+#define PIDR2_ARCH_REV_SHIFT 4
+#define PIDR2_ARCH_REV_MASK U(0xf)
+
+/* GIC revision as reported by PIDR2.ArchRev register field */
+#define ARCH_REV_GICV1 U(0x1)
+#define ARCH_REV_GICV2 U(0x2)
+#define ARCH_REV_GICV3 U(0x3)
+#define ARCH_REV_GICV4 U(0x4)
+
+#define IGROUPR_SHIFT 5
+#define ISENABLER_SHIFT 5
+#define ICENABLER_SHIFT ISENABLER_SHIFT
+#define ISPENDR_SHIFT 5
+#define ICPENDR_SHIFT ISPENDR_SHIFT
+#define ISACTIVER_SHIFT 5
+#define ICACTIVER_SHIFT ISACTIVER_SHIFT
+#define IPRIORITYR_SHIFT 2
+#define ITARGETSR_SHIFT 2
+#define ICFGR_SHIFT 4
+#define NSACR_SHIFT 4
+
+/* GICD_TYPER shifts and masks */
+#define TYPER_IT_LINES_NO_SHIFT U(0)
+#define TYPER_IT_LINES_NO_MASK U(0x1f)
+
+/* Value used to initialize Normal world interrupt priorities four at a time */
+#define GICD_IPRIORITYR_DEF_VAL \
+ (GIC_HIGHEST_NS_PRIORITY | \
+ (GIC_HIGHEST_NS_PRIORITY << 8) | \
+ (GIC_HIGHEST_NS_PRIORITY << 16) | \
+ (GIC_HIGHEST_NS_PRIORITY << 24))
+
+#endif /* GIC_COMMON_H */
diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h
new file mode 100644
index 0000000..cfc168d
--- /dev/null
+++ b/include/drivers/arm/gicv2.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GICV2_H
+#define GICV2_H
+
+#include <drivers/arm/gic_common.h>
+#include <platform_def.h>
+
+/*******************************************************************************
+ * GICv2 miscellaneous definitions
+ ******************************************************************************/
+
+/* Interrupt group definitions */
+#define GICV2_INTR_GROUP0 U(0)
+#define GICV2_INTR_GROUP1 U(1)
+
+/* Interrupt IDs reported by the HPPIR and IAR registers */
+#define PENDING_G1_INTID U(1022)
+
+/* GICv2 can only target up to 8 PEs */
+#define GICV2_MAX_TARGET_PE U(8)
+
+/*******************************************************************************
+ * GICv2 specific Distributor interface register offsets and constants.
+ ******************************************************************************/
+#define GICD_ITARGETSR U(0x800)
+#define GICD_SGIR U(0xF00)
+#define GICD_CPENDSGIR U(0xF10)
+#define GICD_SPENDSGIR U(0xF20)
+
+/*
+ * Some GICv2 implementations violate the specification and have this register
+ * at a different address. Allow overriding it in platform_def.h as workaround.
+ */
+#ifndef GICD_PIDR2_GICV2
+#define GICD_PIDR2_GICV2 U(0xFE8)
+#endif
+
+#define ITARGETSR_SHIFT 2
+#define GIC_TARGET_CPU_MASK U(0xff)
+
+#define CPENDSGIR_SHIFT 2
+#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT
+
+#define SGIR_TGTLSTFLT_SHIFT 24
+#define SGIR_TGTLSTFLT_MASK U(0x3)
+#define SGIR_TGTLST_SHIFT 16
+#define SGIR_TGTLST_MASK U(0xff)
+#define SGIR_NSATT (U(0x1) << 16)
+#define SGIR_INTID_MASK ULL(0xf)
+
+#define SGIR_TGT_SPECIFIC U(0)
+
+#define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, nsatt, intid) \
+ ((((tgt_lst_flt) & SGIR_TGTLSTFLT_MASK) << SGIR_TGTLSTFLT_SHIFT) | \
+ (((tgt) & SGIR_TGTLST_MASK) << SGIR_TGTLST_SHIFT) | \
+ ((nsatt) ? SGIR_NSATT : U(0)) | \
+ ((intid) & SGIR_INTID_MASK))
+
+/*******************************************************************************
+ * GICv2 specific CPU interface register offsets and constants.
+ ******************************************************************************/
+/* Physical CPU Interface registers */
+#define GICC_CTLR U(0x0)
+#define GICC_PMR U(0x4)
+#define GICC_BPR U(0x8)
+#define GICC_IAR U(0xC)
+#define GICC_EOIR U(0x10)
+#define GICC_RPR U(0x14)
+#define GICC_HPPIR U(0x18)
+#define GICC_AHPPIR U(0x28)
+#define GICC_IIDR U(0xFC)
+#define GICC_DIR U(0x1000)
+#define GICC_PRIODROP GICC_EOIR
+
+/* GICC_CTLR bit definitions */
+#define EOI_MODE_NS BIT_32(10)
+#define EOI_MODE_S BIT_32(9)
+#define IRQ_BYP_DIS_GRP1 BIT_32(8)
+#define FIQ_BYP_DIS_GRP1 BIT_32(7)
+#define IRQ_BYP_DIS_GRP0 BIT_32(6)
+#define FIQ_BYP_DIS_GRP0 BIT_32(5)
+#define CBPR BIT_32(4)
+#define FIQ_EN_SHIFT 3
+#define FIQ_EN_BIT BIT_32(FIQ_EN_SHIFT)
+#define ACK_CTL BIT_32(2)
+
+/* GICC_IIDR bit masks and shifts */
+#define GICC_IIDR_PID_SHIFT 20
+#define GICC_IIDR_ARCH_SHIFT 16
+#define GICC_IIDR_REV_SHIFT 12
+#define GICC_IIDR_IMP_SHIFT 0
+
+#define GICC_IIDR_PID_MASK U(0xfff)
+#define GICC_IIDR_ARCH_MASK U(0xf)
+#define GICC_IIDR_REV_MASK U(0xf)
+#define GICC_IIDR_IMP_MASK U(0xfff)
+
+/* HYP view virtual CPU Interface registers */
+#define GICH_CTL U(0x0)
+#define GICH_VTR U(0x4)
+#define GICH_ELRSR0 U(0x30)
+#define GICH_ELRSR1 U(0x34)
+#define GICH_APR0 U(0xF0)
+#define GICH_LR_BASE U(0x100)
+
+/* Virtual CPU Interface registers */
+#define GICV_CTL U(0x0)
+#define GICV_PRIMASK U(0x4)
+#define GICV_BP U(0x8)
+#define GICV_INTACK U(0xC)
+#define GICV_EOI U(0x10)
+#define GICV_RUNNINGPRI U(0x14)
+#define GICV_HIGHESTPEND U(0x18)
+#define GICV_DEACTIVATE U(0x1000)
+
+/* GICD_CTLR bit definitions */
+#define CTLR_ENABLE_G1_SHIFT 1
+#define CTLR_ENABLE_G1_MASK U(0x1)
+#define CTLR_ENABLE_G1_BIT BIT_32(CTLR_ENABLE_G1_SHIFT)
+
+/* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
+#define INT_ID_MASK U(0x3ff)
+
+#ifndef __ASSEMBLER__
+
+#include <cdefs.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <common/interrupt_props.h>
+
+/*******************************************************************************
+ * This structure describes some of the implementation defined attributes of
+ * the GICv2 IP. It is used by the platform port to specify these attributes
+ * in order to initialize the GICv2 driver. The attributes are described
+ * below.
+ *
+ * The 'gicd_base' field contains the base address of the Distributor interface
+ * programmer's view.
+ *
+ * The 'gicc_base' field contains the base address of the CPU Interface
+ * programmer's view.
+ *
+ * The 'target_masks' is a pointer to an array containing 'target_masks_num'
+ * elements. The GIC driver will populate the array with per-PE target mask to
+ * use to when targeting interrupts.
+ *
+ * The 'interrupt_props' field is a pointer to an array that enumerates secure
+ * interrupts and their properties. If this field is not NULL, both
+ * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored.
+ *
+ * The 'interrupt_props_num' field contains the number of entries in the
+ * 'interrupt_props' array. If this field is non-zero, 'g0_interrupt_num' is
+ * ignored.
+ ******************************************************************************/
+typedef struct gicv2_driver_data {
+ uintptr_t gicd_base;
+ uintptr_t gicc_base;
+ unsigned int *target_masks;
+ unsigned int target_masks_num;
+ const interrupt_prop_t *interrupt_props;
+ unsigned int interrupt_props_num;
+} gicv2_driver_data_t;
+
+/*******************************************************************************
+ * Function prototypes
+ ******************************************************************************/
+void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data);
+void gicv2_distif_init(void);
+void gicv2_pcpu_distif_init(void);
+void gicv2_cpuif_enable(void);
+void gicv2_cpuif_disable(void);
+unsigned int gicv2_is_fiq_enabled(void);
+unsigned int gicv2_get_pending_interrupt_type(void);
+unsigned int gicv2_get_pending_interrupt_id(void);
+unsigned int gicv2_acknowledge_interrupt(void);
+void gicv2_end_of_interrupt(unsigned int id);
+unsigned int gicv2_get_interrupt_group(unsigned int id);
+unsigned int gicv2_get_running_priority(void);
+void gicv2_set_pe_target_mask(unsigned int proc_num);
+unsigned int gicv2_get_interrupt_active(unsigned int id);
+void gicv2_enable_interrupt(unsigned int id);
+void gicv2_disable_interrupt(unsigned int id);
+void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority);
+void gicv2_set_interrupt_type(unsigned int id, unsigned int type);
+void gicv2_raise_sgi(int sgi_num, bool ns, int proc_num);
+void gicv2_set_spi_routing(unsigned int id, int proc_num);
+void gicv2_set_interrupt_pending(unsigned int id);
+void gicv2_clear_interrupt_pending(unsigned int id);
+unsigned int gicv2_set_pmr(unsigned int mask);
+void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg);
+
+#endif /* __ASSEMBLER__ */
+#endif /* GICV2_H */
diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h
new file mode 100644
index 0000000..5bb22fd
--- /dev/null
+++ b/include/drivers/arm/gicv3.h
@@ -0,0 +1,605 @@
+/*
+ * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GICV3_H
+#define GICV3_H
+
+/*******************************************************************************
+ * GICv3 and 3.1 miscellaneous definitions
+ ******************************************************************************/
+/* Interrupt group definitions */
+#define INTR_GROUP1S U(0)
+#define INTR_GROUP0 U(1)
+#define INTR_GROUP1NS U(2)
+
+/* Interrupt IDs reported by the HPPIR and IAR registers */
+#define PENDING_G1S_INTID U(1020)
+#define PENDING_G1NS_INTID U(1021)
+
+/* Constant to categorize LPI interrupt */
+#define MIN_LPI_ID U(8192)
+
+/* GICv3 can only target up to 16 PEs with SGI */
+#define GICV3_MAX_SGI_TARGETS U(16)
+
+/* PPIs INTIDs 16-31 */
+#define MAX_PPI_ID U(31)
+
+#if GIC_EXT_INTID
+
+/* GICv3.1 extended PPIs INTIDs 1056-1119 */
+#define MIN_EPPI_ID U(1056)
+#define MAX_EPPI_ID U(1119)
+
+/* Total number of GICv3.1 EPPIs */
+#define TOTAL_EPPI_INTR_NUM (MAX_EPPI_ID - MIN_EPPI_ID + U(1))
+
+/* Total number of GICv3.1 PPIs and EPPIs */
+#define TOTAL_PRIVATE_INTR_NUM (TOTAL_PCPU_INTR_NUM + TOTAL_EPPI_INTR_NUM)
+
+/* GICv3.1 extended SPIs INTIDs 4096 - 5119 */
+#define MIN_ESPI_ID U(4096)
+#define MAX_ESPI_ID U(5119)
+
+/* Total number of GICv3.1 ESPIs */
+#define TOTAL_ESPI_INTR_NUM (MAX_ESPI_ID - MIN_ESPI_ID + U(1))
+
+/* Total number of GICv3.1 SPIs and ESPIs */
+#define TOTAL_SHARED_INTR_NUM (TOTAL_SPI_INTR_NUM + TOTAL_ESPI_INTR_NUM)
+
+/* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */
+#define IS_SGI_PPI(id) (((id) <= MAX_PPI_ID) || \
+ (((id) >= MIN_EPPI_ID) && \
+ ((id) <= MAX_EPPI_ID)))
+
+/* SPIs: 32-1019, ESPIs: 4096-5119 */
+#define IS_SPI(id) ((((id) >= MIN_SPI_ID) && \
+ ((id) <= MAX_SPI_ID)) || \
+ (((id) >= MIN_ESPI_ID) && \
+ ((id) <= MAX_ESPI_ID)))
+#else /* GICv3 */
+
+/* Total number of GICv3 PPIs */
+#define TOTAL_PRIVATE_INTR_NUM TOTAL_PCPU_INTR_NUM
+
+/* Total number of GICv3 SPIs */
+#define TOTAL_SHARED_INTR_NUM TOTAL_SPI_INTR_NUM
+
+/* SGIs: 0-15, PPIs: 16-31 */
+#define IS_SGI_PPI(id) ((id) <= MAX_PPI_ID)
+
+/* SPIs: 32-1019 */
+#define IS_SPI(id) (((id) >= MIN_SPI_ID) && ((id) <= MAX_SPI_ID))
+
+#endif /* GIC_EXT_INTID */
+
+#define GIC_REV(r, p) ((r << 4) | p)
+
+/*******************************************************************************
+ * GICv3 and 3.1 specific Distributor interface register offsets and constants
+ ******************************************************************************/
+#define GICD_TYPER2 U(0x0c)
+#define GICD_STATUSR U(0x10)
+#define GICD_SETSPI_NSR U(0x40)
+#define GICD_CLRSPI_NSR U(0x48)
+#define GICD_SETSPI_SR U(0x50)
+#define GICD_CLRSPI_SR U(0x58)
+#define GICD_IGRPMODR U(0xd00)
+#define GICD_IGROUPRE U(0x1000)
+#define GICD_ISENABLERE U(0x1200)
+#define GICD_ICENABLERE U(0x1400)
+#define GICD_ISPENDRE U(0x1600)
+#define GICD_ICPENDRE U(0x1800)
+#define GICD_ISACTIVERE U(0x1a00)
+#define GICD_ICACTIVERE U(0x1c00)
+#define GICD_IPRIORITYRE U(0x2000)
+#define GICD_ICFGRE U(0x3000)
+#define GICD_IGRPMODRE U(0x3400)
+#define GICD_NSACRE U(0x3600)
+/*
+ * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt ID
+ * and n >= 32, making the effective offset as 0x6100
+ */
+#define GICD_IROUTER U(0x6000)
+#define GICD_IROUTERE U(0x8000)
+
+#define GICD_PIDR0_GICV3 U(0xffe0)
+#define GICD_PIDR1_GICV3 U(0xffe4)
+#define GICD_PIDR2_GICV3 U(0xffe8)
+
+#define IGRPMODR_SHIFT 5
+
+/* GICD_CTLR bit definitions */
+#define CTLR_ENABLE_G1NS_SHIFT 1
+#define CTLR_ENABLE_G1S_SHIFT 2
+#define CTLR_ARE_S_SHIFT 4
+#define CTLR_ARE_NS_SHIFT 5
+#define CTLR_DS_SHIFT 6
+#define CTLR_E1NWF_SHIFT 7
+#define GICD_CTLR_RWP_SHIFT 31
+
+#define CTLR_ENABLE_G1NS_MASK U(0x1)
+#define CTLR_ENABLE_G1S_MASK U(0x1)
+#define CTLR_ARE_S_MASK U(0x1)
+#define CTLR_ARE_NS_MASK U(0x1)
+#define CTLR_DS_MASK U(0x1)
+#define CTLR_E1NWF_MASK U(0x1)
+#define GICD_CTLR_RWP_MASK U(0x1)
+
+#define CTLR_ENABLE_G1NS_BIT BIT_32(CTLR_ENABLE_G1NS_SHIFT)
+#define CTLR_ENABLE_G1S_BIT BIT_32(CTLR_ENABLE_G1S_SHIFT)
+#define CTLR_ARE_S_BIT BIT_32(CTLR_ARE_S_SHIFT)
+#define CTLR_ARE_NS_BIT BIT_32(CTLR_ARE_NS_SHIFT)
+#define CTLR_DS_BIT BIT_32(CTLR_DS_SHIFT)
+#define CTLR_E1NWF_BIT BIT_32(CTLR_E1NWF_SHIFT)
+#define GICD_CTLR_RWP_BIT BIT_32(GICD_CTLR_RWP_SHIFT)
+
+/* GICD_IROUTER shifts and masks */
+#define IROUTER_SHIFT 0
+#define IROUTER_IRM_SHIFT 31
+#define IROUTER_IRM_MASK U(0x1)
+
+#define GICV3_IRM_PE U(0)
+#define GICV3_IRM_ANY U(1)
+
+#define NUM_OF_DIST_REGS 30
+
+/* GICD_TYPER shifts and masks */
+#define TYPER_ESPI U(1 << 8)
+#define TYPER_DVIS U(1 << 18)
+#define TYPER_ESPI_RANGE_MASK U(0x1f)
+#define TYPER_ESPI_RANGE_SHIFT U(27)
+#define TYPER_ESPI_RANGE U(TYPER_ESPI_MASK << TYPER_ESPI_SHIFT)
+
+/*******************************************************************************
+ * Common GIC Redistributor interface registers & constants
+ ******************************************************************************/
+#define GICR_V4_PCPUBASE_SHIFT 0x12
+#define GICR_V3_PCPUBASE_SHIFT 0x11
+#define GICR_SGIBASE_OFFSET U(65536) /* 64 KB */
+#define GICR_CTLR U(0x0)
+#define GICR_IIDR U(0x04)
+#define GICR_TYPER U(0x08)
+#define GICR_STATUSR U(0x10)
+#define GICR_WAKER U(0x14)
+#define GICR_PROPBASER U(0x70)
+#define GICR_PENDBASER U(0x78)
+#define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + U(0x80))
+#define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + U(0x100))
+#define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + U(0x180))
+#define GICR_ISPENDR0 (GICR_SGIBASE_OFFSET + U(0x200))
+#define GICR_ICPENDR0 (GICR_SGIBASE_OFFSET + U(0x280))
+#define GICR_ISACTIVER0 (GICR_SGIBASE_OFFSET + U(0x300))
+#define GICR_ICACTIVER0 (GICR_SGIBASE_OFFSET + U(0x380))
+#define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + U(0x400))
+#define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + U(0xc00))
+#define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + U(0xc04))
+#define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + U(0xd00))
+#define GICR_NSACR (GICR_SGIBASE_OFFSET + U(0xe00))
+
+#define GICR_IGROUPR GICR_IGROUPR0
+#define GICR_ISENABLER GICR_ISENABLER0
+#define GICR_ICENABLER GICR_ICENABLER0
+#define GICR_ISPENDR GICR_ISPENDR0
+#define GICR_ICPENDR GICR_ICPENDR0
+#define GICR_ISACTIVER GICR_ISACTIVER0
+#define GICR_ICACTIVER GICR_ICACTIVER0
+#define GICR_ICFGR GICR_ICFGR0
+#define GICR_IGRPMODR GICR_IGRPMODR0
+
+/* GICR_CTLR bit definitions */
+#define GICR_CTLR_UWP_SHIFT 31
+#define GICR_CTLR_UWP_MASK U(0x1)
+#define GICR_CTLR_UWP_BIT BIT_32(GICR_CTLR_UWP_SHIFT)
+#define GICR_CTLR_DPG1S_SHIFT 26
+#define GICR_CTLR_DPG1S_MASK U(0x1)
+#define GICR_CTLR_DPG1S_BIT BIT_32(GICR_CTLR_DPG1S_SHIFT)
+#define GICR_CTLR_DPG1NS_SHIFT 25
+#define GICR_CTLR_DPG1NS_MASK U(0x1)
+#define GICR_CTLR_DPG1NS_BIT BIT_32(GICR_CTLR_DPG1NS_SHIFT)
+#define GICR_CTLR_DPG0_SHIFT 24
+#define GICR_CTLR_DPG0_MASK U(0x1)
+#define GICR_CTLR_DPG0_BIT BIT_32(GICR_CTLR_DPG0_SHIFT)
+#define GICR_CTLR_RWP_SHIFT 3
+#define GICR_CTLR_RWP_MASK U(0x1)
+#define GICR_CTLR_RWP_BIT BIT_32(GICR_CTLR_RWP_SHIFT)
+#define GICR_CTLR_EN_LPIS_BIT BIT_32(0)
+
+/* GICR_WAKER bit definitions */
+#define WAKER_CA_SHIFT 2
+#define WAKER_PS_SHIFT 1
+
+#define WAKER_CA_MASK U(0x1)
+#define WAKER_PS_MASK U(0x1)
+
+#define WAKER_CA_BIT BIT_32(WAKER_CA_SHIFT)
+#define WAKER_PS_BIT BIT_32(WAKER_PS_SHIFT)
+
+/* GICR_TYPER bit definitions */
+#define TYPER_AFF_VAL_SHIFT 32
+#define TYPER_PROC_NUM_SHIFT 8
+#define TYPER_LAST_SHIFT 4
+#define TYPER_VLPI_SHIFT 1
+
+#define TYPER_AFF_VAL_MASK U(0xffffffff)
+#define TYPER_PROC_NUM_MASK U(0xffff)
+#define TYPER_LAST_MASK U(0x1)
+
+#define TYPER_LAST_BIT BIT_32(TYPER_LAST_SHIFT)
+#define TYPER_VLPI_BIT BIT_32(TYPER_VLPI_SHIFT)
+
+#define TYPER_PPI_NUM_SHIFT U(27)
+#define TYPER_PPI_NUM_MASK U(0x1f)
+
+/* GICR_IIDR bit definitions */
+#define IIDR_PRODUCT_ID_MASK U(0xff)
+#define IIDR_VARIANT_MASK U(0xf)
+#define IIDR_REV_MASK U(0xf)
+#define IIDR_IMPLEMENTER_MASK U(0xfff)
+#define IIDR_PRODUCT_ID_SHIFT 24
+#define IIDR_VARIANT_SHIFT 16
+#define IIDR_REV_SHIFT 12
+#define IIDR_IMPLEMENTER_SHIFT 0
+#define IIDR_PRODUCT_ID_BIT BIT_32(IIDR_PRODUCT_ID_SHIFT)
+#define IIDR_VARIANT_BIT BIT_32(IIDR_VARIANT_SHIFT)
+#define IIDR_REV_BIT BIT_32(IIDR_REVISION_SHIFT)
+#define IIDR_IMPLEMENTER_BIT BIT_32(IIDR_IMPLEMENTER_SHIFT)
+
+#define IIDR_MODEL_MASK (IIDR_PRODUCT_ID_MASK << IIDR_PRODUCT_ID_SHIFT | \
+ IIDR_IMPLEMENTER_MASK << IIDR_IMPLEMENTER_SHIFT)
+
+#define GIC_PRODUCT_ID_GIC600 U(0x2)
+#define GIC_PRODUCT_ID_GIC600AE U(0x3)
+#define GIC_PRODUCT_ID_GIC700 U(0x4)
+
+/*
+ * Note that below revisions and variants definations are as per GIC600/GIC600AE
+ * specification.
+ */
+#define GIC_REV_P0 U(0x1)
+#define GIC_REV_P1 U(0x3)
+#define GIC_REV_P2 U(0x4)
+#define GIC_REV_P3 U(0x5)
+#define GIC_REV_P4 U(0x6)
+#define GIC_REV_P6 U(0x7)
+
+#define GIC_VARIANT_R0 U(0x0)
+#define GIC_VARIANT_R1 U(0x1)
+#define GIC_VARIANT_R2 U(0x2)
+
+/*******************************************************************************
+ * GICv3 and 3.1 CPU interface registers & constants
+ ******************************************************************************/
+/* ICC_SRE bit definitions */
+#define ICC_SRE_EN_BIT BIT_32(3)
+#define ICC_SRE_DIB_BIT BIT_32(2)
+#define ICC_SRE_DFB_BIT BIT_32(1)
+#define ICC_SRE_SRE_BIT BIT_32(0)
+
+/* ICC_IGRPEN1_EL3 bit definitions */
+#define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0
+#define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1
+
+#define IGRPEN1_EL3_ENABLE_G1NS_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1NS_SHIFT)
+#define IGRPEN1_EL3_ENABLE_G1S_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1S_SHIFT)
+
+/* ICC_IGRPEN0_EL1 bit definitions */
+#define IGRPEN1_EL1_ENABLE_G0_SHIFT 0
+#define IGRPEN1_EL1_ENABLE_G0_BIT BIT_32(IGRPEN1_EL1_ENABLE_G0_SHIFT)
+
+/* ICC_HPPIR0_EL1 bit definitions */
+#define HPPIR0_EL1_INTID_SHIFT 0
+#define HPPIR0_EL1_INTID_MASK U(0xffffff)
+
+/* ICC_HPPIR1_EL1 bit definitions */
+#define HPPIR1_EL1_INTID_SHIFT 0
+#define HPPIR1_EL1_INTID_MASK U(0xffffff)
+
+/* ICC_IAR0_EL1 bit definitions */
+#define IAR0_EL1_INTID_SHIFT 0
+#define IAR0_EL1_INTID_MASK U(0xffffff)
+
+/* ICC_IAR1_EL1 bit definitions */
+#define IAR1_EL1_INTID_SHIFT 0
+#define IAR1_EL1_INTID_MASK U(0xffffff)
+
+/* ICC SGI macros */
+#define SGIR_TGT_MASK ULL(0xffff)
+#define SGIR_AFF1_SHIFT 16
+#define SGIR_INTID_SHIFT 24
+#define SGIR_INTID_MASK ULL(0xf)
+#define SGIR_AFF2_SHIFT 32
+#define SGIR_IRM_SHIFT 40
+#define SGIR_IRM_MASK ULL(0x1)
+#define SGIR_AFF3_SHIFT 48
+#define SGIR_AFF_MASK ULL(0xff)
+
+#define SGIR_IRM_TO_AFF U(0)
+
+#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
+ ((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
+ (((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
+ (((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
+ (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
+ (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
+ ((_tgt) & SGIR_TGT_MASK))
+
+/*****************************************************************************
+ * GICv3 and 3.1 ITS registers and constants
+ *****************************************************************************/
+#define GITS_CTLR U(0x0)
+#define GITS_IIDR U(0x4)
+#define GITS_TYPER U(0x8)
+#define GITS_CBASER U(0x80)
+#define GITS_CWRITER U(0x88)
+#define GITS_CREADR U(0x90)
+#define GITS_BASER U(0x100)
+
+/* GITS_CTLR bit definitions */
+#define GITS_CTLR_ENABLED_BIT BIT_32(0)
+#define GITS_CTLR_QUIESCENT_BIT BIT_32(1)
+
+#define GITS_TYPER_VSGI BIT_64(39)
+
+#ifndef __ASSEMBLER__
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <arch_helpers.h>
+#include <common/interrupt_props.h>
+#include <drivers/arm/gic_common.h>
+#include <lib/utils_def.h>
+
+typedef enum {
+ GICV3_G1S,
+ GICV3_G1NS,
+ GICV3_G0
+} gicv3_irq_group_t;
+
+static inline uintptr_t gicv3_redist_size(uint64_t typer_val)
+{
+#if GIC_ENABLE_V4_EXTN
+ if ((typer_val & TYPER_VLPI_BIT) != 0U) {
+ return 1U << GICR_V4_PCPUBASE_SHIFT;
+ } else {
+ return 1U << GICR_V3_PCPUBASE_SHIFT;
+ }
+#else
+ return 1U << GICR_V3_PCPUBASE_SHIFT;
+#endif
+}
+
+unsigned int gicv3_get_component_partnum(const uintptr_t gic_frame);
+
+static inline bool gicv3_is_intr_id_special_identifier(unsigned int id)
+{
+ return (id >= PENDING_G1S_INTID) && (id <= GIC_SPURIOUS_INTERRUPT);
+}
+
+/*******************************************************************************
+ * Helper GICv3 and 3.1 macros for SEL1
+ ******************************************************************************/
+static inline uint32_t gicv3_acknowledge_interrupt_sel1(void)
+{
+ return (uint32_t)read_icc_iar1_el1() & IAR1_EL1_INTID_MASK;
+}
+
+static inline uint32_t gicv3_get_pending_interrupt_id_sel1(void)
+{
+ return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
+}
+
+static inline void gicv3_end_of_interrupt_sel1(unsigned int id)
+{
+ /*
+ * Interrupt request deassertion from peripheral to GIC happens
+ * by clearing interrupt condition by a write to the peripheral
+ * register. It is desired that the write transfer is complete
+ * before the core tries to change GIC state from 'AP/Active' to
+ * a new state on seeing 'EOI write'.
+ * Since ICC interface writes are not ordered against Device
+ * memory writes, a barrier is required to ensure the ordering.
+ * The dsb will also ensure *completion* of previous writes with
+ * DEVICE nGnRnE attribute.
+ */
+ dsbishst();
+ write_icc_eoir1_el1(id);
+}
+
+/*******************************************************************************
+ * Helper GICv3 macros for EL3
+ ******************************************************************************/
+static inline uint32_t gicv3_acknowledge_interrupt(void)
+{
+ return (uint32_t)read_icc_iar0_el1() & IAR0_EL1_INTID_MASK;
+}
+
+static inline void gicv3_end_of_interrupt(unsigned int id)
+{
+ /*
+ * Interrupt request deassertion from peripheral to GIC happens
+ * by clearing interrupt condition by a write to the peripheral
+ * register. It is desired that the write transfer is complete
+ * before the core tries to change GIC state from 'AP/Active' to
+ * a new state on seeing 'EOI write'.
+ * Since ICC interface writes are not ordered against Device
+ * memory writes, a barrier is required to ensure the ordering.
+ * The dsb will also ensure *completion* of previous writes with
+ * DEVICE nGnRnE attribute.
+ */
+ dsbishst();
+ return write_icc_eoir0_el1(id);
+}
+
+/*
+ * This macro returns the total number of GICD/GICR registers corresponding to
+ * the register name
+ */
+#define GICD_NUM_REGS(reg_name) \
+ DIV_ROUND_UP_2EVAL(TOTAL_SHARED_INTR_NUM, (1 << reg_name##_SHIFT))
+
+#define GICR_NUM_REGS(reg_name) \
+ DIV_ROUND_UP_2EVAL(TOTAL_PRIVATE_INTR_NUM, (1 << reg_name##_SHIFT))
+
+/* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
+#define INT_ID_MASK U(0xffffff)
+
+/*******************************************************************************
+ * This structure describes some of the implementation defined attributes of the
+ * GICv3 IP. It is used by the platform port to specify these attributes in order
+ * to initialise the GICV3 driver. The attributes are described below.
+ *
+ * The 'gicd_base' field contains the base address of the Distributor interface
+ * programmer's view.
+ *
+ * The 'gicr_base' field contains the base address of the Re-distributor
+ * interface programmer's view.
+ *
+ * The 'interrupt_props' field is a pointer to an array that enumerates secure
+ * interrupts and their properties. If this field is not NULL, both
+ * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored.
+ *
+ * The 'interrupt_props_num' field contains the number of entries in the
+ * 'interrupt_props' array. If this field is non-zero, both 'g0_interrupt_num'
+ * and 'g1s_interrupt_num' are ignored.
+ *
+ * The 'rdistif_num' field contains the number of Redistributor interfaces the
+ * GIC implements. This is equal to the number of CPUs or CPU interfaces
+ * instantiated in the GIC.
+ *
+ * The 'rdistif_base_addrs' field is a pointer to an array that has an entry for
+ * storing the base address of the Redistributor interface frame of each CPU in
+ * the system. The size of the array = 'rdistif_num'. The base addresses are
+ * detected during driver initialisation.
+ *
+ * The 'mpidr_to_core_pos' field is a pointer to a hash function which the
+ * driver will use to convert an MPIDR value to a linear core index. This index
+ * will be used for accessing the 'rdistif_base_addrs' array. This is an
+ * optional field. A GICv3 implementation maps each MPIDR to a linear core index
+ * as well. This mapping can be found by reading the "Affinity Value" and
+ * "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the
+ * "Processor Numbers" are suitable to index into an array to access core
+ * specific information. If this not the case, the platform port must provide a
+ * hash function. Otherwise, the "Processor Number" field will be used to access
+ * the array elements.
+ ******************************************************************************/
+typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr);
+
+typedef struct gicv3_driver_data {
+ uintptr_t gicd_base;
+ uintptr_t gicr_base;
+ const interrupt_prop_t *interrupt_props;
+ unsigned int interrupt_props_num;
+ unsigned int rdistif_num;
+ uintptr_t *rdistif_base_addrs;
+ mpidr_hash_fn mpidr_to_core_pos;
+} gicv3_driver_data_t;
+
+typedef struct gicv3_redist_ctx {
+ /* 64 bits registers */
+ uint64_t gicr_propbaser;
+ uint64_t gicr_pendbaser;
+
+ /* 32 bits registers */
+ uint32_t gicr_ctlr;
+ uint32_t gicr_igroupr[GICR_NUM_REGS(IGROUPR)];
+ uint32_t gicr_isenabler[GICR_NUM_REGS(ISENABLER)];
+ uint32_t gicr_ispendr[GICR_NUM_REGS(ISPENDR)];
+ uint32_t gicr_isactiver[GICR_NUM_REGS(ISACTIVER)];
+ uint32_t gicr_ipriorityr[GICR_NUM_REGS(IPRIORITYR)];
+ uint32_t gicr_icfgr[GICR_NUM_REGS(ICFGR)];
+ uint32_t gicr_igrpmodr[GICR_NUM_REGS(IGRPMODR)];
+ uint32_t gicr_nsacr;
+} gicv3_redist_ctx_t;
+
+typedef struct gicv3_dist_ctx {
+ /* 64 bits registers */
+ uint64_t gicd_irouter[TOTAL_SHARED_INTR_NUM];
+
+ /* 32 bits registers */
+ uint32_t gicd_ctlr;
+ uint32_t gicd_igroupr[GICD_NUM_REGS(IGROUPR)];
+ uint32_t gicd_isenabler[GICD_NUM_REGS(ISENABLER)];
+ uint32_t gicd_ispendr[GICD_NUM_REGS(ISPENDR)];
+ uint32_t gicd_isactiver[GICD_NUM_REGS(ISACTIVER)];
+ uint32_t gicd_ipriorityr[GICD_NUM_REGS(IPRIORITYR)];
+ uint32_t gicd_icfgr[GICD_NUM_REGS(ICFGR)];
+ uint32_t gicd_igrpmodr[GICD_NUM_REGS(IGRPMODR)];
+ uint32_t gicd_nsacr[GICD_NUM_REGS(NSACR)];
+} gicv3_dist_ctx_t;
+
+typedef struct gicv3_its_ctx {
+ /* 64 bits registers */
+ uint64_t gits_cbaser;
+ uint64_t gits_cwriter;
+ uint64_t gits_baser[8];
+
+ /* 32 bits registers */
+ uint32_t gits_ctlr;
+} gicv3_its_ctx_t;
+
+/*******************************************************************************
+ * GICv3 EL3 driver API
+ ******************************************************************************/
+void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data);
+int gicv3_rdistif_probe(const uintptr_t gicr_frame);
+void gicv3_distif_init(void);
+void gicv3_rdistif_init(unsigned int proc_num);
+void gicv3_rdistif_on(unsigned int proc_num);
+void gicv3_rdistif_off(unsigned int proc_num);
+unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame);
+void gicv3_cpuif_enable(unsigned int proc_num);
+void gicv3_cpuif_disable(unsigned int proc_num);
+unsigned int gicv3_get_pending_interrupt_type(void);
+unsigned int gicv3_get_pending_interrupt_id(void);
+unsigned int gicv3_get_interrupt_type(unsigned int id,
+ unsigned int proc_num);
+void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx);
+void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx);
+/*
+ * gicv3_distif_post_restore and gicv3_distif_pre_save must be implemented if
+ * gicv3_distif_save and gicv3_rdistif_init_restore are used. If no
+ * implementation-defined sequence is needed at these steps, an empty function
+ * can be provided.
+ */
+void gicv3_distif_post_restore(unsigned int proc_num);
+void gicv3_distif_pre_save(unsigned int proc_num);
+void gicv3_rdistif_init_restore(unsigned int proc_num, const gicv3_redist_ctx_t * const rdist_ctx);
+void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx);
+void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx);
+void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx);
+
+unsigned int gicv3_get_running_priority(void);
+unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num);
+void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num);
+void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num);
+void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
+ unsigned int priority);
+void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
+ unsigned int type);
+void gicv3_raise_sgi(unsigned int sgi_num, gicv3_irq_group_t group,
+ u_register_t target);
+void gicv3_set_spi_routing(unsigned int id, unsigned int irm,
+ u_register_t mpidr);
+void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num);
+void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num);
+unsigned int gicv3_set_pmr(unsigned int mask);
+
+void gicv3_get_component_prodid_rev(const uintptr_t gicd_base,
+ unsigned int *gic_prod_id,
+ uint8_t *gic_rev);
+void gicv3_check_erratas_applies(const uintptr_t gicd_base);
+#if GIC600_ERRATA_WA_2384374
+void gicv3_apply_errata_wa_2384374(const uintptr_t gicr_base);
+#else
+static inline void gicv3_apply_errata_wa_2384374(const uintptr_t gicr_base)
+{
+}
+#endif /* GIC600_ERRATA_WA_2384374 */
+
+#endif /* __ASSEMBLER__ */
+#endif /* GICV3_H */
diff --git a/include/drivers/arm/mhu.h b/include/drivers/arm/mhu.h
new file mode 100644
index 0000000..31c6a81
--- /dev/null
+++ b/include/drivers/arm/mhu.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MHU_H
+#define MHU_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+/**
+ * Generic MHU error enumeration types.
+ */
+enum mhu_error_t {
+ MHU_ERR_NONE = 0,
+ MHU_ERR_NOT_INIT = -1,
+ MHU_ERR_ALREADY_INIT = -2,
+ MHU_ERR_UNSUPPORTED_VERSION = -3,
+ MHU_ERR_UNSUPPORTED = -4,
+ MHU_ERR_INVALID_ARG = -5,
+ MHU_ERR_BUFFER_TOO_SMALL = -6,
+ MHU_ERR_GENERAL = -7,
+};
+
+/**
+ * Initializes sender MHU.
+ *
+ * mhu_sender_base Base address of sender MHU.
+ *
+ * Returns mhu_error_t error code.
+ *
+ * This function must be called before mhu_send_data().
+ */
+enum mhu_error_t mhu_init_sender(uintptr_t mhu_sender_base);
+
+
+/**
+ * Initializes receiver MHU.
+ *
+ * mhu_receiver_base Base address of receiver MHU.
+ *
+ * Returns mhu_error_t error code.
+ *
+ * This function must be called before mhu_receive_data().
+ */
+enum mhu_error_t mhu_init_receiver(uintptr_t mhu_receiver_base);
+
+/**
+ * Sends data over MHU.
+ *
+ * send_buffer Pointer to buffer containing the data to be transmitted.
+ * size Size of the data to be transmitted in bytes.
+ *
+ * Returns mhu_error_t error code.
+ *
+ * The send_buffer must be 4-byte aligned and its length must be at least
+ * (4 - (size % 4)) bytes bigger than the data size to prevent buffer
+ * over-reading.
+ */
+enum mhu_error_t mhu_send_data(const uint8_t *send_buffer, size_t size);
+
+/**
+ * Receives data from MHU.
+ *
+ * receive_buffer Pointer the buffer where to store the received data.
+ * size As input the size of the receive_buffer, as output the
+ * number of bytes received. As a limitation,
+ * the size of the buffer must be a multiple of 4.
+ *
+ * Returns mhu_error_t error code.
+ *
+ * The receive_buffer must be 4-byte aligned and its length must be a
+ * multiple of 4.
+ */
+enum mhu_error_t mhu_receive_data(uint8_t *receive_buffer, size_t *size);
+
+/**
+ * Gets the maximum amount of bytes that can be transmitted in a single send by MHU.
+ *
+ * Returns The amount of bytes that can be sent or received in a single message.
+ */
+size_t mhu_get_max_message_size(void);
+
+#endif /* MHU_H */
diff --git a/include/drivers/arm/nic_400.h b/include/drivers/arm/nic_400.h
new file mode 100644
index 0000000..bb74982
--- /dev/null
+++ b/include/drivers/arm/nic_400.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NIC_400_H
+#define NIC_400_H
+
+/*
+ * Address of slave 'n' security setting in the NIC-400 address region
+ * control
+ */
+#define NIC400_ADDR_CTRL_SECURITY_REG(n) (0x8 + (n) * 4)
+
+#endif /* NIC_400_H */
diff --git a/include/drivers/arm/pl011.h b/include/drivers/arm/pl011.h
new file mode 100644
index 0000000..ebc6643
--- /dev/null
+++ b/include/drivers/arm/pl011.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PL011_H
+#define PL011_H
+
+#include <drivers/console.h>
+
+/* PL011 Registers */
+#define UARTDR 0x000
+#define UARTRSR 0x004
+#define UARTECR 0x004
+#define UARTFR 0x018
+#define UARTIMSC 0x038
+#define UARTRIS 0x03C
+#define UARTICR 0x044
+
+/* PL011 registers (out of the SBSA specification) */
+#if !PL011_GENERIC_UART
+#define UARTILPR 0x020
+#define UARTIBRD 0x024
+#define UARTFBRD 0x028
+#define UARTLCR_H 0x02C
+#define UARTCR 0x030
+#define UARTIFLS 0x034
+#define UARTMIS 0x040
+#define UARTDMACR 0x048
+#endif /* !PL011_GENERIC_UART */
+
+/* Data status bits */
+#define UART_DATA_ERROR_MASK 0x0F00
+
+/* Status reg bits */
+#define UART_STATUS_ERROR_MASK 0x0F
+
+/* Flag reg bits */
+#define PL011_UARTFR_RI (1 << 8) /* Ring indicator */
+#define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */
+#define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */
+#define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */
+#define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */
+#define PL011_UARTFR_BUSY (1 << 3) /* UART busy */
+#define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */
+#define PL011_UARTFR_DSR (1 << 1) /* Data set ready */
+#define PL011_UARTFR_CTS (1 << 0) /* Clear to send */
+
+#define PL011_UARTFR_TXFF_BIT 5 /* Transmit FIFO full bit in UARTFR register */
+#define PL011_UARTFR_RXFE_BIT 4 /* Receive FIFO empty bit in UARTFR register */
+#define PL011_UARTFR_BUSY_BIT 3 /* UART busy bit in UARTFR register */
+
+/* Control reg bits */
+#if !PL011_GENERIC_UART
+#define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */
+#define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */
+#define PL011_UARTCR_RTS (1 << 11) /* Request to send */
+#define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */
+#define PL011_UARTCR_RXE (1 << 9) /* Receive enable */
+#define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */
+#define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */
+#define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */
+
+#if !defined(PL011_LINE_CONTROL)
+/* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */
+#define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8)
+#endif
+
+/* Line Control Register Bits */
+#define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */
+#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
+#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
+#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
+#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
+#define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */
+#define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */
+#define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */
+#define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */
+#define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */
+
+#endif /* !PL011_GENERIC_UART */
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+/*
+ * Initialize a new PL011 console instance and register it with the console
+ * framework. The |console| pointer must point to storage that will be valid
+ * for the lifetime of the console, such as a global or static local variable.
+ * Its contents will be reinitialized from scratch.
+ */
+int console_pl011_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
+ console_t *console);
+
+#endif /*__ASSEMBLER__*/
+
+#endif /* PL011_H */
diff --git a/include/drivers/arm/pl061_gpio.h b/include/drivers/arm/pl061_gpio.h
new file mode 100644
index 0000000..68238c9
--- /dev/null
+++ b/include/drivers/arm/pl061_gpio.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PL061_GPIO_H
+#define PL061_GPIO_H
+
+#include <drivers/gpio.h>
+
+void pl061_gpio_register(uintptr_t base_addr, int gpio_dev);
+void pl061_gpio_init(void);
+
+#endif /* PL061_GPIO_H */
diff --git a/include/drivers/arm/rss_comms.h b/include/drivers/arm/rss_comms.h
new file mode 100644
index 0000000..b96c79f
--- /dev/null
+++ b/include/drivers/arm/rss_comms.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef RSS_COMMS_H
+#define RSS_COMMS_H
+
+#include <stdint.h>
+
+int rss_comms_init(uintptr_t mhu_sender_base, uintptr_t mhu_receiver_base);
+
+#endif /* RSS_COMMS_H */
diff --git a/include/drivers/arm/sbsa.h b/include/drivers/arm/sbsa.h
new file mode 100644
index 0000000..9403634
--- /dev/null
+++ b/include/drivers/arm/sbsa.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2019, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SBSA_H
+#define SBSA_H
+
+#include <stdint.h>
+
+/* Register Offsets */
+#define SBSA_WDOG_WCS_OFFSET UL(0x000)
+#define SBSA_WDOG_WOR_LOW_OFFSET UL(0x008)
+#define SBSA_WDOG_WOR_HIGH_OFFSET UL(0x00C)
+
+#define SBSA_WDOG_WCS_EN U(0x1)
+
+#define SBSA_WDOG_WOR_WIDTH UL(48)
+
+void sbsa_wdog_start(uintptr_t base, uint64_t ms);
+void sbsa_wdog_stop(uintptr_t base);
+
+#endif /* SBSA_H */
diff --git a/include/drivers/arm/scu.h b/include/drivers/arm/scu.h
new file mode 100644
index 0000000..992539f
--- /dev/null
+++ b/include/drivers/arm/scu.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SCU_H
+#define SCU_H
+
+#include <stdint.h>
+
+#define SCU_CTRL_REG 0x00
+#define SCU_CFG_REG 0x04
+
+#define SCU_ENABLE_BIT (1 << 0)
+
+void enable_snoop_ctrl_unit(uintptr_t base);
+uint32_t read_snoop_ctrl_unit_cfg(uintptr_t base);
+
+#endif /* SCU_H */
diff --git a/include/drivers/arm/smmu_v3.h b/include/drivers/arm/smmu_v3.h
new file mode 100644
index 0000000..37da56f
--- /dev/null
+++ b/include/drivers/arm/smmu_v3.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SMMU_V3_H
+#define SMMU_V3_H
+
+#include <stdint.h>
+#include <lib/utils_def.h>
+#include <platform_def.h>
+
+/* SMMUv3 register offsets from device base */
+#define SMMU_CR0 U(0x0020)
+#define SMMU_CR0ACK U(0x0024)
+#define SMMU_GBPA U(0x0044)
+#define SMMU_S_IDR1 U(0x8004)
+#define SMMU_S_INIT U(0x803c)
+#define SMMU_S_GBPA U(0x8044)
+
+/*
+ * TODO: SMMU_ROOT_PAGE_OFFSET is platform specific.
+ * Currently defined as a command line model parameter.
+ */
+#if ENABLE_RME
+
+#define SMMU_ROOT_PAGE_OFFSET (PLAT_ARM_SMMUV3_ROOT_REG_OFFSET)
+#define SMMU_ROOT_IDR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0000)
+#define SMMU_ROOT_IIDR U(SMMU_ROOT_PAGE_OFFSET + 0x0008)
+#define SMMU_ROOT_CR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0020)
+#define SMMU_ROOT_CR0ACK U(SMMU_ROOT_PAGE_OFFSET + 0x0024)
+#define SMMU_ROOT_GPT_BASE U(SMMU_ROOT_PAGE_OFFSET + 0x0028)
+#define SMMU_ROOT_GPT_BASE_CFG U(SMMU_ROOT_PAGE_OFFSET + 0x0030)
+#define SMMU_ROOT_GPF_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0038)
+#define SMMU_ROOT_GPT_CFG_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0040)
+#define SMMU_ROOT_TLBI U(SMMU_ROOT_PAGE_OFFSET + 0x0050)
+#define SMMU_ROOT_TLBI_CTRL U(SMMU_ROOT_PAGE_OFFSET + 0x0058)
+
+#endif /* ENABLE_RME */
+
+/* SMMU_CR0 and SMMU_CR0ACK register fields */
+#define SMMU_CR0_SMMUEN (1UL << 0)
+
+/* SMMU_GBPA register fields */
+#define SMMU_GBPA_UPDATE (1UL << 31)
+#define SMMU_GBPA_ABORT (1UL << 20)
+
+/* SMMU_S_IDR1 register fields */
+#define SMMU_S_IDR1_SECURE_IMPL (1UL << 31)
+
+/* SMMU_S_INIT register fields */
+#define SMMU_S_INIT_INV_ALL (1UL << 0)
+
+/* SMMU_S_GBPA register fields */
+#define SMMU_S_GBPA_UPDATE (1UL << 31)
+#define SMMU_S_GBPA_ABORT (1UL << 20)
+
+/* SMMU_ROOT_IDR0 register fields */
+#define SMMU_ROOT_IDR0_ROOT_IMPL (1UL << 0)
+
+/* SMMU_ROOT_CR0 register fields */
+#define SMMU_ROOT_CR0_GPCEN (1UL << 1)
+#define SMMU_ROOT_CR0_ACCESSEN (1UL << 0)
+
+int smmuv3_init(uintptr_t smmu_base);
+int smmuv3_security_init(uintptr_t smmu_base);
+
+int smmuv3_ns_set_abort_all(uintptr_t smmu_base);
+
+#endif /* SMMU_V3_H */
diff --git a/include/drivers/arm/sp804_delay_timer.h b/include/drivers/arm/sp804_delay_timer.h
new file mode 100644
index 0000000..f8769e8
--- /dev/null
+++ b/include/drivers/arm/sp804_delay_timer.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SP804_DELAY_TIMER_H
+#define SP804_DELAY_TIMER_H
+
+#include <stdint.h>
+
+#include <drivers/delay_timer.h>
+
+uint32_t sp804_get_timer_value(void);
+
+void sp804_timer_ops_init(uintptr_t base_addr, const timer_ops_t *ops);
+
+#define sp804_timer_init(base_addr, clk_mult, clk_div) \
+ do { \
+ static const timer_ops_t sp804_timer_ops = { \
+ sp804_get_timer_value, \
+ (clk_mult), \
+ (clk_div) \
+ }; \
+ sp804_timer_ops_init((base_addr), &sp804_timer_ops); \
+ } while (0)
+
+#endif /* SP804_DELAY_TIMER_H */
diff --git a/include/drivers/arm/sp805.h b/include/drivers/arm/sp805.h
new file mode 100644
index 0000000..b00ede1
--- /dev/null
+++ b/include/drivers/arm/sp805.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SP805_H
+#define SP805_H
+
+#include <lib/utils_def.h>
+
+/* SP805 register offset */
+#define SP805_WDOG_LOAD_OFF UL(0x000)
+#define SP805_WDOG_CTR_OFF UL(0x008)
+#define SP805_WDOG_LOCK_OFF UL(0xc00)
+
+/* Magic word to unlock the wd registers */
+#define WDOG_UNLOCK_KEY U(0x1ACCE551)
+
+/* Register field definitions */
+#define SP805_CTR_RESEN (U(1) << 1)
+#define SP805_CTR_INTEN (U(1) << 0)
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+/* Public high level API */
+
+void sp805_start(uintptr_t base, unsigned int ticks);
+void sp805_stop(uintptr_t base);
+void sp805_refresh(uintptr_t base, unsigned int ticks);
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* SP805_H */
diff --git a/include/drivers/arm/tzc380.h b/include/drivers/arm/tzc380.h
new file mode 100644
index 0000000..9bd5f21
--- /dev/null
+++ b/include/drivers/arm/tzc380.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TZC380_H
+#define TZC380_H
+
+#include <drivers/arm/tzc_common.h>
+#include <lib/utils_def.h>
+
+#define TZC380_CONFIGURATION_OFF U(0x000)
+#define ACTION_OFF U(0x004)
+#define LOCKDOWN_RANGE_OFF U(0x008)
+#define LOCKDOWN_SELECT_OFF U(0x00C)
+#define INT_STATUS U(0x010)
+#define INT_CLEAR U(0x014)
+
+#define FAIL_ADDRESS_LOW_OFF U(0x020)
+#define FAIL_ADDRESS_HIGH_OFF U(0x024)
+#define FAIL_CONTROL_OFF U(0x028)
+#define FAIL_ID U(0x02c)
+
+#define SPECULATION_CTRL_OFF U(0x030)
+#define SECURITY_INV_EN_OFF U(0x034)
+
+#define REGION_SETUP_LOW_OFF(n) U(0x100 + (n) * 0x10)
+#define REGION_SETUP_HIGH_OFF(n) U(0x104 + (n) * 0x10)
+#define REGION_ATTRIBUTES_OFF(n) U(0x108 + (n) * 0x10)
+
+#define BUILD_CONFIG_AW_SHIFT 8
+#define BUILD_CONFIG_AW_MASK U(0x3f)
+#define BUILD_CONFIG_NR_SHIFT 0
+#define BUILD_CONFIG_NR_MASK U(0xf)
+
+#define ACTION_RV_SHIFT 0
+#define ACTION_RV_MASK U(0x3)
+#define ACTION_RV_LOWOK U(0x0)
+#define ACTION_RV_LOWERR U(0x1)
+#define ACTION_RV_HIGHOK U(0x2)
+#define ACTION_RV_HIGHERR U(0x3)
+
+/* Speculation is enabled by default. */
+#define SPECULATION_CTRL_WRITE_DISABLE BIT_32(1)
+#define SPECULATION_CTRL_READ_DISABLE BIT_32(0)
+
+#define INT_STATUS_OVERRUN_SHIFT 1
+#define INT_STATUS_OVERRUN_MASK U(0x1)
+#define INT_STATUS_STATUS_SHIFT 0
+#define INT_STATUS_STATUS_MASK U(0x1)
+
+#define INT_CLEAR_CLEAR_SHIFT 0
+#define INT_CLEAR_CLEAR_MASK U(0x1)
+
+#define TZC380_COMPONENT_ID U(0xb105f00d)
+#define TZC380_PERIPH_ID_LOW U(0x001bb380)
+#define TZC380_PERIPH_ID_HIGH U(0x00000004)
+
+#define TZC_SP_NS_W BIT_32(0)
+#define TZC_SP_NS_R BIT_32(1)
+#define TZC_SP_S_W BIT_32(2)
+#define TZC_SP_S_R BIT_32(3)
+
+#define TZC_ATTR_SP_SHIFT 28
+#define TZC_ATTR_SP_ALL ((TZC_SP_S_W | TZC_SP_S_R | TZC_SP_NS_W | \
+ TZC_SP_NS_R) << TZC_ATTR_SP_SHIFT)
+#define TZC_ATTR_SP_S_RW ((TZC_SP_S_W | TZC_SP_S_R) << \
+ TZC_ATTR_SP_SHIFT)
+#define TZC_ATTR_SP_NS_RW ((TZC_SP_NS_W | TZC_SP_NS_R) << \
+ TZC_ATTR_SP_SHIFT)
+
+#define TZC_REGION_SIZE_32K U(0xe)
+#define TZC_REGION_SIZE_64K U(0xf)
+#define TZC_REGION_SIZE_128K U(0x10)
+#define TZC_REGION_SIZE_256K U(0x11)
+#define TZC_REGION_SIZE_512K U(0x12)
+#define TZC_REGION_SIZE_1M U(0x13)
+#define TZC_REGION_SIZE_2M U(0x14)
+#define TZC_REGION_SIZE_4M U(0x15)
+#define TZC_REGION_SIZE_8M U(0x16)
+#define TZC_REGION_SIZE_16M U(0x17)
+#define TZC_REGION_SIZE_32M U(0x18)
+#define TZC_REGION_SIZE_64M U(0x19)
+#define TZC_REGION_SIZE_128M U(0x1a)
+#define TZC_REGION_SIZE_256M U(0x1b)
+#define TZC_REGION_SIZE_512M U(0x1c)
+#define TZC_REGION_SIZE_1G U(0x1d)
+#define TZC_REGION_SIZE_2G U(0x1e)
+#define TZC_REGION_SIZE_4G U(0x1f)
+#define TZC_REGION_SIZE_8G U(0x20)
+#define TZC_REGION_SIZE_16G U(0x21)
+#define TZC_REGION_SIZE_32G U(0x22)
+#define TZC_REGION_SIZE_64G U(0x23)
+#define TZC_REGION_SIZE_128G U(0x24)
+#define TZC_REGION_SIZE_256G U(0x25)
+#define TZC_REGION_SIZE_512G U(0x26)
+#define TZC_REGION_SIZE_1T U(0x27)
+#define TZC_REGION_SIZE_2T U(0x28)
+#define TZC_REGION_SIZE_4T U(0x29)
+#define TZC_REGION_SIZE_8T U(0x2a)
+#define TZC_REGION_SIZE_16T U(0x2b)
+#define TZC_REGION_SIZE_32T U(0x2c)
+#define TZC_REGION_SIZE_64T U(0x2d)
+#define TZC_REGION_SIZE_128T U(0x2e)
+#define TZC_REGION_SIZE_256T U(0x2f)
+#define TZC_REGION_SIZE_512T U(0x30)
+#define TZC_REGION_SIZE_1P U(0x31)
+#define TZC_REGION_SIZE_2P U(0x32)
+#define TZC_REGION_SIZE_4P U(0x33)
+#define TZC_REGION_SIZE_8P U(0x34)
+#define TZC_REGION_SIZE_16P U(0x35)
+#define TZC_REGION_SIZE_32P U(0x36)
+#define TZC_REGION_SIZE_64P U(0x37)
+#define TZC_REGION_SIZE_128P U(0x38)
+#define TZC_REGION_SIZE_256P U(0x39)
+#define TZC_REGION_SIZE_512P U(0x3a)
+#define TZC_REGION_SIZE_1E U(0x3b)
+#define TZC_REGION_SIZE_2E U(0x3c)
+#define TZC_REGION_SIZE_4E U(0x3d)
+#define TZC_REGION_SIZE_8E U(0x3e)
+#define TZC_REGION_SIZE_16E U(0x3f)
+
+#define TZC_SUBREGION_DIS_SHIFT 0x8
+#define TZC_SUBREGION_DIS_MASK U(0xff)
+#define TZC_ATTR_SUBREG_DIS(s) (((s) & TZC_SUBREGION_DIS_MASK) \
+ << TZC_SUBREGION_DIS_SHIFT)
+
+#define TZC_REGION_SIZE_SHIFT 0x1
+#define TZC_REGION_SIZE_MASK U(0x7e)
+#define TZC_ATTR_REGION_SIZE(s) ((s) << TZC_REGION_SIZE_SHIFT)
+
+#define TZC_ATTR_REGION_EN_SHIFT 0x0
+#define TZC_ATTR_REGION_EN_MASK U(0x1)
+
+#define TZC_ATTR_REGION_EN
+#define TZC_ATTR_REGION_ENABLE U(0x1)
+#define TZC_ATTR_REGION_DISABLE U(0x0)
+
+#define REGION_MAX 16
+
+void tzc380_init(uintptr_t base);
+void tzc380_configure_region(uint8_t region,
+ uintptr_t region_base,
+ unsigned int attr);
+void tzc380_set_action(unsigned int action);
+static inline void tzc_init(uintptr_t base)
+{
+ tzc380_init(base);
+}
+
+static inline void tzc_configure_region(uint8_t region,
+ uintptr_t region_base,
+ unsigned int attr)
+{
+ tzc380_configure_region(region, region_base, attr);
+}
+
+static inline void tzc_set_action(unsigned int action)
+{
+ tzc380_set_action(action);
+}
+
+#endif /* TZC380_H */
diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h
new file mode 100644
index 0000000..765c130
--- /dev/null
+++ b/include/drivers/arm/tzc400.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TZC400_H
+#define TZC400_H
+
+#include <drivers/arm/tzc_common.h>
+#include <lib/utils_def.h>
+
+#define BUILD_CONFIG_OFF U(0x000)
+#define GATE_KEEPER_OFF U(0x008)
+#define SPECULATION_CTRL_OFF U(0x00c)
+#define INT_STATUS U(0x010)
+#define INT_CLEAR U(0x014)
+
+#define FAIL_ADDRESS_LOW_OFF U(0x020)
+#define FAIL_ADDRESS_HIGH_OFF U(0x024)
+#define FAIL_CONTROL_OFF U(0x028)
+#define FAIL_ID U(0x02c)
+
+/* ID registers not common across different varieties of TZC */
+#define PID5 U(0xFD4)
+#define PID6 U(0xFD8)
+#define PID7 U(0xFDC)
+
+#define BUILD_CONFIG_NF_SHIFT 24
+#define BUILD_CONFIG_NF_MASK U(0x3)
+#define BUILD_CONFIG_AW_SHIFT 8
+#define BUILD_CONFIG_AW_MASK U(0x3f)
+#define BUILD_CONFIG_NR_SHIFT 0
+#define BUILD_CONFIG_NR_MASK U(0x1f)
+
+/*
+ * Number of gate keepers is implementation defined. But we know the max for
+ * this device is 4. Get implementation details from BUILD_CONFIG.
+ */
+#define GATE_KEEPER_OS_SHIFT 16
+#define GATE_KEEPER_OS_MASK U(0xf)
+#define GATE_KEEPER_OR_SHIFT 0
+#define GATE_KEEPER_OR_MASK U(0xf)
+#define GATE_KEEPER_FILTER_MASK U(0x1)
+
+/* Speculation is enabled by default. */
+#define SPECULATION_CTRL_WRITE_DISABLE BIT_32(1)
+#define SPECULATION_CTRL_READ_DISABLE BIT_32(0)
+
+/* Max number of filters allowed is 4. */
+#define INT_STATUS_OVERLAP_SHIFT 16
+#define INT_STATUS_OVERLAP_MASK U(0xf)
+#define INT_STATUS_OVERRUN_SHIFT 8
+#define INT_STATUS_OVERRUN_MASK U(0xf)
+#define INT_STATUS_STATUS_SHIFT 0
+#define INT_STATUS_STATUS_MASK U(0xf)
+
+#define INT_CLEAR_CLEAR_SHIFT 0
+#define INT_CLEAR_CLEAR_MASK U(0xf)
+
+#define FAIL_CONTROL_DIR_SHIFT 24
+#define FAIL_CONTROL_DIR_READ U(0)
+#define FAIL_CONTROL_DIR_WRITE U(1)
+#define FAIL_CONTROL_NS_SHIFT 21
+#define FAIL_CONTROL_NS_SECURE U(0)
+#define FAIL_CONTROL_NS_NONSECURE U(1)
+#define FAIL_CONTROL_PRIV_SHIFT 20
+#define FAIL_CONTROL_PRIV_UNPRIV U(0)
+#define FAIL_CONTROL_PRIV_PRIV U(1)
+
+/*
+ * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific.
+ * Platform should provide the value on initialisation.
+ */
+#define FAIL_ID_VNET_SHIFT 24
+#define FAIL_ID_VNET_MASK U(0xf)
+#define FAIL_ID_ID_SHIFT 0
+
+#define TZC_400_PERIPHERAL_ID U(0x460)
+
+/* Filter enable bits in a TZC */
+#define TZC_400_REGION_ATTR_F_EN_MASK U(0xf)
+#define TZC_400_REGION_ATTR_FILTER_BIT(x) (U(1) << (x))
+#define TZC_400_REGION_ATTR_FILTER_BIT_ALL TZC_400_REGION_ATTR_F_EN_MASK
+
+/*
+ * All TZC region configuration registers are placed one after another. It
+ * depicts size of block of registers for programming each region.
+ */
+#define TZC_400_REGION_SIZE U(0x20)
+#define TZC_400_ACTION_OFF U(0x4)
+
+#define FILTER_OFFSET U(0x10)
+
+#ifndef __ASSEMBLER__
+
+#include <cdefs.h>
+#include <stdint.h>
+
+/*******************************************************************************
+ * Function & variable prototypes
+ ******************************************************************************/
+void tzc400_init(uintptr_t base);
+void tzc400_configure_region0(unsigned int sec_attr,
+ unsigned int ns_device_access);
+void tzc400_configure_region(unsigned int filters,
+ unsigned int region,
+ unsigned long long region_base,
+ unsigned long long region_top,
+ unsigned int sec_attr,
+ unsigned int nsaid_permissions);
+void tzc400_update_filters(unsigned int region, unsigned int filters);
+void tzc400_set_action(unsigned int action);
+void tzc400_enable_filters(void);
+void tzc400_disable_filters(void);
+int tzc400_it_handler(void);
+
+static inline void tzc_init(uintptr_t base)
+{
+ tzc400_init(base);
+}
+
+static inline void tzc_configure_region0(
+ unsigned int sec_attr,
+ unsigned int ns_device_access)
+{
+ tzc400_configure_region0(sec_attr, ns_device_access);
+}
+
+static inline void tzc_configure_region(
+ unsigned int filters,
+ unsigned int region,
+ unsigned long long region_base,
+ unsigned long long region_top,
+ unsigned int sec_attr,
+ unsigned int ns_device_access)
+{
+ tzc400_configure_region(filters, region, region_base,
+ region_top, sec_attr, ns_device_access);
+}
+
+static inline void tzc_set_action(unsigned int action)
+{
+ tzc400_set_action(action);
+}
+
+
+static inline void tzc_enable_filters(void)
+{
+ tzc400_enable_filters();
+}
+
+static inline void tzc_disable_filters(void)
+{
+ tzc400_disable_filters();
+}
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* TZC400_H */
diff --git a/include/drivers/arm/tzc_common.h b/include/drivers/arm/tzc_common.h
new file mode 100644
index 0000000..e58201c
--- /dev/null
+++ b/include/drivers/arm/tzc_common.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TZC_COMMON_H
+#define TZC_COMMON_H
+
+#include <lib/utils_def.h>
+
+/*
+ * Offset of core registers from the start of the base of configuration
+ * registers for each region.
+ */
+
+/* ID Registers */
+#define PID0_OFF U(0xfe0)
+#define PID1_OFF U(0xfe4)
+#define PID2_OFF U(0xfe8)
+#define PID3_OFF U(0xfec)
+#define PID4_OFF U(0xfd0)
+#define CID0_OFF U(0xff0)
+#define CID1_OFF U(0xff4)
+#define CID2_OFF U(0xff8)
+#define CID3_OFF U(0xffc)
+
+/*
+ * What type of action is expected when an access violation occurs.
+ * The memory requested is returned as zero. But we can also raise an event to
+ * let the system know it happened.
+ * We can raise an interrupt(INT) and/or cause an exception(ERR).
+ * TZC_ACTION_NONE - No interrupt, no Exception
+ * TZC_ACTION_ERR - No interrupt, raise exception -> sync external
+ * data abort
+ * TZC_ACTION_INT - Raise interrupt, no exception
+ * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync
+ * external data abort
+ */
+#define TZC_ACTION_NONE U(0)
+#define TZC_ACTION_ERR U(1)
+#define TZC_ACTION_INT U(2)
+#define TZC_ACTION_ERR_INT (TZC_ACTION_ERR | TZC_ACTION_INT)
+
+/* Bit positions of TZC_ACTION registers */
+#define TZC_ACTION_RV_SHIFT 0
+#define TZC_ACTION_RV_MASK U(0x3)
+#define TZC_ACTION_RV_LOWOK U(0x0)
+#define TZC_ACTION_RV_LOWERR U(0x1)
+#define TZC_ACTION_RV_HIGHOK U(0x2)
+#define TZC_ACTION_RV_HIGHERR U(0x3)
+
+/*
+ * Controls secure access to a region. If not enabled secure access is not
+ * allowed to region.
+ */
+#define TZC_REGION_S_NONE U(0)
+#define TZC_REGION_S_RD U(1)
+#define TZC_REGION_S_WR U(2)
+#define TZC_REGION_S_RDWR (TZC_REGION_S_RD | TZC_REGION_S_WR)
+
+#define TZC_REGION_ATTR_S_RD_SHIFT 30
+#define TZC_REGION_ATTR_S_WR_SHIFT 31
+#define TZC_REGION_ATTR_F_EN_SHIFT 0
+#define TZC_REGION_ATTR_SEC_SHIFT 30
+#define TZC_REGION_ATTR_S_RD_MASK U(0x1)
+#define TZC_REGION_ATTR_S_WR_MASK U(0x1)
+#define TZC_REGION_ATTR_SEC_MASK U(0x3)
+
+#define TZC_REGION_ACCESS_WR_EN_SHIFT 16
+#define TZC_REGION_ACCESS_RD_EN_SHIFT 0
+#define TZC_REGION_ACCESS_ID_MASK U(0xf)
+
+/* Macros for allowing Non-Secure access to a region based on NSAID */
+#define TZC_REGION_ACCESS_RD(nsaid) \
+ ((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \
+ TZC_REGION_ACCESS_RD_EN_SHIFT)
+#define TZC_REGION_ACCESS_WR(nsaid) \
+ ((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \
+ TZC_REGION_ACCESS_WR_EN_SHIFT)
+#define TZC_REGION_ACCESS_RDWR(nsaid) \
+ (TZC_REGION_ACCESS_RD(nsaid) | \
+ TZC_REGION_ACCESS_WR(nsaid))
+
+/* Returns offset of registers to program for a given region no */
+#define TZC_REGION_OFFSET(region_size, region_no) \
+ ((region_size) * (region_no))
+
+#endif /* TZC_COMMON_H */
diff --git a/include/drivers/arm/tzc_dmc500.h b/include/drivers/arm/tzc_dmc500.h
new file mode 100644
index 0000000..cce074c
--- /dev/null
+++ b/include/drivers/arm/tzc_dmc500.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TZC_DMC500_H
+#define TZC_DMC500_H
+
+#include <drivers/arm/tzc_common.h>
+#include <lib/utils_def.h>
+
+#define SI_STATUS_OFFSET U(0x000)
+#define SI_STATE_CTRL_OFFSET U(0x030)
+#define SI_FLUSH_CTRL_OFFSET U(0x034)
+#define SI_INT_CONTROL_OFFSET U(0x048)
+
+#define SI_INT_STATUS_OFFSET U(0x004)
+#define SI_TZ_FAIL_ADDRESS_LOW_OFFSET U(0x008)
+#define SI_TZ_FAIL_ADDRESS_HIGH_OFFSET U(0x00c)
+#define SI_FAIL_CONTROL_OFFSET U(0x010)
+#define SI_FAIL_ID_OFFSET U(0x014)
+#define SI_INT_CLR_OFFSET U(0x04c)
+
+/*
+ * DMC-500 has 2 system interfaces each having a similar set of regs
+ * to configure each interface.
+ */
+#define SI0_BASE U(0x0000)
+#define SI1_BASE U(0x0200)
+
+/* Bit positions of SIx_SI_STATUS */
+#define SI_EMPTY_SHIFT 1
+#define SI_STALL_ACK_SHIFT 0
+#define SI_EMPTY_MASK U(0x01)
+#define SI_STALL_ACK_MASK U(0x01)
+
+/* Bit positions of SIx_SI_INT_STATUS */
+#define PMU_REQ_INT_OVERFLOW_STATUS_SHIFT 18
+#define FAILED_ACCESS_INT_OVERFLOW_STATUS_SHIFT 16
+#define PMU_REQ_INT_STATUS_SHIFT 2
+#define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_SHIFT 1
+#define FAILED_ACCESS_INT_STATUS_SHIFT 0
+#define PMU_REQ_INT_OVERFLOW_STATUS_MASK U(0x1)
+#define FAILED_ACCESS_INT_OVERFLOW_STATUS_MASK U(0x1)
+#define PMU_REQ_INT_STATUS_MASK U(0x1)
+#define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_MASK U(0x1)
+#define FAILED_ACCESS_INT_STATUS_MASK U(0x1)
+
+/* Bit positions of SIx_TZ_FAIL_CONTROL */
+#define DIRECTION_SHIFT 24
+#define NON_SECURE_SHIFT 21
+#define PRIVILEGED_SHIFT 20
+#define FAILED_ACCESS_INT_INFO_RANK_MASKED_SHIFT 3
+#define FAILED_ACCESS_INT_INFO_UNMAPPED_SHIFT 2
+#define FAILED_ACCESS_INT_TZ_FAIL_SHIFT 1
+#define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_SHIFT 0
+#define DIRECTION_MASK U(0x1)
+#define NON_SECURE_MASK U(0x1)
+#define PRIVILEGED_MASK U(0x1)
+#define FAILED_ACCESS_INT_INFO_RANK_MASKED_MASK U(0x1)
+#define FAILED_ACCESS_INT_INFO_UNMAPPED_MASK U(0x1)
+#define FAILED_ACCESS_INT_TZ_FAIL_MASK U(0x1)
+#define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_MASK U(0x1)
+
+/* Bit positions of SIx_FAIL_STATUS */
+#define FAIL_ID_VNET_SHIFT 24
+#define FAIL_ID_ID_SHIFT 0
+#define FAIL_ID_VNET_MASK U(0xf)
+#define FAIL_ID_ID_MASK U(0xffffff)
+
+/* Bit positions of SIx_SI_STATE_CONTRL */
+#define SI_STALL_REQ_GO 0x0
+#define SI_STALL_REQ_STALL 0x1
+
+/* Bit positions of SIx_SI_FLUSH_CONTROL */
+#define SI_FLUSH_REQ_INACTIVE 0x0
+#define SI_FLUSH_REQ_ACTIVE 0x1
+#define SI_FLUSH_REQ_MASK 0x1
+
+/* Bit positions of SIx_SI_INT_CONTROL */
+#define PMU_REQ_INT_EN_SHIFT 2
+#define OVERLAP_DETECT_INT_EN_SHIFT 1
+#define FAILED_ACCESS_INT_EN_SHIFT 0
+#define PMU_REQ_INT_EN_MASK U(0x1)
+#define OVERLAP_DETECT_INT_EN_MASK U(0x1)
+#define FAILED_ACCESS_INT_EN_MASK U(0x1)
+#define PMU_REQ_INT_EN U(0x1)
+#define OVERLAP_DETECT_INT_EN U(0x1)
+#define FAILED_ACCESS_INT_EN U(0x1)
+
+/* Bit positions of SIx_SI_INT_CLR */
+#define PMU_REQ_OFLOW_CLR_SHIFT 18
+#define FAILED_ACCESS_OFLOW_CLR_SHIFT 16
+#define PMU_REQ_INT_CLR_SHIFT 2
+#define FAILED_ACCESS_INT_CLR_SHIFT 0
+#define PMU_REQ_OFLOW_CLR_MASK U(0x1)
+#define FAILED_ACCESS_OFLOW_CLR_MASK U(0x1)
+#define PMU_REQ_INT_CLR_MASK U(0x1)
+#define FAILED_ACCESS_INT_CLR_MASK U(0x1)
+#define PMU_REQ_OFLOW_CLR U(0x1)
+#define FAILED_ACCESS_OFLOW_CLR U(0x1)
+#define PMU_REQ_INT_CLR U(0x1)
+#define FAILED_ACCESS_INT_CLR U(0x1)
+
+/* Macro to get the correct base register for a system interface */
+#define IFACE_OFFSET(sys_if) ((sys_if) ? SI1_BASE : SI0_BASE)
+
+#define MAX_SYS_IF_COUNT U(2)
+#define MAX_REGION_VAL 8
+
+/* DMC-500 supports striping across a max of 4 DMC instances */
+#define MAX_DMC_COUNT 4
+
+/* Consist of part_number_1 and part_number_0 */
+#define DMC500_PERIPHERAL_ID U(0x0450)
+
+/* Filter enable bits in a TZC */
+#define TZC_DMC500_REGION_ATTR_F_EN_MASK U(0x1)
+
+/* Length of registers for configuring each region */
+#define TZC_DMC500_REGION_SIZE U(0x018)
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+/*
+ * Contains the base addresses of all the DMC instances.
+ */
+typedef struct tzc_dmc500_driver_data {
+ uintptr_t dmc_base[MAX_DMC_COUNT];
+ int dmc_count;
+ unsigned int sys_if_count;
+} tzc_dmc500_driver_data_t;
+
+void tzc_dmc500_driver_init(const tzc_dmc500_driver_data_t *plat_driver_data);
+void tzc_dmc500_configure_region0(unsigned int sec_attr,
+ unsigned int nsaid_permissions);
+void tzc_dmc500_configure_region(unsigned int region_no,
+ unsigned long long region_base,
+ unsigned long long region_top,
+ unsigned int sec_attr,
+ unsigned int nsaid_permissions);
+void tzc_dmc500_set_action(unsigned int action);
+void tzc_dmc500_config_complete(void);
+int tzc_dmc500_verify_complete(void);
+
+
+#endif /* __ASSEMBLER__ */
+#endif /* TZC_DMC500_H */
diff --git a/include/drivers/arm/tzc_dmc620.h b/include/drivers/arm/tzc_dmc620.h
new file mode 100644
index 0000000..26c444d
--- /dev/null
+++ b/include/drivers/arm/tzc_dmc620.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TZC_DMC620_H
+#define TZC_DMC620_H
+
+#include <lib/utils_def.h>
+
+/* DMC-620 memc register offsets */
+#define DMC620_MEMC_STATUS U(0x0000)
+#define DMC620_MEMC_CMD U(0x0008)
+
+/* Mask value to check the status of memc_cmd register */
+#define DMC620_MEMC_CMD_MASK U(0x00000007)
+
+/* memc_cmd register's action values */
+#define DMC620_MEMC_CMD_GO U(0x00000003)
+#define DMC620_MEMC_CMD_EXECUTE U(0x00000004)
+
+/* Address offsets of access address next region 0 registers */
+#define DMC620_ACC_ADDR_MIN_31_00_NEXT_BASE U(0x0080)
+#define DMC620_ACC_ADDR_MIN_47_32_NEXT_BASE U(0x0084)
+#define DMC620_ACC_ADDR_MAX_31_00_NEXT_BASE U(0x0088)
+#define DMC620_ACC_ADDR_MAX_47_32_NEXT_BASE U(0x008c)
+
+/* Length of one block of access address next register region */
+#define DMC620_ACC_ADDR_NEXT_SIZE U(0x0010)
+
+/* Address offsets of access address next registers */
+#define DMC620_ACC_ADDR_MIN_31_00_NEXT(region_no) \
+ (DMC620_ACC_ADDR_MIN_31_00_NEXT_BASE + \
+ ((region_no) * DMC620_ACC_ADDR_NEXT_SIZE))
+#define DMC620_ACC_ADDR_MIN_47_32_NEXT(region_no) \
+ (DMC620_ACC_ADDR_MIN_47_32_NEXT_BASE + \
+ ((region_no) * DMC620_ACC_ADDR_NEXT_SIZE))
+#define DMC620_ACC_ADDR_MAX_31_00_NEXT(region_no) \
+ (DMC620_ACC_ADDR_MAX_31_00_NEXT_BASE + \
+ ((region_no) * DMC620_ACC_ADDR_NEXT_SIZE))
+#define DMC620_ACC_ADDR_MAX_47_32_NEXT(region_no) \
+ (DMC620_ACC_ADDR_MAX_47_32_NEXT_BASE + \
+ ((region_no) * DMC620_ACC_ADDR_NEXT_SIZE))
+
+/* Number of TZC address regions in DMC-620 */
+#define DMC620_ACC_ADDR_COUNT U(8)
+/* Width of access address registers */
+#define DMC620_ACC_ADDR_WIDTH U(32)
+
+/* Peripheral ID registers offsets */
+#define DMC620_PERIPHERAL_ID_0 U(0x1fe0)
+
+/* Default values in id registers */
+#define DMC620_PERIPHERAL_ID_0_VALUE U(0x00000054)
+
+/* Secure access region attributes. */
+#define TZC_DMC620_REGION_NS_RD U(0x00000001)
+#define TZC_DMC620_REGION_NS_WR U(0x00000002)
+#define TZC_DMC620_REGION_NS_RDWR \
+ (TZC_DMC620_REGION_NS_RD | TZC_DMC620_REGION_NS_WR)
+#define TZC_DMC620_REGION_S_RD U(0x00000004)
+#define TZC_DMC620_REGION_S_WR U(0x00000008)
+#define TZC_DMC620_REGION_S_RDWR \
+ (TZC_DMC620_REGION_S_RD | TZC_DMC620_REGION_S_WR)
+#define TZC_DMC620_REGION_S_NS_RDWR \
+ (TZC_DMC620_REGION_NS_RDWR | TZC_DMC620_REGION_S_RDWR)
+
+/*
+ * Contains pointer to the base addresses of all the DMC-620 instances.
+ * 'dmc_count' specifies the number of DMC base addresses contained in the
+ * array pointed to by dmc_base.
+ */
+typedef struct tzc_dmc620_driver_data {
+ const uintptr_t *dmc_base;
+ const unsigned int dmc_count;
+} tzc_dmc620_driver_data_t;
+
+/*
+ * Contains region base, region top addresses and corresponding attributes
+ * for configuring TZC access region registers.
+ */
+typedef struct tzc_dmc620_acc_addr_data {
+ const unsigned long long region_base;
+ const unsigned long long region_top;
+ const unsigned int sec_attr;
+} tzc_dmc620_acc_addr_data_t;
+
+/*
+ * Contains platform specific data for configuring TZC region base and
+ * region top address. 'acc_addr_count' specifies the number of
+ * valid entries in 'plat_acc_addr_data' array.
+ */
+typedef struct tzc_dmc620_config_data {
+ const tzc_dmc620_driver_data_t *plat_drv_data;
+ const tzc_dmc620_acc_addr_data_t *plat_acc_addr_data;
+ const uint8_t acc_addr_count;
+} tzc_dmc620_config_data_t;
+
+/* Function prototypes */
+void arm_tzc_dmc620_setup(const tzc_dmc620_config_data_t *plat_config_data);
+
+#endif /* TZC_DMC620_H */
+
diff --git a/include/drivers/auth/auth_common.h b/include/drivers/auth/auth_common.h
new file mode 100644
index 0000000..e6859fd
--- /dev/null
+++ b/include/drivers/auth/auth_common.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AUTH_COMMON_H
+#define AUTH_COMMON_H
+
+/*
+ * Authentication framework common types
+ */
+
+/*
+ * Type of parameters that can be extracted from an image and
+ * used for authentication
+ */
+typedef enum auth_param_type_enum {
+ AUTH_PARAM_NONE,
+ AUTH_PARAM_RAW_DATA, /* Raw image data */
+ AUTH_PARAM_SIG, /* The image signature */
+ AUTH_PARAM_SIG_ALG, /* The image signature algorithm */
+ AUTH_PARAM_HASH, /* A hash (including the algorithm) */
+ AUTH_PARAM_PUB_KEY, /* A public key */
+ AUTH_PARAM_NV_CTR, /* A non-volatile counter */
+} auth_param_type_t;
+
+/*
+ * Defines an authentication parameter. The cookie will be interpreted by the
+ * image parser module.
+ */
+typedef struct auth_param_type_desc_s {
+ auth_param_type_t type;
+ void *cookie;
+} auth_param_type_desc_t;
+
+/*
+ * Store a pointer to the authentication parameter and its length
+ */
+typedef struct auth_param_data_desc_s {
+ void *ptr;
+ unsigned int len;
+} auth_param_data_desc_t;
+
+/*
+ * Authentication parameter descriptor, including type and value
+ */
+typedef struct auth_param_desc_s {
+ auth_param_type_desc_t *type_desc;
+ auth_param_data_desc_t data;
+} auth_param_desc_t;
+
+/*
+ * The method type defines how an image is authenticated
+ */
+typedef enum auth_method_type_enum {
+ AUTH_METHOD_NONE = 0,
+ AUTH_METHOD_HASH, /* Authenticate by hash matching */
+ AUTH_METHOD_SIG, /* Authenticate by PK operation */
+ AUTH_METHOD_NV_CTR, /* Authenticate by Non-Volatile Counter */
+ AUTH_METHOD_NUM /* Number of methods */
+} auth_method_type_t;
+
+/*
+ * Parameters for authentication by hash matching
+ */
+typedef struct auth_method_param_hash_s {
+ auth_param_type_desc_t *data; /* Data to hash */
+ auth_param_type_desc_t *hash; /* Hash to match with */
+} auth_method_param_hash_t;
+
+/*
+ * Parameters for authentication by signature
+ */
+typedef struct auth_method_param_sig_s {
+ auth_param_type_desc_t *pk; /* Public key */
+ auth_param_type_desc_t *sig; /* Signature to check */
+ auth_param_type_desc_t *alg; /* Signature algorithm */
+ auth_param_type_desc_t *data; /* Data signed */
+} auth_method_param_sig_t;
+
+/*
+ * Parameters for authentication by NV counter
+ */
+typedef struct auth_method_param_nv_ctr_s {
+ auth_param_type_desc_t *cert_nv_ctr; /* NV counter in certificate */
+ auth_param_type_desc_t *plat_nv_ctr; /* NV counter in platform */
+} auth_method_param_nv_ctr_t;
+
+/*
+ * Authentication method descriptor
+ */
+typedef struct auth_method_desc_s {
+ auth_method_type_t type;
+ union {
+ auth_method_param_hash_t hash;
+ auth_method_param_sig_t sig;
+ auth_method_param_nv_ctr_t nv_ctr;
+ } param;
+} auth_method_desc_t;
+
+/*
+ * Helper macro to define an authentication parameter type descriptor
+ */
+#define AUTH_PARAM_TYPE_DESC(_type, _cookie) \
+ { \
+ .type = _type, \
+ .cookie = (void *)_cookie \
+ }
+
+/*
+ * Helper macro to define an authentication parameter data descriptor
+ */
+#define AUTH_PARAM_DATA_DESC(_ptr, _len) \
+ { \
+ .ptr = (void *)_ptr, \
+ .len = (unsigned int)_len \
+ }
+
+#endif /* AUTH_COMMON_H */
diff --git a/include/drivers/auth/auth_mod.h b/include/drivers/auth/auth_mod.h
new file mode 100644
index 0000000..94537f6
--- /dev/null
+++ b/include/drivers/auth/auth_mod.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AUTH_MOD_H
+#define AUTH_MOD_H
+
+#include <common/tbbr/cot_def.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <drivers/auth/auth_common.h>
+#include <drivers/auth/img_parser_mod.h>
+
+#include <lib/utils_def.h>
+
+/*
+ * Image flags
+ */
+#define IMG_FLAG_AUTHENTICATED (1 << 0)
+
+#if COT_DESC_IN_DTB && !IMAGE_BL1
+/*
+ * Authentication image descriptor
+ */
+typedef struct auth_img_desc_s {
+ unsigned int img_id;
+ img_type_t img_type;
+ const struct auth_img_desc_s *parent;
+ auth_method_desc_t *img_auth_methods;
+ auth_param_desc_t *authenticated_data;
+} auth_img_desc_t;
+#else
+/*
+ * Authentication image descriptor
+ */
+typedef struct auth_img_desc_s {
+ unsigned int img_id;
+ img_type_t img_type;
+ const struct auth_img_desc_s *parent;
+ const auth_method_desc_t *const img_auth_methods;
+ const auth_param_desc_t *const authenticated_data;
+} auth_img_desc_t;
+#endif /* COT_DESC_IN_DTB && !IMAGE_BL1 */
+
+/* Public functions */
+#if TRUSTED_BOARD_BOOT
+void auth_mod_init(void);
+#else
+static inline void auth_mod_init(void)
+{
+}
+#endif /* TRUSTED_BOARD_BOOT */
+int auth_mod_get_parent_id(unsigned int img_id, unsigned int *parent_id);
+int auth_mod_verify_img(unsigned int img_id,
+ void *img_ptr,
+ unsigned int img_len);
+
+/* Macro to register a CoT defined as an array of auth_img_desc_t pointers */
+#define REGISTER_COT(_cot) \
+ const auth_img_desc_t *const *const cot_desc_ptr = (_cot); \
+ const size_t cot_desc_size = ARRAY_SIZE(_cot); \
+ unsigned int auth_img_flags[MAX_NUMBER_IDS]
+
+extern const auth_img_desc_t *const *const cot_desc_ptr;
+extern const size_t cot_desc_size;
+extern unsigned int auth_img_flags[MAX_NUMBER_IDS];
+
+#if defined(SPD_spmd)
+
+#define DEFINE_SIP_SP_PKG(n) DEFINE_SP_PKG(n, sip_sp_content_cert)
+#define DEFINE_PLAT_SP_PKG(n) DEFINE_SP_PKG(n, plat_sp_content_cert)
+
+#define DEFINE_SP_PKG(n, cert) \
+ static const auth_img_desc_t sp_pkg##n = { \
+ .img_id = SP_PKG##n##_ID, \
+ .img_type = IMG_RAW, \
+ .parent = &cert, \
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { \
+ [0] = { \
+ .type = AUTH_METHOD_HASH, \
+ .param.hash = { \
+ .data = &raw_data, \
+ .hash = &sp_pkg##n##_hash \
+ } \
+ } \
+ } \
+ }
+
+#endif
+
+#endif /* AUTH_MOD_H */
diff --git a/include/drivers/auth/crypto_mod.h b/include/drivers/auth/crypto_mod.h
new file mode 100644
index 0000000..3a23df4
--- /dev/null
+++ b/include/drivers/auth/crypto_mod.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CRYPTO_MOD_H
+#define CRYPTO_MOD_H
+
+#define CRYPTO_AUTH_VERIFY_ONLY 1
+#define CRYPTO_HASH_CALC_ONLY 2
+#define CRYPTO_AUTH_VERIFY_AND_HASH_CALC 3
+
+/* Return values */
+enum crypto_ret_value {
+ CRYPTO_SUCCESS = 0,
+ CRYPTO_ERR_INIT,
+ CRYPTO_ERR_HASH,
+ CRYPTO_ERR_SIGNATURE,
+ CRYPTO_ERR_DECRYPTION,
+ CRYPTO_ERR_UNKNOWN
+};
+
+#define CRYPTO_MAX_IV_SIZE 16U
+#define CRYPTO_MAX_TAG_SIZE 16U
+
+/* Decryption algorithm */
+enum crypto_dec_algo {
+ CRYPTO_GCM_DECRYPT = 0
+};
+
+/* Message digest algorithm */
+enum crypto_md_algo {
+ CRYPTO_MD_SHA256,
+ CRYPTO_MD_SHA384,
+ CRYPTO_MD_SHA512,
+};
+
+/* Maximum size as per the known stronger hash algorithm i.e.SHA512 */
+#define CRYPTO_MD_MAX_SIZE 64U
+
+/*
+ * Cryptographic library descriptor
+ */
+typedef struct crypto_lib_desc_s {
+ const char *name;
+
+ /* Initialize library. This function is not expected to fail. All errors
+ * must be handled inside the function, asserting or panicing in case of
+ * a non-recoverable error */
+ void (*init)(void);
+
+ /* Verify a digital signature. Return one of the
+ * 'enum crypto_ret_value' options */
+#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \
+CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
+ int (*verify_signature)(void *data_ptr, unsigned int data_len,
+ void *sig_ptr, unsigned int sig_len,
+ void *sig_alg, unsigned int sig_alg_len,
+ void *pk_ptr, unsigned int pk_len);
+
+ /* Verify a hash. Return one of the 'enum crypto_ret_value' options */
+ int (*verify_hash)(void *data_ptr, unsigned int data_len,
+ void *digest_info_ptr, unsigned int digest_info_len);
+#endif /* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \
+ CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */
+
+#if CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \
+CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
+ /* Calculate a hash. Return hash value */
+ int (*calc_hash)(enum crypto_md_algo md_alg, void *data_ptr,
+ unsigned int data_len,
+ unsigned char output[CRYPTO_MD_MAX_SIZE]);
+#endif /* CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \
+ CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */
+
+ /*
+ * Authenticated decryption. Return one of the
+ * 'enum crypto_ret_value' options.
+ */
+ int (*auth_decrypt)(enum crypto_dec_algo dec_algo, void *data_ptr,
+ size_t len, const void *key, unsigned int key_len,
+ unsigned int key_flags, const void *iv,
+ unsigned int iv_len, const void *tag,
+ unsigned int tag_len);
+} crypto_lib_desc_t;
+
+/* Public functions */
+#if CRYPTO_SUPPORT
+void crypto_mod_init(void);
+#else
+static inline void crypto_mod_init(void)
+{
+}
+#endif /* CRYPTO_SUPPORT */
+
+#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \
+CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
+int crypto_mod_verify_signature(void *data_ptr, unsigned int data_len,
+ void *sig_ptr, unsigned int sig_len,
+ void *sig_alg_ptr, unsigned int sig_alg_len,
+ void *pk_ptr, unsigned int pk_len);
+int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len,
+ void *digest_info_ptr, unsigned int digest_info_len);
+#endif /* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \
+ CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */
+
+int crypto_mod_auth_decrypt(enum crypto_dec_algo dec_algo, void *data_ptr,
+ size_t len, const void *key, unsigned int key_len,
+ unsigned int key_flags, const void *iv,
+ unsigned int iv_len, const void *tag,
+ unsigned int tag_len);
+
+#if CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \
+CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
+int crypto_mod_calc_hash(enum crypto_md_algo alg, void *data_ptr,
+ unsigned int data_len,
+ unsigned char output[CRYPTO_MD_MAX_SIZE]);
+#endif /* CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \
+ CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */
+
+#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
+/* Macro to register a cryptographic library */
+#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \
+ _calc_hash, _auth_decrypt) \
+ const crypto_lib_desc_t crypto_lib_desc = { \
+ .name = _name, \
+ .init = _init, \
+ .verify_signature = _verify_signature, \
+ .verify_hash = _verify_hash, \
+ .calc_hash = _calc_hash, \
+ .auth_decrypt = _auth_decrypt \
+ }
+#elif CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY
+#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \
+ _auth_decrypt) \
+ const crypto_lib_desc_t crypto_lib_desc = { \
+ .name = _name, \
+ .init = _init, \
+ .verify_signature = _verify_signature, \
+ .verify_hash = _verify_hash, \
+ .auth_decrypt = _auth_decrypt \
+ }
+#elif CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY
+#define REGISTER_CRYPTO_LIB(_name, _init, _calc_hash) \
+ const crypto_lib_desc_t crypto_lib_desc = { \
+ .name = _name, \
+ .init = _init, \
+ .calc_hash = _calc_hash, \
+ }
+#endif /* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */
+
+extern const crypto_lib_desc_t crypto_lib_desc;
+
+#endif /* CRYPTO_MOD_H */
diff --git a/include/drivers/auth/img_parser_mod.h b/include/drivers/auth/img_parser_mod.h
new file mode 100644
index 0000000..b2fb60e
--- /dev/null
+++ b/include/drivers/auth/img_parser_mod.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IMG_PARSER_MOD_H
+#define IMG_PARSER_MOD_H
+
+#include <drivers/auth/auth_common.h>
+
+/*
+ * Return values
+ */
+enum img_parser_ret_value {
+ IMG_PARSER_OK,
+ IMG_PARSER_ERR, /* Parser internal error */
+ IMG_PARSER_ERR_FORMAT, /* Malformed image */
+ IMG_PARSER_ERR_NOT_FOUND /* Authentication data not found */
+};
+
+/*
+ * Image types. A parser should be instantiated and registered for each type
+ */
+typedef enum img_type_enum {
+ IMG_RAW, /* Binary image */
+ IMG_PLAT, /* Platform specific format */
+ IMG_CERT, /* X509v3 certificate */
+ IMG_MAX_TYPES,
+} img_type_t;
+
+/* Image parser library structure */
+typedef struct img_parser_lib_desc_s {
+ img_type_t img_type;
+ const char *name;
+
+ void (*init)(void);
+ int (*check_integrity)(void *img, unsigned int img_len);
+ int (*get_auth_param)(const auth_param_type_desc_t *type_desc,
+ void *img, unsigned int img_len,
+ void **param, unsigned int *param_len);
+} img_parser_lib_desc_t;
+
+/* Exported functions */
+void img_parser_init(void);
+int img_parser_check_integrity(img_type_t img_type,
+ void *img_ptr, unsigned int img_len);
+int img_parser_get_auth_param(img_type_t img_type,
+ const auth_param_type_desc_t *type_desc,
+ void *img_ptr, unsigned int img_len,
+ void **param_ptr, unsigned int *param_len);
+
+/* Macro to register an image parser library */
+#define REGISTER_IMG_PARSER_LIB(_type, _name, _init, _check_int, _get_param) \
+ static const img_parser_lib_desc_t __img_parser_lib_desc_##_type \
+ __section(".img_parser_lib_descs") __used = { \
+ .img_type = _type, \
+ .name = _name, \
+ .init = _init, \
+ .check_integrity = _check_int, \
+ .get_auth_param = _get_param \
+ }
+
+#endif /* IMG_PARSER_MOD_H */
diff --git a/include/drivers/auth/mbedtls/mbedtls_common.h b/include/drivers/auth/mbedtls/mbedtls_common.h
new file mode 100644
index 0000000..a9c2352
--- /dev/null
+++ b/include/drivers/auth/mbedtls/mbedtls_common.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MBEDTLS_COMMON_H
+#define MBEDTLS_COMMON_H
+
+void mbedtls_init(void);
+
+#endif /* MBEDTLS_COMMON_H */
diff --git a/include/drivers/auth/mbedtls/mbedtls_config.h b/include/drivers/auth/mbedtls/mbedtls_config.h
new file mode 100644
index 0000000..01e261a
--- /dev/null
+++ b/include/drivers/auth/mbedtls/mbedtls_config.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2015-2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef MBEDTLS_CONFIG_H
+#define MBEDTLS_CONFIG_H
+
+/*
+ * Key algorithms currently supported on mbed TLS libraries
+ */
+#define TF_MBEDTLS_RSA 1
+#define TF_MBEDTLS_ECDSA 2
+#define TF_MBEDTLS_RSA_AND_ECDSA 3
+
+#define TF_MBEDTLS_USE_RSA (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA \
+ || TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA)
+#define TF_MBEDTLS_USE_ECDSA (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA \
+ || TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA)
+
+/*
+ * Hash algorithms currently supported on mbed TLS libraries
+ */
+#define TF_MBEDTLS_SHA256 1
+#define TF_MBEDTLS_SHA384 2
+#define TF_MBEDTLS_SHA512 3
+
+/*
+ * Configuration file to build mbed TLS with the required features for
+ * Trusted Boot
+ */
+
+#define MBEDTLS_PLATFORM_MEMORY
+#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+/* Prevent mbed TLS from using snprintf so that it can use tf_snprintf. */
+#define MBEDTLS_PLATFORM_SNPRINTF_ALT
+
+#define MBEDTLS_PKCS1_V21
+
+#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
+#define MBEDTLS_X509_CHECK_KEY_USAGE
+#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
+
+#define MBEDTLS_ASN1_PARSE_C
+#define MBEDTLS_ASN1_WRITE_C
+
+#define MBEDTLS_BASE64_C
+#define MBEDTLS_BIGNUM_C
+
+#define MBEDTLS_ERROR_C
+#define MBEDTLS_MD_C
+
+#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
+#define MBEDTLS_OID_C
+
+#define MBEDTLS_PK_C
+#define MBEDTLS_PK_PARSE_C
+#define MBEDTLS_PK_WRITE_C
+
+#define MBEDTLS_PLATFORM_C
+
+#if TF_MBEDTLS_USE_ECDSA
+#define MBEDTLS_ECDSA_C
+#define MBEDTLS_ECP_C
+#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
+#define MBEDTLS_ECP_NO_INTERNAL_RNG
+#endif
+#if TF_MBEDTLS_USE_RSA
+#define MBEDTLS_RSA_C
+#define MBEDTLS_X509_RSASSA_PSS_SUPPORT
+#endif
+
+#define MBEDTLS_SHA256_C
+
+/*
+ * If either Trusted Boot or Measured Boot require a stronger algorithm than
+ * SHA-256, pull in SHA-512 support.
+ */
+#if (TF_MBEDTLS_HASH_ALG_ID != TF_MBEDTLS_SHA256) /* TBB hash algo */
+#define MBEDTLS_SHA512_C
+#else
+ /* TBB uses SHA-256, what about measured boot? */
+#if defined(TF_MBEDTLS_MBOOT_USE_SHA512)
+#define MBEDTLS_SHA512_C
+#endif
+#endif
+
+#define MBEDTLS_VERSION_C
+
+#define MBEDTLS_X509_USE_C
+#define MBEDTLS_X509_CRT_PARSE_C
+
+#if TF_MBEDTLS_USE_AES_GCM
+#define MBEDTLS_AES_C
+#define MBEDTLS_CIPHER_C
+#define MBEDTLS_GCM_C
+#endif
+
+/* MPI / BIGNUM options */
+#define MBEDTLS_MPI_WINDOW_SIZE 2
+
+#if TF_MBEDTLS_USE_RSA
+#if TF_MBEDTLS_KEY_SIZE <= 2048
+#define MBEDTLS_MPI_MAX_SIZE 256
+#else
+#define MBEDTLS_MPI_MAX_SIZE 512
+#endif
+#else
+#define MBEDTLS_MPI_MAX_SIZE 256
+#endif
+
+/* Memory buffer allocator options */
+#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 8
+
+/*
+ * Prevent the use of 128-bit division which
+ * creates dependency on external libraries.
+ */
+#define MBEDTLS_NO_UDBL_DIVISION
+
+#ifndef __ASSEMBLER__
+/* System headers required to build mbed TLS with the current configuration */
+#include <stdlib.h>
+#include <mbedtls/check_config.h>
+#endif
+
+/*
+ * Determine Mbed TLS heap size
+ * 13312 = 13*1024
+ * 11264 = 11*1024
+ * 7168 = 7*1024
+ */
+#if TF_MBEDTLS_USE_ECDSA
+#define TF_MBEDTLS_HEAP_SIZE U(13312)
+#elif TF_MBEDTLS_USE_RSA
+#if TF_MBEDTLS_KEY_SIZE <= 2048
+#define TF_MBEDTLS_HEAP_SIZE U(7168)
+#else
+#define TF_MBEDTLS_HEAP_SIZE U(11264)
+#endif
+#endif
+
+/*
+ * Warn if errors from certain functions are ignored.
+ *
+ * The warnings are always enabled (where supported) for critical functions
+ * where ignoring the return value is almost always a bug. This macro extends
+ * the warnings to more functions.
+ */
+#define MBEDTLS_CHECK_RETURN_WARNING
+
+#endif /* MBEDTLS_CONFIG_H */
diff --git a/include/drivers/auth/tbbr_cot_common.h b/include/drivers/auth/tbbr_cot_common.h
new file mode 100644
index 0000000..a51faee
--- /dev/null
+++ b/include/drivers/auth/tbbr_cot_common.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TBBR_COT_COMMON_H
+#define TBBR_COT_COMMON_H
+
+#include <drivers/auth/auth_mod.h>
+
+extern unsigned char tb_fw_hash_buf[HASH_DER_LEN];
+extern unsigned char scp_fw_hash_buf[HASH_DER_LEN];
+extern unsigned char nt_world_bl_hash_buf[HASH_DER_LEN];
+
+extern auth_param_type_desc_t trusted_nv_ctr;
+extern auth_param_type_desc_t subject_pk;
+extern auth_param_type_desc_t sig;
+extern auth_param_type_desc_t sig_alg;
+extern auth_param_type_desc_t raw_data;
+
+extern auth_param_type_desc_t tb_fw_hash;
+extern auth_param_type_desc_t tb_fw_config_hash;
+extern auth_param_type_desc_t fw_config_hash;
+
+extern const auth_img_desc_t trusted_boot_fw_cert;
+extern const auth_img_desc_t hw_config;
+
+#endif /* TBBR_COT_COMMON_H */
diff --git a/include/drivers/brcm/chimp.h b/include/drivers/brcm/chimp.h
new file mode 100644
index 0000000..02d528b
--- /dev/null
+++ b/include/drivers/brcm/chimp.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SR_CHIMP_H
+#define SR_CHIMP_H
+
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+#define CHIMP_WINDOW_SIZE 0x400000
+#define CHIMP_ERROR_OFFSET 28
+#define CHIMP_ERROR_MASK 0xf0000000
+
+#ifndef EMULATION_SETUP
+#define CHIMP_HANDSHAKE_TIMEOUT_MS 10000
+#else
+/*
+ * 1hr timeout for test in emulator
+ * By doing this ChiMP is given a chance to boot
+ * fully from the QSPI
+ * (on Palladium this takes upto 50 min depending on QSPI clk)
+ */
+
+#define CHIMP_HANDSHAKE_TIMEOUT_MS 3600000
+#endif
+
+#define CHIMP_BPE_MODE_ID_PATTERN (0x25000000)
+#define CHIMP_BPE_MODE_ID_MASK (0x7f000000)
+#define NIC_RESET_RELEASE_TIMEOUT_US (10)
+
+/* written by M0, used by ChiMP ROM */
+#define SR_IN_SMARTNIC_MODE_BIT 0
+/* written by M0, used by ChiMP ROM */
+#define SR_CHIMP_SECURE_BOOT_BIT 1
+/* cleared by AP, set by ChiMP BC2 code */
+#define SR_FLASH_ACCESS_DONE_BIT 2
+
+#ifdef USE_CHIMP
+void bcm_chimp_write(uintptr_t addr, uint32_t value);
+uint32_t bcm_chimp_read(uintptr_t addr);
+uint32_t bcm_chimp_read_ctrl(uint32_t offset);
+void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits);
+void bcm_chimp_setbits(uintptr_t addr, uint32_t bits);
+int bcm_chimp_is_nic_mode(void);
+void bcm_chimp_fru_prog_done(bool status);
+int bcm_chimp_handshake_done(void);
+int bcm_chimp_wait_handshake(void);
+/* Fastboot-related*/
+int bcm_chimp_initiate_fastboot(int fastboot_type);
+#else
+static inline void bcm_chimp_write(uintptr_t addr, uint32_t value)
+{
+}
+static inline uint32_t bcm_chimp_read(uintptr_t addr)
+{
+ return 0;
+}
+static inline uint32_t bcm_chimp_read_ctrl(uint32_t offset)
+{
+ return 0;
+}
+static inline void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits)
+{
+}
+static inline void bcm_chimp_setbits(uintptr_t addr, uint32_t bits)
+{
+}
+static inline int bcm_chimp_is_nic_mode(void)
+{
+ return 0;
+}
+static inline void bcm_chimp_fru_prog_done(bool status)
+{
+}
+static inline int bcm_chimp_handshake_done(void)
+{
+ return 0;
+}
+static inline int bcm_chimp_wait_handshake(void)
+{
+ return 0;
+}
+static inline int bcm_chimp_initiate_fastboot(int fastboot_type)
+{
+ return 0;
+}
+#endif /* USE_CHIMP */
+#endif
diff --git a/include/drivers/brcm/chimp_nv_defs.h b/include/drivers/brcm/chimp_nv_defs.h
new file mode 100644
index 0000000..9be361f
--- /dev/null
+++ b/include/drivers/brcm/chimp_nv_defs.h
@@ -0,0 +1,419 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BNXNVM_DEFS_H
+#define BNXNVM_DEFS_H
+
+#if defined(__GNUC__)
+ #define PACKED_STRUCT __packed
+#else /* non-GCC compiler */
+
+#ifndef DOS_DRIVERS
+ #pragma pack(push)
+ #pragma pack(1)
+#endif
+ #define PACKED_STRUCT
+#endif
+
+typedef uint32_t u32_t;
+typedef uint8_t u8_t;
+typedef uint16_t u16_t;
+
+#define BNXNVM_DEFAULT_BLOCK_SIZE 4096
+#define BNXNVM_UNUSED_BYTE_VALUE 0xff
+
+#define NV_MAX_BLOCK_SIZE 16384
+
+#define BITS_PER_BYTE (8)
+#define SIZEOF_IN_BITS(x) (sizeof(x)*BITS_PER_BYTE)
+
+/************************/
+/* byte-swapping macros */
+/************************/
+#define BYTE_SWAP_16(x) \
+ ((((u16_t)(x) & 0xff00) >> 8) | \
+ (((u16_t)(x) & 0x00ff) << 8))
+#define BYTE_SWAP_32(x) \
+ ((((u32_t)(x) & 0xff000000) >> 24) | \
+ (((u32_t)(x) & 0x00ff0000) >> 8) | \
+ (((u32_t)(x) & 0x0000ff00) << 8) | \
+ (((u32_t)(x) & 0x000000ff) << 24))
+
+/* auto-detect integer size */
+#define BYTE_SWAP_INT(x) \
+ (SIZEOF_IN_BITS(x) == 16 ? BYTE_SWAP_16(x) : \
+ SIZEOF_IN_BITS(x) == 32 ? BYTE_SWAP_32(x) : (x))
+
+/********************************/
+/* Architecture-specific macros */
+/********************************/
+#ifdef __BIG_ENDIAN__ /* e.g. Motorola */
+
+ #define BE_INT16(x) (x)
+ #define BE_INT32(x) (x)
+ #define BE_INT(x) (x)
+ #define LE_INT16(x) BYTE_SWAP_16(x)
+ #define LE_INT32(x) BYTE_SWAP_32(x)
+ #define LE_INT(x) BYTE_SWAP_INT(x)
+
+#else /* Little Endian (e.g. Intel) */
+
+ #define LE_INT16(x) (x)
+ #define LE_INT32(x) (x)
+ #define LE_INT(x) (x)
+ #define BE_INT16(x) BYTE_SWAP_16(x)
+ #define BE_INT32(x) BYTE_SWAP_32(x)
+ #define BE_INT(x) BYTE_SWAP_INT(x)
+
+#endif
+
+
+enum {
+ NV_OK = 0,
+ NV_NOT_NVRAM,
+ NV_BAD_MB,
+ NV_BAD_DIR_HEADER,
+ NV_BAD_DIR_ENTRY,
+ NV_FW_NOT_FOUND,
+};
+
+typedef struct {
+#define BNXNVM_MASTER_BLOCK_SIG BE_INT32(0x424E5834) /*"BNX4"*/
+ /* Signature*/
+ u32_t sig;
+ /* Length of Master Block Header, in bytes [32] */
+ u32_t length;
+ /* Block size, in bytes [4096] */
+ u32_t block_size;
+ /* Byte-offset to Directory Block (translated) */
+ u32_t directory_offset;
+ /* Byte-offset to Block Redirection Table (non-translated) */
+ u32_t redirect_offset;
+ /* Size, in bytes of Reserved Blocks region (at end of NVRAM) */
+ u32_t reserved_size;
+ /*
+ * Size of NVRAM (in bytes) - may be used to
+ * override auto-detected size
+ */
+ u32_t nvram_size;
+ /* CRC-32 (IEEE 802.3 compatible) of the above */
+ u32_t chksum;
+} PACKED_STRUCT bnxnvm_master_block_header_t;
+
+typedef struct {
+#define BNXNVM_DIRECTORY_BLOCK_SIG BE_INT32(0x44697230) /* "Dir0" */
+ /* Signature */
+ u32_t sig;
+ /* Length of Directory Header, in bytes [16] */
+ u32_t length;
+ /* Number of Directory Entries */
+ u32_t entries;
+ /* Length of each Directory Entry, in bytes [24] */
+ u32_t entry_length;
+} PACKED_STRUCT bnxnvm_directory_block_header_t;
+
+typedef struct {
+ /* Directory Entry Type (see enum bnxnvm_directory_type) */
+ u16_t type;
+ /* Instance of this Directory Entry type (0-based) */
+ u16_t ordinal;
+ /*
+ * Directory Entry Extension flags used to identify
+ * secondary instances of a type:ordinal combinations
+ */
+ u16_t ext;
+ /* Directory Entry Attribute flags used to describe the item contents */
+ u16_t attr;
+ /* Item location in NVRAM specified as offset (in bytes) */
+ u32_t item_location;
+ /*
+ * Length of NVRAM item in bytes
+ * (including padding - multiple of block size)
+ */
+ u32_t item_length;
+ /* Length of item data in bytes (excluding padding) */
+ u32_t data_length;
+ /*
+ * CRC-32 (IEEE 802.3 compatible) of item data
+ * (excluding padding) (optional)
+ */
+ u32_t data_chksum;
+} PACKED_STRUCT bnxnvm_directory_entry_t;
+
+enum bnxnvm_version_format {
+ /* US-ASCII string (not necessarily null-terminated) */
+ BNX_VERSION_FMT_ASCII = 0,
+ /* Each field 16-bits, displayed as unpadded decimal (e.g. "1.2.3.4") */
+ BNX_VERSION_FMT_DEC = 1,
+ /* A single hexadecimal value, up to 64-bits (no dots) */
+ BNX_VERSION_FMT_HEX = 2,
+ /* Multiple version values (three 8-bit version fields) */
+ BNX_VERSION_FMT_MULTI = 3
+};
+
+/* This structure definition must not change: */
+typedef struct {
+ u16_t flags; /* bit-flags (defaults to 0x0000) */
+ u8_t version_format; /* enum bnxnvm_version_format */
+ u8_t version_length; /* in bytes */
+ u8_t version[16]; /* version value */
+ u16_t dir_type; /* enum bnxnvm_directory_type */
+ /* size of the entire trailer (to locate end of component data) */
+ u16_t trailer_length;
+#define BNXNVM_COMPONENT_TRAILER_SIG BE_INT32(0x54726c72) /* "Trlr" */
+ u32_t sig;
+ u32_t chksum; /* CRC-32 of all bytes to this point */
+} PACKED_STRUCT bnxnvm_component_trailer_base_t;
+
+typedef struct {
+ /*
+ * new trailer members (e.g. digital signature)
+ * go here (insert at top):
+ */
+ u8_t rsa_sig[256]; /* 2048-bit RSA-encrypted SHA-256 hash */
+ bnxnvm_component_trailer_base_t base;
+} PACKED_STRUCT bnxnvm_component_trailer_t;
+
+#define BNX_MAX_LEN_DIR_NAME 12
+#define BNX_MAX_LEN_DIR_DESC 50
+/*********************************************************
+ * NVRAM Directory Entry/Item Types, Names, and Descriptions
+ *
+ * If you see a name or description that needs improvement,
+ * please correct it or raise for discussion.
+ * When adding a new directory type, it would be appreciated
+ * if you also updated ../../libs/nvm/bnxt_nvm_str.c.
+ * DIR_NAME macros may contain up to 12 alpha-numeric
+ * US-ASCII characters only, camelCase is preferred for clarity.
+ * DIR_DESC macros may contain up to 50 US-ASCII characters
+ * providing a verbose description of the directory type.
+ */
+enum bnxnvm_directory_type {
+ /* 0x00 Unused directory entry, available for use */
+ BNX_DIR_TYPE_UNUSED = 0,
+#define BNX_DIR_NAME_UNUSED "unused"
+#define BNX_DIR_DESC_UNUSED "Deleted directory entry, available for reuse"
+ /* 0x01 Package installation log */
+ BNX_DIR_TYPE_PKG_LOG = 1,
+#define BNX_DIR_NAME_PKG_LOG "pkgLog"
+#define BNX_DIR_DESC_PKG_LOG "Package Installation Log"
+ BNX_DIR_TYPE_CHIMP_PATCH = 3,
+#define BNX_DIR_NAME_CHIMP_PATCH "chimpPatch"
+#define BNX_DIR_DESC_CHIMP_PATCH "ChiMP Patch Firmware"
+ /* 0x04 ChiMP firmware: Boot Code phase 1 */
+ BNX_DIR_TYPE_BOOTCODE = 4,
+#define BNX_DIR_NAME_BOOTCODE "chimpBoot"
+#define BNX_DIR_DESC_BOOTCODE "Chip Management Processor Boot Firmware"
+ /* 0x05 VPD data block */
+ BNX_DIR_TYPE_VPD = 5,
+#define BNX_DIR_NAME_VPD "VPD"
+#define BNX_DIR_DESC_VPD "Vital Product Data"
+ /* 0x06 Exp ROM MBA */
+ BNX_DIR_TYPE_EXP_ROM_MBA = 6,
+#define BNX_DIR_NAME_EXP_ROM_MBA "MBA"
+#define BNX_DIR_DESC_EXP_ROM_MBA "Multiple Boot Agent Expansion ROM"
+ BNX_DIR_TYPE_AVS = 7, /* 0x07 AVS FW */
+#define BNX_DIR_NAME_AVS "AVS"
+#define BNX_DIR_DESC_AVS "Adaptive Voltage Scaling Firmware"
+ BNX_DIR_TYPE_PCIE = 8, /* 0x08 PCIE FW */
+#define BNX_DIR_NAME_PCIE "PCIEucode"
+#define BNX_DIR_DESC_PCIE "PCIe Microcode"
+ BNX_DIR_TYPE_PORT_MACRO = 9, /* 0x09 PORT MACRO FW */
+#define BNX_DIR_NAME_PORT_MACRO "portMacro"
+#define BNX_DIR_DESC_PORT_MACRO "Port Macro Firmware"
+ BNX_DIR_TYPE_APE_FW = 10, /* 0x0A APE Firmware */
+#define BNX_DIR_NAME_APE_FW "apeFW"
+#define BNX_DIR_DESC_APE_FW "Application Processing Engine Firmware"
+ /* 0x0B Patch firmware executed by APE ROM */
+ BNX_DIR_TYPE_APE_PATCH = 11,
+#define BNX_DIR_NAME_APE_PATCH "apePatch"
+#define BNX_DIR_DESC_APE_PATCH "APE Patch Firmware"
+ BNX_DIR_TYPE_KONG_FW = 12, /* 0x0C Kong Firmware */
+#define BNX_DIR_NAME_KONG_FW "kongFW"
+#define BNX_DIR_DESC_KONG_FW "Kong Firmware"
+ /* 0x0D Patch firmware executed by Kong ROM */
+ BNX_DIR_TYPE_KONG_PATCH = 13,
+#define BNX_DIR_NAME_KONG_PATCH "kongPatch"
+#define BNX_DIR_DESC_KONG_PATCH "Kong Patch Firmware"
+ BNX_DIR_TYPE_BONO_FW = 14, /* 0x0E Bono Firmware */
+#define BNX_DIR_NAME_BONO_FW "bonoFW"
+#define BNX_DIR_DESC_BONO_FW "Bono Firmware"
+ /* 0x0F Patch firmware executed by Bono ROM */
+ BNX_DIR_TYPE_BONO_PATCH = 15,
+#define BNX_DIR_NAME_BONO_PATCH "bonoPatch"
+#define BNX_DIR_DESC_BONO_PATCH "Bono Patch Firmware"
+ BNX_DIR_TYPE_TANG_FW = 16, /* 0x10 Tang firmware */
+#define BNX_DIR_NAME_TANG_FW "tangFW"
+#define BNX_DIR_DESC_TANG_FW "Tang Firmware"
+ /* 0x11 Patch firmware executed by Tang ROM */
+ BNX_DIR_TYPE_TANG_PATCH = 17,
+#define BNX_DIR_NAME_TANG_PATCH "tangPatch"
+#define BNX_DIR_DESC_TANG_PATCH "Tang Patch Firmware"
+ /* 0x12 ChiMP firmware: Boot Code phase 2 (loaded by phase 1) */
+ BNX_DIR_TYPE_BOOTCODE_2 = 18,
+#define BNX_DIR_NAME_BOOTCODE_2 "chimpHWRM"
+#define BNX_DIR_DESC_BOOTCODE_2 "ChiMP Hardware Resource Manager Firmware"
+ BNX_DIR_TYPE_CCM = 19, /* 0x13 CCM ROM binary */
+#define BNX_DIR_NAME_CCM "CCM"
+#define BNX_DIR_DESC_CCM "Comprehensive Configuration Management"
+ /* 0x14 PCI-IDs, PCI-related configuration properties */
+ BNX_DIR_TYPE_PCI_CFG = 20,
+#define BNX_DIR_NAME_PCI_CFG "pciCFG"
+#define BNX_DIR_DESC_PCI_CFG "PCIe Configuration Data"
+
+ BNX_DIR_TYPE_TSCF_UCODE = 21, /* 0x15 TSCF micro-code */
+#define BNX_DIR_NAME_TSCF_UCODE "PHYucode"
+#define BNX_DIR_DESC_TSCF_UCODE "Falcon PHY Microcode"
+ BNX_DIR_TYPE_ISCSI_BOOT = 22, /* 0x16 iSCSI Boot */
+#define BNX_DIR_NAME_ISCSI_BOOT "iSCSIboot"
+#define BNX_DIR_DESC_ISCSI_BOOT "iSCSI Boot Software Initiator"
+ /* 0x18 iSCSI Boot IPV6 - ***DEPRECATED*** */
+ BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24,
+ /* 0x19 iSCSI Boot IPV4N6 - ***DEPRECATED*** */
+ BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25,
+ BNX_DIR_TYPE_ISCSI_BOOT_CFG = 26, /* 0x1a iSCSI Boot CFG v6 */
+#define BNX_DIR_NAME_ISCSI_BOOT_CFG "iSCSIcfg"
+#define BNX_DIR_DESC_ISCSI_BOOT_CFG "iSCSI Boot Configuration Data"
+ BNX_DIR_TYPE_EXT_PHY = 27, /* 0x1b External PHY FW */
+#define BNX_DIR_NAME_EXT_PHY "extPHYfw"
+#define BNX_DIR_DESC_EXT_PHY "External PHY Firmware"
+ BNX_DIR_TYPE_MODULES_PN = 28, /* 0x1c Modules PartNum list */
+#define BNX_DIR_NAME_MODULES_PN "modPartNums"
+#define BNX_DIR_DESC_MODULES_PN "Optical Modules Part Number List"
+ BNX_DIR_TYPE_SHARED_CFG = 40, /* 0x28 shared configuration block */
+#define BNX_DIR_NAME_SHARED_CFG "sharedCFG"
+#define BNX_DIR_DESC_SHARED_CFG "Shared Configuration Data"
+ BNX_DIR_TYPE_PORT_CFG = 41, /* 0x29 port configuration block */
+#define BNX_DIR_NAME_PORT_CFG "portCFG"
+#define BNX_DIR_DESC_PORT_CFG "Port Configuration Data"
+ BNX_DIR_TYPE_FUNC_CFG = 42, /* 0x2A func configuration block */
+#define BNX_DIR_NAME_FUNC_CFG "funcCFG"
+#define BNX_DIR_DESC_FUNC_CFG "Function Configuration Data"
+
+ /* Management Firmware (TruManage) related dir entries*/
+ /* 0x30 Management firmware configuration (see BMCFG library)*/
+ BNX_DIR_TYPE_MGMT_CFG = 48,
+#define BNX_DIR_NAME_MGMT_CFG "mgmtCFG"
+#define BNX_DIR_DESC_MGMT_CFG "Out-of-band Management Configuration Data"
+ BNX_DIR_TYPE_MGMT_DATA = 49, /* 0x31 "Opaque Management Data" */
+#define BNX_DIR_NAME_MGMT_DATA "mgmtData"
+#define BNX_DIR_DESC_MGMT_DATA "Out-of-band Management Data"
+ BNX_DIR_TYPE_MGMT_WEB_DATA = 50, /* 0x32 "Web GUI" file data */
+#define BNX_DIR_NAME_MGMT_WEB_DATA "webData"
+#define BNX_DIR_DESC_MGMT_WEB_DATA "Out-of-band Management Web Data"
+ /* 0x33 "Web GUI" file metadata */
+ BNX_DIR_TYPE_MGMT_WEB_META = 51,
+#define BNX_DIR_NAME_MGMT_WEB_META "webMeta"
+#define BNX_DIR_DESC_MGMT_WEB_META "Out-of-band Management Web Metadata"
+ /* 0x34 Management firmware Event Log (a.k.a. "SEL") */
+ BNX_DIR_TYPE_MGMT_EVENT_LOG = 52,
+#define BNX_DIR_NAME_MGMT_EVENT_LOG "eventLog"
+#define BNX_DIR_DESC_MGMT_EVENT_LOG "Out-of-band Management Event Log"
+ /* 0x35 Management firmware Audit Log */
+ BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53
+#define BNX_DIR_NAME_MGMT_AUDIT_LOG "auditLog"
+#define BNX_DIR_DESC_MGMT_AUDIT_LOG "Out-of-band Management Audit Log"
+
+};
+
+/* For backwards compatibility only, may be removed later */
+#define BNX_DIR_TYPE_ISCSI_BOOT_CFG6 BNX_DIR_TYPE_ISCSI_BOOT_CFG
+
+/* Firmware NVM items of "APE BIN" format are identified with
+ * the following macro:
+ */
+#define BNX_DIR_TYPE_IS_APE_BIN_FMT(type)\
+ ((type) == BNX_DIR_TYPE_CHIMP_PATCH \
+ || (type) == BNX_DIR_TYPE_BOOTCODE \
+ || (type) == BNX_DIR_TYPE_BOOTCODE_2 \
+ || (type) == BNX_DIR_TYPE_APE_FW \
+ || (type) == BNX_DIR_TYPE_APE_PATCH \
+ || (type) == BNX_DIR_TYPE_TANG_FW \
+ || (type) == BNX_DIR_TYPE_TANG_PATCH \
+ || (type) == BNX_DIR_TYPE_KONG_FW \
+ || (type) == BNX_DIR_TYPE_KONG_PATCH \
+ || (type) == BNX_DIR_TYPE_BONO_FW \
+ || (type) == BNX_DIR_TYPE_BONO_PATCH \
+ )
+
+/* Other (non APE BIN) executable NVM items are identified with
+ * the following macro:
+ */
+#define BNX_DIR_TYPE_IS_OTHER_EXEC(type)\
+ ((type) == BNX_DIR_TYPE_AVS \
+ || (type) == BNX_DIR_TYPE_EXP_ROM_MBA \
+ || (type) == BNX_DIR_TYPE_PCIE \
+ || (type) == BNX_DIR_TYPE_TSCF_UCODE \
+ || (type) == BNX_DIR_TYPE_EXT_PHY \
+ || (type) == BNX_DIR_TYPE_CCM \
+ || (type) == BNX_DIR_TYPE_ISCSI_BOOT \
+ )
+
+/* Executable NVM items (e.g. microcode, firmware, software) identified
+ * with the following macro
+ */
+#define BNX_DIR_TYPE_IS_EXECUTABLE(type) \
+ (BNX_DIR_TYPE_IS_APE_BIN_FMT(type) \
+ || BNX_DIR_TYPE_IS_OTHER_EXEC(type))
+
+#define BNX_DIR_ORDINAL_FIRST 0 /* Ordinals are 0-based */
+
+/* No extension flags for this directory entry */
+#define BNX_DIR_EXT_NONE 0
+/* Directory entry is inactive (not used, not hidden,
+ * not available for reuse)
+ */
+#define BNX_DIR_EXT_INACTIVE (1 << 0)
+/* Directory content is a temporary staging location for
+ * updating the primary (non-update) directory entry contents
+ * (e.g. performing a secure firmware update)
+ */
+#define BNX_DIR_EXT_UPDATE (1 << 1)
+
+/* No attribute flags set for this directory entry */
+#define BNX_DIR_ATTR_NONE 0
+/* Directory entry checksum of contents is purposely incorrect */
+#define BNX_DIR_ATTR_NO_CHKSUM (1 << 0)
+/* Directory contents are in the form of a property-stream
+ * (e.g. configuration properties)
+ */
+#define BNX_DIR_ATTR_PROP_STREAM (1 << 1)
+/* Directory content (e.g. iSCSI boot) supports IPv4 */
+#define BNX_DIR_ATTR_IPv4 (1 << 2)
+/* Directory content (e.g. iSCSI boot) supports IPv6 */
+#define BNX_DIR_ATTR_IPv6 (1 << 3)
+/* Directory content includes standard NVM component trailer
+ * (bnxnvm_component_trailer_t)
+ */
+#define BNX_DIR_ATTR_TRAILER (1 << 4)
+
+/* Index of tab-delimited fields in each package log
+ * (BNX_DIR_TYPE_PKG_LOG) record (\n-terminated line):
+ */
+enum bnxnvm_pkglog_field_index {
+ /* Package installation date/time in ISO-8601 format */
+ BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0,
+ /* Installed package description (from package header) or "N/A" */
+ BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1,
+ /* Installed package version string (from package header) or "N/A" */
+ BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2,
+ /* Installed package creation/modification timestamp (ISO-8601) */
+ BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3,
+ /* Installed package checksum in hexadecimal (CRC-32) or "N/A" */
+ BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4,
+ /* Total number of packaged items applied in this installation */
+ BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5,
+ /* Hexadecimal bit-mask identifying which items were installed */
+ BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6
+};
+
+#if !defined(__GNUC__)
+#ifndef DOS_DRIVERS
+ #pragma pack(pop) /* original packing */
+#endif
+#endif
+
+#endif /* Don't add anything after this line */
diff --git a/include/drivers/brcm/dmu.h b/include/drivers/brcm/dmu.h
new file mode 100644
index 0000000..3a57bbd
--- /dev/null
+++ b/include/drivers/brcm/dmu.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2015 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DMU_H
+#define DMU_H
+
+/* Clock field should be 2 bits only */
+#define CLKCONFIG_MASK 0x3
+
+/* argument */
+struct DmuBlockEnable {
+ uint32_t sotp:1;
+ uint32_t pka_rng:1;
+ uint32_t crypto:1;
+ uint32_t spl:1;
+ uint32_t cdru_vgm:1;
+ uint32_t apbs_s0_idm:1;
+ uint32_t smau_s0_idm:1;
+};
+
+/* prototype */
+uint32_t bcm_dmu_block_enable(struct DmuBlockEnable dbe);
+uint32_t bcm_dmu_block_disable(struct DmuBlockEnable dbe);
+uint32_t bcm_set_ihost_pll_freq(uint32_t cluster_num, int ihost_pll_freq_sel);
+uint32_t bcm_get_ihost_pll_freq(uint32_t cluster_num);
+
+#define PLL_FREQ_BYPASS 0x0
+#define PLL_FREQ_FULL 0x1
+#define PLL_FREQ_HALF 0x2
+#define PLL_FREQ_QRTR 0x3
+
+#endif
diff --git a/include/drivers/brcm/emmc/bcm_emmc.h b/include/drivers/brcm/emmc/bcm_emmc.h
new file mode 100644
index 0000000..67f0602
--- /dev/null
+++ b/include/drivers/brcm/emmc/bcm_emmc.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EMMC_H
+#define EMMC_H
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include <platform_def.h>
+
+#include "emmc_chal_types.h"
+#include "emmc_chal_sd.h"
+#include "emmc_csl_sdprot.h"
+#include "emmc_csl_sdcmd.h"
+#include "emmc_pboot_hal_memory_drv.h"
+
+/* ------------------------------------------------------------------- */
+#define EXT_CSD_SIZE 512
+
+#ifdef PLAT_SD_MAX_READ_LENGTH
+#define SD_MAX_READ_LENGTH PLAT_SD_MAX_READ_LENGTH
+#ifdef USE_EMMC_LARGE_BLK_TRANSFER_LENGTH
+#define SD_MAX_BLK_TRANSFER_LENGTH 0x10000000
+#else
+#define SD_MAX_BLK_TRANSFER_LENGTH 0x1000
+#endif
+#else
+#define SD_MAX_READ_LENGTH EMMC_BLOCK_SIZE
+#define SD_MAX_BLK_TRANSFER_LENGTH EMMC_BLOCK_SIZE
+#endif
+
+struct emmc_global_buffer {
+ union {
+ uint8_t Ext_CSD_storage[EXT_CSD_SIZE];
+ uint8_t tempbuf[SD_MAX_READ_LENGTH];
+ } u;
+};
+
+struct emmc_global_vars {
+ struct sd_card_data cardData;
+ struct sd_handle sdHandle;
+ struct sd_dev sdDevice;
+ struct sd_card_info sdCard;
+ unsigned int init_done;
+};
+
+#define ICFG_SDIO0_CAP0__SLOT_TYPE_R 27
+#define ICFG_SDIO0_CAP0__INT_MODE_R 26
+#define ICFG_SDIO0_CAP0__SYS_BUS_64BIT_R 25
+#define ICFG_SDIO0_CAP0__VOLTAGE_1P8V_R 24
+#define ICFG_SDIO0_CAP0__VOLTAGE_3P0V_R 23
+#define ICFG_SDIO0_CAP0__VOLTAGE_3P3V_R 22
+#define ICFG_SDIO0_CAP0__SUSPEND_RESUME_R 21
+#define ICFG_SDIO0_CAP0__SDMA_R 20
+#define ICFG_SDIO0_CAP0__HIGH_SPEED_R 19
+#define ICFG_SDIO0_CAP0__ADMA2_R 18
+#define ICFG_SDIO0_CAP0__EXTENDED_MEDIA_R 17
+#define ICFG_SDIO0_CAP0__MAX_BLOCK_LEN_R 15
+#define ICFG_SDIO0_CAP0__BASE_CLK_FREQ_R 7
+#define ICFG_SDIO0_CAP0__TIMEOUT_UNIT_R 6
+#define ICFG_SDIO0_CAP0__TIMEOUT_CLK_FREQ_R 0
+#define ICFG_SDIO0_CAP1__SPI_BLOCK_MODE_R 22
+#define ICFG_SDIO0_CAP1__SPI_MODE_R 21
+#define ICFG_SDIO0_CAP1__CLK_MULT_R 13
+#define ICFG_SDIO0_CAP1__RETUNING_MODE_R 11
+#define ICFG_SDIO0_CAP1__TUNE_SDR50_R 10
+#define ICFG_SDIO0_CAP1__TIME_RETUNE_R 6
+#define ICFG_SDIO0_CAP1__DRIVER_D_R 5
+#define ICFG_SDIO0_CAP1__DRIVER_C_R 4
+#define ICFG_SDIO0_CAP1__DRIVER_A_R 3
+#define ICFG_SDIO0_CAP1__DDR50_R 2
+#define ICFG_SDIO0_CAP1__SDR104_R 1
+#define ICFG_SDIO0_CAP1__SDR50_R 0
+
+#define SDIO0_CTRL_REGS_BASE_ADDR (SDIO0_EMMCSDXC_SYSADDR)
+#define SDIO0_IDM_RESET_CTRL_ADDR (SDIO_IDM0_IDM_RESET_CONTROL)
+
+#define EMMC_CTRL_REGS_BASE_ADDR SDIO0_CTRL_REGS_BASE_ADDR
+#define EMMC_IDM_RESET_CTRL_ADDR SDIO0_IDM_RESET_CTRL_ADDR
+#define EMMC_IDM_IO_CTRL_DIRECT_ADDR SDIO_IDM0_IO_CONTROL_DIRECT
+
+extern struct emmc_global_buffer *emmc_global_buf_ptr;
+
+extern struct emmc_global_vars *emmc_global_vars_ptr;
+
+#define EMMC_CARD_DETECT_TIMEOUT_MS 1200
+#define EMMC_CMD_TIMEOUT_MS 200
+#define EMMC_BUSY_CMD_TIMEOUT_MS 200
+#define EMMC_CLOCK_SETTING_TIMEOUT_MS 100
+#define EMMC_WFE_RETRY 40000
+#define EMMC_WFE_RETRY_DELAY_US 10
+
+#ifdef EMMC_DEBUG
+#define EMMC_TRACE INFO
+#else
+#define EMMC_TRACE(...)
+#endif
+
+#endif /* EMMC_H */
diff --git a/include/drivers/brcm/emmc/emmc_api.h b/include/drivers/brcm/emmc/emmc_api.h
new file mode 100644
index 0000000..c4c2a58
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_api.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EMMC_API_H
+#define EMMC_API_H
+
+#include "bcm_emmc.h"
+#include "emmc_pboot_hal_memory_drv.h"
+
+#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
+/*
+ * The erasable unit of the eMMC is the Erase Group
+ * Erase group is measured in write blocks which
+ * are the basic writable units of the Device
+ * EMMC_ERASE_GROUP_SIZE is the number of writeable
+ * units (each unit is 512 bytes)
+ */
+
+/* Start address (sector) */
+#define EMMC_ERASE_START_BLOCK 0x0
+/* Number of blocks to be erased */
+#define EMMC_ERASE_BLOCK_COUNT 0x1
+
+#define EMMC_ERASE_USER_AREA 0
+#define EMMC_ERASE_BOOT_PARTITION1 1
+#define EMMC_ERASE_BOOT_PARTITION2 2
+
+/* eMMC partition to be erased */
+#define EMMC_ERASE_PARTITION EMMC_ERASE_USER_AREA
+#endif
+
+uint32_t bcm_emmc_init(bool card_rdy_only);
+void emmc_deinit(void);
+
+#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
+int emmc_erase(uintptr_t mem_addr, size_t num_of_blocks, uint32_t partition);
+#endif
+
+uint32_t emmc_partition_select(uint32_t partition);
+uint32_t emmc_read(uintptr_t mem_addr, uintptr_t storage_addr,
+ size_t storage_size, size_t bytes_to_read);
+uint32_t emmc_write(uintptr_t mem_addr, uintptr_t data_addr,
+ size_t bytes_to_write);
+#endif /* EMMC_API_H */
diff --git a/include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h b/include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h
new file mode 100644
index 0000000..96c333d
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h
@@ -0,0 +1,1116 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BRCM_RDB_SD4_EMMC_TOP_H
+#define BRCM_RDB_SD4_EMMC_TOP_H
+
+#define SD4_EMMC_TOP_SYSADDR_OFFSET 0x00000000
+#define SD4_EMMC_TOP_SYSADDR_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_SYSADDR_TYPE uint32_t
+#define SD4_EMMC_TOP_SYSADDR_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_SYSADDR_SYSADDR_SHIFT 0
+#define SD4_EMMC_TOP_SYSADDR_SYSADDR_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_BLOCK_OFFSET 0x00000004
+#define SD4_EMMC_TOP_BLOCK_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_BLOCK_TYPE uint32_t
+#define SD4_EMMC_TOP_BLOCK_RESERVED_MASK 0x00008000
+#define SD4_EMMC_TOP_BLOCK_BCNT_SHIFT 16
+#define SD4_EMMC_TOP_BLOCK_BCNT_MASK 0xFFFF0000
+#define SD4_EMMC_TOP_BLOCK_HSBS_SHIFT 12
+#define SD4_EMMC_TOP_BLOCK_HSBS_MASK 0x00007000
+#define SD4_EMMC_TOP_BLOCK_TBS_SHIFT 0
+#define SD4_EMMC_TOP_BLOCK_TBS_MASK 0x00000FFF
+
+#define SD4_EMMC_TOP_ARG_OFFSET 0x00000008
+#define SD4_EMMC_TOP_ARG_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_ARG_TYPE uint32_t
+#define SD4_EMMC_TOP_ARG_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_ARG_ARG_SHIFT 0
+#define SD4_EMMC_TOP_ARG_ARG_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_CMD_OFFSET 0x0000000C
+#define SD4_EMMC_TOP_CMD_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_CMD_TYPE uint32_t
+#define SD4_EMMC_TOP_CMD_RESERVED_MASK 0xC004FFC0
+#define SD4_EMMC_TOP_CMD_CIDX_SHIFT 24
+#define SD4_EMMC_TOP_CMD_CIDX_MASK 0x3F000000
+#define SD4_EMMC_TOP_CMD_CTYP_SHIFT 22
+#define SD4_EMMC_TOP_CMD_CTYP_MASK 0x00C00000
+#define SD4_EMMC_TOP_CMD_DPS_SHIFT 21
+#define SD4_EMMC_TOP_CMD_DPS_MASK 0x00200000
+#define SD4_EMMC_TOP_CMD_CCHK_EN_SHIFT 20
+#define SD4_EMMC_TOP_CMD_CCHK_EN_MASK 0x00100000
+#define SD4_EMMC_TOP_CMD_CRC_EN_SHIFT 19
+#define SD4_EMMC_TOP_CMD_CRC_EN_MASK 0x00080000
+#define SD4_EMMC_TOP_CMD_RTSEL_SHIFT 16
+#define SD4_EMMC_TOP_CMD_RTSEL_MASK 0x00030000
+#define SD4_EMMC_TOP_CMD_MSBS_SHIFT 5
+#define SD4_EMMC_TOP_CMD_MSBS_MASK 0x00000020
+#define SD4_EMMC_TOP_CMD_DTDS_SHIFT 4
+#define SD4_EMMC_TOP_CMD_DTDS_MASK 0x00000010
+#define SD4_EMMC_TOP_CMD_ACMDEN_SHIFT 2
+#define SD4_EMMC_TOP_CMD_ACMDEN_MASK 0x0000000C
+#define SD4_EMMC_TOP_CMD_BCEN_SHIFT 1
+#define SD4_EMMC_TOP_CMD_BCEN_MASK 0x00000002
+#define SD4_EMMC_TOP_CMD_DMA_SHIFT 0
+#define SD4_EMMC_TOP_CMD_DMA_MASK 0x00000001
+
+#define SD4_EMMC_TOP_CMD_SD4_OFFSET 0x0000000C
+#define SD4_EMMC_TOP_CMD_SD4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_CMD_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_CMD_SD4_RESERVED_MASK 0xC004FE00
+#define SD4_EMMC_TOP_CMD_SD4_CIDX_SHIFT 24
+#define SD4_EMMC_TOP_CMD_SD4_CIDX_MASK 0x3F000000
+#define SD4_EMMC_TOP_CMD_SD4_CTYP_SHIFT 22
+#define SD4_EMMC_TOP_CMD_SD4_CTYP_MASK 0x00C00000
+#define SD4_EMMC_TOP_CMD_SD4_DPS_SHIFT 21
+#define SD4_EMMC_TOP_CMD_SD4_DPS_MASK 0x00200000
+#define SD4_EMMC_TOP_CMD_SD4_CCHK_EN_SHIFT 20
+#define SD4_EMMC_TOP_CMD_SD4_CCHK_EN_MASK 0x00100000
+#define SD4_EMMC_TOP_CMD_SD4_CRC_EN_SHIFT 19
+#define SD4_EMMC_TOP_CMD_SD4_CRC_EN_MASK 0x00080000
+#define SD4_EMMC_TOP_CMD_SD4_RTSEL_SHIFT 16
+#define SD4_EMMC_TOP_CMD_SD4_RTSEL_MASK 0x00030000
+#define SD4_EMMC_TOP_CMD_SD4_RESPIRQDIS_SHIFT 8
+#define SD4_EMMC_TOP_CMD_SD4_RESPIRQDIS_MASK 0x00000100
+#define SD4_EMMC_TOP_CMD_SD4_RESPERRCHKEN_SHIFT 7
+#define SD4_EMMC_TOP_CMD_SD4_RESPERRCHKEN_MASK 0x00000080
+#define SD4_EMMC_TOP_CMD_SD4_RESPR1R5_SHIFT 6
+#define SD4_EMMC_TOP_CMD_SD4_RESPR1R5_MASK 0x00000040
+#define SD4_EMMC_TOP_CMD_SD4_MSBS_SHIFT 5
+#define SD4_EMMC_TOP_CMD_SD4_MSBS_MASK 0x00000020
+#define SD4_EMMC_TOP_CMD_SD4_DTDS_SHIFT 4
+#define SD4_EMMC_TOP_CMD_SD4_DTDS_MASK 0x00000010
+#define SD4_EMMC_TOP_CMD_SD4_ACMDEN_SHIFT 2
+#define SD4_EMMC_TOP_CMD_SD4_ACMDEN_MASK 0x0000000C
+#define SD4_EMMC_TOP_CMD_SD4_BCEN_SHIFT 1
+#define SD4_EMMC_TOP_CMD_SD4_BCEN_MASK 0x00000002
+#define SD4_EMMC_TOP_CMD_SD4_DMA_SHIFT 0
+#define SD4_EMMC_TOP_CMD_SD4_DMA_MASK 0x00000001
+
+#define SD4_EMMC_TOP_RESP0_OFFSET 0x00000010
+#define SD4_EMMC_TOP_RESP0_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_RESP0_TYPE uint32_t
+#define SD4_EMMC_TOP_RESP0_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_RESP0_RESP0_SHIFT 0
+#define SD4_EMMC_TOP_RESP0_RESP0_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_RESP2_OFFSET 0x00000014
+#define SD4_EMMC_TOP_RESP2_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_RESP2_TYPE uint32_t
+#define SD4_EMMC_TOP_RESP2_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_RESP2_RESP2_SHIFT 0
+#define SD4_EMMC_TOP_RESP2_RESP2_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_RESP4_OFFSET 0x00000018
+#define SD4_EMMC_TOP_RESP4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_RESP4_TYPE uint32_t
+#define SD4_EMMC_TOP_RESP4_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_RESP4_RESP4_SHIFT 0
+#define SD4_EMMC_TOP_RESP4_RESP4_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_RESP6_OFFSET 0x0000001C
+#define SD4_EMMC_TOP_RESP6_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_RESP6_TYPE uint32_t
+#define SD4_EMMC_TOP_RESP6_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_RESP6_RESP6_SHIFT 0
+#define SD4_EMMC_TOP_RESP6_RESP6_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_BUFDAT_OFFSET 0x00000020
+#define SD4_EMMC_TOP_BUFDAT_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_BUFDAT_TYPE uint32_t
+#define SD4_EMMC_TOP_BUFDAT_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_BUFDAT_BUFDAT_SHIFT 0
+#define SD4_EMMC_TOP_BUFDAT_BUFDAT_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_PSTATE_OFFSET 0x00000024
+#define SD4_EMMC_TOP_PSTATE_DEFAULT 0x1FFC0000
+#define SD4_EMMC_TOP_PSTATE_TYPE uint32_t
+#define SD4_EMMC_TOP_PSTATE_RESERVED_MASK 0xE000F0F0
+#define SD4_EMMC_TOP_PSTATE_DLS7_4_SHIFT 25
+#define SD4_EMMC_TOP_PSTATE_DLS7_4_MASK 0x1E000000
+#define SD4_EMMC_TOP_PSTATE_CLSL_SHIFT 24
+#define SD4_EMMC_TOP_PSTATE_CLSL_MASK 0x01000000
+#define SD4_EMMC_TOP_PSTATE_DLS3_0_SHIFT 20
+#define SD4_EMMC_TOP_PSTATE_DLS3_0_MASK 0x00F00000
+#define SD4_EMMC_TOP_PSTATE_WPSL_SHIFT 19
+#define SD4_EMMC_TOP_PSTATE_WPSL_MASK 0x00080000
+#define SD4_EMMC_TOP_PSTATE_CDPL_SHIFT 18
+#define SD4_EMMC_TOP_PSTATE_CDPL_MASK 0x00040000
+#define SD4_EMMC_TOP_PSTATE_CSS_SHIFT 17
+#define SD4_EMMC_TOP_PSTATE_CSS_MASK 0x00020000
+#define SD4_EMMC_TOP_PSTATE_CINS_SHIFT 16
+#define SD4_EMMC_TOP_PSTATE_CINS_MASK 0x00010000
+#define SD4_EMMC_TOP_PSTATE_BREN_SHIFT 11
+#define SD4_EMMC_TOP_PSTATE_BREN_MASK 0x00000800
+#define SD4_EMMC_TOP_PSTATE_BWEN_SHIFT 10
+#define SD4_EMMC_TOP_PSTATE_BWEN_MASK 0x00000400
+#define SD4_EMMC_TOP_PSTATE_RXACT_SHIFT 9
+#define SD4_EMMC_TOP_PSTATE_RXACT_MASK 0x00000200
+#define SD4_EMMC_TOP_PSTATE_WXACT_SHIFT 8
+#define SD4_EMMC_TOP_PSTATE_WXACT_MASK 0x00000100
+#define SD4_EMMC_TOP_PSTATE_RETUNE_REQ_SHIFT 3
+#define SD4_EMMC_TOP_PSTATE_RETUNE_REQ_MASK 0x00000008
+#define SD4_EMMC_TOP_PSTATE_DATACT_SHIFT 2
+#define SD4_EMMC_TOP_PSTATE_DATACT_MASK 0x00000004
+#define SD4_EMMC_TOP_PSTATE_DATINH_SHIFT 1
+#define SD4_EMMC_TOP_PSTATE_DATINH_MASK 0x00000002
+#define SD4_EMMC_TOP_PSTATE_CMDINH_SHIFT 0
+#define SD4_EMMC_TOP_PSTATE_CMDINH_MASK 0x00000001
+
+#define SD4_EMMC_TOP_PSTATE_SD4_OFFSET 0x00000024
+#define SD4_EMMC_TOP_PSTATE_SD4_DEFAULT 0x01FC00F0
+#define SD4_EMMC_TOP_PSTATE_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_PSTATE_SD4_RESERVED_MASK 0x1E00F000
+#define SD4_EMMC_TOP_PSTATE_SD4_STBLDET_SHIFT 31
+#define SD4_EMMC_TOP_PSTATE_SD4_STBLDET_MASK 0x80000000
+#define SD4_EMMC_TOP_PSTATE_SD4_LANESYNC_SHIFT 30
+#define SD4_EMMC_TOP_PSTATE_SD4_LANESYNC_MASK 0x40000000
+#define SD4_EMMC_TOP_PSTATE_SD4_INDORMNTSTATE_SHIFT 29
+#define SD4_EMMC_TOP_PSTATE_SD4_INDORMNTSTATE_MASK 0x20000000
+#define SD4_EMMC_TOP_PSTATE_SD4_CLSL_SHIFT 24
+#define SD4_EMMC_TOP_PSTATE_SD4_CLSL_MASK 0x01000000
+#define SD4_EMMC_TOP_PSTATE_SD4_DLS3_0_SHIFT 20
+#define SD4_EMMC_TOP_PSTATE_SD4_DLS3_0_MASK 0x00F00000
+#define SD4_EMMC_TOP_PSTATE_SD4_WPSL_SHIFT 19
+#define SD4_EMMC_TOP_PSTATE_SD4_WPSL_MASK 0x00080000
+#define SD4_EMMC_TOP_PSTATE_SD4_CDPL_SHIFT 18
+#define SD4_EMMC_TOP_PSTATE_SD4_CDPL_MASK 0x00040000
+#define SD4_EMMC_TOP_PSTATE_SD4_CSS_SHIFT 17
+#define SD4_EMMC_TOP_PSTATE_SD4_CSS_MASK 0x00020000
+#define SD4_EMMC_TOP_PSTATE_SD4_CINS_SHIFT 16
+#define SD4_EMMC_TOP_PSTATE_SD4_CINS_MASK 0x00010000
+#define SD4_EMMC_TOP_PSTATE_SD4_BREN_SHIFT 11
+#define SD4_EMMC_TOP_PSTATE_SD4_BREN_MASK 0x00000800
+#define SD4_EMMC_TOP_PSTATE_SD4_BWEN_SHIFT 10
+#define SD4_EMMC_TOP_PSTATE_SD4_BWEN_MASK 0x00000400
+#define SD4_EMMC_TOP_PSTATE_SD4_RXACT_SHIFT 9
+#define SD4_EMMC_TOP_PSTATE_SD4_RXACT_MASK 0x00000200
+#define SD4_EMMC_TOP_PSTATE_SD4_WXACT_SHIFT 8
+#define SD4_EMMC_TOP_PSTATE_SD4_WXACT_MASK 0x00000100
+#define SD4_EMMC_TOP_PSTATE_SD4_DLS7_4_SHIFT 4
+#define SD4_EMMC_TOP_PSTATE_SD4_DLS7_4_MASK 0x000000F0
+#define SD4_EMMC_TOP_PSTATE_SD4_RETUNE_REQ_SHIFT 3
+#define SD4_EMMC_TOP_PSTATE_SD4_RETUNE_REQ_MASK 0x00000008
+#define SD4_EMMC_TOP_PSTATE_SD4_DATACT_SHIFT 2
+#define SD4_EMMC_TOP_PSTATE_SD4_DATACT_MASK 0x00000004
+#define SD4_EMMC_TOP_PSTATE_SD4_DATINH_SHIFT 1
+#define SD4_EMMC_TOP_PSTATE_SD4_DATINH_MASK 0x00000002
+#define SD4_EMMC_TOP_PSTATE_SD4_CMDINH_SHIFT 0
+#define SD4_EMMC_TOP_PSTATE_SD4_CMDINH_MASK 0x00000001
+
+#define SD4_EMMC_TOP_CTRL_OFFSET 0x00000028
+#define SD4_EMMC_TOP_CTRL_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_CTRL_TYPE uint32_t
+#define SD4_EMMC_TOP_CTRL_RESERVED_MASK 0xF800E000
+#define SD4_EMMC_TOP_CTRL_WAKENRMV_SHIFT 26
+#define SD4_EMMC_TOP_CTRL_WAKENRMV_MASK 0x04000000
+#define SD4_EMMC_TOP_CTRL_WAKENINS_SHIFT 25
+#define SD4_EMMC_TOP_CTRL_WAKENINS_MASK 0x02000000
+#define SD4_EMMC_TOP_CTRL_WAKENIRQ_SHIFT 24
+#define SD4_EMMC_TOP_CTRL_WAKENIRQ_MASK 0x01000000
+#define SD4_EMMC_TOP_CTRL_BOOTACK_SHIFT 23
+#define SD4_EMMC_TOP_CTRL_BOOTACK_MASK 0x00800000
+#define SD4_EMMC_TOP_CTRL_ATLBOOTEN_SHIFT 22
+#define SD4_EMMC_TOP_CTRL_ATLBOOTEN_MASK 0x00400000
+#define SD4_EMMC_TOP_CTRL_BOOTEN_SHIFT 21
+#define SD4_EMMC_TOP_CTRL_BOOTEN_MASK 0x00200000
+#define SD4_EMMC_TOP_CTRL_SPIMODE_SHIFT 20
+#define SD4_EMMC_TOP_CTRL_SPIMODE_MASK 0x00100000
+#define SD4_EMMC_TOP_CTRL_BLKIRQ_SHIFT 19
+#define SD4_EMMC_TOP_CTRL_BLKIRQ_MASK 0x00080000
+#define SD4_EMMC_TOP_CTRL_RDWTCRTL_SHIFT 18
+#define SD4_EMMC_TOP_CTRL_RDWTCRTL_MASK 0x00040000
+#define SD4_EMMC_TOP_CTRL_CONTREQ_SHIFT 17
+#define SD4_EMMC_TOP_CTRL_CONTREQ_MASK 0x00020000
+#define SD4_EMMC_TOP_CTRL_BLKSTPREQ_SHIFT 16
+#define SD4_EMMC_TOP_CTRL_BLKSTPREQ_MASK 0x00010000
+#define SD4_EMMC_TOP_CTRL_HRESET_SHIFT 12
+#define SD4_EMMC_TOP_CTRL_HRESET_MASK 0x00001000
+#define SD4_EMMC_TOP_CTRL_SDVSELVDD1_SHIFT 9
+#define SD4_EMMC_TOP_CTRL_SDVSELVDD1_MASK 0x00000E00
+#define SD4_EMMC_TOP_CTRL_SDPWR_SHIFT 8
+#define SD4_EMMC_TOP_CTRL_SDPWR_MASK 0x00000100
+#define SD4_EMMC_TOP_CTRL_CDSD_SHIFT 7
+#define SD4_EMMC_TOP_CTRL_CDSD_MASK 0x00000080
+#define SD4_EMMC_TOP_CTRL_CDTL_SHIFT 6
+#define SD4_EMMC_TOP_CTRL_CDTL_MASK 0x00000040
+#define SD4_EMMC_TOP_CTRL_SDB_SHIFT 5
+#define SD4_EMMC_TOP_CTRL_SDB_MASK 0x00000020
+#define SD4_EMMC_TOP_CTRL_DMASEL_SHIFT 3
+#define SD4_EMMC_TOP_CTRL_DMASEL_MASK 0x00000018
+#define SD4_EMMC_TOP_CTRL_HSEN_SHIFT 2
+#define SD4_EMMC_TOP_CTRL_HSEN_MASK 0x00000004
+#define SD4_EMMC_TOP_CTRL_DXTW_SHIFT 1
+#define SD4_EMMC_TOP_CTRL_DXTW_MASK 0x00000002
+#define SD4_EMMC_TOP_CTRL_LEDCTL_SHIFT 0
+#define SD4_EMMC_TOP_CTRL_LEDCTL_MASK 0x00000001
+
+#define SD4_EMMC_TOP_CTRL_SD4_OFFSET 0x00000028
+#define SD4_EMMC_TOP_CTRL_SD4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_CTRL_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_CTRL_SD4_RESERVED_MASK 0xF8F00000
+#define SD4_EMMC_TOP_CTRL_SD4_WAKENRMV_SHIFT 26
+#define SD4_EMMC_TOP_CTRL_SD4_WAKENRMV_MASK 0x04000000
+#define SD4_EMMC_TOP_CTRL_SD4_WAKENINS_SHIFT 25
+#define SD4_EMMC_TOP_CTRL_SD4_WAKENINS_MASK 0x02000000
+#define SD4_EMMC_TOP_CTRL_SD4_WAKENIRQ_SHIFT 24
+#define SD4_EMMC_TOP_CTRL_SD4_WAKENIRQ_MASK 0x01000000
+#define SD4_EMMC_TOP_CTRL_SD4_BLKIRQ_SHIFT 19
+#define SD4_EMMC_TOP_CTRL_SD4_BLKIRQ_MASK 0x00080000
+#define SD4_EMMC_TOP_CTRL_SD4_RDWTCRTL_SHIFT 18
+#define SD4_EMMC_TOP_CTRL_SD4_RDWTCRTL_MASK 0x00040000
+#define SD4_EMMC_TOP_CTRL_SD4_CONTREQ_SHIFT 17
+#define SD4_EMMC_TOP_CTRL_SD4_CONTREQ_MASK 0x00020000
+#define SD4_EMMC_TOP_CTRL_SD4_BLKSTPREQ_SHIFT 16
+#define SD4_EMMC_TOP_CTRL_SD4_BLKSTPREQ_MASK 0x00010000
+#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD2_SHIFT 13
+#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD2_MASK 0x0000E000
+#define SD4_EMMC_TOP_CTRL_SD4_SDPWRVDD2_SHIFT 12
+#define SD4_EMMC_TOP_CTRL_SD4_SDPWRVDD2_MASK 0x00001000
+#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD1_SHIFT 9
+#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD1_MASK 0x00000E00
+#define SD4_EMMC_TOP_CTRL_SD4_SDPWR_SHIFT 8
+#define SD4_EMMC_TOP_CTRL_SD4_SDPWR_MASK 0x00000100
+#define SD4_EMMC_TOP_CTRL_SD4_CDSD_SHIFT 7
+#define SD4_EMMC_TOP_CTRL_SD4_CDSD_MASK 0x00000080
+#define SD4_EMMC_TOP_CTRL_SD4_CDTL_SHIFT 6
+#define SD4_EMMC_TOP_CTRL_SD4_CDTL_MASK 0x00000040
+#define SD4_EMMC_TOP_CTRL_SD4_SDB_SHIFT 5
+#define SD4_EMMC_TOP_CTRL_SD4_SDB_MASK 0x00000020
+#define SD4_EMMC_TOP_CTRL_SD4_DMASEL_SHIFT 3
+#define SD4_EMMC_TOP_CTRL_SD4_DMASEL_MASK 0x00000018
+#define SD4_EMMC_TOP_CTRL_SD4_HSEN_SHIFT 2
+#define SD4_EMMC_TOP_CTRL_SD4_HSEN_MASK 0x00000004
+#define SD4_EMMC_TOP_CTRL_SD4_DXTW_SHIFT 1
+#define SD4_EMMC_TOP_CTRL_SD4_DXTW_MASK 0x00000002
+#define SD4_EMMC_TOP_CTRL_SD4_LEDCTL_SHIFT 0
+#define SD4_EMMC_TOP_CTRL_SD4_LEDCTL_MASK 0x00000001
+
+#define SD4_EMMC_TOP_CTRL1_OFFSET 0x0000002C
+#define SD4_EMMC_TOP_CTRL1_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_CTRL1_TYPE uint32_t
+#define SD4_EMMC_TOP_CTRL1_RESERVED_MASK 0xF8F00018
+#define SD4_EMMC_TOP_CTRL1_DATRST_SHIFT 26
+#define SD4_EMMC_TOP_CTRL1_DATRST_MASK 0x04000000
+#define SD4_EMMC_TOP_CTRL1_CMDRST_SHIFT 25
+#define SD4_EMMC_TOP_CTRL1_CMDRST_MASK 0x02000000
+#define SD4_EMMC_TOP_CTRL1_RST_SHIFT 24
+#define SD4_EMMC_TOP_CTRL1_RST_MASK 0x01000000
+#define SD4_EMMC_TOP_CTRL1_DTCNT_SHIFT 16
+#define SD4_EMMC_TOP_CTRL1_DTCNT_MASK 0x000F0000
+#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_SHIFT 8
+#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_MASK 0x0000FF00
+#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_SHIFT 6
+#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_MASK 0x000000C0
+#define SD4_EMMC_TOP_CTRL1_CLKGENSEL_SHIFT 5
+#define SD4_EMMC_TOP_CTRL1_CLKGENSEL_MASK 0x00000020
+#define SD4_EMMC_TOP_CTRL1_SDCLKEN_SHIFT 2
+#define SD4_EMMC_TOP_CTRL1_SDCLKEN_MASK 0x00000004
+#define SD4_EMMC_TOP_CTRL1_ICLKSTB_SHIFT 1
+#define SD4_EMMC_TOP_CTRL1_ICLKSTB_MASK 0x00000002
+#define SD4_EMMC_TOP_CTRL1_ICLKEN_SHIFT 0
+#define SD4_EMMC_TOP_CTRL1_ICLKEN_MASK 0x00000001
+
+#define SD4_EMMC_TOP_INTR_OFFSET 0x00000030
+#define SD4_EMMC_TOP_INTR_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_INTR_TYPE uint32_t
+#define SD4_EMMC_TOP_INTR_RESERVED_MASK 0xEC000000
+#define SD4_EMMC_TOP_INTR_TRESPERR_SHIFT 28
+#define SD4_EMMC_TOP_INTR_TRESPERR_MASK 0x10000000
+#define SD4_EMMC_TOP_INTR_ADMAERR_SHIFT 25
+#define SD4_EMMC_TOP_INTR_ADMAERR_MASK 0x02000000
+#define SD4_EMMC_TOP_INTR_CMDERROR_SHIFT 24
+#define SD4_EMMC_TOP_INTR_CMDERROR_MASK 0x01000000
+#define SD4_EMMC_TOP_INTR_IERR_SHIFT 23
+#define SD4_EMMC_TOP_INTR_IERR_MASK 0x00800000
+#define SD4_EMMC_TOP_INTR_DEBERR_SHIFT 22
+#define SD4_EMMC_TOP_INTR_DEBERR_MASK 0x00400000
+#define SD4_EMMC_TOP_INTR_DCRCERR_SHIFT 21
+#define SD4_EMMC_TOP_INTR_DCRCERR_MASK 0x00200000
+#define SD4_EMMC_TOP_INTR_DTOERR_SHIFT 20
+#define SD4_EMMC_TOP_INTR_DTOERR_MASK 0x00100000
+#define SD4_EMMC_TOP_INTR_CMDIDXERR_SHIFT 19
+#define SD4_EMMC_TOP_INTR_CMDIDXERR_MASK 0x00080000
+#define SD4_EMMC_TOP_INTR_CEBERR_SHIFT 18
+#define SD4_EMMC_TOP_INTR_CEBERR_MASK 0x00040000
+#define SD4_EMMC_TOP_INTR_CCRCERR_SHIFT 17
+#define SD4_EMMC_TOP_INTR_CCRCERR_MASK 0x00020000
+#define SD4_EMMC_TOP_INTR_CTOERR_SHIFT 16
+#define SD4_EMMC_TOP_INTR_CTOERR_MASK 0x00010000
+#define SD4_EMMC_TOP_INTR_ERRIRQ_SHIFT 15
+#define SD4_EMMC_TOP_INTR_ERRIRQ_MASK 0x00008000
+#define SD4_EMMC_TOP_INTR_BTIRQ_SHIFT 14
+#define SD4_EMMC_TOP_INTR_BTIRQ_MASK 0x00004000
+#define SD4_EMMC_TOP_INTR_BTACKRX_SHIFT 13
+#define SD4_EMMC_TOP_INTR_BTACKRX_MASK 0x00002000
+#define SD4_EMMC_TOP_INTR_RETUNE_EVENT_SHIFT 12
+#define SD4_EMMC_TOP_INTR_RETUNE_EVENT_MASK 0x00001000
+#define SD4_EMMC_TOP_INTR_INT_C_SHIFT 11
+#define SD4_EMMC_TOP_INTR_INT_C_MASK 0x00000800
+#define SD4_EMMC_TOP_INTR_INT_B_SHIFT 10
+#define SD4_EMMC_TOP_INTR_INT_B_MASK 0x00000400
+#define SD4_EMMC_TOP_INTR_INT_A_SHIFT 9
+#define SD4_EMMC_TOP_INTR_INT_A_MASK 0x00000200
+#define SD4_EMMC_TOP_INTR_CRDIRQ_SHIFT 8
+#define SD4_EMMC_TOP_INTR_CRDIRQ_MASK 0x00000100
+#define SD4_EMMC_TOP_INTR_CRDRMV_SHIFT 7
+#define SD4_EMMC_TOP_INTR_CRDRMV_MASK 0x00000080
+#define SD4_EMMC_TOP_INTR_CRDINS_SHIFT 6
+#define SD4_EMMC_TOP_INTR_CRDINS_MASK 0x00000040
+#define SD4_EMMC_TOP_INTR_BRRDY_SHIFT 5
+#define SD4_EMMC_TOP_INTR_BRRDY_MASK 0x00000020
+#define SD4_EMMC_TOP_INTR_BWRDY_SHIFT 4
+#define SD4_EMMC_TOP_INTR_BWRDY_MASK 0x00000010
+#define SD4_EMMC_TOP_INTR_DMAIRQ_SHIFT 3
+#define SD4_EMMC_TOP_INTR_DMAIRQ_MASK 0x00000008
+#define SD4_EMMC_TOP_INTR_BLKENT_SHIFT 2
+#define SD4_EMMC_TOP_INTR_BLKENT_MASK 0x00000004
+#define SD4_EMMC_TOP_INTR_TXDONE_SHIFT 1
+#define SD4_EMMC_TOP_INTR_TXDONE_MASK 0x00000002
+#define SD4_EMMC_TOP_INTR_CMDDONE_SHIFT 0
+#define SD4_EMMC_TOP_INTR_CMDDONE_MASK 0x00000001
+
+#define SD4_EMMC_TOP_INTR_SD4_OFFSET 0x00000030
+#define SD4_EMMC_TOP_INTR_SD4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_INTR_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_INTR_SD4_RESERVED_MASK 0xF0006000
+#define SD4_EMMC_TOP_INTR_SD4_TRESPERR_SHIFT 27
+#define SD4_EMMC_TOP_INTR_SD4_TRESPERR_MASK 0x08000000
+#define SD4_EMMC_TOP_INTR_SD4_TUNEERR_SHIFT 26
+#define SD4_EMMC_TOP_INTR_SD4_TUNEERR_MASK 0x04000000
+#define SD4_EMMC_TOP_INTR_SD4_ADMAERR_SHIFT 25
+#define SD4_EMMC_TOP_INTR_SD4_ADMAERR_MASK 0x02000000
+#define SD4_EMMC_TOP_INTR_SD4_CMDERROR_SHIFT 24
+#define SD4_EMMC_TOP_INTR_SD4_CMDERROR_MASK 0x01000000
+#define SD4_EMMC_TOP_INTR_SD4_IERR_SHIFT 23
+#define SD4_EMMC_TOP_INTR_SD4_IERR_MASK 0x00800000
+#define SD4_EMMC_TOP_INTR_SD4_DEBERR_SHIFT 22
+#define SD4_EMMC_TOP_INTR_SD4_DEBERR_MASK 0x00400000
+#define SD4_EMMC_TOP_INTR_SD4_DCRCERR_SHIFT 21
+#define SD4_EMMC_TOP_INTR_SD4_DCRCERR_MASK 0x00200000
+#define SD4_EMMC_TOP_INTR_SD4_DTOERR_SHIFT 20
+#define SD4_EMMC_TOP_INTR_SD4_DTOERR_MASK 0x00100000
+#define SD4_EMMC_TOP_INTR_SD4_CMDIDXERR_SHIFT 19
+#define SD4_EMMC_TOP_INTR_SD4_CMDIDXERR_MASK 0x00080000
+#define SD4_EMMC_TOP_INTR_SD4_CEBERR_SHIFT 18
+#define SD4_EMMC_TOP_INTR_SD4_CEBERR_MASK 0x00040000
+#define SD4_EMMC_TOP_INTR_SD4_CCRCERR_SHIFT 17
+#define SD4_EMMC_TOP_INTR_SD4_CCRCERR_MASK 0x00020000
+#define SD4_EMMC_TOP_INTR_SD4_CTOERR_SHIFT 16
+#define SD4_EMMC_TOP_INTR_SD4_CTOERR_MASK 0x00010000
+#define SD4_EMMC_TOP_INTR_SD4_ERRIRQ_SHIFT 15
+#define SD4_EMMC_TOP_INTR_SD4_ERRIRQ_MASK 0x00008000
+#define SD4_EMMC_TOP_INTR_SD4_RETUNE_EVENT_SHIFT 12
+#define SD4_EMMC_TOP_INTR_SD4_RETUNE_EVENT_MASK 0x00001000
+#define SD4_EMMC_TOP_INTR_SD4_INT_C_SHIFT 11
+#define SD4_EMMC_TOP_INTR_SD4_INT_C_MASK 0x00000800
+#define SD4_EMMC_TOP_INTR_SD4_INT_B_SHIFT 10
+#define SD4_EMMC_TOP_INTR_SD4_INT_B_MASK 0x00000400
+#define SD4_EMMC_TOP_INTR_SD4_INT_A_SHIFT 9
+#define SD4_EMMC_TOP_INTR_SD4_INT_A_MASK 0x00000200
+#define SD4_EMMC_TOP_INTR_SD4_CRDIRQ_SHIFT 8
+#define SD4_EMMC_TOP_INTR_SD4_CRDIRQ_MASK 0x00000100
+#define SD4_EMMC_TOP_INTR_SD4_CRDRMV_SHIFT 7
+#define SD4_EMMC_TOP_INTR_SD4_CRDRMV_MASK 0x00000080
+#define SD4_EMMC_TOP_INTR_SD4_CRDINS_SHIFT 6
+#define SD4_EMMC_TOP_INTR_SD4_CRDINS_MASK 0x00000040
+#define SD4_EMMC_TOP_INTR_SD4_BRRDY_SHIFT 5
+#define SD4_EMMC_TOP_INTR_SD4_BRRDY_MASK 0x00000020
+#define SD4_EMMC_TOP_INTR_SD4_BWRDY_SHIFT 4
+#define SD4_EMMC_TOP_INTR_SD4_BWRDY_MASK 0x00000010
+#define SD4_EMMC_TOP_INTR_SD4_DMAIRQ_SHIFT 3
+#define SD4_EMMC_TOP_INTR_SD4_DMAIRQ_MASK 0x00000008
+#define SD4_EMMC_TOP_INTR_SD4_BLKENT_SHIFT 2
+#define SD4_EMMC_TOP_INTR_SD4_BLKENT_MASK 0x00000004
+#define SD4_EMMC_TOP_INTR_SD4_TXDONE_SHIFT 1
+#define SD4_EMMC_TOP_INTR_SD4_TXDONE_MASK 0x00000002
+#define SD4_EMMC_TOP_INTR_SD4_CMDDONE_SHIFT 0
+#define SD4_EMMC_TOP_INTR_SD4_CMDDONE_MASK 0x00000001
+
+#define SD4_EMMC_TOP_INTREN1_OFFSET 0x00000034
+#define SD4_EMMC_TOP_INTREN1_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_INTREN1_TYPE uint32_t
+#define SD4_EMMC_TOP_INTREN1_RESERVED_MASK 0xEC000000
+#define SD4_EMMC_TOP_INTREN1_TRESPERREN_SHIFT 28
+#define SD4_EMMC_TOP_INTREN1_TRESPERREN_MASK 0x10000000
+#define SD4_EMMC_TOP_INTREN1_ADMAEREN_SHIFT 25
+#define SD4_EMMC_TOP_INTREN1_ADMAEREN_MASK 0x02000000
+#define SD4_EMMC_TOP_INTREN1_CMDERREN_SHIFT 24
+#define SD4_EMMC_TOP_INTREN1_CMDERREN_MASK 0x01000000
+#define SD4_EMMC_TOP_INTREN1_ILIMERREN_SHIFT 23
+#define SD4_EMMC_TOP_INTREN1_ILIMERREN_MASK 0x00800000
+#define SD4_EMMC_TOP_INTREN1_DEBERREN_SHIFT 22
+#define SD4_EMMC_TOP_INTREN1_DEBERREN_MASK 0x00400000
+#define SD4_EMMC_TOP_INTREN1_DCRCERREN_SHIFT 21
+#define SD4_EMMC_TOP_INTREN1_DCRCERREN_MASK 0x00200000
+#define SD4_EMMC_TOP_INTREN1_DTOERREN_SHIFT 20
+#define SD4_EMMC_TOP_INTREN1_DTOERREN_MASK 0x00100000
+#define SD4_EMMC_TOP_INTREN1_CIDXERREN_SHIFT 19
+#define SD4_EMMC_TOP_INTREN1_CIDXERREN_MASK 0x00080000
+#define SD4_EMMC_TOP_INTREN1_CEBERREN_SHIFT 18
+#define SD4_EMMC_TOP_INTREN1_CEBERREN_MASK 0x00040000
+#define SD4_EMMC_TOP_INTREN1_CMDCRCEN_SHIFT 17
+#define SD4_EMMC_TOP_INTREN1_CMDCRCEN_MASK 0x00020000
+#define SD4_EMMC_TOP_INTREN1_CMDTOEN_SHIFT 16
+#define SD4_EMMC_TOP_INTREN1_CMDTOEN_MASK 0x00010000
+#define SD4_EMMC_TOP_INTREN1_FIXZ_SHIFT 15
+#define SD4_EMMC_TOP_INTREN1_FIXZ_MASK 0x00008000
+#define SD4_EMMC_TOP_INTREN1_BTIRQEN_SHIFT 14
+#define SD4_EMMC_TOP_INTREN1_BTIRQEN_MASK 0x00004000
+#define SD4_EMMC_TOP_INTREN1_BTACKRXEN_SHIFT 13
+#define SD4_EMMC_TOP_INTREN1_BTACKRXEN_MASK 0x00002000
+#define SD4_EMMC_TOP_INTREN1_RETUNE_EVENTEN_SHIFT 12
+#define SD4_EMMC_TOP_INTREN1_RETUNE_EVENTEN_MASK 0x00001000
+#define SD4_EMMC_TOP_INTREN1_INT_C_EN_SHIFT 11
+#define SD4_EMMC_TOP_INTREN1_INT_C_EN_MASK 0x00000800
+#define SD4_EMMC_TOP_INTREN1_INT_B_EN_SHIFT 10
+#define SD4_EMMC_TOP_INTREN1_INT_B_EN_MASK 0x00000400
+#define SD4_EMMC_TOP_INTREN1_INT_A_EN_SHIFT 9
+#define SD4_EMMC_TOP_INTREN1_INT_A_EN_MASK 0x00000200
+#define SD4_EMMC_TOP_INTREN1_CIRQEN_SHIFT 8
+#define SD4_EMMC_TOP_INTREN1_CIRQEN_MASK 0x00000100
+#define SD4_EMMC_TOP_INTREN1_CRDRMVEN_SHIFT 7
+#define SD4_EMMC_TOP_INTREN1_CRDRMVEN_MASK 0x00000080
+#define SD4_EMMC_TOP_INTREN1_CRDINSEN_SHIFT 6
+#define SD4_EMMC_TOP_INTREN1_CRDINSEN_MASK 0x00000040
+#define SD4_EMMC_TOP_INTREN1_BUFRREN_SHIFT 5
+#define SD4_EMMC_TOP_INTREN1_BUFRREN_MASK 0x00000020
+#define SD4_EMMC_TOP_INTREN1_BUFWREN_SHIFT 4
+#define SD4_EMMC_TOP_INTREN1_BUFWREN_MASK 0x00000010
+#define SD4_EMMC_TOP_INTREN1_DMAIRQEN_SHIFT 3
+#define SD4_EMMC_TOP_INTREN1_DMAIRQEN_MASK 0x00000008
+#define SD4_EMMC_TOP_INTREN1_BLKEN_SHIFT 2
+#define SD4_EMMC_TOP_INTREN1_BLKEN_MASK 0x00000004
+#define SD4_EMMC_TOP_INTREN1_TXDONEEN_SHIFT 1
+#define SD4_EMMC_TOP_INTREN1_TXDONEEN_MASK 0x00000002
+#define SD4_EMMC_TOP_INTREN1_CMDDONEEN_SHIFT 0
+#define SD4_EMMC_TOP_INTREN1_CMDDONEEN_MASK 0x00000001
+
+#define SD4_EMMC_TOP_INTREN1_SD4_OFFSET 0x00000034
+#define SD4_EMMC_TOP_INTREN1_SD4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_INTREN1_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_INTREN1_SD4_RESERVED_MASK 0x00006000
+#define SD4_EMMC_TOP_INTREN1_SD4_VNDRERREN_SHIFT 28
+#define SD4_EMMC_TOP_INTREN1_SD4_VNDRERREN_MASK 0xF0000000
+#define SD4_EMMC_TOP_INTREN1_SD4_TRESPERREN_SHIFT 27
+#define SD4_EMMC_TOP_INTREN1_SD4_TRESPERREN_MASK 0x08000000
+#define SD4_EMMC_TOP_INTREN1_SD4_TUNEERREN_SHIFT 26
+#define SD4_EMMC_TOP_INTREN1_SD4_TUNEERREN_MASK 0x04000000
+#define SD4_EMMC_TOP_INTREN1_SD4_ADMAEREN_SHIFT 25
+#define SD4_EMMC_TOP_INTREN1_SD4_ADMAEREN_MASK 0x02000000
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDERREN_SHIFT 24
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDERREN_MASK 0x01000000
+#define SD4_EMMC_TOP_INTREN1_SD4_ILIMERREN_SHIFT 23
+#define SD4_EMMC_TOP_INTREN1_SD4_ILIMERREN_MASK 0x00800000
+#define SD4_EMMC_TOP_INTREN1_SD4_DEBERREN_SHIFT 22
+#define SD4_EMMC_TOP_INTREN1_SD4_DEBERREN_MASK 0x00400000
+#define SD4_EMMC_TOP_INTREN1_SD4_DCRCERREN_SHIFT 21
+#define SD4_EMMC_TOP_INTREN1_SD4_DCRCERREN_MASK 0x00200000
+#define SD4_EMMC_TOP_INTREN1_SD4_DTOERREN_SHIFT 20
+#define SD4_EMMC_TOP_INTREN1_SD4_DTOERREN_MASK 0x00100000
+#define SD4_EMMC_TOP_INTREN1_SD4_CIDXERREN_SHIFT 19
+#define SD4_EMMC_TOP_INTREN1_SD4_CIDXERREN_MASK 0x00080000
+#define SD4_EMMC_TOP_INTREN1_SD4_CEBERREN_SHIFT 18
+#define SD4_EMMC_TOP_INTREN1_SD4_CEBERREN_MASK 0x00040000
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDCRCEN_SHIFT 17
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDCRCEN_MASK 0x00020000
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDTOEN_SHIFT 16
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDTOEN_MASK 0x00010000
+#define SD4_EMMC_TOP_INTREN1_SD4_FIXZ_SHIFT 15
+#define SD4_EMMC_TOP_INTREN1_SD4_FIXZ_MASK 0x00008000
+#define SD4_EMMC_TOP_INTREN1_SD4_RETUNE_EVENTEN_SHIFT 12
+#define SD4_EMMC_TOP_INTREN1_SD4_RETUNE_EVENTEN_MASK 0x00001000
+#define SD4_EMMC_TOP_INTREN1_SD4_INT_C_EN_SHIFT 11
+#define SD4_EMMC_TOP_INTREN1_SD4_INT_C_EN_MASK 0x00000800
+#define SD4_EMMC_TOP_INTREN1_SD4_INT_B_EN_SHIFT 10
+#define SD4_EMMC_TOP_INTREN1_SD4_INT_B_EN_MASK 0x00000400
+#define SD4_EMMC_TOP_INTREN1_SD4_INT_A_EN_SHIFT 9
+#define SD4_EMMC_TOP_INTREN1_SD4_INT_A_EN_MASK 0x00000200
+#define SD4_EMMC_TOP_INTREN1_SD4_CIRQEN_SHIFT 8
+#define SD4_EMMC_TOP_INTREN1_SD4_CIRQEN_MASK 0x00000100
+#define SD4_EMMC_TOP_INTREN1_SD4_CRDRMVEN_SHIFT 7
+#define SD4_EMMC_TOP_INTREN1_SD4_CRDRMVEN_MASK 0x00000080
+#define SD4_EMMC_TOP_INTREN1_SD4_CRDINSEN_SHIFT 6
+#define SD4_EMMC_TOP_INTREN1_SD4_CRDINSEN_MASK 0x00000040
+#define SD4_EMMC_TOP_INTREN1_SD4_BUFRREN_SHIFT 5
+#define SD4_EMMC_TOP_INTREN1_SD4_BUFRREN_MASK 0x00000020
+#define SD4_EMMC_TOP_INTREN1_SD4_BUFWREN_SHIFT 4
+#define SD4_EMMC_TOP_INTREN1_SD4_BUFWREN_MASK 0x00000010
+#define SD4_EMMC_TOP_INTREN1_SD4_DMAIRQEN_SHIFT 3
+#define SD4_EMMC_TOP_INTREN1_SD4_DMAIRQEN_MASK 0x00000008
+#define SD4_EMMC_TOP_INTREN1_SD4_BLKEN_SHIFT 2
+#define SD4_EMMC_TOP_INTREN1_SD4_BLKEN_MASK 0x00000004
+#define SD4_EMMC_TOP_INTREN1_SD4_TXDONEEN_SHIFT 1
+#define SD4_EMMC_TOP_INTREN1_SD4_TXDONEEN_MASK 0x00000002
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDDONEEN_SHIFT 0
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDDONEEN_MASK 0x00000001
+
+#define SD4_EMMC_TOP_INTREN2_OFFSET 0x00000038
+#define SD4_EMMC_TOP_INTREN2_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_INTREN2_TYPE uint32_t
+#define SD4_EMMC_TOP_INTREN2_RESERVED_MASK 0xEC000000
+#define SD4_EMMC_TOP_INTREN2_TRESPERRSEN_SHIFT 28
+#define SD4_EMMC_TOP_INTREN2_TRESPERRSEN_MASK 0x10000000
+#define SD4_EMMC_TOP_INTREN2_ADMASIGEN_SHIFT 25
+#define SD4_EMMC_TOP_INTREN2_ADMASIGEN_MASK 0x02000000
+#define SD4_EMMC_TOP_INTREN2_CMDSIGEN_SHIFT 24
+#define SD4_EMMC_TOP_INTREN2_CMDSIGEN_MASK 0x01000000
+#define SD4_EMMC_TOP_INTREN2_ILIMSIGEN_SHIFT 23
+#define SD4_EMMC_TOP_INTREN2_ILIMSIGEN_MASK 0x00800000
+#define SD4_EMMC_TOP_INTREN2_DEBSIGEN_SHIFT 22
+#define SD4_EMMC_TOP_INTREN2_DEBSIGEN_MASK 0x00400000
+#define SD4_EMMC_TOP_INTREN2_DCRCSIGEN_SHIFT 21
+#define SD4_EMMC_TOP_INTREN2_DCRCSIGEN_MASK 0x00200000
+#define SD4_EMMC_TOP_INTREN2_DTOSIGEN_SHIFT 20
+#define SD4_EMMC_TOP_INTREN2_DTOSIGEN_MASK 0x00100000
+#define SD4_EMMC_TOP_INTREN2_CIDXSIGEN_SHIFT 19
+#define SD4_EMMC_TOP_INTREN2_CIDXSIGEN_MASK 0x00080000
+#define SD4_EMMC_TOP_INTREN2_CEBSIGEN_SHIFT 18
+#define SD4_EMMC_TOP_INTREN2_CEBSIGEN_MASK 0x00040000
+#define SD4_EMMC_TOP_INTREN2_CMDCRCSIGEN_SHIFT 17
+#define SD4_EMMC_TOP_INTREN2_CMDCRCSIGEN_MASK 0x00020000
+#define SD4_EMMC_TOP_INTREN2_CMDTOSIGEN_SHIFT 16
+#define SD4_EMMC_TOP_INTREN2_CMDTOSIGEN_MASK 0x00010000
+#define SD4_EMMC_TOP_INTREN2_FIXZERO_SHIFT 15
+#define SD4_EMMC_TOP_INTREN2_FIXZERO_MASK 0x00008000
+#define SD4_EMMC_TOP_INTREN2_BTIRQSEN_SHIFT 14
+#define SD4_EMMC_TOP_INTREN2_BTIRQSEN_MASK 0x00004000
+#define SD4_EMMC_TOP_INTREN2_BTACKRXSEN_SHIFT 13
+#define SD4_EMMC_TOP_INTREN2_BTACKRXSEN_MASK 0x00002000
+#define SD4_EMMC_TOP_INTREN2_RETUNE_EVENTSIGEN_SHIFT 12
+#define SD4_EMMC_TOP_INTREN2_RETUNE_EVENTSIGEN_MASK 0x00001000
+#define SD4_EMMC_TOP_INTREN2_INT_C_SIGEN_SHIFT 11
+#define SD4_EMMC_TOP_INTREN2_INT_C_SIGEN_MASK 0x00000800
+#define SD4_EMMC_TOP_INTREN2_INT_B_SIGEN_SHIFT 10
+#define SD4_EMMC_TOP_INTREN2_INT_B_SIGEN_MASK 0x00000400
+#define SD4_EMMC_TOP_INTREN2_INT_A_SIGEN_SHIFT 9
+#define SD4_EMMC_TOP_INTREN2_INT_A_SIGEN_MASK 0x00000200
+#define SD4_EMMC_TOP_INTREN2_CRDIRQEN_SHIFT 8
+#define SD4_EMMC_TOP_INTREN2_CRDIRQEN_MASK 0x00000100
+#define SD4_EMMC_TOP_INTREN2_CRDRVMEN_SHIFT 7
+#define SD4_EMMC_TOP_INTREN2_CRDRVMEN_MASK 0x00000080
+#define SD4_EMMC_TOP_INTREN2_CRDINSEN_SHIFT 6
+#define SD4_EMMC_TOP_INTREN2_CRDINSEN_MASK 0x00000040
+#define SD4_EMMC_TOP_INTREN2_BUFRRDYEN_SHIFT 5
+#define SD4_EMMC_TOP_INTREN2_BUFRRDYEN_MASK 0x00000020
+#define SD4_EMMC_TOP_INTREN2_BUFWRDYEN_SHIFT 4
+#define SD4_EMMC_TOP_INTREN2_BUFWRDYEN_MASK 0x00000010
+#define SD4_EMMC_TOP_INTREN2_DMAIRQEN_SHIFT 3
+#define SD4_EMMC_TOP_INTREN2_DMAIRQEN_MASK 0x00000008
+#define SD4_EMMC_TOP_INTREN2_BLKGAPEN_SHIFT 2
+#define SD4_EMMC_TOP_INTREN2_BLKGAPEN_MASK 0x00000004
+#define SD4_EMMC_TOP_INTREN2_TXDONE_SHIFT 1
+#define SD4_EMMC_TOP_INTREN2_TXDONE_MASK 0x00000002
+#define SD4_EMMC_TOP_INTREN2_CMDDONE_SHIFT 0
+#define SD4_EMMC_TOP_INTREN2_CMDDONE_MASK 0x00000001
+
+#define SD4_EMMC_TOP_INTREN2_SD4_OFFSET 0x00000038
+#define SD4_EMMC_TOP_INTREN2_SD4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_INTREN2_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_INTREN2_SD4_RESERVED_MASK 0xF0006000
+#define SD4_EMMC_TOP_INTREN2_SD4_TRESPERRSEN_SHIFT 27
+#define SD4_EMMC_TOP_INTREN2_SD4_TRESPERRSEN_MASK 0x08000000
+#define SD4_EMMC_TOP_INTREN2_SD4_TUNERRSIGEN_SHIFT 26
+#define SD4_EMMC_TOP_INTREN2_SD4_TUNERRSIGEN_MASK 0x04000000
+#define SD4_EMMC_TOP_INTREN2_SD4_ADMASIGEN_SHIFT 25
+#define SD4_EMMC_TOP_INTREN2_SD4_ADMASIGEN_MASK 0x02000000
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDSIGEN_SHIFT 24
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDSIGEN_MASK 0x01000000
+#define SD4_EMMC_TOP_INTREN2_SD4_ILIMSIGEN_SHIFT 23
+#define SD4_EMMC_TOP_INTREN2_SD4_ILIMSIGEN_MASK 0x00800000
+#define SD4_EMMC_TOP_INTREN2_SD4_DEBSIGEN_SHIFT 22
+#define SD4_EMMC_TOP_INTREN2_SD4_DEBSIGEN_MASK 0x00400000
+#define SD4_EMMC_TOP_INTREN2_SD4_DCRCSIGEN_SHIFT 21
+#define SD4_EMMC_TOP_INTREN2_SD4_DCRCSIGEN_MASK 0x00200000
+#define SD4_EMMC_TOP_INTREN2_SD4_DTOSIGEN_SHIFT 20
+#define SD4_EMMC_TOP_INTREN2_SD4_DTOSIGEN_MASK 0x00100000
+#define SD4_EMMC_TOP_INTREN2_SD4_CIDXSIGEN_SHIFT 19
+#define SD4_EMMC_TOP_INTREN2_SD4_CIDXSIGEN_MASK 0x00080000
+#define SD4_EMMC_TOP_INTREN2_SD4_CEBSIGEN_SHIFT 18
+#define SD4_EMMC_TOP_INTREN2_SD4_CEBSIGEN_MASK 0x00040000
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDCRCSIGEN_SHIFT 17
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDCRCSIGEN_MASK 0x00020000
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDTOSIGEN_SHIFT 16
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDTOSIGEN_MASK 0x00010000
+#define SD4_EMMC_TOP_INTREN2_SD4_FIXZERO_SHIFT 15
+#define SD4_EMMC_TOP_INTREN2_SD4_FIXZERO_MASK 0x00008000
+#define SD4_EMMC_TOP_INTREN2_SD4_RETUNE_EVENTSIGEN_SHIFT 12
+#define SD4_EMMC_TOP_INTREN2_SD4_RETUNE_EVENTSIGEN_MASK 0x00001000
+#define SD4_EMMC_TOP_INTREN2_SD4_INT_C_SIGEN_SHIFT 11
+#define SD4_EMMC_TOP_INTREN2_SD4_INT_C_SIGEN_MASK 0x00000800
+#define SD4_EMMC_TOP_INTREN2_SD4_INT_B_SIGEN_SHIFT 10
+#define SD4_EMMC_TOP_INTREN2_SD4_INT_B_SIGEN_MASK 0x00000400
+#define SD4_EMMC_TOP_INTREN2_SD4_INT_A_SIGEN_SHIFT 9
+#define SD4_EMMC_TOP_INTREN2_SD4_INT_A_SIGEN_MASK 0x00000200
+#define SD4_EMMC_TOP_INTREN2_SD4_CRDIRQEN_SHIFT 8
+#define SD4_EMMC_TOP_INTREN2_SD4_CRDIRQEN_MASK 0x00000100
+#define SD4_EMMC_TOP_INTREN2_SD4_CRDRVMEN_SHIFT 7
+#define SD4_EMMC_TOP_INTREN2_SD4_CRDRVMEN_MASK 0x00000080
+#define SD4_EMMC_TOP_INTREN2_SD4_CRDINSEN_SHIFT 6
+#define SD4_EMMC_TOP_INTREN2_SD4_CRDINSEN_MASK 0x00000040
+#define SD4_EMMC_TOP_INTREN2_SD4_BUFRRDYEN_SHIFT 5
+#define SD4_EMMC_TOP_INTREN2_SD4_BUFRRDYEN_MASK 0x00000020
+#define SD4_EMMC_TOP_INTREN2_SD4_BUFWRDYEN_SHIFT 4
+#define SD4_EMMC_TOP_INTREN2_SD4_BUFWRDYEN_MASK 0x00000010
+#define SD4_EMMC_TOP_INTREN2_SD4_DMAIRQEN_SHIFT 3
+#define SD4_EMMC_TOP_INTREN2_SD4_DMAIRQEN_MASK 0x00000008
+#define SD4_EMMC_TOP_INTREN2_SD4_BLKGAPEN_SHIFT 2
+#define SD4_EMMC_TOP_INTREN2_SD4_BLKGAPEN_MASK 0x00000004
+#define SD4_EMMC_TOP_INTREN2_SD4_TXDONE_SHIFT 1
+#define SD4_EMMC_TOP_INTREN2_SD4_TXDONE_MASK 0x00000002
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDDONE_SHIFT 0
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDDONE_MASK 0x00000001
+
+#define SD4_EMMC_TOP_ERRSTAT_OFFSET 0x0000003C
+#define SD4_EMMC_TOP_ERRSTAT_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_ERRSTAT_TYPE uint32_t
+#define SD4_EMMC_TOP_ERRSTAT_RESERVED_MASK 0x3F00FF60
+#define SD4_EMMC_TOP_ERRSTAT_PRESETEN_SHIFT 31
+#define SD4_EMMC_TOP_ERRSTAT_PRESETEN_MASK 0x80000000
+#define SD4_EMMC_TOP_ERRSTAT_ASYNC_INTREN_SHIFT 30
+#define SD4_EMMC_TOP_ERRSTAT_ASYNC_INTREN_MASK 0x40000000
+#define SD4_EMMC_TOP_ERRSTAT_SAMPLECLOCKSEL_SHIFT 23
+#define SD4_EMMC_TOP_ERRSTAT_SAMPLECLOCKSEL_MASK 0x00800000
+#define SD4_EMMC_TOP_ERRSTAT_EXECTUNE_SHIFT 22
+#define SD4_EMMC_TOP_ERRSTAT_EXECTUNE_MASK 0x00400000
+#define SD4_EMMC_TOP_ERRSTAT_DRVSTRESEL_SHIFT 20
+#define SD4_EMMC_TOP_ERRSTAT_DRVSTRESEL_MASK 0x00300000
+#define SD4_EMMC_TOP_ERRSTAT_EN1P8V_SHIFT 19
+#define SD4_EMMC_TOP_ERRSTAT_EN1P8V_MASK 0x00080000
+#define SD4_EMMC_TOP_ERRSTAT_UHSMODESEL_SHIFT 16
+#define SD4_EMMC_TOP_ERRSTAT_UHSMODESEL_MASK 0x00070000
+#define SD4_EMMC_TOP_ERRSTAT_NOCMD_SHIFT 7
+#define SD4_EMMC_TOP_ERRSTAT_NOCMD_MASK 0x00000080
+#define SD4_EMMC_TOP_ERRSTAT_CMDIDXERR_SHIFT 4
+#define SD4_EMMC_TOP_ERRSTAT_CMDIDXERR_MASK 0x00000010
+#define SD4_EMMC_TOP_ERRSTAT_CMDENDERR_SHIFT 3
+#define SD4_EMMC_TOP_ERRSTAT_CMDENDERR_MASK 0x00000008
+#define SD4_EMMC_TOP_ERRSTAT_CMDCRCERR_SHIFT 2
+#define SD4_EMMC_TOP_ERRSTAT_CMDCRCERR_MASK 0x00000004
+#define SD4_EMMC_TOP_ERRSTAT_CMDTOERR_SHIFT 1
+#define SD4_EMMC_TOP_ERRSTAT_CMDTOERR_MASK 0x00000002
+#define SD4_EMMC_TOP_ERRSTAT_CMDNOEXEC_SHIFT 0
+#define SD4_EMMC_TOP_ERRSTAT_CMDNOEXEC_MASK 0x00000001
+
+#define SD4_EMMC_TOP_ERRSTAT_SD4_OFFSET 0x0000003C
+#define SD4_EMMC_TOP_ERRSTAT_SD4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_ERRSTAT_SD4_RESERVED_MASK 0x0E00FF40
+#define SD4_EMMC_TOP_ERRSTAT_SD4_PRESETEN_SHIFT 31
+#define SD4_EMMC_TOP_ERRSTAT_SD4_PRESETEN_MASK 0x80000000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_ASYNC_INTREN_SHIFT 30
+#define SD4_EMMC_TOP_ERRSTAT_SD4_ASYNC_INTREN_MASK 0x40000000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_ADDR64_SHIFT 29
+#define SD4_EMMC_TOP_ERRSTAT_SD4_ADDR64_MASK 0x20000000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_HOSTVER4_00_SHIFT 28
+#define SD4_EMMC_TOP_ERRSTAT_SD4_HOSTVER4_00_MASK 0x10000000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_UHS2INTFEN_SHIFT 24
+#define SD4_EMMC_TOP_ERRSTAT_SD4_UHS2INTFEN_MASK 0x01000000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_SAMPLECLOCKSEL_SHIFT 23
+#define SD4_EMMC_TOP_ERRSTAT_SD4_SAMPLECLOCKSEL_MASK 0x00800000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_EXECTUNE_SHIFT 22
+#define SD4_EMMC_TOP_ERRSTAT_SD4_EXECTUNE_MASK 0x00400000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_DRVSTRESEL_SHIFT 20
+#define SD4_EMMC_TOP_ERRSTAT_SD4_DRVSTRESEL_MASK 0x00300000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_EN1P8V_SHIFT 19
+#define SD4_EMMC_TOP_ERRSTAT_SD4_EN1P8V_MASK 0x00080000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_UHSMODESEL_SHIFT 16
+#define SD4_EMMC_TOP_ERRSTAT_SD4_UHSMODESEL_MASK 0x00070000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_NOCMD_SHIFT 7
+#define SD4_EMMC_TOP_ERRSTAT_SD4_NOCMD_MASK 0x00000080
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDRESPERR_SHIFT 5
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDRESPERR_MASK 0x00000020
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDIDXERR_SHIFT 4
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDIDXERR_MASK 0x00000010
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDENDERR_SHIFT 3
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDENDERR_MASK 0x00000008
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDCRCERR_SHIFT 2
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDCRCERR_MASK 0x00000004
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDTOERR_SHIFT 1
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDTOERR_MASK 0x00000002
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDNOEXEC_SHIFT 0
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDNOEXEC_MASK 0x00000001
+
+#define SD4_EMMC_TOP_CAPABILITIES1_OFFSET 0x00000040
+#define SD4_EMMC_TOP_CAPABILITIES1_DEFAULT 0x17EFD0B0
+#define SD4_EMMC_TOP_CAPABILITIES1_TYPE uint32_t
+#define SD4_EMMC_TOP_CAPABILITIES1_RESERVED_MASK 0x08100040
+#define SD4_EMMC_TOP_CAPABILITIES1_SLOTTYPE_SHIFT 30
+#define SD4_EMMC_TOP_CAPABILITIES1_SLOTTYPE_MASK 0xC0000000
+#define SD4_EMMC_TOP_CAPABILITIES1_ASYNCHIRQ_SHIFT 29
+#define SD4_EMMC_TOP_CAPABILITIES1_ASYNCHIRQ_MASK 0x20000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SYSBUS64_SHIFT 28
+#define SD4_EMMC_TOP_CAPABILITIES1_SYSBUS64_MASK 0x10000000
+#define SD4_EMMC_TOP_CAPABILITIES1_V18_SHIFT 26
+#define SD4_EMMC_TOP_CAPABILITIES1_V18_MASK 0x04000000
+#define SD4_EMMC_TOP_CAPABILITIES1_V3_SHIFT 25
+#define SD4_EMMC_TOP_CAPABILITIES1_V3_MASK 0x02000000
+#define SD4_EMMC_TOP_CAPABILITIES1_V33_SHIFT 24
+#define SD4_EMMC_TOP_CAPABILITIES1_V33_MASK 0x01000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SUPRSM_SHIFT 23
+#define SD4_EMMC_TOP_CAPABILITIES1_SUPRSM_MASK 0x00800000
+#define SD4_EMMC_TOP_CAPABILITIES1_SDMA_SHIFT 22
+#define SD4_EMMC_TOP_CAPABILITIES1_SDMA_MASK 0x00400000
+#define SD4_EMMC_TOP_CAPABILITIES1_HSPEED_SHIFT 21
+#define SD4_EMMC_TOP_CAPABILITIES1_HSPEED_MASK 0x00200000
+#define SD4_EMMC_TOP_CAPABILITIES1_ADMA2_SHIFT 19
+#define SD4_EMMC_TOP_CAPABILITIES1_ADMA2_MASK 0x00080000
+#define SD4_EMMC_TOP_CAPABILITIES1_EXTBUSMED_SHIFT 18
+#define SD4_EMMC_TOP_CAPABILITIES1_EXTBUSMED_MASK 0x00040000
+#define SD4_EMMC_TOP_CAPABILITIES1_MAXBLK_SHIFT 16
+#define SD4_EMMC_TOP_CAPABILITIES1_MAXBLK_MASK 0x00030000
+#define SD4_EMMC_TOP_CAPABILITIES1_BCLK_SHIFT 8
+#define SD4_EMMC_TOP_CAPABILITIES1_BCLK_MASK 0x0000FF00
+#define SD4_EMMC_TOP_CAPABILITIES1_TOUT_SHIFT 7
+#define SD4_EMMC_TOP_CAPABILITIES1_TOUT_MASK 0x00000080
+#define SD4_EMMC_TOP_CAPABILITIES1_TOUTFREQ_SHIFT 0
+#define SD4_EMMC_TOP_CAPABILITIES1_TOUTFREQ_MASK 0x0000003F
+
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_OFFSET 0x00000040
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_DEFAULT 0x10E934B4
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_RESERVED_MASK 0x08100040
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SLOTTYPE_SHIFT 30
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SLOTTYPE_MASK 0xC0000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ASYNCHIRQ_SHIFT 29
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ASYNCHIRQ_MASK 0x20000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SYSBUS64_SHIFT 28
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SYSBUS64_MASK 0x10000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V18_SHIFT 26
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V18_MASK 0x04000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V3_SHIFT 25
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V3_MASK 0x02000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V33_SHIFT 24
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V33_MASK 0x01000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SUPRSM_SHIFT 23
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SUPRSM_MASK 0x00800000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SDMA_SHIFT 22
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SDMA_MASK 0x00400000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_HSPEED_SHIFT 21
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_HSPEED_MASK 0x00200000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ADMA2_SHIFT 19
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ADMA2_MASK 0x00080000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_EXTBUSMED_SHIFT 18
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_EXTBUSMED_MASK 0x00040000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_MAXBLK_SHIFT 16
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_MAXBLK_MASK 0x00030000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_BCLK_SHIFT 8
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_BCLK_MASK 0x0000FF00
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUT_SHIFT 7
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUT_MASK 0x00000080
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUTFREQ_SHIFT 0
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUTFREQ_MASK 0x0000003F
+
+#define SD4_EMMC_TOP_CAPABILITIES2_OFFSET 0x00000044
+#define SD4_EMMC_TOP_CAPABILITIES2_DEFAULT 0x03002177
+#define SD4_EMMC_TOP_CAPABILITIES2_TYPE uint32_t
+#define SD4_EMMC_TOP_CAPABILITIES2_RESERVED_MASK 0xFC001088
+#define SD4_EMMC_TOP_CAPABILITIES2_SPIBLOCKMODE_SHIFT 25
+#define SD4_EMMC_TOP_CAPABILITIES2_SPIBLOCKMODE_MASK 0x02000000
+#define SD4_EMMC_TOP_CAPABILITIES2_SPIMODE_CAP_SHIFT 24
+#define SD4_EMMC_TOP_CAPABILITIES2_SPIMODE_CAP_MASK 0x01000000
+#define SD4_EMMC_TOP_CAPABILITIES2_CLOCKMULT_SHIFT 16
+#define SD4_EMMC_TOP_CAPABILITIES2_CLOCKMULT_MASK 0x00FF0000
+#define SD4_EMMC_TOP_CAPABILITIES2_RETUNE_MODE_SHIFT 14
+#define SD4_EMMC_TOP_CAPABILITIES2_RETUNE_MODE_MASK 0x0000C000
+#define SD4_EMMC_TOP_CAPABILITIES2_USETUNE_SDR50_SHIFT 13
+#define SD4_EMMC_TOP_CAPABILITIES2_USETUNE_SDR50_MASK 0x00002000
+#define SD4_EMMC_TOP_CAPABILITIES2_TMRCNT_RETUNE_SHIFT 8
+#define SD4_EMMC_TOP_CAPABILITIES2_TMRCNT_RETUNE_MASK 0x00000F00
+#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPED_SHIFT 6
+#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPED_MASK 0x00000040
+#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEC_SHIFT 5
+#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEC_MASK 0x00000020
+#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEA_SHIFT 4
+#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEA_MASK 0x00000010
+#define SD4_EMMC_TOP_CAPABILITIES2_DDR50_SHIFT 2
+#define SD4_EMMC_TOP_CAPABILITIES2_DDR50_MASK 0x00000004
+#define SD4_EMMC_TOP_CAPABILITIES2_SDR104_SHIFT 1
+#define SD4_EMMC_TOP_CAPABILITIES2_SDR104_MASK 0x00000002
+#define SD4_EMMC_TOP_CAPABILITIES2_SDR50_SHIFT 0
+#define SD4_EMMC_TOP_CAPABILITIES2_SDR50_MASK 0x00000001
+
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_OFFSET 0x00000044
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DEFAULT 0x10000064
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_RESERVED_MASK 0xE7001080
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_VDD2_18_SHIFT 28
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_VDD2_18_MASK 0x10000000
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_ADMA3_SHIFT 27
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_ADMA3_MASK 0x08000000
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_CLOCKMULT_SHIFT 16
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_CLOCKMULT_MASK 0x00FF0000
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_RETUNE_MODE_SHIFT 14
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_RETUNE_MODE_MASK 0x0000C000
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_USETUNE_SDR50_SHIFT 13
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_USETUNE_SDR50_MASK 0x00002000
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_TMRCNT_RETUNE_SHIFT 8
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_TMRCNT_RETUNE_MASK 0x00000F00
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPED_SHIFT 6
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPED_MASK 0x00000040
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEC_SHIFT 5
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEC_MASK 0x00000020
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEA_SHIFT 4
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEA_MASK 0x00000010
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_UHS_II_SHIFT 3
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_UHS_II_MASK 0x00000008
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DDR50_SHIFT 2
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DDR50_MASK 0x00000004
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR104_SHIFT 1
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR104_MASK 0x00000002
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR50_SHIFT 0
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR50_MASK 0x00000001
+
+#define SD4_EMMC_TOP_MAX_A1_OFFSET 0x00000048
+#define SD4_EMMC_TOP_MAX_A1_DEFAULT 0x00000001
+#define SD4_EMMC_TOP_MAX_A1_TYPE uint32_t
+#define SD4_EMMC_TOP_MAX_A1_RESERVED_MASK 0xFF000000
+#define SD4_EMMC_TOP_MAX_A1_MAXA18_SHIFT 16
+#define SD4_EMMC_TOP_MAX_A1_MAXA18_MASK 0x00FF0000
+#define SD4_EMMC_TOP_MAX_A1_MAXA30_SHIFT 8
+#define SD4_EMMC_TOP_MAX_A1_MAXA30_MASK 0x0000FF00
+#define SD4_EMMC_TOP_MAX_A1_MAXA33_SHIFT 0
+#define SD4_EMMC_TOP_MAX_A1_MAXA33_MASK 0x000000FF
+
+#define SD4_EMMC_TOP_MAX_A2_OFFSET 0x0000004C
+#define SD4_EMMC_TOP_MAX_A2_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_MAX_A2_TYPE uint32_t
+#define SD4_EMMC_TOP_MAX_A2_RESERVED_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_MAX_A2_SD4_OFFSET 0x0000004C
+#define SD4_EMMC_TOP_MAX_A2_SD4_DEFAULT 0x00000001
+#define SD4_EMMC_TOP_MAX_A2_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_MAX_A2_SD4_RESERVED_MASK 0xFFFFFF00
+#define SD4_EMMC_TOP_MAX_A2_SD4_MAXAVDD2_SHIFT 0
+#define SD4_EMMC_TOP_MAX_A2_SD4_MAXAVDD2_MASK 0x000000FF
+
+#define SD4_EMMC_TOP_CMDENTSTAT_OFFSET 0x00000050
+#define SD4_EMMC_TOP_CMDENTSTAT_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_CMDENTSTAT_TYPE uint32_t
+#define SD4_EMMC_TOP_CMDENTSTAT_RESERVED_MASK 0x2C00FF60
+#define SD4_EMMC_TOP_CMDENTSTAT_VSES_SHIFT 30
+#define SD4_EMMC_TOP_CMDENTSTAT_VSES_MASK 0xC0000000
+#define SD4_EMMC_TOP_CMDENTSTAT_TRERR_SHIFT 28
+#define SD4_EMMC_TOP_CMDENTSTAT_TRERR_MASK 0x10000000
+#define SD4_EMMC_TOP_CMDENTSTAT_ADMAERR_SHIFT 25
+#define SD4_EMMC_TOP_CMDENTSTAT_ADMAERR_MASK 0x02000000
+#define SD4_EMMC_TOP_CMDENTSTAT_ACMDERR_SHIFT 24
+#define SD4_EMMC_TOP_CMDENTSTAT_ACMDERR_MASK 0x01000000
+#define SD4_EMMC_TOP_CMDENTSTAT_ILERR_SHIFT 23
+#define SD4_EMMC_TOP_CMDENTSTAT_ILERR_MASK 0x00800000
+#define SD4_EMMC_TOP_CMDENTSTAT_DENDERR_SHIFT 22
+#define SD4_EMMC_TOP_CMDENTSTAT_DENDERR_MASK 0x00400000
+#define SD4_EMMC_TOP_CMDENTSTAT_DCRCERR_SHIFT 21
+#define SD4_EMMC_TOP_CMDENTSTAT_DCRCERR_MASK 0x00200000
+#define SD4_EMMC_TOP_CMDENTSTAT_DTOUTERR_SHIFT 20
+#define SD4_EMMC_TOP_CMDENTSTAT_DTOUTERR_MASK 0x00100000
+#define SD4_EMMC_TOP_CMDENTSTAT_CIDXERR_SHIFT 19
+#define SD4_EMMC_TOP_CMDENTSTAT_CIDXERR_MASK 0x00080000
+#define SD4_EMMC_TOP_CMDENTSTAT_CENDERR_SHIFT 18
+#define SD4_EMMC_TOP_CMDENTSTAT_CENDERR_MASK 0x00040000
+#define SD4_EMMC_TOP_CMDENTSTAT_CCRCERR_SHIFT 17
+#define SD4_EMMC_TOP_CMDENTSTAT_CCRCERR_MASK 0x00020000
+#define SD4_EMMC_TOP_CMDENTSTAT_CTOUTERR_SHIFT 16
+#define SD4_EMMC_TOP_CMDENTSTAT_CTOUTERR_MASK 0x00010000
+#define SD4_EMMC_TOP_CMDENTSTAT_NOFRCENT_SHIFT 7
+#define SD4_EMMC_TOP_CMDENTSTAT_NOFRCENT_MASK 0x00000080
+#define SD4_EMMC_TOP_CMDENTSTAT_IDXERR_SHIFT 4
+#define SD4_EMMC_TOP_CMDENTSTAT_IDXERR_MASK 0x00000010
+#define SD4_EMMC_TOP_CMDENTSTAT_EBITERR_SHIFT 3
+#define SD4_EMMC_TOP_CMDENTSTAT_EBITERR_MASK 0x00000008
+#define SD4_EMMC_TOP_CMDENTSTAT_CRCERR_SHIFT 2
+#define SD4_EMMC_TOP_CMDENTSTAT_CRCERR_MASK 0x00000004
+#define SD4_EMMC_TOP_CMDENTSTAT_TOUTERR_SHIFT 1
+#define SD4_EMMC_TOP_CMDENTSTAT_TOUTERR_MASK 0x00000002
+#define SD4_EMMC_TOP_CMDENTSTAT_AUTONOEX_SHIFT 0
+#define SD4_EMMC_TOP_CMDENTSTAT_AUTONOEX_MASK 0x00000001
+
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_OFFSET 0x00000050
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_RESERVED_MASK 0x0000FF40
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_VSES_SHIFT 28
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_VSES_MASK 0xF0000000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TRESPERR_SHIFT 27
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TRESPERR_MASK 0x08000000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TUNERR_SHIFT 26
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TUNERR_MASK 0x04000000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ADMAERR_SHIFT 25
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ADMAERR_MASK 0x02000000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ACMDERR_SHIFT 24
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ACMDERR_MASK 0x01000000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ILERR_SHIFT 23
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ILERR_MASK 0x00800000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DENDERR_SHIFT 22
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DENDERR_MASK 0x00400000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DCRCERR_SHIFT 21
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DCRCERR_MASK 0x00200000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DTOUTERR_SHIFT 20
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DTOUTERR_MASK 0x00100000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CIDXERR_SHIFT 19
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CIDXERR_MASK 0x00080000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CENDERR_SHIFT 18
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CENDERR_MASK 0x00040000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CCRCERR_SHIFT 17
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CCRCERR_MASK 0x00020000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CTOUTERR_SHIFT 16
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CTOUTERR_MASK 0x00010000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_NOFRCENT_SHIFT 7
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_NOFRCENT_MASK 0x00000080
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_RESPERR_SHIFT 5
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_RESPERR_MASK 0x00000020
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_IDXERR_SHIFT 4
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_IDXERR_MASK 0x00000010
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_EBITERR_SHIFT 3
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_EBITERR_MASK 0x00000008
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CRCERR_SHIFT 2
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CRCERR_MASK 0x00000004
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TOUTERR_SHIFT 1
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TOUTERR_MASK 0x00000002
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_AUTONOEX_SHIFT 0
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_AUTONOEX_MASK 0x00000001
+
+#define SD4_EMMC_TOP_ADMAERR_OFFSET 0x00000054
+#define SD4_EMMC_TOP_ADMAERR_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_ADMAERR_TYPE uint32_t
+#define SD4_EMMC_TOP_ADMAERR_RESERVED_MASK 0xFFFFFFF8
+#define SD4_EMMC_TOP_ADMAERR_ADMALERR_SHIFT 2
+#define SD4_EMMC_TOP_ADMAERR_ADMALERR_MASK 0x00000004
+#define SD4_EMMC_TOP_ADMAERR_ADMAERR_SHIFT 0
+#define SD4_EMMC_TOP_ADMAERR_ADMAERR_MASK 0x00000003
+
+#define SD4_EMMC_TOP_ADMAADDR0_OFFSET 0x00000058
+#define SD4_EMMC_TOP_ADMAADDR0_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_ADMAADDR0_TYPE uint32_t
+#define SD4_EMMC_TOP_ADMAADDR0_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_ADMAADDR0_ADMAADDR0_SHIFT 0
+#define SD4_EMMC_TOP_ADMAADDR0_ADMAADDR0_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_ADMAADDR1_OFFSET 0x0000005C
+#define SD4_EMMC_TOP_ADMAADDR1_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_ADMAADDR1_TYPE uint32_t
+#define SD4_EMMC_TOP_ADMAADDR1_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_ADMAADDR1_ADMAADDR1_SHIFT 0
+#define SD4_EMMC_TOP_ADMAADDR1_ADMAADDR1_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_PRESETVAL1_OFFSET 0x00000060
+#define SD4_EMMC_TOP_PRESETVAL1_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_PRESETVAL1_TYPE uint32_t
+#define SD4_EMMC_TOP_PRESETVAL1_RESERVED_MASK 0x38003800
+#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_DFS_SHIFT 30
+#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_DFS_MASK 0xC0000000
+#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_DFS_SHIFT 26
+#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_DFS_MASK 0x04000000
+#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_DFS_SHIFT 16
+#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_DFS_MASK 0x03FF0000
+#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_INIT_SHIFT 14
+#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_INIT_MASK 0x0000C000
+#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_INIT_SHIFT 10
+#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_INIT_MASK 0x00000400
+#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_INIT_SHIFT 0
+#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_INIT_MASK 0x000003FF
+
+#define SD4_EMMC_TOP_PRESETVAL2_OFFSET 0x00000064
+#define SD4_EMMC_TOP_PRESETVAL2_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_PRESETVAL2_TYPE uint32_t
+#define SD4_EMMC_TOP_PRESETVAL2_RESERVED_MASK 0x38003800
+#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_SDR12_SHIFT 30
+#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_SDR12_MASK 0xC0000000
+#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_SDR12_SHIFT 26
+#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_SDR12_MASK 0x04000000
+#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_SDR12_SHIFT 16
+#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_SDR12_MASK 0x03FF0000
+#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_HS_SHIFT 14
+#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_HS_MASK 0x0000C000
+#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_HS_SHIFT 10
+#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_HS_MASK 0x00000400
+#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_HS_SHIFT 0
+#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_HS_MASK 0x000003FF
+
+#define SD4_EMMC_TOP_PRESETVAL3_OFFSET 0x00000068
+#define SD4_EMMC_TOP_PRESETVAL3_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_PRESETVAL3_TYPE uint32_t
+#define SD4_EMMC_TOP_PRESETVAL3_RESERVED_MASK 0x38003800
+#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR50_SHIFT 30
+#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR50_MASK 0xC0000000
+#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR50_SHIFT 26
+#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR50_MASK 0x04000000
+#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR50_SHIFT 16
+#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR50_MASK 0x03FF0000
+#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR25_SHIFT 14
+#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR25_MASK 0x0000C000
+#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR25_SHIFT 10
+#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR25_MASK 0x00000400
+#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR25_SHIFT 0
+#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR25_MASK 0x000003FF
+
+#define SD4_EMMC_TOP_PRESETVAL4_OFFSET 0x0000006C
+#define SD4_EMMC_TOP_PRESETVAL4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_PRESETVAL4_TYPE uint32_t
+#define SD4_EMMC_TOP_PRESETVAL4_RESERVED_MASK 0x38003800
+#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_DDR50_SHIFT 30
+#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_DDR50_MASK 0xC0000000
+#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_DDR50_SHIFT 26
+#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_DDR50_MASK 0x04000000
+#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_DDR50_SHIFT 16
+#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_DDR50_MASK 0x03FF0000
+#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_SDR104_SHIFT 14
+#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_SDR104_MASK 0x0000C000
+#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_SDR104_SHIFT 10
+#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_SDR104_MASK 0x00000400
+#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_SDR104_SHIFT 0
+#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_SDR104_MASK 0x000003FF
+
+#define SD4_EMMC_TOP_BOOTTIMEOUT_OFFSET 0x00000070
+#define SD4_EMMC_TOP_BOOTTIMEOUT_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_BOOTTIMEOUT_TYPE uint32_t
+#define SD4_EMMC_TOP_BOOTTIMEOUT_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_BOOTTIMEOUT_BOOTDATATIMEOUTCTRVALUE_SHIFT 0
+#define SD4_EMMC_TOP_BOOTTIMEOUT_BOOTDATATIMEOUTCTRVALUE_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_DBGSEL_OFFSET 0x00000074
+#define SD4_EMMC_TOP_DBGSEL_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_DBGSEL_TYPE uint32_t
+#define SD4_EMMC_TOP_DBGSEL_RESERVED_MASK 0xFFFFFFFE
+#define SD4_EMMC_TOP_DBGSEL_DBGSEL_SHIFT 0
+#define SD4_EMMC_TOP_DBGSEL_DBGSEL_MASK 0x00000001
+
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_OFFSET 0x00000074
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_TYPE uint32_t
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_RESERVED_MASK 0xFFFF3800
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_DRVSTRVAL_SHIFT 14
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_DRVSTRVAL_MASK 0x0000C000
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_CLKGENSELVAL_SHIFT 10
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_CLKGENSELVAL_MASK 0x00000400
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_SDCLKFREQSELVAL_SHIFT 0
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_SDCLKFREQSELVAL_MASK 0x000003FF
+
+#define SD4_EMMC_TOP_HCVERSIRQ_OFFSET 0x000000FC
+#define SD4_EMMC_TOP_HCVERSIRQ_DEFAULT 0x10020000
+#define SD4_EMMC_TOP_HCVERSIRQ_TYPE uint32_t
+#define SD4_EMMC_TOP_HCVERSIRQ_RESERVED_MASK 0x0000FF00
+#define SD4_EMMC_TOP_HCVERSIRQ_VENDVER_SHIFT 24
+#define SD4_EMMC_TOP_HCVERSIRQ_VENDVER_MASK 0xFF000000
+#define SD4_EMMC_TOP_HCVERSIRQ_SPECVER_SHIFT 16
+#define SD4_EMMC_TOP_HCVERSIRQ_SPECVER_MASK 0x00FF0000
+#define SD4_EMMC_TOP_HCVERSIRQ_SIRQ_SHIFT 0
+#define SD4_EMMC_TOP_HCVERSIRQ_SIRQ_MASK 0x000000FF
+
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_OFFSET 0x000000FC
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_DEFAULT 0x01030000
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_RESERVED_MASK 0x0000FF00
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_VENDVER_SHIFT 24
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_VENDVER_MASK 0xFF000000
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SPECVER_SHIFT 16
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SPECVER_MASK 0x00FF0000
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SIRQ_SHIFT 0
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SIRQ_MASK 0x000000FF
+
+#endif /* BRCM_RDB_SD4_EMMC_TOP_H */
diff --git a/include/drivers/brcm/emmc/emmc_chal_sd.h b/include/drivers/brcm/emmc/emmc_chal_sd.h
new file mode 100644
index 0000000..8d223f9
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_chal_sd.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CHAL_SD_H
+#define CHAL_SD_H
+
+#include <stddef.h>
+
+#define BASE_CLK_FREQ (200 * 1000 * 1000)
+#define INIT_CLK_FREQ (400 * 1000)
+
+#define SD_ERROR_RECOVERABLE 0
+#define SD_ERROR_NON_RECOVERABLE 1
+
+#define SD_OK 0
+#define SD_FAIL (-1)
+#define SD_INVALID_HANDLE (-2)
+#define SD_CEATA_INIT_ERROR (-3)
+#define SD_RESET_ERROR (-4)
+#define SD_CARD_INIT_ERROR (-5)
+#define SD_INV_DATA_WIDTH (-6)
+#define SD_SET_BUS_WIDTH_ERROR (-7)
+#define SD_DMA_NOT_SUPPORT (-8)
+#define SD_SDIO_READ_ERROR (-9)
+#define SD_SDIO_WRITE_ERROR (-10)
+#define SD_WRITE_ERROR (-11)
+#define SD_READ_ERROR (-12)
+#define SD_READ_SIZE_ERROR (-13)
+#define SD_RW_ADDRESS_ERROR (-14)
+#define SD_XFER_ADDRESS_ERROR (-15)
+#define SD_DATA_XFER_ADDR_ERROR (-16)
+#define SD_DATA_XFER_ERROR (-17)
+#define SD_WRITE_SIZE_ERROR (-18)
+#define SD_CMD_STATUS_UPDATE_ERR (-19)
+#define SD_CMD12_ERROR (-20)
+#define SD_CMD_DATA_ERROR (-21)
+#define SD_CMD_TIMEOUT (-22)
+#define SD_CMD_NO_RESPONSE (-22)
+#define SD_CMD_ABORT_ERROR (-23)
+#define SD_CMD_INVALID (-24)
+#define SD_CMD_RESUME_ERROR (-25)
+#define SD_CMD_ERR_INVALID_RESPONSE (-26)
+#define SD_WAIT_TIMEOUT (-27)
+#define SD_READ_TIMEOUT (-28)
+#define SD_CEATA_REST_ERROR (-29)
+#define SD_INIT_CAED_FAILED (-30)
+#define SD_ERROR_CLOCK_OFFLIMIT (-31)
+#define SD_INV_SLOT (-32)
+
+#define SD_NOR_INTERRUPTS 0x000000FF
+#define SD_ERR_INTERRUPTS 0x03FF0000
+#define SD_CMD_ERROR_INT 0x010F0000
+#define SD_DAT_ERROR_INT 0x02F00000
+#define SD_DAT_TIMEOUT 0x00100000
+
+/* Operation modes */
+#define SD_PIO_MODE 0
+#define SD_INT_MODE 1
+
+/* Support both ADMA and SDMA (for version 2.0 and above) */
+#define SD_DMA_OFF 0
+#define SD_DMA_SDMA 1
+#define SD_DMA_ADMA 2
+
+#define SD_NORMAL_SPEED 0
+#define SD_HIGH_SPEED 1
+
+#define SD_XFER_CARD_TO_HOST 3
+#define SD_XFER_HOST_TO_CARD 4
+
+#define SD_CARD_DETECT_AUTO 0
+#define SD_CARD_DETECT_SD 1
+#define SD_CARD_DETECT_SDIO 2
+#define SD_CARD_DETECT_MMC 3
+#define SD_CARD_DETECT_CEATA 4
+
+#define SD_ABORT_SYNC_MODE 0
+#define SD_ABORT_ASYNC_MODE 1
+
+#define SD_CMD_ERROR_FLAGS (0x18F << 16)
+#define SD_DATA_ERROR_FLAGS (0x70 << 16)
+#define SD_AUTO_CMD12_ERROR_FLAGS (0x9F)
+
+#define SD_CARD_STATUS_ERROR 0x10000000
+#define SD_CMD_MISSING 0x80000000
+#define SD_ERROR_INT 0x8000
+
+#define SD_TRAN_HIGH_SPEED 0x32
+#define SD_CARD_HIGH_CAPACITY 0x40000000
+#define SD_CARD_POWER_UP_STATUS 0x80000000
+
+#define SD_HOST_CORE_TIMEOUT 0x0E
+
+/* SD CARD and Host Controllers bus width */
+#define SD_BUS_DATA_WIDTH_1BIT 0x00
+#define SD_BUS_DATA_WIDTH_4BIT 0x02
+#define SD_BUS_DATA_WIDTH_8BIT 0x20
+
+/* dma boundary settings */
+#define SD_DMA_BOUNDARY_4K 0
+#define SD_DMA_BOUNDARY_8K (1 << 12)
+#define SD_DMA_BOUNDARY_16K (2 << 12)
+#define SD_DMA_BOUNDARY_32K (3 << 12)
+#define SD_DMA_BOUNDARY_64K (4 << 12)
+#define SD_DMA_BOUNDARY_128K (5 << 12)
+#define SD_DMA_BOUNDARY_256K (6 << 12)
+#define SD_DMA_BOUNDARY_512K (7 << 12)
+
+#define SD_CMDR_CMD_NORMAL 0x00000000
+#define SD_CMDR_CMD_SUSPEND 0x00400000
+#define SD_CMDR_CMD_RESUME 0x00800000
+#define SD_CMDR_CMD_ABORT 0x00c00000
+
+#define SD_CMDR_RSP_TYPE_NONE 0x0
+#define SD_CMDR_RSP_TYPE_R2 0x1
+#define SD_CMDR_RSP_TYPE_R3_4 0x2
+#define SD_CMDR_RSP_TYPE_R1_5_6 0x2
+#define SD_CMDR_RSP_TYPE_R1b_5b 0x3
+#define SD_CMDR_RSP_TYPE_S 16
+
+struct sd_ctrl_info {
+ uint32_t blkReg; /* current block register cache value */
+ uint32_t cmdReg; /* current command register cache value */
+ uint32_t argReg; /* current argument register cache value */
+ uint32_t cmdIndex; /* current command index */
+ uint32_t cmdStatus; /* current command status, cmd/data compelete */
+ uint16_t rca; /* relative card address */
+ uint32_t ocr; /* operation codition */
+ uint32_t eventList; /* events list */
+ uint32_t blkGapEnable;
+
+ uint32_t capability; /* controller's capbilities */
+ uint32_t maxCurrent; /* maximum current supported */
+ uint32_t present; /* if card is inserted or removed */
+ uint32_t version; /* SD spec version 1.0 or 2.0 */
+ uint32_t vendor; /* vendor number */
+
+ uintptr_t sdRegBaseAddr; /* sdio control registers */
+ uintptr_t hostRegBaseAddr; /* SD Host control registers */
+};
+
+struct sd_cfg {
+ uint32_t mode; /* interrupt or polling */
+ uint32_t dma; /* dma enabled or disabled */
+ uint32_t retryLimit; /* command retry limit */
+ uint32_t speedMode; /* speed mode, 0 standard, 1 high speed */
+ uint32_t voltage; /* voltage level */
+ uint32_t blockSize; /* access block size (512 for HC card) */
+ uint32_t dmaBoundary; /* dma address boundary */
+ uint32_t detSignal; /* card det signal src, for test purpose only */
+ uint32_t rdWaiting;
+ uint32_t wakeupOut;
+ uint32_t wakeupIn;
+ uint32_t wakeupInt;
+ uint32_t wfe_retry;
+ uint32_t gapInt;
+ uint32_t readWait;
+ uint32_t led;
+};
+
+struct sd_dev {
+ struct sd_cfg cfg; /* SD configuration */
+ struct sd_ctrl_info ctrl; /* SD info */
+};
+
+int32_t chal_sd_start(CHAL_HANDLE *sdHandle, uint32_t mode,
+ uint32_t sdBase, uint32_t hostBase);
+int32_t chal_sd_config(CHAL_HANDLE *sdHandle, uint32_t speed,
+ uint32_t retry, uint32_t boundary,
+ uint32_t blkSize, uint32_t dma);
+int32_t chal_sd_stop(void);
+int32_t chal_sd_set_dma(CHAL_HANDLE *sdHandle, uint32_t mode);
+uintptr_t chal_sd_get_dma_addr(CHAL_HANDLE *handle);
+int32_t chal_sd_config_bus_width(CHAL_HANDLE *sdHandle, int32_t width);
+int32_t chal_sd_send_cmd(CHAL_HANDLE *sdHandle, uint32_t cmdIndex,
+ uint32_t arg, uint32_t options);
+int32_t chal_sd_set_dma_addr(CHAL_HANDLE *sdHandle, uintptr_t address);
+int32_t chal_sd_set_clock(CHAL_HANDLE *sdHandle,
+ uint32_t div_ctrl_setting, uint32_t on);
+uint32_t chal_sd_freq_2_div_ctrl_setting(uint32_t desired_freq);
+int32_t chal_sd_setup_xfer(CHAL_HANDLE *sdHandle, uint8_t *data,
+ uint32_t length, int32_t dir);
+int32_t chal_sd_write_buffer(CHAL_HANDLE *sdHandle, uint32_t length,
+ uint8_t *data);
+int32_t chal_sd_read_buffer(CHAL_HANDLE *sdHandle, uint32_t length,
+ uint8_t *data);
+int32_t chal_sd_reset_line(CHAL_HANDLE *sdHandle, uint32_t line);
+int32_t chal_sd_get_response(CHAL_HANDLE *sdHandle, uint32_t *resp);
+int32_t chal_sd_clear_pending_irq(CHAL_HANDLE *sdHandle);
+int32_t chal_sd_get_irq_status(CHAL_HANDLE *sdHandle);
+int32_t chal_sd_clear_irq(CHAL_HANDLE *sdHandle, uint32_t mask);
+uint32_t chal_sd_get_present_status(CHAL_HANDLE *sdHandle);
+int32_t chal_sd_get_atuo12_error(CHAL_HANDLE *sdHandle);
+void chal_sd_set_speed(CHAL_HANDLE *sdHandle, uint32_t speed);
+int32_t chal_sd_check_cap(CHAL_HANDLE *sdHandle, uint32_t cap);
+void chal_sd_set_irq_signal(CHAL_HANDLE *sdHandle, uint32_t mask,
+ uint32_t state);
+void chal_sd_dump_fifo(CHAL_HANDLE *sdHandle);
+#endif /* CHAL_SD_H */
diff --git a/include/drivers/brcm/emmc/emmc_chal_types.h b/include/drivers/brcm/emmc/emmc_chal_types.h
new file mode 100644
index 0000000..9563273
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_chal_types.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef CHAL_TYPES_H
+#define CHAL_TYPES_H
+
+#include <stdint.h>
+
+//
+// Generic cHAL handler
+//
+#ifndef CHAL_HANDLE
+ typedef void *CHAL_HANDLE; ///< void pointer (32 bits wide)
+#endif
+
+#endif /* _CHAL_TYPES_H_ */
diff --git a/include/drivers/brcm/emmc/emmc_csl_sd.h b/include/drivers/brcm/emmc/emmc_csl_sd.h
new file mode 100644
index 0000000..52b8bc8
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_csl_sd.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CSL_SD_H
+#define CSL_SD_H
+
+#define SD_CLOCK_BASE 104000000
+#define SD_CLOCK_52MHZ 52000000
+#define SD_CLOCK_26MHZ 26000000
+#define SD_CLOCK_17MHZ 17330000
+#define SD_CLOCK_13MHZ 13000000
+#define SD_CLOCK_10MHZ 10000000
+#define SD_CLOCK_9MHZ 9000000
+#define SD_CLOCK_7MHZ 7000000
+#define SD_CLOCK_5MHZ 5000000
+#define SD_CLOCK_1MHZ 1000000
+#define SD_CLOCK_400KHZ 400000
+
+#define SD_DRIVE_STRENGTH_MASK 0x38000000
+#if defined(_BCM213x1_) || defined(_BCM21551_) || defined(_ATHENA_)
+#define SD_DRIVE_STRENGTH 0x28000000
+#elif defined(_BCM2153_)
+#define SD_DRIVE_STRENGTH 0x38000000
+#else
+#define SD_DRIVE_STRENGTH 0x00000000
+#endif
+
+#define SD_NUM_HOST 2
+
+#define SD_CARD_UNLOCK 0
+#define SD_CARD_LOCK 0x4
+#define SD_CARD_CLEAR_PWD 0x2
+#define SD_CARD_SET_PWD 0x1
+#define SD_CARD_ERASE_PWD 0x8
+
+#define SD_CARD_LOCK_STATUS 0x02000000
+#define SD_CARD_UNLOCK_STATUS 0x01000000
+
+#define SD_CMD_ERROR_FLAGS (0x18F << 16)
+#define SD_DATA_ERROR_FLAGS (0x70 << 16)
+#define SD_AUTO_CMD12_ERROR_FLAGS (0x9F)
+#define SD_CARD_STATUS_ERROR 0x10000000
+#define SD_CMD_MISSING 0x80000000
+
+#define SD_TRAN_HIGH_SPEED 0x32
+#define SD_CARD_HIGH_CAPACITY 0x40000000
+#define SD_CARD_POWER_UP_STATUS 0x80000000
+
+struct sd_dev_info {
+ uint32_t mode; /* interrupt or polling */
+ uint32_t dma; /* dma enabled or disabled */
+ uint32_t voltage; /* voltage level */
+ uint32_t slot; /* if the HC is locatd at slot 0 or slot 1 */
+ uint32_t version; /* 1.0 or 2.0 */
+ uint32_t curSystemAddr; /* system address */
+ uint32_t dataWidth; /* data width for the controller */
+ uint32_t clock; /* clock rate */
+ uint32_t status; /* if device is active on transfer or not */
+};
+
+void data_xfer_setup(struct sd_handle *handle, uint8_t *data,
+ uint32_t length, int dir);
+int reset_card(struct sd_handle *handle);
+int reset_host_ctrl(struct sd_handle *handle);
+int init_card(struct sd_handle *handle, int detection);
+int init_mmc_card(struct sd_handle *handle);
+int write_buffer(struct sd_handle *handle, uint32_t len, uint8_t *buffer);
+int read_buffer(struct sd_handle *handle, uint32_t len, uint8_t *buffer);
+int select_blk_sz(struct sd_handle *handle, uint16_t size);
+int check_error(struct sd_handle *handle, uint32_t ints);
+
+int process_data_xfer(struct sd_handle *handle, uint8_t *buffer,
+ uint32_t addr, uint32_t length, int dir);
+int read_block(struct sd_handle *handle, uint8_t *dst, uint32_t addr,
+ uint32_t len);
+#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
+int erase_card(struct sd_handle *handle, uint32_t addr, uint32_t blocks);
+#endif
+int write_block(struct sd_handle *handle, uint8_t *src, uint32_t addr,
+ uint32_t len);
+int process_cmd_response(struct sd_handle *handle, uint32_t cmdIndex,
+ uint32_t rsp0, uint32_t rsp1, uint32_t rsp2,
+ uint32_t rsp3, struct sd_resp *resp);
+int32_t set_config(struct sd_handle *handle, uint32_t speed,
+ uint32_t retry, uint32_t dma, uint32_t dmaBound,
+ uint32_t blkSize, uint32_t wfe_retry);
+
+uint32_t wait_for_event(struct sd_handle *handle, uint32_t mask,
+ uint32_t retry);
+int set_boot_config(struct sd_handle *handle, uint32_t config);
+
+int mmc_cmd1(struct sd_handle *handle);
+#endif /* CSL_SD_H */
diff --git a/include/drivers/brcm/emmc/emmc_csl_sdcmd.h b/include/drivers/brcm/emmc/emmc_csl_sdcmd.h
new file mode 100644
index 0000000..425603f
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_csl_sdcmd.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CSL_SD_CMD_H
+#define CSL_SD_CMD_H
+
+#define SD_CMD_OK 0
+#define SD_CMD_ERROR -1
+
+#define SD_CMD_ERR_NO_IO_FUNC 5
+#define SD_CMD_ERR_INVALID_PARAMETER 6
+#define SD_CMD_ERR_R1_ILLEGAL_COMMAND 7
+#define SD_CMD_ERR_R1_COM_CRC_ERROR 8
+#define SD_CMD_ERR_R1_FUNC_NUM_ERROR 9
+#define SD_CMD_ERR_R1_ADDRESS_ERROR 10
+#define SD_CMD_ERR_R1_PARAMETER_ERROR 11
+#define SD_CMD_ERR_DATA_ERROR_TOKEN 12
+#define SD_CMD_ERR_DATA_NOT_ACCEPTED 13
+#define SD_CMD7_ARG_RCA_SHIFT 16
+
+#define SD_CARD_STATUS_PENDING 0x01
+#define SD_CARD_STATUS_BUFFER_OVERFLOW 0x01
+#define SD_CARD_STATUS_DEVICE_BUSY 0x02
+#define SD_CARD_STATUS_UNSUCCESSFUL 0x03
+#define SD_CARD_STATUS_NOT_IMPLEMENTED 0x04
+#define SD_CARD_STATUS_ACCESS_VIOLATION 0x05
+#define SD_CARD_STATUS_INVALID_HANDLE 0x06
+#define SD_CARD_STATUS_INVALID_PARAMETER 0x07
+#define SD_CARD_STATUS_NO_SUCH_DEVICE 0x08
+#define SD_CARD_STATUS_INVALID_DEVICE_REQUEST 0x09
+#define SD_CARD_STATUS_NO_MEMORY 0x0A
+#define SD_CARD_STATUS_BUS_DRIVER_NOT_READY 0x0B
+#define SD_CARD_STATUS_DATA_ERROR 0x0C
+#define SD_CARD_STATUS_CRC_ERROR 0x0D
+#define SD_CARD_STATUS_INSUFFICIENT_RESOURCES 0x0E
+#define SD_CARD_STATUS_DEVICE_NOT_CONNECTED 0x10
+#define SD_CARD_STATUS_DEVICE_REMOVED 0x11
+#define SD_CARD_STATUS_DEVICE_NOT_RESPONDING 0x12
+#define SD_CARD_STATUS_CANCELED 0x13
+#define SD_CARD_STATUS_RESPONSE_TIMEOUT 0x14
+#define SD_CARD_STATUS_DATA_TIMEOUT 0x15
+#define SD_CARD_STATUS_DEVICE_RESPONSE_ERROR 0x16
+#define SD_CARD_STATUS_DEVICE_UNSUPPORTED 0x17
+
+/* Response structure */
+struct sd_r2_resp {
+ uint32_t rsp4; /* 127:96 */
+ uint32_t rsp3; /* 95:64 */
+ uint32_t rsp2; /* 63:32 */
+ uint32_t rsp1; /* 31:0 */
+};
+
+struct sd_r3_resp {
+ uint32_t ocr;
+};
+
+struct sd_r4_resp {
+ uint8_t cardReady;
+ uint8_t funcs;
+ uint8_t memPresent;
+ uint32_t ocr;
+};
+
+struct sd_r5_resp {
+ uint8_t data;
+};
+
+struct sd_r6_resp {
+ uint16_t rca;
+ uint16_t cardStatus;
+};
+
+struct sd_r7_resp {
+ uint16_t rca;
+};
+
+struct sd_resp {
+ uint8_t r1;
+ uint32_t cardStatus;
+ uint32_t rawData[4];
+ union {
+ struct sd_r2_resp r2;
+ struct sd_r3_resp r3;
+ struct sd_r4_resp r4;
+ struct sd_r5_resp r5;
+ struct sd_r6_resp r6;
+ struct sd_r7_resp r7;
+ } data;
+};
+
+struct sd_card_info {
+ uint32_t type; /* card type SD, MMC or SDIO */
+ uint64_t size; /* card size */
+ uint32_t speed; /* card speed */
+ uint32_t voltage; /* voltage supported */
+ uint32_t mId; /* manufacturer ID */
+ uint32_t oId; /* OEM ID */
+ uint32_t classes; /* card class */
+ uint32_t name1; /* product name part 1 */
+ uint32_t name2; /* product name part 2 */
+ uint32_t revision; /* revison */
+ uint32_t sn; /* serial number */
+ uint32_t numIoFuns; /* total I/O function number */
+ uint32_t maxRdBlkLen; /* max read block length */
+ uint32_t maxWtBlkLen; /* max write block length */
+ uint32_t blkMode; /* sdio card block mode support */
+ uint32_t f0Cis; /* sdio card block mode support */
+ uint32_t f1Cis; /* sdio card block mode support */
+
+ uint8_t partRead; /* partial block read allowed */
+ uint8_t partWrite; /* partial block write allowed */
+ uint8_t dsr; /* card DSR */
+ uint8_t rdCurMin; /* min current for read */
+ uint8_t rdCurMax; /* max current for read */
+ uint8_t wtCurMin; /* min current for write */
+ uint8_t wtCurMax; /* max current for write */
+ uint8_t erase; /* erase enable */
+ uint8_t eraseSecSize; /* erase sector size */
+ uint8_t proGrpSize; /* write protection group size */
+ uint8_t protect; /* permanent write protection or not */
+ uint8_t tmpProt; /* temp write protection or not */
+ uint8_t wtSpeed; /* write speed relatively to read */
+ uint8_t version; /* card version 0:1.0 - 1.01, 1:1.10, 2:2.0 */
+ uint8_t eraseState; /* if the data will be 0 or 1 after erase */
+ uint8_t bus; /* data with supported */
+ uint8_t security; /* security support 0, 2:1.01 3:2.0 */
+ uint8_t format; /* file format */
+ uint8_t fileGrp; /* file group */
+ char pwd[20]; /* password */
+};
+
+struct sd_handle {
+ struct sd_dev *device;
+ struct sd_card_info *card;
+};
+
+int sd_cmd0(struct sd_handle *handle);
+int sd_cmd1(struct sd_handle *handle, uint32_t initOcr, uint32_t *ocr);
+int sd_cmd2(struct sd_handle *handle);
+int sd_cmd3(struct sd_handle *handle);
+int sd_cmd7(struct sd_handle *handle, uint32_t rca);
+int sd_cmd9(struct sd_handle *handle, struct sd_card_data *card);
+int sd_cmd13(struct sd_handle *handle, uint32_t *status);
+int sd_cmd16(struct sd_handle *handle, uint32_t blockLen);
+int sd_cmd17(struct sd_handle *handle,
+ uint32_t addr, uint32_t len, uint8_t *buffer);
+int sd_cmd18(struct sd_handle *handle,
+ uint32_t addr, uint32_t len, uint8_t *buffer);
+#ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
+int sd_cmd24(struct sd_handle *handle,
+ uint32_t addr, uint32_t len, uint8_t *buffer);
+int sd_cmd25(struct sd_handle *handle,
+ uint32_t addr, uint32_t len, uint8_t *buffer);
+#endif
+#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
+int sd_cmd35(struct sd_handle *handle, uint32_t start);
+int sd_cmd36(struct sd_handle *handle, uint32_t end);
+int sd_cmd38(struct sd_handle *handle);
+#endif
+int mmc_cmd6(struct sd_handle *handle, uint32_t argument);
+int mmc_cmd8(struct sd_handle *handle, uint8_t *extCsdReg);
+
+int send_cmd(struct sd_handle *handle, uint32_t cmdIndex,
+ uint32_t argument, uint32_t options, struct sd_resp *resp);
+#endif /* CSL_SD_CMD_H */
diff --git a/include/drivers/brcm/emmc/emmc_csl_sdprot.h b/include/drivers/brcm/emmc/emmc_csl_sdprot.h
new file mode 100644
index 0000000..597e1e0
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_csl_sdprot.h
@@ -0,0 +1,435 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CSL_SD_PROT_H
+#define CSL_SD_PROT_H
+
+#define SD_CARD_UNKNOWN 0 /* bad type or unrecognized */
+#define SD_CARD_SD 1 /* IO only card */
+#define SD_CARD_SDIO 2 /* memory only card */
+#define SD_CARD_COMBO 3 /* IO and memory combo card */
+#define SD_CARD_MMC 4 /* memory only card */
+#define SD_CARD_CEATA 5 /* IO and memory combo card */
+
+#define SD_IO_FIXED_ADDRESS 0 /* fix Address */
+#define SD_IO_INCREMENT_ADDRESS 1
+
+#define SD_HIGH_CAPACITY_CARD 0x40000000
+
+#define MMC_CMD_IDLE_RESET_ARG 0xF0F0F0F0
+
+/* Supported operating voltages are 3.2-3.3 and 3.3-3.4 */
+#define MMC_OCR_OP_VOLT 0x00300000
+/* Enable sector access mode */
+#define MMC_OCR_SECTOR_ACCESS_MODE 0x40000000
+
+/* command index */
+#define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */
+#define SD_CMD_SEND_OPCOND 1
+#define SD_CMD_ALL_SEND_CID 2
+#define SD_CMD_MMC_SET_RCA 3
+#define SD_CMD_MMC_SET_DSR 4
+#define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */
+#define SD_ACMD_SET_BUS_WIDTH 6
+#define SD_CMD_SWITCH_FUNC 6
+#define SD_CMD_SELECT_DESELECT_CARD 7
+#define SD_CMD_READ_EXT_CSD 8
+#define SD_CMD_SEND_CSD 9
+#define SD_CMD_SEND_CID 10
+#define SD_CMD_STOP_TRANSMISSION 12
+#define SD_CMD_SEND_STATUS 13
+#define SD_ACMD_SD_STATUS 13
+#define SD_CMD_GO_INACTIVE_STATE 15
+#define SD_CMD_SET_BLOCKLEN 16
+#define SD_CMD_READ_SINGLE_BLOCK 17
+#define SD_CMD_READ_MULTIPLE_BLOCK 18
+#define SD_CMD_WRITE_BLOCK 24
+#define SD_CMD_WRITE_MULTIPLE_BLOCK 25
+#define SD_CMD_PROGRAM_CSD 27
+#define SD_CMD_SET_WRITE_PROT 28
+#define SD_CMD_CLR_WRITE_PROT 29
+#define SD_CMD_SEND_WRITE_PROT 30
+#define SD_CMD_ERASE_WR_BLK_START 32
+#define SD_CMD_ERASE_WR_BLK_END 33
+#define SD_CMD_ERASE_GROUP_START 35
+#define SD_CMD_ERASE_GROUP_END 36
+#define SD_CMD_ERASE 38
+#define SD_CMD_LOCK_UNLOCK 42
+#define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */
+#define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */
+#define SD_CMD_APP_CMD 55
+#define SD_CMD_GEN_CMD 56
+#define SD_CMD_READ_OCR 58
+#define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */
+#define SD_ACMD_SEND_NUM_WR_BLOCKS 22
+#define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23
+#define SD_ACMD_SD_SEND_OP_COND 41
+#define SD_ACMD_SET_CLR_CARD_DETECT 42
+#define SD_ACMD_SEND_SCR 51
+
+/* response parameters */
+#define SD_RSP_NO_NONE 0
+#define SD_RSP_NO_1 1
+#define SD_RSP_NO_2 2
+#define SD_RSP_NO_3 3
+#define SD_RSP_NO_4 4
+#define SD_RSP_NO_5 5
+#define SD_RSP_NO_6 6
+
+/* Modified R6 response (to CMD3) */
+#define SD_RSP_MR6_COM_CRC_ERROR 0x8000
+#define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000
+#define SD_RSP_MR6_ERROR 0x2000
+
+/* Modified R1 in R4 Response (to CMD5) */
+#define SD_RSP_MR1_SBIT 0x80
+#define SD_RSP_MR1_PARAMETER_ERROR 0x40
+#define SD_RSP_MR1_RFU5 0x20
+#define SD_RSP_MR1_FUNC_NUM_ERROR 0x10
+#define SD_RSP_MR1_COM_CRC_ERROR 0x80
+#define SD_RSP_MR1_ILLEGAL_COMMAND 0x40
+#define SD_RSP_MR1_RFU1 0x20
+#define SD_RSP_MR1_IDLE_STATE 0x01
+
+/* R5 response (to CMD52 and CMD53) */
+#define SD_RSP_R5_COM_CRC_ERROR 0x80
+#define SD_RSP_R5_ILLEGAL_COMMAND 0x40
+#define SD_RSP_R5_IO_CURRENTSTATE1 0x20
+#define SD_RSP_R5_IO_CURRENTSTATE0 0x10
+#define SD_RSP_R5_ERROR 0x80
+#define SD_RSP_R5_RFU 0x40
+#define SD_RSP_R5_FUNC_NUM_ERROR 0x20
+#define SD_RSP_R5_OUT_OF_RANGE 0x01
+
+/* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */
+#define SD_OP_READ 0 /* Read_Write */
+#define SD_OP_WRITE 1 /* Read_Write */
+
+#define SD_RW_NORMAL 0 /* no RAW */
+#define SD_RW_RAW 1 /* RAW */
+
+#define SD_BYTE_MODE 0 /* Byte Mode */
+#define SD_BLOCK_MODE 1 /* BlockMode */
+
+#define SD_FIXED_ADDRESS 0 /* fix Address */
+#define SD_INCREMENT_ADDRESS 1 /* IncrementAddress */
+
+#define SD_CMD5_ARG_IO_OCR_MASK 0x00FFFFFF
+#define SD_CMD5_ARG_IO_OCR_SHIFT 0
+#define SD_CMD55_ARG_RCA_SHIFT 16
+#define SD_CMD59_ARG_CRC_OPTION_MASK 0x01
+#define SD_CMD59_ARG_CRC_OPTION_SHIFT 0
+
+/* SD_CMD_IO_RW_DIRECT Argument */
+#define SdioIoRWDirectArg(rw, raw, func, addr, data) \
+ (((rw & 1) << 31) | ((func & 0x7) << 28) | \
+ ((raw & 1) << 27) | ((addr & 0x1FFFF) << 9) | \
+ (data & 0xFF))
+
+/* build SD_CMD_IO_RW_EXTENDED Argument */
+#define SdioIoRWExtArg(rw, blk, func, addr, inc_addr, count) \
+ (((rw & 1) << 31) | ((func & 0x7) << 28) | \
+ ((blk & 1) << 27) | ((inc_addr & 1) << 26) | \
+ ((addr & 0x1FFFF) << 9) | (count & 0x1FF))
+
+/*
+ * The Common I/O area shall be implemented on all SDIO cards and
+ * is accessed the the host via I/O reads and writes to function 0,
+ * the registers within the CIA are provided to enable/disable
+ * the operationo fthe i/o funciton.
+ */
+
+/* cccr_sdio_rev */
+#define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */
+#define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */
+
+/* sd_rev */
+#define SDIO_REV_PHY_MASK 0x0f /* SD format version number */
+#define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */
+#define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */
+#define SDIO_INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */
+#define SDIO_INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */
+#define SDIO_INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */
+#define SDIO_IO_ABORT_RESET_ALL 0x08 /* I/O card reset */
+#define SDIO_IO_ABORT_FUNC_MASK 0x07 /* abort selection: function x */
+#define SDIO_BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */
+#define SDIO_BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */
+#define SDIO_BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */
+#define SDIO_BUS_DATA_WIDTH_MASK 0x03 /* bus width mask */
+#define SDIO_BUS_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */
+#define SDIO_BUS_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */
+
+/* capability */
+#define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */
+#define SDIO_CAP_LSC 0x40 /* low speed card */
+#define SDIO_CAP_E4MI 0x20 /* enable int between block in 4-bit mode */
+#define SDIO_CAP_S4MI 0x10 /* support int between block in 4-bit mode */
+#define SDIO_CAP_SBS 0x08 /* support suspend/resume */
+#define SDIO_CAP_SRW 0x04 /* support read wait */
+#define SDIO_CAP_SMB 0x02 /* support multi-block transfer */
+#define SDIO_CAP_SDC 0x01 /* Support Direct cmd during multi-uint8 transfer */
+
+/* CIA FBR1 registers */
+#define SDIO_FUNC1_INFO 0x100 /* basic info for function 1 */
+#define SDIO_FUNC1_EXT 0x101 /* extension of standard I/O device */
+#define SDIO_CIS_FUNC1_BASE_LOW 0x109 /* function 1 cis address bit 0-7 */
+#define SDIO_CIS_FUNC1_BASE_MID 0x10A /* function 1 cis address bit 8-15 */
+#define SDIO_CIS_FUNC1_BASE_HIGH 0x10B /* function 1 cis address bit 16 */
+#define SDIO_CSA_BASE_LOW 0x10C /* CSA base address uint8_t 0 */
+#define SDIO_CSA_BASE_MID 0x10D /* CSA base address uint8_t 1 */
+#define SDIO_CSA_BASE_HIGH 0x10E /* CSA base address uint8_t 2 */
+#define SDIO_CSA_DATA_OFFSET 0x10F /* CSA data register */
+#define SDIO_IO_BLK_SIZE_LOW 0x110 /* I/O block size uint8_t 0 */
+#define SDIO_IO_BLK_SIZE_HIGH 0x111 /* I/O block size uint8_t 1 */
+
+/* SD_SDIO_FUNC1_INFO bits */
+#define SDIO_FUNC1_INFO_DIC 0x0f /* device interface code */
+#define SDIO_FUNC1_INFO_CSA 0x40 /* CSA support flag */
+#define SDIO_FUNC1_INFO_CSA_EN 0x80 /* CSA enabled */
+
+/* SD_SDIO_FUNC1_EXT bits */
+#define SDIO_FUNC1_EXT_SHP 0x03 /* support high power */
+#define SDIO_FUNC1_EXT_EHP 0x04 /* enable high power */
+
+/* devctr */
+/* I/O device interface code */
+#define SDIO_DEVCTR_DEVINTER 0x0f
+/* support CSA */
+#define SDIO_DEVCTR_CSA_SUP 0x40
+/* enable CSA */
+#define SDIO_DEVCTR_CSA_EN 0x80
+
+/* ext_dev */
+/* supports high-power mask */
+#define SDIO_HIGHPWR_SUPPORT_M 0x3
+/* enable high power */
+#define SDIO_HIGHPWR_EN 0x4
+/* standard power function(up to 200mA */
+#define SDIO_HP_STD 0
+/* need high power to operate */
+#define SDIO_HP_REQUIRED 0x2
+/* can work with standard power, but prefer high power */
+#define SDIO_HP_DESIRED 0x3
+
+/* misc define */
+/* macro to calculate fbr register base */
+#define FBR_REG_BASE(n) (n*0x100)
+#define SDIO_FUNC_0 0
+#define SDIO_FUNC_1 1
+#define SDIO_FUNC_2 2
+#define SDIO_FUNC_3 3
+#define SDIO_FUNC_4 4
+#define SDIO_FUNC_5 5
+#define SDIO_FUNC_6 6
+#define SDIO_FUNC_7 7
+
+/* maximum block size for block mode operation */
+#define SDIO_MAX_BLOCK_SIZE 2048
+/* minimum block size for block mode operation */
+#define SDIO_MIN_BLOCK_SIZE 1
+
+/* Card registers: status bit position */
+#define SDIO_STATUS_OUTOFRANGE 31
+#define SDIO_STATUS_COMCRCERROR 23
+#define SDIO_STATUS_ILLEGALCOMMAND 22
+#define SDIO_STATUS_ERROR 19
+#define SDIO_STATUS_IOCURRENTSTATE3 12
+#define SDIO_STATUS_IOCURRENTSTATE2 11
+#define SDIO_STATUS_IOCURRENTSTATE1 10
+#define SDIO_STATUS_IOCURRENTSTATE0 9
+#define SDIO_STATUS_FUN_NUM_ERROR 4
+
+#define GET_SDIOCARD_STATUS(x) ((x >> 9) & 0x0f)
+#define SDIO_STATUS_STATE_IDLE 0
+#define SDIO_STATUS_STATE_READY 1
+#define SDIO_STATUS_STATE_IDENT 2
+#define SDIO_STATUS_STATE_STBY 3
+#define SDIO_STATUS_STATE_TRAN 4
+#define SDIO_STATUS_STATE_DATA 5
+#define SDIO_STATUS_STATE_RCV 6
+#define SDIO_STATUS_STATE_PRG 7
+#define SDIO_STATUS_STATE_DIS 8
+
+/* sprom */
+#define SBSDIO_SPROM_CS 0x10000 /* command and status */
+#define SBSDIO_SPROM_INFO 0x10001 /* info register */
+#define SBSDIO_SPROM_DATA_LOW 0x10002 /* indirect access data uint8_t 0 */
+#define SBSDIO_SPROM_DATA_HIGH 0x10003 /* indirect access data uint8_t 1 */
+#define SBSDIO_SPROM_ADDR_LOW 0x10004 /* indirect access addr uint8_t 0 */
+#define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* indirect access addr uint8_t 0 */
+#define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu data output */
+#define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu enable */
+#define SBSDIO_WATERMARK 0x10008 /* retired in rev 7 */
+#define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */
+
+#define SBSDIO_SPROM_IDLE 0
+#define SBSDIO_SPROM_WRITE 1
+#define SBSDIO_SPROM_READ 2
+#define SBSDIO_SPROM_WEN 4
+#define SBSDIO_SPROM_WDS 7
+#define SBSDIO_SPROM_DONE 8
+
+/* SBSDIO_SPROM_INFO */
+#define SBSDIO_SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */
+#define SBSDIO_SROM_BLANK 0x04 /* depreciated in corerev 6 */
+#define SBSDIO_SROM_OTP 0x80 /* OTP present */
+
+/* SBSDIO_CHIP_CTRL */
+/* or'd with onchip xtal_pu, 1: power on oscillator */
+#define SBSDIO_CHIP_CTRL_XTAL 0x01
+
+/* SBSDIO_WATERMARK */
+/* number of bytes minus 1 for sd device to wait before sending data to host */
+#define SBSDIO_WATERMARK_MASK 0x3f
+
+/* SBSDIO_DEVICE_CTL */
+/* 1: device will assert busy signal when receiving CMD53 */
+#define SBSDIO_DEVCTL_SETBUSY 0x01
+/* 1: assertion of sdio interrupt is synchronous to the sdio clock */
+#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
+
+/* function 1 OCP space */
+/* sb offset addr is <= 15 bits, 32k */
+#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF
+#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
+/* sdsdio function 1 OCP space has 16/32 bit section */
+#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000
+
+/* direct(mapped) cis space */
+/* MAPPED common CIS address */
+#define SBSDIO_CIS_BASE_COMMON 0x1000
+/* function 0(common) cis size in bytes */
+#define SBSDIO_CIS_FUNC0_LIMIT 0x020
+/* funciton 1 cis size in bytes */
+#define SBSDIO_CIS_SIZE_LIMIT 0x200
+/* cis offset addr is < 17 bits */
+#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
+/* manfid tuple length, include tuple, link bytes */
+#define SBSDIO_CIS_MANFID_TUPLE_LEN 6
+
+/* indirect cis access (in sprom) */
+/* 8 control bytes first, CIS starts from 8th uint8_t */
+#define SBSDIO_SPROM_CIS_OFFSET 0x8
+/* sdio uint8_t mode: maximum length of one data comamnd */
+#define SBSDIO_BYTEMODE_DATALEN_MAX 64
+/* 4317 supports less */
+#define SBSDIO_BYTEMODE_DATALEN_MAX_4317 52
+/* sdio core function one address mask */
+#define SBSDIO_CORE_ADDR_MASK 0x1FFFF
+
+/* CEATA defines */
+#define CEATA_EXT_CSDBLOCK_SIZE 512
+#define CEATA_FAST_IO 39
+#define CEATA_MULTIPLE_REGISTER_RW 60
+#define CEATA_MULTIPLE_BLOCK_RW 61
+
+/* defines CE ATA task file registers */
+#define CEATA_SCT_CNT_EXP_REG 0x02
+#define CEATA_LBA_LOW_EXP_REG 0x03
+#define CEATA_LBA_MID_EXP_REG 0x04
+#define CEATA_LBA_HIGH_EXP_REG 0x05
+#define CEATA_CNTRL_REG 0x06
+#define CEATA_FEATURE_REG 0x09 /* write */
+#define CEATA_ERROR_REG 0x09 /* read */
+#define CEATA_SCT_CNT_REG 0x0A
+#define CEATA_LBA_LOW_REG 0x0B
+#define CEATA_LBA_MID_REG 0x0C
+#define CEATA_LBA_HIGH_REG 0x0D
+#define CEATA_DEV_HEAD_REG 0x0E
+#define CEATA_STA_REG 0x0F /* read */
+#define CEATA_CMD_REG 0x0F /* write */
+
+/* defines CEATA control and status registers for ce ata client driver */
+#define CEATA_SCR_TEMPC_REG 0x80
+#define CEATA_SCR_TEMPMAXP_REG 0x84
+#define CEATA_TEMPMINP_REG 0x88
+#define CEATA_SCR_STATUS_REG 0x8C
+#define CEATA_SCR_REALLOCSA_REG 0x90
+#define CEATA_SCR_ERETRACTSA_REG 0x94
+#define CEATA_SCR_CAPABILITIES_REG 0x98
+#define CEATA_SCR_CONTROL_REG 0xC0
+
+/* defines for SCR capabilities register bits for ce ata client driver */
+#define CEATA_SCR_CAP_512 0x00000001
+#define CEATA_SCR_CAP_1K 0x00000002
+#define CEATA_SCR_CAP_4K 0x00000004
+
+/* defines CE ATA Control reg bits for ce ata client driver */
+#define CEATA_CNTRL_ENABLE_INTR 0x00
+#define CEATA_CNTRL_DISABLE_INTR 0x02
+#define CEATA_CNTRL_SRST 0x04
+#define CEATA_CNTRL_RSRST 0x00
+
+/* define CE ATA Status reg bits for ce ata client driver */
+#define CEATA_STA_ERROR_BIT 0x01
+#define CEATA_STA_OVR_BIT 0x02
+#define CEATA_STA_SPT_BIT 0x04
+#define CEATA_STA_DRQ_BIT 0x08
+#define CEATA_STA_DRDY_BIT 0x40
+#define CEATA_STA_BSY_BIT 0x80
+
+/* define CE ATA Error reg bits for ce ata client driver */
+#define CEATA_ERROR_ABORTED_BIT 0x04
+#define CEATA_ERROR_IDNF_BIT 0x10
+#define CEATA_ERROR_UNCORRECTABLE_BIT 0x40
+#define CEATA_ERROR_ICRC_BIT 0x80
+
+/* define CE ATA Commands for ce ata client driver */
+#define CEATA_CMD_IDENTIFY_DEVICE 0xEC
+#define CEATA_CMD_READ_DMA_EXT 0x25
+#define CEATA_CMD_WRITE_DMA_EXT 0x35
+#define CEATA_CMD_STANDBY_IMMEDIATE 0xE0
+#define CEATA_CMD_FLUSH_CACHE_EXT 0xEA
+
+struct csd_mmc {
+ uint32_t padding:8;
+ uint32_t structure:2;
+ uint32_t csdSpecVer:4;
+ uint32_t reserved1:2;
+ uint32_t taac:8;
+ uint32_t nsac:8;
+ uint32_t speed:8;
+ uint32_t classes:12;
+ uint32_t rdBlkLen:4;
+ uint32_t rdBlkPartial:1;
+ uint32_t wrBlkMisalign:1;
+ uint32_t rdBlkMisalign:1;
+ uint32_t dsr:1;
+ uint32_t reserved2:2;
+ uint32_t size:12;
+ uint32_t vddRdCurrMin:3;
+ uint32_t vddRdCurrMax:3;
+ uint32_t vddWrCurrMin:3;
+ uint32_t vddWrCurrMax:3;
+ uint32_t devSizeMulti:3;
+ uint32_t eraseGrpSize:5;
+ uint32_t eraseGrpSizeMulti:5;
+ uint32_t wrProtGroupSize:5;
+ uint32_t wrProtGroupEnable:1;
+ uint32_t manuDefEcc:2;
+ uint32_t wrSpeedFactor:3;
+ uint32_t wrBlkLen:4;
+ uint32_t wrBlkPartial:1;
+ uint32_t reserved5:4;
+ uint32_t protAppl:1;
+ uint32_t fileFormatGrp:1;
+ uint32_t copyFlag:1;
+ uint32_t permWrProt:1;
+ uint32_t tmpWrProt:1;
+ uint32_t fileFormat:2;
+ uint32_t eccCode:2;
+};
+
+/* CSD register*/
+union sd_csd {
+ uint32_t csd[4];
+ struct csd_mmc mmc;
+};
+
+struct sd_card_data {
+ union sd_csd csd;
+};
+#endif /* CSL_SD_PROT_H */
diff --git a/include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h b/include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h
new file mode 100644
index 0000000..8e61b51
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PBOOT_HAL_MEMORY_EMMC_DRV_H
+#define PBOOT_HAL_MEMORY_EMMC_DRV_H
+
+#include <drivers/delay_timer.h>
+
+#include "emmc_chal_types.h"
+#include "emmc_chal_sd.h"
+#include "emmc_csl_sdprot.h"
+#include "emmc_csl_sdcmd.h"
+#include "emmc_csl_sd.h"
+#include "emmc_brcm_rdb_sd4_top.h"
+
+#define CLK_SDIO_DIV_52MHZ 0x0
+#define SYSCFG_IOCR4_PAD_10MA 0x38000000
+
+#define SDCLK_CNT_PER_MS 52000
+#define BOOT_ACK_TIMEOUT (50 * SDCLK_CNT_PER_MS)
+#define BOOT_DATA_TIMEOUT (1000 * SDCLK_CNT_PER_MS)
+
+#define EMMC_BOOT_OK 0
+#define EMMC_BOOT_ERROR 1
+#define EMMC_BOOT_TIMEOUT 2
+#define EMMC_BOOT_INVALIDIMAGE 3
+#define EMMC_BOOT_NO_CARD 4
+
+#define EMMC_USER_AREA 0
+#define EMMC_BOOT_PARTITION1 1
+#define EMMC_BOOT_PARTITION2 2
+#define EMMC_USE_CURRENT_PARTITION 3
+
+#define EMMC_BOOT_PARTITION_SIZE (128*1024)
+#define EMMC_BLOCK_SIZE 512
+#define EMMC_DMA_SIZE (4*1024)
+
+/*
+ * EMMC4.3 definitions
+ * Table 6 EXT_CSD access mode
+ * Access
+ * Bits Access Name Operation
+ * 00 Command Set The command set is changed according to the Cmd Set field of
+ * the argument
+ * 01 Set Bits The bits in the pointed uint8_t are set,
+ * according to the 1 bits in the Value field.
+ * 10 Clear Bits The bits in the pointed uint8_t are cleared,
+ * according to the 1 bits in the Value field.
+ * 11 Write Byte The Value field is written into the pointed uint8_t.
+ */
+
+#define SDIO_HW_EMMC_EXT_CSD_WRITE_BYTE 0X03000000
+
+/* Boot bus width1 BOOT_BUS_WIDTH 1 R/W [177] */
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_BUS_WIDTH_OFFSET 0X00B10000
+
+/* Boot configuration BOOT_CONFIG 1 R/W [179] */
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_CONFIG_OFFSET 0X00B30000
+
+/* Bus width mode BUS_WIDTH 1 WO [183] */
+#define SDIO_HW_EMMC_EXT_CSD_BUS_WIDTH_OFFSET 0X00B70000
+
+/*
+ * Bit 6: BOOT_ACK (non-volatile)
+ * 0x0 : No boot acknowledge sent (default)
+ * 0x1 : Boot acknowledge sent during boot operation
+ * Bit[5:3] : BOOT_PARTITION_ENABLE (non-volatile)
+ * User selects boot data that will be sent to master
+ * 0x0 : Device not boot enabled (default)
+ * 0x1 : Boot partition 1 enabled for boot
+ * 0x2 : Boot partition 2 enabled for boot
+ * 0x3-0x6 : Reserved
+ * 0x7 : User area enabled for boot
+ * Bit[2:0] : BOOT_PARTITION_ACCESS
+ * User selects boot partition for read and write operation
+ * 0x0 : No access to boot partition (default)
+ * 0x1 : R/W boot partition 1
+ * 0x2 : R/W boot partition 2
+ * 0x3-0x7 : Reserved
+ */
+
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_BOOT1 0X00000100
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_BOOT2 0X00000200
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_USER 0X00000000
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_EN_BOOT1 0X00004800
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_EN_BOOT2 0X00005000
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_EN_USER 0X00007800
+
+#define SD_US_DELAY(x) udelay(x)
+
+#endif
diff --git a/include/drivers/brcm/fru.h b/include/drivers/brcm/fru.h
new file mode 100644
index 0000000..ee863b4
--- /dev/null
+++ b/include/drivers/brcm/fru.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2019-2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FRU_H
+#define FRU_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/* max string length */
+#define FRU_MAX_STR_LEN 32
+
+/* max number of DDR channels */
+#define BCM_MAX_NR_DDR 3
+
+/* max supported FRU table size */
+#define BCM_MAX_FRU_LEN 512
+
+/* FRU table starting offset */
+#define BCM_FRU_TBL_OFFSET 0x300000
+
+/* FRU time constants */
+#define MINS_PER_DAY 1440
+#define MINS_PER_HOUR 60
+#define FRU_YEAR_START 1996
+#define FRU_MONTH_START 1
+#define FRU_DAY_START 1
+#define MONTHS_PER_YEAR 12
+
+/*
+ * FRU areas based on the spec
+ */
+enum fru_area_name {
+ FRU_AREA_INTERNAL = 0,
+ FRU_AREA_CHASSIS_INFO,
+ FRU_AREA_BOARD_INFO,
+ FRU_AREA_PRODUCT_INFO,
+ FRU_AREA_MRECORD_INFO,
+ FRU_MAX_NR_AREAS
+};
+
+/*
+ * FRU area information
+ *
+ * @use: indicate this area is being used
+ * @version: format version
+ * @offset: offset of this area from the beginning of the FRU table
+ * @len: total length of the area
+ */
+struct fru_area_info {
+ bool use;
+ uint8_t version;
+ unsigned int offset;
+ unsigned int len;
+};
+
+/*
+ * DDR MCB information
+ *
+ * @idx: DDR channel index
+ * @size_mb: DDR size of this channel in MB
+ * @ref_id: DDR MCB reference ID
+ */
+struct ddr_mcb {
+ unsigned int idx;
+ unsigned int size_mb;
+ uint32_t ref_id;
+};
+
+/*
+ * DDR information
+ *
+ * @ddr_info: array that contains MCB related info for each channel
+ */
+struct ddr_info {
+ struct ddr_mcb mcb[BCM_MAX_NR_DDR];
+};
+
+/*
+ * FRU board area information
+ *
+ * @lang: Language code
+ * @mfg_date: Manufacturing date
+ * @manufacturer: Manufacturer
+ * @product_name: Product name
+ * @serial_number: Serial number
+ * @part_number: Part number
+ * @file_id: FRU file ID
+ */
+struct fru_board_info {
+ unsigned char lang;
+ unsigned int mfg_date;
+ unsigned char manufacturer[FRU_MAX_STR_LEN];
+ unsigned char product_name[FRU_MAX_STR_LEN];
+ unsigned char serial_number[FRU_MAX_STR_LEN];
+ unsigned char part_number[FRU_MAX_STR_LEN];
+ unsigned char file_id[FRU_MAX_STR_LEN];
+};
+
+/*
+ * FRU manufacture date in human readable format
+ */
+struct fru_time {
+ unsigned int min;
+ unsigned int hour;
+ unsigned int day;
+ unsigned int month;
+ unsigned int year;
+};
+
+#ifdef USE_FRU
+int fru_validate(uint8_t *data, struct fru_area_info *fru_area);
+int fru_parse_ddr(uint8_t *data, struct fru_area_info *area,
+ struct ddr_info *ddr);
+int fru_parse_board(uint8_t *data, struct fru_area_info *area,
+ struct fru_board_info *board);
+void fru_format_time(unsigned int min, struct fru_time *tm);
+#else
+static inline int fru_validate(uint8_t *data, struct fru_area_info *fru_area)
+{
+ return -1;
+}
+
+static inline int fru_parse_ddr(uint8_t *data, struct fru_area_info *area,
+ struct ddr_info *ddr)
+{
+ return -1;
+}
+
+static inline int fru_parse_board(uint8_t *data, struct fru_area_info *area,
+ struct fru_board_info *board)
+{
+ return -1;
+}
+
+static inline void fru_format_time(unsigned int min, struct fru_time *tm)
+{
+}
+#endif /* USE_FRU */
+
+#endif /* FRU_H */
diff --git a/include/drivers/brcm/i2c/i2c.h b/include/drivers/brcm/i2c/i2c.h
new file mode 100644
index 0000000..24d42e2
--- /dev/null
+++ b/include/drivers/brcm/i2c/i2c.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2016 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef I2C_H
+#define I2C_H
+
+#include <stdint.h>
+
+#define I2C_SPEED_100KHz 100000
+#define I2C_SPEED_400KHz 400000
+#define I2C_SPEED_DEFAULT I2C_SPEED_100KHz
+
+/*
+ * Function Name: i2c_probe
+ *
+ * Description:
+ * This function probes the I2C bus for the existence of the specified
+ * device.
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * devaddr - Device Address
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_probe(uint32_t bus_id, uint8_t devaddr);
+
+/*
+ * Function Name: i2c_init
+ *
+ * Description:
+ * This function initializes the SMBUS.
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * speed - I2C bus speed in Hz
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_init(uint32_t bus_id, int speed);
+
+/*
+ * Function Name: i2c_set_bus_speed
+ *
+ * Description:
+ * This function configures the SMBUS speed
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * speed - I2C bus speed in Hz
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_set_bus_speed(uint32_t bus_id, uint32_t speed);
+
+/*
+ * Function Name: i2c_get_bus_speed
+ *
+ * Description:
+ * This function returns the SMBUS speed.
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ *
+ * Return:
+ * Bus speed in Hz, 0 on failure
+ */
+uint32_t i2c_get_bus_speed(uint32_t bus_id);
+
+/*
+ * Function Name: i2c_recv_byte
+ *
+ * Description:
+ * This function reads I2C data from a device without specifying
+ * a command regsiter.
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * devaddr - Device Address
+ * value - Data Read
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_recv_byte(uint32_t bus_id, uint8_t devaddr, uint8_t *value);
+
+/*
+ * Function Name: i2c_send_byte
+ *
+ * Description:
+ * This function send I2C data to a device without specifying
+ * a command regsiter.
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * devaddr - Device Address
+ * value - Data Send
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_send_byte(uint32_t bus_id, uint8_t devaddr, uint8_t value);
+
+/*
+ * Function Name: i2c_read
+ *
+ * Description:
+ * This function reads I2C data from a device with a designated
+ * command register
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * devaddr - Device Address
+ * addr - Register Offset
+ * alen - Address Length, 1 for byte, 2 for word (not supported)
+ * buffer - Data Buffer
+ * len - Data Length in bytes
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_read(uint32_t bus_id,
+ uint8_t devaddr,
+ uint32_t addr,
+ int alen,
+ uint8_t *buffer,
+ int len);
+
+/*
+ * Function Name: i2c_write
+ *
+ * Description:
+ * This function write I2C data to a device with a designated
+ * command register
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * devaddr - Device Address
+ * addr - Register Offset
+ * alen - Address Length, 1 for byte, 2 for word (not supported)
+ * buffer - Data Buffer
+ * len - Data Length in bytes
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_write(uint32_t bus_id,
+ uint8_t devaddr,
+ uint32_t addr,
+ int alen,
+ uint8_t *buffer,
+ int len);
+
+
+#endif /* I2C_H */
diff --git a/include/drivers/brcm/i2c/i2c_regs.h b/include/drivers/brcm/i2c/i2c_regs.h
new file mode 100644
index 0000000..74ea824
--- /dev/null
+++ b/include/drivers/brcm/i2c/i2c_regs.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2016 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef I2C_REGS
+#define I2C_REGS
+
+/* SMBUS Config register */
+#define SMB_CFG_REG 0x0U
+
+#define SMB_CFG_RST_MASK 0x80000000U
+#define SMB_CFG_RST_SHIFT 31U
+
+#define SMB_CFG_SMBEN_MASK 0x40000000U
+#define SMB_CFG_SMBEN_SHIFT 30U
+
+#define SMB_CFG_BITBANGEN_MASK 0x20000000U
+#define SMB_CFG_BITBANGEN_SHIFT 29U
+
+#define SMB_CFG_EN_NIC_SMBADDR0_MASK 0x10000000U
+#define SMB_CFG_EN_NIC_SMBADDR0_SHIFT 28U
+
+#define SMB_CFG_PROMISCMODE_MASK 0x08000000U
+#define SMB_CFG_PROMISCMODE_SHIFT 27U
+
+#define SMB_CFG_TSTMPCNTEN_MASK 0x04000000U
+#define SMB_CFG_TSTMPCNTEN_SHIFT 26U
+
+#define SMB_CFG_MSTRRTRYCNT_MASK 0x000F0000U
+#define SMB_CFG_MSTRRTRYCNT_SHIFT 16U
+
+/* SMBUS Timing config register */
+#define SMB_TIMGCFG_REG 0x4U
+
+#define SMB_TIMGCFG_MODE400_MASK 0x80000000U
+#define SMB_TIMGCFG_MODE400_SHIFT 31U
+
+#define SMB_TIMGCFG_RNDSLVSTR_MASK 0x7F000000U
+#define SMB_TIMGCFG_RNDSLVSTR_SHIFT 24U
+
+#define SMB_TIMGCFG_PERSLVSTR_MASK 0x00FF0000U
+#define SMB_TIMGCFG_PERSLVSTR_SHIFT 16U
+
+#define SMB_TIMGCFG_IDLTIME_MASK 0x0000FF00U
+#define SMB_TIMGCFG_IDLTIME_SHIFT 8U
+
+/* SMBUS Slave address register */
+#define SMB_ADDR_REG 0x8U
+
+#define SMB_EN_NIC_SMBADDR3_MASK 0x80000000U
+#define SMB_EN_NIC_SMBADDR3_SHIFT 31U
+
+#define SMB_NIC_SMBADDR3_MASK 0x7F000000U
+#define SMB_NIC_SMBADDR3_SHIFT 24U
+
+#define SMB_EN_NIC_SMBADDR2_MASK 0x00800000U
+#define SMB_EN_NIC_SMBADDR2_SHIFT 23U
+
+#define SMB_NIC_SMBADDR2_MASK 0x007F0000U
+#define SMB_NIC_SMBADDR2_SHIFT 16U
+
+#define SMB_EN_NIC_SMBADDR1_MASK 0x00008000U
+#define SMB_EN_NIC_SMBADDR1_SHIFT 15U
+
+#define SMB_NIC_SMBADDR1_MASK 0x00007F00U
+#define SMB_NIC_SMBADDR1_SHIFT 8U
+
+#define SMB_EN_NIC_SMBADDR0_MASK 0x00000080U
+#define SMB_EN_NIC_SMBADDR0_SHIFT 7U
+
+#define SMB_NIC_SMBADDR0_MASK 0x0000007FU
+#define SMB_NIC_SMBADDR0_SHIFT 0U
+
+/* SMBUS Master FIFO control register */
+#define SMB_MSTRFIFOCTL_REG 0xCU
+
+#define SMB_MSTRRXFIFOFLSH_MASK 0x80000000U
+#define SMB_MSTRRXFIFOFLSH_SHIFT 31U
+
+#define SMB_MSTRTXFIFOFLSH_MASK 0x40000000U
+#define SMB_MSTRTXFIFOFLSH_SHIFT 30U
+
+#define SMB_MSTRRXPKTCNT_MASK 0x007F0000U
+#define SMB_MSTRRXPKTCNT_SHIFT 16U
+
+#define SMB_MSTRRXFIFOTHR_MASK 0x00003F00U
+#define SMB_MSTRRXFIFOTHR_SHIFT 8U
+
+/* SMBUS Slave FIFO control register */
+#define SMB_SLVFIFOCTL_REG 0x10U
+
+#define SMB_SLVRXFIFOFLSH_MASK 0x80000000U
+#define SMB_SLVRXFIFOFLSH_SHIFT 31U
+
+#define SMB_SLVTXFIFOFLSH_MASK 0x40000000U
+#define SMB_SLVTXFIFOFLSH_SHIFT 30U
+
+#define SMB_SLVRXPKTCNT_MASK 0x007F0000U
+#define SMB_SLVRXPKTCNT_SHIFT 16U
+
+#define SMB_SLVRXFIFOTHR_MASK 0x00003F00U
+#define SMB_SLVRXFIFOTHR_SHIFT 8U
+
+/* SMBUS Bit-bang mode control register */
+#define SMB_BITBANGCTL_REG 0x14U
+
+#define SMB_SMBCLKIN_MASK 0x80000000U
+#define SMB_SMBCLKIN_SHIFT 31U
+
+#define SMB_SMBCLKOUTEN_MASK 0x40000000U
+#define SMB_SMBCLKOUTEN_SHIFT 30U
+
+#define SMB_SMBDATAIN_MASK 0x20000000U
+#define SMB_SMBDATAIN_SHIFT 29U
+
+#define SMB_SMBDATAOUTEN_MASK 0x10000000U
+#define SMB_SMBDATAOUTEN_SHIFT 28U
+
+/* SMBUS Master command register */
+#define SMB_MSTRCMD_REG 0x30U
+
+#define SMB_MSTRSTARTBUSYCMD_MASK 0x80000000U
+#define SMB_MSTRSTARTBUSYCMD_SHIFT 31U
+
+#define SMB_MSTRABORT_MASK 0x40000000U
+#define SMB_MSTRABORT_SHIFT 30U
+
+#define SMB_MSTRSTS_MASK 0x0E000000U
+#define SMB_MSTRSTS_SHIFT 25U
+
+#define SMB_MSTRSMBUSPROTO_MASK 0x00001E00U
+#define SMB_MSTRSMBUSPROTO_SHIFT 9U
+
+#define SMB_MSTRPEC_MASK 0x00000100U
+#define SMB_MSTRPEC_SHIFT 8U
+
+#define SMB_MSTRRDBYTECNT_MASK 0x000000FFU
+#define SMB_MSTRRDBYTECNT_SHIFT 0U
+
+/* SMBUS Slave command register */
+#define SMB_SLVCMD_REG 0x34U
+
+#define SMB_SLVSTARTBUSYCMD_MASK 0x80000000U
+#define SMB_SLVSTARTBUSYCMD_SHIFT 31U
+
+#define SMB_SLVABORT_MASK 0x40000000U
+#define SMB_SLVABORT_SHIFT 30U
+
+#define SMB_SLVSTS_MASK 0x03800000U
+#define SMB_SLVSTS_SHIFT 23U
+
+#define SMB_SLVPEC_MASK 0x00000100U
+#define SMB_SLVPEC_SHIFT 8U
+
+/* SMBUS Event enable register */
+#define SMB_EVTEN_REG 0x38U
+
+#define SMB_MSTRRXFIFOFULLEN_MASK 0x80000000U
+#define SMB_MSTRRXFIFOFULLEN_SHIFT 31U
+
+#define SMB_MSTRRXFIFOTHRHITEN_MASK 0x40000000U
+#define SMB_MSTRRXFIFOTHRHITEN_SHIFT 30U
+
+#define SMB_MSTRRXEVTEN_MASK 0x20000000U
+#define SMB_MSTRRXEVTEN_SHIFT 29U
+
+#define SMB_MSTRSTARTBUSYEN_MASK 0x10000000U
+#define SMB_MSTRSTARTBUSYEN_SHIFT 28U
+
+#define SMB_MSTRTXUNDEN_MASK 0x08000000U
+#define SMB_MSTRTXUNDEN_SHIFT 27U
+
+#define SMB_SLVRXFIFOFULLEN_MASK 0x04000000U
+#define SMB_SLVRXFIFOFULLEN_SHIFT 26U
+
+#define SMB_SLVRXFIFOTHRHITEN_MASK 0x02000000U
+#define SMB_SLVRXFIFOTHRHITEN_SHIFT 25U
+
+#define SMB_SLVRXEVTEN_MASK 0x01000000U
+#define SMB_SLVRXEVTEN_SHIFT 24U
+
+#define SMB_SLVSTARTBUSYEN_MASK 0x00800000U
+#define SMB_SLVSTARTBUSYEN_SHIFT 23U
+
+#define SMB_SLVTXUNDEN_MASK 0x00400000U
+#define SMB_SLVTXUNDEN_SHIFT 22U
+
+#define SMB_SLVRDEVTEN_MASK 0x00200000U
+#define SMB_SLVRDEVTEN_SHIFT 21U
+
+/* SMBUS Event status register */
+#define SMB_EVTSTS_REG 0x3CU
+
+#define SMB_MSTRRXFIFOFULLSTS_MASK 0x80000000U
+#define SMB_MSTRRXFIFOFULLSTS_SHIFT 31U
+
+#define SMB_MSTRRXFIFOTHRHITSTS_MASK 0x40000000U
+#define SMB_MSTRRXFIFOTHRHITSTS_SHIFT 30U
+
+#define SMB_MSTRRXEVTSTS_MASK 0x20000000U
+#define SMB_MSTRRXEVTSTS_SHIFT 29U
+
+#define SMB_MSTRSTARTBUSYSTS_MASK 0x10000000U
+#define SMB_MSTRSTARTBUSYSTS_SHIFT 28U
+
+#define SMB_MSTRTXUNDSTS_MASK 0x08000000U
+#define SMB_MSTRTXUNDSTS_SHIFT 27U
+
+#define SMB_SLVRXFIFOFULLSTS_MASK 0x04000000U
+#define SMB_SLVRXFIFOFULLSTS_SHIFT 26U
+
+#define SMB_SLVRXFIFOTHRHITSTS_MASK 0x02000000U
+#define SMB_SLVRXFIFOTHRHITSTS_SHIFT 25U
+
+#define SMB_SLVRXEVTSTS_MASK 0x01000000U
+#define SMB_SLVRXEVTSTS_SHIFT 24U
+
+#define SMB_SLVSTARTBUSYSTS_MASK 0x00800000U
+#define SMB_SLVSTARTBUSYSTS_SHIFT 23U
+
+#define SMB_SLVTXUNDSTS_MASK 0x00400000U
+#define SMB_SLVTXUNDSTS_SHIFT 22U
+
+#define SMB_SLVRDEVTSTS_MASK 0x00200000U
+#define SMB_SLVRDEVTSTS_SHIFT 21U
+
+/* SMBUS Master data write register */
+#define SMB_MSTRDATAWR_REG 0x40U
+
+#define SMB_MSTRWRSTS_MASK 0x80000000U
+#define SMB_MSTRWRSTS_SHIFT 31U
+
+#define SMB_MSTRWRDATA_MASK 0x000000FFU
+#define SMB_MSTRWRDATA_SHIFT 0U
+
+/* SMBUS Master data read register */
+#define SMB_MSTRDATARD_REG 0x44U
+
+#define SMB_MSTRRDSTS_MASK 0xC0000000U
+#define SMB_MSTRRDSTS_SHIFT 30U
+
+#define SMB_MSTRRDPECERR_MASK 0x20000000U
+#define SMB_MSTRRDPECERR_SHIFT 29U
+
+#define SMB_MSTRRDDATA_MASK 0x000000FFU
+#define SMB_MSTRRDDATA_SHIFT 0U
+
+/* SMBUS Slave data write register */
+#define SMB_SLVDATAWR_REG 0x48U
+
+#define SMB_SLVWRSTS_MASK 0x80000000U
+#define SMB_SLVWRSTS_SHIFT 31U
+
+#define SMB_SLVWRDATA_MASK 0x000000FFU
+#define SMB_SLVWRDATA_SHIFT 0U
+
+/* SMBUS Slave data read register */
+#define SMB_SLVDATARD_REG 0x4CU
+
+#define SMB_SLVRDSTS_MASK 0xC0000000U
+#define SMB_SLVRDSTS_SHIFT 30U
+
+#define SMB_SLVRDERRSTS_MASK 0x30000000U
+#define SMB_SLVRDERRSTS_SHIFT 28U
+
+#define SMB_SLVRDDATA_MASK 0x000000FFU
+#define SMB_SLVRDDATA_SHIFT 0U
+
+#endif /* I2C_REGS */
diff --git a/include/drivers/brcm/iproc_gpio.h b/include/drivers/brcm/iproc_gpio.h
new file mode 100644
index 0000000..be971f6
--- /dev/null
+++ b/include/drivers/brcm/iproc_gpio.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019-2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IPROC_GPIO_H
+#define IPROC_GPIO_H
+
+#ifdef USE_GPIO
+void iproc_gpio_init(uintptr_t base, int nr_gpios, uintptr_t pinmux_base,
+ uintptr_t pinconf_base);
+#else
+static void iproc_gpio_init(uintptr_t base, int nr_gpios, uintptr_t pinmux_base,
+ uintptr_t pinconf_base)
+{
+}
+#endif /* IPROC_GPIO */
+
+#endif /* IPROC_GPIO_H */
diff --git a/include/drivers/brcm/mdio/mdio.h b/include/drivers/brcm/mdio/mdio.h
new file mode 100644
index 0000000..b27c7b3
--- /dev/null
+++ b/include/drivers/brcm/mdio/mdio.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MDIO_H
+#define MDIO_H
+
+#define CMIC_MIIM_PARAM (PLAT_CMIC_MIIM_BASE + 0x23cU)
+#define MDIO_PARAM_MIIM_CYCLE 29U
+#define MDIO_PARAM_INTERNAL_SEL 25U
+#define MDIO_PARAM_BUSID 22U
+#define MDIO_PARAM_BUSID_MASK 0x7U
+#define MDIO_PARAM_C45_SEL 21U
+#define MDIO_PARAM_PHYID 16U
+#define MDIO_PARAM_PHYID_MASK 0x1FU
+#define MDIO_PARAM_DATA 0U
+#define MDIO_PARAM_DATA_MASK 0xFFFFU
+#define CMIC_MIIM_READ_DATA (PLAT_CMIC_MIIM_BASE + 0x240U)
+#define MDIO_READ_DATA_MASK 0xffffU
+#define CMIC_MIIM_ADDRESS (PLAT_CMIC_MIIM_BASE + 0x244U)
+#define CMIC_MIIM_CTRL (PLAT_CMIC_MIIM_BASE + 0x248U)
+#define MDIO_CTRL_WRITE_OP 0x1U
+#define MDIO_CTRL_READ_OP 0x2U
+#define CMIC_MIIM_STAT (PLAT_CMIC_MIIM_BASE + 0x24cU)
+#define MDIO_STAT_DONE 1U
+
+int mdio_write(uint16_t busid, uint16_t phyid, uint32_t reg, uint16_t val);
+int mdio_read(uint16_t busid, uint16_t phyid, uint32_t reg);
+#endif /* MDIO_H */
diff --git a/include/drivers/brcm/ocotp.h b/include/drivers/brcm/ocotp.h
new file mode 100644
index 0000000..830b3e4
--- /dev/null
+++ b/include/drivers/brcm/ocotp.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef OCOTP_H
+#define OCOTP_H
+
+#include <stdint.h>
+
+struct otpc_map {
+ /* in words. */
+ uint32_t otpc_row_size;
+ /* 128 bit row / 4 words support. */
+ uint16_t data_r_offset[4];
+ /* 128 bit row / 4 words support. */
+ uint16_t data_w_offset[4];
+ int word_size;
+ int stride;
+};
+
+int bcm_otpc_init(struct otpc_map *map);
+int bcm_otpc_read(unsigned int offset, void *val, uint32_t bytes,
+ uint32_t ecc_flag);
+
+#endif /* OCOTP_H */
diff --git a/include/drivers/brcm/scp.h b/include/drivers/brcm/scp.h
new file mode 100644
index 0000000..7806314
--- /dev/null
+++ b/include/drivers/brcm/scp.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2017 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SCP_H
+#define SCP_H
+
+#include <stdint.h>
+
+int download_scp_patch(void *image, unsigned int image_size);
+
+#endif /* SCP_H */
diff --git a/include/drivers/brcm/sf.h b/include/drivers/brcm/sf.h
new file mode 100644
index 0000000..c32cbeb
--- /dev/null
+++ b/include/drivers/brcm/sf.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2019-2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SF_H
+#define SF_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef SPI_DEBUG
+#define SPI_DEBUG(fmt, ...) INFO(fmt, ##__VA_ARGS__)
+#else
+#define SPI_DEBUG(fmt, ...)
+#endif
+
+#define SPI_FLASH_MAX_ID_LEN 6
+
+#define CMD_WRSR 0x01 /* Write status register */
+#define CMD_PAGE_PROGRAM 0x02
+#define CMD_READ_NORMAL 0x03
+#define CMD_RDSR 0x05
+#define CMD_WRITE_ENABLE 0x06
+#define CMD_RDFSR 0x70
+#define CMD_READ_ID 0x9f
+#define CMD_ERASE_4K 0x20
+#define CMD_ERASE_64K 0xd8
+#define ERASE_SIZE_64K (64 * 1024)
+
+/* Common status */
+#define STATUS_WIP BIT(0)
+
+struct spi_flash {
+ struct spi_slave *spi;
+ uint32_t size;
+ uint32_t page_size;
+ uint32_t sector_size;
+ uint32_t erase_size;
+ uint8_t erase_cmd;
+ uint8_t read_cmd;
+ uint8_t write_cmd;
+ uint8_t flags;
+};
+
+struct spi_flash_info {
+ const char *name;
+
+ /*
+ * This array stores the ID bytes.
+ * The first three bytes are the JEDIC ID.
+ * JEDEC ID zero means "no ID" (mostly older chips).
+ */
+ uint8_t id[SPI_FLASH_MAX_ID_LEN];
+ uint8_t id_len;
+
+ uint32_t sector_size;
+ uint32_t n_sectors;
+ uint16_t page_size;
+
+ uint8_t flags;
+};
+
+/* Enum list - Full read commands */
+enum spi_read_cmds {
+ ARRAY_SLOW = BIT(0),
+ ARRAY_FAST = BIT(1),
+ DUAL_OUTPUT_FAST = BIT(2),
+ DUAL_IO_FAST = BIT(3),
+ QUAD_OUTPUT_FAST = BIT(4),
+ QUAD_IO_FAST = BIT(5),
+};
+
+/* sf param flags */
+enum spi_param_flag {
+ SECT_4K = BIT(0),
+ SECT_32K = BIT(1),
+ E_FSR = BIT(2),
+ SST_BP = BIT(3),
+ SST_WP = BIT(4),
+ WR_QPP = BIT(5),
+};
+
+int spi_flash_cmd_read(const uint8_t *cmd, size_t cmd_len,
+ void *data, size_t data_len);
+int spi_flash_cmd(uint8_t cmd, void *response, size_t len);
+int spi_flash_cmd_write(const uint8_t *cmd, size_t cmd_len,
+ const void *data, size_t data_len);
+#endif
diff --git a/include/drivers/brcm/sotp.h b/include/drivers/brcm/sotp.h
new file mode 100644
index 0000000..a93d687
--- /dev/null
+++ b/include/drivers/brcm/sotp.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2016-2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SOTP_H
+#define SOTP_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+#include <platform_sotp.h>
+
+#define SOTP_ROW_NO_ECC 0
+#define SOTP_ROW_ECC 1
+
+#define SOTP_STATUS_1 (SOTP_REGS_OTP_BASE + 0x001c)
+#define SOTP_FAIL_BITS 0x18000000000
+#define SOTP_ECC_ERR_DETECT 0x8000000000000000
+
+#define SOTP_REGS_SOTP_CHIP_STATES (SOTP_REGS_OTP_BASE + 0x0028)
+#define SOTP_REGS_OTP_WR_LOCK (SOTP_REGS_OTP_BASE + 0x0038)
+
+#define SOTP_CHIP_STATES_MANU_DEBUG_MASK (1 << 8)
+#define SOTP_DEVICE_SECURE_CFG0_OTP_ERASED_MASK (3 << 16)
+#define SOTP_REGS_SOTP_CHIP_STATES_OTP_ERASED_MASK (1 << 16)
+
+#define SOTP_DEVICE_SECURE_CFG0_CID_MASK (3 << 2)
+#define SOTP_DEVICE_SECURE_CFG0_AB_MASK (3 << 6)
+#define SOTP_DEVICE_SECURE_CFG0_DEV_MASK (3 << 8)
+
+#define SOTP_BOOT_SOURCE_SHIFT 8
+/* bits 14 and 15 */
+#define SOTP_BOOT_SOURCE_ENABLE_MASK (0xC0 << SOTP_BOOT_SOURCE_SHIFT)
+/* bits 8 to 13 */
+#define SOTP_BOOT_SOURCE_BITS0 (0x03 << SOTP_BOOT_SOURCE_SHIFT)
+#define SOTP_BOOT_SOURCE_BITS1 (0x0C << SOTP_BOOT_SOURCE_SHIFT)
+#define SOTP_BOOT_SOURCE_BITS2 (0x30 << SOTP_BOOT_SOURCE_SHIFT)
+#define SOTP_BOOT_SOURCE_MASK (0x3F << SOTP_BOOT_SOURCE_SHIFT)
+
+#define SOTP_ATF_CFG_ROW_ID SOTP_DEVICE_SECURE_CFG2_ROW
+/* bits 28 and 29 */
+#define SOTP_SBL_MASK (3 << 28)
+/* bits 30 and 31 */
+#define SOTP_ATF_NVCOUNTER_ENABLE_MASK ((uint64_t)3 << 30)
+/* bits 32 and 33 */
+#define SOTP_ATF_WATCHDOG_ENABLE_MASK ((uint64_t)3 << 32)
+/* bits 34 and 35 */
+#define SOTP_ATF_PLL_ON ((uint64_t)3 << 34)
+/* bits 36 and 37 */
+#define SOTP_ATF_RESET_RETRY ((uint64_t)3 << 36)
+/* bits 38 to 40 */
+#define SOTP_ATF_LOG_LEVEL_SHIFT 38
+#define SOTP_ATF_LOG_LEVEL ((uint64_t)7 << SOTP_ATF_LOG_LEVEL_SHIFT)
+
+#define SOTP_ATF2_CFG_ROW_ID SOTP_DEVICE_SECURE_CFG3_ROW
+/* bits 16 and 17 */
+#define SOTP_ROMKEY_MASK (3 << 16)
+/* bits 18 and 19 */
+#define SOTP_EC_EN_MASK (3 << 18)
+
+#define SOTP_ENC_DEV_TYPE_AB_DEV ((uint64_t)0x19999800000)
+#define SOTP_ENC_DEV_TYPE_MASK ((uint64_t)0x1ffff800000)
+
+uint64_t sotp_mem_read(uint32_t offset, uint32_t sotp_add_ecc);
+void sotp_mem_write(uint32_t addr, uint32_t sotp_add_ecc, uint64_t wdata);
+int sotp_read_key(uint8_t *key, size_t keysize, int start_row, int end_row);
+int sotp_key_erased(void);
+uint32_t sotp_redundancy_reduction(uint32_t sotp_row_data);
+#endif
diff --git a/include/drivers/brcm/spi.h b/include/drivers/brcm/spi.h
new file mode 100644
index 0000000..9d92d8c
--- /dev/null
+++ b/include/drivers/brcm/spi.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2017 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SPI_H
+#define SPI_H
+
+#include <stdint.h>
+
+#define SPI_XFER_BEGIN (1 << 0) /* Assert CS before transfer */
+#define SPI_XFER_END (1 << 1) /* De-assert CS after transfer */
+#define SPI_XFER_QUAD (1 << 2)
+
+int spi_init(void);
+int spi_claim_bus(void);
+void spi_release_bus(void);
+int spi_xfer(uint32_t bitlen, const void *dout, void *din, uint32_t flags);
+
+#endif /* _SPI_H_ */
diff --git a/include/drivers/brcm/spi_flash.h b/include/drivers/brcm/spi_flash.h
new file mode 100644
index 0000000..bbaaa50
--- /dev/null
+++ b/include/drivers/brcm/spi_flash.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2019-2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SPI_FLASH_H
+#define SPI_FLASH_H
+
+#include <sf.h>
+
+int spi_flash_probe(struct spi_flash *flash);
+int spi_flash_erase(struct spi_flash *flash, uint32_t offset, uint32_t len);
+int spi_flash_write(struct spi_flash *flash, uint32_t offset,
+ uint32_t len, void *buf);
+int spi_flash_read(struct spi_flash *flash, uint32_t offset,
+ uint32_t len, void *data);
+#endif /* _SPI_FLASH_H_ */
diff --git a/include/drivers/brcm/usbh_xhci_regs.h b/include/drivers/brcm/usbh_xhci_regs.h
new file mode 100644
index 0000000..93dec7b
--- /dev/null
+++ b/include/drivers/brcm/usbh_xhci_regs.h
@@ -0,0 +1,4809 @@
+/*
+ * Copyright (c) 2017 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef USBH_XHCI_REGS_H
+#define USBH_XHCI_REGS_H
+
+#include <lib/mmio.h>
+#include <platform_def.h>
+
+#define XHCI_LEN (8096U)
+
+#define XHC_CPLIVER_OFFSET 0x000U
+#define XHC_SPARAMS1_OFFSET 0x004U
+#define XHC_SPARAMS2_OFFSET 0x008U
+#define XHC_SPARAMS3_OFFSET 0x00cU
+#define XHC_CPARAMS1_OFFSET 0x010U
+#define XHC_DBOFF_OFFSET 0x014U
+#define XHC_RTOFF_OFFSET 0x018U
+#define XHC_CPARAMS2_OFFSET 0x01cU
+#define XHC_USBCMD_OFFSET 0x020U
+#define XHC_USBSTS_OFFSET 0x024U
+#define XHC_PAGESIZE_OFFSET 0x028U
+#define XHC_DNCTRL_OFFSET 0x034U
+#define XHC_CRCRL_OFFSET 0x038U
+#define XHC_CRCRH_OFFSET 0x03cU
+#define XHC_DCBAAPL_OFFSET 0x050U
+#define XHC_DCBAAPH_OFFSET 0x054U
+#define XHC_CONFIG_OFFSET 0x058U
+#define XHC_PORTSC1_OFFSET 0x420U
+#define XHC_PORTPM1_OFFSET 0x424U
+#define XHC_PORTLC1_OFFSET 0x428U
+#define XHC_PORTSC2_OFFSET 0x430U
+#define XHC_PORTPM2_OFFSET 0x434U
+#define XHC_PORTLC2_OFFSET 0x43cU
+#define XHC_PORTSC3_OFFSET 0x440U
+#define XHC_PORTPM3_OFFSET 0x444U
+#define XHC_PORTLI3_OFFSET 0x44cU
+#define XHC_MFINDEX_OFFSET 0x4a0U
+#define XHC_IMAN0_OFFSET 0x4c0U
+#define XHC_IMOD0_OFFSET 0x4c4U
+#define XHC_ERSTSZ0_OFFSET 0x4c8U
+#define XHC_ERSTBAL0_OFFSET 0x4d0U
+#define XHC_ERSTBAH0_OFFSET 0x4d4U
+#define XHC_ERDPL0_OFFSET 0x4d8U
+#define XHC_ERDPH0_OFFSET 0x4dcU
+#define XHC_IMAN1_OFFSET 0x4e0U
+#define XHC_IMOD1_OFFSET 0x4e4U
+#define XHC_ERSTSZ1_OFFSET 0x4e8U
+#define XHC_ERSTBAL1_OFFSET 0x4f0U
+#define XHC_ERSTBAH1_OFFSET 0x4f4U
+#define XHC_ERDPL1_OFFSET 0x4f8U
+#define XHC_ERDPH1_OFFSET 0x4fcU
+#define XHC_DBLCMD_OFFSET 0x8c0U
+#define XHC_DBLDVX1_OFFSET 0x8c4U
+#define XHC_DBLDVX2_OFFSET 0x8c8U
+#define XHC_DBLDVX3_OFFSET 0x8ccU
+#define XHC_DBLDVX4_OFFSET 0x8d0U
+#define XHC_DBLDVX5_OFFSET 0x8d4U
+#define XHC_DBLDVX6_OFFSET 0x8d8U
+#define XHC_DBLDVX7_OFFSET 0x8dcU
+#define XHC_DBLDVX8_OFFSET 0x8e0U
+#define XHC_DBLDVX9_OFFSET 0x8e4U
+#define XHC_DBLDVX10_OFFSET 0x8e8U
+#define XHC_DBLDVX11_OFFSET 0x8ecU
+#define XHC_DBLDVX12_OFFSET 0x8f0U
+#define XHC_DBLDVX13_OFFSET 0x8f4U
+#define XHC_DBLDVX14_OFFSET 0x8f8U
+#define XHC_DBLDVX15_OFFSET 0x8fcU
+#define XHC_DBLDVX16_OFFSET 0x900U
+#define XHC_ECHSPT3_OFFSET 0x940U
+#define XHC_PNSTR3_OFFSET 0x944U
+#define XHC_PSUM3_OFFSET 0x948U
+#define XHC_PTSLTYP3_OFFSET 0x94cU
+#define XHC_ECHSPT2_OFFSET 0x950U
+#define XHC_PNSTR2_OFFSET 0x954U
+#define XHC_PSUM2_OFFSET 0x958U
+#define XHC_PTSLTYP2_OFFSET 0x95cU
+#define XHC_ECHRSVP_OFFSET 0x960U
+#define XHC_ECHRSVI_OFFSET 0x968U
+#define XHC_ECHRSVM_OFFSET 0xae8U
+#define XHC_ECHRSVD_OFFSET 0xaf8U
+#define XHC_ECHRSVO_OFFSET 0xb38U
+#define XHC_ECHCTT_OFFSET 0xbf0U
+#define XHC_CTTMTS0_OFFSET 0xbf8U
+#define XHC_CTTMTS1_OFFSET 0xbfcU
+#define XHC_ECHBIU_OFFSET 0xc00U
+#define XHC_BIUSPC_OFFSET 0xc04U
+#define XHC_AXIWRA_OFFSET 0xc08U
+#define XHC_AXIRDA_OFFSET 0xc0cU
+#define XHC_AXILPM_OFFSET 0xc10U
+#define XHC_AXIQOS_OFFSET 0xc14U
+#define XHC_ECHCSR_OFFSET 0xc20U
+#define XHC_CSRSPC_OFFSET 0xc24U
+#define XHC_ECHAIU_OFFSET 0xc30U
+#define XHC_AIUDMA_OFFSET 0xc34U
+#define XHC_AIUFLA_OFFSET 0xc38U
+#define XHC_AIUCFG_OFFSET 0xc3cU
+#define XHC_ECHFSC_OFFSET 0xc40U
+#define XHC_FSCPOC_OFFSET 0xc54U
+#define XHC_FSCGOC_OFFSET 0xc58U
+#define XHC_FSCNOC_OFFSET 0xc5cU
+#define XHC_FSCAIC_OFFSET 0xc60U
+#define XHC_FSCPIC_OFFSET 0xc64U
+#define XHC_FSCGIC_OFFSET 0xc68U
+#define XHC_FSCNIC_OFFSET 0xc6cU
+#define XHC_ECHPRT_OFFSET 0xc70U
+#define XHC_PRTHSC_OFFSET 0xc78U
+#define XHC_PRTHSR_OFFSET 0xc7cU
+#define XHC_ECHRHS_OFFSET 0xc80U
+#define XHC_RHSDES_OFFSET 0xc84U
+#define XHC_RHSHSC0_OFFSET 0xc90U
+#define XHC_RHSHSR0_OFFSET 0xc94U
+#define XHC_RHSHSC1_OFFSET 0xc98U
+#define XHC_RHSHSR1_OFFSET 0xc9cU
+#define XHC_RHSHSC2_OFFSET 0xca0U
+#define XHC_RHSHSR2_OFFSET 0xca4U
+#define XHC_RHSHSC3_OFFSET 0xca8U
+#define XHC_RHSHSR3_OFFSET 0xcacU
+#define XHC_ECHSSP_OFFSET 0xcb0U
+#define XHC_SSPVER_OFFSET 0xcb4U
+#define XHC_SSPMGN_OFFSET 0xcb8U
+#define XHC_ECHFSC2_OFFSET 0xcc0U
+#define XHC_FSC2POC_OFFSET 0xcd4U
+#define XHC_FSC2GOC_OFFSET 0xcd8U
+#define XHC_FSC2NOC_OFFSET 0xcdcU
+#define XHC_FSC2AIC_OFFSET 0xce0U
+#define XHC_FSC2PIC_OFFSET 0xce4U
+#define XHC_FSC2GIC_OFFSET 0xce8U
+#define XHC_FSC2NIC_OFFSET 0xcecU
+#define XHC_ECHPRT2_OFFSET 0xcf0U
+#define XHC_PRT2HSC_OFFSET 0xcf8U
+#define XHC_PRT2HSR_OFFSET 0xcfcU
+#define XHC_ECHRH2_OFFSET 0xd00U
+#define XHC_RH2DES_OFFSET 0xd04U
+#define XHC_RH2HSC0_OFFSET 0xd10U
+#define XHC_RH2HSR0_OFFSET 0xd14U
+#define XHC_RH2HSC1_OFFSET 0xd18U
+#define XHC_RH2HSR1_OFFSET 0xd1cU
+#define XHC_RH2HSC2_OFFSET 0xd20U
+#define XHC_RH2HSR2_OFFSET 0xd24U
+#define XHC_RH2HSC3_OFFSET 0xd28U
+#define XHC_RH2HSR3_OFFSET 0xd2cU
+#define XHC_ECHU2P_OFFSET 0xd30U
+#define XHC_U2PVER_OFFSET 0xd34U
+#define XHC_U2PMGN_OFFSET 0xd38U
+#define XHC_ECHRSV2_OFFSET 0xd40U
+#define XHC_ECHIRA_OFFSET 0xf90U
+#define XHC_IRAADR_OFFSET 0xf98U
+#define XHC_IRADAT_OFFSET 0xf9cU
+#define XHC_ECHHST_OFFSET 0xfa0U
+#define XHC_HSTDBG_OFFSET 0xfa4U
+#define XHC_HSTNPL_OFFSET 0xfa8U
+#define XHC_HSTNPH_OFFSET 0xfacU
+#define XHC_ECHRBV_OFFSET 0xfb0U
+#define XHC_RBVPDT_OFFSET 0xfb4U
+#define XHC_RBVMGN_OFFSET 0xfbcU
+
+#define XHC_CPLIVER_BASE 0x000U
+#define XHC_CPLIVER__IVH_L 31U
+#define XHC_CPLIVER__IVH_R 24U
+#define XHC_CPLIVER__IVH_WIDTH 8U
+#define XHC_CPLIVER__IVH_RESETVALUE 0x01U
+#define XHC_CPLIVER__IVL_L 23U
+#define XHC_CPLIVER__IVL_R 16U
+#define XHC_CPLIVER__IVL_WIDTH 8U
+#define XHC_CPLIVER__IVL_RESETVALUE 0x10U
+#define XHC_CPLIVER__reserved_L 15U
+#define XHC_CPLIVER__reserved_R 8U
+#define XHC_CPLIVER__reserved_WIDTH 8U
+#define XHC_CPLIVER__reserved_RESETVALUE 0x00U
+#define XHC_CPLIVER__CPL_L 7U
+#define XHC_CPLIVER__CPL_R 0U
+#define XHC_CPLIVER__CPL_WIDTH 8U
+#define XHC_CPLIVER__CPL_RESETVALUE 0x00U
+#define XHC_CPLIVER_WIDTH 32U
+#define XHC_CPLIVER__WIDTH 32U
+#define XHC_CPLIVER_ALL_L 31U
+#define XHC_CPLIVER_ALL_R 0U
+#define XHC_CPLIVER__ALL_L 31U
+#define XHC_CPLIVER__ALL_R 0U
+#define XHC_CPLIVER_DATAMASK 0xffffffffU
+#define XHC_CPLIVER_RDWRMASK 0x00000000U
+#define XHC_CPLIVER_RESETVALUE 0x01100000U
+
+#define XHC_SPARAMS1_OFFSET 0x004U
+#define XHC_SPARAMS1_BASE 0x004U
+#define XHC_SPARAMS1__NPTS_L 31U
+#define XHC_SPARAMS1__NPTS_R 24U
+#define XHC_SPARAMS1__NPTS_WIDTH 8U
+#define XHC_SPARAMS1__NPTS_RESETVALUE 0x00U
+#define XHC_SPARAMS1__reserved_L 23U
+#define XHC_SPARAMS1__reserved_R 19U
+#define XHC_SPARAMS1__reserved_WIDTH 5U
+#define XHC_SPARAMS1__reserved_RESETVALUE 0x0U
+#define XHC_SPARAMS1__MITS_L 18U
+#define XHC_SPARAMS1__MITS_R 8U
+#define XHC_SPARAMS1__MITS_WIDTH 11U
+#define XHC_SPARAMS1__MITS_RESETVALUE 0x1U
+#define XHC_SPARAMS1__MSLS_L 7U
+#define XHC_SPARAMS1__MSLS_R 0U
+#define XHC_SPARAMS1__MSLS_WIDTH 8U
+#define XHC_SPARAMS1__MSLS_RESETVALUE 0x00U
+#define XHC_SPARAMS1_WIDTH 32U
+#define XHC_SPARAMS1__WIDTH 32U
+#define XHC_SPARAMS1_ALL_L 31U
+#define XHC_SPARAMS1_ALL_R 0U
+#define XHC_SPARAMS1__ALL_L 31U
+#define XHC_SPARAMS1__ALL_R 0U
+#define XHC_SPARAMS1_DATAMASK 0xffffffffU
+#define XHC_SPARAMS1_RDWRMASK 0x00000000U
+#define XHC_SPARAMS1_RESETVALUE 0x00000100U
+
+#define XHC_SPARAMS2_OFFSET 0x008U
+#define XHC_SPARAMS2_BASE 0x008U
+#define XHC_SPARAMS2__MSPBSL_L 31U
+#define XHC_SPARAMS2__MSPBSL_R 27U
+#define XHC_SPARAMS2__MSPBSL_WIDTH 5U
+#define XHC_SPARAMS2__MSPBSL_RESETVALUE 0x0U
+#define XHC_SPARAMS2__SPR 26U
+#define XHC_SPARAMS2__SPR_L 26U
+#define XHC_SPARAMS2__SPR_R 26U
+#define XHC_SPARAMS2__SPR_WIDTH 1U
+#define XHC_SPARAMS2__SPR_RESETVALUE 0x1U
+#define XHC_SPARAMS2__MSPBSH_L 25U
+#define XHC_SPARAMS2__MSPBSH_R 21U
+#define XHC_SPARAMS2__MSPBSH_WIDTH 5U
+#define XHC_SPARAMS2__MSPBSH_RESETVALUE 0x0U
+#define XHC_SPARAMS2__reserved_L 20U
+#define XHC_SPARAMS2__reserved_R 8U
+#define XHC_SPARAMS2__reserved_WIDTH 13U
+#define XHC_SPARAMS2__reserved_RESETVALUE 0x0U
+#define XHC_SPARAMS2__MERST_L 7U
+#define XHC_SPARAMS2__MERST_R 4U
+#define XHC_SPARAMS2__MERST_WIDTH 4U
+#define XHC_SPARAMS2__MERST_RESETVALUE 0x0U
+#define XHC_SPARAMS2__IST_L 3U
+#define XHC_SPARAMS2__IST_R 0U
+#define XHC_SPARAMS2__IST_WIDTH 4U
+#define XHC_SPARAMS2__IST_RESETVALUE 0x0U
+#define XHC_SPARAMS2_WIDTH 32U
+#define XHC_SPARAMS2__WIDTH 32U
+#define XHC_SPARAMS2_ALL_L 31U
+#define XHC_SPARAMS2_ALL_R 0U
+#define XHC_SPARAMS2__ALL_L 31U
+#define XHC_SPARAMS2__ALL_R 0U
+#define XHC_SPARAMS2_DATAMASK 0xffffffffU
+#define XHC_SPARAMS2_RDWRMASK 0x00000000U
+#define XHC_SPARAMS2_RESETVALUE 0x04000000U
+
+#define XHC_SPARAMS3_OFFSET 0x00cU
+#define XHC_SPARAMS3_BASE 0x00cU
+#define XHC_SPARAMS3__U2L_L 31U
+#define XHC_SPARAMS3__U2L_R 16U
+#define XHC_SPARAMS3__U2L_WIDTH 16U
+#define XHC_SPARAMS3__U2L_RESETVALUE 0x0000U
+#define XHC_SPARAMS3__reserved_L 15U
+#define XHC_SPARAMS3__reserved_R 8U
+#define XHC_SPARAMS3__reserved_WIDTH 8U
+#define XHC_SPARAMS3__reserved_RESETVALUE 0x00U
+#define XHC_SPARAMS3__U1L_L 7U
+#define XHC_SPARAMS3__U1L_R 0U
+#define XHC_SPARAMS3__U1L_WIDTH 8U
+#define XHC_SPARAMS3__U1L_RESETVALUE 0x00U
+#define XHC_SPARAMS3_WIDTH 32U
+#define XHC_SPARAMS3__WIDTH 32U
+#define XHC_SPARAMS3_ALL_L 31U
+#define XHC_SPARAMS3_ALL_R 0U
+#define XHC_SPARAMS3__ALL_L 31U
+#define XHC_SPARAMS3__ALL_R 0U
+#define XHC_SPARAMS3_DATAMASK 0xffffffffU
+#define XHC_SPARAMS3_RDWRMASK 0x00000000U
+#define XHC_SPARAMS3_RESETVALUE 0x00000000U
+
+#define XHC_CPARAMS1_OFFSET 0x010U
+#define XHC_CPARAMS1_BASE 0x010U
+#define XHC_CPARAMS1__XECP_L 31U
+#define XHC_CPARAMS1__XECP_R 16U
+#define XHC_CPARAMS1__XECP_WIDTH 16U
+#define XHC_CPARAMS1__XECP_RESETVALUE 0x0000U
+#define XHC_CPARAMS1__MPSA_L 15U
+#define XHC_CPARAMS1__MPSA_R 12U
+#define XHC_CPARAMS1__MPSA_WIDTH 4U
+#define XHC_CPARAMS1__MPSA_RESETVALUE 0x0U
+#define XHC_CPARAMS1__CFC 11U
+#define XHC_CPARAMS1__CFC_L 11U
+#define XHC_CPARAMS1__CFC_R 11U
+#define XHC_CPARAMS1__CFC_WIDTH 1U
+#define XHC_CPARAMS1__CFC_RESETVALUE 0x0U
+#define XHC_CPARAMS1__SEC 10U
+#define XHC_CPARAMS1__SEC_L 10U
+#define XHC_CPARAMS1__SEC_R 10U
+#define XHC_CPARAMS1__SEC_WIDTH 1U
+#define XHC_CPARAMS1__SEC_RESETVALUE 0x0U
+#define XHC_CPARAMS1__SPC 9U
+#define XHC_CPARAMS1__SPC_L 9U
+#define XHC_CPARAMS1__SPC_R 9U
+#define XHC_CPARAMS1__SPC_WIDTH 1U
+#define XHC_CPARAMS1__SPC_RESETVALUE 0x0U
+#define XHC_CPARAMS1__PAE 8U
+#define XHC_CPARAMS1__PAE_L 8U
+#define XHC_CPARAMS1__PAE_R 8U
+#define XHC_CPARAMS1__PAE_WIDTH 1U
+#define XHC_CPARAMS1__PAE_RESETVALUE 0x1U
+#define XHC_CPARAMS1__NSS 7U
+#define XHC_CPARAMS1__NSS_L 7U
+#define XHC_CPARAMS1__NSS_R 7U
+#define XHC_CPARAMS1__NSS_WIDTH 1U
+#define XHC_CPARAMS1__NSS_RESETVALUE 0x0U
+#define XHC_CPARAMS1__LTC 6U
+#define XHC_CPARAMS1__LTC_L 6U
+#define XHC_CPARAMS1__LTC_R 6U
+#define XHC_CPARAMS1__LTC_WIDTH 1U
+#define XHC_CPARAMS1__LTC_RESETVALUE 0x1U
+#define XHC_CPARAMS1__LRC 5U
+#define XHC_CPARAMS1__LRC_L 5U
+#define XHC_CPARAMS1__LRC_R 5U
+#define XHC_CPARAMS1__LRC_WIDTH 1U
+#define XHC_CPARAMS1__LRC_RESETVALUE 0x0U
+#define XHC_CPARAMS1__PIND 4U
+#define XHC_CPARAMS1__PIND_L 4U
+#define XHC_CPARAMS1__PIND_R 4U
+#define XHC_CPARAMS1__PIND_WIDTH 1U
+#define XHC_CPARAMS1__PIND_RESETVALUE 0x0U
+
+#define XHC_CPARAMS1__PPC_L 3U
+#define XHC_CPARAMS1__PPC_R 3U
+#define XHC_CPARAMS1__PPC_WIDTH 1U
+#define XHC_CPARAMS1__PPC_RESETVALUE 0x0U
+#define XHC_CPARAMS1__CSZ 2U
+#define XHC_CPARAMS1__CSZ_L 2U
+#define XHC_CPARAMS1__CSZ_R 2U
+#define XHC_CPARAMS1__CSZ_WIDTH 1U
+#define XHC_CPARAMS1__CSZ_RESETVALUE 0x1U
+#define XHC_CPARAMS1__BNC 1U
+#define XHC_CPARAMS1__BNC_L 1U
+#define XHC_CPARAMS1__BNC_R 1U
+#define XHC_CPARAMS1__BNC_WIDTH 1U
+#define XHC_CPARAMS1__BNC_RESETVALUE 0x0U
+#define XHC_CPARAMS1__AC64 0U
+#define XHC_CPARAMS1__AC64_L 0U
+#define XHC_CPARAMS1__AC64_R 0U
+#define XHC_CPARAMS1__AC64_WIDTH 1U
+#define XHC_CPARAMS1__AC64_RESETVALUE 0x0U
+#define XHC_CPARAMS1_WIDTH 32U
+#define XHC_CPARAMS1__WIDTH 32U
+#define XHC_CPARAMS1_ALL_L 31U
+#define XHC_CPARAMS1_ALL_R 0U
+#define XHC_CPARAMS1__ALL_L 31U
+#define XHC_CPARAMS1__ALL_R 0U
+#define XHC_CPARAMS1_DATAMASK 0xffffffffU
+#define XHC_CPARAMS1_RDWRMASK 0x00000000U
+#define XHC_CPARAMS1_RESETVALUE 0x00000144U
+
+#define XHC_DBOFF_OFFSET 0x014U
+#define XHC_DBOFF_BASE 0x014U
+#define XHC_DBOFF__DBO_L 15U
+#define XHC_DBOFF__DBO_R 2U
+#define XHC_DBOFF__DBO_WIDTH 14U
+#define XHC_DBOFF__DBO_RESETVALUE 0x0U
+#define XHC_DBOFF__reserved_L 1U
+#define XHC_DBOFF__reserved_R 0U
+#define XHC_DBOFF__reserved_WIDTH 2U
+#define XHC_DBOFF__reserved_RESETVALUE 0x0U
+#define XHC_DBOFF__RESERVED_L 31U
+#define XHC_DBOFF__RESERVED_R 16U
+#define XHC_DBOFF_WIDTH 16U
+#define XHC_DBOFF__WIDTH 16U
+#define XHC_DBOFF_ALL_L 15U
+#define XHC_DBOFF_ALL_R 0U
+#define XHC_DBOFF__ALL_L 15U
+#define XHC_DBOFF__ALL_R 0U
+#define XHC_DBOFF_DATAMASK 0x0000ffffU
+#define XHC_DBOFF_RDWRMASK 0xffff0000U
+#define XHC_DBOFF_RESETVALUE 0x0000U
+
+#define XHC_RTOFF_OFFSET 0x018U
+#define XHC_RTOFF_BASE 0x018U
+#define XHC_RTOFF__RTO_L 15U
+#define XHC_RTOFF__RTO_R 5U
+#define XHC_RTOFF__RTO_WIDTH 11U
+#define XHC_RTOFF__RTO_RESETVALUE 0x0U
+#define XHC_RTOFF__reserved_L 4U
+#define XHC_RTOFF__reserved_R 0U
+#define XHC_RTOFF__reserved_WIDTH 5U
+#define XHC_RTOFF__reserved_RESETVALUE 0x0U
+#define XHC_RTOFF__RESERVED_L 31U
+#define XHC_RTOFF__RESERVED_R 16U
+#define XHC_RTOFF_WIDTH 16U
+#define XHC_RTOFF__WIDTH 16U
+#define XHC_RTOFF_ALL_L 15U
+#define XHC_RTOFF_ALL_R 0U
+#define XHC_RTOFF__ALL_L 15U
+#define XHC_RTOFF__ALL_R 0U
+#define XHC_RTOFF_DATAMASK 0x0000ffffU
+#define XHC_RTOFF_RDWRMASK 0xffff0000U
+#define XHC_RTOFF_RESETVALUE 0x0000U
+
+#define XHC_CPARAMS2_OFFSET 0x01cU
+#define XHC_CPARAMS2_BASE 0x01cU
+#define XHC_CPARAMS2__reserved_L 31U
+#define XHC_CPARAMS2__reserved_R 6U
+#define XHC_CPARAMS2__reserved_WIDTH 26U
+#define XHC_CPARAMS2__reserved_RESETVALUE 0x0U
+#define XHC_CPARAMS2__CIC 5U
+#define XHC_CPARAMS2__CIC_L 5U
+#define XHC_CPARAMS2__CIC_R 5U
+#define XHC_CPARAMS2__CIC_WIDTH 1U
+#define XHC_CPARAMS2__CIC_RESETVALUE 0x0U
+#define XHC_CPARAMS2__LEC 4U
+#define XHC_CPARAMS2__LEC_L 4U
+#define XHC_CPARAMS2__LEC_R 4U
+#define XHC_CPARAMS2__LEC_WIDTH 1U
+#define XHC_CPARAMS2__LEC_RESETVALUE 0x0U
+#define XHC_CPARAMS2__CTC 3U
+#define XHC_CPARAMS2__CTC_L 3U
+#define XHC_CPARAMS2__CTC_R 3U
+#define XHC_CPARAMS2__CTC_WIDTH 1U
+#define XHC_CPARAMS2__CTC_RESETVALUE 0x0U
+#define XHC_CPARAMS2__FSC 2U
+#define XHC_CPARAMS2__FSC_L 2U
+#define XHC_CPARAMS2__FSC_R 2U
+#define XHC_CPARAMS2__FSC_WIDTH 1U
+#define XHC_CPARAMS2__FSC_RESETVALUE 0x0U
+#define XHC_CPARAMS2__CMC 1U
+#define XHC_CPARAMS2__CMC_L 1U
+#define XHC_CPARAMS2__CMC_R 1U
+#define XHC_CPARAMS2__CMC_WIDTH 1U
+#define XHC_CPARAMS2__CMC_RESETVALUE 0x0U
+#define XHC_CPARAMS2__U3C 0U
+#define XHC_CPARAMS2__U3C_L 0U
+#define XHC_CPARAMS2__U3C_R 0U
+#define XHC_CPARAMS2__U3C_WIDTH 1U
+#define XHC_CPARAMS2__U3C_RESETVALUE 0x0U
+#define XHC_CPARAMS2_WIDTH 32U
+#define XHC_CPARAMS2__WIDTH 32U
+#define XHC_CPARAMS2_ALL_L 31U
+#define XHC_CPARAMS2_ALL_R 0U
+#define XHC_CPARAMS2__ALL_L 31U
+#define XHC_CPARAMS2__ALL_R 0U
+#define XHC_CPARAMS2_DATAMASK 0xffffffffU
+#define XHC_CPARAMS2_RDWRMASK 0x00000000U
+#define XHC_CPARAMS2_RESETVALUE 0x00000000U
+
+#define XHC_USBCMD_OFFSET 0x020U
+#define XHC_USBCMD_BASE 0x020U
+#define XHC_USBCMD__CME 13U
+#define XHC_USBCMD__CME_L 13U
+#define XHC_USBCMD__CME_R 13U
+#define XHC_USBCMD__CME_WIDTH 1U
+#define XHC_USBCMD__CME_RESETVALUE 0x0U
+#define XHC_USBCMD__SPE 12U
+#define XHC_USBCMD__SPE_L 12U
+#define XHC_USBCMD__SPE_R 12U
+#define XHC_USBCMD__SPE_WIDTH 1U
+#define XHC_USBCMD__SPE_RESETVALUE 0x0U
+#define XHC_USBCMD__EU3S 11U
+#define XHC_USBCMD__EU3S_L 11U
+#define XHC_USBCMD__EU3S_R 11U
+#define XHC_USBCMD__EU3S_WIDTH 1U
+#define XHC_USBCMD__EU3S_RESETVALUE 0x0U
+#define XHC_USBCMD__EWE 10U
+#define XHC_USBCMD__EWE_L 10U
+#define XHC_USBCMD__EWE_R 10U
+#define XHC_USBCMD__EWE_WIDTH 1U
+#define XHC_USBCMD__EWE_RESETVALUE 0x0U
+#define XHC_USBCMD__CRS 9U
+#define XHC_USBCMD__CRS_L 9U
+#define XHC_USBCMD__CRS_R 9U
+#define XHC_USBCMD__CRS_WIDTH 1U
+#define XHC_USBCMD__CRS_RESETVALUE 0x0U
+#define XHC_USBCMD__CSS 8U
+#define XHC_USBCMD__CSS_L 8U
+#define XHC_USBCMD__CSS_R 8U
+#define XHC_USBCMD__CSS_WIDTH 1U
+#define XHC_USBCMD__CSS_RESETVALUE 0x0U
+#define XHC_USBCMD__LRST 7U
+#define XHC_USBCMD__LRST_L 7U
+#define XHC_USBCMD__LRST_R 7U
+#define XHC_USBCMD__LRST_WIDTH 1U
+#define XHC_USBCMD__LRST_RESETVALUE 0x0U
+#define XHC_USBCMD__reserved_L 6U
+#define XHC_USBCMD__reserved_R 4U
+#define XHC_USBCMD__reserved_WIDTH 3U
+#define XHC_USBCMD__reserved_RESETVALUE 0x0U
+#define XHC_USBCMD__HSEE 3U
+#define XHC_USBCMD__HSEE_L 3U
+#define XHC_USBCMD__HSEE_R 3U
+#define XHC_USBCMD__HSEE_WIDTH 1U
+#define XHC_USBCMD__HSEE_RESETVALUE 0x0U
+#define XHC_USBCMD__INTE 2U
+#define XHC_USBCMD__INTE_L 2U
+#define XHC_USBCMD__INTE_R 2U
+#define XHC_USBCMD__INTE_WIDTH 1U
+#define XHC_USBCMD__INTE_RESETVALUE 0x0U
+#define XHC_USBCMD__RST 1U
+#define XHC_USBCMD__RST_L 1U
+#define XHC_USBCMD__RST_R 1U
+#define XHC_USBCMD__RST_WIDTH 1U
+#define XHC_USBCMD__RST_RESETVALUE 0x0U
+#define XHC_USBCMD__RS 0U
+#define XHC_USBCMD__RS_L 0U
+#define XHC_USBCMD__RS_R 0U
+#define XHC_USBCMD__RS_WIDTH 1U
+#define XHC_USBCMD__RS_RESETVALUE 0x0U
+#define XHC_USBCMD__RESERVED_L 31U
+#define XHC_USBCMD__RESERVED_R 14U
+#define XHC_USBCMD_WIDTH 14U
+#define XHC_USBCMD__WIDTH 14U
+#define XHC_USBCMD_ALL_L 13U
+#define XHC_USBCMD_ALL_R 0U
+#define XHC_USBCMD__ALL_L 13U
+#define XHC_USBCMD__ALL_R 0U
+#define XHC_USBCMD_DATAMASK 0x00003fffU
+#define XHC_USBCMD_RDWRMASK 0xffffc000U
+#define XHC_USBCMD_RESETVALUE 0x0000U
+
+#define XHC_USBSTS_OFFSET 0x024U
+#define XHC_USBSTS_BASE 0x024U
+#define XHC_USBSTS__CE 12U
+#define XHC_USBSTS__CE_L 12U
+#define XHC_USBSTS__CE_R 12U
+#define XHC_USBSTS__CE_WIDTH 1U
+#define XHC_USBSTS__CE_RESETVALUE 0x0U
+#define XHC_USBSTS__CNR 11U
+#define XHC_USBSTS__CNR_L 11U
+#define XHC_USBSTS__CNR_R 11U
+#define XHC_USBSTS__CNR_WIDTH 1U
+#define XHC_USBSTS__CNR_RESETVALUE 0x1U
+
+#define XHC_USBSTS__SRE 10U
+#define XHC_USBSTS__SRE_L 10U
+#define XHC_USBSTS__SRE_R 10U
+#define XHC_USBSTS__SRE_WIDTH 1U
+#define XHC_USBSTS__SRE_RESETVALUE 0x0U
+#define XHC_USBSTS__RSS 9U
+#define XHC_USBSTS__RSS_L 9U
+#define XHC_USBSTS__RSS_R 9U
+#define XHC_USBSTS__RSS_WIDTH 1U
+#define XHC_USBSTS__RSS_RESETVALUE 0x0U
+#define XHC_USBSTS__SSS 8U
+#define XHC_USBSTS__SSS_L 8U
+#define XHC_USBSTS__SSS_R 8U
+#define XHC_USBSTS__SSS_WIDTH 1U
+#define XHC_USBSTS__SSS_RESETVALUE 0x0U
+#define XHC_USBSTS__PCD 4U
+#define XHC_USBSTS__PCD_L 4U
+#define XHC_USBSTS__PCD_R 4U
+#define XHC_USBSTS__PCD_WIDTH 1U
+#define XHC_USBSTS__PCD_RESETVALUE 0x0U
+#define XHC_USBSTS__EINT 3U
+#define XHC_USBSTS__EINT_L 3U
+#define XHC_USBSTS__EINT_R 3U
+#define XHC_USBSTS__EINT_WIDTH 1U
+#define XHC_USBSTS__EINT_RESETVALUE 0x0U
+#define XHC_USBSTS__HSE 2U
+#define XHC_USBSTS__HSE_L 2U
+#define XHC_USBSTS__HSE_R 2U
+#define XHC_USBSTS__HSE_WIDTH 1U
+#define XHC_USBSTS__HSE_RESETVALUE 0x0U
+#define XHC_USBSTS__reserved 1U
+#define XHC_USBSTS__reserved_L 1U
+#define XHC_USBSTS__reserved_R 1U
+#define XHC_USBSTS__reserved_WIDTH 1U
+#define XHC_USBSTS__reserved_RESETVALUE 0x0U
+
+#define XHC_USBSTS__CH_L 0U
+#define XHC_USBSTS__CH_R 0U
+#define XHC_USBSTS__CH_WIDTH 1U
+#define XHC_USBSTS__CH_RESETVALUE 0x1U
+#define XHC_USBSTS__RESERVED_L 31U
+#define XHC_USBSTS__RESERVED_R 13U
+#define XHC_USBSTS_WIDTH 13U
+#define XHC_USBSTS__WIDTH 13U
+#define XHC_USBSTS_ALL_L 12U
+#define XHC_USBSTS_ALL_R 0U
+#define XHC_USBSTS__ALL_L 12U
+#define XHC_USBSTS__ALL_R 0U
+#define XHC_USBSTS_DATAMASK 0x00001f1fU
+#define XHC_USBSTS_RDWRMASK 0xffffe0e0U
+#define XHC_USBSTS_RESETVALUE 0x0801U
+
+#define XHC_PAGESIZE_OFFSET 0x028U
+#define XHC_PAGESIZE_BASE 0x028U
+#define XHC_PAGESIZE__reserved_L 31U
+#define XHC_PAGESIZE__reserved_R 16U
+#define XHC_PAGESIZE__reserved_WIDTH 16U
+#define XHC_PAGESIZE__reserved_RESETVALUE 0x0000U
+#define XHC_PAGESIZE__PS_L 15U
+#define XHC_PAGESIZE__PS_R 0U
+#define XHC_PAGESIZE__PS_WIDTH 16U
+#define XHC_PAGESIZE__PS_RESETVALUE 0x0000U
+#define XHC_PAGESIZE_WIDTH 32U
+#define XHC_PAGESIZE__WIDTH 32U
+#define XHC_PAGESIZE_ALL_L 31U
+#define XHC_PAGESIZE_ALL_R 0U
+#define XHC_PAGESIZE__ALL_L 31U
+#define XHC_PAGESIZE__ALL_R 0U
+#define XHC_PAGESIZE_DATAMASK 0xffffffffU
+#define XHC_PAGESIZE_RDWRMASK 0x00000000U
+#define XHC_PAGESIZE_RESETVALUE 0x00000000U
+
+#define XHC_DNCTRL_OFFSET 0x034U
+#define XHC_DNCTRL_BASE 0x034U
+#define XHC_DNCTRL__reserved_L 31U
+#define XHC_DNCTRL__reserved_R 16U
+#define XHC_DNCTRL__reserved_WIDTH 16U
+#define XHC_DNCTRL__reserved_RESETVALUE 0x0000U
+#define XHC_DNCTRL__DNE_L 15U
+#define XHC_DNCTRL__DNE_R 0U
+#define XHC_DNCTRL__DNE_WIDTH 16U
+#define XHC_DNCTRL__DNE_RESETVALUE 0x0000U
+#define XHC_DNCTRL_WIDTH 32U
+#define XHC_DNCTRL__WIDTH 32U
+#define XHC_DNCTRL_ALL_L 31U
+#define XHC_DNCTRL_ALL_R 0U
+#define XHC_DNCTRL__ALL_L 31U
+#define XHC_DNCTRL__ALL_R 0U
+#define XHC_DNCTRL_DATAMASK 0xffffffffU
+#define XHC_DNCTRL_RDWRMASK 0x00000000U
+#define XHC_DNCTRL_RESETVALUE 0x00000000U
+
+#define XHC_CRCRL_OFFSET 0x038U
+#define XHC_CRCRL_BASE 0x038U
+#define XHC_CRCRL__CRPL_L 31U
+#define XHC_CRCRL__CRPL_R 6U
+#define XHC_CRCRL__CRPL_WIDTH 26U
+#define XHC_CRCRL__CRPL_RESETVALUE 0x0U
+#define XHC_CRCRL__reserved_L 5U
+#define XHC_CRCRL__reserved_R 4U
+#define XHC_CRCRL__reserved_WIDTH 2U
+#define XHC_CRCRL__reserved_RESETVALUE 0x0U
+#define XHC_CRCRL__CRR 3U
+#define XHC_CRCRL__CRR_L 3U
+#define XHC_CRCRL__CRR_R 3U
+#define XHC_CRCRL__CRR_WIDTH 1U
+#define XHC_CRCRL__CRR_RESETVALUE 0x0U
+#define XHC_CRCRL__CA 2U
+#define XHC_CRCRL__CA_L 2U
+#define XHC_CRCRL__CA_R 2U
+#define XHC_CRCRL__CA_WIDTH 1U
+#define XHC_CRCRL__CA_RESETVALUE 0x0U
+#define XHC_CRCRL__CS 1U
+#define XHC_CRCRL__CS_L 1U
+#define XHC_CRCRL__CS_R 1U
+#define XHC_CRCRL__CS_WIDTH 1U
+#define XHC_CRCRL__CS_RESETVALUE 0x0U
+#define XHC_CRCRL__RCS 0U
+#define XHC_CRCRL__RCS_L 0U
+#define XHC_CRCRL__RCS_R 0U
+#define XHC_CRCRL__RCS_WIDTH 1U
+#define XHC_CRCRL__RCS_RESETVALUE 0x0U
+#define XHC_CRCRL_WIDTH 32U
+#define XHC_CRCRL__WIDTH 32U
+#define XHC_CRCRL_ALL_L 31U
+#define XHC_CRCRL_ALL_R 0U
+#define XHC_CRCRL__ALL_L 31U
+#define XHC_CRCRL__ALL_R 0U
+#define XHC_CRCRL_DATAMASK 0xffffffffU
+#define XHC_CRCRL_RDWRMASK 0x00000000U
+#define XHC_CRCRL_RESETVALUE 0x00000000U
+
+#define XHC_CRCRH_OFFSET 0x03cU
+#define XHC_CRCRH_BASE 0x03cU
+#define XHC_CRCRH__CRPH_L 31U
+#define XHC_CRCRH__CRPH_R 0U
+#define XHC_CRCRH__CRPH_WIDTH 32U
+#define XHC_CRCRH__CRPH_RESETVALUE 0x00000000U
+#define XHC_CRCRH_WIDTH 32U
+#define XHC_CRCRH__WIDTH 32U
+#define XHC_CRCRH_ALL_L 31U
+#define XHC_CRCRH_ALL_R 0U
+#define XHC_CRCRH__ALL_L 31U
+#define XHC_CRCRH__ALL_R 0U
+#define XHC_CRCRH_DATAMASK 0xffffffffU
+#define XHC_CRCRH_RDWRMASK 0x00000000U
+#define XHC_CRCRH_RESETVALUE 0x00000000U
+
+#define XHC_DCBAAPL_OFFSET 0x050U
+#define XHC_DCBAAPL_BASE 0x050U
+#define XHC_DCBAAPL__DCAL_L 31U
+#define XHC_DCBAAPL__DCAL_R 6U
+#define XHC_DCBAAPL__DCAL_WIDTH 26U
+#define XHC_DCBAAPL__DCAL_RESETVALUE 0x0U
+
+#define XHC_DCBAAPL__reserved_L 5U
+#define XHC_DCBAAPL__reserved_R 0U
+#define XHC_DCBAAPL__reserved_WIDTH 6U
+#define XHC_DCBAAPL__reserved_RESETVALUE 0x0U
+#define XHC_DCBAAPL_WIDTH 32U
+#define XHC_DCBAAPL__WIDTH 32U
+#define XHC_DCBAAPL_ALL_L 31U
+#define XHC_DCBAAPL_ALL_R 0U
+#define XHC_DCBAAPL__ALL_L 31U
+#define XHC_DCBAAPL__ALL_R 0U
+#define XHC_DCBAAPL_DATAMASK 0xffffffffU
+#define XHC_DCBAAPL_RDWRMASK 0x00000000U
+#define XHC_DCBAAPL_RESETVALUE 0x00000000U
+
+#define XHC_DCBAAPH_OFFSET 0x054U
+#define XHC_DCBAAPH_BASE 0x054U
+#define XHC_DCBAAPH__DCAH_L 31U
+#define XHC_DCBAAPH__DCAH_R 0U
+#define XHC_DCBAAPH__DCAH_WIDTH 32U
+#define XHC_DCBAAPH__DCAH_RESETVALUE 0x00000000U
+#define XHC_DCBAAPH_WIDTH 32U
+#define XHC_DCBAAPH__WIDTH 32U
+#define XHC_DCBAAPH_ALL_L 31U
+#define XHC_DCBAAPH_ALL_R 0U
+#define XHC_DCBAAPH__ALL_L 31U
+#define XHC_DCBAAPH__ALL_R 0U
+#define XHC_DCBAAPH_DATAMASK 0xffffffffU
+#define XHC_DCBAAPH_RDWRMASK 0x00000000U
+#define XHC_DCBAAPH_RESETVALUE 0x00000000U
+
+#define XHC_CONFIG_OFFSET 0x058U
+#define XHC_CONFIG_BASE 0x058U
+#define XHC_CONFIG__reserved_L 31U
+#define XHC_CONFIG__reserved_R 10U
+#define XHC_CONFIG__reserved_WIDTH 22U
+#define XHC_CONFIG__reserved_RESETVALUE 0x0U
+#define XHC_CONFIG__CIE 9U
+#define XHC_CONFIG__CIE_L 9U
+#define XHC_CONFIG__CIE_R 9U
+#define XHC_CONFIG__CIE_WIDTH 1U
+#define XHC_CONFIG__CIE_RESETVALUE 0x0U
+#define XHC_CONFIG__U3E 8U
+#define XHC_CONFIG__U3E_L 8U
+#define XHC_CONFIG__U3E_R 8U
+#define XHC_CONFIG__U3E_WIDTH 1U
+#define XHC_CONFIG__U3E_RESETVALUE 0x0U
+#define XHC_CONFIG__MSE_L 7U
+#define XHC_CONFIG__MSE_R 0U
+#define XHC_CONFIG__MSE_WIDTH 8U
+#define XHC_CONFIG__MSE_RESETVALUE 0x00U
+#define XHC_CONFIG_WIDTH 32U
+#define XHC_CONFIG__WIDTH 32U
+#define XHC_CONFIG_ALL_L 31U
+#define XHC_CONFIG_ALL_R 0U
+#define XHC_CONFIG__ALL_L 31U
+#define XHC_CONFIG__ALL_R 0U
+#define XHC_CONFIG_DATAMASK 0xffffffffU
+#define XHC_CONFIG_RDWRMASK 0x00000000U
+#define XHC_CONFIG_RESETVALUE 0x00000000U
+
+#define XHC_PORTSC1_OFFSET 0x420U
+#define XHC_PORTSC1_BASE 0x420U
+
+#define XHC_PORTSC1__WPR_L 31U
+#define XHC_PORTSC1__WPR_R 31U
+#define XHC_PORTSC1__WPR_WIDTH 1U
+#define XHC_PORTSC1__WPR_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__DNR_L 30U
+#define XHC_PORTSC1__DNR_R 30U
+#define XHC_PORTSC1__DNR_WIDTH 1U
+#define XHC_PORTSC1__DNR_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__WOE_L 27U
+#define XHC_PORTSC1__WOE_R 27U
+#define XHC_PORTSC1__WOE_WIDTH 1U
+#define XHC_PORTSC1__WOE_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__WDE_L 26U
+#define XHC_PORTSC1__WDE_R 26U
+#define XHC_PORTSC1__WDE_WIDTH 1U
+#define XHC_PORTSC1__WDE_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__WCE_L 25U
+#define XHC_PORTSC1__WCE_R 25U
+#define XHC_PORTSC1__WCE_WIDTH 1U
+#define XHC_PORTSC1__WCE_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__CAS_L 24U
+#define XHC_PORTSC1__CAS_R 24U
+#define XHC_PORTSC1__CAS_WIDTH 1U
+#define XHC_PORTSC1__CAS_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__CEC_L 23U
+#define XHC_PORTSC1__CEC_R 23U
+#define XHC_PORTSC1__CEC_WIDTH 1U
+#define XHC_PORTSC1__CEC_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__PLC_L 22U
+#define XHC_PORTSC1__PLC_R 22U
+#define XHC_PORTSC1__PLC_WIDTH 1U
+#define XHC_PORTSC1__PLC_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__PRC_L 21U
+#define XHC_PORTSC1__PRC_R 21U
+#define XHC_PORTSC1__PRC_WIDTH 1U
+#define XHC_PORTSC1__PRC_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__OCC_L 20U
+#define XHC_PORTSC1__OCC_R 20U
+#define XHC_PORTSC1__OCC_WIDTH 1U
+#define XHC_PORTSC1__OCC_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__WRC_L 19U
+#define XHC_PORTSC1__WRC_R 19U
+#define XHC_PORTSC1__WRC_WIDTH 1U
+#define XHC_PORTSC1__WRC_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__PEC_L 18U
+#define XHC_PORTSC1__PEC_R 18U
+#define XHC_PORTSC1__PEC_WIDTH 1U
+#define XHC_PORTSC1__PEC_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__CSC_L 17U
+#define XHC_PORTSC1__CSC_R 17U
+#define XHC_PORTSC1__CSC_WIDTH 1U
+#define XHC_PORTSC1__CSC_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__LWS_L 16U
+#define XHC_PORTSC1__LWS_R 16U
+#define XHC_PORTSC1__LWS_WIDTH 1U
+#define XHC_PORTSC1__LWS_RESETVALUE 0x0U
+#define XHC_PORTSC1__PIC_L 15U
+#define XHC_PORTSC1__PIC_R 14U
+#define XHC_PORTSC1__PIC_WIDTH 2U
+#define XHC_PORTSC1__PIC_RESETVALUE 0x0U
+#define XHC_PORTSC1__PS_L 13U
+#define XHC_PORTSC1__PS_R 10U
+#define XHC_PORTSC1__PS_WIDTH 4U
+#define XHC_PORTSC1__PS_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__PP_L 9U
+#define XHC_PORTSC1__PP_R 9U
+#define XHC_PORTSC1__PP_WIDTH 1U
+#define XHC_PORTSC1__PP_RESETVALUE 0x0U
+#define XHC_PORTSC1__PLS_L 8U
+#define XHC_PORTSC1__PLS_R 5U
+#define XHC_PORTSC1__PLS_WIDTH 4U
+#define XHC_PORTSC1__PLS_RESETVALUE 0x5U
+
+#define XHC_PORTSC1__PRST_L 4U
+#define XHC_PORTSC1__PRST_R 4U
+#define XHC_PORTSC1__PRST_WIDTH 1U
+#define XHC_PORTSC1__PRST_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__OCA_L 3U
+#define XHC_PORTSC1__OCA_R 3U
+#define XHC_PORTSC1__OCA_WIDTH 1U
+#define XHC_PORTSC1__OCA_RESETVALUE 0x0U
+#define XHC_PORTSC1__reserved 2U
+#define XHC_PORTSC1__reserved_L 2U
+#define XHC_PORTSC1__reserved_R 2U
+#define XHC_PORTSC1__reserved_WIDTH 1U
+#define XHC_PORTSC1__reserved_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__PED_L 1U
+#define XHC_PORTSC1__PED_R 1U
+#define XHC_PORTSC1__PED_WIDTH 1U
+#define XHC_PORTSC1__PED_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__CCS_L 0U
+#define XHC_PORTSC1__CCS_R 0U
+#define XHC_PORTSC1__CCS_WIDTH 1U
+#define XHC_PORTSC1__CCS_RESETVALUE 0x0U
+#define XHC_PORTSC1__RESERVED_L 29U
+#define XHC_PORTSC1__RESERVED_R 28U
+#define XHC_PORTSC1_WIDTH 32U
+#define XHC_PORTSC1__WIDTH 32U
+#define XHC_PORTSC1_ALL_L 31U
+#define XHC_PORTSC1_ALL_R 0U
+#define XHC_PORTSC1__ALL_L 31U
+#define XHC_PORTSC1__ALL_R 0U
+#define XHC_PORTSC1_DATAMASK 0xcfffffffU
+#define XHC_PORTSC1_RDWRMASK 0x30000000U
+#define XHC_PORTSC1_RESETVALUE 0x000000a0U
+
+#define XHC_PORTPM1_OFFSET 0x424U
+#define XHC_PORTPM1_BASE 0x424U
+#define XHC_PORTPM1__reserved_L 31U
+#define XHC_PORTPM1__reserved_R 17U
+#define XHC_PORTPM1__reserved_WIDTH 15U
+#define XHC_PORTPM1__reserved_RESETVALUE 0x0U
+#define XHC_PORTPM1__FLA 16U
+#define XHC_PORTPM1__FLA_L 16U
+#define XHC_PORTPM1__FLA_R 16U
+#define XHC_PORTPM1__FLA_WIDTH 1U
+#define XHC_PORTPM1__FLA_RESETVALUE 0x0U
+#define XHC_PORTPM1__U2T_L 15U
+#define XHC_PORTPM1__U2T_R 8U
+#define XHC_PORTPM1__U2T_WIDTH 8U
+#define XHC_PORTPM1__U2T_RESETVALUE 0x00U
+#define XHC_PORTPM1__U1T_L 7U
+#define XHC_PORTPM1__U1T_R 0U
+#define XHC_PORTPM1__U1T_WIDTH 8U
+#define XHC_PORTPM1__U1T_RESETVALUE 0x00U
+#define XHC_PORTPM1_WIDTH 32U
+#define XHC_PORTPM1__WIDTH 32U
+#define XHC_PORTPM1_ALL_L 31U
+#define XHC_PORTPM1_ALL_R 0U
+#define XHC_PORTPM1__ALL_L 31U
+#define XHC_PORTPM1__ALL_R 0U
+#define XHC_PORTPM1_DATAMASK 0xffffffffU
+#define XHC_PORTPM1_RDWRMASK 0x00000000U
+#define XHC_PORTPM1_RESETVALUE 0x00000000U
+
+#define XHC_PORTLC1_OFFSET 0x428U
+#define XHC_PORTLC1_BASE 0x428U
+#define XHC_PORTLC1__reserved_L 31U
+#define XHC_PORTLC1__reserved_R 0U
+#define XHC_PORTLC1__reserved_WIDTH 32U
+#define XHC_PORTLC1__reserved_RESETVALUE 0x00000000U
+#define XHC_PORTLC1_WIDTH 32U
+#define XHC_PORTLC1__WIDTH 32U
+#define XHC_PORTLC1_ALL_L 31U
+#define XHC_PORTLC1_ALL_R 0U
+#define XHC_PORTLC1__ALL_L 31U
+#define XHC_PORTLC1__ALL_R 0U
+#define XHC_PORTLC1_DATAMASK 0xffffffffU
+#define XHC_PORTLC1_RDWRMASK 0x00000000U
+#define XHC_PORTLC1_RESETVALUE 0x00000000U
+
+#define XHC_PORTSC2_OFFSET 0x430U
+#define XHC_PORTSC2_BASE 0x430U
+#define XHC_PORTSC2__WPR 31U
+#define XHC_PORTSC2__WPR_L 31U
+#define XHC_PORTSC2__WPR_R 31U
+#define XHC_PORTSC2__WPR_WIDTH 1U
+#define XHC_PORTSC2__WPR_RESETVALUE 0x0U
+#define XHC_PORTSC2__DNR 30U
+#define XHC_PORTSC2__DNR_L 30U
+#define XHC_PORTSC2__DNR_R 30U
+#define XHC_PORTSC2__DNR_WIDTH 1U
+#define XHC_PORTSC2__DNR_RESETVALUE 0x0U
+#define XHC_PORTSC2__WOE 27U
+#define XHC_PORTSC2__WOE_L 27U
+#define XHC_PORTSC2__WOE_R 27U
+#define XHC_PORTSC2__WOE_WIDTH 1U
+#define XHC_PORTSC2__WOE_RESETVALUE 0x0U
+#define XHC_PORTSC2__WDE 26U
+#define XHC_PORTSC2__WDE_L 26U
+#define XHC_PORTSC2__WDE_R 26U
+#define XHC_PORTSC2__WDE_WIDTH 1U
+#define XHC_PORTSC2__WDE_RESETVALUE 0x0U
+#define XHC_PORTSC2__WCE 25U
+#define XHC_PORTSC2__WCE_L 25U
+#define XHC_PORTSC2__WCE_R 25U
+#define XHC_PORTSC2__WCE_WIDTH 1U
+#define XHC_PORTSC2__WCE_RESETVALUE 0x0U
+#define XHC_PORTSC2__CAS 24U
+#define XHC_PORTSC2__CAS_L 24U
+#define XHC_PORTSC2__CAS_R 24U
+#define XHC_PORTSC2__CAS_WIDTH 1U
+#define XHC_PORTSC2__CAS_RESETVALUE 0x0U
+#define XHC_PORTSC2__CEC 23U
+#define XHC_PORTSC2__CEC_L 23U
+#define XHC_PORTSC2__CEC_R 23U
+#define XHC_PORTSC2__CEC_WIDTH 1U
+#define XHC_PORTSC2__CEC_RESETVALUE 0x0U
+#define XHC_PORTSC2__PLC 22U
+#define XHC_PORTSC2__PLC_L 22U
+#define XHC_PORTSC2__PLC_R 22U
+#define XHC_PORTSC2__PLC_WIDTH 1U
+#define XHC_PORTSC2__PLC_RESETVALUE 0x0U
+#define XHC_PORTSC2__PRC 21U
+#define XHC_PORTSC2__PRC_L 21U
+#define XHC_PORTSC2__PRC_R 21U
+#define XHC_PORTSC2__PRC_WIDTH 1U
+#define XHC_PORTSC2__PRC_RESETVALUE 0x0U
+#define XHC_PORTSC2__OCC 20U
+#define XHC_PORTSC2__OCC_L 20U
+#define XHC_PORTSC2__OCC_R 20U
+#define XHC_PORTSC2__OCC_WIDTH 1U
+#define XHC_PORTSC2__OCC_RESETVALUE 0x0U
+#define XHC_PORTSC2__WRC 19U
+#define XHC_PORTSC2__WRC_L 19U
+#define XHC_PORTSC2__WRC_R 19U
+#define XHC_PORTSC2__WRC_WIDTH 1U
+#define XHC_PORTSC2__WRC_RESETVALUE 0x0U
+#define XHC_PORTSC2__PEC 18U
+#define XHC_PORTSC2__PEC_L 18U
+#define XHC_PORTSC2__PEC_R 18U
+#define XHC_PORTSC2__PEC_WIDTH 1U
+#define XHC_PORTSC2__PEC_RESETVALUE 0x0U
+#define XHC_PORTSC2__CSC 17U
+#define XHC_PORTSC2__CSC_L 17U
+#define XHC_PORTSC2__CSC_R 17U
+#define XHC_PORTSC2__CSC_WIDTH 1U
+#define XHC_PORTSC2__CSC_RESETVALUE 0x0U
+#define XHC_PORTSC2__LWS 16U
+#define XHC_PORTSC2__LWS_L 16U
+#define XHC_PORTSC2__LWS_R 16U
+#define XHC_PORTSC2__LWS_WIDTH 1U
+#define XHC_PORTSC2__LWS_RESETVALUE 0x0U
+#define XHC_PORTSC2__PIC_L 15U
+#define XHC_PORTSC2__PIC_R 14U
+#define XHC_PORTSC2__PIC_WIDTH 2U
+#define XHC_PORTSC2__PIC_RESETVALUE 0x0U
+#define XHC_PORTSC2__PS_L 13U
+#define XHC_PORTSC2__PS_R 10U
+#define XHC_PORTSC2__PS_WIDTH 4U
+#define XHC_PORTSC2__PS_RESETVALUE 0x0U
+#define XHC_PORTSC2__PP 9U
+#define XHC_PORTSC2__PP_L 9U
+#define XHC_PORTSC2__PP_R 9U
+#define XHC_PORTSC2__PP_WIDTH 1U
+#define XHC_PORTSC2__PP_RESETVALUE 0x0U
+#define XHC_PORTSC2__PLS_L 8U
+#define XHC_PORTSC2__PLS_R 5U
+#define XHC_PORTSC2__PLS_WIDTH 4U
+#define XHC_PORTSC2__PLS_RESETVALUE 0x5U
+
+#define XHC_PORTSC2__PRST_L 4U
+#define XHC_PORTSC2__PRST_R 4U
+#define XHC_PORTSC2__PRST_WIDTH 1U
+#define XHC_PORTSC2__PRST_RESETVALUE 0x0U
+#define XHC_PORTSC2__OCA 3U
+#define XHC_PORTSC2__OCA_L 3U
+#define XHC_PORTSC2__OCA_R 3U
+#define XHC_PORTSC2__OCA_WIDTH 1U
+#define XHC_PORTSC2__OCA_RESETVALUE 0x0U
+#define XHC_PORTSC2__reserved 2U
+#define XHC_PORTSC2__reserved_L 2U
+#define XHC_PORTSC2__reserved_R 2U
+#define XHC_PORTSC2__reserved_WIDTH 1U
+#define XHC_PORTSC2__reserved_RESETVALUE 0x0U
+#define XHC_PORTSC2__PED 1U
+#define XHC_PORTSC2__PED_L 1U
+#define XHC_PORTSC2__PED_R 1U
+#define XHC_PORTSC2__PED_WIDTH 1U
+#define XHC_PORTSC2__PED_RESETVALUE 0x0U
+#define XHC_PORTSC2__CCS 0U
+#define XHC_PORTSC2__CCS_L 0U
+#define XHC_PORTSC2__CCS_R 0U
+#define XHC_PORTSC2__CCS_WIDTH 1U
+#define XHC_PORTSC2__CCS_RESETVALUE 0x0U
+#define XHC_PORTSC2__RESERVED_L 29U
+#define XHC_PORTSC2__RESERVED_R 28U
+#define XHC_PORTSC2_WIDTH 32U
+#define XHC_PORTSC2__WIDTH 32U
+#define XHC_PORTSC2_ALL_L 31U
+#define XHC_PORTSC2_ALL_R 0U
+#define XHC_PORTSC2__ALL_L 31U
+#define XHC_PORTSC2__ALL_R 0U
+#define XHC_PORTSC2_DATAMASK 0xcfffffffU
+#define XHC_PORTSC2_RDWRMASK 0x30000000U
+#define XHC_PORTSC2_RESETVALUE 0x000000a0U
+
+#define XHC_PORTPM2_OFFSET 0x434U
+#define XHC_PORTPM2_BASE 0x434U
+#define XHC_PORTPM2__PTC_L 31U
+#define XHC_PORTPM2__PTC_R 28U
+#define XHC_PORTPM2__PTC_WIDTH 4U
+#define XHC_PORTPM2__PTC_RESETVALUE 0x0U
+#define XHC_PORTPM2__reserved_L 27U
+#define XHC_PORTPM2__reserved_R 17U
+#define XHC_PORTPM2__reserved_WIDTH 11U
+#define XHC_PORTPM2__reserved_RESETVALUE 0x0U
+#define XHC_PORTPM2__HLE 16U
+#define XHC_PORTPM2__HLE_L 16U
+#define XHC_PORTPM2__HLE_R 16U
+#define XHC_PORTPM2__HLE_WIDTH 1U
+#define XHC_PORTPM2__HLE_RESETVALUE 0x0U
+#define XHC_PORTPM2__L1DS_L 15U
+#define XHC_PORTPM2__L1DS_R 8U
+#define XHC_PORTPM2__L1DS_WIDTH 8U
+#define XHC_PORTPM2__L1DS_RESETVALUE 0x00U
+#define XHC_PORTPM2__BESL_L 7U
+#define XHC_PORTPM2__BESL_R 4U
+#define XHC_PORTPM2__BESL_WIDTH 4U
+#define XHC_PORTPM2__BESL_RESETVALUE 0x0U
+#define XHC_PORTPM2__RWE 3U
+#define XHC_PORTPM2__RWE_L 3U
+#define XHC_PORTPM2__RWE_R 3U
+#define XHC_PORTPM2__RWE_WIDTH 1U
+#define XHC_PORTPM2__RWE_RESETVALUE 0x0U
+#define XHC_PORTPM2__L1S_L 2U
+#define XHC_PORTPM2__L1S_R 0U
+#define XHC_PORTPM2__L1S_WIDTH 3U
+#define XHC_PORTPM2__L1S_RESETVALUE 0x0U
+#define XHC_PORTPM2_WIDTH 32U
+#define XHC_PORTPM2__WIDTH 32U
+#define XHC_PORTPM2_ALL_L 31U
+#define XHC_PORTPM2_ALL_R 0U
+#define XHC_PORTPM2__ALL_L 31U
+#define XHC_PORTPM2__ALL_R 0U
+#define XHC_PORTPM2_DATAMASK 0xffffffffU
+#define XHC_PORTPM2_RDWRMASK 0x00000000U
+#define XHC_PORTPM2_RESETVALUE 0x00000000U
+
+#define XHC_PORTLC2_OFFSET 0x43cU
+#define XHC_PORTLC2_BASE 0x43cU
+#define XHC_PORTLC2__reserved_L 31U
+#define XHC_PORTLC2__reserved_R 14U
+#define XHC_PORTLC2__reserved_WIDTH 18U
+#define XHC_PORTLC2__reserved_RESETVALUE 0x0U
+#define XHC_PORTLC2__BESLD_L 13U
+#define XHC_PORTLC2__BESLD_R 10U
+#define XHC_PORTLC2__BESLD_WIDTH 4U
+#define XHC_PORTLC2__BESLD_RESETVALUE 0x0U
+#define XHC_PORTLC2__L1T_L 9U
+#define XHC_PORTLC2__L1T_R 2U
+#define XHC_PORTLC2__L1T_WIDTH 8U
+#define XHC_PORTLC2__L1T_RESETVALUE 0x00U
+#define XHC_PORTLC2__HIRDM_L 1U
+#define XHC_PORTLC2__HIRDM_R 0U
+#define XHC_PORTLC2__HIRDM_WIDTH 2U
+#define XHC_PORTLC2__HIRDM_RESETVALUE 0x0U
+#define XHC_PORTLC2_WIDTH 32U
+#define XHC_PORTLC2__WIDTH 32U
+#define XHC_PORTLC2_ALL_L 31U
+#define XHC_PORTLC2_ALL_R 0U
+#define XHC_PORTLC2__ALL_L 31U
+#define XHC_PORTLC2__ALL_R 0U
+#define XHC_PORTLC2_DATAMASK 0xffffffffU
+#define XHC_PORTLC2_RDWRMASK 0x00000000U
+#define XHC_PORTLC2_RESETVALUE 0x00000000U
+
+#define XHC_PORTSC3_OFFSET 0x440U
+#define XHC_PORTSC3_BASE 0x440U
+#define XHC_PORTSC3__WPR 31U
+#define XHC_PORTSC3__WPR_L 31U
+#define XHC_PORTSC3__WPR_R 31U
+#define XHC_PORTSC3__WPR_WIDTH 1U
+#define XHC_PORTSC3__WPR_RESETVALUE 0x0U
+#define XHC_PORTSC3__DNR 30U
+#define XHC_PORTSC3__DNR_L 30U
+#define XHC_PORTSC3__DNR_R 30U
+#define XHC_PORTSC3__DNR_WIDTH 1U
+#define XHC_PORTSC3__DNR_RESETVALUE 0x0U
+#define XHC_PORTSC3__WOE 27U
+#define XHC_PORTSC3__WOE_L 27U
+#define XHC_PORTSC3__WOE_R 27U
+#define XHC_PORTSC3__WOE_WIDTH 1U
+#define XHC_PORTSC3__WOE_RESETVALUE 0x0U
+#define XHC_PORTSC3__WDE 26U
+#define XHC_PORTSC3__WDE_L 26U
+#define XHC_PORTSC3__WDE_R 26U
+#define XHC_PORTSC3__WDE_WIDTH 1U
+#define XHC_PORTSC3__WDE_RESETVALUE 0x0U
+#define XHC_PORTSC3__WCE 25U
+#define XHC_PORTSC3__WCE_L 25U
+#define XHC_PORTSC3__WCE_R 25U
+#define XHC_PORTSC3__WCE_WIDTH 1U
+#define XHC_PORTSC3__WCE_RESETVALUE 0x0U
+#define XHC_PORTSC3__CAS 24U
+#define XHC_PORTSC3__CAS_L 24U
+#define XHC_PORTSC3__CAS_R 24U
+#define XHC_PORTSC3__CAS_WIDTH 1U
+#define XHC_PORTSC3__CAS_RESETVALUE 0x0U
+#define XHC_PORTSC3__CEC 23U
+#define XHC_PORTSC3__CEC_L 23U
+#define XHC_PORTSC3__CEC_R 23U
+#define XHC_PORTSC3__CEC_WIDTH 1U
+#define XHC_PORTSC3__CEC_RESETVALUE 0x0U
+#define XHC_PORTSC3__PLC 22U
+#define XHC_PORTSC3__PLC_L 22U
+#define XHC_PORTSC3__PLC_R 22U
+#define XHC_PORTSC3__PLC_WIDTH 1U
+#define XHC_PORTSC3__PLC_RESETVALUE 0x0U
+#define XHC_PORTSC3__PRC 21U
+#define XHC_PORTSC3__PRC_L 21U
+#define XHC_PORTSC3__PRC_R 21U
+#define XHC_PORTSC3__PRC_WIDTH 1U
+#define XHC_PORTSC3__PRC_RESETVALUE 0x0U
+#define XHC_PORTSC3__OCC 20U
+#define XHC_PORTSC3__OCC_L 20U
+#define XHC_PORTSC3__OCC_R 20U
+#define XHC_PORTSC3__OCC_WIDTH 1U
+#define XHC_PORTSC3__OCC_RESETVALUE 0x0U
+#define XHC_PORTSC3__WRC 19U
+#define XHC_PORTSC3__WRC_L 19U
+#define XHC_PORTSC3__WRC_R 19U
+#define XHC_PORTSC3__WRC_WIDTH 1U
+#define XHC_PORTSC3__WRC_RESETVALUE 0x0U
+#define XHC_PORTSC3__PEC 18U
+#define XHC_PORTSC3__PEC_L 18U
+#define XHC_PORTSC3__PEC_R 18U
+#define XHC_PORTSC3__PEC_WIDTH 1U
+#define XHC_PORTSC3__PEC_RESETVALUE 0x0U
+#define XHC_PORTSC3__CSC 17U
+#define XHC_PORTSC3__CSC_L 17U
+#define XHC_PORTSC3__CSC_R 17U
+#define XHC_PORTSC3__CSC_WIDTH 1U
+#define XHC_PORTSC3__CSC_RESETVALUE 0x0U
+#define XHC_PORTSC3__LWS 16U
+#define XHC_PORTSC3__LWS_L 16U
+#define XHC_PORTSC3__LWS_R 16U
+#define XHC_PORTSC3__LWS_WIDTH 1U
+#define XHC_PORTSC3__LWS_RESETVALUE 0x0U
+#define XHC_PORTSC3__PIC_L 15U
+#define XHC_PORTSC3__PIC_R 14U
+#define XHC_PORTSC3__PIC_WIDTH 2U
+#define XHC_PORTSC3__PIC_RESETVALUE 0x0U
+#define XHC_PORTSC3__PS_L 13U
+#define XHC_PORTSC3__PS_R 10U
+#define XHC_PORTSC3__PS_WIDTH 4U
+#define XHC_PORTSC3__PS_RESETVALUE 0x0U
+#define XHC_PORTSC3__PP 9U
+#define XHC_PORTSC3__PP_L 9U
+#define XHC_PORTSC3__PP_R 9U
+#define XHC_PORTSC3__PP_WIDTH 1U
+#define XHC_PORTSC3__PP_RESETVALUE 0x0U
+#define XHC_PORTSC3__PLS_L 8U
+#define XHC_PORTSC3__PLS_R 5U
+#define XHC_PORTSC3__PLS_WIDTH 4U
+#define XHC_PORTSC3__PLS_RESETVALUE 0x5U
+#define XHC_PORTSC3__PR 4U
+#define XHC_PORTSC3__PR_L 4U
+#define XHC_PORTSC3__PR_R 4U
+#define XHC_PORTSC3__PR_WIDTH 1U
+#define XHC_PORTSC3__PR_RESETVALUE 0x0U
+#define XHC_PORTSC3__OCA 3U
+#define XHC_PORTSC3__OCA_L 3U
+#define XHC_PORTSC3__OCA_R 3U
+#define XHC_PORTSC3__OCA_WIDTH 1U
+#define XHC_PORTSC3__OCA_RESETVALUE 0x0U
+#define XHC_PORTSC3__reserved 2U
+#define XHC_PORTSC3__reserved_L 2U
+#define XHC_PORTSC3__reserved_R 2U
+#define XHC_PORTSC3__reserved_WIDTH 1U
+#define XHC_PORTSC3__reserved_RESETVALUE 0x0U
+#define XHC_PORTSC3__PED 1U
+#define XHC_PORTSC3__PED_L 1U
+#define XHC_PORTSC3__PED_R 1U
+#define XHC_PORTSC3__PED_WIDTH 1U
+#define XHC_PORTSC3__PED_RESETVALUE 0x0U
+#define XHC_PORTSC3__CCS 0U
+#define XHC_PORTSC3__CCS_L 0U
+#define XHC_PORTSC3__CCS_R 0U
+#define XHC_PORTSC3__CCS_WIDTH 1U
+#define XHC_PORTSC3__CCS_RESETVALUE 0x0U
+#define XHC_PORTSC3__RESERVED_L 29U
+#define XHC_PORTSC3__RESERVED_R 28U
+#define XHC_PORTSC3_WIDTH 32U
+#define XHC_PORTSC3__WIDTH 32U
+#define XHC_PORTSC3_ALL_L 31U
+#define XHC_PORTSC3_ALL_R 0U
+#define XHC_PORTSC3__ALL_L 31U
+#define XHC_PORTSC3__ALL_R 0U
+#define XHC_PORTSC3_DATAMASK 0xcfffffffU
+#define XHC_PORTSC3_RDWRMASK 0x30000000U
+#define XHC_PORTSC3_RESETVALUE 0x000000a0U
+
+#define XHC_PORTPM3_OFFSET 0x444U
+#define XHC_PORTPM3_BASE 0x444U
+#define XHC_PORTPM3__PTC_L 31U
+#define XHC_PORTPM3__PTC_R 28U
+#define XHC_PORTPM3__PTC_WIDTH 4U
+#define XHC_PORTPM3__PTC_RESETVALUE 0x0U
+#define XHC_PORTPM3__reserved_L 27U
+#define XHC_PORTPM3__reserved_R 17U
+#define XHC_PORTPM3__reserved_WIDTH 11U
+#define XHC_PORTPM3__reserved_RESETVALUE 0x0U
+#define XHC_PORTPM3__HLE 16U
+#define XHC_PORTPM3__HLE_L 16U
+#define XHC_PORTPM3__HLE_R 16U
+#define XHC_PORTPM3__HLE_WIDTH 1U
+#define XHC_PORTPM3__HLE_RESETVALUE 0x0U
+#define XHC_PORTPM3__L1DS_L 15U
+#define XHC_PORTPM3__L1DS_R 8U
+#define XHC_PORTPM3__L1DS_WIDTH 8U
+#define XHC_PORTPM3__L1DS_RESETVALUE 0x00U
+#define XHC_PORTPM3__BESL_L 7U
+#define XHC_PORTPM3__BESL_R 4U
+#define XHC_PORTPM3__BESL_WIDTH 4U
+#define XHC_PORTPM3__BESL_RESETVALUE 0x0U
+#define XHC_PORTPM3__RWE 3U
+#define XHC_PORTPM3__RWE_L 3U
+#define XHC_PORTPM3__RWE_R 3U
+#define XHC_PORTPM3__RWE_WIDTH 1U
+#define XHC_PORTPM3__RWE_RESETVALUE 0x0U
+#define XHC_PORTPM3__L1S_L 2U
+#define XHC_PORTPM3__L1S_R 0U
+#define XHC_PORTPM3__L1S_WIDTH 3U
+#define XHC_PORTPM3__L1S_RESETVALUE 0x0U
+#define XHC_PORTPM3_WIDTH 32U
+#define XHC_PORTPM3__WIDTH 32U
+#define XHC_PORTPM3_ALL_L 31U
+#define XHC_PORTPM3_ALL_R 0U
+#define XHC_PORTPM3__ALL_L 31U
+#define XHC_PORTPM3__ALL_R 0U
+#define XHC_PORTPM3_DATAMASK 0xffffffffU
+#define XHC_PORTPM3_RDWRMASK 0x00000000U
+#define XHC_PORTPM3_RESETVALUE 0x00000000U
+
+#define XHC_PORTLI3_OFFSET 0x44cU
+#define XHC_PORTLI3_BASE 0x44cU
+#define XHC_PORTLI3__reserved_L 31U
+#define XHC_PORTLI3__reserved_R 0U
+#define XHC_PORTLI3__reserved_WIDTH 32U
+#define XHC_PORTLI3__reserved_RESETVALUE 0x00000000U
+#define XHC_PORTLI3_WIDTH 32U
+#define XHC_PORTLI3__WIDTH 32U
+#define XHC_PORTLI3_ALL_L 31U
+#define XHC_PORTLI3_ALL_R 0U
+#define XHC_PORTLI3__ALL_L 31U
+#define XHC_PORTLI3__ALL_R 0U
+#define XHC_PORTLI3_DATAMASK 0xffffffffU
+#define XHC_PORTLI3_RDWRMASK 0x00000000U
+#define XHC_PORTLI3_RESETVALUE 0x00000000U
+
+#define XHC_MFINDEX_OFFSET 0x4a0U
+#define XHC_MFINDEX_BASE 0x4a0U
+#define XHC_MFINDEX__reserved_L 31U
+#define XHC_MFINDEX__reserved_R 14U
+#define XHC_MFINDEX__reserved_WIDTH 18U
+#define XHC_MFINDEX__reserved_RESETVALUE 0x0U
+#define XHC_MFINDEX__MFI_L 13U
+#define XHC_MFINDEX__MFI_R 0U
+#define XHC_MFINDEX__MFI_WIDTH 14U
+#define XHC_MFINDEX__MFI_RESETVALUE 0x0U
+#define XHC_MFINDEX_WIDTH 32U
+#define XHC_MFINDEX__WIDTH 32U
+#define XHC_MFINDEX_ALL_L 31U
+#define XHC_MFINDEX_ALL_R 0U
+#define XHC_MFINDEX__ALL_L 31U
+#define XHC_MFINDEX__ALL_R 0U
+#define XHC_MFINDEX_DATAMASK 0xffffffffU
+#define XHC_MFINDEX_RDWRMASK 0x00000000U
+#define XHC_MFINDEX_RESETVALUE 0x00000000U
+
+#define XHC_IMAN0_OFFSET 0x4c0U
+#define XHC_IMAN0_BASE 0x4c0U
+#define XHC_IMAN0__reserved_L 31U
+#define XHC_IMAN0__reserved_R 2U
+#define XHC_IMAN0__reserved_WIDTH 30U
+#define XHC_IMAN0__reserved_RESETVALUE 0x0U
+#define XHC_IMAN0__IE 1U
+#define XHC_IMAN0__IE_L 1U
+#define XHC_IMAN0__IE_R 1U
+#define XHC_IMAN0__IE_WIDTH 1U
+#define XHC_IMAN0__IE_RESETVALUE 0x0U
+#define XHC_IMAN0__IP 0U
+#define XHC_IMAN0__IP_L 0U
+#define XHC_IMAN0__IP_R 0U
+#define XHC_IMAN0__IP_WIDTH 1U
+#define XHC_IMAN0__IP_RESETVALUE 0x0U
+#define XHC_IMAN0_WIDTH 32U
+#define XHC_IMAN0__WIDTH 32U
+#define XHC_IMAN0_ALL_L 31U
+#define XHC_IMAN0_ALL_R 0U
+#define XHC_IMAN0__ALL_L 31U
+#define XHC_IMAN0__ALL_R 0U
+#define XHC_IMAN0_DATAMASK 0xffffffffU
+#define XHC_IMAN0_RDWRMASK 0x00000000U
+#define XHC_IMAN0_RESETVALUE 0x00000000U
+
+#define XHC_IMOD0_OFFSET 0x4c4U
+#define XHC_IMOD0_BASE 0x4c4U
+#define XHC_IMOD0__IMODC_L 31U
+#define XHC_IMOD0__IMODC_R 16U
+#define XHC_IMOD0__IMODC_WIDTH 16U
+#define XHC_IMOD0__IMODC_RESETVALUE 0x0000U
+#define XHC_IMOD0__IMODI_L 15U
+#define XHC_IMOD0__IMODI_R 0U
+#define XHC_IMOD0__IMODI_WIDTH 16U
+#define XHC_IMOD0__IMODI_RESETVALUE 0x4000U
+#define XHC_IMOD0_WIDTH 32U
+#define XHC_IMOD0__WIDTH 32U
+#define XHC_IMOD0_ALL_L 31U
+#define XHC_IMOD0_ALL_R 0U
+#define XHC_IMOD0__ALL_L 31U
+#define XHC_IMOD0__ALL_R 0U
+#define XHC_IMOD0_DATAMASK 0xffffffffU
+#define XHC_IMOD0_RDWRMASK 0x00000000U
+#define XHC_IMOD0_RESETVALUE 0x00004000U
+
+#define XHC_ERSTSZ0_OFFSET 0x4c8U
+#define XHC_ERSTSZ0_BASE 0x4c8U
+#define XHC_ERSTSZ0__reserved_L 31U
+#define XHC_ERSTSZ0__reserved_R 16U
+#define XHC_ERSTSZ0__reserved_WIDTH 16U
+#define XHC_ERSTSZ0__reserved_RESETVALUE 0x0000U
+#define XHC_ERSTSZ0__TSZ_L 15U
+#define XHC_ERSTSZ0__TSZ_R 0U
+#define XHC_ERSTSZ0__TSZ_WIDTH 16U
+#define XHC_ERSTSZ0__TSZ_RESETVALUE 0x0000U
+#define XHC_ERSTSZ0_WIDTH 32U
+#define XHC_ERSTSZ0__WIDTH 32U
+#define XHC_ERSTSZ0_ALL_L 31U
+#define XHC_ERSTSZ0_ALL_R 0U
+#define XHC_ERSTSZ0__ALL_L 31U
+#define XHC_ERSTSZ0__ALL_R 0U
+#define XHC_ERSTSZ0_DATAMASK 0xffffffffU
+#define XHC_ERSTSZ0_RDWRMASK 0x00000000U
+#define XHC_ERSTSZ0_RESETVALUE 0x00000000U
+
+#define XHC_ERSTBAL0_OFFSET 0x4d0U
+#define XHC_ERSTBAL0_BASE 0x4d0U
+#define XHC_ERSTBAL0__BAL_L 31U
+#define XHC_ERSTBAL0__BAL_R 4U
+#define XHC_ERSTBAL0__BAL_WIDTH 28U
+#define XHC_ERSTBAL0__BAL_RESETVALUE 0x0000000U
+#define XHC_ERSTBAL0__reserved_L 3U
+#define XHC_ERSTBAL0__reserved_R 0U
+#define XHC_ERSTBAL0__reserved_WIDTH 4U
+#define XHC_ERSTBAL0__reserved_RESETVALUE 0x0U
+#define XHC_ERSTBAL0_WIDTH 32U
+#define XHC_ERSTBAL0__WIDTH 32U
+#define XHC_ERSTBAL0_ALL_L 31U
+#define XHC_ERSTBAL0_ALL_R 0U
+#define XHC_ERSTBAL0__ALL_L 31U
+#define XHC_ERSTBAL0__ALL_R 0U
+#define XHC_ERSTBAL0_DATAMASK 0xffffffffU
+#define XHC_ERSTBAL0_RDWRMASK 0x00000000U
+#define XHC_ERSTBAL0_RESETVALUE 0x00000000U
+
+#define XHC_ERSTBAH0_OFFSET 0x4d4U
+#define XHC_ERSTBAH0_BASE 0x4d4U
+#define XHC_ERSTBAH0__BAH_L 31U
+#define XHC_ERSTBAH0__BAH_R 0U
+#define XHC_ERSTBAH0__BAH_WIDTH 32U
+#define XHC_ERSTBAH0__BAH_RESETVALUE 0x00000000U
+#define XHC_ERSTBAH0_WIDTH 32U
+#define XHC_ERSTBAH0__WIDTH 32U
+#define XHC_ERSTBAH0_ALL_L 31U
+#define XHC_ERSTBAH0_ALL_R 0U
+#define XHC_ERSTBAH0__ALL_L 31U
+#define XHC_ERSTBAH0__ALL_R 0U
+#define XHC_ERSTBAH0_DATAMASK 0xffffffffU
+#define XHC_ERSTBAH0_RDWRMASK 0x00000000U
+#define XHC_ERSTBAH0_RESETVALUE 0x00000000U
+
+#define XHC_ERDPL0_OFFSET 0x4d8U
+#define XHC_ERDPL0_BASE 0x4d8U
+#define XHC_ERDPL0__DPL_L 31U
+#define XHC_ERDPL0__DPL_R 4U
+#define XHC_ERDPL0__DPL_WIDTH 28U
+#define XHC_ERDPL0__DPL_RESETVALUE 0x0000000U
+#define XHC_ERDPL0__EHB 3U
+#define XHC_ERDPL0__EHB_L 3U
+#define XHC_ERDPL0__EHB_R 3U
+#define XHC_ERDPL0__EHB_WIDTH 1U
+#define XHC_ERDPL0__EHB_RESETVALUE 0x0U
+#define XHC_ERDPL0__DESI_L 2U
+#define XHC_ERDPL0__DESI_R 0U
+#define XHC_ERDPL0__DESI_WIDTH 3U
+#define XHC_ERDPL0__DESI_RESETVALUE 0x0U
+#define XHC_ERDPL0_WIDTH 32U
+#define XHC_ERDPL0__WIDTH 32U
+#define XHC_ERDPL0_ALL_L 31U
+#define XHC_ERDPL0_ALL_R 0U
+#define XHC_ERDPL0__ALL_L 31U
+#define XHC_ERDPL0__ALL_R 0U
+#define XHC_ERDPL0_DATAMASK 0xffffffffU
+#define XHC_ERDPL0_RDWRMASK 0x00000000U
+#define XHC_ERDPL0_RESETVALUE 0x00000000U
+
+#define XHC_ERDPH0_OFFSET 0x4dcU
+#define XHC_ERDPH0_BASE 0x4dcU
+#define XHC_ERDPH0__DPH_L 31U
+#define XHC_ERDPH0__DPH_R 0U
+#define XHC_ERDPH0__DPH_WIDTH 32U
+#define XHC_ERDPH0__DPH_RESETVALUE 0x00000000U
+#define XHC_ERDPH0_WIDTH 32U
+#define XHC_ERDPH0__WIDTH 32U
+#define XHC_ERDPH0_ALL_L 31U
+#define XHC_ERDPH0_ALL_R 0U
+#define XHC_ERDPH0__ALL_L 31U
+#define XHC_ERDPH0__ALL_R 0U
+#define XHC_ERDPH0_DATAMASK 0xffffffffU
+#define XHC_ERDPH0_RDWRMASK 0x00000000U
+#define XHC_ERDPH0_RESETVALUE 0x00000000U
+
+#define XHC_IMAN1_OFFSET 0x4e0U
+#define XHC_IMAN1_BASE 0x4e0U
+#define XHC_IMAN1__reserved_L 31U
+#define XHC_IMAN1__reserved_R 2U
+#define XHC_IMAN1__reserved_WIDTH 30U
+#define XHC_IMAN1__reserved_RESETVALUE 0x0U
+#define XHC_IMAN1__IE 1U
+#define XHC_IMAN1__IE_L 1U
+#define XHC_IMAN1__IE_R 1U
+#define XHC_IMAN1__IE_WIDTH 1U
+#define XHC_IMAN1__IE_RESETVALUE 0x0U
+#define XHC_IMAN1__IP 0U
+#define XHC_IMAN1__IP_L 0U
+#define XHC_IMAN1__IP_R 0U
+#define XHC_IMAN1__IP_WIDTH 1U
+#define XHC_IMAN1__IP_RESETVALUE 0x0U
+#define XHC_IMAN1_WIDTH 32U
+#define XHC_IMAN1__WIDTH 32U
+#define XHC_IMAN1_ALL_L 31U
+#define XHC_IMAN1_ALL_R 0U
+#define XHC_IMAN1__ALL_L 31U
+#define XHC_IMAN1__ALL_R 0U
+#define XHC_IMAN1_DATAMASK 0xffffffffU
+#define XHC_IMAN1_RDWRMASK 0x00000000U
+#define XHC_IMAN1_RESETVALUE 0x00000000U
+
+#define XHC_IMOD1_OFFSET 0x4e4U
+#define XHC_IMOD1_BASE 0x4e4U
+#define XHC_IMOD1__IMODC_L 31U
+#define XHC_IMOD1__IMODC_R 16U
+#define XHC_IMOD1__IMODC_WIDTH 16U
+#define XHC_IMOD1__IMODC_RESETVALUE 0x0000U
+#define XHC_IMOD1__IMODI_L 15U
+#define XHC_IMOD1__IMODI_R 0U
+#define XHC_IMOD1__IMODI_WIDTH 16U
+#define XHC_IMOD1__IMODI_RESETVALUE 0x4000U
+#define XHC_IMOD1_WIDTH 32U
+#define XHC_IMOD1__WIDTH 32U
+#define XHC_IMOD1_ALL_L 31U
+#define XHC_IMOD1_ALL_R 0U
+#define XHC_IMOD1__ALL_L 31U
+#define XHC_IMOD1__ALL_R 0U
+#define XHC_IMOD1_DATAMASK 0xffffffffU
+#define XHC_IMOD1_RDWRMASK 0x00000000U
+#define XHC_IMOD1_RESETVALUE 0x00004000U
+
+#define XHC_ERSTSZ1_OFFSET 0x4e8U
+#define XHC_ERSTSZ1_BASE 0x4e8U
+#define XHC_ERSTSZ1__reserved_L 31U
+#define XHC_ERSTSZ1__reserved_R 16U
+#define XHC_ERSTSZ1__reserved_WIDTH 16U
+#define XHC_ERSTSZ1__reserved_RESETVALUE 0x0000U
+#define XHC_ERSTSZ1__TSZ_L 15U
+#define XHC_ERSTSZ1__TSZ_R 0U
+#define XHC_ERSTSZ1__TSZ_WIDTH 16U
+#define XHC_ERSTSZ1__TSZ_RESETVALUE 0x0000U
+#define XHC_ERSTSZ1_WIDTH 32U
+#define XHC_ERSTSZ1__WIDTH 32U
+#define XHC_ERSTSZ1_ALL_L 31U
+#define XHC_ERSTSZ1_ALL_R 0U
+#define XHC_ERSTSZ1__ALL_L 31U
+#define XHC_ERSTSZ1__ALL_R 0U
+#define XHC_ERSTSZ1_DATAMASK 0xffffffffU
+#define XHC_ERSTSZ1_RDWRMASK 0x00000000U
+#define XHC_ERSTSZ1_RESETVALUE 0x00000000U
+
+#define XHC_ERSTBAL1_OFFSET 0x4f0U
+#define XHC_ERSTBAL1_BASE 0x4f0U
+#define XHC_ERSTBAL1__BAL_L 31U
+#define XHC_ERSTBAL1__BAL_R 4U
+#define XHC_ERSTBAL1__BAL_WIDTH 28U
+#define XHC_ERSTBAL1__BAL_RESETVALUE 0x0000000U
+#define XHC_ERSTBAL1__reserved_L 3U
+#define XHC_ERSTBAL1__reserved_R 0U
+#define XHC_ERSTBAL1__reserved_WIDTH 4U
+#define XHC_ERSTBAL1__reserved_RESETVALUE 0x0U
+#define XHC_ERSTBAL1_WIDTH 32U
+#define XHC_ERSTBAL1__WIDTH 32U
+#define XHC_ERSTBAL1_ALL_L 31U
+#define XHC_ERSTBAL1_ALL_R 0U
+#define XHC_ERSTBAL1__ALL_L 31U
+#define XHC_ERSTBAL1__ALL_R 0U
+#define XHC_ERSTBAL1_DATAMASK 0xffffffffU
+#define XHC_ERSTBAL1_RDWRMASK 0x00000000U
+#define XHC_ERSTBAL1_RESETVALUE 0x00000000U
+
+#define XHC_ERSTBAH1_OFFSET 0x4f4U
+#define XHC_ERSTBAH1_BASE 0x4f4U
+#define XHC_ERSTBAH1__BAH_L 31U
+#define XHC_ERSTBAH1__BAH_R 0U
+#define XHC_ERSTBAH1__BAH_WIDTH 32U
+#define XHC_ERSTBAH1__BAH_RESETVALUE 0x00000000U
+#define XHC_ERSTBAH1_WIDTH 32U
+#define XHC_ERSTBAH1__WIDTH 32U
+#define XHC_ERSTBAH1_ALL_L 31U
+#define XHC_ERSTBAH1_ALL_R 0U
+#define XHC_ERSTBAH1__ALL_L 31U
+#define XHC_ERSTBAH1__ALL_R 0U
+#define XHC_ERSTBAH1_DATAMASK 0xffffffffU
+#define XHC_ERSTBAH1_RDWRMASK 0x00000000U
+#define XHC_ERSTBAH1_RESETVALUE 0x00000000U
+
+#define XHC_ERDPL1_OFFSET 0x4f8U
+#define XHC_ERDPL1_BASE 0x4f8U
+#define XHC_ERDPL1__DPL_L 31U
+#define XHC_ERDPL1__DPL_R 4U
+#define XHC_ERDPL1__DPL_WIDTH 28U
+#define XHC_ERDPL1__DPL_RESETVALUE 0x0000000U
+#define XHC_ERDPL1__EHB 3U
+#define XHC_ERDPL1__EHB_L 3U
+#define XHC_ERDPL1__EHB_R 3U
+#define XHC_ERDPL1__EHB_WIDTH 1U
+#define XHC_ERDPL1__EHB_RESETVALUE 0x0U
+#define XHC_ERDPL1__DESI_L 2U
+#define XHC_ERDPL1__DESI_R 0U
+#define XHC_ERDPL1__DESI_WIDTH 3U
+#define XHC_ERDPL1__DESI_RESETVALUE 0x0U
+#define XHC_ERDPL1_WIDTH 32U
+#define XHC_ERDPL1__WIDTH 32U
+#define XHC_ERDPL1_ALL_L 31U
+#define XHC_ERDPL1_ALL_R 0U
+#define XHC_ERDPL1__ALL_L 31U
+#define XHC_ERDPL1__ALL_R 0U
+#define XHC_ERDPL1_DATAMASK 0xffffffffU
+#define XHC_ERDPL1_RDWRMASK 0x00000000U
+#define XHC_ERDPL1_RESETVALUE 0x00000000U
+
+#define XHC_ERDPH1_OFFSET 0x4fcU
+#define XHC_ERDPH1_BASE 0x4fcU
+#define XHC_ERDPH1__DPH_L 31U
+#define XHC_ERDPH1__DPH_R 0U
+#define XHC_ERDPH1__DPH_WIDTH 32U
+#define XHC_ERDPH1__DPH_RESETVALUE 0x00000000U
+#define XHC_ERDPH1_WIDTH 32U
+#define XHC_ERDPH1__WIDTH 32U
+#define XHC_ERDPH1_ALL_L 31U
+#define XHC_ERDPH1_ALL_R 0U
+#define XHC_ERDPH1__ALL_L 31U
+#define XHC_ERDPH1__ALL_R 0U
+#define XHC_ERDPH1_DATAMASK 0xffffffffU
+#define XHC_ERDPH1_RDWRMASK 0x00000000U
+#define XHC_ERDPH1_RESETVALUE 0x00000000U
+
+#define XHC_DBLCMD_OFFSET 0x8c0U
+#define XHC_DBLCMD_BASE 0x8c0U
+#define XHC_DBLCMD__SID_L 31U
+#define XHC_DBLCMD__SID_R 16U
+#define XHC_DBLCMD__SID_WIDTH 16U
+#define XHC_DBLCMD__SID_RESETVALUE 0x0000U
+#define XHC_DBLCMD__reserved_L 15U
+#define XHC_DBLCMD__reserved_R 8U
+#define XHC_DBLCMD__reserved_WIDTH 8U
+#define XHC_DBLCMD__reserved_RESETVALUE 0x00U
+#define XHC_DBLCMD__TGT_L 7U
+#define XHC_DBLCMD__TGT_R 0U
+#define XHC_DBLCMD__TGT_WIDTH 8U
+#define XHC_DBLCMD__TGT_RESETVALUE 0x00U
+#define XHC_DBLCMD_WIDTH 32U
+#define XHC_DBLCMD__WIDTH 32U
+#define XHC_DBLCMD_ALL_L 31U
+#define XHC_DBLCMD_ALL_R 0U
+#define XHC_DBLCMD__ALL_L 31U
+#define XHC_DBLCMD__ALL_R 0U
+#define XHC_DBLCMD_DATAMASK 0xffffffffU
+#define XHC_DBLCMD_RDWRMASK 0x00000000U
+#define XHC_DBLCMD_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX1_OFFSET 0x8c4U
+#define XHC_DBLDVX1_BASE 0x8c4U
+#define XHC_DBLDVX1__SID_L 31U
+#define XHC_DBLDVX1__SID_R 16U
+#define XHC_DBLDVX1__SID_WIDTH 16U
+#define XHC_DBLDVX1__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX1__reserved_L 15U
+#define XHC_DBLDVX1__reserved_R 8U
+#define XHC_DBLDVX1__reserved_WIDTH 8U
+#define XHC_DBLDVX1__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX1__TGT_L 7U
+#define XHC_DBLDVX1__TGT_R 0U
+#define XHC_DBLDVX1__TGT_WIDTH 8U
+#define XHC_DBLDVX1__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX1_WIDTH 32U
+#define XHC_DBLDVX1__WIDTH 32U
+#define XHC_DBLDVX1_ALL_L 31U
+#define XHC_DBLDVX1_ALL_R 0U
+#define XHC_DBLDVX1__ALL_L 31U
+#define XHC_DBLDVX1__ALL_R 0U
+#define XHC_DBLDVX1_DATAMASK 0xffffffffU
+#define XHC_DBLDVX1_RDWRMASK 0x00000000U
+#define XHC_DBLDVX1_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX2_OFFSET 0x8c8U
+#define XHC_DBLDVX2_BASE 0x8c8U
+#define XHC_DBLDVX2__SID_L 31U
+#define XHC_DBLDVX2__SID_R 16U
+#define XHC_DBLDVX2__SID_WIDTH 16U
+#define XHC_DBLDVX2__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX2__reserved_L 15U
+#define XHC_DBLDVX2__reserved_R 8U
+#define XHC_DBLDVX2__reserved_WIDTH 8U
+#define XHC_DBLDVX2__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX2__TGT_L 7U
+#define XHC_DBLDVX2__TGT_R 0U
+#define XHC_DBLDVX2__TGT_WIDTH 8U
+#define XHC_DBLDVX2__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX2_WIDTH 32U
+#define XHC_DBLDVX2__WIDTH 32U
+#define XHC_DBLDVX2_ALL_L 31U
+#define XHC_DBLDVX2_ALL_R 0U
+#define XHC_DBLDVX2__ALL_L 31U
+#define XHC_DBLDVX2__ALL_R 0U
+#define XHC_DBLDVX2_DATAMASK 0xffffffffU
+#define XHC_DBLDVX2_RDWRMASK 0x00000000U
+#define XHC_DBLDVX2_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX3_OFFSET 0x8ccU
+#define XHC_DBLDVX3_BASE 0x8ccU
+#define XHC_DBLDVX3__SID_L 31U
+#define XHC_DBLDVX3__SID_R 16U
+#define XHC_DBLDVX3__SID_WIDTH 16U
+#define XHC_DBLDVX3__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX3__reserved_L 15U
+#define XHC_DBLDVX3__reserved_R 8U
+#define XHC_DBLDVX3__reserved_WIDTH 8U
+#define XHC_DBLDVX3__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX3__TGT_L 7U
+#define XHC_DBLDVX3__TGT_R 0U
+#define XHC_DBLDVX3__TGT_WIDTH 8U
+#define XHC_DBLDVX3__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX3_WIDTH 32U
+#define XHC_DBLDVX3__WIDTH 32U
+#define XHC_DBLDVX3_ALL_L 31U
+#define XHC_DBLDVX3_ALL_R 0U
+#define XHC_DBLDVX3__ALL_L 31U
+#define XHC_DBLDVX3__ALL_R 0U
+#define XHC_DBLDVX3_DATAMASK 0xffffffffU
+#define XHC_DBLDVX3_RDWRMASK 0x00000000U
+#define XHC_DBLDVX3_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX4_OFFSET 0x8d0U
+#define XHC_DBLDVX4_BASE 0x8d0U
+#define XHC_DBLDVX4__SID_L 31U
+#define XHC_DBLDVX4__SID_R 16U
+#define XHC_DBLDVX4__SID_WIDTH 16U
+#define XHC_DBLDVX4__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX4__reserved_L 15U
+#define XHC_DBLDVX4__reserved_R 8U
+#define XHC_DBLDVX4__reserved_WIDTH 8U
+#define XHC_DBLDVX4__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX4__TGT_L 7U
+#define XHC_DBLDVX4__TGT_R 0U
+#define XHC_DBLDVX4__TGT_WIDTH 8U
+#define XHC_DBLDVX4__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX4_WIDTH 32U
+#define XHC_DBLDVX4__WIDTH 32U
+#define XHC_DBLDVX4_ALL_L 31U
+#define XHC_DBLDVX4_ALL_R 0U
+#define XHC_DBLDVX4__ALL_L 31U
+#define XHC_DBLDVX4__ALL_R 0U
+#define XHC_DBLDVX4_DATAMASK 0xffffffffU
+#define XHC_DBLDVX4_RDWRMASK 0x00000000U
+#define XHC_DBLDVX4_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX5_OFFSET 0x8d4U
+#define XHC_DBLDVX5_BASE 0x8d4U
+#define XHC_DBLDVX5__SID_L 31U
+#define XHC_DBLDVX5__SID_R 16U
+#define XHC_DBLDVX5__SID_WIDTH 16U
+#define XHC_DBLDVX5__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX5__reserved_L 15U
+#define XHC_DBLDVX5__reserved_R 8U
+#define XHC_DBLDVX5__reserved_WIDTH 8U
+#define XHC_DBLDVX5__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX5__TGT_L 7U
+#define XHC_DBLDVX5__TGT_R 0U
+#define XHC_DBLDVX5__TGT_WIDTH 8U
+#define XHC_DBLDVX5__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX5_WIDTH 32U
+#define XHC_DBLDVX5__WIDTH 32U
+#define XHC_DBLDVX5_ALL_L 31U
+#define XHC_DBLDVX5_ALL_R 0U
+#define XHC_DBLDVX5__ALL_L 31U
+#define XHC_DBLDVX5__ALL_R 0U
+#define XHC_DBLDVX5_DATAMASK 0xffffffffU
+#define XHC_DBLDVX5_RDWRMASK 0x00000000U
+#define XHC_DBLDVX5_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX6_OFFSET 0x8d8U
+#define XHC_DBLDVX6_BASE 0x8d8U
+#define XHC_DBLDVX6__SID_L 31U
+#define XHC_DBLDVX6__SID_R 16U
+#define XHC_DBLDVX6__SID_WIDTH 16U
+#define XHC_DBLDVX6__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX6__reserved_L 15U
+#define XHC_DBLDVX6__reserved_R 8U
+#define XHC_DBLDVX6__reserved_WIDTH 8U
+#define XHC_DBLDVX6__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX6__TGT_L 7U
+#define XHC_DBLDVX6__TGT_R 0U
+#define XHC_DBLDVX6__TGT_WIDTH 8U
+#define XHC_DBLDVX6__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX6_WIDTH 32U
+#define XHC_DBLDVX6__WIDTH 32U
+#define XHC_DBLDVX6_ALL_L 31U
+#define XHC_DBLDVX6_ALL_R 0U
+#define XHC_DBLDVX6__ALL_L 31U
+#define XHC_DBLDVX6__ALL_R 0U
+#define XHC_DBLDVX6_DATAMASK 0xffffffffU
+#define XHC_DBLDVX6_RDWRMASK 0x00000000U
+#define XHC_DBLDVX6_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX7_OFFSET 0x8dcU
+#define XHC_DBLDVX7_BASE 0x8dcU
+#define XHC_DBLDVX7__SID_L 31U
+#define XHC_DBLDVX7__SID_R 16U
+#define XHC_DBLDVX7__SID_WIDTH 16U
+#define XHC_DBLDVX7__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX7__reserved_L 15U
+#define XHC_DBLDVX7__reserved_R 8U
+#define XHC_DBLDVX7__reserved_WIDTH 8U
+#define XHC_DBLDVX7__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX7__TGT_L 7U
+#define XHC_DBLDVX7__TGT_R 0U
+#define XHC_DBLDVX7__TGT_WIDTH 8U
+#define XHC_DBLDVX7__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX7_WIDTH 32U
+#define XHC_DBLDVX7__WIDTH 32U
+#define XHC_DBLDVX7_ALL_L 31U
+#define XHC_DBLDVX7_ALL_R 0U
+#define XHC_DBLDVX7__ALL_L 31U
+#define XHC_DBLDVX7__ALL_R 0U
+#define XHC_DBLDVX7_DATAMASK 0xffffffffU
+#define XHC_DBLDVX7_RDWRMASK 0x00000000U
+#define XHC_DBLDVX7_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX8_OFFSET 0x8e0U
+#define XHC_DBLDVX8_BASE 0x8e0U
+#define XHC_DBLDVX8__SID_L 31U
+#define XHC_DBLDVX8__SID_R 16U
+#define XHC_DBLDVX8__SID_WIDTH 16U
+#define XHC_DBLDVX8__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX8__reserved_L 15U
+#define XHC_DBLDVX8__reserved_R 8U
+#define XHC_DBLDVX8__reserved_WIDTH 8U
+#define XHC_DBLDVX8__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX8__TGT_L 7U
+#define XHC_DBLDVX8__TGT_R 0U
+#define XHC_DBLDVX8__TGT_WIDTH 8U
+#define XHC_DBLDVX8__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX8_WIDTH 32U
+#define XHC_DBLDVX8__WIDTH 32U
+#define XHC_DBLDVX8_ALL_L 31U
+#define XHC_DBLDVX8_ALL_R 0U
+#define XHC_DBLDVX8__ALL_L 31U
+#define XHC_DBLDVX8__ALL_R 0U
+#define XHC_DBLDVX8_DATAMASK 0xffffffffU
+#define XHC_DBLDVX8_RDWRMASK 0x00000000U
+#define XHC_DBLDVX8_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX9_OFFSET 0x8e4U
+#define XHC_DBLDVX9_BASE 0x8e4U
+#define XHC_DBLDVX9__SID_L 31U
+#define XHC_DBLDVX9__SID_R 16U
+#define XHC_DBLDVX9__SID_WIDTH 16U
+#define XHC_DBLDVX9__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX9__reserved_L 15U
+#define XHC_DBLDVX9__reserved_R 8U
+#define XHC_DBLDVX9__reserved_WIDTH 8U
+#define XHC_DBLDVX9__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX9__TGT_L 7U
+#define XHC_DBLDVX9__TGT_R 0U
+#define XHC_DBLDVX9__TGT_WIDTH 8U
+#define XHC_DBLDVX9__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX9_WIDTH 32U
+#define XHC_DBLDVX9__WIDTH 32U
+#define XHC_DBLDVX9_ALL_L 31U
+#define XHC_DBLDVX9_ALL_R 0U
+#define XHC_DBLDVX9__ALL_L 31U
+#define XHC_DBLDVX9__ALL_R 0U
+#define XHC_DBLDVX9_DATAMASK 0xffffffffU
+#define XHC_DBLDVX9_RDWRMASK 0x00000000U
+#define XHC_DBLDVX9_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX10_OFFSET 0x8e8U
+#define XHC_DBLDVX10_BASE 0x8e8U
+#define XHC_DBLDVX10__SID_L 31U
+#define XHC_DBLDVX10__SID_R 16U
+#define XHC_DBLDVX10__SID_WIDTH 16U
+#define XHC_DBLDVX10__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX10__reserved_L 15U
+#define XHC_DBLDVX10__reserved_R 8U
+#define XHC_DBLDVX10__reserved_WIDTH 8U
+#define XHC_DBLDVX10__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX10__TGT_L 7U
+#define XHC_DBLDVX10__TGT_R 0U
+#define XHC_DBLDVX10__TGT_WIDTH 8U
+#define XHC_DBLDVX10__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX10_WIDTH 32U
+#define XHC_DBLDVX10__WIDTH 32U
+#define XHC_DBLDVX10_ALL_L 31U
+#define XHC_DBLDVX10_ALL_R 0U
+#define XHC_DBLDVX10__ALL_L 31U
+#define XHC_DBLDVX10__ALL_R 0U
+#define XHC_DBLDVX10_DATAMASK 0xffffffffU
+#define XHC_DBLDVX10_RDWRMASK 0x00000000U
+#define XHC_DBLDVX10_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX11_OFFSET 0x8ecU
+#define XHC_DBLDVX11_BASE 0x8ecU
+#define XHC_DBLDVX11__SID_L 31U
+#define XHC_DBLDVX11__SID_R 16U
+#define XHC_DBLDVX11__SID_WIDTH 16U
+#define XHC_DBLDVX11__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX11__reserved_L 15U
+#define XHC_DBLDVX11__reserved_R 8U
+#define XHC_DBLDVX11__reserved_WIDTH 8U
+#define XHC_DBLDVX11__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX11__TGT_L 7U
+#define XHC_DBLDVX11__TGT_R 0U
+#define XHC_DBLDVX11__TGT_WIDTH 8U
+#define XHC_DBLDVX11__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX11_WIDTH 32U
+#define XHC_DBLDVX11__WIDTH 32U
+#define XHC_DBLDVX11_ALL_L 31U
+#define XHC_DBLDVX11_ALL_R 0U
+#define XHC_DBLDVX11__ALL_L 31U
+#define XHC_DBLDVX11__ALL_R 0U
+#define XHC_DBLDVX11_DATAMASK 0xffffffffU
+#define XHC_DBLDVX11_RDWRMASK 0x00000000U
+#define XHC_DBLDVX11_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX12_OFFSET 0x8f0U
+#define XHC_DBLDVX12_BASE 0x8f0U
+#define XHC_DBLDVX12__SID_L 31U
+#define XHC_DBLDVX12__SID_R 16U
+#define XHC_DBLDVX12__SID_WIDTH 16U
+#define XHC_DBLDVX12__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX12__reserved_L 15U
+#define XHC_DBLDVX12__reserved_R 8U
+#define XHC_DBLDVX12__reserved_WIDTH 8U
+#define XHC_DBLDVX12__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX12__TGT_L 7U
+#define XHC_DBLDVX12__TGT_R 0U
+#define XHC_DBLDVX12__TGT_WIDTH 8U
+#define XHC_DBLDVX12__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX12_WIDTH 32U
+#define XHC_DBLDVX12__WIDTH 32U
+#define XHC_DBLDVX12_ALL_L 31U
+#define XHC_DBLDVX12_ALL_R 0U
+#define XHC_DBLDVX12__ALL_L 31U
+#define XHC_DBLDVX12__ALL_R 0U
+#define XHC_DBLDVX12_DATAMASK 0xffffffffU
+#define XHC_DBLDVX12_RDWRMASK 0x00000000U
+#define XHC_DBLDVX12_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX13_OFFSET 0x8f4U
+#define XHC_DBLDVX13_BASE 0x8f4U
+#define XHC_DBLDVX13__SID_L 31U
+#define XHC_DBLDVX13__SID_R 16U
+#define XHC_DBLDVX13__SID_WIDTH 16U
+#define XHC_DBLDVX13__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX13__reserved_L 15U
+#define XHC_DBLDVX13__reserved_R 8U
+#define XHC_DBLDVX13__reserved_WIDTH 8U
+#define XHC_DBLDVX13__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX13__TGT_L 7U
+#define XHC_DBLDVX13__TGT_R 0U
+#define XHC_DBLDVX13__TGT_WIDTH 8U
+#define XHC_DBLDVX13__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX13_WIDTH 32U
+#define XHC_DBLDVX13__WIDTH 32U
+#define XHC_DBLDVX13_ALL_L 31U
+#define XHC_DBLDVX13_ALL_R 0U
+#define XHC_DBLDVX13__ALL_L 31U
+#define XHC_DBLDVX13__ALL_R 0U
+#define XHC_DBLDVX13_DATAMASK 0xffffffffU
+#define XHC_DBLDVX13_RDWRMASK 0x00000000U
+#define XHC_DBLDVX13_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX14_OFFSET 0x8f8U
+#define XHC_DBLDVX14_BASE 0x8f8U
+#define XHC_DBLDVX14__SID_L 31U
+#define XHC_DBLDVX14__SID_R 16U
+#define XHC_DBLDVX14__SID_WIDTH 16U
+#define XHC_DBLDVX14__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX14__reserved_L 15U
+#define XHC_DBLDVX14__reserved_R 8U
+#define XHC_DBLDVX14__reserved_WIDTH 8U
+#define XHC_DBLDVX14__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX14__TGT_L 7U
+#define XHC_DBLDVX14__TGT_R 0U
+#define XHC_DBLDVX14__TGT_WIDTH 8U
+#define XHC_DBLDVX14__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX14_WIDTH 32U
+#define XHC_DBLDVX14__WIDTH 32U
+#define XHC_DBLDVX14_ALL_L 31U
+#define XHC_DBLDVX14_ALL_R 0U
+#define XHC_DBLDVX14__ALL_L 31U
+#define XHC_DBLDVX14__ALL_R 0U
+#define XHC_DBLDVX14_DATAMASK 0xffffffffU
+#define XHC_DBLDVX14_RDWRMASK 0x00000000U
+#define XHC_DBLDVX14_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX15_OFFSET 0x8fcU
+#define XHC_DBLDVX15_BASE 0x8fcU
+#define XHC_DBLDVX15__SID_L 31U
+#define XHC_DBLDVX15__SID_R 16U
+#define XHC_DBLDVX15__SID_WIDTH 16U
+#define XHC_DBLDVX15__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX15__reserved_L 15U
+#define XHC_DBLDVX15__reserved_R 8U
+#define XHC_DBLDVX15__reserved_WIDTH 8U
+#define XHC_DBLDVX15__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX15__TGT_L 7U
+#define XHC_DBLDVX15__TGT_R 0U
+#define XHC_DBLDVX15__TGT_WIDTH 8U
+#define XHC_DBLDVX15__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX15_WIDTH 32U
+#define XHC_DBLDVX15__WIDTH 32U
+#define XHC_DBLDVX15_ALL_L 31U
+#define XHC_DBLDVX15_ALL_R 0U
+#define XHC_DBLDVX15__ALL_L 31U
+#define XHC_DBLDVX15__ALL_R 0U
+#define XHC_DBLDVX15_DATAMASK 0xffffffffU
+#define XHC_DBLDVX15_RDWRMASK 0x00000000U
+#define XHC_DBLDVX15_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX16_OFFSET 0x900U
+#define XHC_DBLDVX16_BASE 0x900U
+#define XHC_DBLDVX16__SID_L 31U
+#define XHC_DBLDVX16__SID_R 16U
+#define XHC_DBLDVX16__SID_WIDTH 16U
+#define XHC_DBLDVX16__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX16__reserved_L 15U
+#define XHC_DBLDVX16__reserved_R 8U
+#define XHC_DBLDVX16__reserved_WIDTH 8U
+#define XHC_DBLDVX16__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX16__TGT_L 7U
+#define XHC_DBLDVX16__TGT_R 0U
+#define XHC_DBLDVX16__TGT_WIDTH 8U
+#define XHC_DBLDVX16__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX16_WIDTH 32U
+#define XHC_DBLDVX16__WIDTH 32U
+#define XHC_DBLDVX16_ALL_L 31U
+#define XHC_DBLDVX16_ALL_R 0U
+#define XHC_DBLDVX16__ALL_L 31U
+#define XHC_DBLDVX16__ALL_R 0U
+#define XHC_DBLDVX16_DATAMASK 0xffffffffU
+#define XHC_DBLDVX16_RDWRMASK 0x00000000U
+#define XHC_DBLDVX16_RESETVALUE 0x00000000U
+
+#define XHC_ECHSPT3_OFFSET 0x940U
+#define XHC_ECHSPT3_BASE 0x940U
+#define XHC_ECHSPT3__RMAJ_L 31U
+#define XHC_ECHSPT3__RMAJ_R 24U
+#define XHC_ECHSPT3__RMAJ_WIDTH 8U
+#define XHC_ECHSPT3__RMAJ_RESETVALUE 0x00U
+#define XHC_ECHSPT3__RMIN_L 23U
+#define XHC_ECHSPT3__RMIN_R 16U
+#define XHC_ECHSPT3__RMIN_WIDTH 8U
+#define XHC_ECHSPT3__RMIN_RESETVALUE 0x00U
+#define XHC_ECHSPT3__NCP_L 15U
+#define XHC_ECHSPT3__NCP_R 8U
+#define XHC_ECHSPT3__NCP_WIDTH 8U
+#define XHC_ECHSPT3__NCP_RESETVALUE 0x00U
+#define XHC_ECHSPT3__CID_L 7U
+#define XHC_ECHSPT3__CID_R 0U
+#define XHC_ECHSPT3__CID_WIDTH 8U
+#define XHC_ECHSPT3__CID_RESETVALUE 0x02U
+#define XHC_ECHSPT3_WIDTH 32U
+#define XHC_ECHSPT3__WIDTH 32U
+#define XHC_ECHSPT3_ALL_L 31U
+#define XHC_ECHSPT3_ALL_R 0U
+#define XHC_ECHSPT3__ALL_L 31U
+#define XHC_ECHSPT3__ALL_R 0U
+#define XHC_ECHSPT3_DATAMASK 0xffffffffU
+#define XHC_ECHSPT3_RDWRMASK 0x00000000U
+#define XHC_ECHSPT3_RESETVALUE 0x00000002U
+
+#define XHC_PNSTR3_OFFSET 0x944U
+#define XHC_PNSTR3_BASE 0x944U
+#define XHC_PNSTR3__STR_L 31U
+#define XHC_PNSTR3__STR_R 0U
+#define XHC_PNSTR3__STR_WIDTH 32U
+#define XHC_PNSTR3__STR_RESETVALUE 0x20425355U
+#define XHC_PNSTR3_WIDTH 32U
+#define XHC_PNSTR3__WIDTH 32U
+#define XHC_PNSTR3_ALL_L 31U
+#define XHC_PNSTR3_ALL_R 0U
+#define XHC_PNSTR3__ALL_L 31U
+#define XHC_PNSTR3__ALL_R 0U
+#define XHC_PNSTR3_DATAMASK 0xffffffffU
+#define XHC_PNSTR3_RDWRMASK 0x00000000U
+#define XHC_PNSTR3_RESETVALUE 0x20425355U
+
+#define XHC_PSUM3_OFFSET 0x948U
+#define XHC_PSUM3_BASE 0x948U
+#define XHC_PSUM3__PSIC_L 31U
+#define XHC_PSUM3__PSIC_R 28U
+#define XHC_PSUM3__PSIC_WIDTH 4U
+#define XHC_PSUM3__PSIC_RESETVALUE 0x0U
+#define XHC_PSUM3__MHD_L 27U
+#define XHC_PSUM3__MHD_R 25U
+#define XHC_PSUM3__MHD_WIDTH 3U
+#define XHC_PSUM3__MHD_RESETVALUE 0x0U
+#define XHC_PSUM3__BLC 20U
+#define XHC_PSUM3__BLC_L 20U
+#define XHC_PSUM3__BLC_R 20U
+#define XHC_PSUM3__BLC_WIDTH 1U
+#define XHC_PSUM3__BLC_RESETVALUE 0x0U
+#define XHC_PSUM3__HLC 19U
+#define XHC_PSUM3__HLC_L 19U
+#define XHC_PSUM3__HLC_R 19U
+#define XHC_PSUM3__HLC_WIDTH 1U
+#define XHC_PSUM3__HLC_RESETVALUE 0x1U
+#define XHC_PSUM3__IHI 18U
+#define XHC_PSUM3__IHI_L 18U
+#define XHC_PSUM3__IHI_R 18U
+#define XHC_PSUM3__IHI_WIDTH 1U
+#define XHC_PSUM3__IHI_RESETVALUE 0x0U
+#define XHC_PSUM3__HSO 17U
+#define XHC_PSUM3__HSO_L 17U
+#define XHC_PSUM3__HSO_R 17U
+#define XHC_PSUM3__HSO_WIDTH 1U
+#define XHC_PSUM3__HSO_RESETVALUE 0x0U
+#define XHC_PSUM3__reserved 16U
+#define XHC_PSUM3__reserved_L 16U
+#define XHC_PSUM3__reserved_R 16U
+#define XHC_PSUM3__reserved_WIDTH 1U
+#define XHC_PSUM3__reserved_RESETVALUE 0x0U
+#define XHC_PSUM3__CPC_L 15U
+#define XHC_PSUM3__CPC_R 8U
+#define XHC_PSUM3__CPC_WIDTH 8U
+#define XHC_PSUM3__CPC_RESETVALUE 0x00U
+#define XHC_PSUM3__CPO_L 7U
+#define XHC_PSUM3__CPO_R 0U
+#define XHC_PSUM3__CPO_WIDTH 8U
+#define XHC_PSUM3__CPO_RESETVALUE 0x00U
+#define XHC_PSUM3__RESERVED_L 24U
+#define XHC_PSUM3__RESERVED_R 21U
+#define XHC_PSUM3_WIDTH 32U
+#define XHC_PSUM3__WIDTH 32U
+#define XHC_PSUM3_ALL_L 31U
+#define XHC_PSUM3_ALL_R 0U
+#define XHC_PSUM3__ALL_L 31U
+#define XHC_PSUM3__ALL_R 0U
+#define XHC_PSUM3_DATAMASK 0xfe1fffffU
+#define XHC_PSUM3_RDWRMASK 0x01e00000U
+#define XHC_PSUM3_RESETVALUE 0x00080000U
+
+#define XHC_PTSLTYP3_OFFSET 0x94cU
+#define XHC_PTSLTYP3_BASE 0x94cU
+#define XHC_PTSLTYP3__reserved_L 31U
+#define XHC_PTSLTYP3__reserved_R 5U
+#define XHC_PTSLTYP3__reserved_WIDTH 27U
+#define XHC_PTSLTYP3__reserved_RESETVALUE 0x0U
+#define XHC_PTSLTYP3__PST_L 4U
+#define XHC_PTSLTYP3__PST_R 0U
+#define XHC_PTSLTYP3__PST_WIDTH 5U
+#define XHC_PTSLTYP3__PST_RESETVALUE 0x0U
+#define XHC_PTSLTYP3_WIDTH 32U
+#define XHC_PTSLTYP3__WIDTH 32U
+#define XHC_PTSLTYP3_ALL_L 31U
+#define XHC_PTSLTYP3_ALL_R 0U
+#define XHC_PTSLTYP3__ALL_L 31U
+#define XHC_PTSLTYP3__ALL_R 0U
+#define XHC_PTSLTYP3_DATAMASK 0xffffffffU
+#define XHC_PTSLTYP3_RDWRMASK 0x00000000U
+#define XHC_PTSLTYP3_RESETVALUE 0x00000000U
+
+#define XHC_ECHSPT2_OFFSET 0x950U
+#define XHC_ECHSPT2_BASE 0x950U
+#define XHC_ECHSPT2__RMAJ_L 31U
+#define XHC_ECHSPT2__RMAJ_R 24U
+#define XHC_ECHSPT2__RMAJ_WIDTH 8U
+#define XHC_ECHSPT2__RMAJ_RESETVALUE 0x00U
+#define XHC_ECHSPT2__RMIN_L 23U
+#define XHC_ECHSPT2__RMIN_R 16U
+#define XHC_ECHSPT2__RMIN_WIDTH 8U
+#define XHC_ECHSPT2__RMIN_RESETVALUE 0x00U
+#define XHC_ECHSPT2__NCP_L 15U
+#define XHC_ECHSPT2__NCP_R 8U
+#define XHC_ECHSPT2__NCP_WIDTH 8U
+#define XHC_ECHSPT2__NCP_RESETVALUE 0x00U
+#define XHC_ECHSPT2__CID_L 7U
+#define XHC_ECHSPT2__CID_R 0U
+#define XHC_ECHSPT2__CID_WIDTH 8U
+#define XHC_ECHSPT2__CID_RESETVALUE 0x02U
+#define XHC_ECHSPT2_WIDTH 32U
+#define XHC_ECHSPT2__WIDTH 32U
+#define XHC_ECHSPT2_ALL_L 31U
+#define XHC_ECHSPT2_ALL_R 0U
+#define XHC_ECHSPT2__ALL_L 31U
+#define XHC_ECHSPT2__ALL_R 0U
+#define XHC_ECHSPT2_DATAMASK 0xffffffffU
+#define XHC_ECHSPT2_RDWRMASK 0x00000000U
+#define XHC_ECHSPT2_RESETVALUE 0x00000002U
+
+#define XHC_PNSTR2_OFFSET 0x954U
+#define XHC_PNSTR2_BASE 0x954U
+#define XHC_PNSTR2__STR_L 31U
+#define XHC_PNSTR2__STR_R 0U
+#define XHC_PNSTR2__STR_WIDTH 32U
+#define XHC_PNSTR2__STR_RESETVALUE 0x20425355U
+#define XHC_PNSTR2_WIDTH 32U
+#define XHC_PNSTR2__WIDTH 32U
+#define XHC_PNSTR2_ALL_L 31U
+#define XHC_PNSTR2_ALL_R 0U
+#define XHC_PNSTR2__ALL_L 31U
+#define XHC_PNSTR2__ALL_R 0U
+#define XHC_PNSTR2_DATAMASK 0xffffffffU
+#define XHC_PNSTR2_RDWRMASK 0x00000000U
+#define XHC_PNSTR2_RESETVALUE 0x20425355U
+
+#define XHC_PSUM2_OFFSET 0x958U
+#define XHC_PSUM2_BASE 0x958U
+#define XHC_PSUM2__PSIC_L 31U
+#define XHC_PSUM2__PSIC_R 28U
+#define XHC_PSUM2__PSIC_WIDTH 4U
+#define XHC_PSUM2__PSIC_RESETVALUE 0x0U
+#define XHC_PSUM2__MHD_L 27U
+#define XHC_PSUM2__MHD_R 25U
+#define XHC_PSUM2__MHD_WIDTH 3U
+#define XHC_PSUM2__MHD_RESETVALUE 0x0U
+#define XHC_PSUM2__BLC 20U
+#define XHC_PSUM2__BLC_L 20U
+#define XHC_PSUM2__BLC_R 20U
+#define XHC_PSUM2__BLC_WIDTH 1U
+#define XHC_PSUM2__BLC_RESETVALUE 0x0U
+#define XHC_PSUM2__HLC 19U
+#define XHC_PSUM2__HLC_L 19U
+#define XHC_PSUM2__HLC_R 19U
+#define XHC_PSUM2__HLC_WIDTH 1U
+#define XHC_PSUM2__HLC_RESETVALUE 0x1U
+#define XHC_PSUM2__IHI 18U
+#define XHC_PSUM2__IHI_L 18U
+#define XHC_PSUM2__IHI_R 18U
+#define XHC_PSUM2__IHI_WIDTH 1U
+#define XHC_PSUM2__IHI_RESETVALUE 0x0U
+#define XHC_PSUM2__HSO 17U
+#define XHC_PSUM2__HSO_L 17U
+#define XHC_PSUM2__HSO_R 17U
+#define XHC_PSUM2__HSO_WIDTH 1U
+#define XHC_PSUM2__HSO_RESETVALUE 0x0U
+#define XHC_PSUM2__reserved 16U
+#define XHC_PSUM2__reserved_L 16U
+#define XHC_PSUM2__reserved_R 16U
+#define XHC_PSUM2__reserved_WIDTH 1U
+#define XHC_PSUM2__reserved_RESETVALUE 0x0U
+#define XHC_PSUM2__CPC_L 15U
+#define XHC_PSUM2__CPC_R 8U
+#define XHC_PSUM2__CPC_WIDTH 8U
+#define XHC_PSUM2__CPC_RESETVALUE 0x00U
+#define XHC_PSUM2__CPO_L 7U
+#define XHC_PSUM2__CPO_R 0U
+#define XHC_PSUM2__CPO_WIDTH 8U
+#define XHC_PSUM2__CPO_RESETVALUE 0x00U
+#define XHC_PSUM2__RESERVED_L 24U
+#define XHC_PSUM2__RESERVED_R 21U
+#define XHC_PSUM2_WIDTH 32U
+#define XHC_PSUM2__WIDTH 32U
+#define XHC_PSUM2_ALL_L 31U
+#define XHC_PSUM2_ALL_R 0U
+#define XHC_PSUM2__ALL_L 31U
+#define XHC_PSUM2__ALL_R 0U
+#define XHC_PSUM2_DATAMASK 0xfe1fffffU
+#define XHC_PSUM2_RDWRMASK 0x01e00000U
+#define XHC_PSUM2_RESETVALUE 0x00080000U
+
+#define XHC_PTSLTYP2_OFFSET 0x95cU
+#define XHC_PTSLTYP2_BASE 0x95cU
+#define XHC_PTSLTYP2__reserved_L 31U
+#define XHC_PTSLTYP2__reserved_R 5U
+#define XHC_PTSLTYP2__reserved_WIDTH 27U
+#define XHC_PTSLTYP2__reserved_RESETVALUE 0x0U
+#define XHC_PTSLTYP2__PST_L 4U
+#define XHC_PTSLTYP2__PST_R 0U
+#define XHC_PTSLTYP2__PST_WIDTH 5U
+#define XHC_PTSLTYP2__PST_RESETVALUE 0x0U
+#define XHC_PTSLTYP2_WIDTH 32U
+#define XHC_PTSLTYP2__WIDTH 32U
+#define XHC_PTSLTYP2_ALL_L 31U
+#define XHC_PTSLTYP2_ALL_R 0U
+#define XHC_PTSLTYP2__ALL_L 31U
+#define XHC_PTSLTYP2__ALL_R 0U
+#define XHC_PTSLTYP2_DATAMASK 0xffffffffU
+#define XHC_PTSLTYP2_RDWRMASK 0x00000000U
+#define XHC_PTSLTYP2_RESETVALUE 0x00000000U
+
+#define XHC_ECHRSVP_OFFSET 0x960U
+#define XHC_ECHRSVP_BASE 0x960U
+#define XHC_ECHRSVP__reserved_L 31U
+#define XHC_ECHRSVP__reserved_R 16U
+#define XHC_ECHRSVP__reserved_WIDTH 16U
+#define XHC_ECHRSVP__reserved_RESETVALUE 0x0000U
+#define XHC_ECHRSVP__NCP_L 15U
+#define XHC_ECHRSVP__NCP_R 8U
+#define XHC_ECHRSVP__NCP_WIDTH 8U
+#define XHC_ECHRSVP__NCP_RESETVALUE 0x00U
+#define XHC_ECHRSVP__CID_L 7U
+#define XHC_ECHRSVP__CID_R 0U
+#define XHC_ECHRSVP__CID_WIDTH 8U
+#define XHC_ECHRSVP__CID_RESETVALUE 0xffU
+#define XHC_ECHRSVP_WIDTH 32U
+#define XHC_ECHRSVP__WIDTH 32U
+#define XHC_ECHRSVP_ALL_L 31U
+#define XHC_ECHRSVP_ALL_R 0U
+#define XHC_ECHRSVP__ALL_L 31U
+#define XHC_ECHRSVP__ALL_R 0U
+#define XHC_ECHRSVP_DATAMASK 0xffffffffU
+#define XHC_ECHRSVP_RDWRMASK 0x00000000U
+#define XHC_ECHRSVP_RESETVALUE 0x000000ffU
+
+#define XHC_ECHRSVI_OFFSET 0x968U
+#define XHC_ECHRSVI_BASE 0x968U
+#define XHC_ECHRSVI__reserved_L 31U
+#define XHC_ECHRSVI__reserved_R 16U
+#define XHC_ECHRSVI__reserved_WIDTH 16U
+#define XHC_ECHRSVI__reserved_RESETVALUE 0x0000U
+#define XHC_ECHRSVI__NCP_L 15U
+#define XHC_ECHRSVI__NCP_R 8U
+#define XHC_ECHRSVI__NCP_WIDTH 8U
+#define XHC_ECHRSVI__NCP_RESETVALUE 0x00U
+#define XHC_ECHRSVI__CID_L 7U
+#define XHC_ECHRSVI__CID_R 0U
+#define XHC_ECHRSVI__CID_WIDTH 8U
+#define XHC_ECHRSVI__CID_RESETVALUE 0xffU
+#define XHC_ECHRSVI_WIDTH 32U
+#define XHC_ECHRSVI__WIDTH 32U
+#define XHC_ECHRSVI_ALL_L 31U
+#define XHC_ECHRSVI_ALL_R 0U
+#define XHC_ECHRSVI__ALL_L 31U
+#define XHC_ECHRSVI__ALL_R 0U
+#define XHC_ECHRSVI_DATAMASK 0xffffffffU
+#define XHC_ECHRSVI_RDWRMASK 0x00000000U
+#define XHC_ECHRSVI_RESETVALUE 0x000000ffU
+
+#define XHC_ECHRSVM_OFFSET 0xae8U
+#define XHC_ECHRSVM_BASE 0xae8U
+#define XHC_ECHRSVM__reserved_L 31U
+#define XHC_ECHRSVM__reserved_R 16U
+#define XHC_ECHRSVM__reserved_WIDTH 16U
+#define XHC_ECHRSVM__reserved_RESETVALUE 0x0000U
+#define XHC_ECHRSVM__NCP_L 15U
+#define XHC_ECHRSVM__NCP_R 8U
+#define XHC_ECHRSVM__NCP_WIDTH 8U
+#define XHC_ECHRSVM__NCP_RESETVALUE 0x00U
+#define XHC_ECHRSVM__CID_L 7U
+#define XHC_ECHRSVM__CID_R 0U
+#define XHC_ECHRSVM__CID_WIDTH 8U
+#define XHC_ECHRSVM__CID_RESETVALUE 0xffU
+#define XHC_ECHRSVM_WIDTH 32U
+#define XHC_ECHRSVM__WIDTH 32U
+#define XHC_ECHRSVM_ALL_L 31U
+#define XHC_ECHRSVM_ALL_R 0U
+#define XHC_ECHRSVM__ALL_L 31U
+#define XHC_ECHRSVM__ALL_R 0U
+#define XHC_ECHRSVM_DATAMASK 0xffffffffU
+#define XHC_ECHRSVM_RDWRMASK 0x00000000U
+#define XHC_ECHRSVM_RESETVALUE 0x000000ffU
+
+#define XHC_ECHRSVD_OFFSET 0xaf8U
+#define XHC_ECHRSVD_BASE 0xaf8U
+#define XHC_ECHRSVD__reserved_L 31U
+#define XHC_ECHRSVD__reserved_R 16U
+#define XHC_ECHRSVD__reserved_WIDTH 16U
+#define XHC_ECHRSVD__reserved_RESETVALUE 0x0000U
+#define XHC_ECHRSVD__NCP_L 15U
+#define XHC_ECHRSVD__NCP_R 8U
+#define XHC_ECHRSVD__NCP_WIDTH 8U
+#define XHC_ECHRSVD__NCP_RESETVALUE 0x00U
+#define XHC_ECHRSVD__CID_L 7U
+#define XHC_ECHRSVD__CID_R 0U
+#define XHC_ECHRSVD__CID_WIDTH 8U
+#define XHC_ECHRSVD__CID_RESETVALUE 0xffU
+#define XHC_ECHRSVD_WIDTH 32U
+#define XHC_ECHRSVD__WIDTH 32U
+#define XHC_ECHRSVD_ALL_L 31U
+#define XHC_ECHRSVD_ALL_R 0U
+#define XHC_ECHRSVD__ALL_L 31U
+#define XHC_ECHRSVD__ALL_R 0U
+#define XHC_ECHRSVD_DATAMASK 0xffffffffU
+#define XHC_ECHRSVD_RDWRMASK 0x00000000U
+#define XHC_ECHRSVD_RESETVALUE 0x000000ffU
+
+#define XHC_ECHRSVO_OFFSET 0xb38U
+#define XHC_ECHRSVO_BASE 0xb38U
+#define XHC_ECHRSVO__reserved_L 31U
+#define XHC_ECHRSVO__reserved_R 16U
+#define XHC_ECHRSVO__reserved_WIDTH 16U
+#define XHC_ECHRSVO__reserved_RESETVALUE 0x0000U
+#define XHC_ECHRSVO__NCP_L 15U
+#define XHC_ECHRSVO__NCP_R 8U
+#define XHC_ECHRSVO__NCP_WIDTH 8U
+#define XHC_ECHRSVO__NCP_RESETVALUE 0x00U
+#define XHC_ECHRSVO__CID_L 7U
+#define XHC_ECHRSVO__CID_R 0U
+#define XHC_ECHRSVO__CID_WIDTH 8U
+#define XHC_ECHRSVO__CID_RESETVALUE 0xffU
+#define XHC_ECHRSVO_WIDTH 32U
+#define XHC_ECHRSVO__WIDTH 32U
+#define XHC_ECHRSVO_ALL_L 31U
+#define XHC_ECHRSVO_ALL_R 0U
+#define XHC_ECHRSVO__ALL_L 31U
+#define XHC_ECHRSVO__ALL_R 0U
+#define XHC_ECHRSVO_DATAMASK 0xffffffffU
+#define XHC_ECHRSVO_RDWRMASK 0x00000000U
+#define XHC_ECHRSVO_RESETVALUE 0x000000ffU
+
+#define XHC_ECHCTT_OFFSET 0xbf0U
+#define XHC_ECHCTT_BASE 0xbf0U
+#define XHC_ECHCTT__reserved_L 31U
+#define XHC_ECHCTT__reserved_R 16U
+#define XHC_ECHCTT__reserved_WIDTH 16U
+#define XHC_ECHCTT__reserved_RESETVALUE 0x0000U
+#define XHC_ECHCTT__NCP_L 15U
+#define XHC_ECHCTT__NCP_R 8U
+#define XHC_ECHCTT__NCP_WIDTH 8U
+#define XHC_ECHCTT__NCP_RESETVALUE 0x04U
+#define XHC_ECHCTT__CID_L 7U
+#define XHC_ECHCTT__CID_R 0U
+#define XHC_ECHCTT__CID_WIDTH 8U
+#define XHC_ECHCTT__CID_RESETVALUE 0xe0U
+#define XHC_ECHCTT_WIDTH 32U
+#define XHC_ECHCTT__WIDTH 32U
+#define XHC_ECHCTT_ALL_L 31U
+#define XHC_ECHCTT_ALL_R 0U
+#define XHC_ECHCTT__ALL_L 31U
+#define XHC_ECHCTT__ALL_R 0U
+#define XHC_ECHCTT_DATAMASK 0xffffffffU
+#define XHC_ECHCTT_RDWRMASK 0x00000000U
+#define XHC_ECHCTT_RESETVALUE 0x000004e0U
+
+#define XHC_CTTMTS0_OFFSET 0xbf8U
+#define XHC_CTTMTS0_BASE 0xbf8U
+#define XHC_CTTMTS0__DCM 31U
+#define XHC_CTTMTS0__DCM_L 31U
+#define XHC_CTTMTS0__DCM_R 31U
+#define XHC_CTTMTS0__DCM_WIDTH 1U
+#define XHC_CTTMTS0__DCM_RESETVALUE 0x0U
+#define XHC_CTTMTS0__reserved_L 30U
+#define XHC_CTTMTS0__reserved_R 10U
+#define XHC_CTTMTS0__reserved_WIDTH 21U
+#define XHC_CTTMTS0__reserved_RESETVALUE 0x0U
+#define XHC_CTTMTS0__SLA_L 9U
+#define XHC_CTTMTS0__SLA_R 0U
+#define XHC_CTTMTS0__SLA_WIDTH 10U
+#define XHC_CTTMTS0__SLA_RESETVALUE 0x0U
+#define XHC_CTTMTS0_WIDTH 32U
+#define XHC_CTTMTS0__WIDTH 32U
+#define XHC_CTTMTS0_ALL_L 31U
+#define XHC_CTTMTS0_ALL_R 0U
+#define XHC_CTTMTS0__ALL_L 31U
+#define XHC_CTTMTS0__ALL_R 0U
+#define XHC_CTTMTS0_DATAMASK 0xffffffffU
+#define XHC_CTTMTS0_RDWRMASK 0x00000000U
+#define XHC_CTTMTS0_RESETVALUE 0x00000000U
+
+#define XHC_CTTMTS1_OFFSET 0xbfcU
+#define XHC_CTTMTS1_BASE 0xbfcU
+#define XHC_CTTMTS1__TXF_L 25U
+#define XHC_CTTMTS1__TXF_R 16U
+#define XHC_CTTMTS1__TXF_WIDTH 10U
+#define XHC_CTTMTS1__TXF_RESETVALUE 0x0U
+#define XHC_CTTMTS1__reserved_L 15U
+#define XHC_CTTMTS1__reserved_R 10U
+#define XHC_CTTMTS1__reserved_WIDTH 6U
+#define XHC_CTTMTS1__reserved_RESETVALUE 0x0U
+#define XHC_CTTMTS1__RXF_L 9U
+#define XHC_CTTMTS1__RXF_R 0U
+#define XHC_CTTMTS1__RXF_WIDTH 10U
+#define XHC_CTTMTS1__RXF_RESETVALUE 0x0U
+#define XHC_CTTMTS1__RESERVED_L 31U
+#define XHC_CTTMTS1__RESERVED_R 26U
+#define XHC_CTTMTS1_WIDTH 26U
+#define XHC_CTTMTS1__WIDTH 26U
+#define XHC_CTTMTS1_ALL_L 25U
+#define XHC_CTTMTS1_ALL_R 0U
+#define XHC_CTTMTS1__ALL_L 25U
+#define XHC_CTTMTS1__ALL_R 0U
+#define XHC_CTTMTS1_DATAMASK 0x03ffffffU
+#define XHC_CTTMTS1_RDWRMASK 0xfc000000U
+#define XHC_CTTMTS1_RESETVALUE 0x0000000U
+
+#define XHC_ECHBIU_OFFSET 0xc00U
+#define XHC_ECHBIU_BASE 0xc00U
+#define XHC_ECHBIU__CLK_L 31U
+#define XHC_ECHBIU__CLK_R 21U
+#define XHC_ECHBIU__CLK_WIDTH 11U
+#define XHC_ECHBIU__CLK_RESETVALUE 0x0U
+#define XHC_ECHBIU__reserved_L 20U
+#define XHC_ECHBIU__reserved_R 19U
+#define XHC_ECHBIU__reserved_WIDTH 2U
+#define XHC_ECHBIU__reserved_RESETVALUE 0x0U
+#define XHC_ECHBIU__WID_L 18U
+#define XHC_ECHBIU__WID_R 16U
+#define XHC_ECHBIU__WID_WIDTH 3U
+#define XHC_ECHBIU__WID_RESETVALUE 0x0U
+#define XHC_ECHBIU__NCP_L 15U
+#define XHC_ECHBIU__NCP_R 8U
+#define XHC_ECHBIU__NCP_WIDTH 8U
+#define XHC_ECHBIU__NCP_RESETVALUE 0x08U
+#define XHC_ECHBIU__CID_L 7U
+#define XHC_ECHBIU__CID_R 0U
+#define XHC_ECHBIU__CID_WIDTH 8U
+#define XHC_ECHBIU__CID_RESETVALUE 0xc0U
+#define XHC_ECHBIU_WIDTH 32U
+#define XHC_ECHBIU__WIDTH 32U
+#define XHC_ECHBIU_ALL_L 31U
+#define XHC_ECHBIU_ALL_R 0U
+#define XHC_ECHBIU__ALL_L 31U
+#define XHC_ECHBIU__ALL_R 0U
+#define XHC_ECHBIU_DATAMASK 0xffffffffU
+#define XHC_ECHBIU_RDWRMASK 0x00000000U
+#define XHC_ECHBIU_RESETVALUE 0x000008c0U
+
+#define XHC_BIUSPC_OFFSET 0xc04U
+#define XHC_BIUSPC_BASE 0xc04U
+#define XHC_BIUSPC__MAJ_L 31U
+#define XHC_BIUSPC__MAJ_R 28U
+#define XHC_BIUSPC__MAJ_WIDTH 4U
+#define XHC_BIUSPC__MAJ_RESETVALUE 0x0U
+#define XHC_BIUSPC__MIN_L 27U
+#define XHC_BIUSPC__MIN_R 24U
+#define XHC_BIUSPC__MIN_WIDTH 4U
+#define XHC_BIUSPC__MIN_RESETVALUE 0x0U
+#define XHC_BIUSPC__RLS_L 23U
+#define XHC_BIUSPC__RLS_R 20U
+#define XHC_BIUSPC__RLS_WIDTH 4U
+#define XHC_BIUSPC__RLS_RESETVALUE 0x0U
+#define XHC_BIUSPC__reserved_L 19U
+#define XHC_BIUSPC__reserved_R 4U
+#define XHC_BIUSPC__reserved_WIDTH 16U
+#define XHC_BIUSPC__reserved_RESETVALUE 0x0000U
+#define XHC_BIUSPC__SPI_L 3U
+#define XHC_BIUSPC__SPI_R 2U
+#define XHC_BIUSPC__SPI_WIDTH 2U
+#define XHC_BIUSPC__SPI_RESETVALUE 0x3U
+#define XHC_BIUSPC__TYP_L 1U
+#define XHC_BIUSPC__TYP_R 0U
+#define XHC_BIUSPC__TYP_WIDTH 2U
+#define XHC_BIUSPC__TYP_RESETVALUE 0x0U
+#define XHC_BIUSPC_WIDTH 32U
+#define XHC_BIUSPC__WIDTH 32U
+#define XHC_BIUSPC_ALL_L 31U
+#define XHC_BIUSPC_ALL_R 0U
+#define XHC_BIUSPC__ALL_L 31U
+#define XHC_BIUSPC__ALL_R 0U
+#define XHC_BIUSPC_DATAMASK 0xffffffffU
+#define XHC_BIUSPC_RDWRMASK 0x00000000U
+#define XHC_BIUSPC_RESETVALUE 0x0000000cU
+
+#define XHC_AXIWRA_OFFSET 0xc08U
+#define XHC_AXIWRA_BASE 0xc08U
+#define XHC_AXIWRA__WTS_L 31U
+#define XHC_AXIWRA__WTS_R 28U
+#define XHC_AXIWRA__WTS_WIDTH 4U
+#define XHC_AXIWRA__WTS_RESETVALUE 0x2U
+#define XHC_AXIWRA__WUA_L 24U
+#define XHC_AXIWRA__WUA_R 16U
+#define XHC_AXIWRA__WUA_WIDTH 9U
+#define XHC_AXIWRA__WUA_RESETVALUE 0x0U
+#define XHC_AXIWRA__reserved_L 15U
+#define XHC_AXIWRA__reserved_R 10U
+#define XHC_AXIWRA__reserved_WIDTH 6U
+#define XHC_AXIWRA__reserved_RESETVALUE 0x0U
+#define XHC_AXIWRA__BYP 9U
+#define XHC_AXIWRA__BYP_L 9U
+#define XHC_AXIWRA__BYP_R 9U
+#define XHC_AXIWRA__BYP_WIDTH 1U
+#define XHC_AXIWRA__BYP_RESETVALUE 0x0U
+#define XHC_AXIWRA__WSA_L 8U
+#define XHC_AXIWRA__WSA_R 0U
+#define XHC_AXIWRA__WSA_WIDTH 9U
+#define XHC_AXIWRA__WSA_RESETVALUE 0x0U
+#define XHC_AXIWRA__RESERVED_L 27U
+#define XHC_AXIWRA__RESERVED_R 25U
+#define XHC_AXIWRA_WIDTH 32U
+#define XHC_AXIWRA__WIDTH 32U
+#define XHC_AXIWRA_ALL_L 31U
+#define XHC_AXIWRA_ALL_R 0U
+#define XHC_AXIWRA__ALL_L 31U
+#define XHC_AXIWRA__ALL_R 0U
+#define XHC_AXIWRA_DATAMASK 0xf1ffffffU
+#define XHC_AXIWRA_RDWRMASK 0x0e000000U
+#define XHC_AXIWRA_RESETVALUE 0x20000000U
+
+#define XHC_AXIRDA_OFFSET 0xc0cU
+#define XHC_AXIRDA_BASE 0xc0cU
+#define XHC_AXIRDA__RTS_L 31U
+#define XHC_AXIRDA__RTS_R 28U
+#define XHC_AXIRDA__RTS_WIDTH 4U
+#define XHC_AXIRDA__RTS_RESETVALUE 0x2U
+#define XHC_AXIRDA__RFPC 27U
+#define XHC_AXIRDA__RFPC_L 27U
+#define XHC_AXIRDA__RFPC_R 27U
+#define XHC_AXIRDA__RFPC_WIDTH 1U
+#define XHC_AXIRDA__RFPC_RESETVALUE 0x0U
+#define XHC_AXIRDA__RUA_L 24U
+#define XHC_AXIRDA__RUA_R 16U
+#define XHC_AXIRDA__RUA_WIDTH 9U
+#define XHC_AXIRDA__RUA_RESETVALUE 0x0U
+#define XHC_AXIRDA__reserved_L 15U
+#define XHC_AXIRDA__reserved_R 9U
+#define XHC_AXIRDA__reserved_WIDTH 7U
+#define XHC_AXIRDA__reserved_RESETVALUE 0x0U
+#define XHC_AXIRDA__RSA_L 8U
+#define XHC_AXIRDA__RSA_R 0U
+#define XHC_AXIRDA__RSA_WIDTH 9U
+#define XHC_AXIRDA__RSA_RESETVALUE 0x0U
+#define XHC_AXIRDA__RESERVED_L 26U
+#define XHC_AXIRDA__RESERVED_R 25U
+#define XHC_AXIRDA_WIDTH 32U
+#define XHC_AXIRDA__WIDTH 32U
+#define XHC_AXIRDA_ALL_L 31U
+#define XHC_AXIRDA_ALL_R 0U
+#define XHC_AXIRDA__ALL_L 31U
+#define XHC_AXIRDA__ALL_R 0U
+#define XHC_AXIRDA_DATAMASK 0xf9ffffffU
+#define XHC_AXIRDA_RDWRMASK 0x06000000U
+#define XHC_AXIRDA_RESETVALUE 0x20000000U
+
+#define XHC_AXILPM_OFFSET 0xc10U
+#define XHC_AXILPM_BASE 0xc10U
+#define XHC_AXILPM__ENB 31U
+#define XHC_AXILPM__ENB_L 31U
+#define XHC_AXILPM__ENB_R 31U
+#define XHC_AXILPM__ENB_WIDTH 1U
+#define XHC_AXILPM__ENB_RESETVALUE 0x0U
+#define XHC_AXILPM__reserved_L 30U
+#define XHC_AXILPM__reserved_R 3U
+#define XHC_AXILPM__reserved_WIDTH 28U
+#define XHC_AXILPM__reserved_RESETVALUE 0x0000000U
+#define XHC_AXILPM__ITT_L 2U
+#define XHC_AXILPM__ITT_R 0U
+#define XHC_AXILPM__ITT_WIDTH 3U
+#define XHC_AXILPM__ITT_RESETVALUE 0x0U
+#define XHC_AXILPM_WIDTH 32U
+#define XHC_AXILPM__WIDTH 32U
+#define XHC_AXILPM_ALL_L 31U
+#define XHC_AXILPM_ALL_R 0U
+#define XHC_AXILPM__ALL_L 31U
+#define XHC_AXILPM__ALL_R 0U
+#define XHC_AXILPM_DATAMASK 0xffffffffU
+#define XHC_AXILPM_RDWRMASK 0x00000000U
+#define XHC_AXILPM_RESETVALUE 0x00000000U
+
+#define XHC_AXIQOS_OFFSET 0xc14U
+#define XHC_AXIQOS_BASE 0xc14U
+#define XHC_AXIQOS__WQOS3_L 31U
+#define XHC_AXIQOS__WQOS3_R 28U
+#define XHC_AXIQOS__WQOS3_WIDTH 4U
+#define XHC_AXIQOS__WQOS3_RESETVALUE 0x0U
+#define XHC_AXIQOS__WQOS2_L 27U
+#define XHC_AXIQOS__WQOS2_R 24U
+#define XHC_AXIQOS__WQOS2_WIDTH 4U
+#define XHC_AXIQOS__WQOS2_RESETVALUE 0x0U
+#define XHC_AXIQOS__WQOS1_L 23U
+#define XHC_AXIQOS__WQOS1_R 20U
+#define XHC_AXIQOS__WQOS1_WIDTH 4U
+#define XHC_AXIQOS__WQOS1_RESETVALUE 0x0U
+#define XHC_AXIQOS__WQOS0_L 19U
+#define XHC_AXIQOS__WQOS0_R 16U
+#define XHC_AXIQOS__WQOS0_WIDTH 4U
+#define XHC_AXIQOS__WQOS0_RESETVALUE 0x0U
+#define XHC_AXIQOS__RQOS3_L 15U
+#define XHC_AXIQOS__RQOS3_R 12U
+#define XHC_AXIQOS__RQOS3_WIDTH 4U
+#define XHC_AXIQOS__RQOS3_RESETVALUE 0x0U
+#define XHC_AXIQOS__RQOS2_L 11U
+#define XHC_AXIQOS__RQOS2_R 8U
+#define XHC_AXIQOS__RQOS2_WIDTH 4U
+#define XHC_AXIQOS__RQOS2_RESETVALUE 0x0U
+#define XHC_AXIQOS__RQOS1_L 7U
+#define XHC_AXIQOS__RQOS1_R 4U
+#define XHC_AXIQOS__RQOS1_WIDTH 4U
+#define XHC_AXIQOS__RQOS1_RESETVALUE 0x0U
+#define XHC_AXIQOS__RQOS0_L 3U
+#define XHC_AXIQOS__RQOS0_R 0U
+#define XHC_AXIQOS__RQOS0_WIDTH 4U
+#define XHC_AXIQOS__RQOS0_RESETVALUE 0x0U
+#define XHC_AXIQOS_WIDTH 32U
+#define XHC_AXIQOS__WIDTH 32U
+#define XHC_AXIQOS_ALL_L 31U
+#define XHC_AXIQOS_ALL_R 0U
+#define XHC_AXIQOS__ALL_L 31U
+#define XHC_AXIQOS__ALL_R 0U
+#define XHC_AXIQOS_DATAMASK 0xffffffffU
+#define XHC_AXIQOS_RDWRMASK 0x00000000U
+#define XHC_AXIQOS_RESETVALUE 0x00000000U
+
+#define XHC_ECHCSR_OFFSET 0xc20U
+#define XHC_ECHCSR_BASE 0xc20U
+#define XHC_ECHCSR__CLK_L 31U
+#define XHC_ECHCSR__CLK_R 21U
+#define XHC_ECHCSR__CLK_WIDTH 11U
+#define XHC_ECHCSR__CLK_RESETVALUE 0x0U
+#define XHC_ECHCSR__reserved_L 20U
+#define XHC_ECHCSR__reserved_R 19U
+#define XHC_ECHCSR__reserved_WIDTH 2U
+#define XHC_ECHCSR__reserved_RESETVALUE 0x0U
+#define XHC_ECHCSR__WID_L 18U
+#define XHC_ECHCSR__WID_R 16U
+#define XHC_ECHCSR__WID_WIDTH 3U
+#define XHC_ECHCSR__WID_RESETVALUE 0x0U
+#define XHC_ECHCSR__NCP_L 15U
+#define XHC_ECHCSR__NCP_R 8U
+#define XHC_ECHCSR__NCP_WIDTH 8U
+#define XHC_ECHCSR__NCP_RESETVALUE 0x04U
+#define XHC_ECHCSR__CID_L 7U
+#define XHC_ECHCSR__CID_R 0U
+#define XHC_ECHCSR__CID_WIDTH 8U
+#define XHC_ECHCSR__CID_RESETVALUE 0xc1U
+#define XHC_ECHCSR_WIDTH 32U
+#define XHC_ECHCSR__WIDTH 32U
+#define XHC_ECHCSR_ALL_L 31U
+#define XHC_ECHCSR_ALL_R 0U
+#define XHC_ECHCSR__ALL_L 31U
+#define XHC_ECHCSR__ALL_R 0U
+#define XHC_ECHCSR_DATAMASK 0xffffffffU
+#define XHC_ECHCSR_RDWRMASK 0x00000000U
+#define XHC_ECHCSR_RESETVALUE 0x000004c1U
+
+#define XHC_CSRSPC_OFFSET 0xc24U
+#define XHC_CSRSPC_BASE 0xc24U
+#define XHC_CSRSPC__MAJ_L 31U
+#define XHC_CSRSPC__MAJ_R 28U
+#define XHC_CSRSPC__MAJ_WIDTH 4U
+#define XHC_CSRSPC__MAJ_RESETVALUE 0x0U
+#define XHC_CSRSPC__MIN_L 27U
+#define XHC_CSRSPC__MIN_R 24U
+#define XHC_CSRSPC__MIN_WIDTH 4U
+#define XHC_CSRSPC__MIN_RESETVALUE 0x0U
+#define XHC_CSRSPC__RLS_L 23U
+#define XHC_CSRSPC__RLS_R 20U
+#define XHC_CSRSPC__RLS_WIDTH 4U
+#define XHC_CSRSPC__RLS_RESETVALUE 0x0U
+#define XHC_CSRSPC__reserved_L 19U
+#define XHC_CSRSPC__reserved_R 3U
+#define XHC_CSRSPC__reserved_WIDTH 17U
+#define XHC_CSRSPC__reserved_RESETVALUE 0x0U
+#define XHC_CSRSPC__ASP 2U
+#define XHC_CSRSPC__ASP_L 2U
+#define XHC_CSRSPC__ASP_R 2U
+#define XHC_CSRSPC__ASP_WIDTH 1U
+#define XHC_CSRSPC__ASP_RESETVALUE 0x0U
+#define XHC_CSRSPC__TYP_L 1U
+#define XHC_CSRSPC__TYP_R 0U
+#define XHC_CSRSPC__TYP_WIDTH 2U
+#define XHC_CSRSPC__TYP_RESETVALUE 0x0U
+#define XHC_CSRSPC_WIDTH 32U
+#define XHC_CSRSPC__WIDTH 32U
+#define XHC_CSRSPC_ALL_L 31U
+#define XHC_CSRSPC_ALL_R 0U
+#define XHC_CSRSPC__ALL_L 31U
+#define XHC_CSRSPC__ALL_R 0U
+#define XHC_CSRSPC_DATAMASK 0xffffffffU
+#define XHC_CSRSPC_RDWRMASK 0x00000000U
+#define XHC_CSRSPC_RESETVALUE 0x00000000U
+
+#define XHC_ECHAIU_OFFSET 0xc30U
+#define XHC_ECHAIU_BASE 0xc30U
+#define XHC_ECHAIU__DMA_L 31U
+#define XHC_ECHAIU__DMA_R 30U
+#define XHC_ECHAIU__DMA_WIDTH 2U
+#define XHC_ECHAIU__DMA_RESETVALUE 0x1U
+#define XHC_ECHAIU__PBRS_L 29U
+#define XHC_ECHAIU__PBRS_R 28U
+#define XHC_ECHAIU__PBRS_WIDTH 2U
+#define XHC_ECHAIU__PBRS_RESETVALUE 0x0U
+#define XHC_ECHAIU__PBR2_L 27U
+#define XHC_ECHAIU__PBR2_R 26U
+#define XHC_ECHAIU__PBR2_WIDTH 2U
+#define XHC_ECHAIU__PBR2_RESETVALUE 0x0U
+#define XHC_ECHAIU__SCHS_L 25U
+#define XHC_ECHAIU__SCHS_R 24U
+#define XHC_ECHAIU__SCHS_WIDTH 2U
+#define XHC_ECHAIU__SCHS_RESETVALUE 0x0U
+#define XHC_ECHAIU__SCH2_L 23U
+#define XHC_ECHAIU__SCH2_R 22U
+#define XHC_ECHAIU__SCH2_WIDTH 2U
+#define XHC_ECHAIU__SCH2_RESETVALUE 0x0U
+#define XHC_ECHAIU__CHMS_L 21U
+#define XHC_ECHAIU__CHMS_R 20U
+#define XHC_ECHAIU__CHMS_WIDTH 2U
+#define XHC_ECHAIU__CHMS_RESETVALUE 0x3U
+#define XHC_ECHAIU__CHM2_L 19U
+#define XHC_ECHAIU__CHM2_R 18U
+#define XHC_ECHAIU__CHM2_WIDTH 2U
+#define XHC_ECHAIU__CHM2_RESETVALUE 0x0U
+#define XHC_ECHAIU__reserved_L 17U
+#define XHC_ECHAIU__reserved_R 16U
+#define XHC_ECHAIU__reserved_WIDTH 2U
+#define XHC_ECHAIU__reserved_RESETVALUE 0x0U
+#define XHC_ECHAIU__NCP_L 15U
+#define XHC_ECHAIU__NCP_R 8U
+#define XHC_ECHAIU__NCP_WIDTH 8U
+#define XHC_ECHAIU__NCP_RESETVALUE 0x04U
+#define XHC_ECHAIU__CID_L 7U
+#define XHC_ECHAIU__CID_R 0U
+#define XHC_ECHAIU__CID_WIDTH 8U
+#define XHC_ECHAIU__CID_RESETVALUE 0xc2U
+#define XHC_ECHAIU_WIDTH 32U
+#define XHC_ECHAIU__WIDTH 32U
+#define XHC_ECHAIU_ALL_L 31U
+#define XHC_ECHAIU_ALL_R 0U
+#define XHC_ECHAIU__ALL_L 31U
+#define XHC_ECHAIU__ALL_R 0U
+#define XHC_ECHAIU_DATAMASK 0xffffffffU
+#define XHC_ECHAIU_RDWRMASK 0x00000000U
+#define XHC_ECHAIU_RESETVALUE 0x403004c2U
+
+#define XHC_AIUDMA_OFFSET 0xc34U
+#define XHC_AIUDMA_BASE 0xc34U
+#define XHC_AIUDMA__WRMB_L 31U
+#define XHC_AIUDMA__WRMB_R 28U
+#define XHC_AIUDMA__WRMB_WIDTH 4U
+#define XHC_AIUDMA__WRMB_RESETVALUE 0x0U
+#define XHC_AIUDMA__WRD_L 27U
+#define XHC_AIUDMA__WRD_R 26U
+#define XHC_AIUDMA__WRD_WIDTH 2U
+#define XHC_AIUDMA__WRD_RESETVALUE 0x0U
+#define XHC_AIUDMA__WED_L 25U
+#define XHC_AIUDMA__WED_R 24U
+#define XHC_AIUDMA__WED_WIDTH 2U
+#define XHC_AIUDMA__WED_RESETVALUE 0x0U
+#define XHC_AIUDMA__WMS_L 23U
+#define XHC_AIUDMA__WMS_R 22U
+#define XHC_AIUDMA__WMS_WIDTH 2U
+#define XHC_AIUDMA__WMS_RESETVALUE 0x0U
+#define XHC_AIUDMA__WMI_L 21U
+#define XHC_AIUDMA__WMI_R 20U
+#define XHC_AIUDMA__WMI_WIDTH 2U
+#define XHC_AIUDMA__WMI_RESETVALUE 0x0U
+#define XHC_AIUDMA__WPF_L 19U
+#define XHC_AIUDMA__WPF_R 16U
+#define XHC_AIUDMA__WPF_WIDTH 4U
+#define XHC_AIUDMA__WPF_RESETVALUE 0x6U
+#define XHC_AIUDMA__RRMB_L 15U
+#define XHC_AIUDMA__RRMB_R 12U
+#define XHC_AIUDMA__RRMB_WIDTH 4U
+#define XHC_AIUDMA__RRMB_RESETVALUE 0x0U
+#define XHC_AIUDMA__RTD_L 11U
+#define XHC_AIUDMA__RTD_R 10U
+#define XHC_AIUDMA__RTD_WIDTH 2U
+#define XHC_AIUDMA__RTD_RESETVALUE 0x0U
+#define XHC_AIUDMA__RTF_L 9U
+#define XHC_AIUDMA__RTF_R 8U
+#define XHC_AIUDMA__RTF_WIDTH 2U
+#define XHC_AIUDMA__RTF_RESETVALUE 0x0U
+#define XHC_AIUDMA__RM_S_L 7U
+#define XHC_AIUDMA__RM_S_R 6U
+#define XHC_AIUDMA__RM_S_WIDTH 2U
+#define XHC_AIUDMA__RM_S_RESETVALUE 0x0U
+#define XHC_AIUDMA__TFBS_L 5U
+#define XHC_AIUDMA__TFBS_R 3U
+#define XHC_AIUDMA__TFBS_WIDTH 3U
+#define XHC_AIUDMA__TFBS_RESETVALUE 0x0U
+#define XHC_AIUDMA__reserved_L 2U
+#define XHC_AIUDMA__reserved_R 0U
+#define XHC_AIUDMA__reserved_WIDTH 3U
+#define XHC_AIUDMA__reserved_RESETVALUE 0x0U
+#define XHC_AIUDMA_WIDTH 32U
+#define XHC_AIUDMA__WIDTH 32U
+#define XHC_AIUDMA_ALL_L 31U
+#define XHC_AIUDMA_ALL_R 0U
+#define XHC_AIUDMA__ALL_L 31U
+#define XHC_AIUDMA__ALL_R 0U
+#define XHC_AIUDMA_DATAMASK 0xffffffffU
+#define XHC_AIUDMA_RDWRMASK 0x00000000U
+#define XHC_AIUDMA_RESETVALUE 0x00060000U
+
+#define XHC_AIUFLA_OFFSET 0xc38U
+#define XHC_AIUFLA_BASE 0xc38U
+#define XHC_AIUFLA__ACLK_L 31U
+#define XHC_AIUFLA__ACLK_R 23U
+#define XHC_AIUFLA__ACLK_WIDTH 9U
+#define XHC_AIUFLA__ACLK_RESETVALUE 0x0U
+#define XHC_AIUFLA__MFLV_L 22U
+#define XHC_AIUFLA__MFLV_R 7U
+#define XHC_AIUFLA__MFLV_WIDTH 16U
+#define XHC_AIUFLA__MFLV_RESETVALUE 0x0000U
+#define XHC_AIUFLA__NFC 6U
+#define XHC_AIUFLA__NFC_L 6U
+#define XHC_AIUFLA__NFC_R 6U
+#define XHC_AIUFLA__NFC_WIDTH 1U
+#define XHC_AIUFLA__NFC_RESETVALUE 0x1U
+#define XHC_AIUFLA__FLADJ_L 5U
+#define XHC_AIUFLA__FLADJ_R 0U
+#define XHC_AIUFLA__FLADJ_WIDTH 6U
+#define XHC_AIUFLA__FLADJ_RESETVALUE 0x20U
+#define XHC_AIUFLA_WIDTH 32U
+#define XHC_AIUFLA__WIDTH 32U
+#define XHC_AIUFLA_ALL_L 31U
+#define XHC_AIUFLA_ALL_R 0U
+#define XHC_AIUFLA__ALL_L 31U
+#define XHC_AIUFLA__ALL_R 0U
+#define XHC_AIUFLA_DATAMASK 0xffffffffU
+#define XHC_AIUFLA_RDWRMASK 0x00000000U
+#define XHC_AIUFLA_RESETVALUE 0x00000060U
+
+#define XHC_AIUCFG_OFFSET 0xc3cU
+#define XHC_AIUCFG_BASE 0xc3cU
+#define XHC_AIUCFG__ISO_L 30U
+#define XHC_AIUCFG__ISO_R 28U
+#define XHC_AIUCFG__ISO_WIDTH 3U
+#define XHC_AIUCFG__ISO_RESETVALUE 0x0U
+#define XHC_AIUCFG__EPC_L 26U
+#define XHC_AIUCFG__EPC_R 24U
+#define XHC_AIUCFG__EPC_WIDTH 3U
+#define XHC_AIUCFG__EPC_RESETVALUE 0x5U
+#define XHC_AIUCFG__PTQ_L 22U
+#define XHC_AIUCFG__PTQ_R 20U
+#define XHC_AIUCFG__PTQ_WIDTH 3U
+#define XHC_AIUCFG__PTQ_RESETVALUE 0x3U
+#define XHC_AIUCFG__NTQ_L 18U
+#define XHC_AIUCFG__NTQ_R 16U
+#define XHC_AIUCFG__NTQ_WIDTH 3U
+#define XHC_AIUCFG__NTQ_RESETVALUE 0x3U
+#define XHC_AIUCFG__HID 15U
+#define XHC_AIUCFG__HID_L 15U
+#define XHC_AIUCFG__HID_R 15U
+#define XHC_AIUCFG__HID_WIDTH 1U
+#define XHC_AIUCFG__HID_RESETVALUE 0x0U
+#define XHC_AIUCFG__EPS_L 14U
+#define XHC_AIUCFG__EPS_R 12U
+#define XHC_AIUCFG__EPS_WIDTH 3U
+#define XHC_AIUCFG__EPS_RESETVALUE 0x0U
+#define XHC_AIUCFG__reserved_L 11U
+#define XHC_AIUCFG__reserved_R 9U
+#define XHC_AIUCFG__reserved_WIDTH 3U
+#define XHC_AIUCFG__reserved_RESETVALUE 0x0U
+#define XHC_AIUCFG__PEP2_L 8U
+#define XHC_AIUCFG__PEP2_R 6U
+#define XHC_AIUCFG__PEP2_WIDTH 3U
+#define XHC_AIUCFG__PEP2_RESETVALUE 0x4U
+#define XHC_AIUCFG__MELADJ_L 5U
+#define XHC_AIUCFG__MELADJ_R 0U
+#define XHC_AIUCFG__MELADJ_WIDTH 6U
+#define XHC_AIUCFG__MELADJ_RESETVALUE 0x0U
+#define XHC_AIUCFG__RESERVED_0 31U
+#define XHC_AIUCFG__RESERVED_0_L 31U
+#define XHC_AIUCFG__RESERVED_0_R 31U
+#define XHC_AIUCFG__RESERVED_1 27U
+#define XHC_AIUCFG__RESERVED_1_L 27U
+#define XHC_AIUCFG__RESERVED_1_R 27U
+#define XHC_AIUCFG__RESERVED_2 23U
+#define XHC_AIUCFG__RESERVED_2_L 23U
+#define XHC_AIUCFG__RESERVED_2_R 23U
+#define XHC_AIUCFG__RESERVED_3 19U
+#define XHC_AIUCFG__RESERVED_3_L 19U
+#define XHC_AIUCFG__RESERVED_3_R 19U
+#define XHC_AIUCFG_WIDTH 31U
+#define XHC_AIUCFG__WIDTH 31U
+#define XHC_AIUCFG_ALL_L 30U
+#define XHC_AIUCFG_ALL_R 0U
+#define XHC_AIUCFG__ALL_L 30U
+#define XHC_AIUCFG__ALL_R 0U
+#define XHC_AIUCFG_DATAMASK 0x7777ffffU
+#define XHC_AIUCFG_RDWRMASK 0x88880000U
+#define XHC_AIUCFG_RESETVALUE 0x05330100U
+
+#define XHC_ECHFSC_OFFSET 0xc40U
+#define XHC_ECHFSC_BASE 0xc40U
+#define XHC_ECHFSC__reserved_L 31U
+#define XHC_ECHFSC__reserved_R 24U
+#define XHC_ECHFSC__reserved_WIDTH 8U
+#define XHC_ECHFSC__reserved_RESETVALUE 0x00U
+#define XHC_ECHFSC__WRMB_L 23U
+#define XHC_ECHFSC__WRMB_R 20U
+#define XHC_ECHFSC__WRMB_WIDTH 4U
+#define XHC_ECHFSC__WRMB_RESETVALUE 0x0U
+#define XHC_ECHFSC__RRMB_L 19U
+#define XHC_ECHFSC__RRMB_R 16U
+#define XHC_ECHFSC__RRMB_WIDTH 4U
+#define XHC_ECHFSC__RRMB_RESETVALUE 0x0U
+#define XHC_ECHFSC__NCP_L 15U
+#define XHC_ECHFSC__NCP_R 8U
+#define XHC_ECHFSC__NCP_WIDTH 8U
+#define XHC_ECHFSC__NCP_RESETVALUE 0x50U
+#define XHC_ECHFSC__CID_L 7U
+#define XHC_ECHFSC__CID_R 0U
+#define XHC_ECHFSC__CID_WIDTH 8U
+#define XHC_ECHFSC__CID_RESETVALUE 0xc3U
+#define XHC_ECHFSC_WIDTH 32U
+#define XHC_ECHFSC__WIDTH 32U
+#define XHC_ECHFSC_ALL_L 31U
+#define XHC_ECHFSC_ALL_R 0U
+#define XHC_ECHFSC__ALL_L 31U
+#define XHC_ECHFSC__ALL_R 0U
+#define XHC_ECHFSC_DATAMASK 0xffffffffU
+#define XHC_ECHFSC_RDWRMASK 0x00000000U
+#define XHC_ECHFSC_RESETVALUE 0x000050c3U
+
+#define XHC_FSCPOC_OFFSET 0xc54U
+#define XHC_FSCPOC_BASE 0xc54U
+#define XHC_FSCPOC__NCS_L 31U
+#define XHC_FSCPOC__NCS_R 28U
+#define XHC_FSCPOC__NCS_WIDTH 4U
+#define XHC_FSCPOC__NCS_RESETVALUE 0x0U
+#define XHC_FSCPOC__FSIZ_L 22U
+#define XHC_FSCPOC__FSIZ_R 18U
+#define XHC_FSCPOC__FSIZ_WIDTH 5U
+#define XHC_FSCPOC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSCPOC__PSIZ_L 16U
+#define XHC_FSCPOC__PSIZ_R 12U
+#define XHC_FSCPOC__PSIZ_WIDTH 5U
+#define XHC_FSCPOC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSCPOC__reserved_L 11U
+#define XHC_FSCPOC__reserved_R 5U
+#define XHC_FSCPOC__reserved_WIDTH 7U
+#define XHC_FSCPOC__reserved_RESETVALUE 0x0U
+#define XHC_FSCPOC__TSIZ_L 4U
+#define XHC_FSCPOC__TSIZ_R 0U
+#define XHC_FSCPOC__TSIZ_WIDTH 5U
+#define XHC_FSCPOC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSCPOC__RESERVED_L 27U
+#define XHC_FSCPOC__RESERVED_R 23U
+#define XHC_FSCPOC_WIDTH 32U
+#define XHC_FSCPOC__WIDTH 32U
+#define XHC_FSCPOC_ALL_L 31U
+#define XHC_FSCPOC_ALL_R 0U
+#define XHC_FSCPOC__ALL_L 31U
+#define XHC_FSCPOC__ALL_R 0U
+#define XHC_FSCPOC_DATAMASK 0xf07dffffU
+#define XHC_FSCPOC_RDWRMASK 0x0f820000U
+#define XHC_FSCPOC_RESETVALUE 0x00000000U
+
+#define XHC_FSCGOC_OFFSET 0xc58U
+#define XHC_FSCGOC_BASE 0xc58U
+#define XHC_FSCGOC__NCS_L 31U
+#define XHC_FSCGOC__NCS_R 28U
+#define XHC_FSCGOC__NCS_WIDTH 4U
+#define XHC_FSCGOC__NCS_RESETVALUE 0x0U
+#define XHC_FSCGOC__FSIZ_L 22U
+#define XHC_FSCGOC__FSIZ_R 18U
+#define XHC_FSCGOC__FSIZ_WIDTH 5U
+#define XHC_FSCGOC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSCGOC__PSIZ_L 16U
+#define XHC_FSCGOC__PSIZ_R 12U
+#define XHC_FSCGOC__PSIZ_WIDTH 5U
+#define XHC_FSCGOC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSCGOC__reserved_L 11U
+#define XHC_FSCGOC__reserved_R 5U
+#define XHC_FSCGOC__reserved_WIDTH 7U
+#define XHC_FSCGOC__reserved_RESETVALUE 0x0U
+#define XHC_FSCGOC__TSIZ_L 4U
+#define XHC_FSCGOC__TSIZ_R 0U
+#define XHC_FSCGOC__TSIZ_WIDTH 5U
+#define XHC_FSCGOC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSCGOC__RESERVED_L 27U
+#define XHC_FSCGOC__RESERVED_R 23U
+#define XHC_FSCGOC_WIDTH 32U
+#define XHC_FSCGOC__WIDTH 32U
+#define XHC_FSCGOC_ALL_L 31U
+#define XHC_FSCGOC_ALL_R 0U
+#define XHC_FSCGOC__ALL_L 31U
+#define XHC_FSCGOC__ALL_R 0U
+#define XHC_FSCGOC_DATAMASK 0xf07dffffU
+#define XHC_FSCGOC_RDWRMASK 0x0f820000U
+#define XHC_FSCGOC_RESETVALUE 0x00000000U
+
+#define XHC_FSCNOC_OFFSET 0xc5cU
+#define XHC_FSCNOC_BASE 0xc5cU
+#define XHC_FSCNOC__NCS_L 31U
+#define XHC_FSCNOC__NCS_R 28U
+#define XHC_FSCNOC__NCS_WIDTH 4U
+#define XHC_FSCNOC__NCS_RESETVALUE 0x0U
+#define XHC_FSCNOC__FSIZ_L 22U
+#define XHC_FSCNOC__FSIZ_R 18U
+#define XHC_FSCNOC__FSIZ_WIDTH 5U
+#define XHC_FSCNOC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSCNOC__PSIZ_L 16U
+#define XHC_FSCNOC__PSIZ_R 12U
+#define XHC_FSCNOC__PSIZ_WIDTH 5U
+#define XHC_FSCNOC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSCNOC__reserved_L 11U
+#define XHC_FSCNOC__reserved_R 5U
+#define XHC_FSCNOC__reserved_WIDTH 7U
+#define XHC_FSCNOC__reserved_RESETVALUE 0x0U
+#define XHC_FSCNOC__TSIZ_L 4U
+#define XHC_FSCNOC__TSIZ_R 0U
+#define XHC_FSCNOC__TSIZ_WIDTH 5U
+#define XHC_FSCNOC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSCNOC__RESERVED_L 27U
+#define XHC_FSCNOC__RESERVED_R 23U
+#define XHC_FSCNOC_WIDTH 32U
+#define XHC_FSCNOC__WIDTH 32U
+#define XHC_FSCNOC_ALL_L 31U
+#define XHC_FSCNOC_ALL_R 0U
+#define XHC_FSCNOC__ALL_L 31U
+#define XHC_FSCNOC__ALL_R 0U
+#define XHC_FSCNOC_DATAMASK 0xf07dffffU
+#define XHC_FSCNOC_RDWRMASK 0x0f820000U
+#define XHC_FSCNOC_RESETVALUE 0x00000000U
+
+#define XHC_FSCAIC_OFFSET 0xc60U
+#define XHC_FSCAIC_BASE 0xc60U
+#define XHC_FSCAIC__FSIZ_L 22U
+#define XHC_FSCAIC__FSIZ_R 18U
+#define XHC_FSCAIC__FSIZ_WIDTH 5U
+#define XHC_FSCAIC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSCAIC__PSIZ_L 16U
+#define XHC_FSCAIC__PSIZ_R 12U
+#define XHC_FSCAIC__PSIZ_WIDTH 5U
+#define XHC_FSCAIC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSCAIC__reserved_L 11U
+#define XHC_FSCAIC__reserved_R 0U
+#define XHC_FSCAIC__reserved_WIDTH 12U
+#define XHC_FSCAIC__reserved_RESETVALUE 0x000U
+#define XHC_FSCAIC__RESERVED_L 31U
+#define XHC_FSCAIC__RESERVED_R 23U
+#define XHC_FSCAIC_WIDTH 23U
+#define XHC_FSCAIC__WIDTH 23U
+#define XHC_FSCAIC_ALL_L 22U
+#define XHC_FSCAIC_ALL_R 0U
+#define XHC_FSCAIC__ALL_L 22U
+#define XHC_FSCAIC__ALL_R 0U
+#define XHC_FSCAIC_DATAMASK 0x007dffffU
+#define XHC_FSCAIC_RDWRMASK 0xff820000U
+#define XHC_FSCAIC_RESETVALUE 0x000000U
+
+#define XHC_FSCPIC_OFFSET 0xc64U
+#define XHC_FSCPIC_BASE 0xc64U
+#define XHC_FSCPIC__NCS_L 31U
+#define XHC_FSCPIC__NCS_R 28U
+#define XHC_FSCPIC__NCS_WIDTH 4U
+#define XHC_FSCPIC__NCS_RESETVALUE 0x0U
+#define XHC_FSCPIC__reserved_L 27U
+#define XHC_FSCPIC__reserved_R 5U
+#define XHC_FSCPIC__reserved_WIDTH 23U
+#define XHC_FSCPIC__reserved_RESETVALUE 0x0U
+#define XHC_FSCPIC__TSIZ_L 4U
+#define XHC_FSCPIC__TSIZ_R 0U
+#define XHC_FSCPIC__TSIZ_WIDTH 5U
+#define XHC_FSCPIC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSCPIC_WIDTH 32U
+#define XHC_FSCPIC__WIDTH 32U
+#define XHC_FSCPIC_ALL_L 31U
+#define XHC_FSCPIC_ALL_R 0U
+#define XHC_FSCPIC__ALL_L 31U
+#define XHC_FSCPIC__ALL_R 0U
+#define XHC_FSCPIC_DATAMASK 0xffffffffU
+#define XHC_FSCPIC_RDWRMASK 0x00000000U
+#define XHC_FSCPIC_RESETVALUE 0x00000000U
+
+#define XHC_FSCGIC_OFFSET 0xc68U
+#define XHC_FSCGIC_BASE 0xc68U
+#define XHC_FSCGIC__NCS_L 31U
+#define XHC_FSCGIC__NCS_R 28U
+#define XHC_FSCGIC__NCS_WIDTH 4U
+#define XHC_FSCGIC__NCS_RESETVALUE 0x0U
+#define XHC_FSCGIC__reserved_L 27U
+#define XHC_FSCGIC__reserved_R 5U
+#define XHC_FSCGIC__reserved_WIDTH 23U
+#define XHC_FSCGIC__reserved_RESETVALUE 0x0U
+#define XHC_FSCGIC__TSIZ_L 4U
+#define XHC_FSCGIC__TSIZ_R 0U
+#define XHC_FSCGIC__TSIZ_WIDTH 5U
+#define XHC_FSCGIC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSCGIC_WIDTH 32U
+#define XHC_FSCGIC__WIDTH 32U
+#define XHC_FSCGIC_ALL_L 31U
+#define XHC_FSCGIC_ALL_R 0U
+#define XHC_FSCGIC__ALL_L 31U
+#define XHC_FSCGIC__ALL_R 0U
+#define XHC_FSCGIC_DATAMASK 0xffffffffU
+#define XHC_FSCGIC_RDWRMASK 0x00000000U
+#define XHC_FSCGIC_RESETVALUE 0x00000000U
+
+#define XHC_FSCNIC_OFFSET 0xc6cU
+#define XHC_FSCNIC_BASE 0xc6cU
+#define XHC_FSCNIC__NCS_L 31U
+#define XHC_FSCNIC__NCS_R 28U
+#define XHC_FSCNIC__NCS_WIDTH 4U
+#define XHC_FSCNIC__NCS_RESETVALUE 0x0U
+#define XHC_FSCNIC__reserved_L 27U
+#define XHC_FSCNIC__reserved_R 5U
+#define XHC_FSCNIC__reserved_WIDTH 23U
+#define XHC_FSCNIC__reserved_RESETVALUE 0x0U
+#define XHC_FSCNIC__TSIZ_L 4U
+#define XHC_FSCNIC__TSIZ_R 0U
+#define XHC_FSCNIC__TSIZ_WIDTH 5U
+#define XHC_FSCNIC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSCNIC_WIDTH 32U
+#define XHC_FSCNIC__WIDTH 32U
+#define XHC_FSCNIC_ALL_L 31U
+#define XHC_FSCNIC_ALL_R 0U
+#define XHC_FSCNIC__ALL_L 31U
+#define XHC_FSCNIC__ALL_R 0U
+#define XHC_FSCNIC_DATAMASK 0xffffffffU
+#define XHC_FSCNIC_RDWRMASK 0x00000000U
+#define XHC_FSCNIC_RESETVALUE 0x00000000U
+
+#define XHC_ECHPRT_OFFSET 0xc70U
+#define XHC_ECHPRT_BASE 0xc70U
+#define XHC_ECHPRT__TDP 31U
+#define XHC_ECHPRT__TDP_L 31U
+#define XHC_ECHPRT__TDP_R 31U
+#define XHC_ECHPRT__TDP_WIDTH 1U
+#define XHC_ECHPRT__TDP_RESETVALUE 0x0U
+#define XHC_ECHPRT__RDP 30U
+#define XHC_ECHPRT__RDP_L 30U
+#define XHC_ECHPRT__RDP_R 30U
+#define XHC_ECHPRT__RDP_WIDTH 1U
+#define XHC_ECHPRT__RDP_RESETVALUE 0x0U
+#define XHC_ECHPRT__reserved_L 29U
+#define XHC_ECHPRT__reserved_R 25U
+#define XHC_ECHPRT__reserved_WIDTH 5U
+#define XHC_ECHPRT__reserved_RESETVALUE 0x0U
+#define XHC_ECHPRT__MFT_L 24U
+#define XHC_ECHPRT__MFT_R 17U
+#define XHC_ECHPRT__MFT_WIDTH 8U
+#define XHC_ECHPRT__MFT_RESETVALUE 0x7dU
+#define XHC_ECHPRT__HST 16U
+#define XHC_ECHPRT__HST_L 16U
+#define XHC_ECHPRT__HST_R 16U
+#define XHC_ECHPRT__HST_WIDTH 1U
+#define XHC_ECHPRT__HST_RESETVALUE 0x0U
+#define XHC_ECHPRT__NCP_L 15U
+#define XHC_ECHPRT__NCP_R 8U
+#define XHC_ECHPRT__NCP_WIDTH 8U
+#define XHC_ECHPRT__NCP_RESETVALUE 0x04U
+#define XHC_ECHPRT__CID_L 7U
+#define XHC_ECHPRT__CID_R 0U
+#define XHC_ECHPRT__CID_WIDTH 8U
+#define XHC_ECHPRT__CID_RESETVALUE 0xc4U
+#define XHC_ECHPRT_WIDTH 32U
+#define XHC_ECHPRT__WIDTH 32U
+#define XHC_ECHPRT_ALL_L 31U
+#define XHC_ECHPRT_ALL_R 0U
+#define XHC_ECHPRT__ALL_L 31U
+#define XHC_ECHPRT__ALL_R 0U
+#define XHC_ECHPRT_DATAMASK 0xffffffffU
+#define XHC_ECHPRT_RDWRMASK 0x00000000U
+#define XHC_ECHPRT_RESETVALUE 0x00fa04c4U
+
+#define XHC_PRTHSC_OFFSET 0xc78U
+#define XHC_PRTHSC_BASE 0xc78U
+#define XHC_PRTHSC__TMR_L 31U
+#define XHC_PRTHSC__TMR_R 16U
+#define XHC_PRTHSC__TMR_WIDTH 16U
+#define XHC_PRTHSC__TMR_RESETVALUE 0x0000U
+#define XHC_PRTHSC__RSL_L 7U
+#define XHC_PRTHSC__RSL_R 6U
+#define XHC_PRTHSC__RSL_WIDTH 2U
+#define XHC_PRTHSC__RSL_RESETVALUE 0x0U
+#define XHC_PRTHSC__AS_M_L 5U
+#define XHC_PRTHSC__AS_M_R 4U
+#define XHC_PRTHSC__AS_M_WIDTH 2U
+#define XHC_PRTHSC__AS_M_RESETVALUE 0x0U
+#define XHC_PRTHSC__CMD_L 3U
+#define XHC_PRTHSC__CMD_R 2U
+#define XHC_PRTHSC__CMD_WIDTH 2U
+#define XHC_PRTHSC__CMD_RESETVALUE 0x0U
+#define XHC_PRTHSC__reserved 1U
+#define XHC_PRTHSC__reserved_L 1U
+#define XHC_PRTHSC__reserved_R 1U
+#define XHC_PRTHSC__reserved_WIDTH 1U
+#define XHC_PRTHSC__reserved_RESETVALUE 0x0U
+#define XHC_PRTHSC__STB 0U
+#define XHC_PRTHSC__STB_L 0U
+#define XHC_PRTHSC__STB_R 0U
+#define XHC_PRTHSC__STB_WIDTH 1U
+#define XHC_PRTHSC__STB_RESETVALUE 0x0U
+#define XHC_PRTHSC__RESERVED_L 15U
+#define XHC_PRTHSC__RESERVED_R 8U
+#define XHC_PRTHSC_WIDTH 32U
+#define XHC_PRTHSC__WIDTH 32U
+#define XHC_PRTHSC_ALL_L 31U
+#define XHC_PRTHSC_ALL_R 0U
+#define XHC_PRTHSC__ALL_L 31U
+#define XHC_PRTHSC__ALL_R 0U
+#define XHC_PRTHSC_DATAMASK 0xffff00ffU
+#define XHC_PRTHSC_RDWRMASK 0x0000ff00U
+#define XHC_PRTHSC_RESETVALUE 0x00000000U
+
+#define XHC_PRTHSR_OFFSET 0xc7cU
+#define XHC_PRTHSR_BASE 0xc7cU
+#define XHC_PRTHSR__RDLY_L 31U
+#define XHC_PRTHSR__RDLY_R 24U
+#define XHC_PRTHSR__RDLY_WIDTH 8U
+#define XHC_PRTHSR__RDLY_RESETVALUE 0x00U
+#define XHC_PRTHSR__TDPP_L 23U
+#define XHC_PRTHSR__TDPP_R 16U
+#define XHC_PRTHSR__TDPP_WIDTH 8U
+#define XHC_PRTHSR__TDPP_RESETVALUE 0x00U
+#define XHC_PRTHSR__RDPP_L 15U
+#define XHC_PRTHSR__RDPP_R 8U
+#define XHC_PRTHSR__RDPP_WIDTH 8U
+#define XHC_PRTHSR__RDPP_RESETVALUE 0x00U
+#define XHC_PRTHSR__TRTY_L 7U
+#define XHC_PRTHSR__TRTY_R 0U
+#define XHC_PRTHSR__TRTY_WIDTH 8U
+#define XHC_PRTHSR__TRTY_RESETVALUE 0x00U
+#define XHC_PRTHSR_WIDTH 32U
+#define XHC_PRTHSR__WIDTH 32U
+#define XHC_PRTHSR_ALL_L 31U
+#define XHC_PRTHSR_ALL_R 0U
+#define XHC_PRTHSR__ALL_L 31U
+#define XHC_PRTHSR__ALL_R 0U
+#define XHC_PRTHSR_DATAMASK 0xffffffffU
+#define XHC_PRTHSR_RDWRMASK 0x00000000U
+#define XHC_PRTHSR_RESETVALUE 0x00000000U
+
+#define XHC_ECHRHS_OFFSET 0xc80U
+#define XHC_ECHRHS_BASE 0xc80U
+#define XHC_ECHRHS__RPO_L 30U
+#define XHC_ECHRHS__RPO_R 24U
+#define XHC_ECHRHS__RPO_WIDTH 7U
+#define XHC_ECHRHS__RPO_RESETVALUE 0x0U
+#define XHC_ECHRHS__reserved_L 23U
+#define XHC_ECHRHS__reserved_R 22U
+#define XHC_ECHRHS__reserved_WIDTH 2U
+#define XHC_ECHRHS__reserved_RESETVALUE 0x0U
+#define XHC_ECHRHS__RPN_L 21U
+#define XHC_ECHRHS__RPN_R 20U
+#define XHC_ECHRHS__RPN_WIDTH 2U
+#define XHC_ECHRHS__RPN_RESETVALUE 0x0U
+#define XHC_ECHRHS__DNR_L 19U
+#define XHC_ECHRHS__DNR_R 16U
+#define XHC_ECHRHS__DNR_WIDTH 4U
+#define XHC_ECHRHS__DNR_RESETVALUE 0x0U
+#define XHC_ECHRHS__NCP_L 15U
+#define XHC_ECHRHS__NCP_R 8U
+#define XHC_ECHRHS__NCP_WIDTH 8U
+#define XHC_ECHRHS__NCP_RESETVALUE 0x0cU
+#define XHC_ECHRHS__CID_L 7U
+#define XHC_ECHRHS__CID_R 0U
+#define XHC_ECHRHS__CID_WIDTH 8U
+#define XHC_ECHRHS__CID_RESETVALUE 0xc8U
+#define XHC_ECHRHS__RESERVED 31U
+#define XHC_ECHRHS__RESERVED_L 31U
+#define XHC_ECHRHS__RESERVED_R 31U
+#define XHC_ECHRHS_WIDTH 31U
+#define XHC_ECHRHS__WIDTH 31U
+#define XHC_ECHRHS_ALL_L 30U
+#define XHC_ECHRHS_ALL_R 0U
+#define XHC_ECHRHS__ALL_L 30U
+#define XHC_ECHRHS__ALL_R 0U
+#define XHC_ECHRHS_DATAMASK 0x7fffffffU
+#define XHC_ECHRHS_RDWRMASK 0x80000000U
+#define XHC_ECHRHS_RESETVALUE 0x00000cc8U
+
+#define XHC_RHSDES_OFFSET 0xc84U
+#define XHC_RHSDES_BASE 0xc84U
+#define XHC_RHSDES__PIS3_L 31U
+#define XHC_RHSDES__PIS3_R 30U
+#define XHC_RHSDES__PIS3_WIDTH 2U
+#define XHC_RHSDES__PIS3_RESETVALUE 0x0U
+#define XHC_RHSDES__HIST3 24U
+#define XHC_RHSDES__HIST3_L 24U
+#define XHC_RHSDES__HIST3_R 24U
+#define XHC_RHSDES__HIST3_WIDTH 1U
+#define XHC_RHSDES__HIST3_RESETVALUE 0x0U
+#define XHC_RHSDES__PIS2_L 23U
+#define XHC_RHSDES__PIS2_R 22U
+#define XHC_RHSDES__PIS2_WIDTH 2U
+#define XHC_RHSDES__PIS2_RESETVALUE 0x0U
+#define XHC_RHSDES__HIST2 16U
+#define XHC_RHSDES__HIST2_L 16U
+#define XHC_RHSDES__HIST2_R 16U
+#define XHC_RHSDES__HIST2_WIDTH 1U
+#define XHC_RHSDES__HIST2_RESETVALUE 0x0U
+#define XHC_RHSDES__PIS1_L 15U
+#define XHC_RHSDES__PIS1_R 14U
+#define XHC_RHSDES__PIS1_WIDTH 2U
+#define XHC_RHSDES__PIS1_RESETVALUE 0x0U
+#define XHC_RHSDES__HIST1 8U
+#define XHC_RHSDES__HIST1_L 8U
+#define XHC_RHSDES__HIST1_R 8U
+#define XHC_RHSDES__HIST1_WIDTH 1U
+#define XHC_RHSDES__HIST1_RESETVALUE 0x0U
+#define XHC_RHSDES__PIS0_L 7U
+#define XHC_RHSDES__PIS0_R 6U
+#define XHC_RHSDES__PIS0_WIDTH 2U
+#define XHC_RHSDES__PIS0_RESETVALUE 0x0U
+#define XHC_RHSDES__reserved_L 5U
+#define XHC_RHSDES__reserved_R 1U
+#define XHC_RHSDES__reserved_WIDTH 5U
+#define XHC_RHSDES__reserved_RESETVALUE 0x0U
+#define XHC_RHSDES__HIST0 0U
+#define XHC_RHSDES__HIST0_L 0U
+#define XHC_RHSDES__HIST0_R 0U
+#define XHC_RHSDES__HIST0_WIDTH 1U
+#define XHC_RHSDES__HIST0_RESETVALUE 0x0U
+#define XHC_RHSDES__RESERVED_0_L 29U
+#define XHC_RHSDES__RESERVED_0_R 25U
+#define XHC_RHSDES__RESERVED_1_L 21U
+#define XHC_RHSDES__RESERVED_1_R 17U
+#define XHC_RHSDES__RESERVED_2_L 13U
+#define XHC_RHSDES__RESERVED_2_R 9U
+#define XHC_RHSDES__RESERVED_L 29U
+#define XHC_RHSDES__RESERVED_R 25U
+#define XHC_RHSDES_WIDTH 32U
+#define XHC_RHSDES__WIDTH 32U
+#define XHC_RHSDES_ALL_L 31U
+#define XHC_RHSDES_ALL_R 0U
+#define XHC_RHSDES__ALL_L 31U
+#define XHC_RHSDES__ALL_R 0U
+#define XHC_RHSDES_DATAMASK 0xc1c1c1ffU
+#define XHC_RHSDES_RDWRMASK 0x3e3e3e00U
+#define XHC_RHSDES_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSC0_OFFSET 0xc90U
+#define XHC_RHSHSC0_BASE 0xc90U
+#define XHC_RHSHSC0__TMR_L 31U
+#define XHC_RHSHSC0__TMR_R 16U
+#define XHC_RHSHSC0__TMR_WIDTH 16U
+#define XHC_RHSHSC0__TMR_RESETVALUE 0x0000U
+#define XHC_RHSHSC0__RSL_L 7U
+#define XHC_RHSHSC0__RSL_R 6U
+#define XHC_RHSHSC0__RSL_WIDTH 2U
+#define XHC_RHSHSC0__RSL_RESETVALUE 0x0U
+#define XHC_RHSHSC0__AS_M_L 5U
+#define XHC_RHSHSC0__AS_M_R 4U
+#define XHC_RHSHSC0__AS_M_WIDTH 2U
+#define XHC_RHSHSC0__AS_M_RESETVALUE 0x0U
+#define XHC_RHSHSC0__CMD_L 3U
+#define XHC_RHSHSC0__CMD_R 2U
+#define XHC_RHSHSC0__CMD_WIDTH 2U
+#define XHC_RHSHSC0__CMD_RESETVALUE 0x0U
+#define XHC_RHSHSC0__reserved 1U
+#define XHC_RHSHSC0__reserved_L 1U
+#define XHC_RHSHSC0__reserved_R 1U
+#define XHC_RHSHSC0__reserved_WIDTH 1U
+#define XHC_RHSHSC0__reserved_RESETVALUE 0x0U
+#define XHC_RHSHSC0__STB 0U
+#define XHC_RHSHSC0__STB_L 0U
+#define XHC_RHSHSC0__STB_R 0U
+#define XHC_RHSHSC0__STB_WIDTH 1U
+#define XHC_RHSHSC0__STB_RESETVALUE 0x0U
+#define XHC_RHSHSC0__RESERVED_L 15U
+#define XHC_RHSHSC0__RESERVED_R 8U
+#define XHC_RHSHSC0_WIDTH 32U
+#define XHC_RHSHSC0__WIDTH 32U
+#define XHC_RHSHSC0_ALL_L 31U
+#define XHC_RHSHSC0_ALL_R 0U
+#define XHC_RHSHSC0__ALL_L 31U
+#define XHC_RHSHSC0__ALL_R 0U
+#define XHC_RHSHSC0_DATAMASK 0xffff00ffU
+#define XHC_RHSHSC0_RDWRMASK 0x0000ff00U
+#define XHC_RHSHSC0_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSR0_OFFSET 0xc94U
+#define XHC_RHSHSR0_BASE 0xc94U
+#define XHC_RHSHSR0__C2U_L 31U
+#define XHC_RHSHSR0__C2U_R 24U
+#define XHC_RHSHSR0__C2U_WIDTH 8U
+#define XHC_RHSHSR0__C2U_RESETVALUE 0x00U
+#define XHC_RHSHSR0__C1U_L 23U
+#define XHC_RHSHSR0__C1U_R 16U
+#define XHC_RHSHSR0__C1U_WIDTH 8U
+#define XHC_RHSHSR0__C1U_RESETVALUE 0x00U
+#define XHC_RHSHSR0__RCV_L 15U
+#define XHC_RHSHSR0__RCV_R 8U
+#define XHC_RHSHSR0__RCV_WIDTH 8U
+#define XHC_RHSHSR0__RCV_RESETVALUE 0x00U
+#define XHC_RHSHSR0__RTY_L 7U
+#define XHC_RHSHSR0__RTY_R 0U
+#define XHC_RHSHSR0__RTY_WIDTH 8U
+#define XHC_RHSHSR0__RTY_RESETVALUE 0x00U
+#define XHC_RHSHSR0_WIDTH 32U
+#define XHC_RHSHSR0__WIDTH 32U
+#define XHC_RHSHSR0_ALL_L 31U
+#define XHC_RHSHSR0_ALL_R 0U
+#define XHC_RHSHSR0__ALL_L 31U
+#define XHC_RHSHSR0__ALL_R 0U
+#define XHC_RHSHSR0_DATAMASK 0xffffffffU
+#define XHC_RHSHSR0_RDWRMASK 0x00000000U
+#define XHC_RHSHSR0_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSC1_OFFSET 0xc98U
+#define XHC_RHSHSC1_BASE 0xc98U
+#define XHC_RHSHSC1__TMR_L 31U
+#define XHC_RHSHSC1__TMR_R 16U
+#define XHC_RHSHSC1__TMR_WIDTH 16U
+#define XHC_RHSHSC1__TMR_RESETVALUE 0x0000U
+#define XHC_RHSHSC1__RSL_L 7U
+#define XHC_RHSHSC1__RSL_R 6U
+#define XHC_RHSHSC1__RSL_WIDTH 2U
+#define XHC_RHSHSC1__RSL_RESETVALUE 0x0U
+#define XHC_RHSHSC1__AS_M_L 5U
+#define XHC_RHSHSC1__AS_M_R 4U
+#define XHC_RHSHSC1__AS_M_WIDTH 2U
+#define XHC_RHSHSC1__AS_M_RESETVALUE 0x0U
+#define XHC_RHSHSC1__CMD_L 3U
+#define XHC_RHSHSC1__CMD_R 2U
+#define XHC_RHSHSC1__CMD_WIDTH 2U
+#define XHC_RHSHSC1__CMD_RESETVALUE 0x0U
+#define XHC_RHSHSC1__reserved 1U
+#define XHC_RHSHSC1__reserved_L 1U
+#define XHC_RHSHSC1__reserved_R 1U
+#define XHC_RHSHSC1__reserved_WIDTH 1U
+#define XHC_RHSHSC1__reserved_RESETVALUE 0x0U
+#define XHC_RHSHSC1__STB 0U
+#define XHC_RHSHSC1__STB_L 0U
+#define XHC_RHSHSC1__STB_R 0U
+#define XHC_RHSHSC1__STB_WIDTH 1U
+#define XHC_RHSHSC1__STB_RESETVALUE 0x0U
+#define XHC_RHSHSC1__RESERVED_L 15U
+#define XHC_RHSHSC1__RESERVED_R 8U
+#define XHC_RHSHSC1_WIDTH 32U
+#define XHC_RHSHSC1__WIDTH 32U
+#define XHC_RHSHSC1_ALL_L 31U
+#define XHC_RHSHSC1_ALL_R 0U
+#define XHC_RHSHSC1__ALL_L 31U
+#define XHC_RHSHSC1__ALL_R 0U
+#define XHC_RHSHSC1_DATAMASK 0xffff00ffU
+#define XHC_RHSHSC1_RDWRMASK 0x0000ff00U
+#define XHC_RHSHSC1_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSR1_OFFSET 0xc9cU
+#define XHC_RHSHSR1_BASE 0xc9cU
+#define XHC_RHSHSR1__C2U_L 31U
+#define XHC_RHSHSR1__C2U_R 24U
+#define XHC_RHSHSR1__C2U_WIDTH 8U
+#define XHC_RHSHSR1__C2U_RESETVALUE 0x00U
+#define XHC_RHSHSR1__C1U_L 23U
+#define XHC_RHSHSR1__C1U_R 16U
+#define XHC_RHSHSR1__C1U_WIDTH 8U
+#define XHC_RHSHSR1__C1U_RESETVALUE 0x00U
+#define XHC_RHSHSR1__RCV_L 15U
+#define XHC_RHSHSR1__RCV_R 8U
+#define XHC_RHSHSR1__RCV_WIDTH 8U
+#define XHC_RHSHSR1__RCV_RESETVALUE 0x00U
+#define XHC_RHSHSR1__RTY_L 7U
+#define XHC_RHSHSR1__RTY_R 0U
+#define XHC_RHSHSR1__RTY_WIDTH 8U
+#define XHC_RHSHSR1__RTY_RESETVALUE 0x00U
+#define XHC_RHSHSR1_WIDTH 32U
+#define XHC_RHSHSR1__WIDTH 32U
+#define XHC_RHSHSR1_ALL_L 31U
+#define XHC_RHSHSR1_ALL_R 0U
+#define XHC_RHSHSR1__ALL_L 31U
+#define XHC_RHSHSR1__ALL_R 0U
+#define XHC_RHSHSR1_DATAMASK 0xffffffffU
+#define XHC_RHSHSR1_RDWRMASK 0x00000000U
+#define XHC_RHSHSR1_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSC2_OFFSET 0xca0U
+#define XHC_RHSHSC2_BASE 0xca0U
+#define XHC_RHSHSC2__TMR_L 31U
+#define XHC_RHSHSC2__TMR_R 16U
+#define XHC_RHSHSC2__TMR_WIDTH 16U
+#define XHC_RHSHSC2__TMR_RESETVALUE 0x0000U
+#define XHC_RHSHSC2__RSL_L 7U
+#define XHC_RHSHSC2__RSL_R 6U
+#define XHC_RHSHSC2__RSL_WIDTH 2U
+#define XHC_RHSHSC2__RSL_RESETVALUE 0x0U
+#define XHC_RHSHSC2__AS_M_L 5U
+#define XHC_RHSHSC2__AS_M_R 4U
+#define XHC_RHSHSC2__AS_M_WIDTH 2U
+#define XHC_RHSHSC2__AS_M_RESETVALUE 0x0U
+#define XHC_RHSHSC2__CMD_L 3U
+#define XHC_RHSHSC2__CMD_R 2U
+#define XHC_RHSHSC2__CMD_WIDTH 2U
+#define XHC_RHSHSC2__CMD_RESETVALUE 0x0U
+#define XHC_RHSHSC2__reserved 1U
+#define XHC_RHSHSC2__reserved_L 1U
+#define XHC_RHSHSC2__reserved_R 1U
+#define XHC_RHSHSC2__reserved_WIDTH 1U
+#define XHC_RHSHSC2__reserved_RESETVALUE 0x0U
+#define XHC_RHSHSC2__STB 0U
+#define XHC_RHSHSC2__STB_L 0U
+#define XHC_RHSHSC2__STB_R 0U
+#define XHC_RHSHSC2__STB_WIDTH 1U
+#define XHC_RHSHSC2__STB_RESETVALUE 0x0U
+#define XHC_RHSHSC2__RESERVED_L 15U
+#define XHC_RHSHSC2__RESERVED_R 8U
+#define XHC_RHSHSC2_WIDTH 32U
+#define XHC_RHSHSC2__WIDTH 32U
+#define XHC_RHSHSC2_ALL_L 31U
+#define XHC_RHSHSC2_ALL_R 0U
+#define XHC_RHSHSC2__ALL_L 31U
+#define XHC_RHSHSC2__ALL_R 0U
+#define XHC_RHSHSC2_DATAMASK 0xffff00ffU
+#define XHC_RHSHSC2_RDWRMASK 0x0000ff00U
+#define XHC_RHSHSC2_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSR2_OFFSET 0xca4U
+#define XHC_RHSHSR2_BASE 0xca4U
+#define XHC_RHSHSR2__C2U_L 31U
+#define XHC_RHSHSR2__C2U_R 24U
+#define XHC_RHSHSR2__C2U_WIDTH 8U
+#define XHC_RHSHSR2__C2U_RESETVALUE 0x00U
+#define XHC_RHSHSR2__C1U_L 23U
+#define XHC_RHSHSR2__C1U_R 16U
+#define XHC_RHSHSR2__C1U_WIDTH 8U
+#define XHC_RHSHSR2__C1U_RESETVALUE 0x00U
+#define XHC_RHSHSR2__RCV_L 15U
+#define XHC_RHSHSR2__RCV_R 8U
+#define XHC_RHSHSR2__RCV_WIDTH 8U
+#define XHC_RHSHSR2__RCV_RESETVALUE 0x00U
+#define XHC_RHSHSR2__RTY_L 7U
+#define XHC_RHSHSR2__RTY_R 0U
+#define XHC_RHSHSR2__RTY_WIDTH 8U
+#define XHC_RHSHSR2__RTY_RESETVALUE 0x00U
+#define XHC_RHSHSR2_WIDTH 32U
+#define XHC_RHSHSR2__WIDTH 32U
+#define XHC_RHSHSR2_ALL_L 31U
+#define XHC_RHSHSR2_ALL_R 0U
+#define XHC_RHSHSR2__ALL_L 31U
+#define XHC_RHSHSR2__ALL_R 0U
+#define XHC_RHSHSR2_DATAMASK 0xffffffffU
+#define XHC_RHSHSR2_RDWRMASK 0x00000000U
+#define XHC_RHSHSR2_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSC3_OFFSET 0xca8U
+#define XHC_RHSHSC3_BASE 0xca8U
+#define XHC_RHSHSC3__TMR_L 31U
+#define XHC_RHSHSC3__TMR_R 16U
+#define XHC_RHSHSC3__TMR_WIDTH 16U
+#define XHC_RHSHSC3__TMR_RESETVALUE 0x0000U
+#define XHC_RHSHSC3__RSL_L 7U
+#define XHC_RHSHSC3__RSL_R 6U
+#define XHC_RHSHSC3__RSL_WIDTH 2U
+#define XHC_RHSHSC3__RSL_RESETVALUE 0x0U
+#define XHC_RHSHSC3__AS_M_L 5U
+#define XHC_RHSHSC3__AS_M_R 4U
+#define XHC_RHSHSC3__AS_M_WIDTH 2U
+#define XHC_RHSHSC3__AS_M_RESETVALUE 0x0U
+#define XHC_RHSHSC3__CMD_L 3U
+#define XHC_RHSHSC3__CMD_R 2U
+#define XHC_RHSHSC3__CMD_WIDTH 2U
+#define XHC_RHSHSC3__CMD_RESETVALUE 0x0U
+#define XHC_RHSHSC3__reserved 1U
+#define XHC_RHSHSC3__reserved_L 1U
+#define XHC_RHSHSC3__reserved_R 1U
+#define XHC_RHSHSC3__reserved_WIDTH 1U
+#define XHC_RHSHSC3__reserved_RESETVALUE 0x0U
+#define XHC_RHSHSC3__STB 0U
+#define XHC_RHSHSC3__STB_L 0U
+#define XHC_RHSHSC3__STB_R 0U
+#define XHC_RHSHSC3__STB_WIDTH 1U
+#define XHC_RHSHSC3__STB_RESETVALUE 0x0U
+#define XHC_RHSHSC3__RESERVED_L 15U
+#define XHC_RHSHSC3__RESERVED_R 8U
+#define XHC_RHSHSC3_WIDTH 32U
+#define XHC_RHSHSC3__WIDTH 32U
+#define XHC_RHSHSC3_ALL_L 31U
+#define XHC_RHSHSC3_ALL_R 0U
+#define XHC_RHSHSC3__ALL_L 31U
+#define XHC_RHSHSC3__ALL_R 0U
+#define XHC_RHSHSC3_DATAMASK 0xffff00ffU
+#define XHC_RHSHSC3_RDWRMASK 0x0000ff00U
+#define XHC_RHSHSC3_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSR3_OFFSET 0xcacU
+#define XHC_RHSHSR3_BASE 0xcacU
+#define XHC_RHSHSR3__C2U_L 31U
+#define XHC_RHSHSR3__C2U_R 24U
+#define XHC_RHSHSR3__C2U_WIDTH 8U
+#define XHC_RHSHSR3__C2U_RESETVALUE 0x00U
+#define XHC_RHSHSR3__C1U_L 23U
+#define XHC_RHSHSR3__C1U_R 16U
+#define XHC_RHSHSR3__C1U_WIDTH 8U
+#define XHC_RHSHSR3__C1U_RESETVALUE 0x00U
+#define XHC_RHSHSR3__RCV_L 15U
+#define XHC_RHSHSR3__RCV_R 8U
+#define XHC_RHSHSR3__RCV_WIDTH 8U
+#define XHC_RHSHSR3__RCV_RESETVALUE 0x00U
+#define XHC_RHSHSR3__RTY_L 7U
+#define XHC_RHSHSR3__RTY_R 0U
+#define XHC_RHSHSR3__RTY_WIDTH 8U
+#define XHC_RHSHSR3__RTY_RESETVALUE 0x00U
+#define XHC_RHSHSR3_WIDTH 32U
+#define XHC_RHSHSR3__WIDTH 32U
+#define XHC_RHSHSR3_ALL_L 31U
+#define XHC_RHSHSR3_ALL_R 0U
+#define XHC_RHSHSR3__ALL_L 31U
+#define XHC_RHSHSR3__ALL_R 0U
+#define XHC_RHSHSR3_DATAMASK 0xffffffffU
+#define XHC_RHSHSR3_RDWRMASK 0x00000000U
+#define XHC_RHSHSR3_RESETVALUE 0x00000000U
+
+#define XHC_ECHSSP_OFFSET 0xcb0U
+#define XHC_ECHSSP_BASE 0xcb0U
+#define XHC_ECHSSP__reserved_L 31U
+#define XHC_ECHSSP__reserved_R 16U
+#define XHC_ECHSSP__reserved_WIDTH 16U
+#define XHC_ECHSSP__reserved_RESETVALUE 0x0000U
+#define XHC_ECHSSP__NCP_L 15U
+#define XHC_ECHSSP__NCP_R 8U
+#define XHC_ECHSSP__NCP_WIDTH 8U
+#define XHC_ECHSSP__NCP_RESETVALUE 0x04U
+#define XHC_ECHSSP__CID_L 7U
+#define XHC_ECHSSP__CID_R 0U
+#define XHC_ECHSSP__CID_WIDTH 8U
+#define XHC_ECHSSP__CID_RESETVALUE 0xc6U
+#define XHC_ECHSSP_WIDTH 32U
+#define XHC_ECHSSP__WIDTH 32U
+#define XHC_ECHSSP_ALL_L 31U
+#define XHC_ECHSSP_ALL_R 0U
+#define XHC_ECHSSP__ALL_L 31U
+#define XHC_ECHSSP__ALL_R 0U
+#define XHC_ECHSSP_DATAMASK 0xffffffffU
+#define XHC_ECHSSP_RDWRMASK 0x00000000U
+#define XHC_ECHSSP_RESETVALUE 0x000004c6U
+
+#define XHC_SSPVER_OFFSET 0xcb4U
+#define XHC_SSPVER_BASE 0xcb4U
+#define XHC_SSPVER__MAJ_L 31U
+#define XHC_SSPVER__MAJ_R 28U
+#define XHC_SSPVER__MAJ_WIDTH 4U
+#define XHC_SSPVER__MAJ_RESETVALUE 0x0U
+#define XHC_SSPVER__MIN_L 27U
+#define XHC_SSPVER__MIN_R 24U
+#define XHC_SSPVER__MIN_WIDTH 4U
+#define XHC_SSPVER__MIN_RESETVALUE 0x0U
+#define XHC_SSPVER__RLS_L 23U
+#define XHC_SSPVER__RLS_R 20U
+#define XHC_SSPVER__RLS_WIDTH 4U
+#define XHC_SSPVER__RLS_RESETVALUE 0x0U
+#define XHC_SSPVER__reserved_L 19U
+#define XHC_SSPVER__reserved_R 0U
+#define XHC_SSPVER__reserved_WIDTH 20U
+#define XHC_SSPVER__reserved_RESETVALUE 0x00000U
+#define XHC_SSPVER_WIDTH 32U
+#define XHC_SSPVER__WIDTH 32U
+#define XHC_SSPVER_ALL_L 31U
+#define XHC_SSPVER_ALL_R 0U
+#define XHC_SSPVER__ALL_L 31U
+#define XHC_SSPVER__ALL_R 0U
+#define XHC_SSPVER_DATAMASK 0xffffffffU
+#define XHC_SSPVER_RDWRMASK 0x00000000U
+#define XHC_SSPVER_RESETVALUE 0x00000000U
+
+#define XHC_SSPMGN_OFFSET 0xcb8U
+#define XHC_SSPMGN_BASE 0xcb8U
+#define XHC_SSPMGN__MGN_L 31U
+#define XHC_SSPMGN__MGN_R 0U
+#define XHC_SSPMGN__MGN_WIDTH 32U
+#define XHC_SSPMGN__MGN_RESETVALUE 0x4b535040U
+#define XHC_SSPMGN_WIDTH 32U
+#define XHC_SSPMGN__WIDTH 32U
+#define XHC_SSPMGN_ALL_L 31U
+#define XHC_SSPMGN_ALL_R 0U
+#define XHC_SSPMGN__ALL_L 31U
+#define XHC_SSPMGN__ALL_R 0U
+#define XHC_SSPMGN_DATAMASK 0xffffffffU
+#define XHC_SSPMGN_RDWRMASK 0x00000000U
+#define XHC_SSPMGN_RESETVALUE 0x4b535040U
+
+#define XHC_ECHFSC2_OFFSET 0xcc0U
+#define XHC_ECHFSC2_BASE 0xcc0U
+#define XHC_ECHFSC2__reserved_L 31U
+#define XHC_ECHFSC2__reserved_R 16U
+#define XHC_ECHFSC2__reserved_WIDTH 16U
+#define XHC_ECHFSC2__reserved_RESETVALUE 0x0000U
+#define XHC_ECHFSC2__NCP_L 15U
+#define XHC_ECHFSC2__NCP_R 8U
+#define XHC_ECHFSC2__NCP_WIDTH 8U
+#define XHC_ECHFSC2__NCP_RESETVALUE 0x50U
+#define XHC_ECHFSC2__CID_L 7U
+#define XHC_ECHFSC2__CID_R 0U
+#define XHC_ECHFSC2__CID_WIDTH 8U
+#define XHC_ECHFSC2__CID_RESETVALUE 0xc7U
+#define XHC_ECHFSC2_WIDTH 32U
+#define XHC_ECHFSC2__WIDTH 32U
+#define XHC_ECHFSC2_ALL_L 31U
+#define XHC_ECHFSC2_ALL_R 0U
+#define XHC_ECHFSC2__ALL_L 31U
+#define XHC_ECHFSC2__ALL_R 0U
+#define XHC_ECHFSC2_DATAMASK 0xffffffffU
+#define XHC_ECHFSC2_RDWRMASK 0x00000000U
+#define XHC_ECHFSC2_RESETVALUE 0x000050c7U
+
+#define XHC_FSC2POC_OFFSET 0xcd4U
+#define XHC_FSC2POC_BASE 0xcd4U
+#define XHC_FSC2POC__NCS_L 31U
+#define XHC_FSC2POC__NCS_R 28U
+#define XHC_FSC2POC__NCS_WIDTH 4U
+#define XHC_FSC2POC__NCS_RESETVALUE 0x0U
+#define XHC_FSC2POC__FSIZ_L 22U
+#define XHC_FSC2POC__FSIZ_R 18U
+#define XHC_FSC2POC__FSIZ_WIDTH 5U
+#define XHC_FSC2POC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSC2POC__PSIZ_L 16U
+#define XHC_FSC2POC__PSIZ_R 12U
+#define XHC_FSC2POC__PSIZ_WIDTH 5U
+#define XHC_FSC2POC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSC2POC__reserved_L 11U
+#define XHC_FSC2POC__reserved_R 5U
+#define XHC_FSC2POC__reserved_WIDTH 7U
+#define XHC_FSC2POC__reserved_RESETVALUE 0x0U
+#define XHC_FSC2POC__TSIZ_L 4U
+#define XHC_FSC2POC__TSIZ_R 0U
+#define XHC_FSC2POC__TSIZ_WIDTH 5U
+#define XHC_FSC2POC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSC2POC__RESERVED_L 27U
+#define XHC_FSC2POC__RESERVED_R 23U
+#define XHC_FSC2POC_WIDTH 32U
+#define XHC_FSC2POC__WIDTH 32U
+#define XHC_FSC2POC_ALL_L 31U
+#define XHC_FSC2POC_ALL_R 0U
+#define XHC_FSC2POC__ALL_L 31U
+#define XHC_FSC2POC__ALL_R 0U
+#define XHC_FSC2POC_DATAMASK 0xf07dffffU
+#define XHC_FSC2POC_RDWRMASK 0x0f820000U
+#define XHC_FSC2POC_RESETVALUE 0x00000000U
+
+#define XHC_FSC2GOC_OFFSET 0xcd8U
+#define XHC_FSC2GOC_BASE 0xcd8U
+#define XHC_FSC2GOC__NCS_L 31U
+#define XHC_FSC2GOC__NCS_R 28U
+#define XHC_FSC2GOC__NCS_WIDTH 4U
+#define XHC_FSC2GOC__NCS_RESETVALUE 0x0U
+#define XHC_FSC2GOC__FSIZ_L 22U
+#define XHC_FSC2GOC__FSIZ_R 18U
+#define XHC_FSC2GOC__FSIZ_WIDTH 5U
+#define XHC_FSC2GOC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSC2GOC__PSIZ_L 16U
+#define XHC_FSC2GOC__PSIZ_R 12U
+#define XHC_FSC2GOC__PSIZ_WIDTH 5U
+#define XHC_FSC2GOC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSC2GOC__reserved_L 11U
+#define XHC_FSC2GOC__reserved_R 5U
+#define XHC_FSC2GOC__reserved_WIDTH 7U
+#define XHC_FSC2GOC__reserved_RESETVALUE 0x0U
+#define XHC_FSC2GOC__TSIZ_L 4U
+#define XHC_FSC2GOC__TSIZ_R 0U
+#define XHC_FSC2GOC__TSIZ_WIDTH 5U
+#define XHC_FSC2GOC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSC2GOC__RESERVED_L 27U
+#define XHC_FSC2GOC__RESERVED_R 23U
+#define XHC_FSC2GOC_WIDTH 32U
+#define XHC_FSC2GOC__WIDTH 32U
+#define XHC_FSC2GOC_ALL_L 31U
+#define XHC_FSC2GOC_ALL_R 0U
+#define XHC_FSC2GOC__ALL_L 31U
+#define XHC_FSC2GOC__ALL_R 0U
+#define XHC_FSC2GOC_DATAMASK 0xf07dffffU
+#define XHC_FSC2GOC_RDWRMASK 0x0f820000U
+#define XHC_FSC2GOC_RESETVALUE 0x00000000U
+
+#define XHC_FSC2NOC_OFFSET 0xcdcU
+#define XHC_FSC2NOC_BASE 0xcdcU
+#define XHC_FSC2NOC__NCS_L 31U
+#define XHC_FSC2NOC__NCS_R 28U
+#define XHC_FSC2NOC__NCS_WIDTH 4U
+#define XHC_FSC2NOC__NCS_RESETVALUE 0x0U
+#define XHC_FSC2NOC__FSIZ_L 22U
+#define XHC_FSC2NOC__FSIZ_R 18U
+#define XHC_FSC2NOC__FSIZ_WIDTH 5U
+#define XHC_FSC2NOC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSC2NOC__PSIZ_L 16U
+#define XHC_FSC2NOC__PSIZ_R 12U
+#define XHC_FSC2NOC__PSIZ_WIDTH 5U
+#define XHC_FSC2NOC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSC2NOC__reserved_L 11U
+#define XHC_FSC2NOC__reserved_R 5U
+#define XHC_FSC2NOC__reserved_WIDTH 7U
+#define XHC_FSC2NOC__reserved_RESETVALUE 0x0U
+#define XHC_FSC2NOC__TSIZ_L 4U
+#define XHC_FSC2NOC__TSIZ_R 0U
+#define XHC_FSC2NOC__TSIZ_WIDTH 5U
+#define XHC_FSC2NOC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSC2NOC__RESERVED_L 27U
+#define XHC_FSC2NOC__RESERVED_R 23U
+#define XHC_FSC2NOC_WIDTH 32U
+#define XHC_FSC2NOC__WIDTH 32U
+#define XHC_FSC2NOC_ALL_L 31U
+#define XHC_FSC2NOC_ALL_R 0U
+#define XHC_FSC2NOC__ALL_L 31U
+#define XHC_FSC2NOC__ALL_R 0U
+#define XHC_FSC2NOC_DATAMASK 0xf07dffffU
+#define XHC_FSC2NOC_RDWRMASK 0x0f820000U
+#define XHC_FSC2NOC_RESETVALUE 0x00000000U
+
+#define XHC_FSC2AIC_OFFSET 0xce0U
+#define XHC_FSC2AIC_BASE 0xce0U
+#define XHC_FSC2AIC__FSIZ_L 22U
+#define XHC_FSC2AIC__FSIZ_R 18U
+#define XHC_FSC2AIC__FSIZ_WIDTH 5U
+#define XHC_FSC2AIC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSC2AIC__PSIZ_L 16U
+#define XHC_FSC2AIC__PSIZ_R 12U
+#define XHC_FSC2AIC__PSIZ_WIDTH 5U
+#define XHC_FSC2AIC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSC2AIC__reserved_L 11U
+#define XHC_FSC2AIC__reserved_R 0U
+#define XHC_FSC2AIC__reserved_WIDTH 12U
+#define XHC_FSC2AIC__reserved_RESETVALUE 0x000U
+#define XHC_FSC2AIC__RESERVED_L 31U
+#define XHC_FSC2AIC__RESERVED_R 23U
+#define XHC_FSC2AIC_WIDTH 23U
+#define XHC_FSC2AIC__WIDTH 23U
+#define XHC_FSC2AIC_ALL_L 22U
+#define XHC_FSC2AIC_ALL_R 0U
+#define XHC_FSC2AIC__ALL_L 22U
+#define XHC_FSC2AIC__ALL_R 0U
+#define XHC_FSC2AIC_DATAMASK 0x007dffffU
+#define XHC_FSC2AIC_RDWRMASK 0xff820000U
+#define XHC_FSC2AIC_RESETVALUE 0x000000U
+
+#define XHC_FSC2PIC_OFFSET 0xce4U
+#define XHC_FSC2PIC_BASE 0xce4U
+#define XHC_FSC2PIC__NCS_L 31U
+#define XHC_FSC2PIC__NCS_R 28U
+#define XHC_FSC2PIC__NCS_WIDTH 4U
+#define XHC_FSC2PIC__NCS_RESETVALUE 0x0U
+#define XHC_FSC2PIC__reserved_L 27U
+#define XHC_FSC2PIC__reserved_R 5U
+#define XHC_FSC2PIC__reserved_WIDTH 23U
+#define XHC_FSC2PIC__reserved_RESETVALUE 0x0U
+#define XHC_FSC2PIC__TSIZ_L 4U
+#define XHC_FSC2PIC__TSIZ_R 0U
+#define XHC_FSC2PIC__TSIZ_WIDTH 5U
+#define XHC_FSC2PIC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSC2PIC_WIDTH 32U
+#define XHC_FSC2PIC__WIDTH 32U
+#define XHC_FSC2PIC_ALL_L 31U
+#define XHC_FSC2PIC_ALL_R 0U
+#define XHC_FSC2PIC__ALL_L 31U
+#define XHC_FSC2PIC__ALL_R 0U
+#define XHC_FSC2PIC_DATAMASK 0xffffffffU
+#define XHC_FSC2PIC_RDWRMASK 0x00000000U
+#define XHC_FSC2PIC_RESETVALUE 0x00000000U
+
+#define XHC_FSC2GIC_OFFSET 0xce8U
+#define XHC_FSC2GIC_BASE 0xce8U
+#define XHC_FSC2GIC__NCS_L 31U
+#define XHC_FSC2GIC__NCS_R 28U
+#define XHC_FSC2GIC__NCS_WIDTH 4U
+#define XHC_FSC2GIC__NCS_RESETVALUE 0x0U
+#define XHC_FSC2GIC__reserved_L 27U
+#define XHC_FSC2GIC__reserved_R 5U
+#define XHC_FSC2GIC__reserved_WIDTH 23U
+#define XHC_FSC2GIC__reserved_RESETVALUE 0x0U
+#define XHC_FSC2GIC__TSIZ_L 4U
+#define XHC_FSC2GIC__TSIZ_R 0U
+#define XHC_FSC2GIC__TSIZ_WIDTH 5U
+#define XHC_FSC2GIC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSC2GIC_WIDTH 32U
+#define XHC_FSC2GIC__WIDTH 32U
+#define XHC_FSC2GIC_ALL_L 31U
+#define XHC_FSC2GIC_ALL_R 0U
+#define XHC_FSC2GIC__ALL_L 31U
+#define XHC_FSC2GIC__ALL_R 0U
+#define XHC_FSC2GIC_DATAMASK 0xffffffffU
+#define XHC_FSC2GIC_RDWRMASK 0x00000000U
+#define XHC_FSC2GIC_RESETVALUE 0x00000000U
+
+#define XHC_FSC2NIC_OFFSET 0xcecU
+#define XHC_FSC2NIC_BASE 0xcecU
+#define XHC_FSC2NIC__NCS_L 31U
+#define XHC_FSC2NIC__NCS_R 28U
+#define XHC_FSC2NIC__NCS_WIDTH 4U
+#define XHC_FSC2NIC__NCS_RESETVALUE 0x0U
+#define XHC_FSC2NIC__reserved_L 27U
+#define XHC_FSC2NIC__reserved_R 5U
+#define XHC_FSC2NIC__reserved_WIDTH 23U
+#define XHC_FSC2NIC__reserved_RESETVALUE 0x0U
+#define XHC_FSC2NIC__TSIZ_L 4U
+#define XHC_FSC2NIC__TSIZ_R 0U
+#define XHC_FSC2NIC__TSIZ_WIDTH 5U
+#define XHC_FSC2NIC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSC2NIC_WIDTH 32U
+#define XHC_FSC2NIC__WIDTH 32U
+#define XHC_FSC2NIC_ALL_L 31U
+#define XHC_FSC2NIC_ALL_R 0U
+#define XHC_FSC2NIC__ALL_L 31U
+#define XHC_FSC2NIC__ALL_R 0U
+#define XHC_FSC2NIC_DATAMASK 0xffffffffU
+#define XHC_FSC2NIC_RDWRMASK 0x00000000U
+#define XHC_FSC2NIC_RESETVALUE 0x00000000U
+
+#define XHC_ECHPRT2_OFFSET 0xcf0U
+#define XHC_ECHPRT2_BASE 0xcf0U
+#define XHC_ECHPRT2__HDP 31U
+#define XHC_ECHPRT2__HDP_L 31U
+#define XHC_ECHPRT2__HDP_R 31U
+#define XHC_ECHPRT2__HDP_WIDTH 1U
+#define XHC_ECHPRT2__HDP_RESETVALUE 0x0U
+#define XHC_ECHPRT2__FDP 30U
+#define XHC_ECHPRT2__FDP_L 30U
+#define XHC_ECHPRT2__FDP_R 30U
+#define XHC_ECHPRT2__FDP_WIDTH 1U
+#define XHC_ECHPRT2__FDP_RESETVALUE 0x0U
+#define XHC_ECHPRT2__reserved_L 29U
+#define XHC_ECHPRT2__reserved_R 17U
+#define XHC_ECHPRT2__reserved_WIDTH 13U
+#define XHC_ECHPRT2__reserved_RESETVALUE 0x0U
+#define XHC_ECHPRT2__HST 16U
+#define XHC_ECHPRT2__HST_L 16U
+#define XHC_ECHPRT2__HST_R 16U
+#define XHC_ECHPRT2__HST_WIDTH 1U
+#define XHC_ECHPRT2__HST_RESETVALUE 0x0U
+#define XHC_ECHPRT2__NCP_L 15U
+#define XHC_ECHPRT2__NCP_R 8U
+#define XHC_ECHPRT2__NCP_WIDTH 8U
+#define XHC_ECHPRT2__NCP_RESETVALUE 0x04U
+#define XHC_ECHPRT2__CID_L 7U
+#define XHC_ECHPRT2__CID_R 0U
+#define XHC_ECHPRT2__CID_WIDTH 8U
+#define XHC_ECHPRT2__CID_RESETVALUE 0xc8U
+#define XHC_ECHPRT2_WIDTH 32U
+#define XHC_ECHPRT2__WIDTH 32U
+#define XHC_ECHPRT2_ALL_L 31U
+#define XHC_ECHPRT2_ALL_R 0U
+#define XHC_ECHPRT2__ALL_L 31U
+#define XHC_ECHPRT2__ALL_R 0U
+#define XHC_ECHPRT2_DATAMASK 0xffffffffU
+#define XHC_ECHPRT2_RDWRMASK 0x00000000U
+#define XHC_ECHPRT2_RESETVALUE 0x000004c8U
+
+#define XHC_PRT2HSC_OFFSET 0xcf8U
+#define XHC_PRT2HSC_BASE 0xcf8U
+#define XHC_PRT2HSC__TMR_L 31U
+#define XHC_PRT2HSC__TMR_R 16U
+#define XHC_PRT2HSC__TMR_WIDTH 16U
+#define XHC_PRT2HSC__TMR_RESETVALUE 0x0000U
+#define XHC_PRT2HSC__RSL_L 7U
+#define XHC_PRT2HSC__RSL_R 6U
+#define XHC_PRT2HSC__RSL_WIDTH 2U
+#define XHC_PRT2HSC__RSL_RESETVALUE 0x0U
+#define XHC_PRT2HSC__AS_M_L 5U
+#define XHC_PRT2HSC__AS_M_R 4U
+#define XHC_PRT2HSC__AS_M_WIDTH 2U
+#define XHC_PRT2HSC__AS_M_RESETVALUE 0x0U
+#define XHC_PRT2HSC__CMD_L 3U
+#define XHC_PRT2HSC__CMD_R 2U
+#define XHC_PRT2HSC__CMD_WIDTH 2U
+#define XHC_PRT2HSC__CMD_RESETVALUE 0x0U
+#define XHC_PRT2HSC__reserved 1U
+#define XHC_PRT2HSC__reserved_L 1U
+#define XHC_PRT2HSC__reserved_R 1U
+#define XHC_PRT2HSC__reserved_WIDTH 1U
+#define XHC_PRT2HSC__reserved_RESETVALUE 0x0U
+#define XHC_PRT2HSC__STB 0U
+#define XHC_PRT2HSC__STB_L 0U
+#define XHC_PRT2HSC__STB_R 0U
+#define XHC_PRT2HSC__STB_WIDTH 1U
+#define XHC_PRT2HSC__STB_RESETVALUE 0x0U
+#define XHC_PRT2HSC__RESERVED_L 15U
+#define XHC_PRT2HSC__RESERVED_R 8U
+#define XHC_PRT2HSC_WIDTH 32U
+#define XHC_PRT2HSC__WIDTH 32U
+#define XHC_PRT2HSC_ALL_L 31U
+#define XHC_PRT2HSC_ALL_R 0U
+#define XHC_PRT2HSC__ALL_L 31U
+#define XHC_PRT2HSC__ALL_R 0U
+#define XHC_PRT2HSC_DATAMASK 0xffff00ffU
+#define XHC_PRT2HSC_RDWRMASK 0x0000ff00U
+#define XHC_PRT2HSC_RESETVALUE 0x00000000U
+
+#define XHC_PRT2HSR_OFFSET 0xcfcU
+#define XHC_PRT2HSR_BASE 0xcfcU
+#define XHC_PRT2HSR__RNAK_L 31U
+#define XHC_PRT2HSR__RNAK_R 24U
+#define XHC_PRT2HSR__RNAK_WIDTH 8U
+#define XHC_PRT2HSR__RNAK_RESETVALUE 0x00U
+#define XHC_PRT2HSR__HSTX_L 23U
+#define XHC_PRT2HSR__HSTX_R 16U
+#define XHC_PRT2HSR__HSTX_WIDTH 8U
+#define XHC_PRT2HSR__HSTX_RESETVALUE 0x00U
+#define XHC_PRT2HSR__HSRX_L 15U
+#define XHC_PRT2HSR__HSRX_R 8U
+#define XHC_PRT2HSR__HSRX_WIDTH 8U
+#define XHC_PRT2HSR__HSRX_RESETVALUE 0x00U
+#define XHC_PRT2HSR__SPLT_L 7U
+#define XHC_PRT2HSR__SPLT_R 0U
+#define XHC_PRT2HSR__SPLT_WIDTH 8U
+#define XHC_PRT2HSR__SPLT_RESETVALUE 0x00U
+#define XHC_PRT2HSR_WIDTH 32U
+#define XHC_PRT2HSR__WIDTH 32U
+#define XHC_PRT2HSR_ALL_L 31U
+#define XHC_PRT2HSR_ALL_R 0U
+#define XHC_PRT2HSR__ALL_L 31U
+#define XHC_PRT2HSR__ALL_R 0U
+#define XHC_PRT2HSR_DATAMASK 0xffffffffU
+#define XHC_PRT2HSR_RDWRMASK 0x00000000U
+#define XHC_PRT2HSR_RESETVALUE 0x00000000U
+
+#define XHC_ECHRH2_OFFSET 0xd00U
+#define XHC_ECHRH2_BASE 0xd00U
+#define XHC_ECHRH2__MTT 31U
+#define XHC_ECHRH2__MTT_L 31U
+#define XHC_ECHRH2__MTT_R 31U
+#define XHC_ECHRH2__MTT_WIDTH 1U
+#define XHC_ECHRH2__MTT_RESETVALUE 0x0U
+#define XHC_ECHRH2__RPO_L 30U
+#define XHC_ECHRH2__RPO_R 24U
+#define XHC_ECHRH2__RPO_WIDTH 7U
+#define XHC_ECHRH2__RPO_RESETVALUE 0x0U
+#define XHC_ECHRH2__reserved_L 23U
+#define XHC_ECHRH2__reserved_R 22U
+#define XHC_ECHRH2__reserved_WIDTH 2U
+#define XHC_ECHRH2__reserved_RESETVALUE 0x0U
+#define XHC_ECHRH2__RPN_L 21U
+#define XHC_ECHRH2__RPN_R 20U
+#define XHC_ECHRH2__RPN_WIDTH 2U
+#define XHC_ECHRH2__RPN_RESETVALUE 0x0U
+#define XHC_ECHRH2__DNR_L 19U
+#define XHC_ECHRH2__DNR_R 16U
+#define XHC_ECHRH2__DNR_WIDTH 4U
+#define XHC_ECHRH2__DNR_RESETVALUE 0x0U
+#define XHC_ECHRH2__NCP_L 15U
+#define XHC_ECHRH2__NCP_R 8U
+#define XHC_ECHRH2__NCP_WIDTH 8U
+#define XHC_ECHRH2__NCP_RESETVALUE 0x0cU
+#define XHC_ECHRH2__CID_L 7U
+#define XHC_ECHRH2__CID_R 0U
+#define XHC_ECHRH2__CID_WIDTH 8U
+#define XHC_ECHRH2__CID_RESETVALUE 0xc9U
+#define XHC_ECHRH2_WIDTH 32U
+#define XHC_ECHRH2__WIDTH 32U
+#define XHC_ECHRH2_ALL_L 31U
+#define XHC_ECHRH2_ALL_R 0U
+#define XHC_ECHRH2__ALL_L 31U
+#define XHC_ECHRH2__ALL_R 0U
+#define XHC_ECHRH2_DATAMASK 0xffffffffU
+#define XHC_ECHRH2_RDWRMASK 0x00000000U
+#define XHC_ECHRH2_RESETVALUE 0x00000cc9U
+
+#define XHC_RH2DES_OFFSET 0xd04U
+#define XHC_RH2DES_BASE 0xd04U
+#define XHC_RH2DES__PIS3_L 31U
+#define XHC_RH2DES__PIS3_R 30U
+#define XHC_RH2DES__PIS3_WIDTH 2U
+#define XHC_RH2DES__PIS3_RESETVALUE 0x0U
+#define XHC_RH2DES__HIST3 24U
+#define XHC_RH2DES__HIST3_L 24U
+#define XHC_RH2DES__HIST3_R 24U
+#define XHC_RH2DES__HIST3_WIDTH 1U
+#define XHC_RH2DES__HIST3_RESETVALUE 0x0U
+#define XHC_RH2DES__PIS2_L 23U
+#define XHC_RH2DES__PIS2_R 22U
+#define XHC_RH2DES__PIS2_WIDTH 2U
+#define XHC_RH2DES__PIS2_RESETVALUE 0x0U
+#define XHC_RH2DES__HIST2 16U
+#define XHC_RH2DES__HIST2_L 16U
+#define XHC_RH2DES__HIST2_R 16U
+#define XHC_RH2DES__HIST2_WIDTH 1U
+#define XHC_RH2DES__HIST2_RESETVALUE 0x0U
+#define XHC_RH2DES__PIS1_L 15U
+#define XHC_RH2DES__PIS1_R 14U
+#define XHC_RH2DES__PIS1_WIDTH 2U
+#define XHC_RH2DES__PIS1_RESETVALUE 0x0U
+#define XHC_RH2DES__HIST1 8U
+#define XHC_RH2DES__HIST1_L 8U
+#define XHC_RH2DES__HIST1_R 8U
+#define XHC_RH2DES__HIST1_WIDTH 1U
+#define XHC_RH2DES__HIST1_RESETVALUE 0x0U
+#define XHC_RH2DES__PIS0_L 7U
+#define XHC_RH2DES__PIS0_R 6U
+#define XHC_RH2DES__PIS0_WIDTH 2U
+#define XHC_RH2DES__PIS0_RESETVALUE 0x0U
+#define XHC_RH2DES__reserved_L 5U
+#define XHC_RH2DES__reserved_R 1U
+#define XHC_RH2DES__reserved_WIDTH 5U
+#define XHC_RH2DES__reserved_RESETVALUE 0x0U
+#define XHC_RH2DES__HIST0 0U
+#define XHC_RH2DES__HIST0_L 0U
+#define XHC_RH2DES__HIST0_R 0U
+#define XHC_RH2DES__HIST0_WIDTH 1U
+#define XHC_RH2DES__HIST0_RESETVALUE 0x0U
+#define XHC_RH2DES__RESERVED_0_L 29U
+#define XHC_RH2DES__RESERVED_0_R 25U
+#define XHC_RH2DES__RESERVED_1_L 21U
+#define XHC_RH2DES__RESERVED_1_R 17U
+#define XHC_RH2DES__RESERVED_2_L 13U
+#define XHC_RH2DES__RESERVED_2_R 9U
+#define XHC_RH2DES__RESERVED_L 29U
+#define XHC_RH2DES__RESERVED_R 25U
+#define XHC_RH2DES_WIDTH 32U
+#define XHC_RH2DES__WIDTH 32U
+#define XHC_RH2DES_ALL_L 31U
+#define XHC_RH2DES_ALL_R 0U
+#define XHC_RH2DES__ALL_L 31U
+#define XHC_RH2DES__ALL_R 0U
+#define XHC_RH2DES_DATAMASK 0xc1c1c1ffU
+#define XHC_RH2DES_RDWRMASK 0x3e3e3e00U
+#define XHC_RH2DES_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSC0_OFFSET 0xd10U
+#define XHC_RH2HSC0_BASE 0xd10U
+#define XHC_RH2HSC0__TMR_L 31U
+#define XHC_RH2HSC0__TMR_R 16U
+#define XHC_RH2HSC0__TMR_WIDTH 16U
+#define XHC_RH2HSC0__TMR_RESETVALUE 0x0000U
+#define XHC_RH2HSC0__RSL_L 7U
+#define XHC_RH2HSC0__RSL_R 6U
+#define XHC_RH2HSC0__RSL_WIDTH 2U
+#define XHC_RH2HSC0__RSL_RESETVALUE 0x0U
+#define XHC_RH2HSC0__AS_M_L 5U
+#define XHC_RH2HSC0__AS_M_R 4U
+#define XHC_RH2HSC0__AS_M_WIDTH 2U
+#define XHC_RH2HSC0__AS_M_RESETVALUE 0x0U
+#define XHC_RH2HSC0__CMD_L 3U
+#define XHC_RH2HSC0__CMD_R 2U
+#define XHC_RH2HSC0__CMD_WIDTH 2U
+#define XHC_RH2HSC0__CMD_RESETVALUE 0x0U
+#define XHC_RH2HSC0__reserved 1U
+#define XHC_RH2HSC0__reserved_L 1U
+#define XHC_RH2HSC0__reserved_R 1U
+#define XHC_RH2HSC0__reserved_WIDTH 1U
+#define XHC_RH2HSC0__reserved_RESETVALUE 0x0U
+#define XHC_RH2HSC0__STB 0U
+#define XHC_RH2HSC0__STB_L 0U
+#define XHC_RH2HSC0__STB_R 0U
+#define XHC_RH2HSC0__STB_WIDTH 1U
+#define XHC_RH2HSC0__STB_RESETVALUE 0x0U
+#define XHC_RH2HSC0__RESERVED_L 15U
+#define XHC_RH2HSC0__RESERVED_R 8U
+#define XHC_RH2HSC0_WIDTH 32U
+#define XHC_RH2HSC0__WIDTH 32U
+#define XHC_RH2HSC0_ALL_L 31U
+#define XHC_RH2HSC0_ALL_R 0U
+#define XHC_RH2HSC0__ALL_L 31U
+#define XHC_RH2HSC0__ALL_R 0U
+#define XHC_RH2HSC0_DATAMASK 0xffff00ffU
+#define XHC_RH2HSC0_RDWRMASK 0x0000ff00U
+#define XHC_RH2HSC0_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSR0_OFFSET 0xd14U
+#define XHC_RH2HSR0_BASE 0xd14U
+#define XHC_RH2HSR0__C2U_L 31U
+#define XHC_RH2HSR0__C2U_R 24U
+#define XHC_RH2HSR0__C2U_WIDTH 8U
+#define XHC_RH2HSR0__C2U_RESETVALUE 0x00U
+#define XHC_RH2HSR0__C1U_L 23U
+#define XHC_RH2HSR0__C1U_R 16U
+#define XHC_RH2HSR0__C1U_WIDTH 8U
+#define XHC_RH2HSR0__C1U_RESETVALUE 0x00U
+#define XHC_RH2HSR0__reserved_L 15U
+#define XHC_RH2HSR0__reserved_R 8U
+#define XHC_RH2HSR0__reserved_WIDTH 8U
+#define XHC_RH2HSR0__reserved_RESETVALUE 0x00U
+#define XHC_RH2HSR0__RTY_L 7U
+#define XHC_RH2HSR0__RTY_R 0U
+#define XHC_RH2HSR0__RTY_WIDTH 8U
+#define XHC_RH2HSR0__RTY_RESETVALUE 0x00U
+#define XHC_RH2HSR0_WIDTH 32U
+#define XHC_RH2HSR0__WIDTH 32U
+#define XHC_RH2HSR0_ALL_L 31U
+#define XHC_RH2HSR0_ALL_R 0U
+#define XHC_RH2HSR0__ALL_L 31U
+#define XHC_RH2HSR0__ALL_R 0U
+#define XHC_RH2HSR0_DATAMASK 0xffffffffU
+#define XHC_RH2HSR0_RDWRMASK 0x00000000U
+#define XHC_RH2HSR0_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSC1_OFFSET 0xd18U
+#define XHC_RH2HSC1_BASE 0xd18U
+#define XHC_RH2HSC1__TMR_L 31U
+#define XHC_RH2HSC1__TMR_R 16U
+#define XHC_RH2HSC1__TMR_WIDTH 16U
+#define XHC_RH2HSC1__TMR_RESETVALUE 0x0000U
+#define XHC_RH2HSC1__RSL_L 7U
+#define XHC_RH2HSC1__RSL_R 6U
+#define XHC_RH2HSC1__RSL_WIDTH 2U
+#define XHC_RH2HSC1__RSL_RESETVALUE 0x0U
+#define XHC_RH2HSC1__AS_M_L 5U
+#define XHC_RH2HSC1__AS_M_R 4U
+#define XHC_RH2HSC1__AS_M_WIDTH 2U
+#define XHC_RH2HSC1__AS_M_RESETVALUE 0x0U
+#define XHC_RH2HSC1__CMD_L 3U
+#define XHC_RH2HSC1__CMD_R 2U
+#define XHC_RH2HSC1__CMD_WIDTH 2U
+#define XHC_RH2HSC1__CMD_RESETVALUE 0x0U
+#define XHC_RH2HSC1__reserved 1U
+#define XHC_RH2HSC1__reserved_L 1U
+#define XHC_RH2HSC1__reserved_R 1U
+#define XHC_RH2HSC1__reserved_WIDTH 1U
+#define XHC_RH2HSC1__reserved_RESETVALUE 0x0U
+#define XHC_RH2HSC1__STB 0U
+#define XHC_RH2HSC1__STB_L 0U
+#define XHC_RH2HSC1__STB_R 0U
+#define XHC_RH2HSC1__STB_WIDTH 1U
+#define XHC_RH2HSC1__STB_RESETVALUE 0x0U
+#define XHC_RH2HSC1__RESERVED_L 15U
+#define XHC_RH2HSC1__RESERVED_R 8U
+#define XHC_RH2HSC1_WIDTH 32U
+#define XHC_RH2HSC1__WIDTH 32U
+#define XHC_RH2HSC1_ALL_L 31U
+#define XHC_RH2HSC1_ALL_R 0U
+#define XHC_RH2HSC1__ALL_L 31U
+#define XHC_RH2HSC1__ALL_R 0U
+#define XHC_RH2HSC1_DATAMASK 0xffff00ffU
+#define XHC_RH2HSC1_RDWRMASK 0x0000ff00U
+#define XHC_RH2HSC1_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSR1_OFFSET 0xd1cU
+#define XHC_RH2HSR1_BASE 0xd1cU
+#define XHC_RH2HSR1__C2U_L 31U
+#define XHC_RH2HSR1__C2U_R 24U
+#define XHC_RH2HSR1__C2U_WIDTH 8U
+#define XHC_RH2HSR1__C2U_RESETVALUE 0x00U
+#define XHC_RH2HSR1__C1U_L 23U
+#define XHC_RH2HSR1__C1U_R 16U
+#define XHC_RH2HSR1__C1U_WIDTH 8U
+#define XHC_RH2HSR1__C1U_RESETVALUE 0x00U
+#define XHC_RH2HSR1__reserved_L 15U
+#define XHC_RH2HSR1__reserved_R 8U
+#define XHC_RH2HSR1__reserved_WIDTH 8U
+#define XHC_RH2HSR1__reserved_RESETVALUE 0x00U
+#define XHC_RH2HSR1__RTY_L 7U
+#define XHC_RH2HSR1__RTY_R 0U
+#define XHC_RH2HSR1__RTY_WIDTH 8U
+#define XHC_RH2HSR1__RTY_RESETVALUE 0x00U
+#define XHC_RH2HSR1_WIDTH 32U
+#define XHC_RH2HSR1__WIDTH 32U
+#define XHC_RH2HSR1_ALL_L 31U
+#define XHC_RH2HSR1_ALL_R 0U
+#define XHC_RH2HSR1__ALL_L 31U
+#define XHC_RH2HSR1__ALL_R 0U
+#define XHC_RH2HSR1_DATAMASK 0xffffffffU
+#define XHC_RH2HSR1_RDWRMASK 0x00000000U
+#define XHC_RH2HSR1_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSC2_OFFSET 0xd20U
+#define XHC_RH2HSC2_BASE 0xd20U
+#define XHC_RH2HSC2__TMR_L 31U
+#define XHC_RH2HSC2__TMR_R 16U
+#define XHC_RH2HSC2__TMR_WIDTH 16U
+#define XHC_RH2HSC2__TMR_RESETVALUE 0x0000U
+#define XHC_RH2HSC2__RSL_L 7U
+#define XHC_RH2HSC2__RSL_R 6U
+#define XHC_RH2HSC2__RSL_WIDTH 2U
+#define XHC_RH2HSC2__RSL_RESETVALUE 0x0U
+#define XHC_RH2HSC2__AS_M_L 5U
+#define XHC_RH2HSC2__AS_M_R 4U
+#define XHC_RH2HSC2__AS_M_WIDTH 2U
+#define XHC_RH2HSC2__AS_M_RESETVALUE 0x0U
+#define XHC_RH2HSC2__CMD_L 3U
+#define XHC_RH2HSC2__CMD_R 2U
+#define XHC_RH2HSC2__CMD_WIDTH 2U
+#define XHC_RH2HSC2__CMD_RESETVALUE 0x0U
+#define XHC_RH2HSC2__reserved 1U
+#define XHC_RH2HSC2__reserved_L 1U
+#define XHC_RH2HSC2__reserved_R 1U
+#define XHC_RH2HSC2__reserved_WIDTH 1U
+#define XHC_RH2HSC2__reserved_RESETVALUE 0x0U
+#define XHC_RH2HSC2__STB 0U
+#define XHC_RH2HSC2__STB_L 0U
+#define XHC_RH2HSC2__STB_R 0U
+#define XHC_RH2HSC2__STB_WIDTH 1U
+#define XHC_RH2HSC2__STB_RESETVALUE 0x0U
+#define XHC_RH2HSC2__RESERVED_L 15U
+#define XHC_RH2HSC2__RESERVED_R 8U
+#define XHC_RH2HSC2_WIDTH 32U
+#define XHC_RH2HSC2__WIDTH 32U
+#define XHC_RH2HSC2_ALL_L 31U
+#define XHC_RH2HSC2_ALL_R 0U
+#define XHC_RH2HSC2__ALL_L 31U
+#define XHC_RH2HSC2__ALL_R 0U
+#define XHC_RH2HSC2_DATAMASK 0xffff00ffU
+#define XHC_RH2HSC2_RDWRMASK 0x0000ff00U
+#define XHC_RH2HSC2_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSR2_OFFSET 0xd24U
+#define XHC_RH2HSR2_BASE 0xd24U
+#define XHC_RH2HSR2__C2U_L 31U
+#define XHC_RH2HSR2__C2U_R 24U
+#define XHC_RH2HSR2__C2U_WIDTH 8U
+#define XHC_RH2HSR2__C2U_RESETVALUE 0x00U
+#define XHC_RH2HSR2__C1U_L 23U
+#define XHC_RH2HSR2__C1U_R 16U
+#define XHC_RH2HSR2__C1U_WIDTH 8U
+#define XHC_RH2HSR2__C1U_RESETVALUE 0x00U
+#define XHC_RH2HSR2__reserved_L 15U
+#define XHC_RH2HSR2__reserved_R 8U
+#define XHC_RH2HSR2__reserved_WIDTH 8U
+#define XHC_RH2HSR2__reserved_RESETVALUE 0x00U
+#define XHC_RH2HSR2__RTY_L 7U
+#define XHC_RH2HSR2__RTY_R 0U
+#define XHC_RH2HSR2__RTY_WIDTH 8U
+#define XHC_RH2HSR2__RTY_RESETVALUE 0x00U
+#define XHC_RH2HSR2_WIDTH 32U
+#define XHC_RH2HSR2__WIDTH 32U
+#define XHC_RH2HSR2_ALL_L 31U
+#define XHC_RH2HSR2_ALL_R 0U
+#define XHC_RH2HSR2__ALL_L 31U
+#define XHC_RH2HSR2__ALL_R 0U
+#define XHC_RH2HSR2_DATAMASK 0xffffffffU
+#define XHC_RH2HSR2_RDWRMASK 0x00000000U
+#define XHC_RH2HSR2_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSC3_OFFSET 0xd28U
+#define XHC_RH2HSC3_BASE 0xd28U
+#define XHC_RH2HSC3__TMR_L 31U
+#define XHC_RH2HSC3__TMR_R 16U
+#define XHC_RH2HSC3__TMR_WIDTH 16U
+#define XHC_RH2HSC3__TMR_RESETVALUE 0x0000U
+#define XHC_RH2HSC3__RSL_L 7U
+#define XHC_RH2HSC3__RSL_R 6U
+#define XHC_RH2HSC3__RSL_WIDTH 2U
+#define XHC_RH2HSC3__RSL_RESETVALUE 0x0U
+#define XHC_RH2HSC3__AS_M_L 5U
+#define XHC_RH2HSC3__AS_M_R 4U
+#define XHC_RH2HSC3__AS_M_WIDTH 2U
+#define XHC_RH2HSC3__AS_M_RESETVALUE 0x0U
+#define XHC_RH2HSC3__CMD_L 3U
+#define XHC_RH2HSC3__CMD_R 2U
+#define XHC_RH2HSC3__CMD_WIDTH 2U
+#define XHC_RH2HSC3__CMD_RESETVALUE 0x0U
+#define XHC_RH2HSC3__reserved 1U
+#define XHC_RH2HSC3__reserved_L 1U
+#define XHC_RH2HSC3__reserved_R 1U
+#define XHC_RH2HSC3__reserved_WIDTH 1U
+#define XHC_RH2HSC3__reserved_RESETVALUE 0x0U
+#define XHC_RH2HSC3__STB 0U
+#define XHC_RH2HSC3__STB_L 0U
+#define XHC_RH2HSC3__STB_R 0U
+#define XHC_RH2HSC3__STB_WIDTH 1U
+#define XHC_RH2HSC3__STB_RESETVALUE 0x0U
+#define XHC_RH2HSC3__RESERVED_L 15U
+#define XHC_RH2HSC3__RESERVED_R 8U
+#define XHC_RH2HSC3_WIDTH 32U
+#define XHC_RH2HSC3__WIDTH 32U
+#define XHC_RH2HSC3_ALL_L 31U
+#define XHC_RH2HSC3_ALL_R 0U
+#define XHC_RH2HSC3__ALL_L 31U
+#define XHC_RH2HSC3__ALL_R 0U
+#define XHC_RH2HSC3_DATAMASK 0xffff00ffU
+#define XHC_RH2HSC3_RDWRMASK 0x0000ff00U
+#define XHC_RH2HSC3_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSR3_OFFSET 0xd2cU
+#define XHC_RH2HSR3_BASE 0xd2cU
+#define XHC_RH2HSR3__C2U_L 31U
+#define XHC_RH2HSR3__C2U_R 24U
+#define XHC_RH2HSR3__C2U_WIDTH 8U
+#define XHC_RH2HSR3__C2U_RESETVALUE 0x00U
+#define XHC_RH2HSR3__C1U_L 23U
+#define XHC_RH2HSR3__C1U_R 16U
+#define XHC_RH2HSR3__C1U_WIDTH 8U
+#define XHC_RH2HSR3__C1U_RESETVALUE 0x00U
+#define XHC_RH2HSR3__reserved_L 15U
+#define XHC_RH2HSR3__reserved_R 8U
+#define XHC_RH2HSR3__reserved_WIDTH 8U
+#define XHC_RH2HSR3__reserved_RESETVALUE 0x00U
+#define XHC_RH2HSR3__RTY_L 7U
+#define XHC_RH2HSR3__RTY_R 0U
+#define XHC_RH2HSR3__RTY_WIDTH 8U
+#define XHC_RH2HSR3__RTY_RESETVALUE 0x00U
+#define XHC_RH2HSR3_WIDTH 32U
+#define XHC_RH2HSR3__WIDTH 32U
+#define XHC_RH2HSR3_ALL_L 31U
+#define XHC_RH2HSR3_ALL_R 0U
+#define XHC_RH2HSR3__ALL_L 31U
+#define XHC_RH2HSR3__ALL_R 0U
+#define XHC_RH2HSR3_DATAMASK 0xffffffffU
+#define XHC_RH2HSR3_RDWRMASK 0x00000000U
+#define XHC_RH2HSR3_RESETVALUE 0x00000000U
+
+#define XHC_ECHU2P_OFFSET 0xd30U
+#define XHC_ECHU2P_BASE 0xd30U
+#define XHC_ECHU2P__reserved_L 31U
+#define XHC_ECHU2P__reserved_R 16U
+#define XHC_ECHU2P__reserved_WIDTH 16U
+#define XHC_ECHU2P__reserved_RESETVALUE 0x0000U
+#define XHC_ECHU2P__NCP_L 15U
+#define XHC_ECHU2P__NCP_R 8U
+#define XHC_ECHU2P__NCP_WIDTH 8U
+#define XHC_ECHU2P__NCP_RESETVALUE 0x04U
+#define XHC_ECHU2P__CID_L 7U
+#define XHC_ECHU2P__CID_R 0U
+#define XHC_ECHU2P__CID_WIDTH 8U
+#define XHC_ECHU2P__CID_RESETVALUE 0xcaU
+#define XHC_ECHU2P_WIDTH 32U
+#define XHC_ECHU2P__WIDTH 32U
+#define XHC_ECHU2P_ALL_L 31U
+#define XHC_ECHU2P_ALL_R 0U
+#define XHC_ECHU2P__ALL_L 31U
+#define XHC_ECHU2P__ALL_R 0U
+#define XHC_ECHU2P_DATAMASK 0xffffffffU
+#define XHC_ECHU2P_RDWRMASK 0x00000000U
+#define XHC_ECHU2P_RESETVALUE 0x000004caU
+
+#define XHC_U2PVER_OFFSET 0xd34U
+#define XHC_U2PVER_BASE 0xd34U
+#define XHC_U2PVER__MAJ_L 31U
+#define XHC_U2PVER__MAJ_R 28U
+#define XHC_U2PVER__MAJ_WIDTH 4U
+#define XHC_U2PVER__MAJ_RESETVALUE 0x0U
+#define XHC_U2PVER__MIN_L 27U
+#define XHC_U2PVER__MIN_R 24U
+#define XHC_U2PVER__MIN_WIDTH 4U
+#define XHC_U2PVER__MIN_RESETVALUE 0x0U
+#define XHC_U2PVER__RLS_L 23U
+#define XHC_U2PVER__RLS_R 20U
+#define XHC_U2PVER__RLS_WIDTH 4U
+#define XHC_U2PVER__RLS_RESETVALUE 0x0U
+#define XHC_U2PVER__reserved_L 19U
+#define XHC_U2PVER__reserved_R 0U
+#define XHC_U2PVER__reserved_WIDTH 20U
+#define XHC_U2PVER__reserved_RESETVALUE 0x00000U
+#define XHC_U2PVER_WIDTH 32U
+#define XHC_U2PVER__WIDTH 32U
+#define XHC_U2PVER_ALL_L 31U
+#define XHC_U2PVER_ALL_R 0U
+#define XHC_U2PVER__ALL_L 31U
+#define XHC_U2PVER__ALL_R 0U
+#define XHC_U2PVER_DATAMASK 0xffffffffU
+#define XHC_U2PVER_RDWRMASK 0x00000000U
+#define XHC_U2PVER_RESETVALUE 0x00000000U
+
+#define XHC_U2PMGN_OFFSET 0xd38U
+#define XHC_U2PMGN_BASE 0xd38U
+#define XHC_U2PMGN__MGN_L 31U
+#define XHC_U2PMGN__MGN_R 0U
+#define XHC_U2PMGN__MGN_WIDTH 32U
+#define XHC_U2PMGN__MGN_RESETVALUE 0x4b534b4dU
+#define XHC_U2PMGN_WIDTH 32U
+#define XHC_U2PMGN__WIDTH 32U
+#define XHC_U2PMGN_ALL_L 31U
+#define XHC_U2PMGN_ALL_R 0U
+#define XHC_U2PMGN__ALL_L 31U
+#define XHC_U2PMGN__ALL_R 0U
+#define XHC_U2PMGN_DATAMASK 0xffffffffU
+#define XHC_U2PMGN_RDWRMASK 0x00000000U
+#define XHC_U2PMGN_RESETVALUE 0x4b534b4dU
+
+#define XHC_ECHRSV2_OFFSET 0xd40U
+#define XHC_ECHRSV2_BASE 0xd40U
+#define XHC_ECHRSV2__reserved_L 31U
+#define XHC_ECHRSV2__reserved_R 16U
+#define XHC_ECHRSV2__reserved_WIDTH 16U
+#define XHC_ECHRSV2__reserved_RESETVALUE 0x0000U
+#define XHC_ECHRSV2__NCP_L 15U
+#define XHC_ECHRSV2__NCP_R 8U
+#define XHC_ECHRSV2__NCP_WIDTH 8U
+#define XHC_ECHRSV2__NCP_RESETVALUE 0x00U
+#define XHC_ECHRSV2__CID_L 7U
+#define XHC_ECHRSV2__CID_R 0U
+#define XHC_ECHRSV2__CID_WIDTH 8U
+#define XHC_ECHRSV2__CID_RESETVALUE 0xffU
+#define XHC_ECHRSV2_WIDTH 32U
+#define XHC_ECHRSV2__WIDTH 32U
+#define XHC_ECHRSV2_ALL_L 31U
+#define XHC_ECHRSV2_ALL_R 0U
+#define XHC_ECHRSV2__ALL_L 31U
+#define XHC_ECHRSV2__ALL_R 0U
+#define XHC_ECHRSV2_DATAMASK 0xffffffffU
+#define XHC_ECHRSV2_RDWRMASK 0x00000000U
+#define XHC_ECHRSV2_RESETVALUE 0x000000ffU
+
+#define XHC_ECHIRA_OFFSET 0xf90U
+#define XHC_ECHIRA_BASE 0xf90U
+#define XHC_ECHIRA__reserved_L 31U
+#define XHC_ECHIRA__reserved_R 16U
+#define XHC_ECHIRA__reserved_WIDTH 16U
+#define XHC_ECHIRA__reserved_RESETVALUE 0x0000U
+#define XHC_ECHIRA__NCP_L 15U
+#define XHC_ECHIRA__NCP_R 8U
+#define XHC_ECHIRA__NCP_WIDTH 8U
+#define XHC_ECHIRA__NCP_RESETVALUE 0x04U
+#define XHC_ECHIRA__CID_L 7U
+#define XHC_ECHIRA__CID_R 0U
+#define XHC_ECHIRA__CID_WIDTH 8U
+#define XHC_ECHIRA__CID_RESETVALUE 0xfdU
+#define XHC_ECHIRA_WIDTH 32U
+#define XHC_ECHIRA__WIDTH 32U
+#define XHC_ECHIRA_ALL_L 31U
+#define XHC_ECHIRA_ALL_R 0U
+#define XHC_ECHIRA__ALL_L 31U
+#define XHC_ECHIRA__ALL_R 0U
+#define XHC_ECHIRA_DATAMASK 0xffffffffU
+#define XHC_ECHIRA_RDWRMASK 0x00000000U
+#define XHC_ECHIRA_RESETVALUE 0x000004fdU
+
+#define XHC_IRAADR_OFFSET 0xf98U
+#define XHC_IRAADR_BASE 0xf98U
+#define XHC_IRAADR__ADR_L 23U
+#define XHC_IRAADR__ADR_R 2U
+#define XHC_IRAADR__ADR_WIDTH 22U
+#define XHC_IRAADR__ADR_RESETVALUE 0x0U
+#define XHC_IRAADR__reserved 1U
+#define XHC_IRAADR__reserved_L 1U
+#define XHC_IRAADR__reserved_R 1U
+#define XHC_IRAADR__reserved_WIDTH 1U
+#define XHC_IRAADR__reserved_RESETVALUE 0x0U
+#define XHC_IRAADR__MOD 0U
+#define XHC_IRAADR__MOD_L 0U
+#define XHC_IRAADR__MOD_R 0U
+#define XHC_IRAADR__MOD_WIDTH 1U
+#define XHC_IRAADR__MOD_RESETVALUE 0x0U
+#define XHC_IRAADR__RESERVED_L 31U
+#define XHC_IRAADR__RESERVED_R 24U
+#define XHC_IRAADR_WIDTH 24U
+#define XHC_IRAADR__WIDTH 24U
+#define XHC_IRAADR_ALL_L 23U
+#define XHC_IRAADR_ALL_R 0U
+#define XHC_IRAADR__ALL_L 23U
+#define XHC_IRAADR__ALL_R 0U
+#define XHC_IRAADR_DATAMASK 0x00ffffffU
+#define XHC_IRAADR_RDWRMASK 0xff000000U
+#define XHC_IRAADR_RESETVALUE 0x000000U
+
+#define XHC_IRADAT_OFFSET 0xf9cU
+#define XHC_IRADAT_BASE 0xf9cU
+#define XHC_IRADAT__DAT_L 31U
+#define XHC_IRADAT__DAT_R 0U
+#define XHC_IRADAT__DAT_WIDTH 32U
+#define XHC_IRADAT__DAT_RESETVALUE 0x00000000U
+#define XHC_IRADAT_WIDTH 32U
+#define XHC_IRADAT__WIDTH 32U
+#define XHC_IRADAT_ALL_L 31U
+#define XHC_IRADAT_ALL_R 0U
+#define XHC_IRADAT__ALL_L 31U
+#define XHC_IRADAT__ALL_R 0U
+#define XHC_IRADAT_DATAMASK 0xffffffffU
+#define XHC_IRADAT_RDWRMASK 0x00000000U
+#define XHC_IRADAT_RESETVALUE 0x00000000U
+
+
+#define XHC_ECHHST_OFFSET 0xfa0U
+#define XHC_ECHHST_BASE 0xfa0U
+#define XHC_ECHHST__CCC 31U
+#define XHC_ECHHST__CCC_L 31U
+#define XHC_ECHHST__CCC_R 31U
+#define XHC_ECHHST__CCC_WIDTH 1U
+#define XHC_ECHHST__CCC_RESETVALUE 0x1U
+#define XHC_ECHHST__PME 30U
+#define XHC_ECHHST__PME_L 30U
+#define XHC_ECHHST__PME_R 30U
+#define XHC_ECHHST__PME_WIDTH 1U
+#define XHC_ECHHST__PME_RESETVALUE 0x0U
+#define XHC_ECHHST__AUX_L 29U
+#define XHC_ECHHST__AUX_R 24U
+#define XHC_ECHHST__AUX_WIDTH 6U
+#define XHC_ECHHST__AUX_RESETVALUE 0x0U
+#define XHC_ECHHST__IRA 20U
+#define XHC_ECHHST__IRA_L 20U
+#define XHC_ECHHST__IRA_R 20U
+#define XHC_ECHHST__IRA_WIDTH 1U
+#define XHC_ECHHST__IRA_RESETVALUE 0x0U
+#define XHC_ECHHST__ULS 19U
+#define XHC_ECHHST__ULS_L 19U
+#define XHC_ECHHST__ULS_R 19U
+#define XHC_ECHHST__ULS_WIDTH 1U
+#define XHC_ECHHST__ULS_RESETVALUE 0x0U
+#define XHC_ECHHST__reserved 18U
+#define XHC_ECHHST__reserved_L 18U
+#define XHC_ECHHST__reserved_R 18U
+#define XHC_ECHHST__reserved_WIDTH 1U
+#define XHC_ECHHST__reserved_RESETVALUE 0x0U
+#define XHC_ECHHST__TEDA 17U
+#define XHC_ECHHST__TEDA_L 17U
+#define XHC_ECHHST__TEDA_R 17U
+#define XHC_ECHHST__TEDA_WIDTH 1U
+#define XHC_ECHHST__TEDA_RESETVALUE 0x0U
+#define XHC_ECHHST__FSW 16U
+#define XHC_ECHHST__FSW_L 16U
+#define XHC_ECHHST__FSW_R 16U
+#define XHC_ECHHST__FSW_WIDTH 1U
+#define XHC_ECHHST__FSW_RESETVALUE 0x1U
+#define XHC_ECHHST__NCP_L 15U
+#define XHC_ECHHST__NCP_R 8U
+#define XHC_ECHHST__NCP_WIDTH 8U
+#define XHC_ECHHST__NCP_RESETVALUE 0x04U
+#define XHC_ECHHST__CID_L 7U
+#define XHC_ECHHST__CID_R 0U
+#define XHC_ECHHST__CID_WIDTH 8U
+#define XHC_ECHHST__CID_RESETVALUE 0xfcU
+#define XHC_ECHHST__RESERVED_L 23U
+#define XHC_ECHHST__RESERVED_R 21U
+#define XHC_ECHHST_WIDTH 32U
+#define XHC_ECHHST__WIDTH 32U
+#define XHC_ECHHST_ALL_L 31U
+#define XHC_ECHHST_ALL_R 0U
+#define XHC_ECHHST__ALL_L 31U
+#define XHC_ECHHST__ALL_R 0U
+#define XHC_ECHHST_DATAMASK 0xff1fffffU
+#define XHC_ECHHST_RDWRMASK 0x00e00000U
+#define XHC_ECHHST_RESETVALUE 0x800104fcU
+
+#define XHC_HSTDBG_OFFSET 0xfa4U
+#define XHC_HSTDBG_BASE 0xfa4U
+#define XHC_HSTDBG__ETE 31U
+#define XHC_HSTDBG__ETE_L 31U
+#define XHC_HSTDBG__ETE_R 31U
+#define XHC_HSTDBG__ETE_WIDTH 1U
+#define XHC_HSTDBG__ETE_RESETVALUE 0x0U
+#define XHC_HSTDBG__reserved_L 30U
+#define XHC_HSTDBG__reserved_R 16U
+#define XHC_HSTDBG__reserved_WIDTH 15U
+#define XHC_HSTDBG__reserved_RESETVALUE 0x0U
+#define XHC_HSTDBG__OUTP_L 15U
+#define XHC_HSTDBG__OUTP_R 8U
+#define XHC_HSTDBG__OUTP_WIDTH 8U
+#define XHC_HSTDBG__OUTP_RESETVALUE 0x00U
+#define XHC_HSTDBG__INP_L 7U
+#define XHC_HSTDBG__INP_R 0U
+#define XHC_HSTDBG__INP_WIDTH 8U
+#define XHC_HSTDBG__INP_RESETVALUE 0x00U
+#define XHC_HSTDBG_WIDTH 32U
+#define XHC_HSTDBG__WIDTH 32U
+#define XHC_HSTDBG_ALL_L 31U
+#define XHC_HSTDBG_ALL_R 0U
+#define XHC_HSTDBG__ALL_L 31U
+#define XHC_HSTDBG__ALL_R 0U
+#define XHC_HSTDBG_DATAMASK 0xffffffffU
+#define XHC_HSTDBG_RDWRMASK 0x00000000U
+#define XHC_HSTDBG_RESETVALUE 0x00000000U
+
+#define XHC_HSTNPL_OFFSET 0xfa8U
+#define XHC_HSTNPL_BASE 0xfa8U
+#define XHC_HSTNPL__NPL_L 31U
+#define XHC_HSTNPL__NPL_R 9U
+#define XHC_HSTNPL__NPL_WIDTH 23U
+#define XHC_HSTNPL__NPL_RESETVALUE 0x0U
+#define XHC_HSTNPL__reserved_L 8U
+#define XHC_HSTNPL__reserved_R 0U
+#define XHC_HSTNPL__reserved_WIDTH 9U
+#define XHC_HSTNPL__reserved_RESETVALUE 0x0U
+#define XHC_HSTNPL_WIDTH 32U
+#define XHC_HSTNPL__WIDTH 32U
+#define XHC_HSTNPL_ALL_L 31U
+#define XHC_HSTNPL_ALL_R 0U
+#define XHC_HSTNPL__ALL_L 31U
+#define XHC_HSTNPL__ALL_R 0U
+#define XHC_HSTNPL_DATAMASK 0xffffffffU
+#define XHC_HSTNPL_RDWRMASK 0x00000000U
+#define XHC_HSTNPL_RESETVALUE 0x00000000U
+
+#define XHC_HSTNPH_OFFSET 0xfacU
+#define XHC_HSTNPH_BASE 0xfacU
+#define XHC_HSTNPH__NPH_L 31U
+#define XHC_HSTNPH__NPH_R 0U
+#define XHC_HSTNPH__NPH_WIDTH 32U
+#define XHC_HSTNPH__NPH_RESETVALUE 0x00000000U
+#define XHC_HSTNPH_WIDTH 32U
+#define XHC_HSTNPH__WIDTH 32U
+#define XHC_HSTNPH_ALL_L 31U
+#define XHC_HSTNPH_ALL_R 0U
+#define XHC_HSTNPH__ALL_L 31U
+#define XHC_HSTNPH__ALL_R 0U
+#define XHC_HSTNPH_DATAMASK 0xffffffffU
+#define XHC_HSTNPH_RDWRMASK 0x00000000U
+#define XHC_HSTNPH_RESETVALUE 0x00000000U
+
+#define XHC_ECHRBV_OFFSET 0xfb0U
+#define XHC_ECHRBV_BASE 0xfb0U
+#define XHC_ECHRBV__MAJ_L 31U
+#define XHC_ECHRBV__MAJ_R 28U
+#define XHC_ECHRBV__MAJ_WIDTH 4U
+#define XHC_ECHRBV__MAJ_RESETVALUE 0x0U
+#define XHC_ECHRBV__MIN_L 27U
+#define XHC_ECHRBV__MIN_R 24U
+#define XHC_ECHRBV__MIN_WIDTH 4U
+#define XHC_ECHRBV__MIN_RESETVALUE 0x0U
+#define XHC_ECHRBV__RLS_L 23U
+#define XHC_ECHRBV__RLS_R 16U
+#define XHC_ECHRBV__RLS_WIDTH 8U
+#define XHC_ECHRBV__RLS_RESETVALUE 0x00U
+#define XHC_ECHRBV__NCP_L 15U
+#define XHC_ECHRBV__NCP_R 8U
+#define XHC_ECHRBV__NCP_WIDTH 8U
+#define XHC_ECHRBV__NCP_RESETVALUE 0x00U
+#define XHC_ECHRBV__CID_L 7U
+#define XHC_ECHRBV__CID_R 0U
+#define XHC_ECHRBV__CID_WIDTH 8U
+#define XHC_ECHRBV__CID_RESETVALUE 0xfeU
+#define XHC_ECHRBV_WIDTH 32U
+#define XHC_ECHRBV__WIDTH 32U
+#define XHC_ECHRBV_ALL_L 31U
+#define XHC_ECHRBV_ALL_R 0U
+#define XHC_ECHRBV__ALL_L 31U
+#define XHC_ECHRBV__ALL_R 0U
+#define XHC_ECHRBV_DATAMASK 0xffffffffU
+#define XHC_ECHRBV_RDWRMASK 0x00000000U
+#define XHC_ECHRBV_RESETVALUE 0x000000feU
+
+#define XHC_RBVPDT_OFFSET 0xfb4U
+#define XHC_RBVPDT_BASE 0xfb4U
+#define XHC_RBVPDT__VDR_L 31U
+#define XHC_RBVPDT__VDR_R 16U
+#define XHC_RBVPDT__VDR_WIDTH 16U
+#define XHC_RBVPDT__VDR_RESETVALUE 0x0a5cU
+#define XHC_RBVPDT__PDT_L 15U
+#define XHC_RBVPDT__PDT_R 0U
+#define XHC_RBVPDT__PDT_WIDTH 16U
+#define XHC_RBVPDT__PDT_RESETVALUE 0x0000U
+#define XHC_RBVPDT_WIDTH 32U
+#define XHC_RBVPDT__WIDTH 32U
+#define XHC_RBVPDT_ALL_L 31U
+#define XHC_RBVPDT_ALL_R 0U
+#define XHC_RBVPDT__ALL_L 31U
+#define XHC_RBVPDT__ALL_R 0U
+#define XHC_RBVPDT_DATAMASK 0xffffffffU
+#define XHC_RBVPDT_RDWRMASK 0x00000000U
+#define XHC_RBVPDT_RESETVALUE 0x0a5c0000U
+
+#define XHC_RBVMGN_OFFSET 0xfbcU
+#define XHC_RBVMGN_BASE 0xfbcU
+#define XHC_RBVMGN__MGN_L 31U
+#define XHC_RBVMGN__MGN_R 0U
+#define XHC_RBVMGN__MGN_WIDTH 32U
+#define XHC_RBVMGN__MGN_RESETVALUE 0x52535354U
+#define XHC_RBVMGN_WIDTH 32U
+#define XHC_RBVMGN__WIDTH 32U
+#define XHC_RBVMGN_ALL_L 31U
+#define XHC_RBVMGN_ALL_R 0U
+#define XHC_RBVMGN__ALL_L 31U
+#define XHC_RBVMGN__ALL_R 0U
+#define XHC_RBVMGN_DATAMASK 0xffffffffU
+#define XHC_RBVMGN_RDWRMASK 0x00000000U
+#define XHC_RBVMGN_RESETVALUE 0x52535354U
+
+/* PORTSC field defines */
+#define XHC_PORTSC__PS_LINK_STATE_U0 0U
+#define XHC_PORTSC__PS_LINK_STATE_U1 1U
+#define XHC_PORTSC__PS_LINK_STATE_U2 2U
+#define XHC_PORTSC__PS_LINK_STATE_U3 3U
+#define XHC_PORTSC__PS_LINK_STATE_DISABLED 4U
+#define XHC_PORTSC__PS_LINK_STATE_RX_DETECT 5U
+#define XHC_PORTSC__PS_LINK_STATE_INACTIVE 6U
+#define XHC_PORTSC__PS_LINK_STATE_POLLING 7U
+#define XHC_PORTSC__PS_LINK_STATE_RECOVERY 8U
+#define XHC_PORTSC__PS_LINK_STATE_HOT_RESET 9U
+#define XHC_PORTSC__PS_LINK_STATE_COMPLIANCE 10U
+#define XHC_PORTSC__PS_LINK_STATE_TEST 11U
+#define XHC_PORTSC__PS_LINK_STATE_RESUME 15U
+
+#define XHC_PORTSC__PS_SPEED_UNDEFINED 0U
+#define XHC_PORTSC__PS_FS 1U
+#define XHC_PORTSC__PS_LS 2U
+#define XHC_PORTSC__PS_HS 3U
+#define XHC_PORTSC__PS_SS 4U
+
+/* macros and inline functions */
+
+/* write 64bit ptr 'p' to destination 'd' with offset 'v' */
+inline void WRITE64_REG_PTRL(uint32_t r, uint32_t *p)
+{
+ uint32_t *ptr = (uint32_t *) (uint64_t) (XHC_BASE + r);
+
+ *ptr = (uint32_t) ((uint64_t) p & (uint64_t) 0xffffffffU);
+}
+
+inline void WRITE64_REG_PTRH(uint32_t r, uint32_t *p)
+{
+ uint32_t *ptr = (uint32_t *) (uint64_t) (XHC_BASE + r);
+
+ *ptr = (uint32_t) ((uint64_t) p >> 32U);
+}
+
+#define XHC_REG_RD(addr) mmio_read_32(XHC_BASE + addr)
+
+#define XHC_REG_WR(addr, val) mmio_write_32(XHC_BASE+addr, val)
+
+#endif /* USBH_XHCI_REGS_H */
+
diff --git a/include/drivers/cadence/cdns_uart.h b/include/drivers/cadence/cdns_uart.h
new file mode 100644
index 0000000..30ca910
--- /dev/null
+++ b/include/drivers/cadence/cdns_uart.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CDNS_UART_H
+#define CDNS_UART_H
+
+#include <drivers/console.h>
+
+/* This is very minimalistic and will only work in QEMU. */
+
+/* CADENCE Registers */
+#define R_UART_CR 0
+#define R_UART_CR_RXRST (1 << 0) /* RX logic reset */
+#define R_UART_CR_TXRST (1 << 1) /* TX logic reset */
+#define R_UART_CR_RX_EN (1 << 2) /* RX enabled */
+#define R_UART_CR_TX_EN (1 << 4) /* TX enabled */
+
+#define R_UART_SR 0x2C
+#define UART_SR_INTR_REMPTY_BIT 1
+#define UART_SR_INTR_TFUL_BIT 4
+#define UART_SR_INTR_TEMPTY_BIT 3
+
+#define R_UART_TX 0x30
+#define R_UART_RX 0x30
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+/*
+ * Initialize a new Cadence console instance and register it with the console
+ * framework. The |console| pointer must point to storage that will be valid
+ * for the lifetime of the console, such as a global or static local variable.
+ * Its contents will be reinitialized from scratch.
+ */
+int console_cdns_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
+ console_t *console);
+
+#endif /*__ASSEMBLER__*/
+
+#endif /* CDNS_UART_H */
diff --git a/include/drivers/cfi/v2m_flash.h b/include/drivers/cfi/v2m_flash.h
new file mode 100644
index 0000000..6beec50
--- /dev/null
+++ b/include/drivers/cfi/v2m_flash.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef V2M_FLASH_H
+#define V2M_FLASH_H
+
+#include <stdint.h>
+
+/* First bus cycle */
+#define NOR_CMD_READ_ARRAY 0xFF
+#define NOR_CMD_READ_ID_CODE 0x90
+#define NOR_CMD_READ_QUERY 0x98
+#define NOR_CMD_READ_STATUS_REG 0x70
+#define NOR_CMD_CLEAR_STATUS_REG 0x50
+#define NOR_CMD_WRITE_TO_BUFFER 0xE8
+#define NOR_CMD_WORD_PROGRAM 0x40
+#define NOR_CMD_BLOCK_ERASE 0x20
+#define NOR_CMD_LOCK_UNLOCK 0x60
+#define NOR_CMD_BLOCK_ERASE_ACK 0xD0
+
+/* Second bus cycle */
+#define NOR_LOCK_BLOCK 0x01
+#define NOR_UNLOCK_BLOCK 0xD0
+
+/* Status register bits */
+#define NOR_DWS (1 << 7)
+#define NOR_ESS (1 << 6)
+#define NOR_ES (1 << 5)
+#define NOR_PS (1 << 4)
+#define NOR_VPPS (1 << 3)
+#define NOR_PSS (1 << 2)
+#define NOR_BLS (1 << 1)
+#define NOR_BWS (1 << 0)
+
+/* Public API */
+void nor_send_cmd(uintptr_t base_addr, unsigned long cmd);
+int nor_word_program(uintptr_t base_addr, unsigned long data);
+int nor_lock(uintptr_t base_addr);
+int nor_unlock(uintptr_t base_addr);
+int nor_erase(uintptr_t base_addr);
+
+#endif /* V2M_FLASH_H*/
diff --git a/include/drivers/clk.h b/include/drivers/clk.h
new file mode 100644
index 0000000..a18f41f
--- /dev/null
+++ b/include/drivers/clk.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CLK_H
+#define CLK_H
+
+#include <stdbool.h>
+
+struct clk_ops {
+ int (*enable)(unsigned long id);
+ void (*disable)(unsigned long id);
+ unsigned long (*get_rate)(unsigned long id);
+ int (*get_parent)(unsigned long id);
+ bool (*is_enabled)(unsigned long id);
+};
+
+int clk_enable(unsigned long id);
+void clk_disable(unsigned long id);
+unsigned long clk_get_rate(unsigned long id);
+bool clk_is_enabled(unsigned long id);
+int clk_get_parent(unsigned long id);
+
+void clk_register(const struct clk_ops *ops);
+
+#endif /* CLK_H */
diff --git a/include/drivers/console.h b/include/drivers/console.h
new file mode 100644
index 0000000..99bf960
--- /dev/null
+++ b/include/drivers/console.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CONSOLE_H
+#define CONSOLE_H
+
+#include <lib/utils_def.h>
+
+#define CONSOLE_T_NEXT (U(0) * REGSZ)
+#define CONSOLE_T_FLAGS (U(1) * REGSZ)
+#define CONSOLE_T_PUTC (U(2) * REGSZ)
+#define CONSOLE_T_GETC (U(3) * REGSZ)
+#define CONSOLE_T_FLUSH (U(4) * REGSZ)
+#define CONSOLE_T_BASE (U(5) * REGSZ)
+#define CONSOLE_T_DRVDATA (U(6) * REGSZ)
+
+#define CONSOLE_FLAG_BOOT (U(1) << 0)
+#define CONSOLE_FLAG_RUNTIME (U(1) << 1)
+#define CONSOLE_FLAG_CRASH (U(1) << 2)
+/* Bits 3 to 7 reserved for additional scopes in future expansion. */
+#define CONSOLE_FLAG_SCOPE_MASK ((U(1) << 8) - 1)
+/* Bits 8 to 31 for non-scope use. */
+#define CONSOLE_FLAG_TRANSLATE_CRLF (U(1) << 8)
+
+/* Returned by getc callbacks when receive FIFO is empty. */
+#define ERROR_NO_PENDING_CHAR (-1)
+/* Returned by console_xxx() if no registered console implements xxx. */
+#define ERROR_NO_VALID_CONSOLE (-128)
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+typedef struct console {
+ struct console *next;
+ /*
+ * Only the low 32 bits are used. The type is u_register_t to align the
+ * fields of the struct to 64 bits in AArch64 and 32 bits in AArch32
+ */
+ u_register_t flags;
+ int (*const putc)(int character, struct console *console);
+ int (*const getc)(struct console *console);
+ void (*const flush)(struct console *console);
+ uintptr_t base;
+ /* Additional private driver data may follow here. */
+} console_t;
+
+/* offset macro assertions for console_t */
+#include <drivers/console_assertions.h>
+
+/*
+ * Add a console_t instance to the console list. This should only be called by
+ * console drivers after they have initialized all fields in the console
+ * structure. Platforms seeking to register a new console need to call the
+ * respective console__register() function instead.
+ */
+int console_register(console_t *console);
+/* Remove a single console_t instance from the console list. Return a pointer to
+ * the console that was removed if it was found, or NULL if not. */
+console_t *console_unregister(console_t *console);
+/* Returns 1 if this console is already registered, 0 if not */
+int console_is_registered(console_t *console);
+/*
+ * Set scope mask of a console that determines in what states it is active.
+ * By default they are registered with (CONSOLE_FLAG_BOOT|CONSOLE_FLAG_CRASH).
+ */
+void console_set_scope(console_t *console, unsigned int scope);
+
+/* Switch to a new global console state (CONSOLE_FLAG_BOOT/RUNTIME/CRASH). */
+void console_switch_state(unsigned int new_state);
+/* Output a character on all consoles registered for the current state. */
+int console_putc(int c);
+/* Read a character (blocking) from any console registered for current state. */
+int console_getc(void);
+/* Flush all consoles registered for the current state. */
+void console_flush(void);
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* CONSOLE_H */
diff --git a/include/drivers/console_assertions.h b/include/drivers/console_assertions.h
new file mode 100644
index 0000000..00caa31
--- /dev/null
+++ b/include/drivers/console_assertions.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CONSOLE_ASSERTIONS_H
+#define CONSOLE_ASSERTIONS_H
+
+#include <lib/cassert.h>
+
+/*
+ * This file contains some separate assertions about console_t, moved here to
+ * keep them out of the way. Should only be included from <console.h>.
+ */
+CASSERT(CONSOLE_T_NEXT == __builtin_offsetof(console_t, next),
+ assert_console_t_next_offset_mismatch);
+CASSERT(CONSOLE_T_FLAGS == __builtin_offsetof(console_t, flags),
+ assert_console_t_flags_offset_mismatch);
+CASSERT(CONSOLE_T_PUTC == __builtin_offsetof(console_t, putc),
+ assert_console_t_putc_offset_mismatch);
+CASSERT(CONSOLE_T_GETC == __builtin_offsetof(console_t, getc),
+ assert_console_t_getc_offset_mismatch);
+CASSERT(CONSOLE_T_FLUSH == __builtin_offsetof(console_t, flush),
+ assert_console_t_flush_offset_mismatch);
+CASSERT(CONSOLE_T_DRVDATA == sizeof(console_t),
+ assert_console_t_drvdata_offset_mismatch);
+
+#endif /* CONSOLE_ASSERTIONS_H */
diff --git a/include/drivers/coreboot/cbmem_console.h b/include/drivers/coreboot/cbmem_console.h
new file mode 100644
index 0000000..30b39f1
--- /dev/null
+++ b/include/drivers/coreboot/cbmem_console.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CBMEM_CONSOLE_H
+#define CBMEM_CONSOLE_H
+
+#include <drivers/console.h>
+
+#define CONSOLE_T_CBMC_SIZE CONSOLE_T_DRVDATA
+
+#ifndef __ASSEMBLER__
+
+typedef struct {
+ console_t console;
+ uint32_t size;
+} console_cbmc_t;
+
+int console_cbmc_register(uintptr_t base, console_cbmc_t *console);
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* CBMEM_CONSOLE_H */
diff --git a/include/drivers/delay_timer.h b/include/drivers/delay_timer.h
new file mode 100644
index 0000000..20a5543
--- /dev/null
+++ b/include/drivers/delay_timer.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Linaro Limited
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DELAY_TIMER_H
+#define DELAY_TIMER_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <arch_helpers.h>
+
+/********************************************************************
+ * A simple timer driver providing synchronous delay functionality.
+ * The driver must be initialized with a structure that provides a
+ * function pointer to return the timer value and a clock
+ * multiplier/divider. The ratio of the multiplier and the divider is
+ * the clock period in microseconds.
+ ********************************************************************/
+
+typedef struct timer_ops {
+ uint32_t (*get_timer_value)(void);
+ uint32_t clk_mult;
+ uint32_t clk_div;
+} timer_ops_t;
+
+static inline uint64_t timeout_cnt_us2cnt(uint32_t us)
+{
+ return ((uint64_t)us * (uint64_t)read_cntfrq_el0()) / 1000000ULL;
+}
+
+static inline uint64_t timeout_init_us(uint32_t us)
+{
+ uint64_t cnt = timeout_cnt_us2cnt(us);
+
+ cnt += read_cntpct_el0();
+
+ return cnt;
+}
+
+static inline bool timeout_elapsed(uint64_t expire_cnt)
+{
+ return read_cntpct_el0() > expire_cnt;
+}
+
+void mdelay(uint32_t msec);
+void udelay(uint32_t usec);
+void timer_init(const timer_ops_t *ops_ptr);
+
+#endif /* DELAY_TIMER_H */
diff --git a/include/drivers/dw_ufs.h b/include/drivers/dw_ufs.h
new file mode 100644
index 0000000..13e53f1
--- /dev/null
+++ b/include/drivers/dw_ufs.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DW_UFS_H
+#define DW_UFS_H
+
+#include <stdint.h>
+
+/* Bus Throtting */
+#define BUSTHRTL 0xC0
+/* Outstanding OCP Requests */
+#define OOCPR 0xC4
+/* Fatal Error Interrupt Enable */
+#define FEIE 0xC8
+/* C-Port Direct Access Configuration register */
+#define CDACFG 0xD0
+/* C-Port Direct Access Transmit 1 register */
+#define CDATX1 0xD4
+/* C-Port Direct Access Transmit 2 register */
+#define CDATX2 0xD8
+/* C-Port Direct Access Receive 1 register */
+#define CDARX1 0xDC
+/* C-Port Direct Access Receive 2 register */
+#define CDARX2 0xE0
+/* C-Port Direct Access Status register */
+#define CDASTA 0xE4
+/* UPIU Loopback Configuration register */
+#define LBMCFG 0xF0
+/* UPIU Loopback Status */
+#define LBMSTA 0xF4
+/* Debug register */
+#define DBG 0xF8
+/* HClk Divider register */
+#define HCLKDIV 0xFC
+
+#define TX_HIBERN8TIME_CAP_OFFSET 0x000F
+#define TX_FSM_STATE_OFFSET 0x0041
+#define TX_FSM_STATE_LINE_RESET 7
+#define TX_FSM_STATE_LINE_CFG 6
+#define TX_FSM_STATE_HS_BURST 5
+#define TX_FSM_STATE_LS_BURST 4
+#define TX_FSM_STATE_STALL 3
+#define TX_FSM_STATE_SLEEP 2
+#define TX_FSM_STATE_HIBERN8 1
+#define TX_FSM_STATE_DISABLE 0
+
+#define RX_MIN_ACTIVATETIME_CAP_OFFSET 0x008F
+#define RX_HS_G2_SYNC_LENGTH_CAP_OFFSET 0x0094
+#define RX_HS_G3_SYNC_LENGTH_CAP_OFFSET 0x0095
+
+#define PA_AVAIL_TX_DATA_LANES_OFFSET 0x1520
+#define PA_TX_SKIP_OFFSET 0x155C
+#define PA_TX_SKIP_PERIOD_OFFSET 0x155D
+#define PA_LOCAL_TX_LCC_ENABLE_OFFSET 0x155E
+#define PA_ACTIVE_TX_DATA_LANES_OFFSET 0x1560
+#define PA_CONNECTED_TX_DATA_LANES_OFFSET 0x1561
+#define PA_TX_TRAILING_CLOCKS_OFFSET 0x1564
+#define PA_TX_GEAR_OFFSET 0x1568
+#define PA_TX_TERMINATION_OFFSET 0x1569
+#define PA_HS_SERIES_OFFSET 0x156A
+#define PA_PWR_MODE_OFFSET 0x1571
+#define PA_ACTIVE_RX_DATA_LANES_OFFSET 0x1580
+#define PA_CONNECTED_RX_DATA_LANES_OFFSET 0x1581
+#define PA_RX_PWR_STATUS_OFFSET 0x1582
+#define PA_RX_GEAR_OFFSET 0x1583
+#define PA_RX_TERMINATION_OFFSET 0x1584
+#define PA_SCRAMBLING_OFFSET 0x1585
+#define PA_MAX_RX_PWM_GEAR_OFFSET 0x1586
+#define PA_MAX_RX_HS_GEAR_OFFSET 0x1587
+#define PA_PACP_REQ_TIMEOUT_OFFSET 0x1590
+#define PA_PACP_REQ_EOB_TIMEOUT_OFFSET 0x1591
+#define PA_REMOTE_VER_INFO_OFFSET 0x15A0
+#define PA_LOGICAL_LANE_MAP_OFFSET 0x15A1
+#define PA_TACTIVATE_OFFSET 0x15A8
+#define PA_PWR_MODE_USER_DATA0_OFFSET 0x15B0
+#define PA_PWR_MODE_USER_DATA1_OFFSET 0x15B1
+#define PA_PWR_MODE_USER_DATA2_OFFSET 0x15B2
+#define PA_PWR_MODE_USER_DATA3_OFFSET 0x15B3
+#define PA_PWR_MODE_USER_DATA4_OFFSET 0x15B4
+#define PA_PWR_MODE_USER_DATA5_OFFSET 0x15B5
+
+#define DL_TC0_TX_FC_THRESHOLD_OFFSET 0x2040
+#define DL_AFC0_CREDIT_THRESHOLD_OFFSET 0x2044
+#define DL_TC0_OUT_ACK_THRESHOLD_OFFSET 0x2045
+
+#define DME_FC0_PROTECTION_TIMEOUT_OFFSET 0xD041
+#define DME_TC0_REPLAY_TIMEOUT_OFFSET 0xD042
+#define DME_AFC0_REQ_TIMEOUT_OFFSET 0xD043
+#define DME_FC1_PROTECTION_TIMEOUT_OFFSET 0xD044
+#define DME_TC1_REPLAY_TIMEOUT_OFFSET 0xD045
+#define DME_AFC1_REQ_TIMEOUT_OFFSET 0xD046
+
+#define VS_MPHY_CFG_UPDT_OFFSET 0xD085
+#define VS_MK2_EXTN_SUPPORT_OFFSET 0xD0AB
+#define VS_MPHY_DISABLE_OFFSET 0xD0C1
+#define VS_MPHY_DISABLE_MPHYDIS (1 << 0)
+
+typedef struct dw_ufs_params {
+ uintptr_t reg_base;
+ uintptr_t desc_base;
+ size_t desc_size;
+ unsigned long flags;
+} dw_ufs_params_t;
+
+int dw_ufs_init(dw_ufs_params_t *params);
+
+#endif /* DW_UFS_H */
diff --git a/include/drivers/fwu/fwu.h b/include/drivers/fwu/fwu.h
new file mode 100644
index 0000000..9f18e22
--- /dev/null
+++ b/include/drivers/fwu/fwu.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FWU_H
+#define FWU_H
+
+#include <stdbool.h>
+
+void fwu_init(void);
+bool fwu_is_trial_run_state(void);
+const struct fwu_metadata *fwu_get_metadata(void);
+
+#endif /* FWU_H */
diff --git a/include/drivers/fwu/fwu_metadata.h b/include/drivers/fwu/fwu_metadata.h
new file mode 100644
index 0000000..2e88de5
--- /dev/null
+++ b/include/drivers/fwu/fwu_metadata.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * FWU metadata information as per the specification section 4.1:
+ * https://developer.arm.com/documentation/den0118/a/
+ *
+ */
+
+#ifndef FWU_METADATA_H
+#define FWU_METADATA_H
+
+#include <stdint.h>
+#include <tools_share/uuid.h>
+
+/* Properties of image in a bank */
+struct fwu_image_properties {
+
+ /* UUID of the image in this bank */
+ uuid_t img_uuid;
+
+ /* [0]: bit describing the image acceptance status –
+ * 1 means the image is accepted
+ * [31:1]: MBZ
+ */
+ uint32_t accepted;
+
+ /* reserved (MBZ) */
+ uint32_t reserved;
+
+} __packed;
+
+/* Image entry information */
+struct fwu_image_entry {
+
+ /* UUID identifying the image type */
+ uuid_t img_type_uuid;
+
+ /* UUID of the storage volume where the image is located */
+ uuid_t location_uuid;
+
+ /* Properties of images with img_type_uuid in the different FW banks */
+ struct fwu_image_properties img_props[NR_OF_FW_BANKS];
+
+} __packed;
+
+/*
+ * FWU metadata filled by the updater and consumed by TF-A for
+ * various purposes as below:
+ * 1. Get active FW bank.
+ * 2. Rollback to previous working FW bank.
+ * 3. Get properties of all images present in all banks.
+ */
+struct fwu_metadata {
+
+ /* Metadata CRC value */
+ uint32_t crc_32;
+
+ /* Metadata version */
+ uint32_t version;
+
+ /* Bank index with which device boots */
+ uint32_t active_index;
+
+ /* Previous bank index with which device booted successfully */
+ uint32_t previous_active_index;
+
+ /* Image entry information */
+ struct fwu_image_entry img_entry[NR_OF_IMAGES_IN_FW_BANK];
+
+} __packed;
+
+#endif /* FWU_METADATA_H */
diff --git a/include/drivers/generic_delay_timer.h b/include/drivers/generic_delay_timer.h
new file mode 100644
index 0000000..adba10f
--- /dev/null
+++ b/include/drivers/generic_delay_timer.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GENERIC_DELAY_TIMER_H
+#define GENERIC_DELAY_TIMER_H
+
+#include <stdint.h>
+
+void generic_delay_timer_init_args(uint32_t mult, uint32_t div);
+
+void generic_delay_timer_init(void);
+
+#endif /* GENERIC_DELAY_TIMER_H */
diff --git a/include/drivers/gpio.h b/include/drivers/gpio.h
new file mode 100644
index 0000000..9bba993
--- /dev/null
+++ b/include/drivers/gpio.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GPIO_H
+#define GPIO_H
+
+#include <export/drivers/gpio_exp.h>
+
+#define GPIO_DIR_OUT ARM_TF_GPIO_DIR_OUT
+#define GPIO_DIR_IN ARM_TF_GPIO_DIR_IN
+
+#define GPIO_LEVEL_LOW ARM_TF_GPIO_LEVEL_LOW
+#define GPIO_LEVEL_HIGH ARM_TF_GPIO_LEVEL_HIGH
+
+#define GPIO_PULL_NONE ARM_TF_GPIO_PULL_NONE
+#define GPIO_PULL_UP ARM_TF_GPIO_PULL_UP
+#define GPIO_PULL_DOWN ARM_TF_GPIO_PULL_DOWN
+#define GPIO_PULL_REPEATER ARM_TF_GPIO_PULL_REPEATER
+
+typedef struct gpio_ops {
+ int (*get_direction)(int gpio);
+ void (*set_direction)(int gpio, int direction);
+ int (*get_value)(int gpio);
+ void (*set_value)(int gpio, int value);
+ void (*set_pull)(int gpio, int pull);
+ int (*get_pull)(int gpio);
+} gpio_ops_t;
+
+int gpio_get_direction(int gpio);
+void gpio_set_direction(int gpio, int direction);
+int gpio_get_value(int gpio);
+void gpio_set_value(int gpio, int value);
+void gpio_set_pull(int gpio, int pull);
+int gpio_get_pull(int gpio);
+void gpio_init(const gpio_ops_t *ops);
+
+#endif /* GPIO_H */
diff --git a/include/drivers/io/io_block.h b/include/drivers/io/io_block.h
new file mode 100644
index 0000000..c99e8c7
--- /dev/null
+++ b/include/drivers/io/io_block.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IO_BLOCK_H
+#define IO_BLOCK_H
+
+#include <drivers/io/io_storage.h>
+
+/* block devices ops */
+typedef struct io_block_ops {
+ size_t (*read)(int lba, uintptr_t buf, size_t size);
+ size_t (*write)(int lba, const uintptr_t buf, size_t size);
+} io_block_ops_t;
+
+typedef struct io_block_dev_spec {
+ io_block_spec_t buffer;
+ io_block_ops_t ops;
+ size_t block_size;
+} io_block_dev_spec_t;
+
+struct io_dev_connector;
+
+int register_io_dev_block(const struct io_dev_connector **dev_con);
+
+#endif /* IO_BLOCK_H */
diff --git a/include/drivers/io/io_driver.h b/include/drivers/io/io_driver.h
new file mode 100644
index 0000000..d8bb435
--- /dev/null
+++ b/include/drivers/io/io_driver.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IO_DRIVER_H
+#define IO_DRIVER_H
+
+#include <stdint.h>
+
+#include <drivers/io/io_storage.h>
+
+/* Generic IO entity structure,representing an accessible IO construct on the
+ * device, such as a file */
+typedef struct io_entity {
+ struct io_dev_info *dev_handle;
+ uintptr_t info;
+} io_entity_t;
+
+
+/* Device info structure, providing device-specific functions and a means of
+ * adding driver-specific state */
+typedef struct io_dev_info {
+ const struct io_dev_funcs *funcs;
+ uintptr_t info;
+} io_dev_info_t;
+
+
+/* Structure used to create a connection to a type of device */
+typedef struct io_dev_connector {
+ /* dev_open opens a connection to a particular device driver */
+ int (*dev_open)(const uintptr_t dev_spec, io_dev_info_t **dev_info);
+} io_dev_connector_t;
+
+
+/* Structure to hold device driver function pointers */
+typedef struct io_dev_funcs {
+ io_type_t (*type)(void);
+ int (*open)(io_dev_info_t *dev_info, const uintptr_t spec,
+ io_entity_t *entity);
+ int (*seek)(io_entity_t *entity, int mode, signed long long offset);
+ int (*size)(io_entity_t *entity, size_t *length);
+ int (*read)(io_entity_t *entity, uintptr_t buffer, size_t length,
+ size_t *length_read);
+ int (*write)(io_entity_t *entity, const uintptr_t buffer,
+ size_t length, size_t *length_written);
+ int (*close)(io_entity_t *entity);
+ int (*dev_init)(io_dev_info_t *dev_info, const uintptr_t init_params);
+ int (*dev_close)(io_dev_info_t *dev_info);
+} io_dev_funcs_t;
+
+
+/* Operations intended to be performed during platform initialisation */
+
+/* Register an IO device */
+int io_register_device(const io_dev_info_t *dev_info);
+
+#endif /* IO_DRIVER_H */
diff --git a/include/drivers/io/io_dummy.h b/include/drivers/io/io_dummy.h
new file mode 100644
index 0000000..edfc699
--- /dev/null
+++ b/include/drivers/io/io_dummy.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IO_DUMMY_H
+#define IO_DUMMY_H
+
+int register_io_dev_dummy(const struct io_dev_connector **dev_con);
+
+#endif /* IO_DUMMY_H */
diff --git a/include/drivers/io/io_encrypted.h b/include/drivers/io/io_encrypted.h
new file mode 100644
index 0000000..9dcf061
--- /dev/null
+++ b/include/drivers/io/io_encrypted.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2020, Linaro Limited. All rights reserved.
+ * Author: Sumit Garg <sumit.garg@linaro.org>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IO_ENCRYPTED_H
+#define IO_ENCRYPTED_H
+
+struct io_dev_connector;
+
+int register_io_dev_enc(const struct io_dev_connector **dev_con);
+
+#endif /* IO_ENCRYPTED_H */
diff --git a/include/drivers/io/io_fip.h b/include/drivers/io/io_fip.h
new file mode 100644
index 0000000..7e65436
--- /dev/null
+++ b/include/drivers/io/io_fip.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IO_FIP_H
+#define IO_FIP_H
+
+struct io_dev_connector;
+
+int register_io_dev_fip(const struct io_dev_connector **dev_con);
+int fip_dev_get_plat_toc_flag(io_dev_info_t *dev_info, uint16_t *plat_toc_flag);
+
+#endif /* IO_FIP_H */
diff --git a/include/drivers/io/io_memmap.h b/include/drivers/io/io_memmap.h
new file mode 100644
index 0000000..87e3466
--- /dev/null
+++ b/include/drivers/io/io_memmap.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IO_MEMMAP_H
+#define IO_MEMMAP_H
+
+struct io_dev_connector;
+
+int register_io_dev_memmap(const struct io_dev_connector **dev_con);
+
+#endif /* IO_MEMMAP_H */
diff --git a/include/drivers/io/io_mtd.h b/include/drivers/io/io_mtd.h
new file mode 100644
index 0000000..2b5d9b1
--- /dev/null
+++ b/include/drivers/io/io_mtd.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IO_MTD_H
+#define IO_MTD_H
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include <drivers/io/io_storage.h>
+
+/* MTD devices ops */
+typedef struct io_mtd_ops {
+ /*
+ * Initialize MTD framework and retrieve device information.
+ *
+ * @size: [out] MTD device size in bytes.
+ * @erase_size: [out] MTD erase size in bytes.
+ * Return 0 on success, a negative error code otherwise.
+ */
+ int (*init)(unsigned long long *size, unsigned int *erase_size);
+
+ /*
+ * Execute a read memory operation.
+ *
+ * @offset: Offset in bytes to start read operation.
+ * @buffer: [out] Buffer to store read data.
+ * @length: Required length to be read in bytes.
+ * @out_length: [out] Length read in bytes.
+ * Return 0 on success, a negative error code otherwise.
+ */
+ int (*read)(unsigned int offset, uintptr_t buffer, size_t length,
+ size_t *out_length);
+
+ /*
+ * Execute a write memory operation.
+ *
+ * @offset: Offset in bytes to start write operation.
+ * @buffer: Buffer to be written in device.
+ * @length: Required length to be written in bytes.
+ * Return 0 on success, a negative error code otherwise.
+ */
+ int (*write)(unsigned int offset, uintptr_t buffer, size_t length);
+
+ /*
+ * Look for an offset to be added to the given offset.
+ *
+ * @base: Base address of the area.
+ * @offset: Offset in bytes to start read operation.
+ * @extra_offset: [out] Offset to be added to the previous offset.
+ * Return 0 on success, a negative error code otherwise.
+ */
+ int (*seek)(uintptr_t base, unsigned int offset, size_t *extra_offset);
+} io_mtd_ops_t;
+
+typedef struct io_mtd_dev_spec {
+ unsigned long long device_size;
+ unsigned int erase_size;
+ size_t offset;
+ io_mtd_ops_t ops;
+} io_mtd_dev_spec_t;
+
+struct io_dev_connector;
+
+int register_io_dev_mtd(const struct io_dev_connector **dev_con);
+
+#endif /* IO_MTD_H */
diff --git a/include/drivers/io/io_semihosting.h b/include/drivers/io/io_semihosting.h
new file mode 100644
index 0000000..e90ea5c
--- /dev/null
+++ b/include/drivers/io/io_semihosting.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IO_SEMIHOSTING_H
+#define IO_SEMIHOSTING_H
+
+struct io_dev_connector;
+
+int register_io_dev_sh(const struct io_dev_connector **dev_con);
+
+#endif /* IO_SEMIHOSTING_H */
diff --git a/include/drivers/io/io_storage.h b/include/drivers/io/io_storage.h
new file mode 100644
index 0000000..8f30ed0
--- /dev/null
+++ b/include/drivers/io/io_storage.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IO_STORAGE_H
+#define IO_STORAGE_H
+
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h> /* For ssize_t */
+
+#include <tools_share/uuid.h>
+
+/* Device type which can be used to enable policy decisions about which device
+ * to access */
+typedef enum {
+ IO_TYPE_INVALID,
+ IO_TYPE_SEMIHOSTING,
+ IO_TYPE_MEMMAP,
+ IO_TYPE_DUMMY,
+ IO_TYPE_FIRMWARE_IMAGE_PACKAGE,
+ IO_TYPE_BLOCK,
+ IO_TYPE_MTD,
+ IO_TYPE_MMC,
+ IO_TYPE_ENCRYPTED,
+ IO_TYPE_MAX
+} io_type_t;
+
+
+/* Modes used when seeking data on a supported device */
+typedef enum {
+ IO_SEEK_INVALID,
+ IO_SEEK_SET,
+ IO_SEEK_END,
+ IO_SEEK_CUR,
+ IO_SEEK_MAX
+} io_seek_mode_t;
+
+
+/* Connector type, providing a means of identifying a device to open */
+struct io_dev_connector;
+
+
+/* File specification - used to refer to data on a device supporting file-like
+ * entities */
+typedef struct io_file_spec {
+ const char *path;
+ unsigned int mode;
+} io_file_spec_t;
+
+/* UUID specification - used to refer to data accessed using UUIDs (i.e. FIP
+ * images) */
+typedef struct io_uuid_spec {
+ uuid_t uuid;
+} io_uuid_spec_t;
+
+/* Block specification - used to refer to data on a device supporting
+ * block-like entities */
+typedef struct io_block_spec {
+ size_t offset;
+ size_t length;
+} io_block_spec_t;
+
+
+/* Access modes used when accessing data on a device */
+#define IO_MODE_INVALID (0)
+#define IO_MODE_RO (1 << 0)
+#define IO_MODE_RW (1 << 1)
+
+
+/* Open a connection to a device */
+int io_dev_open(const struct io_dev_connector *dev_con,
+ const uintptr_t dev_spec,
+ uintptr_t *handle);
+
+
+/* Initialise a device explicitly - to permit lazy initialisation or
+ * re-initialisation */
+int io_dev_init(uintptr_t dev_handle, const uintptr_t init_params);
+
+/* Close a connection to a device */
+int io_dev_close(uintptr_t dev_handle);
+
+
+/* Synchronous operations */
+int io_open(uintptr_t dev_handle, const uintptr_t spec, uintptr_t *handle);
+
+int io_seek(uintptr_t handle, io_seek_mode_t mode, signed long long offset);
+
+int io_size(uintptr_t handle, size_t *length);
+
+int io_read(uintptr_t handle, uintptr_t buffer, size_t length,
+ size_t *length_read);
+
+int io_write(uintptr_t handle, const uintptr_t buffer, size_t length,
+ size_t *length_written);
+
+int io_close(uintptr_t handle);
+
+
+#endif /* IO_STORAGE_H */
diff --git a/include/drivers/marvell/addr_map.h b/include/drivers/marvell/addr_map.h
new file mode 100644
index 0000000..0d219f2
--- /dev/null
+++ b/include/drivers/marvell/addr_map.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* Address map types for Marvell address translation unit drivers */
+
+#ifndef ADDR_MAP_H
+#define ADDR_MAP_H
+
+#include <stdint.h>
+
+struct addr_map_win {
+ uint64_t base_addr;
+ uint64_t win_size;
+ uint32_t target_id;
+};
+
+#endif /* ADDR_MAP_H */
diff --git a/include/drivers/marvell/amb_adec.h b/include/drivers/marvell/amb_adec.h
new file mode 100644
index 0000000..a92db5b
--- /dev/null
+++ b/include/drivers/marvell/amb_adec.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* AXI to M-Bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs */
+
+#ifndef AMB_ADEC_H
+#define AMB_ADEC_H
+
+#include <stdint.h>
+
+enum amb_attribute_ids {
+ AMB_SPI0_CS0_ID = 0x1E,
+ AMB_SPI0_CS1_ID = 0x5E,
+ AMB_SPI0_CS2_ID = 0x9E,
+ AMB_SPI0_CS3_ID = 0xDE,
+ AMB_SPI1_CS0_ID = 0x1A,
+ AMB_SPI1_CS1_ID = 0x5A,
+ AMB_SPI1_CS2_ID = 0x9A,
+ AMB_SPI1_CS3_ID = 0xDA,
+ AMB_DEV_CS0_ID = 0x3E,
+ AMB_DEV_CS1_ID = 0x3D,
+ AMB_DEV_CS2_ID = 0x3B,
+ AMB_DEV_CS3_ID = 0x37,
+ AMB_BOOT_CS_ID = 0x2f,
+ AMB_BOOT_ROM_ID = 0x1D,
+};
+
+#define AMB_MAX_WIN_ID 7
+
+int init_amb_adec(uintptr_t base);
+
+#endif /* AMB_ADEC_H */
diff --git a/include/drivers/marvell/ap807_clocks_init.h b/include/drivers/marvell/ap807_clocks_init.h
new file mode 100644
index 0000000..4353b83
--- /dev/null
+++ b/include/drivers/marvell/ap807_clocks_init.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#ifndef AP807_INIT_CLOCKS_H
+#define AP807_INIT_CLOCKS_H
+
+void ap807_clocks_init(unsigned int freq_option);
+
+#endif /* AP807_INIT_CLOCKS_H */
+
diff --git a/include/drivers/marvell/aro.h b/include/drivers/marvell/aro.h
new file mode 100644
index 0000000..4d1094a
--- /dev/null
+++ b/include/drivers/marvell/aro.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2017 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+#ifndef ARO_H
+#define ARO_H
+
+enum hws_freq {
+ CPU_FREQ_2000,
+ CPU_FREQ_1800,
+ CPU_FREQ_1600,
+ CPU_FREQ_1400,
+ CPU_FREQ_1300,
+ CPU_FREQ_1200,
+ CPU_FREQ_1000,
+ CPU_FREQ_600,
+ CPU_FREQ_800,
+ DDR_FREQ_LAST,
+ DDR_FREQ_SAR
+};
+
+#include <mvebu_def.h>
+
+enum cpu_clock_freq_mode {
+ CPU_2000_DDR_1200_RCLK_1200 = 0x0,
+ CPU_2000_DDR_1050_RCLK_1050 = 0x1,
+ CPU_1600_DDR_800_RCLK_800 = 0x4,
+ CPU_2200_DDR_1200_RCLK_1200 = 0x6,
+ CPU_1800_DDR_1050_RCLK_1050 = 0x7,
+ CPU_1600_DDR_900_RCLK_900 = 0x0B,
+ CPU_1600_DDR_1050_RCLK_1050 = 0x0D,
+ CPU_1600_DDR_1200_RCLK_1200 = 0x0D,
+ CPU_1600_DDR_900_RCLK_900_2 = 0x0E,
+ CPU_1000_DDR_650_RCLK_650 = 0x13,
+ CPU_1300_DDR_800_RCLK_800 = 0x14,
+ CPU_1300_DDR_650_RCLK_650 = 0x17,
+ CPU_1200_DDR_800_RCLK_800 = 0x19,
+ CPU_1400_DDR_800_RCLK_800 = 0x1a,
+ CPU_600_DDR_800_RCLK_800 = 0x1B,
+ CPU_800_DDR_800_RCLK_800 = 0x1C,
+ CPU_1000_DDR_800_RCLK_800 = 0x1D,
+ CPU_DDR_RCLK_INVALID
+};
+
+int init_aro(void);
+
+#endif /* ARO_H */
diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h
new file mode 100644
index 0000000..72111b3
--- /dev/null
+++ b/include/drivers/marvell/cache_llc.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2018-2020 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* LLC driver is the Last Level Cache (L3C) driver
+ * for Marvell SoCs in AP806, AP807, and AP810
+ */
+
+#ifndef CACHE_LLC_H
+#define CACHE_LLC_H
+
+#define LLC_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x100)
+#define LLC_SECURE_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x10C)
+#define LLC_SYNC(ap) (MVEBU_LLC_BASE(ap) + 0x700)
+#define LLC_BANKED_MNT_AHR(ap) (MVEBU_LLC_BASE(ap) + 0x724)
+#define LLC_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x77C)
+#define LLC_BLK_ALOC(ap) (MVEBU_LLC_BASE(ap) + 0x78c)
+#define LLC_CLEAN_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7BC)
+#define LLC_CLEAN_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7FC)
+#define LLC_TCN_LOCK(ap, tc) (MVEBU_LLC_BASE(ap) + 0x920 + 4 * (tc))
+
+#define MASTER_LLC_CTRL LLC_CTRL(MVEBU_AP0)
+#define MASTER_LLC_INV_WAY LLC_INV_WAY(MVEBU_AP0)
+#define MASTER_LLC_TC0_LOCK LLC_TCN_LOCK(MVEBU_AP0, 0)
+
+#define LLC_CTRL_EN 1
+#define LLC_EXCLUSIVE_EN 0x100
+#define LLC_ALL_WAYS_MASK 0xFFFFFFFF
+
+/* AP806/AP807 - 1MB 8-ways LLC */
+#define LLC_WAYS 8
+#define LLC_WAY_MASK ((1 << LLC_WAYS) - 1)
+#define LLC_SIZE (1024 * 1024)
+#define LLC_WAY_SIZE (LLC_SIZE / LLC_WAYS)
+#define LLC_TC_NUM 15
+
+#define LLC_BLK_ALOC_WAY_ID(way) ((way) & 0x1f)
+#define LLC_BLK_ALOC_WAY_DATA_DSBL (0x0 << 6)
+#define LLC_BLK_ALOC_WAY_DATA_CLR (0x1 << 6)
+#define LLC_BLK_ALOC_WAY_DATA_SET (0x3 << 6)
+#define LLC_BLK_ALOC_BASE_ADDR(addr) ((addr) & ~(LLC_WAY_SIZE - 1))
+
+#ifndef __ASSEMBLER__
+void llc_cache_sync(int ap_index);
+void llc_flush_all(int ap_index);
+void llc_clean_all(int ap_index);
+void llc_inv_all(int ap_index);
+void llc_disable(int ap_index);
+void llc_enable(int ap_index, int excl_mode);
+int llc_is_exclusive(int ap_index);
+void llc_runtime_enable(int ap_index);
+#if LLC_SRAM
+int llc_sram_enable(int ap_index, int size);
+void llc_sram_disable(int ap_index);
+int llc_sram_test(int ap_index, int size, char *msg);
+#endif /* LLC_SRAM */
+#endif /* __ASSEMBLER__ */
+
+#endif /* CACHE_LLC_H */
diff --git a/include/drivers/marvell/ccu.h b/include/drivers/marvell/ccu.h
new file mode 100644
index 0000000..f8f0adf
--- /dev/null
+++ b/include/drivers/marvell/ccu.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */
+
+#ifndef CCU_H
+#define CCU_H
+
+#ifndef __ASSEMBLER__
+#include <drivers/marvell/addr_map.h>
+#endif
+
+/* CCU registers definitions */
+#define CCU_WIN_CR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x0 + \
+ (0x10 * win))
+#define CCU_TARGET_ID_OFFSET (8)
+#define CCU_TARGET_ID_MASK (0x7F)
+
+#define CCU_WIN_SCR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x4 + \
+ (0x10 * win))
+#define CCU_WIN_ENA_WRITE_SECURE (0x1)
+#define CCU_WIN_ENA_READ_SECURE (0x2)
+
+#define CCU_WIN_ALR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x8 + \
+ (0x10 * win))
+#define CCU_WIN_AHR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0xC + \
+ (0x10 * win))
+
+#define CCU_WIN_GCR_OFFSET(ap) (MVEBU_CCU_BASE(ap) + 0xD0)
+#define CCU_GCR_TARGET_OFFSET (8)
+#define CCU_GCR_TARGET_MASK (0xFF)
+
+#define CCU_SRAM_WIN_CR CCU_WIN_CR_OFFSET(MVEBU_AP0, 1)
+
+#ifndef __ASSEMBLER__
+int init_ccu(int);
+void ccu_win_check(struct addr_map_win *win);
+void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id);
+void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
+void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
+void ccu_dram_win_config(int ap_index, struct addr_map_win *win);
+void ccu_dram_target_set(int ap_index, uint32_t target);
+void ccu_save_win_all(int ap_id);
+void ccu_restore_win_all(int ap_id);
+int ccu_is_win_enabled(int ap_index, uint32_t win_id);
+void errata_wa_init(void);
+#endif
+
+#endif /* CCU_H */
diff --git a/include/drivers/marvell/gwin.h b/include/drivers/marvell/gwin.h
new file mode 100644
index 0000000..1b874a7
--- /dev/null
+++ b/include/drivers/marvell/gwin.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* GWIN unit device driver for Marvell AP810 SoC */
+
+#ifndef GWIN_H
+#define GWIN_H
+
+#include <drivers/marvell/addr_map.h>
+
+int init_gwin(int ap_index);
+void gwin_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
+void gwin_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
+
+#endif /* GWIN_H */
diff --git a/include/drivers/marvell/i2c.h b/include/drivers/marvell/i2c.h
new file mode 100644
index 0000000..06c5114
--- /dev/null
+++ b/include/drivers/marvell/i2c.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#ifndef I2C_H
+#define I2C_H
+
+
+void i2c_init(void);
+
+int i2c_read(uint8_t chip,
+ unsigned int addr, int alen, uint8_t *buffer, int len);
+
+int i2c_write(uint8_t chip,
+ unsigned int addr, int alen, uint8_t *buffer, int len);
+
+#endif /* I2C_H */
diff --git a/include/drivers/marvell/io_win.h b/include/drivers/marvell/io_win.h
new file mode 100644
index 0000000..7438d6b
--- /dev/null
+++ b/include/drivers/marvell/io_win.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* IO Window unit device driver for Marvell AP807, AP807 and AP810 SoCs */
+
+#ifndef IO_WIN_H
+#define IO_WIN_H
+
+#include <drivers/marvell/addr_map.h>
+
+int init_io_win(int ap_index);
+void iow_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
+void iow_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
+void iow_save_win_all(int ap_id);
+void iow_restore_win_all(int ap_id);
+
+#endif /* IO_WIN_H */
diff --git a/include/drivers/marvell/iob.h b/include/drivers/marvell/iob.h
new file mode 100644
index 0000000..9b5e515
--- /dev/null
+++ b/include/drivers/marvell/iob.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* IOW unit device driver for Marvell CP110 and CP115 SoCs */
+
+#ifndef IOB_H
+#define IOB_H
+
+#include <drivers/marvell/addr_map.h>
+
+enum target_ids_iob {
+ INTERNAL_TID = 0x0,
+ MCI0_TID = 0x1,
+ PEX1_TID = 0x2,
+ PEX2_TID = 0x3,
+ PEX0_TID = 0x4,
+ NAND_TID = 0x5,
+ RUNIT_TID = 0x6,
+ MCI1_TID = 0x7,
+ IOB_MAX_TID
+};
+
+int init_iob(uintptr_t base);
+void iob_cfg_space_update(int ap_idx, int cp_idx,
+ uintptr_t base, uintptr_t new_base);
+
+#endif /* IOB_H */
diff --git a/include/drivers/marvell/mci.h b/include/drivers/marvell/mci.h
new file mode 100644
index 0000000..af5d620
--- /dev/null
+++ b/include/drivers/marvell/mci.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* MCI bus driver for Marvell ARMADA 8K and 8K+ SoCs */
+
+#ifndef MCI_H
+#define MCI_H
+
+int mci_link_tune(int mci_index);
+void mci_turn_link_down(void);
+void mci_turn_link_on(void);
+int mci_get_link_status(void);
+
+#endif /* MCI_H */
diff --git a/include/drivers/marvell/mochi/ap_setup.h b/include/drivers/marvell/mochi/ap_setup.h
new file mode 100644
index 0000000..5b0e75f
--- /dev/null
+++ b/include/drivers/marvell/mochi/ap_setup.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* AP8xx Marvell SoC driver */
+
+#ifndef AP_SETUP_H
+#define AP_SETUP_H
+
+void ap_init(void);
+void ap_ble_init(void);
+int ap_get_count(void);
+void update_cp110_default_win(int cp_id);
+
+#endif /* AP_SETUP_H */
diff --git a/include/drivers/marvell/mochi/cp110_setup.h b/include/drivers/marvell/mochi/cp110_setup.h
new file mode 100644
index 0000000..4a69257
--- /dev/null
+++ b/include/drivers/marvell/mochi/cp110_setup.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* CP110 Marvell SoC driver */
+
+#ifndef CP110_SETUP_H
+#define CP110_SETUP_H
+
+#include <lib/mmio.h>
+
+#include <mvebu_def.h>
+
+#define MVEBU_DEVICE_ID_REG (MVEBU_CP_DFX_OFFSET + 0x40)
+#define MVEBU_DEVICE_ID_OFFSET (0)
+#define MVEBU_DEVICE_ID_MASK (0xffff << MVEBU_DEVICE_ID_OFFSET)
+#define MVEBU_DEVICE_REV_OFFSET (16)
+#define MVEBU_DEVICE_REV_MASK (0xf << MVEBU_DEVICE_REV_OFFSET)
+#define MVEBU_70X0_DEV_ID (0x7040)
+#define MVEBU_70X0_CP115_DEV_ID (0x7045)
+#define MVEBU_3900_DEV_ID (0x6025)
+#define MVEBU_80X0_DEV_ID (0x8040)
+#define MVEBU_80X0_CP115_DEV_ID (0x8045)
+#define MVEBU_CN9130_DEV_ID (0x7025)
+#define MVEBU_CP110_SA_DEV_ID (0x110)
+#define MVEBU_CP110_REF_ID_A1 1
+#define MVEBU_CP110_REF_ID_A2 2
+#define MAX_STREAM_ID_PER_CP (0x10)
+#define STREAM_ID_BASE (0x40)
+
+#define MVEBU_SECUREBOOT_CTRL_REG (MVEBU_RFU_BASE + 0x4730)
+#define MVEBU_SECUREBOOT_EN_MASK BIT(0)
+
+static inline uint32_t cp110_device_id_get(uintptr_t base)
+{
+ /* Returns:
+ * - MVEBU_70X0_DEV_ID for A70X0 family
+ * - MVEBU_80X0_DEV_ID for A80X0 family
+ * - MVEBU_CP110_SA_DEV_ID for CP that connected stand alone
+ */
+ return (mmio_read_32(base + MVEBU_DEVICE_ID_REG) >>
+ MVEBU_DEVICE_ID_OFFSET) &
+ MVEBU_DEVICE_ID_MASK;
+}
+
+static inline uint32_t cp110_rev_id_get(uintptr_t base)
+{
+ return (mmio_read_32(base + MVEBU_DEVICE_ID_REG) &
+ MVEBU_DEVICE_REV_MASK) >>
+ MVEBU_DEVICE_REV_OFFSET;
+}
+
+static inline uint32_t is_secure(void)
+{
+ return !!(mmio_read_32(MVEBU_SECUREBOOT_CTRL_REG) &
+ MVEBU_SECUREBOOT_EN_MASK);
+}
+
+void cp110_init(uintptr_t cp110_base, uint32_t stream_id);
+void cp110_ble_init(uintptr_t cp110_base);
+void cp110_amb_init(uintptr_t base);
+
+#endif /* CP110_SETUP_H */
diff --git a/include/drivers/marvell/thermal.h b/include/drivers/marvell/thermal.h
new file mode 100644
index 0000000..48376a7
--- /dev/null
+++ b/include/drivers/marvell/thermal.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* Driver for thermal unit located in Marvell ARMADA 8K and compatible SoCs */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+struct tsen_config {
+ /* thermal temperature parameters */
+ int tsen_offset;
+ int tsen_gain;
+ int tsen_divisor;
+ /* thermal data */
+ int tsen_ready;
+ void *regs_base;
+ /* thermal functionality */
+ int (*ptr_tsen_probe)(struct tsen_config *cfg);
+ int (*ptr_tsen_read)(struct tsen_config *cfg, int *temp);
+};
+
+/* Thermal driver APIs */
+int marvell_thermal_init(struct tsen_config *tsen_cfg);
+int marvell_thermal_read(struct tsen_config *tsen_cfg, int *temp);
+struct tsen_config *marvell_thermal_config_get(void);
+
+#endif /* THERMAL_H */
diff --git a/include/drivers/marvell/uart/a3700_console.h b/include/drivers/marvell/uart/a3700_console.h
new file mode 100644
index 0000000..ce673a1
--- /dev/null
+++ b/include/drivers/marvell/uart/a3700_console.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#ifndef A3700_CONSOLE_H
+#define A3700_CONSOLE_H
+
+#include <drivers/console.h>
+#include <platform_def.h>
+
+/* MVEBU UART Registers */
+#define UART_RX_REG 0x00
+#define UART_TX_REG 0x04
+#define UART_CTRL_REG 0x08
+#define UART_STATUS_REG 0x0c
+#define UART_BAUD_REG 0x10
+#define UART_POSSR_REG 0x14
+
+/* FIFO Control Register bits */
+#define UARTFCR_FIFOMD_16450 (0 << 6)
+#define UARTFCR_FIFOMD_16550 (1 << 6)
+#define UARTFCR_RXTRIG_1 (0 << 6)
+#define UARTFCR_RXTRIG_4 (1 << 6)
+#define UARTFCR_RXTRIG_8 (2 << 6)
+#define UARTFCR_RXTRIG_16 (3 << 6)
+#define UARTFCR_TXTRIG_1 (0 << 4)
+#define UARTFCR_TXTRIG_4 (1 << 4)
+#define UARTFCR_TXTRIG_8 (2 << 4)
+#define UARTFCR_TXTRIG_16 (3 << 4)
+#define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */
+#define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */
+#define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */
+#define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */
+
+/* Line Control Register bits */
+#define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */
+#define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */
+#define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */
+#define UARTLCR_EVEN (1 << 4) /* Even Parity Format */
+#define UARTLCR_PAR (1 << 3) /* Parity */
+#define UARTLCR_STOP (1 << 2) /* Stop Bit */
+#define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */
+#define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */
+#define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */
+#define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */
+
+/* Line Status Register bits */
+#define UARTLSR_TXFIFOFULL (1 << 11) /* Tx Fifo Full */
+#define UARTLSR_TXEMPTY (1 << 6) /* Tx Empty */
+#define UARTLSR_RXRDY (1 << 4) /* Rx Ready */
+
+/* UART Control Register bits */
+#define UART_CTRL_RXFIFO_RESET (1 << 14)
+#define UART_CTRL_TXFIFO_RESET (1 << 15)
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+/*
+ * Initialize a new a3700 console instance and register it with the console
+ * framework. The |console| pointer must point to storage that will be valid
+ * for the lifetime of the console, such as a global or static local variable.
+ * Its contents will be reinitialized from scratch.
+ */
+int console_a3700_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
+ console_t *console);
+
+#endif /*__ASSEMBLER__*/
+
+#endif /* A3700_CONSOLE_H */
diff --git a/include/drivers/measured_boot/event_log/event_log.h b/include/drivers/measured_boot/event_log/event_log.h
new file mode 100644
index 0000000..eb0e2b1
--- /dev/null
+++ b/include/drivers/measured_boot/event_log/event_log.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EVENT_LOG_H
+#define EVENT_LOG_H
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <drivers/auth/crypto_mod.h>
+#include <drivers/measured_boot/event_log/tcg.h>
+
+/*
+ * Set Event Log debug level to one of:
+ *
+ * LOG_LEVEL_ERROR
+ * LOG_LEVEL_INFO
+ * LOG_LEVEL_WARNING
+ * LOG_LEVEL_VERBOSE
+ */
+#if EVENT_LOG_LEVEL == LOG_LEVEL_ERROR
+#define LOG_EVENT ERROR
+#elif EVENT_LOG_LEVEL == LOG_LEVEL_NOTICE
+#define LOG_EVENT NOTICE
+#elif EVENT_LOG_LEVEL == LOG_LEVEL_WARNING
+#define LOG_EVENT WARN
+#elif EVENT_LOG_LEVEL == LOG_LEVEL_INFO
+#define LOG_EVENT INFO
+#elif EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
+#define LOG_EVENT VERBOSE
+#else
+#error "Not supported EVENT_LOG_LEVEL"
+#endif
+
+/* Number of hashing algorithms supported */
+#define HASH_ALG_COUNT 1U
+
+#define EVLOG_INVALID_ID UINT32_MAX
+
+#define MEMBER_SIZE(type, member) sizeof(((type *)0)->member)
+
+/*
+ * Each event log entry has some metadata (i.e. a string) that identifies
+ * what is measured.These macros define these strings.
+ * Note that these strings follow the standardization recommendations
+ * defined in the Arm Server Base Security Guide (a.k.a. SBSG, Arm DEN 0086),
+ * where applicable. They should not be changed in the code.
+ * Where the SBSG does not make recommendations, we are free to choose any
+ * naming convention.
+ * The key thing is to choose meaningful strings so that when the TPM event
+ * log is used in attestation, the different components can be identified.
+ */
+#define EVLOG_BL2_STRING "BL_2"
+#define EVLOG_BL31_STRING "SECURE_RT_EL3"
+#if defined(SPD_opteed)
+#define EVLOG_BL32_STRING "SECURE_RT_EL1_OPTEE"
+#elif defined(SPD_tspd)
+#define EVLOG_BL32_STRING "SECURE_RT_EL1_TSPD"
+#elif defined(SPD_tlkd)
+#define EVLOG_BL32_STRING "SECURE_RT_EL1_TLKD"
+#elif defined(SPD_trusty)
+#define EVLOG_BL32_STRING "SECURE_RT_EL1_TRUSTY"
+#else
+#define EVLOG_BL32_STRING "SECURE_RT_EL1_UNKNOWN"
+#endif
+#define EVLOG_BL32_EXTRA1_STRING "SECURE_RT_EL1_OPTEE_EXTRA1"
+#define EVLOG_BL32_EXTRA2_STRING "SECURE_RT_EL1_OPTEE_EXTRA2"
+#define EVLOG_BL33_STRING "BL_33"
+#define EVLOG_FW_CONFIG_STRING "FW_CONFIG"
+#define EVLOG_HW_CONFIG_STRING "HW_CONFIG"
+#define EVLOG_NT_FW_CONFIG_STRING "NT_FW_CONFIG"
+#define EVLOG_SCP_BL2_STRING "SYS_CTRL_2"
+#define EVLOG_SOC_FW_CONFIG_STRING "SOC_FW_CONFIG"
+#define EVLOG_STM32_STRING "STM32"
+#define EVLOG_TB_FW_CONFIG_STRING "TB_FW_CONFIG"
+#define EVLOG_TOS_FW_CONFIG_STRING "TOS_FW_CONFIG"
+#define EVLOG_RMM_STRING "RMM"
+#define EVLOG_SP1_STRING "SP1"
+#define EVLOG_SP2_STRING "SP2"
+#define EVLOG_SP3_STRING "SP3"
+#define EVLOG_SP4_STRING "SP4"
+#define EVLOG_SP5_STRING "SP5"
+#define EVLOG_SP6_STRING "SP6"
+#define EVLOG_SP7_STRING "SP7"
+#define EVLOG_SP8_STRING "SP8"
+
+typedef struct {
+ unsigned int id;
+ const char *name;
+ unsigned int pcr;
+} event_log_metadata_t;
+
+#define ID_EVENT_SIZE (sizeof(id_event_headers_t) + \
+ (sizeof(id_event_algorithm_size_t) * HASH_ALG_COUNT) + \
+ sizeof(id_event_struct_data_t))
+
+#define LOC_EVENT_SIZE (sizeof(event2_header_t) + \
+ sizeof(tpmt_ha) + TCG_DIGEST_SIZE + \
+ sizeof(event2_data_t) + \
+ sizeof(startup_locality_event_t))
+
+#define LOG_MIN_SIZE (ID_EVENT_SIZE + LOC_EVENT_SIZE)
+
+#define EVENT2_HDR_SIZE (sizeof(event2_header_t) + \
+ sizeof(tpmt_ha) + TCG_DIGEST_SIZE + \
+ sizeof(event2_data_t))
+
+/* Functions' declarations */
+void event_log_buf_init(uint8_t *event_log_start, uint8_t *event_log_finish);
+void event_log_init(uint8_t *event_log_start, uint8_t *event_log_finish);
+void event_log_write_specid_event(void);
+void event_log_write_header(void);
+void dump_event_log(uint8_t *log_addr, size_t log_size);
+const event_log_metadata_t *plat_event_log_get_metadata(void);
+int event_log_measure(uintptr_t data_base, uint32_t data_size,
+ unsigned char hash_data[CRYPTO_MD_MAX_SIZE]);
+void event_log_record(const uint8_t *hash, uint32_t event_type,
+ const event_log_metadata_t *metadata_ptr);
+int event_log_measure_and_record(uintptr_t data_base, uint32_t data_size,
+ uint32_t data_id);
+size_t event_log_get_cur_size(uint8_t *event_log_start);
+
+#endif /* EVENT_LOG_H */
diff --git a/include/drivers/measured_boot/event_log/tcg.h b/include/drivers/measured_boot/event_log/tcg.h
new file mode 100644
index 0000000..4ac2c2f
--- /dev/null
+++ b/include/drivers/measured_boot/event_log/tcg.h
@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TCG_H
+#define TCG_H
+
+#include <stdint.h>
+
+#define TCG_ID_EVENT_SIGNATURE_03 "Spec ID Event03"
+#define TCG_STARTUP_LOCALITY_SIGNATURE "StartupLocality"
+
+#define TCG_SPEC_VERSION_MAJOR_TPM2 2
+#define TCG_SPEC_VERSION_MINOR_TPM2 0
+#define TCG_SPEC_ERRATA_TPM2 2
+
+/*
+ * Event types
+ * Ref. Table 9 Events
+ * TCG PC Client Platform Firmware Profile Specification.
+ */
+#define EV_PREBOOT_CERT U(0x00000000)
+#define EV_POST_CODE U(0x00000001)
+#define EV_UNUSED U(0x00000002)
+#define EV_NO_ACTION U(0x00000003)
+#define EV_SEPARATOR U(0x00000004)
+#define EV_ACTION U(0x00000005)
+#define EV_EVENT_TAG U(0x00000006)
+#define EV_S_CRTM_CONTENTS U(0x00000007)
+#define EV_S_CRTM_VERSION U(0x00000008)
+#define EV_CPU_MICROCODE U(0x00000009)
+#define EV_PLATFORM_CONFIG_FLAGS U(0x0000000A)
+#define EV_TABLE_OF_DEVICES U(0x0000000B)
+#define EV_COMPACT_HASH U(0x0000000C)
+#define EV_IPL U(0x0000000D)
+#define EV_IPL_PARTITION_DATA U(0x0000000E)
+#define EV_NONHOST_CODE U(0x0000000F)
+#define EV_NONHOST_CONFIG U(0x00000010)
+#define EV_NONHOST_INFO U(0x00000011)
+#define EV_OMIT_BOOT_DEVICE_EVENTS U(0x00000012)
+#define EV_EFI_EVENT_BASE U(0x80000000)
+#define EV_EFI_VARIABLE_DRIVER_CONFIG U(0x80000001)
+#define EV_EFI_VARIABLE_BOOT U(0x80000002)
+#define EV_EFI_BOOT_SERVICES_APPLICATION U(0x80000003)
+#define EV_EFI_BOOT_SERVICES_DRIVER U(0x80000004)
+#define EV_EFI_RUNTIME_SERVICES_DRIVER U(0x80000005)
+#define EV_EFI_GPT_EVENT U(0x80000006)
+#define EV_EFI_ACTION U(0x80000007)
+#define EV_EFI_PLATFORM_FIRMWARE_BLOB U(0x80000008)
+#define EV_EFI_HANDOFF_TABLES U(0x80000009)
+#define EV_EFI_HCRTM_EVENT U(0x80000010)
+#define EV_EFI_VARIABLE_AUTHORITY U(0x800000E0)
+
+/*
+ * TPM_ALG_ID constants.
+ * Ref. Table 9 - Definition of (UINT16) TPM_ALG_ID Constants
+ * Trusted Platform Module Library. Part 2: Structures
+ */
+#define TPM_ALG_SHA256 0x000B
+#define TPM_ALG_SHA384 0x000C
+#define TPM_ALG_SHA512 0x000D
+
+/* TCG Platform Type */
+#define PLATFORM_CLASS_CLIENT 0
+#define PLATFORM_CLASS_SERVER 1
+
+/* SHA digest sizes in bytes */
+#define SHA1_DIGEST_SIZE 20
+#define SHA256_DIGEST_SIZE 32
+#define SHA384_DIGEST_SIZE 48
+#define SHA512_DIGEST_SIZE 64
+
+enum {
+ /*
+ * SRTM, BIOS, Host Platform Extensions, Embedded
+ * Option ROMs and PI Drivers
+ */
+ PCR_0 = 0,
+ /* Host Platform Configuration */
+ PCR_1,
+ /* UEFI driver and application Code */
+ PCR_2,
+ /* UEFI driver and application Configuration and Data */
+ PCR_3,
+ /* UEFI Boot Manager Code (usually the MBR) and Boot Attempts */
+ PCR_4,
+ /*
+ * Boot Manager Code Configuration and Data (for use
+ * by the Boot Manager Code) and GPT/Partition Table
+ */
+ PCR_5,
+ /* Host Platform Manufacturer Specific */
+ PCR_6,
+ /* Secure Boot Policy */
+ PCR_7,
+ /* 8-15: Defined for use by the Static OS */
+ PCR_8,
+ /* Debug */
+ PCR_16 = 16,
+
+ /* D-CRTM-measurements by DRTM implementation */
+ PCR_17 = 17,
+ /* DCE measurements by DRTM implementation */
+ PCR_18 = 18
+};
+
+#pragma pack(push, 1)
+
+/*
+ * PCR Event Header
+ * TCG EFI Protocol Specification
+ * 5.3 Event Log Header
+ */
+typedef struct {
+ /* PCRIndex:
+ * The PCR Index to which this event is extended
+ */
+ uint32_t pcr_index;
+
+ /* EventType:
+ * SHALL be an EV_NO_ACTION event
+ */
+ uint32_t event_type;
+
+ /* SHALL be 20 Bytes of 0x00 */
+ uint8_t digest[SHA1_DIGEST_SIZE];
+
+ /* The size of the event */
+ uint32_t event_size;
+
+ /* SHALL be a TCG_EfiSpecIdEvent */
+ uint8_t event[]; /* [event_data_size] */
+} tcg_pcr_event_t;
+
+/*
+ * Log Header Entry Data
+ * Ref. Table 14 TCG_EfiSpecIdEventAlgorithmSize
+ * TCG PC Client Platform Firmware Profile 9.4.5.1
+ */
+typedef struct {
+ /* Algorithm ID (hashAlg) of the Hash used by BIOS */
+ uint16_t algorithm_id;
+
+ /* The size of the digest produced by the implemented Hash algorithm */
+ uint16_t digest_size;
+} id_event_algorithm_size_t;
+
+/*
+ * TCG_EfiSpecIdEvent structure
+ * Ref. Table 15 TCG_EfiSpecIdEvent
+ * TCG PC Client Platform Firmware Profile 9.4.5.1
+ */
+typedef struct {
+ /*
+ * The NUL-terminated ASCII string "Spec ID Event03".
+ * SHALL be set to {0x53, 0x70, 0x65, 0x63, 0x20, 0x49, 0x44,
+ * 0x20, 0x45, 0x76, 0x65, 0x6e, 0x74, 0x30, 0x33, 0x00}.
+ */
+ uint8_t signature[16];
+
+ /*
+ * The value for the Platform Class.
+ * The enumeration is defined in the TCG ACPI Specification Client
+ * Common Header.
+ */
+ uint32_t platform_class;
+
+ /*
+ * The PC Client Platform Profile Specification minor version number
+ * this BIOS supports.
+ * Any BIOS supporting this version (2.0) MUST set this value to 0x00.
+ */
+ uint8_t spec_version_minor;
+
+ /*
+ * The PC Client Platform Profile Specification major version number
+ * this BIOS supports.
+ * Any BIOS supporting this version (2.0) MUST set this value to 0x02.
+ */
+ uint8_t spec_version_major;
+
+ /*
+ * The PC Client Platform Profile Specification errata version number
+ * this BIOS supports.
+ * Any BIOS supporting this version (2.0) MUST set this value to 0x02.
+ */
+ uint8_t spec_errata;
+
+ /*
+ * Specifies the size of the UINTN fields used in various data
+ * structures used in this specification.
+ * 0x01 indicates UINT32 and 0x02 indicates UINT64.
+ */
+ uint8_t uintn_size;
+
+ /*
+ * The number of Hash algorithms in the digestSizes field.
+ * This field MUST be set to a value of 0x01 or greater.
+ */
+ uint32_t number_of_algorithms;
+
+ /*
+ * Each TCG_EfiSpecIdEventAlgorithmSize SHALL contain an algorithmId
+ * and digestSize for each hash algorithm used in the TCG_PCR_EVENT2
+ * structure, the first of which is a Hash algorithmID and the second
+ * is the size of the respective digest.
+ */
+ id_event_algorithm_size_t digest_size[]; /* number_of_algorithms */
+} id_event_struct_header_t;
+
+typedef struct {
+ /*
+ * Size in bytes of the VendorInfo field.
+ * Maximum value MUST be FFh bytes.
+ */
+ uint8_t vendor_info_size;
+
+ /*
+ * Provided for use by Platform Firmware implementer. The value might
+ * be used, for example, to provide more detailed information about the
+ * specific BIOS such as BIOS revision numbers, etc. The values within
+ * this field are not standardized and are implementer-specific.
+ * Platform-specific or -unique information MUST NOT be provided in
+ * this field.
+ *
+ */
+ uint8_t vendor_info[]; /* [vendorInfoSize] */
+} id_event_struct_data_t;
+
+typedef struct {
+ id_event_struct_header_t struct_header;
+ id_event_struct_data_t struct_data;
+} id_event_struct_t;
+
+typedef struct {
+ tcg_pcr_event_t header;
+ id_event_struct_header_t struct_header;
+} id_event_headers_t;
+
+/* TPMT_HA Structure */
+typedef struct {
+ /* Selector of the hash contained in the digest that implies
+ * the size of the digest
+ */
+ uint16_t algorithm_id; /* AlgorithmId */
+
+ /* Digest, depends on AlgorithmId */
+ uint8_t digest[]; /* Digest[] */
+} tpmt_ha;
+
+/*
+ * TPML_DIGEST_VALUES Structure
+ */
+typedef struct {
+ /* The number of digests in the list */
+ uint32_t count; /* Count */
+
+ /* The list of tagged digests, as sent to the TPM as part of a
+ * TPM2_PCR_Extend or as received from a TPM2_PCR_Event command
+ */
+ tpmt_ha digests[]; /* Digests[Count] */
+} tpml_digest_values;
+
+/*
+ * TCG_PCR_EVENT2 header
+ */
+typedef struct {
+ /* The PCR Index to which this event was extended */
+ uint32_t pcr_index; /* PCRIndex */
+
+ /* Type of event */
+ uint32_t event_type; /* EventType */
+
+ /* Digests:
+ * A counted list of tagged digests, which contain the digest of
+ * the event data (or external data) for all active PCR banks
+ */
+ tpml_digest_values digests; /* Digests */
+} event2_header_t;
+
+typedef struct event2_data {
+ /* The size of the event data */
+ uint32_t event_size; /* EventSize */
+
+ /* The data of the event */
+ uint8_t event[]; /* Event[EventSize] */
+} event2_data_t;
+
+/*
+ * Startup Locality Event
+ * Ref. TCG PC Client Platform Firmware Profile 9.4.5.3
+ */
+typedef struct {
+ /*
+ * The NUL-terminated ASCII string "StartupLocality" SHALL be
+ * set to {0x53 0x74 0x61 0x72 0x74 0x75 0x70 0x4C 0x6F 0x63
+ * 0x61 0x6C 0x69 0x74 0x79 0x00}
+ */
+ uint8_t signature[16];
+
+ /* The Locality Indicator which sent the TPM2_Startup command */
+ uint8_t startup_locality;
+} startup_locality_event_t;
+
+#pragma pack(pop)
+
+#endif /* TCG_H */
diff --git a/include/drivers/measured_boot/rss/rss_measured_boot.h b/include/drivers/measured_boot/rss/rss_measured_boot.h
new file mode 100644
index 0000000..fe88576
--- /dev/null
+++ b/include/drivers/measured_boot/rss/rss_measured_boot.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RSS_MEASURED_BOOT_H
+#define RSS_MEASURED_BOOT_H
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <measured_boot.h>
+
+#define RSS_MBOOT_INVALID_ID UINT32_MAX
+
+/*
+ * Each boot measurement has some metadata (i.e. a string) that identifies
+ * what was measured and how. The sw_type field of the rss_mboot_metadata
+ * structure represents the role of the software component that was measured.
+ * The below macros define strings suitable for the sw_type.
+ * The key thing is to choose meaningful strings so that when the attestation
+ * token is verified, then the different components can be identified.
+ */
+#define RSS_MBOOT_BL2_STRING "BL_2"
+#define RSS_MBOOT_BL31_STRING "SECURE_RT_EL3"
+#define RSS_MBOOT_HW_CONFIG_STRING "HW_CONFIG"
+#define RSS_MBOOT_FW_CONFIG_STRING "FW_CONFIG"
+#define RSS_MBOOT_TB_FW_CONFIG_STRING "TB_FW_CONFIG"
+#define RSS_MBOOT_SOC_FW_CONFIG_STRING "SOC_FW_CONFIG"
+#define RSS_MBOOT_RMM_STRING "RMM"
+
+
+struct rss_mboot_metadata {
+ unsigned int id;
+ uint8_t slot;
+ uint8_t signer_id[SIGNER_ID_MAX_SIZE];
+ size_t signer_id_size;
+ uint8_t version[VERSION_MAX_SIZE];
+ size_t version_size;
+ uint8_t sw_type[SW_TYPE_MAX_SIZE];
+ size_t sw_type_size;
+ bool lock_measurement;
+};
+
+/* Functions' declarations */
+void rss_measured_boot_init(void);
+struct rss_mboot_metadata *plat_rss_mboot_get_metadata(void);
+int rss_mboot_measure_and_record(uintptr_t data_base, uint32_t data_size,
+ uint32_t data_id);
+
+/* TODO: These metadata are currently not available during TF-A boot */
+int rss_mboot_set_signer_id(unsigned int img_id, const void *pk_ptr, size_t pk_len);
+
+#endif /* RSS_MEASURED_BOOT_H */
diff --git a/include/drivers/mentor/mi2cv.h b/include/drivers/mentor/mi2cv.h
new file mode 100644
index 0000000..85b733b
--- /dev/null
+++ b/include/drivers/mentor/mi2cv.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* This driver provides support for Mentor Graphics MI2CV IP core */
+
+#ifndef MI2CV_H
+#define MI2CV_H
+
+#include <stdint.h>
+
+/*
+ * Initialization, must be called once on start up, may be called
+ * repeatedly to change the speed and slave addresses.
+ */
+void i2c_init(void *i2c_base);
+
+/*
+ * Read/Write interface:
+ * chip: I2C chip address, range 0..127
+ * addr: Memory (register) address within the chip
+ * alen: Number of bytes to use for addr (typically 1, 2 for larger
+ * memories, 0 for register type devices with only one
+ * register)
+ * buffer: Where to read/write the data
+ * len: How many bytes to read/write
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int i2c_read(uint8_t chip,
+ unsigned int addr, int alen, uint8_t *buffer, int len);
+
+int i2c_write(uint8_t chip,
+ unsigned int addr, int alen, uint8_t *buffer, int len);
+
+#endif /* MI2CV_H */
diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h
new file mode 100644
index 0000000..e94693d
--- /dev/null
+++ b/include/drivers/mmc.h
@@ -0,0 +1,272 @@
+/*
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MMC_H
+#define MMC_H
+
+#include <stdint.h>
+
+#include <lib/utils_def.h>
+
+#define MMC_BLOCK_SIZE U(512)
+#define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - U(1))
+#define MMC_BOOT_CLK_RATE (400 * 1000)
+
+#define MMC_CMD(_x) U(_x)
+
+#define MMC_ACMD(_x) U(_x)
+
+#define OCR_POWERUP BIT(31)
+#define OCR_HCS BIT(30)
+#define OCR_BYTE_MODE (U(0) << 29)
+#define OCR_SECTOR_MODE (U(2) << 29)
+#define OCR_ACCESS_MODE_MASK (U(3) << 29)
+#define OCR_3_5_3_6 BIT(23)
+#define OCR_3_4_3_5 BIT(22)
+#define OCR_3_3_3_4 BIT(21)
+#define OCR_3_2_3_3 BIT(20)
+#define OCR_3_1_3_2 BIT(19)
+#define OCR_3_0_3_1 BIT(18)
+#define OCR_2_9_3_0 BIT(17)
+#define OCR_2_8_2_9 BIT(16)
+#define OCR_2_7_2_8 BIT(15)
+#define OCR_VDD_MIN_2V7 GENMASK(23, 15)
+#define OCR_VDD_MIN_2V0 GENMASK(14, 8)
+#define OCR_VDD_MIN_1V7 BIT(7)
+
+#define MMC_RSP_48 BIT(0)
+#define MMC_RSP_136 BIT(1) /* 136 bit response */
+#define MMC_RSP_CRC BIT(2) /* expect valid crc */
+#define MMC_RSP_CMD_IDX BIT(3) /* response contains cmd idx */
+#define MMC_RSP_BUSY BIT(4) /* device may be busy */
+
+/* JEDEC 4.51 chapter 6.12 */
+#define MMC_RESPONSE_R1 (MMC_RSP_48 | MMC_RSP_CMD_IDX | MMC_RSP_CRC)
+#define MMC_RESPONSE_R1B (MMC_RESPONSE_R1 | MMC_RSP_BUSY)
+#define MMC_RESPONSE_R2 (MMC_RSP_48 | MMC_RSP_136 | MMC_RSP_CRC)
+#define MMC_RESPONSE_R3 (MMC_RSP_48)
+#define MMC_RESPONSE_R4 (MMC_RSP_48)
+#define MMC_RESPONSE_R5 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
+#define MMC_RESPONSE_R6 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
+#define MMC_RESPONSE_R7 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
+
+/* Value randomly chosen for eMMC RCA, it should be > 1 */
+#define MMC_FIX_RCA 6
+#define RCA_SHIFT_OFFSET 16
+
+#define CMD_EXTCSD_PARTITION_CONFIG 179
+#define CMD_EXTCSD_BUS_WIDTH 183
+#define CMD_EXTCSD_HS_TIMING 185
+#define CMD_EXTCSD_PART_SWITCH_TIME 199
+#define CMD_EXTCSD_SEC_CNT 212
+#define CMD_EXTCSD_BOOT_SIZE_MULT 226
+
+#define EXT_CSD_PART_CONFIG_ACC_MASK GENMASK(2, 0)
+#define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3)
+#define PART_CFG_BOOT_PARTITION1_ACCESS (U(1) << 0)
+#define PART_CFG_BOOT_PARTITION_NO_ACCESS U(0)
+#define PART_CFG_BOOT_PART_EN_MASK GENMASK(5, 3)
+#define PART_CFG_BOOT_PART_EN_SHIFT 3
+#define PART_CFG_CURRENT_BOOT_PARTITION(x) (((x) & PART_CFG_BOOT_PART_EN_MASK) >> \
+ PART_CFG_BOOT_PART_EN_SHIFT)
+
+/* Values in EXT CSD register */
+#define MMC_BUS_WIDTH_1 U(0)
+#define MMC_BUS_WIDTH_4 U(1)
+#define MMC_BUS_WIDTH_8 U(2)
+#define MMC_BUS_WIDTH_DDR_4 U(5)
+#define MMC_BUS_WIDTH_DDR_8 U(6)
+#define MMC_BOOT_MODE_BACKWARD (U(0) << 3)
+#define MMC_BOOT_MODE_HS_TIMING (U(1) << 3)
+#define MMC_BOOT_MODE_DDR (U(2) << 3)
+
+#define EXTCSD_SET_CMD (U(0) << 24)
+#define EXTCSD_SET_BITS (U(1) << 24)
+#define EXTCSD_CLR_BITS (U(2) << 24)
+#define EXTCSD_WRITE_BYTES (U(3) << 24)
+#define EXTCSD_CMD(x) (((x) & 0xff) << 16)
+#define EXTCSD_VALUE(x) (((x) & 0xff) << 8)
+#define EXTCSD_CMD_SET_NORMAL U(1)
+
+#define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0)
+#define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3)
+#define CSD_TRAN_SPEED_MULT_SHIFT 3
+
+#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9)
+#define STATUS_READY_FOR_DATA BIT(8)
+#define STATUS_SWITCH_ERROR BIT(7)
+#define MMC_GET_STATE(x) (((x) >> 9) & 0xf)
+#define MMC_STATE_IDLE 0
+#define MMC_STATE_READY 1
+#define MMC_STATE_IDENT 2
+#define MMC_STATE_STBY 3
+#define MMC_STATE_TRAN 4
+#define MMC_STATE_DATA 5
+#define MMC_STATE_RCV 6
+#define MMC_STATE_PRG 7
+#define MMC_STATE_DIS 8
+#define MMC_STATE_BTST 9
+#define MMC_STATE_SLP 10
+
+#define MMC_FLAG_CMD23 (U(1) << 0)
+#define MMC_FLAG_SD_CMD6 (U(1) << 1)
+
+#define CMD8_CHECK_PATTERN U(0xAA)
+#define VHS_2_7_3_6_V BIT(8)
+
+#define SD_SCR_BUS_WIDTH_1 BIT(8)
+#define SD_SCR_BUS_WIDTH_4 BIT(10)
+
+#define SD_SWITCH_FUNC_CHECK 0U
+#define SD_SWITCH_FUNC_SWITCH BIT(31)
+#define SD_SWITCH_ALL_GROUPS_MASK GENMASK(23, 0)
+
+struct mmc_cmd {
+ unsigned int cmd_idx;
+ unsigned int cmd_arg;
+ unsigned int resp_type;
+ unsigned int resp_data[4];
+};
+
+struct mmc_ops {
+ void (*init)(void);
+ int (*send_cmd)(struct mmc_cmd *cmd);
+ int (*set_ios)(unsigned int clk, unsigned int width);
+ int (*prepare)(int lba, uintptr_t buf, size_t size);
+ int (*read)(int lba, uintptr_t buf, size_t size);
+ int (*write)(int lba, const uintptr_t buf, size_t size);
+};
+
+struct mmc_csd_emmc {
+ unsigned int not_used: 1;
+ unsigned int crc: 7;
+ unsigned int ecc: 2;
+ unsigned int file_format: 2;
+ unsigned int tmp_write_protect: 1;
+ unsigned int perm_write_protect: 1;
+ unsigned int copy: 1;
+ unsigned int file_format_grp: 1;
+
+ unsigned int reserved_1: 5;
+ unsigned int write_bl_partial: 1;
+ unsigned int write_bl_len: 4;
+ unsigned int r2w_factor: 3;
+ unsigned int default_ecc: 2;
+ unsigned int wp_grp_enable: 1;
+
+ unsigned int wp_grp_size: 5;
+ unsigned int erase_grp_mult: 5;
+ unsigned int erase_grp_size: 5;
+ unsigned int c_size_mult: 3;
+ unsigned int vdd_w_curr_max: 3;
+ unsigned int vdd_w_curr_min: 3;
+ unsigned int vdd_r_curr_max: 3;
+ unsigned int vdd_r_curr_min: 3;
+ unsigned int c_size_low: 2;
+
+ unsigned int c_size_high: 10;
+ unsigned int reserved_2: 2;
+ unsigned int dsr_imp: 1;
+ unsigned int read_blk_misalign: 1;
+ unsigned int write_blk_misalign: 1;
+ unsigned int read_bl_partial: 1;
+ unsigned int read_bl_len: 4;
+ unsigned int ccc: 12;
+
+ unsigned int tran_speed: 8;
+ unsigned int nsac: 8;
+ unsigned int taac: 8;
+ unsigned int reserved_3: 2;
+ unsigned int spec_vers: 4;
+ unsigned int csd_structure: 2;
+};
+
+struct mmc_csd_sd_v2 {
+ unsigned int not_used: 1;
+ unsigned int crc: 7;
+ unsigned int reserved_1: 2;
+ unsigned int file_format: 2;
+ unsigned int tmp_write_protect: 1;
+ unsigned int perm_write_protect: 1;
+ unsigned int copy: 1;
+ unsigned int file_format_grp: 1;
+
+ unsigned int reserved_2: 5;
+ unsigned int write_bl_partial: 1;
+ unsigned int write_bl_len: 4;
+ unsigned int r2w_factor: 3;
+ unsigned int reserved_3: 2;
+ unsigned int wp_grp_enable: 1;
+
+ unsigned int wp_grp_size: 7;
+ unsigned int sector_size: 7;
+ unsigned int erase_block_en: 1;
+ unsigned int reserved_4: 1;
+ unsigned int c_size_low: 16;
+
+ unsigned int c_size_high: 6;
+ unsigned int reserved_5: 6;
+ unsigned int dsr_imp: 1;
+ unsigned int read_blk_misalign: 1;
+ unsigned int write_blk_misalign: 1;
+ unsigned int read_bl_partial: 1;
+ unsigned int read_bl_len: 4;
+ unsigned int ccc: 12;
+
+ unsigned int tran_speed: 8;
+ unsigned int nsac: 8;
+ unsigned int taac: 8;
+ unsigned int reserved_6: 6;
+ unsigned int csd_structure: 2;
+};
+
+struct sd_switch_status {
+ unsigned short max_current;
+ unsigned short support_g6;
+ unsigned short support_g5;
+ unsigned short support_g4;
+ unsigned short support_g3;
+ unsigned short support_g2;
+ unsigned short support_g1;
+ unsigned char sel_g6_g5;
+ unsigned char sel_g4_g3;
+ unsigned char sel_g2_g1;
+ unsigned char data_struct_ver;
+ unsigned short busy_g6;
+ unsigned short busy_g5;
+ unsigned short busy_g4;
+ unsigned short busy_g3;
+ unsigned short busy_g2;
+ unsigned short busy_g1;
+ unsigned short reserved[17];
+};
+
+enum mmc_device_type {
+ MMC_IS_EMMC,
+ MMC_IS_SD,
+ MMC_IS_SD_HC,
+};
+
+struct mmc_device_info {
+ unsigned long long device_size; /* Size of device in bytes */
+ unsigned int block_size; /* Block size in bytes */
+ unsigned int max_bus_freq; /* Max bus freq in Hz */
+ unsigned int ocr_voltage; /* OCR voltage */
+ enum mmc_device_type mmc_dev_type; /* Type of MMC */
+};
+
+size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size);
+size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size);
+size_t mmc_erase_blocks(int lba, size_t size);
+int mmc_part_switch_current_boot(void);
+int mmc_part_switch_user(void);
+size_t mmc_boot_part_size(void);
+size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size);
+int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
+ unsigned int width, unsigned int flags,
+ struct mmc_device_info *device_info);
+
+#endif /* MMC_H */
diff --git a/include/drivers/nand.h b/include/drivers/nand.h
new file mode 100644
index 0000000..5e5607c
--- /dev/null
+++ b/include/drivers/nand.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DRIVERS_NAND_H
+#define DRIVERS_NAND_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+#include <lib/utils_def.h>
+
+#define PSEC_TO_MSEC(x) div_round_up((x), 1000000000ULL)
+
+struct ecc {
+ unsigned int mode; /* ECC mode NAND_ECC_MODE_{NONE|HW|ONDIE} */
+ unsigned int size; /* Data byte per ECC step */
+ unsigned int bytes; /* ECC bytes per step */
+ unsigned int max_bit_corr; /* Max correctible bits per ECC steps */
+};
+
+struct nand_device {
+ unsigned int block_size;
+ unsigned int page_size;
+ unsigned long long size;
+ unsigned int nb_planes;
+ unsigned int buswidth;
+ struct ecc ecc;
+ int (*mtd_block_is_bad)(unsigned int block);
+ int (*mtd_read_page)(struct nand_device *nand, unsigned int page,
+ uintptr_t buffer);
+};
+
+void plat_get_scratch_buffer(void **buffer_addr, size_t *buf_size);
+
+/*
+ * Read bytes from NAND device
+ *
+ * @offset: Byte offset to read from in device
+ * @buffer: [out] Bytes read from device
+ * @length: Number of bytes to read
+ * @length_read: [out] Number of bytes read from device
+ * Return: 0 on success, a negative errno on failure
+ */
+int nand_read(unsigned int offset, uintptr_t buffer, size_t length,
+ size_t *length_read);
+
+/*
+ * Look for an extra offset to be added in case of bad blocks
+ *
+ * @base: Base address of the area
+ * @offset: Byte offset to read from in device
+ * @extra_offset: [out] Extra offset to be added if bad blocks are found
+ * Return: 0 on success, a negative errno on failure
+ */
+int nand_seek_bb(uintptr_t base, unsigned int offset, size_t *extra_offset);
+
+/*
+ * Get NAND device instance
+ *
+ * Return: NAND device instance reference
+ */
+struct nand_device *get_nand_device(void);
+
+#endif /* DRIVERS_NAND_H */
diff --git a/include/drivers/nxp/auth/csf_hdr_parser/csf_hdr.h b/include/drivers/nxp/auth/csf_hdr_parser/csf_hdr.h
new file mode 100644
index 0000000..ae56d3b
--- /dev/null
+++ b/include/drivers/nxp/auth/csf_hdr_parser/csf_hdr.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef CSF_HDR_H
+#define CSF_HDR_H
+
+#include "caam.h"
+#include "hash.h"
+#include "rsa.h"
+
+/* Barker code size in bytes */
+#define CSF_BARKER_LEN 4 /* barker code length in ESBC uboot client */
+ /* header */
+
+#ifdef CSF_HDR_CH3
+struct csf_hdr {
+ uint8_t barker[CSF_BARKER_LEN]; /* 0x00 Barker code */
+ uint32_t srk_tbl_off; /* 0x04 SRK Table Offset */
+
+ struct {
+ uint8_t num_srk; /* 0x08 No. of keys */
+ uint8_t srk_sel; /* Key no. to be used */
+ uint8_t reserve; /* 0x0a rseerved */
+ } len_kr;
+ uint8_t ie_flag;
+
+ uint32_t uid_flag;
+
+ uint32_t psign; /* 0x10 signature offset */
+ uint32_t sign_len; /* 0x14 length of signature */
+
+ union {
+ struct {
+ uint32_t sg_table_offset; /* 0x18 SG Table Offset */
+ uint32_t sg_entries; /* 0x1c no of entries in SG */
+ } sg_isbc;
+ uint64_t img_addr; /* 64 bit pointer to ESBC Image */
+ };
+
+ union {
+ struct {
+ uint32_t img_size; /* ESBC client img size in bytes */
+ uint32_t ie_key_sel;
+ } img;
+ uint64_t entry_point; /* 0x20-0x24 ESBC entry point */
+ };
+
+ uint32_t fsl_uid_0; /* 0x28 Freescale unique id 0 */
+ uint32_t fsl_uid_1; /* 0x2c Freescale unique id 1 */
+ uint32_t oem_uid_0; /* 0x30 OEM unique id 0 */
+ uint32_t oem_uid_1; /* 0x34 OEM unique id 1 */
+ uint32_t oem_uid_2; /* 0x38 OEM unique id 2 */
+ uint32_t oem_uid_3; /* 0x3c OEM unique id 3 */
+ uint32_t oem_uid_4; /* 0x40 OEM unique id 4 */
+
+ uint32_t reserved[3]; /* 0x44 - 0x4f */
+};
+
+/* Srk table and key revocation check */
+#define UNREVOCABLE_KEY 8
+#define REVOC_KEY_ALIGN 7
+#define MAX_KEY_ENTRIES 8
+
+#else
+
+/* CSF header for Chassis 2 */
+struct csf_hdr {
+ uint8_t barker[CSF_BARKER_LEN]; /* barker code */
+ union {
+ uint32_t pkey; /* public key offset */
+ uint32_t srk_tbl_off;
+ };
+
+ union {
+ uint32_t key_len; /* pub key length in bytes */
+ struct {
+ uint32_t srk_table_flag:8;
+ uint32_t srk_sel:8;
+ uint32_t num_srk:16;
+ } len_kr;
+ };
+
+ uint32_t psign; /* signature offset */
+ uint32_t sign_len; /* length of the signature in bytes */
+
+ /* SG Table used by ISBC header */
+ union {
+ struct {
+ uint32_t sg_table_offset; /* 0x14 SG Table Offset */
+ uint32_t sg_entries; /* no of entries in SG table */
+ } sg_isbc;
+ struct {
+ uint32_t reserved1; /* Reserved field */
+ uint32_t img_size; /* ESBC img size in bytes */
+ } img;
+ };
+
+ uint32_t entry_point; /* ESBC client entry point */
+ uint32_t reserved2; /* Scatter gather flag */
+ uint32_t uid_flag;
+ uint32_t fsl_uid_0;
+ uint32_t oem_uid_0;
+ uint32_t reserved3[2];
+ uint32_t fsl_uid_1;
+ uint32_t oem_uid_1;
+
+ /* The entries below aren't present in ISBC header */
+ uint64_t img_addr; /* 64 bit pointer to ESBC Image */
+ uint32_t ie_flag;
+ uint32_t ie_key_sel;
+};
+
+/* Srk table and key revocation check */
+#define UNREVOCABLE_KEY 4
+#define REVOC_KEY_ALIGN 3
+#define MAX_KEY_ENTRIES 4
+
+#endif
+
+struct srk_table {
+ uint32_t key_len;
+ uint8_t pkey[2 * RSA_4K_KEY_SZ_BYTES];
+};
+
+/*
+ * This struct contains the following fields
+ * length of the segment
+ * Destination Target ID
+ * source address
+ * destination address
+ */
+struct sg_table {
+ uint32_t len; /* Length of Image */
+ uint32_t res1;
+ union {
+ uint64_t src_addr; /* SRC Address of Image */
+ struct {
+ uint32_t src_addr;
+ uint32_t dst_addr;
+ } img;
+ };
+};
+
+int validate_esbc_header(void *img_hdr, void **img_key, uint32_t *key_len,
+ void **img_sign, uint32_t *sign_len,
+ enum sig_alg *algo);
+
+int calc_img_hash(struct csf_hdr *hdr, void *img_addr, uint32_t img_size,
+ uint8_t *img_hash, uint32_t *hash_len);
+
+#endif
diff --git a/include/drivers/nxp/console/plat_console.h b/include/drivers/nxp/console/plat_console.h
new file mode 100644
index 0000000..8b1b23a
--- /dev/null
+++ b/include/drivers/nxp/console/plat_console.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_CONSOLE_H
+#define PLAT_CONSOLE_H
+
+#include <stdint.h>
+#include <drivers/console.h>
+
+#if (NXP_CONSOLE == NS16550)
+/*
+ * NXP specific UART - 16550 configuration
+ *
+ * Initialize a NXP 16550 console instance and register it with the console
+ * framework. The |console| pointer must point to storage that will be valid
+ * for the lifetime of the console, such as a global or static local variable.
+ * Its contents will be reinitialized from scratch.
+ * When |clock| has a value of 0, the UART will *not* be initialised. This
+ * means the UART should already be enabled and the baudrate and clock setup
+ * should have been done already, either by platform specific code or by
+ * previous firmware stages. The |baud| parameter will be ignored in this
+ * case as well.
+ */
+int nxp_console_16550_register(uintptr_t baseaddr, uint32_t clock,
+ uint32_t baud, console_t *console);
+#endif
+/*
+ * Function to initialize platform's console
+ * and register with console framework
+ */
+void plat_console_init(uintptr_t nxp_console_addr, uint32_t uart_clk_div,
+ uint32_t baud);
+
+#endif
diff --git a/include/drivers/nxp/crypto/caam/caam.h b/include/drivers/nxp/crypto/caam/caam.h
new file mode 100644
index 0000000..6cc1f3d
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/caam.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2017-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef CAAM_H
+#define CAAM_H
+
+#include "caam_io.h"
+#include "sec_jr_driver.h"
+
+
+/* Job ring 3 is reserved for usage by sec firmware */
+#define DEFAULT_JR 3
+
+#if defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_2)
+#define CAAM_JR0_OFFSET 0x10000
+#define CAAM_JR1_OFFSET 0x20000
+#define CAAM_JR2_OFFSET 0x30000
+#define CAAM_JR3_OFFSET 0x40000
+#endif
+
+enum sig_alg {
+ RSA,
+ ECC
+};
+
+/* This function does basic SEC Initialization */
+int sec_init(uintptr_t nxp_caam_addr);
+int config_sec_block(void);
+uintptr_t get_caam_addr(void);
+
+/* This function is used to submit jobs to JR */
+int run_descriptor_jr(struct job_descriptor *desc);
+
+/* This function is used to instatiate the HW RNG is already not instantiated */
+int hw_rng_instantiate(void);
+
+/* This function is used to return random bytes of byte_len from HW RNG */
+int get_rand_bytes_hw(uint8_t *bytes, int byte_len);
+
+/* This function is used to set the hw unique key from HW CAAM */
+int get_hw_unq_key_blob_hw(uint8_t *hw_key, int size);
+
+/* This function is used to fetch random number from
+ * CAAM of length either of 4 bytes or 8 bytes depending
+ * rngWidth value.
+ */
+unsigned long long get_random(int rngWidth);
+
+#endif /* CAAM_H */
diff --git a/include/drivers/nxp/crypto/caam/caam_io.h b/include/drivers/nxp/crypto/caam/caam_io.h
new file mode 100644
index 0000000..b68f836
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/caam_io.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef CAAM_IO_H
+#define CAAM_IO_H
+
+#include <endian.h>
+#include <lib/mmio.h>
+
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
+
+/* Return higher 32 bits of physical address */
+#define PHYS_ADDR_HI(phys_addr) \
+ (uint32_t)(((uint64_t)phys_addr) >> 32)
+
+/* Return lower 32 bits of physical address */
+#define PHYS_ADDR_LO(phys_addr) \
+ (uint32_t)(((uint64_t)phys_addr) & 0xFFFFFFFF)
+
+#ifdef NXP_SEC_BE
+#define sec_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define sec_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
+#define sec_in64(addr) ( \
+ ((uint64_t)sec_in32((uintptr_t)(addr)) << 32) | \
+ (sec_in32(((uintptr_t)(addr)) + 4)))
+#define sec_out64(addr, val) ({ \
+ sec_out32(((uintptr_t)(addr)), (uint32_t)((val) >> 32)); \
+ sec_out32(((uintptr_t)(addr)) + 4, (uint32_t)(val)); })
+#elif defined(NXP_SEC_LE)
+#define sec_in32(a) mmio_read_32((uintptr_t)(a))
+#define sec_out32(a, v) mmio_write_32((uintptr_t)(a), (v))
+#define sec_in64(addr) ( \
+ ((uint64_t)sec_in32((uintptr_t)(addr) + 4) << 32) | \
+ (sec_in32((uintptr_t)(addr))))
+#define sec_out64(addr, val) ({ \
+ sec_out32(((uintptr_t)(addr)) + 4, (uint32_t)((val) >> 32)); \
+ sec_out32(((uintptr_t)(addr)), (uint32_t)(val)); })
+#else
+#error Please define CCSR SEC register endianness
+#endif
+
+static inline void *ptov(phys_addr_t *ptr)
+{
+ return (void *)ptr;
+}
+
+static inline phys_addr_t *vtop(void *ptr)
+{
+ return (phys_addr_t *)ptr;
+}
+#endif /* CAAM_IO_H */
diff --git a/include/drivers/nxp/crypto/caam/hash.h b/include/drivers/nxp/crypto/caam/hash.h
new file mode 100644
index 0000000..9136dca
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/hash.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __HASH_H__
+#define __HASH_H__
+
+#include <stdbool.h>
+
+/* List of hash algorithms */
+enum hash_algo {
+ SHA1 = 0,
+ SHA256
+};
+
+/* number of bytes in the SHA256-256 digest */
+#define SHA256_DIGEST_SIZE 32
+
+/*
+ * number of words in the digest - Digest is kept internally
+ * as 8 32-bit words
+ */
+#define _SHA256_DIGEST_LENGTH 8
+
+/*
+ * block length - A block, treated as a sequence of
+ * 32-bit words
+ */
+#define SHA256_BLOCK_LENGTH 16
+
+/* number of bytes in the block */
+#define SHA256_DATA_SIZE 64
+
+#define MAX_SG 12
+
+struct sg_entry {
+#if defined(NXP_SEC_LE)
+ uint32_t addr_lo; /* Memory Address - lo */
+ uint32_t addr_hi; /* Memory Address of start of buffer - hi */
+#else
+ uint32_t addr_hi; /* Memory Address of start of buffer - hi */
+ uint32_t addr_lo; /* Memory Address - lo */
+#endif
+
+ uint32_t len_flag; /* Length of the data in the frame */
+#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
+#define SG_ENTRY_EXTENSION_BIT 0x80000000
+#define SG_ENTRY_FINAL_BIT 0x40000000
+ uint32_t bpid_offset;
+#define SG_ENTRY_BPID_MASK 0x00FF0000
+#define SG_ENTRY_BPID_SHIFT 16
+#define SG_ENTRY_OFFSET_MASK 0x00001FFF
+#define SG_ENTRY_OFFSET_SHIFT 0
+};
+
+/*
+ * SHA256-256 context
+ * contain the following fields
+ * State
+ * count low
+ * count high
+ * block data buffer
+ * index to the buffer
+ */
+struct hash_ctx {
+ struct sg_entry sg_tbl[MAX_SG];
+ uint32_t hash_desc[64];
+ uint8_t hash[SHA256_DIGEST_SIZE];
+ uint32_t sg_num;
+ uint32_t len;
+ uint8_t *data;
+ enum hash_algo algo;
+ bool active;
+};
+
+int hash_init(enum hash_algo algo, void **ctx);
+int hash_update(enum hash_algo algo, void *context, void *data_ptr,
+ unsigned int data_len);
+int hash_final(enum hash_algo algo, void *context, void *hash_ptr,
+ unsigned int hash_len);
+
+#endif
diff --git a/include/drivers/nxp/crypto/caam/jobdesc.h b/include/drivers/nxp/crypto/caam/jobdesc.h
new file mode 100644
index 0000000..efef228
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/jobdesc.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __JOBDESC_H
+#define __JOBDESC_H
+
+#include <rsa.h>
+
+#define DESC_LEN_MASK 0x7f
+#define DESC_START_SHIFT 16
+
+#define KEY_BLOB_SIZE 32
+#define MAC_SIZE 16
+
+#define KEY_IDNFR_SZ_BYTES 16
+#define CLASS_SHIFT 25
+#define CLASS_2 (0x02 << CLASS_SHIFT)
+
+#define CMD_SHIFT 27
+#define CMD_OPERATION (U(0x10) << CMD_SHIFT)
+
+#define OP_TYPE_SHIFT 24
+#define OP_TYPE_ENCAP_PROTOCOL (0x07 << OP_TYPE_SHIFT)
+
+/* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */
+#define OP_PCLID_SHIFT 16
+#define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT)
+
+#define BLOB_PROTO_INFO 0x00000002
+
+uint32_t desc_length(uint32_t *desc);
+
+int cnstr_rng_jobdesc(uint32_t *desc, uint32_t state_handle,
+ uint32_t *add_inp, uint32_t add_ip_len,
+ uint8_t *out_data, uint32_t len);
+
+int cnstr_rng_instantiate_jobdesc(uint32_t *desc);
+
+/* Construct descriptor to generate hw key blob */
+int cnstr_hw_encap_blob_jobdesc(uint32_t *desc,
+ uint8_t *key_idnfr, uint32_t key_sz,
+ uint32_t key_class, uint8_t *plain_txt,
+ uint32_t in_sz, uint8_t *enc_blob,
+ uint32_t out_sz, uint32_t operation);
+
+void cnstr_hash_jobdesc(uint32_t *desc, uint8_t *msg, uint32_t msgsz,
+ uint8_t *digest);
+
+void cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
+ struct pk_in_params *pkin, uint8_t *out,
+ uint32_t out_siz);
+#endif
diff --git a/include/drivers/nxp/crypto/caam/jr_driver_config.h b/include/drivers/nxp/crypto/caam/jr_driver_config.h
new file mode 100644
index 0000000..1b3c447
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/jr_driver_config.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _JR_DRIVER_CONFIG_H_
+#define _JR_DRIVER_CONFIG_H_
+
+/* Helper defines */
+
+ /* Define used for setting a flag on */
+#define ON 1
+ /* Define used for setting a flag off */
+#define OFF 0
+
+ /* SEC is configured to start work in polling mode, */
+#define SEC_STARTUP_POLLING_MODE 0
+/*
+ * SEC is configured to start work in interrupt mode,
+ * when configured for NAPI notification style.
+ */
+#define SEC_STARTUP_INTERRUPT_MODE 1
+
+/*
+ * SEC driver will use ONLY interrupts to receive notifications
+ * for processed packets from SEC engine hardware.
+ */
+#define SEC_NOTIFICATION_TYPE_IRQ 1
+/*
+ * SEC driver will use ONLY polling to receive notifications
+ * for processed packets from SEC engine hardware.
+ */
+#define SEC_NOTIFICATION_TYPE_POLL 2
+
+/*
+ * Determines how SEC user space driver will receive notifications
+ * for processed packets from SEC engine.
+ * Valid values are: #SEC_NOTIFICATION_TYPE_POLL, #SEC_NOTIFICATION_TYPE_IRQ
+ */
+#define SEC_NOTIFICATION_TYPE SEC_NOTIFICATION_TYPE_POLL
+
+ /* Maximum number of job rings supported by SEC hardware */
+#define MAX_SEC_JOB_RINGS 1
+
+/*
+ * Size of cryptographic context that is used directly in communicating
+ * with SEC device.
+ * SEC device works only with physical addresses. This is the maximum size
+ * for a SEC descriptor ( = 64 words).
+ */
+
+#define SEC_CRYPTO_DESCRIPTOR_SIZE 256
+
+/*
+ * Size of job descriptor submitted to SEC device for each packet to be
+ * processed.
+ * Job descriptor contains 3 DMA address pointers:
+ * - to shared descriptor, to input buffer and to output buffer.
+ * The job descriptor contains other SEC specific commands as well:
+ * - HEADER command, SEQ IN PTR command SEQ OUT PTR command and opaque
+ * data, each measuring 4 bytes.
+ * Job descriptor size, depending on physical address representation:
+ * - 32 bit - size is 28 bytes - cacheline-aligned size is 64 bytes
+ * - 36 bit - size is 40 bytes - cacheline-aligned size is 64 bytes
+ * @note: Job descriptor must be cacheline-aligned to ensure efficient memory
+ * access.
+ * @note: If other format is used for job descriptor, then the size must be
+ * revised.
+ */
+
+#define SEC_JOB_DESCRIPTOR_SIZE 64
+
+/*
+ * Size of one entry in the input ring of a job ring.
+ * Input ring contains pointers to job descriptors.
+ * The memory used for an input ring and output ring must be physically
+ * contiguous.
+ */
+
+#define SEC_JOB_INPUT_RING_ENTRY_SIZE sizeof(phys_addr_t)
+
+/*
+ * Size of one entry in the output ring of a job ring.
+ * Output ring entry is a pointer to a job descriptor followed by a 4 byte
+ * status word.
+ * The memory used for an input ring and output ring must be physically
+ * contiguous.
+ * @note If desired to use also the optional SEQ OUT indication in output
+ * ring entries, then 4 more bytes must be added to the size.
+ */
+
+#define SEC_JOB_OUTPUT_RING_ENTRY_SIZE (SEC_JOB_INPUT_RING_ENTRY_SIZE + 4)
+
+ /* DMA memory required for an input ring of a job ring. */
+#define SEC_DMA_MEM_INPUT_RING_SIZE \
+ ((SEC_JOB_INPUT_RING_ENTRY_SIZE) * (SEC_JOB_RING_SIZE))
+
+/*
+ * DMA memory required for an output ring of a job ring.
+ * Required extra 4 byte for status word per each entry.
+ */
+#define SEC_DMA_MEM_OUTPUT_RING_SIZE \
+ ((SEC_JOB_OUTPUT_RING_ENTRY_SIZE) * (SEC_JOB_RING_SIZE))
+
+ /* DMA memory required for descriptors of a job ring. */
+#define SEC_DMA_MEM_DESCRIPTORS \
+ ((SEC_CRYPTO_DESCRIPTOR_SIZE)*(SEC_JOB_RING_SIZE))
+
+ /* DMA memory required for a job ring, including both input output rings. */
+#define SEC_DMA_MEM_JOB_RING_SIZE \
+ ((SEC_DMA_MEM_INPUT_RING_SIZE) + \
+ (SEC_DMA_MEM_OUTPUT_RING_SIZE))
+
+/*
+ * When calling sec_init() UA will provide an area of virtual memory
+ * of size #SEC_DMA_MEMORY_SIZE to be used internally by the driver
+ * to allocate data (like SEC descriptors) that needs to be passed to
+ * SEC device in physical addressing and later on retrieved from SEC device.
+ * At initialization the UA provides specialized ptov/vtop functions/macros to
+ * translate addresses allocated from this memory area.
+ */
+#define SEC_DMA_MEMORY_SIZE \
+ ((SEC_DMA_MEM_JOB_RING_SIZE) * (MAX_SEC_JOB_RINGS))
+
+/*
+ * SEC DEVICE related configuration.
+
+ * Enable/Disable logging support at compile time.
+ * Valid values:
+ * ON - enable logging
+ * OFF - disable logging
+ * The messages are logged at stdout.
+ */
+
+#define SEC_DRIVER_LOGGING OFF
+
+/*
+ * Configure logging level at compile time.
+ * Valid values:
+ * SEC_DRIVER_LOG_ERROR - log only errors
+ * SEC_DRIVER_LOG_INFO - log errors and info messages
+ * SEC_DRIVER_LOG_DEBUG - log errors, info and debug messages
+ */
+
+#define SEC_DRIVER_LOGGING_LEVEL SEC_DRIVER_LOG_DEBUG
+
+/*
+ * SEC JOB RING related configuration.
+
+ * Configure the size of the JOB RING.
+ * The maximum size of the ring is hardware limited to 1024.
+ * However the number of packets in flight in a time interval of
+ * 1ms can be calculated
+ * from the traffic rate (Mbps) and packet size.
+ * Here it was considered a packet size of 40 bytes.
+ * @note Round up to nearest power of 2 for optimized update
+ * of producer/consumer indexes of each job ring
+ * \todo Should set to 750, according to the calculation above, but
+ * the JR size must be power of 2, thus the next closest value must
+ * be chosen (i.e. 512 since 1024 is not available)
+ * For firmware choose this to be 16
+ */
+
+#define SEC_JOB_RING_SIZE 16
+
+/*
+ * Interrupt coalescing related configuration.
+ * NOTE: SEC hardware enabled interrupt
+ * coalescing is not supported on SEC version 3.1!
+ * SEC version 4.4 has support for interrupt
+ * coalescing.
+ */
+
+#if SEC_NOTIFICATION_TYPE != SEC_NOTIFICATION_TYPE_POLL
+
+#define SEC_INT_COALESCING_ENABLE ON
+/*
+ * Interrupt Coalescing Descriptor Count Threshold.
+ * While interrupt coalescing is enabled (ICEN=1), this value determines
+ * how many Descriptors are completed before raising an interrupt.
+ * Valid values for this field are from 0 to 255.
+ * Note that a value of 1 functionally defeats the advantages of interrupt
+ * coalescing since the threshold value is reached each time that a
+ * Job Descriptor is completed. A value of 0 is treated in the same
+ * manner as a value of 1.
+ *
+ */
+#define SEC_INTERRUPT_COALESCING_DESCRIPTOR_COUNT_THRESH 10
+
+/*
+ * Interrupt Coalescing Timer Threshold.
+ * While interrupt coalescing is enabled (ICEN=1), this value determines the
+ * maximum amount of time after processing a Descriptor before raising an
+ * interrupt.
+ * The threshold value is represented in units equal to 64 CAAM interface
+ * clocks. Valid values for this field are from 1 to 65535.
+ * A value of 0 results in behavior identical to that when interrupt
+ * coalescing is disabled.
+ */
+#define SEC_INTERRUPT_COALESCING_TIMER_THRESH 100
+#endif /* SEC_NOTIFICATION_TYPE_POLL */
+
+#endif /* _JR_DRIVER_CONFIG_H_ */
diff --git a/include/drivers/nxp/crypto/caam/rsa.h b/include/drivers/nxp/crypto/caam/rsa.h
new file mode 100644
index 0000000..dd9ecdc
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/rsa.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _RSA_H__
+#define _RSA_H__
+
+/* RSA key size defines */
+#define RSA_4K_KEY_SZ 4096
+#define RSA_4K_KEY_SZ_BYTES (RSA_4K_KEY_SZ/8)
+#define RSA_2K_KEY_SZ 2048
+#define RSA_2K_KEY_SZ_BYTES (RSA_2K_KEY_SZ/8)
+#define RSA_1K_KEY_SZ 1024
+#define RSA_1K_KEY_SZ_BYTES (RSA_1K_KEY_SZ/8)
+
+#define SHA256_BYTES (256/8)
+
+struct pk_in_params {
+ uint8_t *e;
+ uint32_t e_siz;
+ uint8_t *n;
+ uint32_t n_siz;
+ uint8_t *a;
+ uint32_t a_siz;
+ uint8_t *b;
+ uint32_t b_siz;
+};
+
+struct rsa_context {
+ struct pk_in_params pkin;
+};
+
+int rsa_verify_signature(void *hash_ptr, unsigned int hash_len,
+ void *sig_ptr, unsigned int sig_len,
+ void *pk_ptr, unsigned int pk_len);
+
+#endif
diff --git a/include/drivers/nxp/crypto/caam/sec_hw_specific.h b/include/drivers/nxp/crypto/caam/sec_hw_specific.h
new file mode 100644
index 0000000..9800793
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/sec_hw_specific.h
@@ -0,0 +1,503 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _SEC_HW_SPECIFIC_H_
+#define _SEC_HW_SPECIFIC_H_
+
+#include "caam.h"
+#include "sec_jr_driver.h"
+
+ /* DEFINES AND MACROS */
+
+/* Used to retry resetting a job ring in SEC hardware. */
+#define SEC_TIMEOUT 100000
+
+/*
+ * Offset to the registers of a job ring.
+ *Is different for each job ring.
+ */
+#define CHAN_BASE(jr) ((phys_addr_t)(jr)->register_base_addr)
+
+#define unlikely(x) __builtin_expect(!!(x), 0)
+
+#define SEC_JOB_RING_IS_FULL(pi, ci, ring_max_size, ring_threshold) \
+ ((((pi) + 1 + ((ring_max_size) - (ring_threshold))) & \
+ (ring_max_size - 1)) == ((ci)))
+
+#define SEC_CIRCULAR_COUNTER(x, max) (((x) + 1) & (max - 1))
+
+ /* Struct representing various job ring registers */
+struct jobring_regs {
+#ifdef NXP_SEC_BE
+ unsigned int irba_h;
+ unsigned int irba_l;
+#else
+ unsigned int irba_l;
+ unsigned int irba_h;
+#endif
+ unsigned int rsvd1;
+ unsigned int irs;
+ unsigned int rsvd2;
+ unsigned int irsa;
+ unsigned int rsvd3;
+ unsigned int irja;
+#ifdef NXP_SEC_BE
+ unsigned int orba_h;
+ unsigned int orba_l;
+#else
+ unsigned int orba_l;
+ unsigned int orba_h;
+#endif
+ unsigned int rsvd4;
+ unsigned int ors;
+ unsigned int rsvd5;
+ unsigned int orjr;
+ unsigned int rsvd6;
+ unsigned int orsf;
+ unsigned int rsvd7;
+ unsigned int jrsta;
+ unsigned int rsvd8;
+ unsigned int jrint;
+ unsigned int jrcfg0;
+ unsigned int jrcfg1;
+ unsigned int rsvd9;
+ unsigned int irri;
+ unsigned int rsvd10;
+ unsigned int orwi;
+ unsigned int rsvd11;
+ unsigned int jrcr;
+};
+
+ /* Offsets representing common SEC Registers */
+#define SEC_REG_MCFGR_OFFSET 0x0004
+#define SEC_REG_SCFGR_OFFSET 0x000C
+#define SEC_REG_JR0ICIDR_MS_OFFSET 0x0010
+#define SEC_REG_JR0ICIDR_LS_OFFSET 0x0014
+#define SEC_REG_JR1ICIDR_MS_OFFSET 0x0018
+#define SEC_REG_JR1ICIDR_LS_OFFSET 0x001C
+#define SEC_REG_JR2ICIDR_MS_OFFSET 0x0020
+#define SEC_REG_JR2ICIDR_LS_OFFSET 0x0024
+#define SEC_REG_JR3ICIDR_MS_OFFSET 0x0028
+#define SEC_REG_JR3ICIDR_LS_OFFSET 0x002C
+#define SEC_REG_JRSTARTR_OFFSET 0x005C
+#define SEC_REG_CTPR_MS_OFFSET 0x0FA8
+
+ /* Offsets representing various RNG registers */
+#define RNG_REG_RTMCTL_OFFSET 0x0600
+#define RNG_REG_RTSDCTL_OFFSET 0x0610
+#define RNG_REG_RTFRQMIN_OFFSET 0x0618
+#define RNG_REG_RTFRQMAX_OFFSET 0x061C
+#define RNG_REG_RDSTA_OFFSET 0x06C0
+#define ALG_AAI_SH_SHIFT 4
+
+ /* SEC Registers Bitmasks */
+#define MCFGR_PS_SHIFT 16
+#define MCFGR_AWCACHE_SHIFT 8
+#define MCFGR_AWCACHE_MASK (0xF << MCFGR_AWCACHE_SHIFT)
+#define MCFGR_ARCACHE_SHIFT 12
+#define MCFGR_ARCACHE_MASK (0xF << MCFGR_ARCACHE_SHIFT)
+
+#define SCFGR_RNGSH0 0x00000200
+#define SCFGR_VIRT_EN 0x00008000
+
+#define JRICID_MS_LICID 0x80000000
+#define JRICID_MS_LAMTD 0x00020000
+#define JRICID_MS_AMTDT 0x00010000
+#define JRICID_MS_TZ 0x00008000
+#define JRICID_LS_SDID_MASK 0x00000FFF
+#define JRICID_LS_NSEQID_MASK 0x0FFF0000
+#define JRICID_LS_NSEQID_SHIFT 16
+#define JRICID_LS_SEQID_MASK 0x00000FFF
+
+#define JRSTARTR_STARTJR0 0x00000001
+#define JRSTARTR_STARTJR1 0x00000002
+#define JRSTARTR_STARTJR2 0x00000004
+#define JRSTARTR_STARTJR3 0x00000008
+
+#define CTPR_VIRT_EN_POR 0x00000002
+#define CTPR_VIRT_EN_INC 0x00000001
+
+ /* RNG RDSTA bitmask */
+#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
+#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
+ /* use von Neumann data in both entropy shifter and statistical checker */
+#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0
+ /* use raw data in both entropy shifter and statistical checker */
+#define RTMCTL_SAMP_MODE_RAW_ES_SC 1
+ /* use von Neumann data in entropy shifter, raw data in statistical checker */
+#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2
+ /* invalid combination */
+#define RTMCTL_SAMP_MODE_INVALID 3
+#define RTSDCTL_ENT_DLY_MIN 3200
+#define RTSDCTL_ENT_DLY_MAX 12800
+#define RTSDCTL_ENT_DLY_SHIFT 16
+#define RTSDCTL_ENT_DLY_MASK (U(0xffff) << RTSDCTL_ENT_DLY_SHIFT)
+#define RTFRQMAX_DISABLE (1 << 20)
+
+ /* Constants for error handling on job ring */
+#define JR_REG_JRINT_ERR_TYPE_SHIFT 8
+#define JR_REG_JRINT_ERR_ORWI_SHIFT 16
+#define JR_REG_JRINIT_JRE_SHIFT 1
+
+#define JRINT_JRE (1 << JR_REG_JRINIT_JRE_SHIFT)
+#define JRINT_ERR_WRITE_STATUS (1 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_BAD_INPUT_BASE (3 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_BAD_OUTPUT_BASE (4 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_WRITE_2_IRBA (5 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_WRITE_2_ORBA (6 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_RES_B4_HALT (7 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_REM_TOO_MANY (8 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_ADD_TOO_MANY (9 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_HALT_MASK 0x0C
+#define JRINT_ERR_HALT_INPROGRESS 0x04
+#define JRINT_ERR_HALT_COMPLETE 0x08
+
+#define JR_REG_JRCR_VAL_RESET 0x00000001
+
+#define JR_REG_JRCFG_LO_ICTT_SHIFT 0x10
+#define JR_REG_JRCFG_LO_ICDCT_SHIFT 0x08
+#define JR_REG_JRCFG_LO_ICEN_EN 0x02
+#define JR_REG_JRCFG_LO_IMSK_EN 0x01
+
+ /* Constants for Descriptor Processing errors */
+#define SEC_HW_ERR_SSRC_NO_SRC 0x00
+#define SEC_HW_ERR_SSRC_CCB_ERR 0x02
+#define SEC_HW_ERR_SSRC_JMP_HALT_U 0x03
+#define SEC_HW_ERR_SSRC_DECO 0x04
+#define SEC_HW_ERR_SSRC_JR 0x06
+#define SEC_HW_ERR_SSRC_JMP_HALT_COND 0x07
+
+#define SEC_HW_ERR_DECO_HFN_THRESHOLD 0xF1
+#define SEC_HW_ERR_CCB_ICV_CHECK_FAIL 0x0A
+
+ /* Macros for extracting error codes for the job ring */
+
+#define JR_REG_JRINT_ERR_TYPE_EXTRACT(value) \
+ ((value) & 0x00000F00)
+
+#define JR_REG_JRINT_ERR_ORWI_EXTRACT(value) \
+ (((value) & 0x3FFF0000) >> \
+ JR_REG_JRINT_ERR_ORWI_SHIFT)
+
+#define JR_REG_JRINT_JRE_EXTRACT(value) \
+ ((value) & JRINT_JRE)
+
+ /* Macros for manipulating JR registers */
+typedef struct {
+#ifdef NXP_SEC_BE
+ uint32_t high;
+ uint32_t low;
+#else
+ uint32_t low;
+ uint32_t high;
+#endif
+} ptr_addr_t;
+
+#if defined(CONFIG_PHYS_64BIT)
+#define sec_read_addr(a) sec_in64((a))
+#define sec_write_addr(a, v) sec_out64((a), (v))
+#else
+#define sec_read_addr(a) sec_in32((a))
+#define sec_write_addr(a, v) sec_out32((a), (v))
+#endif
+
+#define JR_REG(name, jr) (CHAN_BASE(jr) + JR_REG_##name##_OFFSET)
+#define JR_REG_LO(name, jr) (CHAN_BASE(jr) + JR_REG_##name##_OFFSET_LO)
+
+#define GET_JR_REG(name, jr) (sec_in32(JR_REG(name, (jr))))
+#define GET_JR_REG_LO(name, jr) (sec_in32(JR_REG_LO(name, (jr))))
+
+#define SET_JR_REG(name, jr, val) \
+ (sec_out32(JR_REG(name, (jr)), (val)))
+
+#define SET_JR_REG_LO(name, jr, val) \
+ (sec_out32(JR_REG_LO(name, (jr)), (val)))
+
+ /* STRUCTURES AND OTHER TYPEDEFS */
+ /* Lists the possible states for a job ring. */
+typedef enum sec_job_ring_state_e {
+ SEC_JOB_RING_STATE_STARTED, /* Job ring is initialized */
+ SEC_JOB_RING_STATE_RESET, /* Job ring reset is in progres */
+} sec_job_ring_state_t;
+
+struct sec_job_ring_t {
+ /*
+ * Consumer index for job ring (jobs array).
+ * @note: cidx and pidx are accessed from
+ * different threads.
+ * Place the cidx and pidx inside the structure
+ * so that they lay on different cachelines, to
+ * avoid false sharing between threads when the
+ * threads run on different cores!
+ */
+ uint32_t cidx;
+
+ /* Producer index for job ring (jobs array) */
+ uint32_t pidx;
+
+ /* Ring of input descriptors. Size of array is power of 2 to allow
+ * fast update of producer/consumer indexes with bitwise operations.
+ */
+ phys_addr_t *input_ring;
+
+ /* Ring of output descriptors. */
+ struct sec_outring_entry *output_ring;
+
+ /* The file descriptor used for polling for interrupts notifications */
+ uint32_t irq_fd;
+
+ /* Model used by SEC Driver to receive notifications from SEC.
+ * Can be either of the three:
+ * #SEC_NOTIFICATION_TYPE_IRQ or
+ * #SEC_NOTIFICATION_TYPE_POLL
+ */
+ uint32_t jr_mode;
+ /* Base address for SEC's register memory for this job ring. */
+ void *register_base_addr;
+ /* notifies if coelescing is enabled for the job ring */
+ uint8_t coalescing_en;
+ /* The state of this job ring */
+ sec_job_ring_state_t jr_state;
+};
+
+ /* Forward structure declaration */
+typedef struct sec_job_ring_t sec_job_ring_t;
+
+struct sec_outring_entry {
+ phys_addr_t desc; /* Pointer to completed descriptor */
+ uint32_t status; /* Status for completed descriptor */
+} __packed;
+
+ /* Lists the states possible for the SEC user space driver. */
+typedef enum sec_driver_state_e {
+ SEC_DRIVER_STATE_IDLE, /*< Driver not initialized */
+ SEC_DRIVER_STATE_STARTED, /*< Driver initialized and */
+ SEC_DRIVER_STATE_RELEASE, /*< Driver release is in progress */
+} sec_driver_state_t;
+
+ /* Union describing the possible error codes that */
+ /* can be set in the descriptor status word */
+
+union hw_error_code {
+ uint32_t error;
+ union {
+ struct {
+ uint32_t ssrc:4;
+ uint32_t ssed_val:28;
+ } __packed value;
+ struct {
+ uint32_t ssrc:4;
+ uint32_t res:28;
+ } __packed no_status_src;
+ struct {
+ uint32_t ssrc:4;
+ uint32_t jmp:1;
+ uint32_t res:11;
+ uint32_t desc_idx:8;
+ uint32_t cha_id:4;
+ uint32_t err_id:4;
+ } __packed ccb_status_src;
+ struct {
+ uint32_t ssrc:4;
+ uint32_t jmp:1;
+ uint32_t res:11;
+ uint32_t desc_idx:8;
+ uint32_t offset:8;
+ } __packed jmp_halt_user_src;
+ struct {
+ uint32_t ssrc:4;
+ uint32_t jmp:1;
+ uint32_t res:11;
+ uint32_t desc_idx:8;
+ uint32_t desc_err:8;
+ } __packed deco_src;
+ struct {
+ uint32_t ssrc:4;
+ uint32_t res:17;
+ uint32_t naddr:3;
+ uint32_t desc_err:8;
+ } __packed jr_src;
+ struct {
+ uint32_t ssrc:4;
+ uint32_t jmp:1;
+ uint32_t res:11;
+ uint32_t desc_idx:8;
+ uint32_t cond:8;
+ } __packed jmp_halt_cond_src;
+ } __packed error_desc;
+} __packed;
+
+ /* FUNCTION PROTOTYPES */
+
+/*
+ * @brief Initialize a job ring/channel in SEC device.
+ * Write configuration register/s to properly initialize a job ring.
+ *
+ * @param [in] job_ring The job ring
+ *
+ * @retval 0 for success
+ * @retval other for error
+ */
+int hw_reset_job_ring(sec_job_ring_t *job_ring);
+
+/*
+ * @brief Reset a job ring/channel in SEC device.
+ * Write configuration register/s to reset a job ring.
+ *
+ * @param [in] job_ring The job ring
+ *
+ * @retval 0 for success
+ * @retval -1 in case job ring reset failed
+ */
+int hw_shutdown_job_ring(sec_job_ring_t *job_ring);
+
+/*
+ * @brief Handle a job ring/channel error in SEC device.
+ * Identify the error type and clear error bits if required.
+ *
+ * @param [in] job_ring The job ring
+ * @param [in] sec_error_code error code as first read from SEC engine
+ */
+
+void hw_handle_job_ring_error(sec_job_ring_t *job_ring,
+ uint32_t sec_error_code);
+/*
+ * @brief Handle a job ring error in the device.
+ * Identify the error type and printout a explanatory
+ * messages.
+ *
+ * @param [in] job_ring The job ring
+ *
+ */
+
+int hw_job_ring_error(sec_job_ring_t *job_ring);
+
+/* @brief Set interrupt coalescing parameters on the Job Ring.
+ * @param [in] job_ring The job ring
+ * @param [in] irq_coalesing_timer
+ * Interrupt coalescing timer threshold.
+ * This value determines the maximum
+ * amount of time after processing a descriptor
+ * before raising an interrupt.
+ * @param [in] irq_coalescing_count
+ * Interrupt coalescing count threshold.
+ * This value determines how many descriptors
+ * are completed before raising an interrupt.
+ */
+
+int hw_job_ring_set_coalescing_param(sec_job_ring_t *job_ring,
+ uint16_t irq_coalescing_timer,
+ uint8_t irq_coalescing_count);
+
+/* @brief Enable interrupt coalescing on a job ring
+ * @param [in] job_ring The job ring
+ */
+
+int hw_job_ring_enable_coalescing(sec_job_ring_t *job_ring);
+
+/*
+ * @brief Disable interrupt coalescing on a job ring
+ * @param [in] job_ring The job ring
+ */
+
+int hw_job_ring_disable_coalescing(sec_job_ring_t *job_ring);
+
+/*
+ * @brief Poll the HW for already processed jobs in the JR
+ * and notify the available jobs to UA.
+ *
+ * @param [in] job_ring The job ring to poll.
+ * @param [in] limit The maximum number of jobs to notify.
+ * If set to negative value, all available
+ * jobs are notified.
+ *
+ * @retval >=0 for No of jobs notified to UA.
+ * @retval -1 for error
+ */
+
+int hw_poll_job_ring(struct sec_job_ring_t *job_ring, int32_t limit);
+
+/* @brief Poll the HW for already processed jobs in the JR
+ * and silently discard the available jobs or notify them to UA
+ * with indicated error code.
+
+ * @param [in,out] job_ring The job ring to poll.
+ * @param [in] do_notify Can be #TRUE or #FALSE.
+ * Indicates if descriptors to be discarded
+ * or notified to UA with given error_code.
+ * @param [in] error_code The detailed SEC error code.
+ * @param [out] notified_descs Number of notified descriptors.
+ * Can be NULL if do_notify is #FALSE
+ */
+void hw_flush_job_ring(struct sec_job_ring_t *job_ring,
+ uint32_t do_notify,
+ uint32_t error_code, uint32_t *notified_descs);
+
+/*
+ * @brief Flush job rings of any processed descs.
+ * The processed descs are silently dropped,
+ * WITHOUT being notified to UA.
+ */
+void flush_job_rings(void);
+
+/*
+ * @brief Handle desc that generated error in SEC engine.
+ * Identify the exact type of error and handle the error.
+ * Depending on the error type, the job ring could be reset.
+ * All descs that are submitted for processing on this job ring
+ * are notified to User Application with error status and detailed error code.
+
+ * @param [in] job_ring Job ring
+ * @param [in] sec_error_code Error code read from job ring's Channel
+ * Status Register
+ * @param [out] notified_descs Number of notified descs. Can be NULL if
+ * do_notify is #FALSE
+ * @param [out] do_driver_shutdown If set to #TRUE, then UA is returned code
+ * #SEC_PROCESSING_ERROR
+ * which is indication that UA must call
+ * sec_release() after this.
+ */
+void sec_handle_desc_error(struct sec_job_ring_t *job_ring,
+ uint32_t sec_error_code,
+ uint32_t *notified_descs,
+ uint32_t *do_driver_shutdown);
+
+/*
+ * @brief Release the software and hardware resources tied to a job ring.
+ * @param [in] job_ring The job ring
+ * @retval 0 for success
+ * @retval -1 for error
+ */
+int shutdown_job_ring(struct sec_job_ring_t *job_ring);
+
+/*
+ * @brief Enable irqs on associated job ring.
+ * @param [in] job_ring The job ring
+ * @retval 0 for success
+ * @retval -1 for error
+ */
+int jr_enable_irqs(struct sec_job_ring_t *job_ring);
+
+/*
+ * @brief Disable irqs on associated job ring.
+ * @param [in] job_ring The job ring
+ * @retval 0 for success
+ * @retval -1 for error
+ */
+int jr_disable_irqs(struct sec_job_ring_t *job_ring);
+
+ /*
+ * IRJA - Input Ring Jobs Added Register shows
+ * how many new jobs were added to the Input Ring.
+ */
+static inline void hw_enqueue_desc_on_job_ring(struct jobring_regs *regs,
+ int num)
+{
+ sec_out32(&regs->irja, num);
+}
+
+#endif /* _SEC_HW_SPECIFIC_H_ */
diff --git a/include/drivers/nxp/crypto/caam/sec_jr_driver.h b/include/drivers/nxp/crypto/caam/sec_jr_driver.h
new file mode 100644
index 0000000..57e0fa0
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/sec_jr_driver.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _JR_DRIVER_H_
+#define _JR_DRIVER_H_
+
+#include "jr_driver_config.h"
+
+/* The maximum size of a SEC descriptor, in WORDs (32 bits). */
+#define MAX_DESC_SIZE_WORDS 64
+
+#define CAAM_TIMEOUT 200000 /* ms */
+
+/* Return codes for JR user space driver APIs */
+typedef enum sec_return_code_e {
+ SEC_SUCCESS = 0,
+ SEC_INVALID_INPUT_PARAM,
+ SEC_OUT_OF_MEMORY,
+ SEC_DESCRIPTOR_IN_FLIGHT,
+ SEC_LAST_DESCRIPTOR_IN_FLIGHT,
+ SEC_PROCESSING_ERROR,
+ SEC_DESC_PROCESSING_ERROR,
+ SEC_JR_IS_FULL,
+ SEC_DRIVER_RELEASE_IN_PROGRESS,
+ SEC_DRIVER_ALREADY_INITIALIZED,
+ SEC_DRIVER_NOT_INITIALIZED,
+ SEC_JOB_RING_RESET_IN_PROGRESS,
+ SEC_RESET_ENGINE_FAILED,
+ SEC_ENABLE_IRQS_FAILED,
+ SEC_DISABLE_IRQS_FAILED,
+ SEC_RETURN_CODE_MAX_VALUE,
+} sec_return_code_t;
+
+/* STRUCTURES AND OTHER TYPEDEFS */
+
+/*
+ * @brief Function called by JR User Space driver to notify every processed
+ * descriptor.
+ *
+ * Callback provided by the User Application.
+ * Callback is invoked by JR User Space driver for each descriptor processed by
+ * SEC
+ * @param [in] status Status word indicating processing result for
+ * this descriptor.
+ * @param [in] arg Opaque data passed by User Application
+ * It is opaque from JR driver's point of view.
+ * @param [in] job_ring The job ring handle on which the processed
+ * descriptor word was enqueued
+ */
+typedef void (*user_callback) (uint32_t *desc, uint32_t status,
+ void *arg, void *job_ring);
+
+/*
+ * Structure encompassing a job descriptor which is to be processed
+ * by SEC. User should also initialise this structure with the callback
+ * function pointer which will be called by driver after recieving proccessed
+ * descriptor from SEC. User data is also passed in this data structure which
+ * will be sent as an argument to the user callback function.
+ */
+struct job_descriptor {
+ uint32_t desc[MAX_DESC_SIZE_WORDS];
+ void *arg;
+ user_callback callback;
+};
+
+/*
+ * @brief Initialize the JR User Space driver.
+ * This function will handle initialization of sec library
+ * along with registering platform specific callbacks,
+ * as well as local data initialization.
+ * Call once during application startup.
+ * @note Global SEC initialization is done in SEC kernel driver.
+ * @note The hardware IDs of the initialized Job Rings are opaque to the UA.
+ * The exact Job Rings used by this library are decided between SEC user
+ * space driver and SEC kernel driver. A static partitioning of Job Rings is
+ * assumed, configured in DTS(device tree specification) file.
+ * @param [in] platform_cb Registering the platform specific
+ * callbacks with driver
+ * @retval ::0 for successful execution
+ * @retval ::-1 failure
+ */
+int sec_jr_lib_init(void);
+
+/*
+ * @brief Initialize the software and hardware resources tied to a job ring.
+ * @param [in] jr_mode; Model to be used by SEC Driver to receive
+ * notifications from SEC. Can be either
+ * SEC_NOTIFICATION_TYPE_IRQ or
+ * SEC_NOTIFICATION_TYPE_POLL
+ * @param [in] irq_coalescing_timer This value determines the maximum
+ * amount of time after processing a
+ * descriptor before raising an interrupt.
+ * @param [in] irq_coalescing_count This value determines how many
+ * descriptors are completed before
+ * raising an interrupt.
+ * @param [in] reg_base_addr The job ring base address register
+ * @param [in] irq_id The job ring interrupt identification number.
+ * @retval job_ring_handle for successful job ring configuration
+ * @retval NULL on error
+ */
+void *init_job_ring(uint8_t jr_mode,
+ uint16_t irq_coalescing_timer,
+ uint8_t irq_coalescing_count,
+ void *reg_base_addr, uint32_t irq_id);
+
+/*
+ * @brief Release the resources used by the JR User Space driver.
+ * Reset and release SEC's job rings indicated by the User Application at
+ * init_job_ring() and free any memory allocated internally.
+ * Call once during application tear down.
+ * @note In case there are any descriptors in-flight (descriptors received by
+ * JR driver for processing and for which no response was yet provided to UA),
+ * the descriptors are discarded without any notifications to User Application.
+ * @retval ::0 is returned for a successful execution
+ * @retval ::-1 is returned if JR driver release is in progress
+ */
+int sec_release(void);
+
+/*
+ * @brief Submit a descriptor for SEC processing.
+ * This function creates a "job" which is meant to instruct SEC HW
+ * to perform the processing on the input buffer. The "job" is enqueued
+ * in the Job Ring associated. The function will return after the "job"
+ * enqueue is finished. The function will not wait for SEC to
+ * start or/and finish the "job" processing.
+ * After the processing is finished the SEC HW writes the processing result
+ * to the provided output buffer.
+ * The Caller must poll JR driver using jr_dequeue()
+ * to receive notifications of the processing completion
+ * status. The notifications are received by caller by means of callback
+ * (see ::user_callback).
+ * @param [in] job_ring_handle The handle of the job ring on which
+ * descriptor is to be enqueued
+ * @param [in] job_descriptor The job descriptor structure of type
+ * struct job_descriptor. This structure
+ * should be filled with job descriptor along
+ * with callback function to be called after
+ * processing of descriptor and some
+ * opaque data passed to be passed to the
+ * callback function
+ *
+ * @retval ::0 is returned for successful execution
+ * @retval ::-1 is returned if there is some enqueue failure
+ */
+int enq_jr_desc(void *job_ring_handle, struct job_descriptor *jobdescr);
+
+/*
+ * @brief Polls for available descriptors processed by SEC on a specific
+ * Job Ring
+ * This function polls the SEC Job Rings and delivers processed descriptors
+ * Each processed descriptor has a user_callback registered.
+ * This user_callback is invoked for each processed descriptor.
+ * The polling is stopped when "limit" descriptors are notified or when
+ * there are no more descriptors to notify.
+ * @note The dequeue_jr() API cannot be called from within a user_callback
+ * function
+ * @param [in] job_ring_handle The Job Ring handle.
+ * @param [in] limit This value represents the maximum number
+ * of processed descriptors that can be
+ * notified API call on this Job Ring.
+ * Note that fewer descriptors may be notified
+ * if enough processed descriptors are not
+ * available.
+ * If limit has a negative value, then all
+ * ready descriptors will be notified.
+ *
+ * @retval :: >=0 is returned where retval is the total
+ * Number of descriptors notified
+ * during this function call.
+ * @retval :: -1 is returned in case of some error
+ */
+int dequeue_jr(void *job_ring_handle, int32_t limit);
+
+#endif /* _JR_DRIVER_H_ */
diff --git a/include/drivers/nxp/csu/csu.h b/include/drivers/nxp/csu/csu.h
new file mode 100644
index 0000000..83f1834
--- /dev/null
+++ b/include/drivers/nxp/csu/csu.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef CSU_H
+#define CSU_H
+
+#define CSU_SEC_ACCESS_REG_OFFSET (0x0021CU)
+/* Bit mask */
+#define TZASC_BYPASS_MUX_DISABLE (0x4U)
+
+/* Macros defining access permissions to configure
+ * the regions controlled by Central Security Unit.
+ */
+enum csu_cslx_access {
+ CSU_NS_SUP_R = (0x8U),
+ CSU_NS_SUP_W = (0x80U),
+ CSU_NS_SUP_RW = (0x88U),
+ CSU_NS_USER_R = (0x4U),
+ CSU_NS_USER_W = (0x40U),
+ CSU_NS_USER_RW = (0x44U),
+ CSU_S_SUP_R = (0x2U),
+ CSU_S_SUP_W = (0x20U),
+ CSU_S_SUP_RW = (0x22U),
+ CSU_S_USER_R = (0x1U),
+ CSU_S_USER_W = (0x10U),
+ CSU_S_USER_RW = (0x11U),
+ CSU_ALL_RW = (0xffU),
+};
+
+struct csu_ns_dev_st {
+ uintptr_t ind;
+ uint32_t val;
+};
+
+void enable_layerscape_ns_access(struct csu_ns_dev_st *csu_ns_dev,
+ uint32_t num, uintptr_t nxp_csu_addr);
+
+#endif
diff --git a/include/drivers/nxp/dcfg/dcfg.h b/include/drivers/nxp/dcfg/dcfg.h
new file mode 100644
index 0000000..cf29b12
--- /dev/null
+++ b/include/drivers/nxp/dcfg/dcfg.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DCFG_H
+#define DCFG_H
+
+#include <endian.h>
+
+#if defined(CONFIG_CHASSIS_2)
+#include <dcfg_lsch2.h>
+#elif defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_3)
+#include <dcfg_lsch3.h>
+#endif
+
+#ifdef NXP_GUR_BE
+#define gur_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
+#elif defined(NXP_GUR_LE)
+#define gur_in32(a) mmio_read_32((uintptr_t)(a))
+#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), v)
+#else
+#error Please define CCSR GUR register endianness
+#endif
+
+typedef struct {
+ union {
+ uint32_t val;
+ struct {
+ uint32_t min_ver:4;
+ uint32_t maj_ver:4;
+#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2)
+ uint32_t personality:6;
+ uint32_t rsv1:2;
+#elif defined(CONFIG_CHASSIS_2)
+ uint32_t personality:8;
+
+#endif
+#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2)
+ uint32_t dev_id:6;
+ uint32_t rsv2:2;
+ uint32_t family:4;
+#elif defined(CONFIG_CHASSIS_2)
+ uint32_t dev_id:12;
+#endif
+ uint32_t mfr_id;
+ } __packed bf;
+ struct {
+ uint32_t maj_min:8;
+ uint32_t version; /* SoC version without major and minor info */
+ } __packed bf_ver;
+ } __packed svr_reg;
+ bool sec_enabled;
+ bool is_populated;
+} soc_info_t;
+
+typedef struct {
+ bool is_populated;
+ uint8_t ocram_present;
+ uint8_t ddrc1_present;
+#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2)
+ uint8_t ddrc2_present;
+#endif
+} devdisr5_info_t;
+
+typedef struct {
+ uint32_t porsr1;
+ uintptr_t g_nxp_dcfg_addr;
+ unsigned long nxp_sysclk_freq;
+ unsigned long nxp_ddrclk_freq;
+ unsigned int nxp_plat_clk_divider;
+} dcfg_init_info_t;
+
+
+struct sysinfo {
+ unsigned long freq_platform;
+ unsigned long freq_ddr_pll0;
+ unsigned long freq_ddr_pll1;
+};
+
+int get_clocks(struct sysinfo *sys);
+
+/* Read the PORSR1 register */
+uint32_t read_reg_porsr1(void);
+
+/*******************************************************************************
+ * Returns true if secur eboot is enabled on board
+ * mode = 0 (development mode - sb_en = 1)
+ * mode = 1 (production mode - ITS = 1)
+ ******************************************************************************/
+bool check_boot_mode_secure(uint32_t *mode);
+
+const soc_info_t *get_soc_info();
+const devdisr5_info_t *get_devdisr5_info();
+
+void dcfg_init(dcfg_init_info_t *dcfg_init_data);
+bool is_sec_enabled(void);
+
+void error_handler(int error_code);
+#endif /* DCFG_H */
diff --git a/include/drivers/nxp/dcfg/dcfg_lsch2.h b/include/drivers/nxp/dcfg/dcfg_lsch2.h
new file mode 100644
index 0000000..882ba5a
--- /dev/null
+++ b/include/drivers/nxp/dcfg/dcfg_lsch2.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DCFG_LSCH2_H
+#define DCFG_LSCH2_H
+
+/* dcfg block register offsets and bitfields */
+#define DCFG_PORSR1_OFFSET 0x00
+#define DCFG_DEVDISR1_OFFSET 0x070
+#define DCFG_DEVDISR2_OFFSET 0x074
+#define DCFG_DEVDISR3_OFFSET 0x078
+#define DCFG_DEVDISR4_OFFSET 0x07C
+#define DCFG_DEVDISR5_OFFSET 0x080
+#define DCFG_COREDISR_OFFSET 0x094
+#define RCWSR0_OFFSET 0x100
+#define RCWSR5_OFFSET 0x118
+#define DCFG_BOOTLOCPTRL_OFFSET 0x400
+#define DCFG_BOOTLOCPTRH_OFFSET 0x404
+#define DCFG_COREDISABLEDSR_OFFSET 0x990
+#define DCFG_SCRATCH4_OFFSET 0x20C
+#define DCFG_SVR_OFFSET 0x0A4
+#define DCFG_BRR_OFFSET 0x0E4
+
+#define DCFG_RSTCR_OFFSET 0x0B0
+#define RSTCR_RESET_REQ 0x2
+
+#define DCFG_RSTRQSR1_OFFSET 0x0C8
+#define DCFG_RSTRQMR1_OFFSET 0x0C0
+
+/* PORSR1 bit mask */
+#define PORSR1_RCW_MASK 0xff800000
+#define PORSR1_RCW_SHIFT 23
+
+/* DCFG DCSR Macros */
+#define DCFG_DCSR_PORCR1_OFFSET 0x0
+
+#define SVR_MFR_ID_MASK 0xF0000000
+#define SVR_MFR_ID_SHIFT 28
+#define SVR_DEV_ID_MASK 0xFFF0000
+#define SVR_DEV_ID_SHIFT 16
+#define SVR_PERSONALITY_MASK 0xFF00
+#define SVR_PERSONALITY_SHIFT 8
+#define SVR_SEC_MASK 0x100
+#define SVR_SEC_SHIFT 8
+#define SVR_MAJ_VER_MASK 0xF0
+#define SVR_MAJ_VER_SHIFT 4
+#define SVR_MIN_VER_MASK 0xF
+#define SVR_MINOR_VER_0 0x00
+#define SVR_MINOR_VER_1 0x01
+
+#define DISR5_DDRC1_MASK 0x1
+#define DISR5_OCRAM_MASK 0x40
+
+/* DCFG regsiters bit masks */
+#define RCWSR0_SYS_PLL_RAT_SHIFT 25
+#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
+#define RCWSR0_MEM_PLL_RAT_SHIFT 16
+#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
+#define RCWSR0_MEM2_PLL_RAT_SHIFT 18
+#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f
+
+#define RCWSR_SB_EN_OFFSET RCWSR5_OFFSET
+#define RCWSR_SBEN_MASK 0x1
+#define RCWSR_SBEN_SHIFT 21
+
+/* RCW SRC NAND */
+#define RCW_SRC_NAND_MASK (0x100)
+#define RCW_SRC_NAND_VAL (0x100)
+#define NAND_RESERVED_MASK (0xFC)
+#define NAND_RESERVED_1 (0x0)
+#define NAND_RESERVED_2 (0x80)
+
+/* RCW SRC NOR */
+#define RCW_SRC_NOR_MASK (0x1F0)
+#define NOR_8B_VAL (0x10)
+#define NOR_16B_VAL (0x20)
+#define SD_VAL (0x40)
+#define QSPI_VAL1 (0x44)
+#define QSPI_VAL2 (0x45)
+
+#endif /* DCFG_LSCH2_H */
diff --git a/include/drivers/nxp/dcfg/dcfg_lsch3.h b/include/drivers/nxp/dcfg/dcfg_lsch3.h
new file mode 100644
index 0000000..cde86fe
--- /dev/null
+++ b/include/drivers/nxp/dcfg/dcfg_lsch3.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DCFG_LSCH3_H
+#define DCFG_LSCH3_H
+
+/* dcfg block register offsets and bitfields */
+#define DCFG_PORSR1_OFFSET 0x00
+
+#define DCFG_DEVDISR1_OFFSET 0x70
+#define DCFG_DEVDISR1_SEC (1 << 22)
+
+#define DCFG_DEVDISR2_OFFSET 0x74
+
+#define DCFG_DEVDISR3_OFFSET 0x78
+#define DCFG_DEVDISR3_QBMAIN (1 << 12)
+
+#define DCFG_DEVDISR4_OFFSET 0x7C
+#define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5)
+
+#define DCFG_DEVDISR5_OFFSET 0x80
+#define DISR5_DDRC1_MASK 0x1
+#define DISR5_DDRC2_MASK 0x2
+#define DISR5_OCRAM_MASK 0x1000
+#define DEVDISR5_MASK_ALL_MEM 0x00001003
+#define DEVDISR5_MASK_DDR 0x00000003
+#define DEVDISR5_MASK_DBG 0x00000400
+
+#define DCFG_DEVDISR6_OFFSET 0x84
+//#define DEVDISR6_MASK 0x00000001
+
+#define DCFG_COREDISR_OFFSET 0x94
+
+#define DCFG_SVR_OFFSET 0x0A4
+#define SVR_MFR_ID_MASK 0xF0000000
+#define SVR_MFR_ID_SHIFT 28
+#define SVR_FAMILY_MASK 0xF000000
+#define SVR_FAMILY_SHIFT 24
+#define SVR_DEV_ID_MASK 0x3F0000
+#define SVR_DEV_ID_SHIFT 16
+#define SVR_PERSONALITY_MASK 0x3E00
+#define SVR_PERSONALITY_SHIFT 9
+#define SVR_SEC_MASK 0x100
+#define SVR_SEC_SHIFT 8
+#define SVR_MAJ_VER_MASK 0xF0
+#define SVR_MAJ_VER_SHIFT 4
+#define SVR_MIN_VER_MASK 0xF
+
+#define RCWSR0_OFFSET 0x100
+#define RCWSR0_SYS_PLL_RAT_SHIFT 2
+#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
+#define RCWSR0_MEM_PLL_RAT_SHIFT 10
+#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
+#define RCWSR0_MEM2_PLL_RAT_SHIFT 18
+#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f
+
+#define RCWSR5_OFFSET 0x110
+#define RCWSR9_OFFSET 0x120
+#define RCWSR_SB_EN_OFFSET RCWSR9_OFFSET
+#define RCWSR_SBEN_MASK 0x1
+#define RCWSR_SBEN_SHIFT 10
+
+#define RCW_SR27_OFFSET 0x168
+/* DCFG register to dump error code */
+#define DCFG_SCRATCH4_OFFSET 0x20C
+#define DCFG_SCRATCHRW5_OFFSET 0x210
+#define DCFG_SCRATCHRW6_OFFSET 0x214
+#define DCFG_SCRATCHRW7_OFFSET 0x218
+#define DCFG_BOOTLOCPTRL_OFFSET 0x400
+#define DCFG_BOOTLOCPTRH_OFFSET 0x404
+#define DCFG_COREDISABLEDSR_OFFSET 0x990
+
+/* Reset module bit field */
+#define RSTCR_RESET_REQ 0x2
+
+#endif /* DCFG_LSCH3_H */
diff --git a/include/drivers/nxp/dcfg/scfg.h b/include/drivers/nxp/dcfg/scfg.h
new file mode 100644
index 0000000..8067de1
--- /dev/null
+++ b/include/drivers/nxp/dcfg/scfg.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SCFG_H
+#define SCFG_H
+
+#ifdef CONFIG_CHASSIS_2
+
+/* SCFG register offsets */
+#define SCFG_CORE0_SFT_RST_OFFSET 0x0130
+#define SCFG_SNPCNFGCR_OFFSET 0x01A4
+#define SCFG_CORESRENCR_OFFSET 0x0204
+#define SCFG_RVBAR0_0_OFFSET 0x0220
+#define SCFG_RVBAR0_1_OFFSET 0x0224
+#define SCFG_COREBCR_OFFSET 0x0680
+#define SCFG_RETREQCR_OFFSET 0x0424
+
+#define SCFG_COREPMCR_OFFSET 0x042C
+#define COREPMCR_WFIL2 0x1
+
+#define SCFG_GIC400_ADDR_ALIGN_OFFSET 0x0188
+#define SCFG_BOOTLOCPTRH_OFFSET 0x0600
+#define SCFG_BOOTLOCPTRL_OFFSET 0x0604
+#define SCFG_SCRATCHRW2_OFFSET 0x0608
+#define SCFG_SCRATCHRW3_OFFSET 0x060C
+
+/* SCFG bit fields */
+#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
+#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
+
+/* GIC Address Align Register */
+#define SCFG_GIC400_ADDR_ALIGN_4KMODE_MASK 0x80000000
+#define SCFG_GIC400_ADDR_ALIGN_4KMODE_EN 0x80000000
+#define SCFG_GIC400_ADDR_ALIGN_4KMODE_DIS 0x0
+
+#endif /* CONFIG_CHASSIS_2 */
+
+#ifndef __ASSEMBLER__
+#include <endian.h>
+#include <lib/mmio.h>
+
+#ifdef NXP_SCFG_BE
+#define scfg_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
+#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v)
+#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v)
+#define scfg_clrsetbits32(a, clear, set) \
+ mmio_clrsetbits_32((uintptr_t)(a), clear, set)
+#elif defined(NXP_SCFG_LE)
+#define scfg_in32(a) mmio_read_32((uintptr_t)(a))
+#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), v)
+#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v)
+#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v)
+#define scfg_clrsetbits32(a, clear, set) \
+ mmio_clrsetbits_32((uintptr_t)(a), clear, set)
+#else
+#error Please define CCSR SCFG register endianness
+#endif
+#endif /* __ASSEMBLER__ */
+
+#endif /* SCFG_H */
diff --git a/include/drivers/nxp/ddr/ddr.h b/include/drivers/nxp/ddr/ddr.h
new file mode 100644
index 0000000..0ef2870
--- /dev/null
+++ b/include/drivers/nxp/ddr/ddr.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_H
+#define DDR_H
+
+#include "ddr_io.h"
+#include "dimm.h"
+#include "immap.h"
+
+#ifndef DDRC_NUM_CS
+#define DDRC_NUM_CS 4
+#endif
+
+/*
+ * This is irrespective of what is the number of DDR controller,
+ * number of DIMM used. This is set to maximum
+ * Max controllers = 2
+ * Max num of DIMM per controlle = 2
+ * MAX NUM CS = 4
+ * Not to be changed.
+ */
+#define MAX_DDRC_NUM 2
+#define MAX_DIMM_NUM 2
+#define MAX_CS_NUM 4
+
+#include "opts.h"
+#include "regs.h"
+#include "utility.h"
+
+#ifdef DDR_DEBUG
+#define debug(...) INFO(__VA_ARGS__)
+#else
+#define debug(...) VERBOSE(__VA_ARGS__)
+#endif
+
+#ifndef DDRC_NUM_DIMM
+#define DDRC_NUM_DIMM 1
+#endif
+
+#define CONFIG_CS_PER_SLOT \
+ (DDRC_NUM_CS / DDRC_NUM_DIMM)
+
+/* Record of register values computed */
+struct ddr_cfg_regs {
+ struct {
+ unsigned int bnds;
+ unsigned int config;
+ unsigned int config_2;
+ } cs[MAX_CS_NUM];
+ unsigned int dec[10];
+ unsigned int timing_cfg[10];
+ unsigned int sdram_cfg[3];
+ unsigned int sdram_mode[16];
+ unsigned int md_cntl;
+ unsigned int interval;
+ unsigned int data_init;
+ unsigned int clk_cntl;
+ unsigned int init_addr;
+ unsigned int init_ext_addr;
+ unsigned int zq_cntl;
+ unsigned int wrlvl_cntl[3];
+ unsigned int ddr_sr_cntr;
+ unsigned int sdram_rcw[6];
+ unsigned int dq_map[4];
+ unsigned int eor;
+ unsigned int cdr[2];
+ unsigned int err_disable;
+ unsigned int err_int_en;
+ unsigned int tx_cfg[4];
+ unsigned int debug[64];
+};
+
+struct ddr_conf {
+ int dimm_in_use[MAX_DIMM_NUM];
+ int cs_in_use; /* bitmask, bit 0 for cs0, bit 1 for cs1, etc. */
+ int cs_on_dimm[MAX_DIMM_NUM]; /* bitmask */
+ unsigned long long cs_base_addr[MAX_CS_NUM];
+ unsigned long long cs_size[MAX_CS_NUM];
+ unsigned long long base_addr;
+ unsigned long long total_mem;
+};
+
+struct ddr_info {
+ unsigned long clk;
+ unsigned long long mem_base;
+ unsigned int num_ctlrs;
+ unsigned int dimm_on_ctlr;
+ struct dimm_params dimm;
+ struct memctl_opt opt;
+ struct ddr_conf conf;
+ struct ddr_cfg_regs ddr_reg;
+ struct ccsr_ddr *ddr[MAX_DDRC_NUM];
+ uint16_t *phy[MAX_DDRC_NUM];
+ int *spd_addr;
+ unsigned int ip_rev;
+ uintptr_t phy_gen2_fw_img_buf;
+ void *img_loadr;
+ int warm_boot_flag;
+};
+
+struct rc_timing {
+ unsigned int speed_bin;
+ unsigned int clk_adj;
+ unsigned int wrlvl;
+};
+
+struct board_timing {
+ unsigned int rc;
+ struct rc_timing const *p;
+ unsigned int add1;
+ unsigned int add2;
+};
+
+enum warm_boot {
+ DDR_COLD_BOOT = 0,
+ DDR_WARM_BOOT = 1,
+ DDR_WRM_BOOT_NT_SUPPORTED = -1,
+};
+
+int disable_unused_ddrc(struct ddr_info *priv, int mask,
+ uintptr_t nxp_ccn_hn_f0_addr);
+int ddr_board_options(struct ddr_info *priv);
+int compute_ddrc(const unsigned long clk,
+ const struct memctl_opt *popts,
+ const struct ddr_conf *conf,
+ struct ddr_cfg_regs *ddr,
+ const struct dimm_params *dimm_params,
+ const unsigned int ip_rev);
+int compute_ddr_phy(struct ddr_info *priv);
+int ddrc_set_regs(const unsigned long clk,
+ const struct ddr_cfg_regs *regs,
+ const struct ccsr_ddr *ddr,
+ int twopass);
+int cal_board_params(struct ddr_info *priv,
+ const struct board_timing *dimm,
+ int len);
+/* return bit mask of used DIMM(s) */
+int ddr_get_ddr_params(struct dimm_params *pdimm, struct ddr_conf *conf);
+long long dram_init(struct ddr_info *priv
+#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
+ , uintptr_t nxp_ccn_hn_f0_addr
+#endif
+ );
+long long board_static_ddr(struct ddr_info *info);
+
+#endif /* DDR_H */
diff --git a/include/drivers/nxp/ddr/ddr_io.h b/include/drivers/nxp/ddr/ddr_io.h
new file mode 100644
index 0000000..fbd7e97
--- /dev/null
+++ b/include/drivers/nxp/ddr/ddr_io.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_IO_H
+#define DDR_IO_H
+
+#include <endian.h>
+
+#include <lib/mmio.h>
+
+#define min(a, b) (((a) > (b)) ? (b) : (a))
+
+#define max(a, b) (((a) > (b)) ? (a) : (b))
+
+/* macro for memory barrier */
+#define mb() asm volatile("dsb sy" : : : "memory")
+
+#ifdef NXP_DDR_BE
+#define ddr_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define ddr_out32(a, v) mmio_write_32((uintptr_t)(a),\
+ bswap32(v))
+#elif defined(NXP_DDR_LE)
+#define ddr_in32(a) mmio_read_32((uintptr_t)(a))
+#define ddr_out32(a, v) mmio_write_32((uintptr_t)(a), v)
+#else
+#error Please define CCSR DDR register endianness
+#endif
+
+#define ddr_setbits32(a, v) ddr_out32((a), ddr_in32(a) | (v))
+#define ddr_clrbits32(a, v) ddr_out32((a), ddr_in32(a) & ~(v))
+#define ddr_clrsetbits32(a, c, s) ddr_out32((a), (ddr_in32(a) & ~(c)) \
+ | (s))
+
+#endif /* DDR_IO_H */
diff --git a/include/drivers/nxp/ddr/dimm.h b/include/drivers/nxp/ddr/dimm.h
new file mode 100644
index 0000000..fcae179
--- /dev/null
+++ b/include/drivers/nxp/ddr/dimm.h
@@ -0,0 +1,330 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DIMM_H
+#define DIMM_H
+
+#define SPD_MEMTYPE_DDR4 0x0C
+
+#define DDR4_SPD_MODULETYPE_MASK 0x0f
+#define DDR4_SPD_MODULETYPE_EXT 0x00
+#define DDR4_SPD_RDIMM 0x01
+#define DDR4_SPD_UDIMM 0x02
+#define DDR4_SPD_SO_DIMM 0x03
+#define DDR4_SPD_LRDIMM 0x04
+#define DDR4_SPD_MINI_RDIMM 0x05
+#define DDR4_SPD_MINI_UDIMM 0x06
+#define DDR4_SPD_72B_SO_RDIMM 0x08
+#define DDR4_SPD_72B_SO_UDIMM 0x09
+#define DDR4_SPD_16B_SO_DIMM 0x0c
+#define DDR4_SPD_32B_SO_DIMM 0x0d
+
+#define SPD_SPA0_ADDRESS 0x36
+#define SPD_SPA1_ADDRESS 0x37
+
+#define spd_to_ps(mtb, ftb) \
+ ((mtb) * pdimm->mtb_ps + ((ftb) * pdimm->ftb_10th_ps) / 10)
+
+#ifdef DDR_DEBUG
+#define dump_spd(spd, len) { \
+ register int i; \
+ register unsigned char *buf = (void *)(spd); \
+ \
+ for (i = 0; i < (len); i++) { \
+ print_uint(i); \
+ puts("\t: 0x"); \
+ print_hex(buf[i]); \
+ puts("\n"); \
+ } \
+}
+#else
+#define dump_spd(spd, len) {}
+#endif
+
+/* From JEEC Standard No. 21-C release 23A */
+struct ddr4_spd {
+ /* General Section: Bytes 0-127 */
+ unsigned char info_size_crc; /* 0 # bytes */
+ unsigned char spd_rev; /* 1 Total # bytes of SPD */
+ unsigned char mem_type; /* 2 Key Byte / mem type */
+ unsigned char module_type; /* 3 Key Byte / Module Type */
+ unsigned char density_banks; /* 4 Density and Banks */
+ unsigned char addressing; /* 5 Addressing */
+ unsigned char package_type; /* 6 Package type */
+ unsigned char opt_feature; /* 7 Optional features */
+ unsigned char thermal_ref; /* 8 Thermal and refresh */
+ unsigned char oth_opt_features; /* 9 Other optional features */
+ unsigned char res_10; /* 10 Reserved */
+ unsigned char module_vdd; /* 11 Module nominal voltage */
+ unsigned char organization; /* 12 Module Organization */
+ unsigned char bus_width; /* 13 Module Memory Bus Width */
+ unsigned char therm_sensor; /* 14 Module Thermal Sensor */
+ unsigned char ext_type; /* 15 Extended module type */
+ unsigned char res_16;
+ unsigned char timebases; /* 17 MTb and FTB */
+ unsigned char tck_min; /* 18 tCKAVGmin */
+ unsigned char tck_max; /* 19 TCKAVGmax */
+ unsigned char caslat_b1; /* 20 CAS latencies, 1st byte */
+ unsigned char caslat_b2; /* 21 CAS latencies, 2nd byte */
+ unsigned char caslat_b3; /* 22 CAS latencies, 3rd byte */
+ unsigned char caslat_b4; /* 23 CAS latencies, 4th byte */
+ unsigned char taa_min; /* 24 Min CAS Latency Time */
+ unsigned char trcd_min; /* 25 Min RAS# to CAS# Delay Time */
+ unsigned char trp_min; /* 26 Min Row Precharge Delay Time */
+ unsigned char tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */
+ unsigned char tras_min_lsb; /* 28 tRASmin, lsb */
+ unsigned char trc_min_lsb; /* 29 tRCmin, lsb */
+ unsigned char trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */
+ unsigned char trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */
+ unsigned char trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */
+ unsigned char trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */
+ unsigned char trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */
+ unsigned char trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */
+ unsigned char tfaw_msb; /* 36 Upper Nibble for tFAW */
+ unsigned char tfaw_min; /* 37 tFAW, lsb */
+ unsigned char trrds_min; /* 38 tRRD_Smin, MTB */
+ unsigned char trrdl_min; /* 39 tRRD_Lmin, MTB */
+ unsigned char tccdl_min; /* 40 tCCS_Lmin, MTB */
+ unsigned char res_41[60-41]; /* 41 Rserved */
+ unsigned char mapping[78-60]; /* 60~77 Connector to SDRAM bit map */
+ unsigned char res_78[117-78]; /* 78~116, Reserved */
+ signed char fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */
+ signed char fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */
+ signed char fine_trrds_min; /* 119 Fine offset for tRRD_Smin */
+ signed char fine_trc_min; /* 120 Fine offset for tRCmin */
+ signed char fine_trp_min; /* 121 Fine offset for tRPmin */
+ signed char fine_trcd_min; /* 122 Fine offset for tRCDmin */
+ signed char fine_taa_min; /* 123 Fine offset for tAAmin */
+ signed char fine_tck_max; /* 124 Fine offset for tCKAVGmax */
+ signed char fine_tck_min; /* 125 Fine offset for tCKAVGmin */
+ /* CRC: Bytes 126-127 */
+ unsigned char crc[2]; /* 126-127 SPD CRC */
+
+ /* Module-Specific Section: Bytes 128-255 */
+ union {
+ struct {
+ /* 128 (Unbuffered) Module Nominal Height */
+ unsigned char mod_height;
+ /* 129 (Unbuffered) Module Maximum Thickness */
+ unsigned char mod_thickness;
+ /* 130 (Unbuffered) Reference Raw Card Used */
+ unsigned char ref_raw_card;
+ /* 131 (Unbuffered) Address Mapping from
+ * Edge Connector to DRAM
+ */
+ unsigned char addr_mapping;
+ /* 132~253 (Unbuffered) Reserved */
+ unsigned char res_132[254-132];
+ /* 254~255 CRC */
+ unsigned char crc[2];
+ } unbuffered;
+ struct {
+ /* 128 (Registered) Module Nominal Height */
+ unsigned char mod_height;
+ /* 129 (Registered) Module Maximum Thickness */
+ unsigned char mod_thickness;
+ /* 130 (Registered) Reference Raw Card Used */
+ unsigned char ref_raw_card;
+ /* 131 DIMM Module Attributes */
+ unsigned char modu_attr;
+ /* 132 RDIMM Thermal Heat Spreader Solution */
+ unsigned char thermal;
+ /* 133 Register Manufacturer ID Code, LSB */
+ unsigned char reg_id_lo;
+ /* 134 Register Manufacturer ID Code, MSB */
+ unsigned char reg_id_hi;
+ /* 135 Register Revision Number */
+ unsigned char reg_rev;
+ /* 136 Address mapping from register to DRAM */
+ unsigned char reg_map;
+ unsigned char ca_stren;
+ unsigned char clk_stren;
+ /* 139~253 Reserved */
+ unsigned char res_139[254-139];
+ /* 254~255 CRC */
+ unsigned char crc[2];
+ } registered;
+ struct {
+ /* 128 (Loadreduced) Module Nominal Height */
+ unsigned char mod_height;
+ /* 129 (Loadreduced) Module Maximum Thickness */
+ unsigned char mod_thickness;
+ /* 130 (Loadreduced) Reference Raw Card Used */
+ unsigned char ref_raw_card;
+ /* 131 DIMM Module Attributes */
+ unsigned char modu_attr;
+ /* 132 RDIMM Thermal Heat Spreader Solution */
+ unsigned char thermal;
+ /* 133 Register Manufacturer ID Code, LSB */
+ unsigned char reg_id_lo;
+ /* 134 Register Manufacturer ID Code, MSB */
+ unsigned char reg_id_hi;
+ /* 135 Register Revision Number */
+ unsigned char reg_rev;
+ /* 136 Address mapping from register to DRAM */
+ unsigned char reg_map;
+ /* 137 Register Output Drive Strength for CMD/Add*/
+ unsigned char reg_drv;
+ /* 138 Register Output Drive Strength for CK */
+ unsigned char reg_drv_ck;
+ /* 139 Data Buffer Revision Number */
+ unsigned char data_buf_rev;
+ /* 140 DRAM VrefDQ for Package Rank 0 */
+ unsigned char vrefqe_r0;
+ /* 141 DRAM VrefDQ for Package Rank 1 */
+ unsigned char vrefqe_r1;
+ /* 142 DRAM VrefDQ for Package Rank 2 */
+ unsigned char vrefqe_r2;
+ /* 143 DRAM VrefDQ for Package Rank 3 */
+ unsigned char vrefqe_r3;
+ /* 144 Data Buffer VrefDQ for DRAM Interface */
+ unsigned char data_intf;
+ /*
+ * 145 Data Buffer MDQ Drive Strength and RTT
+ * for data rate <= 1866
+ */
+ unsigned char data_drv_1866;
+ /*
+ * 146 Data Buffer MDQ Drive Strength and RTT
+ * for 1866 < data rate <= 2400
+ */
+ unsigned char data_drv_2400;
+ /*
+ * 147 Data Buffer MDQ Drive Strength and RTT
+ * for 2400 < data rate <= 3200
+ */
+ unsigned char data_drv_3200;
+ /* 148 DRAM Drive Strength */
+ unsigned char dram_drv;
+ /*
+ * 149 DRAM ODT (RTT_WR, RTT_NOM)
+ * for data rate <= 1866
+ */
+ unsigned char dram_odt_1866;
+ /*
+ * 150 DRAM ODT (RTT_WR, RTT_NOM)
+ * for 1866 < data rate <= 2400
+ */
+ unsigned char dram_odt_2400;
+ /*
+ * 151 DRAM ODT (RTT_WR, RTT_NOM)
+ * for 2400 < data rate <= 3200
+ */
+ unsigned char dram_odt_3200;
+ /*
+ * 152 DRAM ODT (RTT_PARK)
+ * for data rate <= 1866
+ */
+ unsigned char dram_odt_park_1866;
+ /*
+ * 153 DRAM ODT (RTT_PARK)
+ * for 1866 < data rate <= 2400
+ */
+ unsigned char dram_odt_park_2400;
+ /*
+ * 154 DRAM ODT (RTT_PARK)
+ * for 2400 < data rate <= 3200
+ */
+ unsigned char dram_odt_park_3200;
+ unsigned char res_155[254-155]; /* Reserved */
+ /* 254~255 CRC */
+ unsigned char crc[2];
+ } loadreduced;
+ unsigned char uc[128]; /* 128-255 Module-Specific Section */
+ } mod_section;
+
+ unsigned char res_256[320-256]; /* 256~319 Reserved */
+
+ /* Module supplier's data: Byte 320~383 */
+ unsigned char mmid_lsb; /* 320 Module MfgID Code LSB */
+ unsigned char mmid_msb; /* 321 Module MfgID Code MSB */
+ unsigned char mloc; /* 322 Mfg Location */
+ unsigned char mdate[2]; /* 323~324 Mfg Date */
+ unsigned char sernum[4]; /* 325~328 Module Serial Number */
+ unsigned char mpart[20]; /* 329~348 Mfg's Module Part Number */
+ unsigned char mrev; /* 349 Module Revision Code */
+ unsigned char dmid_lsb; /* 350 DRAM MfgID Code LSB */
+ unsigned char dmid_msb; /* 351 DRAM MfgID Code MSB */
+ unsigned char stepping; /* 352 DRAM stepping */
+ unsigned char msd[29]; /* 353~381 Mfg's Specific Data */
+ unsigned char res_382[2]; /* 382~383 Reserved */
+};
+
+/* Parameters for a DDR dimm computed from the SPD */
+struct dimm_params {
+ /* DIMM organization parameters */
+ char mpart[19]; /* guaranteed null terminated */
+
+ unsigned int n_ranks;
+ unsigned int die_density;
+ unsigned long long rank_density;
+ unsigned long long capacity;
+ unsigned int primary_sdram_width;
+ unsigned int ec_sdram_width;
+ unsigned int rdimm;
+ unsigned int package_3ds; /* number of dies in 3DS */
+ unsigned int device_width; /* x4, x8, x16 components */
+ unsigned int rc;
+
+ /* SDRAM device parameters */
+ unsigned int n_row_addr;
+ unsigned int n_col_addr;
+ unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
+ unsigned int bank_addr_bits;
+ unsigned int bank_group_bits;
+ unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
+
+ /* mirrored DIMMs */
+ unsigned int mirrored_dimm; /* only for ddr3 */
+
+ /* DIMM timing parameters */
+
+ int mtb_ps; /* medium timebase ps */
+ int ftb_10th_ps; /* fine timebase, in 1/10 ps */
+ int taa_ps; /* minimum CAS latency time */
+ int tfaw_ps; /* four active window delay */
+
+ /*
+ * SDRAM clock periods
+ * The range for these are 1000-10000 so a short should be sufficient
+ */
+ int tckmin_x_ps;
+ int tckmax_ps;
+
+ /* SPD-defined CAS latencies */
+ unsigned int caslat_x;
+
+ /* basic timing parameters */
+ int trcd_ps;
+ int trp_ps;
+ int tras_ps;
+
+ int trfc1_ps;
+ int trfc2_ps;
+ int trfc4_ps;
+ int trrds_ps;
+ int trrdl_ps;
+ int tccdl_ps;
+ int trfc_slr_ps;
+
+ int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
+ int twr_ps; /* 15ns for all speed bins */
+
+ unsigned int refresh_rate_ps;
+ unsigned int extended_op_srt;
+
+ /* RDIMM */
+ unsigned char rcw[16]; /* Register Control Word 0-15 */
+ unsigned int dq_mapping[18];
+ unsigned int dq_mapping_ors;
+};
+
+int read_spd(unsigned char chip, void *buf, int len);
+int crc16(unsigned char *ptr, int count);
+int cal_dimm_params(const struct ddr4_spd *spd, struct dimm_params *pdimm);
+
+#endif /* DIMM_H */
diff --git a/include/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.h b/include/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.h
new file mode 100644
index 0000000..31db552
--- /dev/null
+++ b/include/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef FSL_MMDC_H
+#define FSL_MMDC_H
+
+/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
+#define MPWLGCR_HW_WL_EN (1 << 0)
+
+/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
+#define MPPDCMPR2_MPR_COMPARE_EN (1 << 0)
+
+
+/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
+#define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28)
+
+/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
+#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4)
+
+/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
+#define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067
+
+/* MMDC Core Refresh Control Register (MMDC_MDREF) */
+#define MDREF_START_REFRESH (1 << 0)
+
+/* MMDC Core Special Command Register (MDSCR) */
+#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
+#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
+#define MDSCR_DISABLE_CFG_REQ (0 << 15)
+#define MDSCR_ENABLE_CON_REQ (1 << 15)
+#define MDSCR_CON_ACK (1 << 14)
+#define MDSCR_WL_EN (1 << 9)
+#define CMD_NORMAL (0 << 4)
+#define CMD_PRECHARGE (1 << 4)
+#define CMD_AUTO_REFRESH (2 << 4)
+#define CMD_LOAD_MODE_REG (3 << 4)
+#define CMD_ZQ_CALIBRATION (4 << 4)
+#define CMD_PRECHARGE_BANK_OPEN (5 << 4)
+#define CMD_MRR (6 << 4)
+#define CMD_BANK_ADDR_0 0x0
+#define CMD_BANK_ADDR_1 0x1
+#define CMD_BANK_ADDR_2 0x2
+#define CMD_BANK_ADDR_3 0x3
+#define CMD_BANK_ADDR_4 0x4
+#define CMD_BANK_ADDR_5 0x5
+#define CMD_BANK_ADDR_6 0x6
+#define CMD_BANK_ADDR_7 0x7
+
+/* MMDC Core Control Register (MDCTL) */
+#define MDCTL_SDE0 (U(1) << 31)
+#define MDCTL_SDE1 (1 << 30)
+
+/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */
+#define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16)
+
+/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */
+#define MMDC_MPMUR0_FRC_MSR (1 << 11)
+
+/* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */
+/* default 64 for a quarter cycle delay */
+#define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040
+
+/* MMDC Registers */
+struct mmdc_regs {
+ unsigned int mdctl;
+ unsigned int mdpdc;
+ unsigned int mdotc;
+ unsigned int mdcfg0;
+ unsigned int mdcfg1;
+ unsigned int mdcfg2;
+ unsigned int mdmisc;
+ unsigned int mdscr;
+ unsigned int mdref;
+ unsigned int res1[2];
+ unsigned int mdrwd;
+ unsigned int mdor;
+ unsigned int mdmrr;
+ unsigned int mdcfg3lp;
+ unsigned int mdmr4;
+ unsigned int mdasp;
+ unsigned int res2[239];
+ unsigned int maarcr;
+ unsigned int mapsr;
+ unsigned int maexidr0;
+ unsigned int maexidr1;
+ unsigned int madpcr0;
+ unsigned int madpcr1;
+ unsigned int madpsr0;
+ unsigned int madpsr1;
+ unsigned int madpsr2;
+ unsigned int madpsr3;
+ unsigned int madpsr4;
+ unsigned int madpsr5;
+ unsigned int masbs0;
+ unsigned int masbs1;
+ unsigned int res3[2];
+ unsigned int magenp;
+ unsigned int res4[239];
+ unsigned int mpzqhwctrl;
+ unsigned int mpzqswctrl;
+ unsigned int mpwlgcr;
+ unsigned int mpwldectrl0;
+ unsigned int mpwldectrl1;
+ unsigned int mpwldlst;
+ unsigned int mpodtctrl;
+ unsigned int mprddqby0dl;
+ unsigned int mprddqby1dl;
+ unsigned int mprddqby2dl;
+ unsigned int mprddqby3dl;
+ unsigned int mpwrdqby0dl;
+ unsigned int mpwrdqby1dl;
+ unsigned int mpwrdqby2dl;
+ unsigned int mpwrdqby3dl;
+ unsigned int mpdgctrl0;
+ unsigned int mpdgctrl1;
+ unsigned int mpdgdlst0;
+ unsigned int mprddlctl;
+ unsigned int mprddlst;
+ unsigned int mpwrdlctl;
+ unsigned int mpwrdlst;
+ unsigned int mpsdctrl;
+ unsigned int mpzqlp2ctl;
+ unsigned int mprddlhwctl;
+ unsigned int mpwrdlhwctl;
+ unsigned int mprddlhwst0;
+ unsigned int mprddlhwst1;
+ unsigned int mpwrdlhwst0;
+ unsigned int mpwrdlhwst1;
+ unsigned int mpwlhwerr;
+ unsigned int mpdghwst0;
+ unsigned int mpdghwst1;
+ unsigned int mpdghwst2;
+ unsigned int mpdghwst3;
+ unsigned int mppdcmpr1;
+ unsigned int mppdcmpr2;
+ unsigned int mpswdar0;
+ unsigned int mpswdrdr0;
+ unsigned int mpswdrdr1;
+ unsigned int mpswdrdr2;
+ unsigned int mpswdrdr3;
+ unsigned int mpswdrdr4;
+ unsigned int mpswdrdr5;
+ unsigned int mpswdrdr6;
+ unsigned int mpswdrdr7;
+ unsigned int mpmur0;
+ unsigned int mpwrcadl;
+ unsigned int mpdccr;
+};
+
+struct fsl_mmdc_info {
+ unsigned int mdctl;
+ unsigned int mdpdc;
+ unsigned int mdotc;
+ unsigned int mdcfg0;
+ unsigned int mdcfg1;
+ unsigned int mdcfg2;
+ unsigned int mdmisc;
+ unsigned int mdref;
+ unsigned int mdrwd;
+ unsigned int mdor;
+ unsigned int mdasp;
+ unsigned int mpodtctrl;
+ unsigned int mpzqhwctrl;
+ unsigned int mprddlctl;
+};
+
+void mmdc_init(const struct fsl_mmdc_info *priv, uintptr_t nxp_ddr_addr);
+
+#endif /* FSL_MMDC_H */
diff --git a/include/drivers/nxp/ddr/immap.h b/include/drivers/nxp/ddr/immap.h
new file mode 100644
index 0000000..83b4de6
--- /dev/null
+++ b/include/drivers/nxp/ddr/immap.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_IMMAP_H
+#define DDR_IMMAP_H
+
+#define DDR_DBUS_64 0
+#define DDR_DBUS_32 1
+#define DDR_DBUS_16 2
+
+/*
+ * DDRC register file for DDRC 5.0 and above
+ */
+struct ccsr_ddr {
+ struct {
+ unsigned int a; /* 0x0, 0x8, 0x10, 0x18 */
+ unsigned int res; /* 0x4, 0xc, 0x14, 0x1c */
+ } bnds[4];
+ unsigned char res_20[0x40 - 0x20];
+ unsigned int dec[10]; /* 0x40 */
+ unsigned char res_68[0x80 - 0x68];
+ unsigned int csn_cfg[4]; /* 0x80, 0x84, 0x88, 0x8c */
+ unsigned char res_90[48];
+ unsigned int csn_cfg_2[4]; /* 0xc0, 0xc4, 0xc8, 0xcc */
+ unsigned char res_d0[48];
+ unsigned int timing_cfg_3; /* SDRAM Timing Configuration 3 */
+ unsigned int timing_cfg_0; /* SDRAM Timing Configuration 0 */
+ unsigned int timing_cfg_1; /* SDRAM Timing Configuration 1 */
+ unsigned int timing_cfg_2; /* SDRAM Timing Configuration 2 */
+ unsigned int sdram_cfg; /* SDRAM Control Configuration */
+ unsigned int sdram_cfg_2; /* SDRAM Control Configuration 2 */
+ unsigned int sdram_mode; /* SDRAM Mode Configuration */
+ unsigned int sdram_mode_2; /* SDRAM Mode Configuration 2 */
+ unsigned int sdram_md_cntl; /* SDRAM Mode Control */
+ unsigned int sdram_interval; /* SDRAM Interval Configuration */
+ unsigned int sdram_data_init; /* SDRAM Data initialization */
+ unsigned char res_12c[4];
+ unsigned int sdram_clk_cntl; /* SDRAM Clock Control */
+ unsigned char res_134[20];
+ unsigned int init_addr; /* training init addr */
+ unsigned int init_ext_addr; /* training init extended addr */
+ unsigned char res_150[16];
+ unsigned int timing_cfg_4; /* SDRAM Timing Configuration 4 */
+ unsigned int timing_cfg_5; /* SDRAM Timing Configuration 5 */
+ unsigned int timing_cfg_6; /* SDRAM Timing Configuration 6 */
+ unsigned int timing_cfg_7; /* SDRAM Timing Configuration 7 */
+ unsigned int zq_cntl; /* ZQ calibration control*/
+ unsigned int wrlvl_cntl; /* write leveling control*/
+ unsigned char reg_178[4];
+ unsigned int ddr_sr_cntr; /* self refresh counter */
+ unsigned int ddr_sdram_rcw_1; /* Control Words 1 */
+ unsigned int ddr_sdram_rcw_2; /* Control Words 2 */
+ unsigned char reg_188[8];
+ unsigned int ddr_wrlvl_cntl_2; /* write leveling control 2 */
+ unsigned int ddr_wrlvl_cntl_3; /* write leveling control 3 */
+ unsigned char res_198[0x1a0-0x198];
+ unsigned int ddr_sdram_rcw_3;
+ unsigned int ddr_sdram_rcw_4;
+ unsigned int ddr_sdram_rcw_5;
+ unsigned int ddr_sdram_rcw_6;
+ unsigned char res_1b0[0x200-0x1b0];
+ unsigned int sdram_mode_3; /* SDRAM Mode Configuration 3 */
+ unsigned int sdram_mode_4; /* SDRAM Mode Configuration 4 */
+ unsigned int sdram_mode_5; /* SDRAM Mode Configuration 5 */
+ unsigned int sdram_mode_6; /* SDRAM Mode Configuration 6 */
+ unsigned int sdram_mode_7; /* SDRAM Mode Configuration 7 */
+ unsigned int sdram_mode_8; /* SDRAM Mode Configuration 8 */
+ unsigned char res_218[0x220-0x218];
+ unsigned int sdram_mode_9; /* SDRAM Mode Configuration 9 */
+ unsigned int sdram_mode_10; /* SDRAM Mode Configuration 10 */
+ unsigned int sdram_mode_11; /* SDRAM Mode Configuration 11 */
+ unsigned int sdram_mode_12; /* SDRAM Mode Configuration 12 */
+ unsigned int sdram_mode_13; /* SDRAM Mode Configuration 13 */
+ unsigned int sdram_mode_14; /* SDRAM Mode Configuration 14 */
+ unsigned int sdram_mode_15; /* SDRAM Mode Configuration 15 */
+ unsigned int sdram_mode_16; /* SDRAM Mode Configuration 16 */
+ unsigned char res_240[0x250-0x240];
+ unsigned int timing_cfg_8; /* SDRAM Timing Configuration 8 */
+ unsigned int timing_cfg_9; /* SDRAM Timing Configuration 9 */
+ unsigned int timing_cfg_10; /* SDRAM Timing COnfigurtion 10 */
+ unsigned char res_258[0x260-0x25c];
+ unsigned int sdram_cfg_3;
+ unsigned char res_264[0x270-0x264];
+ unsigned int sdram_md_cntl_2;
+ unsigned char res_274[0x400-0x274];
+ unsigned int dq_map[4];
+ unsigned char res_410[0x800-0x410];
+ unsigned int tx_cfg[4];
+ unsigned char res_810[0xb20-0x810];
+ unsigned int ddr_dsr1; /* Debug Status 1 */
+ unsigned int ddr_dsr2; /* Debug Status 2 */
+ unsigned int ddr_cdr1; /* Control Driver 1 */
+ unsigned int ddr_cdr2; /* Control Driver 2 */
+ unsigned char res_b30[200];
+ unsigned int ip_rev1; /* IP Block Revision 1 */
+ unsigned int ip_rev2; /* IP Block Revision 2 */
+ unsigned int eor; /* Enhanced Optimization Register */
+ unsigned char res_c04[252];
+ unsigned int mtcr; /* Memory Test Control Register */
+ unsigned char res_d04[28];
+ unsigned int mtp[10]; /* Memory Test Patterns */
+ unsigned char res_d48[184];
+ unsigned int data_err_inject_hi; /* Data Path Err Injection Mask Hi*/
+ unsigned int data_err_inject_lo;/* Data Path Err Injection Mask Lo*/
+ unsigned int ecc_err_inject; /* Data Path Err Injection Mask ECC */
+ unsigned char res_e0c[20];
+ unsigned int capture_data_hi; /* Data Path Read Capture High */
+ unsigned int capture_data_lo; /* Data Path Read Capture Low */
+ unsigned int capture_ecc; /* Data Path Read Capture ECC */
+ unsigned char res_e2c[20];
+ unsigned int err_detect; /* Error Detect */
+ unsigned int err_disable; /* Error Disable */
+ unsigned int err_int_en;
+ unsigned int capture_attributes; /* Error Attrs Capture */
+ unsigned int capture_address; /* Error Addr Capture */
+ unsigned int capture_ext_address; /* Error Extended Addr Capture */
+ unsigned int err_sbe; /* Single-Bit ECC Error Management */
+ unsigned char res_e5c[164];
+ unsigned int debug[64]; /* debug_1 to debug_64 */
+};
+#endif /* DDR_IMMAP_H */
diff --git a/include/drivers/nxp/ddr/opts.h b/include/drivers/nxp/ddr/opts.h
new file mode 100644
index 0000000..f32891b
--- /dev/null
+++ b/include/drivers/nxp/ddr/opts.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_OPTS_H
+#define DDR_OPTS_H
+
+#define SDRAM_TYPE_DDR4 5 /* sdram_cfg register */
+
+#define DDR_BC4 4 /* burst chop */
+#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
+#define DDR_BL8 8 /* burst length 8 */
+
+#define DDR4_RTT_OFF 0
+#define DDR4_RTT_60_OHM 1 /* RZQ/4 */
+#define DDR4_RTT_120_OHM 2 /* RZQ/2 */
+#define DDR4_RTT_40_OHM 3 /* RZQ/6 */
+#define DDR4_RTT_240_OHM 4 /* RZQ/1 */
+#define DDR4_RTT_48_OHM 5 /* RZQ/5 */
+#define DDR4_RTT_80_OHM 6 /* RZQ/3 */
+#define DDR4_RTT_34_OHM 7 /* RZQ/7 */
+#define DDR4_RTT_WR_OFF 0
+#define DDR4_RTT_WR_120_OHM 1
+#define DDR4_RTT_WR_240_OHM 2
+#define DDR4_RTT_WR_HZ 3
+#define DDR4_RTT_WR_80_OHM 4
+#define DDR_ODT_NEVER 0x0
+#define DDR_ODT_CS 0x1
+#define DDR_ODT_ALL_OTHER_CS 0x2
+#define DDR_ODT_OTHER_DIMM 0x3
+#define DDR_ODT_ALL 0x4
+#define DDR_ODT_SAME_DIMM 0x5
+#define DDR_ODT_CS_AND_OTHER_DIMM 0x6
+#define DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
+#define DDR_BA_INTLV_CS01 0x40
+#define DDR_BA_INTLV_CS0123 0x64
+#define DDR_BA_NONE 0
+#define DDR_256B_INTLV 0x8
+
+struct memctl_opt {
+ int rdimm;
+ unsigned int dbw_cap_shift;
+ struct local_opts_s {
+ unsigned int auto_precharge;
+ unsigned int odt_rd_cfg;
+ unsigned int odt_wr_cfg;
+ unsigned int odt_rtt_norm;
+ unsigned int odt_rtt_wr;
+ } cs_odt[DDRC_NUM_CS];
+ int ctlr_intlv;
+ unsigned int ctlr_intlv_mode;
+ unsigned int ba_intlv;
+ int addr_hash;
+ int ecc_mode;
+ int ctlr_init_ecc;
+ int self_refresh_in_sleep;
+ int self_refresh_irq_en;
+ int dynamic_power;
+ /* memory data width 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
+ unsigned int data_bus_dimm;
+ unsigned int data_bus_used; /* on individual board */
+ unsigned int burst_length; /* BC4, OTF and BL8 */
+ int otf_burst_chop_en;
+ int mirrored_dimm;
+ int quad_rank_present;
+ int output_driver_impedance;
+ int ap_en;
+ int x4_en;
+
+ int caslat_override;
+ unsigned int caslat_override_value;
+ int addt_lat_override;
+ unsigned int addt_lat_override_value;
+
+ unsigned int clk_adj;
+ unsigned int cpo_sample;
+ unsigned int wr_data_delay;
+
+ unsigned int cswl_override;
+ unsigned int wrlvl_override;
+ unsigned int wrlvl_sample;
+ unsigned int wrlvl_start;
+ unsigned int wrlvl_ctl_2;
+ unsigned int wrlvl_ctl_3;
+
+ int half_strength_drive_en;
+ int twot_en;
+ int threet_en;
+ unsigned int bstopre;
+ unsigned int tfaw_ps;
+
+ int rtt_override;
+ unsigned int rtt_override_value;
+ unsigned int rtt_wr_override_value;
+ unsigned int rtt_park;
+
+ int auto_self_refresh_en;
+ unsigned int sr_it;
+ unsigned int ddr_cdr1;
+ unsigned int ddr_cdr2;
+
+ unsigned int trwt_override;
+ unsigned int trwt;
+ unsigned int twrt;
+ unsigned int trrt;
+ unsigned int twwt;
+
+ unsigned int vref_phy;
+ unsigned int vref_dimm;
+ unsigned int odt;
+ unsigned int phy_tx_impedance;
+ unsigned int phy_atx_impedance;
+ unsigned int skip2d;
+};
+
+#endif /* DDR_OPTS_H */
diff --git a/include/drivers/nxp/ddr/regs.h b/include/drivers/nxp/ddr/regs.h
new file mode 100644
index 0000000..e85fd8f
--- /dev/null
+++ b/include/drivers/nxp/ddr/regs.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_REG_H
+#define DDR_REG_H
+
+#define SDRAM_CS_CONFIG_EN 0x80000000
+
+/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN 0x80000000
+#define SDRAM_CFG_SREN 0x40000000
+#define SDRAM_CFG_ECC_EN 0x20000000
+#define SDRAM_CFG_RD_EN 0x10000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
+#define SDRAM_CFG_DYN_PWR 0x00200000
+#define SDRAM_CFG_DBW_MASK 0x00180000
+#define SDRAM_CFG_DBW_SHIFT 19
+#define SDRAM_CFG_32_BW 0x00080000
+#define SDRAM_CFG_16_BW 0x00100000
+#define SDRAM_CFG_8_BW 0x00180000
+#define SDRAM_CFG_8_BE 0x00040000
+#define SDRAM_CFG_2T_EN 0x00008000
+#define SDRAM_CFG_MEM_HLT 0x00000002
+#define SDRAM_CFG_BI 0x00000001
+
+#define SDRAM_CFG2_FRC_SR 0x80000000
+#define SDRAM_CFG2_FRC_SR_CLEAR ~(SDRAM_CFG2_FRC_SR)
+#define SDRAM_CFG2_D_INIT 0x00000010
+#define SDRAM_CFG2_AP_EN 0x00000020
+#define SDRAM_CFG2_ODT_ONLY_READ 2
+
+#define SDRAM_CFG3_DDRC_RST 0x80000000
+
+#define SDRAM_INTERVAL_REFINT 0xFFFF0000
+#define SDRAM_INTERVAL_REFINT_CLEAR ~(SDRAM_INTERVAL_REFINT)
+#define SDRAM_INTERVAL_BSTOPRE 0x3FFF
+
+/* DDR_MD_CNTL */
+#define MD_CNTL_MD_EN 0x80000000
+#define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28)
+#define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24)
+#define MD_CNTL_CKE(x) (((x) & 0x3) << 20)
+
+/* DDR_CDR1 */
+#define DDR_CDR1_DHC_EN 0x80000000
+#define DDR_CDR1_ODT_SHIFT 17
+#define DDR_CDR1_ODT_MASK 0x6
+#define DDR_CDR2_ODT_MASK 0x1
+#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
+#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
+#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
+#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
+#define DDR_CDR2_VREF_RANGE_2 0x00000040
+#define DDR_CDR_ODT_OFF 0x0
+#define DDR_CDR_ODT_100ohm 0x1
+#define DDR_CDR_ODT_120OHM 0x2
+#define DDR_CDR_ODT_80ohm 0x3
+#define DDR_CDR_ODT_60ohm 0x4
+#define DDR_CDR_ODT_40ohm 0x5
+#define DDR_CDR_ODT_50ohm 0x6
+#define DDR_CDR_ODT_30ohm 0x7
+
+
+/* DDR ERR_DISABLE */
+#define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */
+#define DDR_ERR_DISABLE_SBED (1 << 2) /* Address parity error disable */
+#define DDR_ERR_DISABLE_MBED (1 << 3) /* Address parity error disable */
+
+/* Mode Registers */
+#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
+#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
+
+/* DDR DSR2 register */
+#define DDR_DSR_2_PHY_INIT_CMPLT 0x4
+
+/* SDRAM TIMING_CFG_10 register */
+#define DDR_TIMING_CFG_10_T_STAB 0x7FFF
+
+/* DEBUG 2 register */
+#define DDR_DBG_2_MEM_IDLE 0x00000002
+
+/* DEBUG 26 register */
+#define DDR_DEBUG_26_BIT_6 (0x1 << 6)
+#define DDR_DEBUG_26_BIT_7 (0x1 << 7)
+#define DDR_DEBUG_26_BIT_12 (0x1 << 12)
+#define DDR_DEBUG_26_BIT_13 (0x1 << 13)
+#define DDR_DEBUG_26_BIT_14 (0x1 << 14)
+#define DDR_DEBUG_26_BIT_15 (0x1 << 15)
+#define DDR_DEBUG_26_BIT_16 (0x1 << 16)
+#define DDR_DEBUG_26_BIT_17 (0x1 << 17)
+#define DDR_DEBUG_26_BIT_18 (0x1 << 18)
+#define DDR_DEBUG_26_BIT_19 (0x1 << 19)
+#define DDR_DEBUG_26_BIT_24 (0x1 << 24)
+#define DDR_DEBUG_26_BIT_25 (0x1 << 25)
+
+#define DDR_DEBUG_26_BIT_24_CLEAR ~(DDR_DEBUG_26_BIT_24)
+
+/* DEBUG_29 register */
+#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */
+
+#define DDR_INIT_ADDR_EXT_UIA (1 << 31)
+
+#endif /* DDR_REG_H */
diff --git a/include/drivers/nxp/ddr/utility.h b/include/drivers/nxp/ddr/utility.h
new file mode 100644
index 0000000..2e22ad5
--- /dev/null
+++ b/include/drivers/nxp/ddr/utility.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef UTILITY_H
+#define UTILITY_H
+
+#include <dcfg.h>
+
+#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
+#define CCN_HN_F_SAM_CTL 0x8
+#define CCN_HN_F_REGION_SIZE 0x10000
+#endif
+
+unsigned long get_ddr_freq(struct sysinfo *sys, int ctrl_num);
+unsigned int get_memory_clk_ps(unsigned long clk);
+unsigned int picos_to_mclk(unsigned long data_rate, unsigned int picos);
+unsigned int get_ddrc_version(const struct ccsr_ddr *ddr);
+void print_ddr_info(struct ccsr_ddr *ddr);
+
+#endif
diff --git a/include/drivers/nxp/flexspi/flash_info.h b/include/drivers/nxp/flexspi/flash_info.h
new file mode 100644
index 0000000..d0ffc86
--- /dev/null
+++ b/include/drivers/nxp/flexspi/flash_info.h
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2020-2021 NXP
+ */
+
+/**
+ * @Flash info
+ *
+ */
+#ifndef FLASH_INFO_H
+#define FLASH_INFO_H
+
+#define SZ_16M_BYTES 0x1000000U
+
+/* Start of "if defined(CONFIG_MT25QU512A)" */
+#if defined(CONFIG_MT25QU512A)
+#define F_SECTOR_64K 0x10000U
+#define F_PAGE_256 0x100U
+#define F_SECTOR_4K 0x1000U
+#define F_FLASH_SIZE_BYTES 0x4000000U
+#define F_SECTOR_ERASE_SZ F_SECTOR_64K
+#ifdef CONFIG_FSPI_4K_ERASE
+#define F_SECTOR_ERASE_SZ F_SECTOR_4K
+#endif
+
+/* End of "if defined(CONFIG_MT25QU512A)" */
+
+/* Start of "if defined(CONFIG_MX25U25645G)" */
+#elif defined(CONFIG_MX25U25645G)
+#define F_SECTOR_64K 0x10000U
+#define F_PAGE_256 0x100U
+#define F_SECTOR_4K 0x1000U
+#define F_FLASH_SIZE_BYTES 0x2000000U
+#define F_SECTOR_ERASE_SZ F_SECTOR_64K
+#ifdef CONFIG_FSPI_4K_ERASE
+#define F_SECTOR_ERASE_SZ F_SECTOR_4K
+#endif
+
+/* End of "if defined(CONFIG_MX25U25645G)" */
+
+/* Start of "if defined(CONFIG_MX25U51245G)" */
+#elif defined(CONFIG_MX25U51245G)
+#define F_SECTOR_64K 0x10000U
+#define F_PAGE_256 0x100U
+#define F_SECTOR_4K 0x1000U
+#define F_FLASH_SIZE_BYTES 0x4000000U
+#define F_SECTOR_ERASE_SZ F_SECTOR_64K
+#ifdef CONFIG_FSPI_4K_ERASE
+#define F_SECTOR_ERASE_SZ F_SECTOR_4K
+#endif
+
+/* End of "if defined(CONFIG_MX25U51245G)" */
+
+/* Start of "if defined(CONFIG_MT35XU512A)" */
+#elif defined(CONFIG_MT35XU512A)
+#define F_SECTOR_128K 0x20000U
+#define F_SECTOR_32K 0x8000U
+#define F_PAGE_256 0x100U
+#define F_SECTOR_4K 0x1000U
+#define F_FLASH_SIZE_BYTES 0x4000000U
+#define F_SECTOR_ERASE_SZ F_SECTOR_128K
+#ifdef CONFIG_FSPI_4K_ERASE
+#define F_SECTOR_ERASE_SZ F_SECTOR_4K
+#endif
+/* If Warm boot is enabled for the platform,
+ * count of arm instruction N-OP(s) to mark
+ * the completion of write operation to flash;
+ * varies from one flash to other.
+ */
+#ifdef NXP_WARM_BOOT
+#define FLASH_WR_COMP_WAIT_BY_NOP_COUNT 0x20000
+#endif
+
+/* End of "if defined(CONFIG_MT35XU512A)" */
+
+/* Start of #elif defined(CONFIG_MT35XU02G) */
+#elif defined(CONFIG_MT35XU02G)
+#define F_SECTOR_128K 0x20000U
+#define F_PAGE_256 0x100U
+#define F_SECTOR_4K 0x1000U
+#define F_FLASH_SIZE_BYTES 0x10000000U
+#define F_SECTOR_ERASE_SZ F_SECTOR_128K
+#ifdef CONFIG_FSPI_4K_ERASE
+#define F_SECTOR_ERASE_SZ F_SECTOR_4K
+#endif
+
+#endif /* End of #elif defined(CONFIG_MT35XU02G) */
+
+#endif /* FLASH_INFO_H */
diff --git a/include/drivers/nxp/flexspi/fspi_api.h b/include/drivers/nxp/flexspi/fspi_api.h
new file mode 100644
index 0000000..d0de543
--- /dev/null
+++ b/include/drivers/nxp/flexspi/fspi_api.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+/*!
+ * @file fspi_api.h
+ * @brief This file contains the FlexSPI/FSPI API to communicate
+ * to attached Slave device.
+ * @addtogroup FSPI_API
+ * @{
+ */
+
+#ifndef FSPI_API_H
+#define FSPI_API_H
+
+#if DEBUG_FLEXSPI
+#define SZ_57M 0x3900000u
+#endif
+
+/*!
+ * Basic set of APIs.
+ */
+
+/*!
+ * @details AHB read/IP Read, decision to be internal to API
+ * Minimum Read size = 1Byte
+ * @param[in] src_off source offset from where data to read from flash
+ * @param[out] des Destination location where data needs to be copied
+ * @param[in] len length in Bytes,where 1-word=4-bytes/32-bits
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int xspi_read(uint32_t src_off, uint32_t *des, uint32_t len);
+/*!
+ * @details Sector erase, Minimum size
+ * 256KB(0x40000)/128KB(0x20000)/64K(0x10000)/4K(0x1000)
+ * depending upon flash, Calls xspi_wren() internally
+ * @param[out] erase_offset Destination erase location on flash which
+ * has to be erased, needs to be multiple of 0x40000/0x20000/0x10000
+ * @param[in] erase_len length in bytes in Hex like 0x100000 for 1MB, minimum
+ * erase size is 1 sector(0x40000/0x20000/0x10000)
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int xspi_sector_erase(uint32_t erase_offset, uint32_t erase_len);
+/*!
+ * @details IP write, For writing data to flash, calls xspi_wren() internally.
+ * Single/multiple page write can start @any offset, but performance will be low
+ * due to ERRATA
+ * @param[out] dst_off Destination location on flash where data needs to
+ * be written
+ * @param[in] src source offset from where data to be read
+ * @param[in] len length in bytes,where 1-word=4-bytes/32-bits
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int xspi_write(uint32_t dst_off, void *src, uint32_t len);
+/*!
+ * @details fspi_init, Init function.
+ * @param[in] uint32_t base_reg_addr
+ * @param[in] uint32_t flash_start_addr
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int fspi_init(uint32_t base_reg_addr, uint32_t flash_start_addr);
+/*!
+ * @details is_flash_busy, Check if any erase or write or lock is
+ * pending on flash/slave
+ * @param[in] void
+ *
+ * @return TRUE/FLASE
+ */
+bool is_flash_busy(void);
+
+/*!
+ * Advanced set of APIs.
+ */
+
+/*!
+ * @details Write enable, to be used by advance users only.
+ * Step 1 for sending write commands to flash.
+ * @param[in] dst_off destination offset where data will be written
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int xspi_wren(uint32_t dst_off);
+/*!
+ * @details AHB read, meaning direct memory mapped access to flash,
+ * Minimum Read size = 1Byte
+ * @param[in] src_off source offset from where data to read from flash,
+ * needs to be word aligned
+ * @param[out] des Destination location where data needs to be copied
+ * @param[in] len length in Bytes,where 1-word=4-bytes/32-bits
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int xspi_ahb_read(uint32_t src_off, uint32_t *des, uint32_t len);
+/*!
+ * @details IP read, READ via RX buffer from flash, minimum READ size = 1Byte
+ * @param[in] src_off source offset from where data to be read from flash
+ * @param[out] des Destination location where data needs to be copied
+ * @param[in] len length in Bytes,where 1-word=4-bytes/32-bits
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int xspi_ip_read(uint32_t src_off, uint32_t *des, uint32_t len);
+/*!
+ * @details CHIP erase, Erase complete chip in one go
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int xspi_bulk_erase(void);
+
+/*!
+ * Add test cases to confirm flash read/erase/write functionality.
+ */
+void fspi_test(uint32_t fspi_test_addr, uint32_t size, int extra);
+#endif /* FSPI_API_H */
diff --git a/include/drivers/nxp/flexspi/xspi_error_codes.h b/include/drivers/nxp/flexspi/xspi_error_codes.h
new file mode 100644
index 0000000..18b31eb
--- /dev/null
+++ b/include/drivers/nxp/flexspi/xspi_error_codes.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/* error codes */
+#ifndef XSPI_ERROR_CODES_H
+#define XSPI_ERROR_CODES_H
+
+#include <errno.h>
+
+typedef enum {
+ XSPI_SUCCESS = 0,
+ XSPI_READ_FAIL = ELAST + 1,
+ XSPI_ERASE_FAIL,
+ XSPI_IP_READ_FAIL,
+ XSPI_AHB_READ_FAIL,
+ XSPI_IP_WRITE_FAIL,
+ XSPI_AHB_WRITE_FAIL,
+ XSPI_BLOCK_TIMEOUT,
+ XSPI_UNALIGN_ADDR,
+ XSPI_UNALIGN_SIZE,
+} XSPI_STATUS_CODES;
+#undef ELAST
+#define ELAST XSPI_STATUS_CODES.XSPI_UNALIGN_SIZE
+#endif
diff --git a/include/drivers/nxp/gic/gicv2/plat_gic.h b/include/drivers/nxp/gic/gicv2/plat_gic.h
new file mode 100644
index 0000000..ff34744
--- /dev/null
+++ b/include/drivers/nxp/gic/gicv2/plat_gic.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_GICV2_H
+#define PLAT_GICV2_H
+
+#include <drivers/arm/gicv2.h>
+
+ /* register offsets */
+#define GICD_CTLR_OFFSET 0x0
+#define GICD_CPENDSGIR3_OFFSET 0xF1C
+#define GICD_SPENDSGIR3_OFFSET 0xF2C
+#define GICD_SGIR_OFFSET 0xF00
+#define GICD_IGROUPR0_OFFSET 0x080
+#define GICD_TYPER_OFFSET 0x0004
+#define GICD_ISENABLER0_OFFSET 0x0100
+#define GICD_ICENABLER0_OFFSET 0x0180
+#define GICD_IPRIORITYR3_OFFSET 0x040C
+#define GICD_ISENABLERn_OFFSET 0x0100
+#define GICD_ISACTIVER0_OFFSET 0x300
+
+#define GICC_CTLR_OFFSET 0x0
+#define GICC_PMR_OFFSET 0x0004
+#define GICC_IAR_OFFSET 0x000C
+#define GICC_DIR_OFFSET 0x1000
+#define GICC_EOIR_OFFSET 0x0010
+
+ /* bitfield masks */
+#define GICC_CTLR_EN_GRP0 0x1
+#define GICC_CTLR_EN_GRP1 0x2
+#define GICC_CTLR_EOImodeS_MASK 0x200
+#define GICC_CTLR_DIS_BYPASS 0x60
+#define GICC_CTLR_CBPR_MASK 0x10
+#define GICC_CTLR_FIQ_EN_MASK 0x8
+#define GICC_CTLR_ACKCTL_MASK 0x4
+#define GICC_PMR_FILTER 0xFF
+
+#define GICD_CTLR_EN_GRP0 0x1
+#define GICD_CTLR_EN_GRP1 0x2
+#define GICD_IGROUP0_SGI15 0x8000
+#define GICD_ISENABLE0_SGI15 0x8000
+#define GICD_ICENABLE0_SGI15 0x8000
+#define GICD_ISACTIVER0_SGI15 0x8000
+#define GICD_CPENDSGIR_CLR_MASK 0xFF000000
+#define GICD_IPRIORITY_SGI15_MASK 0xFF000000
+#define GICD_SPENDSGIR3_SGI15_MASK 0xFF000000
+#define GICD_SPENDSGIR3_SGI15_OFFSET 0x18
+
+#ifndef __ASSEMBLER__
+
+/* GIC common API's */
+void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr,
+ const uintptr_t nxp_gicc_addr,
+ uint8_t plat_core_count,
+ interrupt_prop_t *ls_interrupt_props,
+ uint8_t ls_interrupt_prop_count,
+ uint32_t *target_mask_array);
+void plat_ls_gic_init(void);
+void plat_ls_gic_cpuif_enable(void);
+void plat_ls_gic_cpuif_disable(void);
+void plat_ls_gic_redistif_on(void);
+void plat_ls_gic_redistif_off(void);
+void plat_gic_pcpu_init(void);
+/* GIC utility functions */
+void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);
+#endif
+
+#endif /* PLAT_GICV2_H */
diff --git a/include/drivers/nxp/gic/gicv3/plat_gic.h b/include/drivers/nxp/gic/gicv3/plat_gic.h
new file mode 100644
index 0000000..794b06b
--- /dev/null
+++ b/include/drivers/nxp/gic/gicv3/plat_gic.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2021-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_GICV3_H
+#define PLAT_GICV3_H
+
+#include <drivers/arm/gicv3.h>
+
+ /* offset between redistributors */
+#define GIC_RD_OFFSET 0x00020000
+ /* offset between SGI's */
+#define GIC_SGI_OFFSET 0x00020000
+ /* offset from rd base to sgi base */
+#define GIC_RD_2_SGI_OFFSET 0x00010000
+
+ /* register offsets */
+#define GICD_CTLR_OFFSET 0x0
+#define GICD_CLR_SPI_SR 0x58
+#define GICD_IGROUPR_2 0x88
+#define GICD_ISENABLER_1 0x104
+#define GICD_ICENABLER_1 0x184
+#define GICD_ISENABLER_2 0x108
+#define GICD_ICENABLER_2 0x188
+#define GICD_ISENABLER_3 0x10c
+#define GICD_ICENABLER_3 0x18c
+#define GICD_ICPENDR_2 0x288
+#define GICD_ICACTIVER_2 0x388
+#define GICD_IPRIORITYR_22 0x458
+#define GICD_ICFGR_5 0xC14
+#define GICD_IGRPMODR_2 0xD08
+
+#define GICD_IROUTER60_OFFSET 0x61e0
+#define GICD_IROUTER76_OFFSET 0x6260
+#define GICD_IROUTER89_OFFSET 0x62C8
+#define GICD_IROUTER112_OFFSET 0x6380
+#define GICD_IROUTER113_OFFSET 0x6388
+
+#define GICR_ICENABLER0_OFFSET 0x180
+#define GICR_CTLR_OFFSET 0x0
+#define GICR_IGROUPR0_OFFSET 0x80
+#define GICR_IGRPMODR0_OFFSET 0xD00
+#define GICR_IPRIORITYR3_OFFSET 0x40C
+#define GICR_ICPENDR0_OFFSET 0x280
+#define GICR_ISENABLER0_OFFSET 0x100
+#define GICR_TYPER_OFFSET 0x8
+#define GICR_WAKER_OFFSET 0x14
+#define GICR_ICACTIVER0_OFFSET 0x380
+#define GICR_ICFGR0_OFFSET 0xC00
+
+ /* bitfield masks */
+#define GICD_CTLR_EN_GRP_MASK 0x7
+#define GICD_CTLR_EN_GRP_1NS 0x2
+#define GICD_CTLR_EN_GRP_1S 0x4
+#define GICD_CTLR_EN_GRP_0 0x1
+#define GICD_CTLR_ARE_S_MASK 0x10
+#define GICD_CTLR_RWP 0x80000000
+
+#define GICR_ICENABLER0_SGI15 0x00008000
+#define GICR_CTLR_RWP 0x8
+#define GICR_IGROUPR0_SGI15 0x00008000
+#define GICR_IGRPMODR0_SGI15 0x00008000
+#define GICR_ISENABLER0_SGI15 0x00008000
+#define GICR_IPRIORITYR3_SGI15_MASK 0xFF000000
+#define GICR_ICPENDR0_SGI15 0x8000
+
+#define GIC_SPI_89_MASK 0x02000000
+#define GIC_SPI89_PRIORITY_MASK 0xFF00
+#define GIC_IRM_SPI89 0x80000000
+
+#define GICD_IROUTER_VALUE 0x100
+#define GICD_ISENABLER_1_VALUE 0x10000000
+#define GICD_ISENABLER_2_VALUE 0x100
+#define GICD_ISENABLER_3_VALUE 0x20100
+#define GICR_WAKER_SLEEP_BIT 0x2
+#define GICR_WAKER_ASLEEP (1 << 2 | 1 << 1)
+
+#define ICC_SRE_EL3_SRE 0x1
+#define ICC_IGRPEN0_EL1_EN 0x1
+#define ICC_CTLR_EL3_CBPR_EL1S 0x1
+#define ICC_CTLR_EL3_RM 0x20
+#define ICC_CTLR_EL3_EOIMODE_EL3 0x4
+#define ICC_CTLR_EL3_PMHE 0x40
+#define ICC_PMR_EL1_P_FILTER 0xFF
+#define ICC_IAR0_EL1_SGI15 0xF
+#define ICC_SGI0R_EL1_INTID 0x0F000000
+#define ICC_IAR0_INTID_SPI_89 0x59
+
+#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
+#define ICC_PMR_EL1 S3_0_C4_C6_0
+#define ICC_SRE_EL3 S3_6_C12_C12_5
+#define ICC_CTLR_EL3 S3_6_C12_C12_4
+#define ICC_SRE_EL2 S3_4_C12_C9_5
+#define ICC_CTLR_EL1 S3_0_C12_C12_4
+
+#ifndef __ASSEMBLER__
+
+/* GIC common API's */
+typedef unsigned int (*my_core_pos_fn)(void);
+
+void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr,
+ const uintptr_t nxp_gicr_addr,
+ uint8_t plat_core_count,
+ interrupt_prop_t *ls_interrupt_props,
+ uint8_t ls_interrupt_prop_count,
+ uintptr_t *target_mask_array,
+ mpidr_hash_fn mpidr_to_core_pos);
+//void plat_ls_gic_driver_init(void);
+void plat_ls_gic_init(void);
+void plat_ls_gic_cpuif_enable(void);
+void plat_ls_gic_cpuif_disable(void);
+void plat_ls_gic_redistif_on(void);
+void plat_ls_gic_redistif_off(void);
+void plat_gic_pcpu_init(void);
+#endif
+
+#endif /* PLAT_GICV3_H */
diff --git a/include/drivers/nxp/gpio/nxp_gpio.h b/include/drivers/nxp/gpio/nxp_gpio.h
new file mode 100644
index 0000000..df75840
--- /dev/null
+++ b/include/drivers/nxp/gpio/nxp_gpio.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_GPIO_H
+#define PLAT_GPIO_H
+
+#include <endian.h>
+#include <lib/mmio.h>
+
+/* GPIO Register offset */
+#define GPIO_SEL_MASK 0x7F
+#define GPIO_BIT_MASK 0x1F
+#define GPDIR_REG_OFFSET 0x0
+#define GPDAT_REG_OFFSET 0x8
+
+#define GPIO_ID_BASE_ADDR_SHIFT 5U
+#define GPIO_BITS_PER_BASE_REG 32U
+
+#define GPIO_0 0
+#define GPIO_1 1
+#define GPIO_2 2
+#define GPIO_3 3
+
+#define GPIO_SUCCESS 0x0
+#define GPIO_FAILURE 0x1
+
+#ifdef NXP_GPIO_BE
+#define gpio_read32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define gpio_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
+#elif defined(NXP_GPIO_LE)
+#define gpio_read32(a) mmio_read_32((uintptr_t)(a))
+#define gpio_write32(a, v) mmio_write_32((uintptr_t)(a), (v))
+#else
+#error Please define GPIO register endianness
+#endif
+
+typedef struct {
+ uintptr_t gpio1_base_addr;
+ uintptr_t gpio2_base_addr;
+ uintptr_t gpio3_base_addr;
+ uintptr_t gpio4_base_addr;
+} gpio_init_info_t;
+
+void gpio_init(gpio_init_info_t *gpio_init_data);
+uint32_t *select_gpio_n_bitnum(uint32_t povdd_gpio, uint32_t *bit_num);
+int clr_gpio_bit(uint32_t *gpio_base_addr, uint32_t bit_num);
+int set_gpio_bit(uint32_t *gpio_base_addr, uint32_t bit_num);
+
+#endif /* PLAT_GPIO_H */
diff --git a/include/drivers/nxp/i2c/i2c.h b/include/drivers/nxp/i2c/i2c.h
new file mode 100644
index 0000000..85e6eb4
--- /dev/null
+++ b/include/drivers/nxp/i2c/i2c.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2016-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+#ifndef I2C_H
+#define I2C_H
+
+#include <lib/mmio.h>
+
+#define I2C_TIMEOUT 1000 /* ms */
+
+#define I2C_FD_CONSERV 0x7e
+#define I2C_CR_DIS (1 << 7)
+#define I2C_CR_EN (0 << 7)
+#define I2C_CR_MA (1 << 5)
+#define I2C_CR_TX (1 << 4)
+#define I2C_CR_TX_NAK (1 << 3)
+#define I2C_CR_RSTA (1 << 2)
+#define I2C_SR_BB (1 << 5)
+#define I2C_SR_IDLE (0 << 5)
+#define I2C_SR_AL (1 << 4)
+#define I2C_SR_IF (1 << 1)
+#define I2C_SR_RX_NAK (1 << 0)
+#define I2C_SR_RST (I2C_SR_AL | I2C_SR_IF)
+
+#define I2C_GLITCH_EN 0x8
+
+#define i2c_in(a) mmio_read_8((uintptr_t)(a))
+#define i2c_out(a, v) mmio_write_8((uintptr_t)(a), (v))
+
+struct ls_i2c {
+ unsigned char ad; /* I2c Bus Address Register */
+ unsigned char fd; /* I2c Bus Frequency Dividor Register */
+ unsigned char cr; /* I2c Bus Control Register */
+ unsigned char sr; /* I2c Bus Status Register */
+ unsigned char dr; /* I2C Bus Data I/O Register */
+ unsigned char ic; /* I2C Bus Interrupt Config Register */
+ unsigned char dbg; /* I2C Bus Debug Register */
+};
+
+void i2c_init(uintptr_t nxp_i2c_addr);
+int i2c_read(unsigned char chip, int addr, int alen,
+ unsigned char *buf, int len);
+int i2c_write(unsigned char chip, int addr, int alen,
+ const unsigned char *buf, int len);
+int i2c_probe_chip(unsigned char chip);
+
+#endif /* I2C_H */
diff --git a/include/drivers/nxp/ifc/ifc_nand.h b/include/drivers/nxp/ifc/ifc_nand.h
new file mode 100644
index 0000000..dbcd762
--- /dev/null
+++ b/include/drivers/nxp/ifc/ifc_nand.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IFC_NAND_H
+#define IFC_NAND_H
+
+#define NXP_IFC_SRAM_BUFFER_SIZE UL(0x100000) /* 1M */
+
+int ifc_nand_init(uintptr_t *block_dev_spec,
+ uintptr_t ifc_region_addr,
+ uintptr_t ifc_register_addr,
+ size_t ifc_sram_size,
+ uintptr_t ifc_nand_blk_offset,
+ size_t ifc_nand_blk_size);
+
+#endif /*IFC_NAND_H*/
diff --git a/include/drivers/nxp/ifc/ifc_nor.h b/include/drivers/nxp/ifc/ifc_nor.h
new file mode 100644
index 0000000..ee14460
--- /dev/null
+++ b/include/drivers/nxp/ifc/ifc_nor.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef IFC_NOR_H
+#define IFC_NOR_H
+
+
+int ifc_nor_init(uintptr_t flash_addr, size_t flash_size);
+
+#endif /*IFC_NOR_H*/
diff --git a/include/drivers/nxp/interconnect/ls_interconnect.h b/include/drivers/nxp/interconnect/ls_interconnect.h
new file mode 100644
index 0000000..777089c
--- /dev/null
+++ b/include/drivers/nxp/interconnect/ls_interconnect.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef LS_INTERCONNECT_H
+#define LS_INTERCONNECT_H
+
+#if (INTERCONNECT == CCI400)
+#define CCI_TERMINATE_BARRIER_TX 0x8
+#endif
+
+/* Interconnect CCI/CCN functions */
+void plat_ls_interconnect_enter_coherency(unsigned int num_clusters);
+void plat_ls_interconnect_exit_coherency(void);
+
+#endif
diff --git a/include/drivers/nxp/pmu/pmu.h b/include/drivers/nxp/pmu/pmu.h
new file mode 100644
index 0000000..28199e8
--- /dev/null
+++ b/include/drivers/nxp/pmu/pmu.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PMU_H
+#define PMU_H
+
+/* PMU Registers' OFFSET */
+#define PMU_PCPW20SR_OFFSET 0x830
+#define PMU_CLL2FLUSHSETR_OFFSET 0x1110
+#define PMU_CLSL2FLUSHCLRR_OFFSET 0x1114
+#define PMU_CLL2FLUSHSR_OFFSET 0x1118
+#define PMU_POWMGTCSR_VAL (1 << 20)
+
+/* PMU Registers */
+#define CORE_TIMEBASE_ENBL_OFFSET 0x8A0
+#define CLUST_TIMER_BASE_ENBL_OFFSET 0x18A0
+
+#define PMU_IDLE_CLUSTER_MASK 0x2
+#define PMU_FLUSH_CLUSTER_MASK 0x2
+#define PMU_IDLE_CORE_MASK 0xfe
+
+/* pmu register offsets and bitmaps */
+#define PMU_POWMGTDCR0_OFFSET 0xC20
+#define PMU_POWMGTCSR_OFFSET 0x4000
+#define PMU_CLAINACTSETR_OFFSET 0x1100
+#define PMU_CLAINACTCLRR_OFFSET 0x1104
+#define PMU_CLSINACTSETR_OFFSET 0x1108
+#define PMU_CLSINACTCLRR_OFFSET 0x110C
+#define PMU_CLL2FLUSHSETR_OFFSET 0x1110
+#define PMU_CLL2FLUSHCLRR_OFFSET 0x1114
+#define PMU_IPPDEXPCR0_OFFSET 0x4040
+#define PMU_IPPDEXPCR1_OFFSET 0x4044
+#define PMU_IPPDEXPCR2_OFFSET 0x4048
+#define PMU_IPPDEXPCR3_OFFSET 0x404C
+#define PMU_IPPDEXPCR4_OFFSET 0x4050
+#define PMU_IPPDEXPCR5_OFFSET 0x4054
+#define PMU_IPPDEXPCR6_OFFSET 0x4058
+#define PMU_IPSTPCR0_OFFSET 0x4120
+#define PMU_IPSTPCR1_OFFSET 0x4124
+#define PMU_IPSTPCR2_OFFSET 0x4128
+#define PMU_IPSTPCR3_OFFSET 0x412C
+#define PMU_IPSTPCR4_OFFSET 0x4130
+#define PMU_IPSTPCR5_OFFSET 0x4134
+#define PMU_IPSTPCR6_OFFSET 0x4138
+#define PMU_IPSTPACKSR0_OFFSET 0x4140
+#define PMU_IPSTPACKSR1_OFFSET 0x4144
+#define PMU_IPSTPACKSR2_OFFSET 0x4148
+#define PMU_IPSTPACKSR3_OFFSET 0x414C
+#define PMU_IPSTPACKSR4_OFFSET 0x4150
+#define PMU_IPSTPACKSR5_OFFSET 0x4154
+#define PMU_IPSTPACKSR6_OFFSET 0x4158
+
+#define CLAINACT_DISABLE_ACP 0xFF
+#define CLSINACT_DISABLE_SKY 0xFF
+#define POWMGTDCR_STP_OV_EN 0x1
+#define POWMGTCSR_LPM20_REQ 0x00100000
+
+/* Used by PMU */
+#define DEVDISR1_MASK 0x024F3504
+#define DEVDISR2_MASK 0x0003FFFF
+#define DEVDISR3_MASK 0x0000303F
+#define DEVDISR4_MASK 0x0000FFFF
+#define DEVDISR5_MASK 0x00F07603
+#define DEVDISR6_MASK 0x00000001
+
+#ifndef __ASSEMBLER__
+void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr);
+void enable_core_tb(uintptr_t nxp_pmu_addr);
+#endif /* __ASSEMBLER__ */
+
+#endif
diff --git a/include/drivers/nxp/qspi/qspi.h b/include/drivers/nxp/qspi/qspi.h
new file mode 100644
index 0000000..db11c3b
--- /dev/null
+++ b/include/drivers/nxp/qspi/qspi.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef QSPI_H
+#define QSPI_H
+
+#include <endian.h>
+#include <lib/mmio.h>
+
+#define CHS_QSPI_MCR 0x01550000
+#define CHS_QSPI_64LE 0xC
+
+#ifdef NXP_QSPI_BE
+#define qspi_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
+#elif defined(NXP_QSPI_LE)
+#define qspi_in32(a) mmio_read_32((uintptr_t)(a))
+#define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), (v))
+#else
+#error Please define CCSR QSPI register endianness
+#endif
+
+int qspi_io_setup(uintptr_t nxp_qspi_flash_addr,
+ size_t nxp_qspi_flash_size,
+ uintptr_t fip_offset);
+#endif /* __QSPI_H__ */
diff --git a/include/drivers/nxp/sd/sd_mmc.h b/include/drivers/nxp/sd/sd_mmc.h
new file mode 100644
index 0000000..32b41f1
--- /dev/null
+++ b/include/drivers/nxp/sd/sd_mmc.h
@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SD_MMC_H
+#define SD_MMC_H
+
+#include <lib/mmio.h>
+
+/* operating freq */
+#define CARD_IDENTIFICATION_FREQ 400000
+#define SD_SS_25MHZ 20000000
+#define SD_HS_50MHZ 40000000
+#define MMC_SS_20MHZ 15000000
+#define MMC_HS_26MHZ 20000000
+#define MMC_HS_52MHZ 40000000
+
+/* Need to check this value ? */
+#define MAX_PLATFORM_CLOCK 800000000
+
+/* eSDHC system control register defines */
+#define ESDHC_SYSCTL_DTOCV(t) (((t) & 0xF) << 16)
+#define ESDHC_SYSCTL_SDCLKFS(f) (((f) & 0xFF) << 8)
+#define ESDHC_SYSCTL_DVS(d) (((d) & 0xF) << 4)
+#define ESDHC_SYSCTL_SDCLKEN (0x00000008)
+#define ESDHC_SYSCTL_RSTA (0x01000000)
+
+/* Data timeout counter value. SDHC_CLK x 227 */
+#define TIMEOUT_COUNTER_SDCLK_2_27 0xE
+#define ESDHC_SYSCTL_INITA 0x08000000
+
+/* eSDHC interrupt status enable register defines */
+#define ESDHC_IRQSTATEN_CINS 0x00000040
+#define ESDHC_IRQSTATEN_BWR 0x00000010
+
+/* eSDHC interrupt status register defines */
+#define ESDHC_IRQSTAT_DMAE (0x10000000)
+#define ESDHC_IRQSTAT_AC12E (0x01000000)
+#define ESDHC_IRQSTAT_DEBE (0x00400000)
+#define ESDHC_IRQSTAT_DCE (0x00200000)
+#define ESDHC_IRQSTAT_DTOE (0x00100000)
+#define ESDHC_IRQSTAT_CIE (0x00080000)
+#define ESDHC_IRQSTAT_CEBE (0x00040000)
+#define ESDHC_IRQSTAT_CCE (0x00020000)
+#define ESDHC_IRQSTAT_CTOE (0x00010000)
+#define ESDHC_IRQSTAT_CINT (0x00000100)
+#define ESDHC_IRQSTAT_CRM (0x00000080)
+#define ESDHC_IRQSTAT_CINS (0x00000040)
+#define ESDHC_IRQSTAT_BRR (0x00000020)
+#define ESDHC_IRQSTAT_BWR (0x00000010)
+#define ESDHC_IRQSTAT_DINT (0x00000008)
+#define ESDHC_IRQSTAT_BGE (0x00000004)
+#define ESDHC_IRQSTAT_TC (0x00000002)
+#define ESDHC_IRQSTAT_CC (0x00000001)
+#define ESDHC_IRQSTAT_CMD_ERR (ESDHC_IRQSTAT_CIE |\
+ ESDHC_IRQSTAT_CEBE |\
+ ESDHC_IRQSTAT_CCE)
+#define ESDHC_IRQSTAT_DATA_ERR (ESDHC_IRQSTAT_DEBE |\
+ ESDHC_IRQSTAT_DCE |\
+ ESDHC_IRQSTAT_DTOE)
+#define ESDHC_IRQSTAT_CLEAR_ALL (0xFFFFFFFF)
+
+/* eSDHC present state register defines */
+#define ESDHC_PRSSTAT_CLSL 0x00800000
+#define ESDHC_PRSSTAT_WPSPL 0x00080000
+#define ESDHC_PRSSTAT_CDPL 0x00040000
+#define ESDHC_PRSSTAT_CINS 0x00010000
+#define ESDHC_PRSSTAT_BREN 0x00000800
+#define ESDHC_PRSSTAT_BWEN 0x00000400
+#define ESDHC_PRSSTAT_RTA 0x00000200
+#define ESDHC_PRSSTAT_WTA 0x00000100
+#define ESDHC_PRSSTAT_SDOFF 0x00000080
+#define ESDHC_PRSSTAT_PEROFF 0x00000040
+#define ESDHC_PRSSTAT_HCKOFF 0x00000020
+#define ESDHC_PRSSTAT_IPGOFF 0x00000010
+#define ESDHC_PRSSTAT_DLA 0x00000004
+#define ESDHC_PRSSTAT_CDIHB 0x00000002
+#define ESDHC_PRSSTAT_CIHB 0x00000001
+
+/* eSDHC protocol control register defines */
+#define ESDHC_PROCTL_EMODE_LE 0x00000020
+#define ESDHC_PROCTL_DTW_1BIT 0x00000000
+#define ESDHC_PROCTL_DTW_4BIT 0x00000002
+#define ESDHC_PROCTL_DTW_8BIT 0x00000004
+
+/* Watermark Level Register (WML) */
+#define ESDHC_WML_RD_WML(w) ((w) & 0x7F)
+#define ESDHC_WML_WR_WML(w) (((w) & 0x7F) << 16)
+#define ESDHC_WML_RD_BRST(w) (((w) & 0xF) << 8)
+#define ESDHC_WML_WR_BRST(w) (((w) & 0xF) << 24)
+#define ESDHC_WML_WR_BRST_MASK (0x0F000000)
+#define ESDHC_WML_RD_BRST_MASK (0x00000F00)
+#define ESDHC_WML_RD_WML_MASK (0x0000007F)
+#define ESDHC_WML_WR_WML_MASK (0x007F0000)
+#define WML_512_BYTES (0x0)
+#define BURST_128_BYTES (0x0)
+
+/* eSDHC control register define */
+#define ESDHC_DCR_SNOOP 0x00000040
+
+/* ESDHC Block attributes register */
+#define ESDHC_BLKATTR_BLKCNT(c) (((c) & 0xffff) << 16)
+#define ESDHC_BLKATTR_BLKSZE(s) ((s) & 0xfff)
+
+/* Transfer Type Register */
+#define ESDHC_XFERTYP_CMD(c) (((c) & 0x3F) << 24)
+#define ESDHC_XFERTYP_CMDTYP_NORMAL (0x0)
+#define ESDHC_XFERTYP_CMDTYP_SUSPEND (0x00400000)
+#define ESDHC_XFERTYP_CMDTYP_RESUME (0x00800000)
+#define ESDHC_XFERTYP_CMDTYP_ABORT (0x00C00000)
+#define ESDHC_XFERTYP_DPSEL (0x00200000)
+#define ESDHC_XFERTYP_CICEN (0x00100000)
+#define ESDHC_XFERTYP_CCCEN (0x00080000)
+#define ESDHC_XFERTYP_RSPTYP_NONE (0x0)
+#define ESDHC_XFERTYP_RSPTYP_136 (0x00010000)
+#define ESDHC_XFERTYP_RSPTYP_48 (0x00020000)
+#define ESDHC_XFERTYP_RSPTYP_48_BUSY (0x00030000)
+#define ESDHC_XFERTYP_MSBSEL (0x00000020)
+#define ESDHC_XFERTYP_DTDSEL (0x00000010)
+#define ESDHC_XFERTYP_AC12EN (0x00000004)
+#define ESDHC_XFERTYP_BCEN (0x00000002)
+#define ESDHC_XFERTYP_DMAEN (0x00000001)
+
+#define MMC_VDD_HIGH_VOLTAGE 0x00000100
+
+/* command index */
+#define CMD0 0
+#define CMD1 1
+#define CMD2 2
+#define CMD3 3
+#define CMD5 5
+#define CMD6 6
+#define CMD7 7
+#define CMD8 8
+#define CMD9 9
+#define CMD12 12
+#define CMD13 13
+#define CMD14 14
+#define CMD16 16
+#define CMD17 17
+#define CMD18 18
+#define CMD19 19
+#define CMD24 24
+#define CMD41 41
+#define CMD42 42
+#define CMD51 51
+#define CMD55 55
+#define CMD56 56
+#define ACMD6 CMD6
+#define ACMD13 CMD13
+#define ACMD41 CMD41
+#define ACMD42 CMD42
+#define ACMD51 CMD51
+
+/* commands abbreviations */
+#define CMD_GO_IDLE_STATE CMD0
+#define CMD_MMC_SEND_OP_COND CMD1
+#define CMD_ALL_SEND_CID CMD2
+#define CMD_SEND_RELATIVE_ADDR CMD3
+#define CMD_SET_DSR CMD4
+#define CMD_SWITCH_FUNC CMD6
+#define CMD_SELECT_CARD CMD7
+#define CMD_DESELECT_CARD CMD7
+#define CMD_SEND_IF_COND CMD8
+#define CMD_MMC_SEND_EXT_CSD CMD8
+#define CMD_SEND_CSD CMD9
+#define CMD_SEND_CID CMD10
+#define CMD_STOP_TRANSMISSION CMD12
+#define CMD_SEND_STATUS CMD13
+#define CMD_BUS_TEST_R CMD14
+#define CMD_GO_INACTIVE_STATE CMD15
+#define CMD_SET_BLOCKLEN CMD16
+#define CMD_READ_SINGLE_BLOCK CMD17
+#define CMD_READ_MULTIPLE_BLOCK CMD18
+#define CMD_WRITE_SINGLE_BLOCK CMD24
+#define CMD_BUS_TEST_W CMD19
+#define CMD_APP_CMD CMD55
+#define CMD_GEN_CMD CMD56
+#define CMD_SET_BUS_WIDTH ACMD6
+#define CMD_SD_STATUS ACMD13
+#define CMD_SD_SEND_OP_COND ACMD41
+#define CMD_SET_CLR_CARD_DETECT ACMD42
+#define CMD_SEND_SCR ACMD51
+
+/* MMC card spec version */
+#define MMC_CARD_VERSION_1_2 0
+#define MMC_CARD_VERSION_1_4 1
+#define MMC_CARD_VERSION_2_X 2
+#define MMC_CARD_VERSION_3_X 3
+#define MMC_CARD_VERSION_4_X 4
+
+/* SD Card Spec Version */
+/* May need to add version 3 here? */
+#define SD_CARD_VERSION_1_0 0
+#define SD_CARD_VERSION_1_10 1
+#define SD_CARD_VERSION_2_0 2
+
+/* card types */
+#define MMC_CARD 0
+#define SD_CARD 1
+#define NOT_SD_CARD MMC_CARD
+
+/* Card rca */
+#define SD_MMC_CARD_RCA 0x1
+#define BLOCK_LEN_512 512
+
+/* card state */
+#define STATE_IDLE 0
+#define STATE_READY 1
+#define STATE_IDENT 2
+#define STATE_STBY 3
+#define STATE_TRAN 4
+#define STATE_DATA 5
+#define STATE_RCV 6
+#define STATE_PRG 7
+#define STATE_DIS 8
+
+/* Card OCR register */
+/* VDD voltage window 1,65 to 1.95 */
+#define MMC_OCR_VDD_165_195 0x00000080
+/* VDD voltage window 2.7-2.8 */
+#define MMC_OCR_VDD_FF8 0x00FF8000
+#define MMC_OCR_CCS 0x40000000/* Card Capacity */
+#define MMC_OCR_BUSY 0x80000000/* busy bit */
+#define SD_OCR_HCS 0x40000000/* High capacity host */
+#define MMC_OCR_SECTOR_MODE 0x40000000/* Access Mode as Sector */
+
+/* mmc Switch function */
+#define SET_EXT_CSD_HS_TIMING 0x03B90100/* set High speed */
+
+/* check supports switching or not */
+#define SD_SWITCH_FUNC_CHECK_MODE 0x00FFFFF1
+#define SD_SWITCH_FUNC_SWITCH_MODE 0x80FFFFF1/* switch */
+#define SD_SWITCH_FUNC_HIGH_SPEED 0x02/* HIGH SPEED FUNC */
+#define SWITCH_ERROR 0x00000080
+
+/* errors in sending commands */
+#define RESP_TIMEOUT 0x1
+#define COMMAND_ERROR 0x2
+/* error in response */
+#define R1_ERROR (1 << 19)
+#define R1_CURRENT_STATE(x) (((x) & 0x00001E00) >> 9)
+
+/* Host Controller Capabilities */
+#define ESDHC_HOSTCAPBLT_DMAS (0x00400000)
+
+
+/* SD/MMC memory map */
+struct esdhc_regs {
+ uint32_t dsaddr; /* dma system address */
+ uint32_t blkattr; /* Block attributes */
+ uint32_t cmdarg; /* Command argument */
+ uint32_t xfertyp; /* Command transfer type */
+ uint32_t cmdrsp[4]; /* Command response0,1,2,3 */
+ uint32_t datport; /* Data buffer access port */
+ uint32_t prsstat; /* Present state */
+ uint32_t proctl; /* Protocol control */
+ uint32_t sysctl; /* System control */
+ uint32_t irqstat; /* Interrupt status */
+ uint32_t irqstaten; /* Interrupt status enable */
+ uint32_t irqsigen; /* Interrupt signal enable */
+ uint32_t autoc12err; /* Auto CMD12 status */
+ uint32_t hostcapblt; /* Host controller capabilities */
+ uint32_t wml; /* Watermark level */
+ uint32_t res1[2];
+ uint32_t fevt; /* Force event */
+ uint32_t res2;
+ uint32_t adsaddrl;
+ uint32_t adsaddrh;
+ uint32_t res3[39];
+ uint32_t hostver; /* Host controller version */
+ uint32_t res4;
+ uint32_t dmaerr; /* DMA error address */
+ uint32_t dmaerrh; /* DMA error address high */
+ uint32_t dmaerrattr; /* DMA error atrribute */
+ uint32_t res5;
+ uint32_t hostcapblt2;/* Host controller capabilities2 */
+ uint32_t res6[2];
+ uint32_t tcr; /* Tuning control */
+ uint32_t res7[7];
+ uint32_t dirctrl; /* Direction control */
+ uint32_t ccr; /* Clock control */
+ uint32_t res8[177];
+ uint32_t ctl; /* Control register */
+};
+
+/* SD/MMC card attributes */
+struct card_attributes {
+ uint32_t type; /* sd or mmc card */
+ uint32_t version; /* version */
+ uint32_t block_len; /* block length */
+ uint32_t bus_freq; /* sdhc bus frequency */
+ uint16_t rca; /* relative card address */
+ uint8_t is_high_capacity; /* high capacity */
+};
+
+struct mmc {
+ struct esdhc_regs *esdhc_regs;
+ struct card_attributes card;
+
+ uint32_t block_len;
+ uint32_t voltages_caps; /* supported voltaes */
+ uint32_t dma_support; /* DMA support */
+};
+
+enum cntrl_num {
+ SDHC1 = 0,
+ SDHC2
+};
+
+int sd_emmc_init(uintptr_t *block_dev_spec,
+ uintptr_t nxp_esdhc_addr,
+ size_t nxp_sd_block_offset,
+ size_t nxp_sd_block_size,
+ bool card_detect);
+
+int esdhc_emmc_init(struct mmc *mmc, bool card_detect);
+int esdhc_read(struct mmc *mmc, uint32_t src_offset, uintptr_t dst,
+ size_t size);
+int esdhc_write(struct mmc *mmc, uintptr_t src, uint32_t dst_offset,
+ size_t size);
+
+#ifdef NXP_ESDHC_BE
+#define esdhc_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define esdhc_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
+#elif defined(NXP_ESDHC_LE)
+#define esdhc_in32(a) mmio_read_32((uintptr_t)(a))
+#define esdhc_out32(a, v) mmio_write_32((uintptr_t)(a), (v))
+#else
+#error Please define CCSR ESDHC register endianness
+#endif
+
+#endif /*SD_MMC_H*/
diff --git a/include/drivers/nxp/sec_mon/snvs.h b/include/drivers/nxp/sec_mon/snvs.h
new file mode 100644
index 0000000..4455383
--- /dev/null
+++ b/include/drivers/nxp/sec_mon/snvs.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SNVS_H
+#define SNVS_H
+
+
+#ifndef __ASSEMBLER__
+
+#include <endian.h>
+#include <stdbool.h>
+
+#include <lib/mmio.h>
+
+struct snvs_regs {
+ uint32_t reserved1;
+ uint32_t hp_com; /* 0x04 SNVS_HP Command Register */
+ uint32_t reserved2[3];
+ uint32_t hp_stat; /* 0x14 SNVS_HP Status Register */
+};
+
+#ifdef NXP_SNVS_BE
+#define snvs_read32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32((v)))
+#elif defined(NXP_SNVS_LE)
+#define snvs_read32(a) mmio_read_32((uintptr_t)(a))
+#define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), (v))
+#else
+#error Please define CCSR SNVS register endianness
+#endif
+
+void snvs_init(uintptr_t nxp_snvs_addr);
+uint32_t get_snvs_state(void);
+void transition_snvs_non_secure(void);
+void transition_snvs_soft_fail(void);
+uint32_t transition_snvs_trusted(void);
+uint32_t transition_snvs_secure(void);
+
+uint32_t snvs_read_lp_gpr_bit(uint32_t offset, uint32_t bit_pos);
+void snvs_write_lp_gpr_bit(uint32_t offset, uint32_t bit_pos, bool flag_val);
+
+void snvs_disable_zeroize_lp_gpr(void);
+
+#if defined(NXP_NV_SW_MAINT_LAST_EXEC_DATA) && defined(NXP_COINED_BB)
+uint32_t snvs_read_app_data(void);
+uint32_t snvs_read_app_data_bit(uint32_t bit_pos);
+void snvs_clear_app_data(void);
+void snvs_write_app_data_bit(uint32_t bit_pos);
+#endif
+
+#endif /* __ASSEMBLER__ */
+
+/* SSM_ST field in SNVS status reg */
+#define HPSTS_CHECK_SSM_ST 0x900 /* SNVS is in check state */
+#define HPSTS_NON_SECURE_SSM_ST 0xb00 /* SNVS is in non secure state */
+#define HPSTS_TRUST_SSM_ST 0xd00 /* SNVS is in trusted state */
+#define HPSTS_SECURE_SSM_ST 0xf00 /* SNVS is in secure state */
+#define HPSTS_SOFT_FAIL_SSM_ST 0x300 /* SNVS is in soft fail state */
+#define HPSTS_MASK_SSM_ST 0xf00 /* SSM_ST field mask in SNVS reg */
+
+/* SNVS register bits */
+#define HPCOM_SW_SV 0x100 /* Security Violation bit */
+#define HPCOM_SW_FSV 0x200 /* Fatal Security Violation bit */
+#define HPCOM_SSM_ST 0x1 /* SSM_ST field in SNVS command reg */
+#define HPCOM_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */
+#define HPCOM_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */
+
+#define NXP_LP_GPR0_OFFSET 0x90
+#define NXP_LPCR_OFFSET 0x38
+#define NXP_GPR_Z_DIS_BIT 24
+
+#ifdef NXP_COINED_BB
+
+#ifndef NXP_APP_DATA_LP_GPR_OFFSET
+#define NXP_APP_DATA_LP_GPR_OFFSET NXP_LP_GPR0_OFFSET
+#endif
+
+#define NXP_LPGPR_ZEROTH_BIT 0
+
+#endif /* NXP_COINED_BB */
+
+#endif /* SNVS_H */
diff --git a/include/drivers/nxp/sfp/fuse_prov.h b/include/drivers/nxp/sfp/fuse_prov.h
new file mode 100644
index 0000000..e015318
--- /dev/null
+++ b/include/drivers/nxp/sfp/fuse_prov.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#if !defined(FUSE_PROV_H) && defined(POLICY_FUSE_PROVISION)
+#define FUSE_PROV_H
+
+#include <endian.h>
+#include <lib/mmio.h>
+
+#define MASK_NONE U(0xFFFFFFFF)
+#define ERROR_WRITE U(0xA)
+#define ERROR_ALREADY_BLOWN U(0xB)
+
+/* Flag bit shifts */
+#define FLAG_POVDD_SHIFT U(0)
+#define FLAG_SYSCFG_SHIFT U(1)
+#define FLAG_SRKH_SHIFT U(2)
+#define FLAG_MC_SHIFT U(3)
+#define FLAG_DCV0_SHIFT U(4)
+#define FLAG_DCV1_SHIFT U(5)
+#define FLAG_DRV0_SHIFT U(6)
+#define FLAG_DRV1_SHIFT U(7)
+#define FLAG_OUID0_SHIFT U(8)
+#define FLAG_OUID1_SHIFT U(9)
+#define FLAG_OUID2_SHIFT U(10)
+#define FLAG_OUID3_SHIFT U(11)
+#define FLAG_OUID4_SHIFT U(12)
+#define FLAG_DBG_LVL_SHIFT U(13)
+#define FLAG_OTPMK_SHIFT U(16)
+#define FLAG_OUID_MASK U(0x1F)
+#define FLAG_DEBUG_MASK U(0xF)
+#define FLAG_OTPMK_MASK U(0xF)
+
+/* OTPMK flag values */
+#define PROG_OTPMK_MIN U(0x0)
+#define PROG_OTPMK_RANDOM U(0x1)
+#define PROG_OTPMK_USER U(0x2)
+#define PROG_OTPMK_RANDOM_MIN U(0x5)
+#define PROG_OTPMK_USER_MIN U(0x6)
+#define PROG_NO_OTPMK U(0x8)
+
+#define OTPMK_MIM_BITS_MASK U(0xF0000000)
+
+/* System configuration bit shifts */
+#define SCB_WP_SHIFT U(0)
+#define SCB_ITS_SHIFT U(2)
+#define SCB_NSEC_SHIFT U(4)
+#define SCB_ZD_SHIFT U(5)
+#define SCB_K0_SHIFT U(15)
+#define SCB_K1_SHIFT U(14)
+#define SCB_K2_SHIFT U(13)
+#define SCB_K3_SHIFT U(12)
+#define SCB_K4_SHIFT U(11)
+#define SCB_K5_SHIFT U(10)
+#define SCB_K6_SHIFT U(9)
+#define SCB_FR0_SHIFT U(30)
+#define SCB_FR1_SHIFT U(31)
+
+/* Fuse Header Structure */
+struct fuse_hdr_t {
+ uint8_t barker[4]; /* 0x00 Barker code */
+ uint32_t flags; /* 0x04 Script flags */
+ uint32_t povdd_gpio; /* 0x08 GPIO for POVDD */
+ uint32_t otpmk[8]; /* 0x0C-0x2B OTPMK */
+ uint32_t srkh[8]; /* 0x2C-0x4B SRKH */
+ uint32_t oem_uid[5]; /* 0x4C-0x5F OEM unique id's */
+ uint32_t dcv[2]; /* 0x60-0x67 Debug Challenge */
+ uint32_t drv[2]; /* 0x68-0x6F Debug Response */
+ uint32_t ospr1; /* 0x70 OSPR1 */
+ uint32_t sc; /* 0x74 OSPR0 (System Configuration) */
+ uint32_t reserved[2]; /* 0x78-0x7F Reserved */
+};
+
+/* Function to do fuse provisioning */
+int provision_fuses(unsigned long long fuse_scr_addr,
+ bool en_povdd_status);
+
+#define EFUSE_POWERUP_DELAY_mSec U(25)
+#endif /* FUSE_PROV_H */
diff --git a/include/drivers/nxp/sfp/sfp.h b/include/drivers/nxp/sfp/sfp.h
new file mode 100644
index 0000000..2cb4c7d
--- /dev/null
+++ b/include/drivers/nxp/sfp/sfp.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SFP_H
+#define SFP_H
+
+#include <endian.h>
+#include <lib/mmio.h>
+
+/* SFP Configuration Register Offsets */
+#define SFP_INGR_OFFSET U(0x20)
+#define SFP_SVHESR_OFFSET U(0x24)
+#define SFP_SFPCR_OFFSET U(0x28)
+#define SFP_VER_OFFSET U(0x38)
+
+/* SFP Hamming register masks for OTPMK and DRV */
+#define SFP_SVHESR_DRV_MASK U(0x7F)
+#define SFP_SVHESR_OTPMK_MASK U(0x7FC00)
+
+/* SFP commands */
+#define SFP_INGR_READFB_CMD U(0x1)
+#define SFP_INGR_PROGFB_CMD U(0x2)
+#define SFP_INGR_ERROR_MASK U(0x100)
+
+/* SFPCR Masks */
+#define SFP_SFPCR_WD U(0x80000000)
+#define SFP_SFPCR_WDL U(0x40000000)
+
+/* SFPCR Masks */
+#define SFP_SFPCR_WD U(0x80000000)
+#define SFP_SFPCR_WDL U(0x40000000)
+
+#define SFP_FUSE_REGS_OFFSET U(0x200)
+
+#ifdef NXP_SFP_VER_3_4
+#define OSPR0_SC_MASK U(0xC000FE35)
+#elif defined(NXP_SFP_VER_3_2)
+#define OSPR0_SC_MASK U(0x0000E035)
+#endif
+
+#if defined(NXP_SFP_VER_3_4)
+#define OSPR_KEY_REVOC_SHIFT U(9)
+#define OSPR_KEY_REVOC_MASK U(0x0000fe00)
+#elif defined(NXP_SFP_VER_3_2)
+#define OSPR_KEY_REVOC_SHIFT U(13)
+#define OSPR_KEY_REVOC_MASK U(0x0000e000)
+#endif /* NXP_SFP_VER_3_4 */
+
+#define OSPR1_MC_MASK U(0xFFFF0000)
+#define OSPR1_DBG_LVL_MASK U(0x00000007)
+
+#define OSPR_ITS_MASK U(0x00000004)
+#define OSPR_WP_MASK U(0x00000001)
+
+#define MAX_OEM_UID U(5)
+#define SRK_HASH_SIZE U(32)
+
+/* SFP CCSR Register Map */
+struct sfp_ccsr_regs_t {
+ uint32_t ospr; /* 0x200 OSPR0 */
+ uint32_t ospr1; /* 0x204 OSPR1 */
+ uint32_t dcv[2]; /* 0x208 Debug Challenge Value */
+ uint32_t drv[2]; /* 0x210 Debug Response Value */
+ uint32_t fswpr; /* 0x218 FSL Section Write Protect */
+ uint32_t fsl_uid[2]; /* 0x21c FSL UID 0 */
+ uint32_t isbcr; /* 0x224 ISBC Configuration */
+ uint32_t fsspr[3]; /* 0x228 FSL Scratch Pad */
+ uint32_t otpmk[8]; /* 0x234 OTPMK */
+ uint32_t srk_hash[SRK_HASH_SIZE/sizeof(uint32_t)];
+ /* 0x254 Super Root Key Hash */
+ uint32_t oem_uid[MAX_OEM_UID]; /* 0x274 OEM UID 0 */
+};
+
+uintptr_t get_sfp_addr(void);
+void sfp_init(uintptr_t nxp_sfp_addr);
+uint32_t *get_sfp_srk_hash(void);
+int sfp_check_its(void);
+int sfp_check_oem_wp(void);
+uint32_t get_key_revoc(void);
+void set_sfp_wr_disable(void);
+int sfp_program_fuses(void);
+
+uint32_t sfp_read_oem_uid(uint8_t oem_uid);
+uint32_t sfp_write_oem_uid(uint8_t oem_uid, uint32_t sfp_val);
+
+#ifdef NXP_SFP_BE
+#define sfp_read32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
+#elif defined(NXP_SFP_LE)
+#define sfp_read32(a) mmio_read_32((uintptr_t)(a))
+#define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), (v))
+#else
+#error Please define CCSR SFP register endianness
+#endif
+
+#endif/* SFP_H */
diff --git a/include/drivers/nxp/sfp/sfp_error_codes.h b/include/drivers/nxp/sfp/sfp_error_codes.h
new file mode 100644
index 0000000..7be7a27
--- /dev/null
+++ b/include/drivers/nxp/sfp/sfp_error_codes.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SFP_ERROR_CODES_H
+#define SFP_ERROR_CODES_H
+
+ /* Error codes */
+#define ERROR_FUSE_BARKER 0x1
+#define ERROR_READFB_CMD 0x2
+#define ERROR_PROGFB_CMD 0x3
+#define ERROR_SRKH_ALREADY_BLOWN 0x4
+#define ERROR_SRKH_WRITE 0x5
+#define ERROR_OEMUID_ALREADY_BLOWN 0x6
+#define ERROR_OEMUID_WRITE 0x7
+#define ERROR_DCV_ALREADY_BLOWN 0x8
+#define ERROR_DCV_WRITE 0x9
+#define ERROR_DRV_ALREADY_BLOWN 0xa
+#define ERROR_DRV_HAMMING_ERROR 0xb
+#define ERROR_DRV_WRITE 0x18
+#define ERROR_OTPMK_ALREADY_BLOWN 0xc
+#define ERROR_OTPMK_HAMMING_ERROR 0xd
+#define ERROR_OTPMK_USER_MIN 0xe
+#define ERROR_OSPR1_ALREADY_BLOWN 0xf
+#define ERROR_OSPR1_WRITE 0x10
+#define ERROR_SC_ALREADY_BLOWN 0x11
+#define ERROR_SC_WRITE 0x12
+#define ERROR_POVDD_GPIO_FAIL 0x13
+#define ERROR_GPIO_SET_FAIL 0x14
+#define ERROR_GPIO_RESET_FAIL 0x15
+#define ERROR_OTPMK_SEC_DISABLED 0x16
+#define ERROR_OTPMK_SEC_ERROR 0x17
+#define ERROR_OTPMK_WRITE 0x19
+#define PLAT_ERROR_ENABLE_POVDD 0x20
+#define PLAT_ERROR_DISABLE_POVDD 0x21
+
+#endif /* SFP_ERROR_CODES_H */
diff --git a/include/drivers/nxp/smmu/nxp_smmu.h b/include/drivers/nxp/smmu/nxp_smmu.h
new file mode 100644
index 0000000..d64c33b
--- /dev/null
+++ b/include/drivers/nxp/smmu/nxp_smmu.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef NXP_SMMU_H
+#define NXP_SMMU_H
+
+#define SMMU_SCR0 (0x0)
+#define SMMU_NSCR0 (0x400)
+
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SCR0_USFCFG_MASK 0x00000400
+
+static inline void bypass_smmu(uintptr_t smmu_base_addr)
+{
+ uint32_t val;
+
+ val = (mmio_read_32(smmu_base_addr + SMMU_SCR0) | SCR0_CLIENTPD_MASK) &
+ ~(SCR0_USFCFG_MASK);
+ mmio_write_32((smmu_base_addr + SMMU_SCR0), val);
+
+ val = (mmio_read_32(smmu_base_addr + SMMU_NSCR0) | SCR0_CLIENTPD_MASK) &
+ ~(SCR0_USFCFG_MASK);
+ mmio_write_32((smmu_base_addr + SMMU_NSCR0), val);
+}
+
+#endif
diff --git a/include/drivers/nxp/timer/nxp_timer.h b/include/drivers/nxp/timer/nxp_timer.h
new file mode 100644
index 0000000..280e5b2
--- /dev/null
+++ b/include/drivers/nxp/timer/nxp_timer.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#
+#ifndef NXP_TIMER_H
+#define NXP_TIMER_H
+
+ /* System Counter Offset and Bit Mask */
+#define SYS_COUNTER_CNTCR_OFFSET 0x0
+#define SYS_COUNTER_CNTCR_EN 0x00000001
+#define CNTCR_EN_MASK 0x1
+
+#ifndef __ASSEMBLER__
+uint64_t get_timer_val(uint64_t start);
+
+#ifdef IMAGE_BL31
+void ls_configure_sys_timer(uintptr_t ls_sys_timctl_base,
+ uint8_t ls_config_cntacr,
+ uint8_t plat_ls_ns_timer_frame_id);
+void enable_init_timer(void);
+#endif
+
+/*
+ * Initialise the nxp on-chip free rolling usec counter as the delay
+ * timer.
+ */
+void delay_timer_init(uintptr_t nxp_timer_addr);
+void ls_bl31_timer_init(uintptr_t nxp_timer_addr);
+#endif /* __ASSEMBLER__ */
+
+#endif /* NXP_TIMER_H */
diff --git a/include/drivers/nxp/tzc/plat_tzc380.h b/include/drivers/nxp/tzc/plat_tzc380.h
new file mode 100644
index 0000000..08d2148
--- /dev/null
+++ b/include/drivers/nxp/tzc/plat_tzc380.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if !defined(PLAT_TZC380_H) && defined(IMAGE_BL2)
+#define PLAT_TZC380_H
+
+#include <tzc380.h>
+
+/* Number of DRAM regions to be configured
+ * for the platform can be over-written.
+ *
+ * Array tzc400_reg_list too, needs be over-written
+ * if there is any changes to default DRAM region
+ * configuration.
+ */
+#ifndef MAX_NUM_TZC_REGION
+/* 3 regions:
+ * Region 0(default),
+ * Region 1 (DRAM0, Secure Memory),
+ * Region 2 (DRAM0, Shared memory)
+ */
+#define MAX_NUM_TZC_REGION 3
+#define DEFAULT_TZASC_CONFIG 1
+#endif
+
+struct tzc380_reg {
+ unsigned int secure;
+ unsigned int enabled;
+ uint64_t addr;
+ uint64_t size;
+ unsigned int sub_mask;
+};
+
+void mem_access_setup(uintptr_t base, uint32_t total_regions,
+ struct tzc380_reg *tzc380_reg_list);
+
+int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
+ int dram_idx, int list_idx,
+ uint64_t dram_start_addr,
+ uint64_t dram_size,
+ uint32_t secure_dram_sz,
+ uint32_t shrd_dram_sz);
+
+#endif /* PLAT_TZC380_H */
diff --git a/include/drivers/nxp/tzc/plat_tzc400.h b/include/drivers/nxp/tzc/plat_tzc400.h
new file mode 100644
index 0000000..1b8e3a4
--- /dev/null
+++ b/include/drivers/nxp/tzc/plat_tzc400.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#if !defined(PLAT_TZC400_H) && defined(IMAGE_BL2)
+#define PLAT_TZC400_H
+
+#include <tzc400.h>
+
+/* Structure to configure TZC Regions' boundaries and attributes. */
+struct tzc400_reg {
+ uint8_t reg_filter_en;
+ unsigned long long start_addr;
+ unsigned long long end_addr;
+ unsigned int sec_attr;
+ unsigned int nsaid_permissions;
+};
+
+#define TZC_REGION_NS_NONE 0x00000000U
+
+/* NXP Platforms do not support NS Access ID (NSAID) based non-secure access.
+ * Supports only non secure through generic NS ACCESS ID
+ */
+#define TZC_NS_ACCESS_ID 0xFFFFFFFFU
+
+/* Number of DRAM regions to be configured
+ * for the platform can be over-written.
+ *
+ * Array tzc400_reg_list too, needs be over-written
+ * if there is any changes to default DRAM region
+ * configuration.
+ */
+#ifndef MAX_NUM_TZC_REGION
+/* 3 regions:
+ * Region 0(default),
+ * Region 1 (DRAM0, Secure Memory),
+ * Region 2 (DRAM0, Shared memory)
+ */
+#define MAX_NUM_TZC_REGION NUM_DRAM_REGIONS + 3
+#define DEFAULT_TZASC_CONFIG 1
+#endif
+
+void mem_access_setup(uintptr_t base, uint32_t total_regions,
+ struct tzc400_reg *tzc400_reg_list);
+int populate_tzc400_reg_list(struct tzc400_reg *tzc400_reg_list,
+ int dram_idx, int list_idx,
+ uint64_t dram_start_addr,
+ uint64_t dram_size,
+ uint32_t secure_dram_sz,
+ uint32_t shrd_dram_sz);
+
+#endif /* PLAT_TZC400_H */
diff --git a/include/drivers/partition/efi.h b/include/drivers/partition/efi.h
new file mode 100644
index 0000000..e463f96
--- /dev/null
+++ b/include/drivers/partition/efi.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2021, Linaro Limited
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DRIVERS_PARTITION_EFI_H
+#define DRIVERS_PARTITION_EFI_H
+
+#include <string.h>
+
+#include <tools_share/uuid.h>
+
+#define EFI_NAMELEN 36
+
+static inline int guidcmp(const void *g1, const void *g2)
+{
+ return memcmp(g1, g2, sizeof(struct efi_guid));
+}
+
+static inline void *guidcpy(void *dst, const void *src)
+{
+ return memcpy(dst, src, sizeof(struct efi_guid));
+}
+
+#define EFI_GUID(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
+ { (a) & 0xffffffff, \
+ (b) & 0xffff, \
+ (c) & 0xffff, \
+ { (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } }
+
+#define NULL_GUID \
+ EFI_GUID(0x00000000, 0x0000, 0x0000, 0x00, 0x00, \
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)
+
+#endif /* DRIVERS_PARTITION_EFI_H */
diff --git a/include/drivers/partition/gpt.h b/include/drivers/partition/gpt.h
new file mode 100644
index 0000000..c2a229e
--- /dev/null
+++ b/include/drivers/partition/gpt.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GPT_H
+#define GPT_H
+
+#include <drivers/partition/efi.h>
+#include <drivers/partition/partition.h>
+#include <tools_share/uuid.h>
+
+#define PARTITION_TYPE_GPT 0xee
+#define GPT_HEADER_OFFSET PLAT_PARTITION_BLOCK_SIZE
+#define GPT_ENTRY_OFFSET (GPT_HEADER_OFFSET + \
+ PLAT_PARTITION_BLOCK_SIZE)
+
+#define GPT_SIGNATURE "EFI PART"
+
+typedef struct gpt_entry {
+ struct efi_guid type_uuid;
+ struct efi_guid unique_uuid;
+ unsigned long long first_lba;
+ unsigned long long last_lba;
+ unsigned long long attr;
+ unsigned short name[EFI_NAMELEN];
+} gpt_entry_t;
+
+typedef struct gpt_header {
+ unsigned char signature[8];
+ unsigned int revision;
+ unsigned int size;
+ unsigned int header_crc;
+ unsigned int reserved;
+ unsigned long long current_lba;
+ unsigned long long backup_lba;
+ unsigned long long first_lba;
+ unsigned long long last_lba;
+ struct efi_guid disk_uuid;
+ /* starting LBA of array of partition entries */
+ unsigned long long part_lba;
+ /* number of partition entries in array */
+ unsigned int list_num;
+ /* size of a single partition entry (usually 128) */
+ unsigned int part_size;
+ unsigned int part_crc;
+} gpt_header_t;
+
+int parse_gpt_entry(gpt_entry_t *gpt_entry, partition_entry_t *entry);
+
+#endif /* GPT_H */
diff --git a/include/drivers/partition/mbr.h b/include/drivers/partition/mbr.h
new file mode 100644
index 0000000..1452c02
--- /dev/null
+++ b/include/drivers/partition/mbr.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MBR_H
+#define MBR_H
+
+#define MBR_OFFSET 0
+
+#define MBR_PRIMARY_ENTRY_OFFSET 0x1be
+#define MBR_PRIMARY_ENTRY_SIZE 0x10
+#define MBR_PRIMARY_ENTRY_NUMBER 4
+#define MBR_CHS_ADDRESS_LEN 3
+
+#define MBR_SIGNATURE_FIRST 0x55
+#define MBR_SIGNATURE_SECOND 0xAA
+
+typedef struct mbr_entry {
+ unsigned char status;
+ unsigned char first_sector[MBR_CHS_ADDRESS_LEN];
+ unsigned char type;
+ unsigned char last_sector[MBR_CHS_ADDRESS_LEN];
+ unsigned int first_lba;
+ unsigned int sector_nums;
+} mbr_entry_t;
+
+#endif /* MBR_H */
diff --git a/include/drivers/partition/partition.h b/include/drivers/partition/partition.h
new file mode 100644
index 0000000..6cb59c3
--- /dev/null
+++ b/include/drivers/partition/partition.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PARTITION_H
+#define PARTITION_H
+
+#include <stdint.h>
+
+#include <lib/cassert.h>
+#include <drivers/partition/efi.h>
+#include <tools_share/uuid.h>
+
+#if !PLAT_PARTITION_MAX_ENTRIES
+# define PLAT_PARTITION_MAX_ENTRIES 128
+#endif /* PLAT_PARTITION_MAX_ENTRIES */
+
+CASSERT(PLAT_PARTITION_MAX_ENTRIES <= 128, assert_plat_partition_max_entries);
+
+#if !PLAT_PARTITION_BLOCK_SIZE
+# define PLAT_PARTITION_BLOCK_SIZE 512
+#endif /* PLAT_PARTITION_BLOCK_SIZE */
+
+CASSERT((PLAT_PARTITION_BLOCK_SIZE == 512) ||
+ (PLAT_PARTITION_BLOCK_SIZE == 4096),
+ assert_plat_partition_block_size);
+
+#define LEGACY_PARTITION_BLOCK_SIZE 512
+
+#define DEFAULT_GPT_HEADER_SIZE 92
+
+typedef struct partition_entry {
+ uint64_t start;
+ uint64_t length;
+ char name[EFI_NAMELEN];
+ struct efi_guid part_guid;
+ struct efi_guid type_guid;
+} partition_entry_t;
+
+typedef struct partition_entry_list {
+ partition_entry_t list[PLAT_PARTITION_MAX_ENTRIES];
+ int entry_count;
+} partition_entry_list_t;
+
+int load_partition_table(unsigned int image_id);
+const partition_entry_t *get_partition_entry(const char *name);
+const partition_entry_t *get_partition_entry_by_type(const uuid_t *type_guid);
+const partition_entry_t *get_partition_entry_by_uuid(const uuid_t *part_uuid);
+const partition_entry_list_t *get_partition_entry_list(void);
+void partition_init(unsigned int image_id);
+
+#endif /* PARTITION_H */
diff --git a/include/drivers/rambus/trng_ip_76.h b/include/drivers/rambus/trng_ip_76.h
new file mode 100644
index 0000000..6de8fc7
--- /dev/null
+++ b/include/drivers/rambus/trng_ip_76.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020, Marvell Technology Group Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef __TRNG_IP_76_H__
+#define __TRNG_IP_76_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+
+int32_t eip76_rng_read_rand_buf(void *data, bool wait);
+int32_t eip76_rng_probe(uintptr_t base_addr);
+int32_t eip76_rng_get_random(uint8_t *data, uint32_t len);
+
+#endif /* __TRNG_IP_76_H__ */
diff --git a/include/drivers/raw_nand.h b/include/drivers/raw_nand.h
new file mode 100644
index 0000000..7152300
--- /dev/null
+++ b/include/drivers/raw_nand.h
@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DRIVERS_RAW_NAND_H
+#define DRIVERS_RAW_NAND_H
+
+#include <cdefs.h>
+#include <stdint.h>
+
+#include <drivers/nand.h>
+
+/* NAND ONFI default value mode 0 in picosecond */
+#define NAND_TADL_MIN 400000UL
+#define NAND_TALH_MIN 20000UL
+#define NAND_TALS_MIN 50000UL
+#define NAND_TAR_MIN 25000UL
+#define NAND_TCCS_MIN 500000UL
+#define NAND_TCEA_MIN 100000UL
+#define NAND_TCEH_MIN 20000UL
+#define NAND_TCH_MIN 20000UL
+#define NAND_TCHZ_MAX 100000UL
+#define NAND_TCLH_MIN 20000UL
+#define NAND_TCLR_MIN 20000UL
+#define NAND_TCLS_MIN 50000UL
+#define NAND_TCOH_MIN 0UL
+#define NAND_TCS_MIN 70000UL
+#define NAND_TDH_MIN 20000UL
+#define NAND_TDS_MIN 40000UL
+#define NAND_TFEAT_MAX 1000000UL
+#define NAND_TIR_MIN 10000UL
+#define NAND_TITC_MIN 1000000UL
+#define NAND_TR_MAX 200000000UL
+#define NAND_TRC_MIN 100000UL
+#define NAND_TREA_MAX 40000UL
+#define NAND_TREH_MIN 30000UL
+#define NAND_TRHOH_MIN 0UL
+#define NAND_TRHW_MIN 200000UL
+#define NAND_TRHZ_MAX 200000UL
+#define NAND_TRLOH_MIN 0UL
+#define NAND_TRP_MIN 50000UL
+#define NAND_TRR_MIN 40000UL
+#define NAND_TRST_MAX 250000000000ULL
+#define NAND_TWB_MAX 200000UL
+#define NAND_TWC_MIN 100000UL
+#define NAND_TWH_MIN 30000UL
+#define NAND_TWHR_MIN 120000UL
+#define NAND_TWP_MIN 50000UL
+#define NAND_TWW_MIN 100000UL
+
+/* NAND request types */
+#define NAND_REQ_CMD 0x0000U
+#define NAND_REQ_ADDR 0x1000U
+#define NAND_REQ_DATAIN 0x2000U
+#define NAND_REQ_DATAOUT 0x3000U
+#define NAND_REQ_WAIT 0x4000U
+#define NAND_REQ_MASK GENMASK(14, 12)
+#define NAND_REQ_BUS_WIDTH_8 BIT(15)
+
+#define PARAM_PAGE_SIZE 256
+
+/* NAND ONFI commands */
+#define NAND_CMD_READ_1ST 0x00U
+#define NAND_CMD_CHANGE_1ST 0x05U
+#define NAND_CMD_READID_SIG_ADDR 0x20U
+#define NAND_CMD_READ_2ND 0x30U
+#define NAND_CMD_STATUS 0x70U
+#define NAND_CMD_READID 0x90U
+#define NAND_CMD_CHANGE_2ND 0xE0U
+#define NAND_CMD_READ_PARAM_PAGE 0xECU
+#define NAND_CMD_RESET 0xFFU
+
+#define ONFI_REV_21 BIT(3)
+#define ONFI_FEAT_BUS_WIDTH_16 BIT(0)
+#define ONFI_FEAT_EXTENDED_PARAM BIT(7)
+
+/* NAND ECC type */
+#define NAND_ECC_NONE U(0)
+#define NAND_ECC_HW U(1)
+#define NAND_ECC_ONDIE U(2)
+
+/* NAND bus width */
+#define NAND_BUS_WIDTH_8 U(0)
+#define NAND_BUS_WIDTH_16 U(1)
+
+struct nand_req {
+ struct nand_device *nand;
+ uint16_t type;
+ uint8_t *addr;
+ unsigned int length;
+ unsigned int delay_ms;
+ unsigned int inst_delay;
+};
+
+struct nand_param_page {
+ /* Rev information and feature block */
+ uint32_t page_sig;
+ uint16_t rev;
+ uint16_t features;
+ uint16_t opt_cmd;
+ uint8_t jtg;
+ uint8_t train_cmd;
+ uint16_t ext_param_length;
+ uint8_t nb_param_pages;
+ uint8_t reserved1[17];
+ /* Manufacturer information */
+ uint8_t manufacturer[12];
+ uint8_t model[20];
+ uint8_t manufacturer_id;
+ uint16_t data_code;
+ uint8_t reserved2[13];
+ /* Memory organization */
+ uint32_t bytes_per_page;
+ uint16_t spare_per_page;
+ uint32_t bytes_per_partial;
+ uint16_t spare_per_partial;
+ uint32_t num_pages_per_blk;
+ uint32_t num_blk_in_lun;
+ uint8_t num_lun;
+ uint8_t num_addr_cycles;
+ uint8_t bit_per_cell;
+ uint16_t max_bb_per_lun;
+ uint16_t blk_endur;
+ uint8_t valid_blk_begin;
+ uint16_t blk_enbur_valid;
+ uint8_t nb_prog_page;
+ uint8_t partial_prog_attr;
+ uint8_t nb_ecc_bits;
+ uint8_t plane_addr;
+ uint8_t mplanes_ops;
+ uint8_t ez_nand;
+ uint8_t reserved3[12];
+ /* Electrical parameters */
+ uint8_t io_pin_cap_max;
+ uint16_t sdr_timing_mode;
+ uint16_t sdr_prog_cache_timing;
+ uint16_t tprog;
+ uint16_t tbers;
+ uint16_t tr;
+ uint16_t tccs;
+ uint8_t nvddr_timing_mode;
+ uint8_t nvddr2_timing_mode;
+ uint8_t nvddr_features;
+ uint16_t clk_input_cap_typ;
+ uint16_t io_pin_cap_typ;
+ uint16_t input_pin_cap_typ;
+ uint8_t input_pin_cap_max;
+ uint8_t drv_strength_support;
+ uint16_t tr_max;
+ uint16_t tadl;
+ uint16_t tr_typ;
+ uint8_t reserved4[6];
+ /* Vendor block */
+ uint16_t vendor_revision;
+ uint8_t vendor[88];
+ uint16_t crc16;
+} __packed;
+
+struct nand_ctrl_ops {
+ int (*exec)(struct nand_req *req);
+ void (*setup)(struct nand_device *nand);
+};
+
+struct rawnand_device {
+ struct nand_device *nand_dev;
+ const struct nand_ctrl_ops *ops;
+};
+
+int nand_raw_init(unsigned long long *size, unsigned int *erase_size);
+int nand_wait_ready(unsigned int delay_ms);
+int nand_read_page_cmd(unsigned int page, unsigned int offset,
+ uintptr_t buffer, unsigned int len);
+int nand_change_read_column_cmd(unsigned int offset, uintptr_t buffer,
+ unsigned int len);
+void nand_raw_ctrl_init(const struct nand_ctrl_ops *ops);
+
+/*
+ * Platform can implement this to override default raw NAND instance
+ * configuration.
+ *
+ * @device: target raw NAND instance.
+ * Return 0 on success, negative value otherwise.
+ */
+int plat_get_raw_nand_data(struct rawnand_device *device);
+
+#endif /* DRIVERS_RAW_NAND_H */
diff --git a/include/drivers/renesas/rcar/console/console.h b/include/drivers/renesas/rcar/console/console.h
new file mode 100644
index 0000000..7d5b5d3
--- /dev/null
+++ b/include/drivers/renesas/rcar/console/console.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RCAR_PRINTF_H
+#define RCAR_PRINTF_H
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+/*
+ * Initialize a new rcar console instance and register it with the console
+ * framework. The |console| pointer must point to storage that will be valid
+ * for the lifetime of the console, such as a global or static local variable.
+ * Its contents will be reinitialized from scratch.
+ */
+int console_rcar_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
+ console_t *console);
+
+#endif /*__ASSEMBLER__*/
+
+#endif /* RCAR_PRINTF_H */
diff --git a/include/drivers/rpi3/gpio/rpi3_gpio.h b/include/drivers/rpi3/gpio/rpi3_gpio.h
new file mode 100644
index 0000000..7bb3ee2
--- /dev/null
+++ b/include/drivers/rpi3/gpio/rpi3_gpio.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019, Linaro Limited
+ * Copyright (c) 2019, Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RPI3_GPIO_H
+#define RPI3_GPIO_H
+
+#include <stdint.h>
+#include <drivers/gpio.h>
+
+void rpi3_gpio_init(void);
+int rpi3_gpio_get_select(int gpio);
+void rpi3_gpio_set_select(int gpio, int fsel);
+
+#define RPI3_GPIO_GPFSEL(n) ((n) * U(0x04))
+#define RPI3_GPIO_GPSET(n) (((n) * U(0x04)) + U(0x1C))
+#define RPI3_GPIO_GPCLR(n) (((n) * U(0x04)) + U(0x28))
+#define RPI3_GPIO_GPLEV(n) (((n) * U(0x04)) + U(0x34))
+#define RPI3_GPIO_GPPUD U(0x94)
+#define RPI3_GPIO_GPPUDCLK(n) (((n) * U(0x04)) + U(0x98))
+
+#define RPI3_GPIO_FUNC_INPUT U(0)
+#define RPI3_GPIO_FUNC_OUTPUT U(1)
+#define RPI3_GPIO_FUNC_ALT0 U(4)
+#define RPI3_GPIO_FUNC_ALT1 U(5)
+#define RPI3_GPIO_FUNC_ALT2 U(6)
+#define RPI3_GPIO_FUNC_ALT3 U(7)
+#define RPI3_GPIO_FUNC_ALT4 U(3)
+#define RPI3_GPIO_FUNC_ALT5 U(2)
+
+#endif /* RPI3_GPIO_H */
diff --git a/include/drivers/rpi3/mailbox/rpi3_mbox.h b/include/drivers/rpi3/mailbox/rpi3_mbox.h
new file mode 100644
index 0000000..c107440
--- /dev/null
+++ b/include/drivers/rpi3/mailbox/rpi3_mbox.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RPI3_MBOX_H
+#define RPI3_MBOX_H
+
+#include <stdint.h>
+
+/* This struct must be aligned to 16 bytes */
+typedef struct __packed __aligned(16) rpi3_mbox_request {
+ uint32_t size; /* Buffer size in bytes */
+ uint32_t code; /* Request/response code */
+ uint32_t tags[0];
+} rpi3_mbox_request_t;
+
+#define RPI3_MBOX_BUFFER_SIZE U(256)
+
+/* Constants to perform a request/check the status of a request. */
+#define RPI3_MBOX_PROCESS_REQUEST U(0x00000000)
+#define RPI3_MBOX_REQUEST_SUCCESSFUL U(0x80000000)
+#define RPI3_MBOX_REQUEST_ERROR U(0x80000001)
+
+/* Command constants */
+#define RPI3_TAG_HARDWARE_GET_BOARD_REVISION U(0x00010002)
+#define RPI3_TAG_END U(0x00000000)
+
+#define RPI3_TAG_REQUEST U(0x00000000)
+#define RPI3_TAG_IS_RESPONSE U(0x80000000) /* Set if response */
+#define RPI3_TAG_RESPONSE_LENGTH_MASK U(0x7FFFFFFF)
+
+#define RPI3_CHANNEL_ARM_TO_VC U(0x8)
+#define RPI3_CHANNEL_MASK U(0xF)
+
+void rpi3_vc_mailbox_request_send(rpi3_mbox_request_t *req, int req_size);
+
+#endif
diff --git a/include/drivers/rpi3/rng/rpi3_rng.h b/include/drivers/rpi3/rng/rpi3_rng.h
new file mode 100644
index 0000000..ea5a677
--- /dev/null
+++ b/include/drivers/rpi3/rng/rpi3_rng.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RPI3_RNG_H
+#define RPI3_RNG_H
+
+void rpi3_rng_read(void *buf, size_t len);
+
+#endif
diff --git a/include/drivers/rpi3/sdhost/rpi3_sdhost.h b/include/drivers/rpi3/sdhost/rpi3_sdhost.h
new file mode 100644
index 0000000..1653240
--- /dev/null
+++ b/include/drivers/rpi3/sdhost/rpi3_sdhost.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2019, Linaro Limited
+ * Copyright (c) 2019, Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RPI3_SDHOST_H
+#define RPI3_SDHOST_H
+
+#include <drivers/mmc.h>
+#include <stdint.h>
+#include <platform_def.h>
+
+struct rpi3_sdhost_params {
+ uintptr_t reg_base;
+ uint32_t clk_rate;
+ uint32_t bus_width;
+ uint32_t flags;
+ uint32_t current_cmd;
+ uint8_t cmdbusy;
+ uint8_t mmc_app_cmd;
+ uint32_t ns_per_fifo_word;
+
+ uint32_t sdcard_rca;
+ uint32_t gpio48_pinselect[6];
+};
+
+void rpi3_sdhost_init(struct rpi3_sdhost_params *params,
+ struct mmc_device_info *mmc_dev_info);
+void rpi3_sdhost_stop(void);
+
+/* Registers */
+#define HC_COMMAND 0x00 /* Command and flags */
+#define HC_ARGUMENT 0x04
+#define HC_TIMEOUTCOUNTER 0x08
+#define HC_CLOCKDIVISOR 0x0c
+#define HC_RESPONSE_0 0x10
+#define HC_RESPONSE_1 0x14
+#define HC_RESPONSE_2 0x18
+#define HC_RESPONSE_3 0x1c
+#define HC_HOSTSTATUS 0x20
+#define HC_POWER 0x30
+#define HC_DEBUG 0x34
+#define HC_HOSTCONFIG 0x38
+#define HC_BLOCKSIZE 0x3c
+#define HC_DATAPORT 0x40
+#define HC_BLOCKCOUNT 0x50
+
+/* Flags for HC_COMMAND register */
+#define HC_CMD_ENABLE 0x8000
+#define HC_CMD_FAILED 0x4000
+#define HC_CMD_BUSY 0x0800
+#define HC_CMD_RESPONSE_NONE 0x0400
+#define HC_CMD_RESPONSE_LONG 0x0200
+#define HC_CMD_WRITE 0x0080
+#define HC_CMD_READ 0x0040
+#define HC_CMD_COMMAND_MASK 0x003f
+
+#define HC_CLOCKDIVISOR_MAXVAL 0x07ff
+#define HC_CLOCKDIVISOR_PREFERVAL 0x027b
+#define HC_CLOCKDIVISOR_SLOWVAL 0x0148
+#define HC_CLOCKDIVISOR_STOPVAL 0x01fb
+
+/* Flags for HC_HOSTSTATUS register */
+#define HC_HSTST_HAVEDATA 0x0001
+#define HC_HSTST_ERROR_FIFO 0x0008
+#define HC_HSTST_ERROR_CRC7 0x0010
+#define HC_HSTST_ERROR_CRC16 0x0020
+#define HC_HSTST_TIMEOUT_CMD 0x0040
+#define HC_HSTST_TIMEOUT_DATA 0x0080
+#define HC_HSTST_INT_BLOCK 0x0200
+#define HC_HSTST_INT_BUSY 0x0400
+
+#define HC_HSTST_RESET 0xffff
+
+#define HC_HSTST_MASK_ERROR_DATA (HC_HSTST_ERROR_FIFO | \
+ HC_HSTST_ERROR_CRC7 | \
+ HC_HSTST_ERROR_CRC16 | \
+ HC_HSTST_TIMEOUT_DATA)
+
+#define HC_HSTST_MASK_ERROR_ALL (HC_HSTST_MASK_ERROR_DATA | \
+ HC_HSTST_TIMEOUT_CMD)
+
+/* Flags for HC_HOSTCONFIG register */
+#define HC_HSTCF_INTBUS_WIDE 0x0002
+#define HC_HSTCF_EXTBUS_4BIT 0x0004
+#define HC_HSTCF_SLOW_CARD 0x0008
+#define HC_HSTCF_INT_DATA 0x0010
+#define HC_HSTCF_INT_BLOCK 0x0100
+#define HC_HSTCF_INT_BUSY 0x0400
+
+/* Flags for HC_DEBUG register */
+#define HC_DBG_FIFO_THRESH_WRITE_SHIFT 9
+#define HC_DBG_FIFO_THRESH_READ_SHIFT 14
+#define HC_DBG_FIFO_THRESH_MASK 0x001f
+#define HC_DBG_FSM_MASK 0xf
+#define HC_DBG_FSM_IDENTMODE 0x0
+#define HC_DBG_FSM_DATAMODE 0x1
+#define HC_DBG_FSM_READDATA 0x2
+#define HC_DBG_FSM_WRITEDATA 0x3
+#define HC_DBG_FSM_READWAIT 0x4
+#define HC_DBG_FSM_READCRC 0x5
+#define HC_DBG_FSM_WRITECRC 0x6
+#define HC_DBG_FSM_WRITEWAIT1 0x7
+#define HC_DBG_FSM_POWERDOWN 0x8
+#define HC_DBG_FSM_POWERUP 0x9
+#define HC_DBG_FSM_WRITESTART1 0xa
+#define HC_DBG_FSM_WRITESTART2 0xb
+#define HC_DBG_FSM_GENPULSES 0xc
+#define HC_DBG_FSM_WRITEWAIT2 0xd
+#define HC_DBG_FSM_STARTPOWDOWN 0xf
+#define HC_DBG_FORCE_DATA_MODE 0x40000
+
+/* Settings */
+#define HC_FIFO_SIZE 16
+#define HC_FIFO_THRESH_READ 4
+#define HC_FIFO_THRESH_WRITE 4
+
+#define HC_TIMEOUT_DEFAULT 0x00f00000
+#define HC_TIMEOUT_IDLE 0x00a00000
+
+#endif /* RPI3_SDHOST_H */
diff --git a/include/drivers/scmi-msg.h b/include/drivers/scmi-msg.h
new file mode 100644
index 0000000..a9a99cf
--- /dev/null
+++ b/include/drivers/scmi-msg.h
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#ifndef SCMI_MSG_H
+#define SCMI_MSG_H
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+/* Minimum size expected for SMT based shared memory message buffers */
+#define SMT_BUF_SLOT_SIZE 128U
+
+/* A channel abstract a communication path between agent and server */
+struct scmi_msg_channel;
+
+/*
+ * struct scmi_msg_channel - Shared memory buffer for a agent-to-server channel
+ *
+ * @shm_addr: Address of the shared memory for the SCMI channel
+ * @shm_size: Byte size of the shared memory for the SCMI channel
+ * @busy: True when channel is busy, flase when channel is free
+ * @agent_name: Agent name, SCMI protocol exposes 16 bytes max, or NULL
+ */
+struct scmi_msg_channel {
+ uintptr_t shm_addr;
+ size_t shm_size;
+ bool busy;
+ const char *agent_name;
+};
+
+/*
+ * Initialize SMT memory buffer, called by platform at init for each
+ * agent channel using the SMT header format.
+ *
+ * @chan: Pointer to the channel shared memory to be initialized
+ */
+void scmi_smt_init_agent_channel(struct scmi_msg_channel *chan);
+
+/*
+ * Process SMT formatted message in a fastcall SMC execution context.
+ * Called by platform on SMC entry. When returning, output message is
+ * available in shared memory for agent to read the response.
+ *
+ * @agent_id: SCMI agent ID the SMT belongs to
+ */
+void scmi_smt_fastcall_smc_entry(unsigned int agent_id);
+
+/*
+ * Process SMT formatted message in a secure interrupt execution context.
+ * Called by platform interrupt handler. When returning, output message is
+ * available in shared memory for agent to read the response.
+ *
+ * @agent_id: SCMI agent ID the SMT belongs to
+ */
+void scmi_smt_interrupt_entry(unsigned int agent_id);
+
+/* Platform callback functions */
+
+/*
+ * Return the SCMI channel related to an agent
+ * @agent_id: SCMI agent ID
+ * Return a pointer to channel on success, NULL otherwise
+ */
+struct scmi_msg_channel *plat_scmi_get_channel(unsigned int agent_id);
+
+/*
+ * Return how many SCMI protocols supported by the platform
+ * According to the SCMI specification, this function does not target
+ * a specific agent ID and shall return all platform known capabilities.
+ */
+size_t plat_scmi_protocol_count(void);
+
+/*
+ * Get the count and list of SCMI protocols (but base) supported for an agent
+ *
+ * @agent_id: SCMI agent ID
+ * Return a pointer to a null terminated array supported protocol IDs.
+ */
+const uint8_t *plat_scmi_protocol_list(unsigned int agent_id);
+
+/* Get the name of the SCMI vendor for the platform */
+const char *plat_scmi_vendor_name(void);
+
+/* Get the name of the SCMI sub-vendor for the platform */
+const char *plat_scmi_sub_vendor_name(void);
+
+/* Handlers for SCMI Clock protocol services */
+
+/*
+ * Return number of clock controllers for an agent
+ * @agent_id: SCMI agent ID
+ * Return number of clock controllers
+ */
+size_t plat_scmi_clock_count(unsigned int agent_id);
+
+/*
+ * Get clock controller string ID (aka name)
+ * @agent_id: SCMI agent ID
+ * @scmi_id: SCMI clock ID
+ * Return pointer to name or NULL
+ */
+const char *plat_scmi_clock_get_name(unsigned int agent_id,
+ unsigned int scmi_id);
+
+/*
+ * Get clock possible rate as an array of frequencies in Hertz.
+ *
+ * @agent_id: SCMI agent ID
+ * @scmi_id: SCMI clock ID
+ * @rates: If NULL, function returns, else output rates array
+ * @nb_elts: Array size of @rates.
+ * Return an SCMI compliant error code
+ */
+int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id,
+ unsigned long *rates, size_t *nb_elts);
+
+/*
+ * Get clock possible rate as range with regular steps in Hertz
+ *
+ * @agent_id: SCMI agent ID
+ * @scmi_id: SCMI clock ID
+ * @min_max_step: 3 cell array for min, max and step rate data
+ * Return an SCMI compliant error code
+ */
+int32_t plat_scmi_clock_rates_by_step(unsigned int agent_id,
+ unsigned int scmi_id,
+ unsigned long *min_max_step);
+
+/*
+ * Get clock rate in Hertz
+ * @agent_id: SCMI agent ID
+ * @scmi_id: SCMI clock ID
+ * Return clock rate or 0 if not supported
+ */
+unsigned long plat_scmi_clock_get_rate(unsigned int agent_id,
+ unsigned int scmi_id);
+
+/*
+ * Set clock rate in Hertz
+ * @agent_id: SCMI agent ID
+ * @scmi_id: SCMI clock ID
+ * @rate: Target clock frequency in Hertz
+ * Return a compliant SCMI error code
+ */
+int32_t plat_scmi_clock_set_rate(unsigned int agent_id, unsigned int scmi_id,
+ unsigned long rate);
+
+/*
+ * Get clock state (enabled or disabled)
+ * @agent_id: SCMI agent ID
+ * @scmi_id: SCMI clock ID
+ * Return 1 if clock is enabled, 0 if disables, or a negative SCMI error code
+ */
+int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id);
+
+/*
+ * Get clock state (enabled or disabled)
+ * @agent_id: SCMI agent ID
+ * @scmi_id: SCMI clock ID
+ * @enable_not_disable: Enable clock if true, disable clock otherwise
+ * Return a compliant SCMI error code
+ */
+int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id,
+ bool enable_not_disable);
+
+/* Handlers for SCMI Reset Domain protocol services */
+
+/*
+ * Return number of reset domains for the agent
+ * @agent_id: SCMI agent ID
+ * Return number of reset domains
+ */
+size_t plat_scmi_rstd_count(unsigned int agent_id);
+
+/*
+ * Get reset domain string ID (aka name)
+ * @agent_id: SCMI agent ID
+ * @scmi_id: SCMI reset domain ID
+ * Return pointer to name or NULL
+ */
+const char *plat_scmi_rstd_get_name(unsigned int agent_id, unsigned int scmi_id);
+
+/*
+ * Perform a reset cycle on a target reset domain
+ * @agent_id: SCMI agent ID
+ * @scmi_id: SCMI reset domain ID
+ * @state: Target reset state (see SCMI specification, 0 means context loss)
+ * Return a compliant SCMI error code
+ */
+int32_t plat_scmi_rstd_autonomous(unsigned int agent_id, unsigned int scmi_id,
+ unsigned int state);
+
+/*
+ * Assert or deassert target reset domain
+ * @agent_id: SCMI agent ID
+ * @scmi_id: SCMI reset domain ID
+ * @assert_not_deassert: Assert domain if true, otherwise deassert domain
+ * Return a compliant SCMI error code
+ */
+int32_t plat_scmi_rstd_set_state(unsigned int agent_id, unsigned int scmi_id,
+ bool assert_not_deassert);
+
+#endif /* SCMI_MSG_H */
diff --git a/include/drivers/scmi.h b/include/drivers/scmi.h
new file mode 100644
index 0000000..ac5dc38
--- /dev/null
+++ b/include/drivers/scmi.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.
+ */
+#ifndef SCMI_MSG_SCMI_H
+#define SCMI_MSG_SCMI_H
+
+#define SCMI_PROTOCOL_ID_BASE 0x10U
+#define SCMI_PROTOCOL_ID_POWER_DOMAIN 0x11U
+#define SCMI_PROTOCOL_ID_SYS_POWER 0x12U
+#define SCMI_PROTOCOL_ID_PERF 0x13U
+#define SCMI_PROTOCOL_ID_CLOCK 0x14U
+#define SCMI_PROTOCOL_ID_SENSOR 0x15U
+#define SCMI_PROTOCOL_ID_RESET_DOMAIN 0x16U
+
+/* SCMI error codes reported to agent through server-to-agent messages */
+#define SCMI_SUCCESS 0
+#define SCMI_NOT_SUPPORTED (-1)
+#define SCMI_INVALID_PARAMETERS (-2)
+#define SCMI_DENIED (-3)
+#define SCMI_NOT_FOUND (-4)
+#define SCMI_OUT_OF_RANGE (-5)
+#define SCMI_BUSY (-6)
+#define SCMI_COMMS_ERROR (-7)
+#define SCMI_GENERIC_ERROR (-8)
+#define SCMI_HARDWARE_ERROR (-9)
+#define SCMI_PROTOCOL_ERROR (-10)
+
+#endif /* SCMI_MSG_SCMI_H */
diff --git a/include/drivers/spi_mem.h b/include/drivers/spi_mem.h
new file mode 100644
index 0000000..d1953ac
--- /dev/null
+++ b/include/drivers/spi_mem.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DRIVERS_SPI_MEM_H
+#define DRIVERS_SPI_MEM_H
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#define SPI_MEM_BUSWIDTH_1_LINE 1U
+#define SPI_MEM_BUSWIDTH_2_LINE 2U
+#define SPI_MEM_BUSWIDTH_4_LINE 4U
+
+/*
+ * enum spi_mem_data_dir - Describes the direction of a SPI memory data
+ * transfer from the controller perspective.
+ * @SPI_MEM_DATA_IN: data coming from the SPI memory.
+ * @SPI_MEM_DATA_OUT: data sent to the SPI memory.
+ */
+enum spi_mem_data_dir {
+ SPI_MEM_DATA_IN,
+ SPI_MEM_DATA_OUT,
+};
+
+/*
+ * struct spi_mem_op - Describes a SPI memory operation.
+ *
+ * @cmd.buswidth: Number of IO lines used to transmit the command.
+ * @cmd.opcode: Operation opcode.
+ * @addr.nbytes: Number of address bytes to send. Can be zero if the operation
+ * does not need to send an address.
+ * @addr.buswidth: Number of IO lines used to transmit the address.
+ * @addr.val: Address value. This value is always sent MSB first on the bus.
+ * Note that only @addr.nbytes are taken into account in this
+ * address value, so users should make sure the value fits in the
+ * assigned number of bytes.
+ * @dummy.nbytes: Number of dummy bytes to send after an opcode or address. Can
+ * be zero if the operation does not require dummy bytes.
+ * @dummy.buswidth: Number of IO lines used to transmit the dummy bytes.
+ * @data.buswidth: Number of IO lines used to send/receive the data.
+ * @data.dir: Direction of the transfer.
+ * @data.nbytes: Number of data bytes to transfer.
+ * @data.buf: Input or output data buffer depending on data::dir.
+ */
+struct spi_mem_op {
+ struct {
+ uint8_t buswidth;
+ uint8_t opcode;
+ } cmd;
+
+ struct {
+ uint8_t nbytes;
+ uint8_t buswidth;
+ uint64_t val;
+ } addr;
+
+ struct {
+ uint8_t nbytes;
+ uint8_t buswidth;
+ } dummy;
+
+ struct {
+ uint8_t buswidth;
+ enum spi_mem_data_dir dir;
+ unsigned int nbytes;
+ void *buf;
+ } data;
+};
+
+/* SPI mode flags */
+#define SPI_CPHA BIT(0) /* clock phase */
+#define SPI_CPOL BIT(1) /* clock polarity */
+#define SPI_CS_HIGH BIT(2) /* CS active high */
+#define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */
+#define SPI_3WIRE BIT(4) /* SI/SO signals shared */
+#define SPI_PREAMBLE BIT(5) /* Skip preamble bytes */
+#define SPI_TX_DUAL BIT(6) /* transmit with 2 wires */
+#define SPI_TX_QUAD BIT(7) /* transmit with 4 wires */
+#define SPI_RX_DUAL BIT(8) /* receive with 2 wires */
+#define SPI_RX_QUAD BIT(9) /* receive with 4 wires */
+
+struct spi_bus_ops {
+ /*
+ * Claim the bus and prepare it for communication.
+ *
+ * @cs: The chip select.
+ * Returns: 0 if the bus was claimed successfully, or a negative value
+ * if it wasn't.
+ */
+ int (*claim_bus)(unsigned int cs);
+
+ /*
+ * Release the SPI bus.
+ */
+ void (*release_bus)(void);
+
+ /*
+ * Set transfer speed.
+ *
+ * @hz: The transfer speed in Hertz.
+ * Returns: 0 on success, a negative error code otherwise.
+ */
+ int (*set_speed)(unsigned int hz);
+
+ /*
+ * Set the SPI mode/flags.
+ *
+ * @mode: Requested SPI mode (SPI_... flags).
+ * Returns: 0 on success, a negative error code otherwise.
+ */
+ int (*set_mode)(unsigned int mode);
+
+ /*
+ * Execute a SPI memory operation.
+ *
+ * @op: The memory operation to execute.
+ * Returns: 0 on success, a negative error code otherwise.
+ */
+ int (*exec_op)(const struct spi_mem_op *op);
+};
+
+int spi_mem_exec_op(const struct spi_mem_op *op);
+int spi_mem_init_slave(void *fdt, int bus_node,
+ const struct spi_bus_ops *ops);
+
+#endif /* DRIVERS_SPI_MEM_H */
diff --git a/include/drivers/spi_nand.h b/include/drivers/spi_nand.h
new file mode 100644
index 0000000..40e2063
--- /dev/null
+++ b/include/drivers/spi_nand.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DRIVERS_SPI_NAND_H
+#define DRIVERS_SPI_NAND_H
+
+#include <drivers/nand.h>
+#include <drivers/spi_mem.h>
+
+#define SPI_NAND_OP_GET_FEATURE 0x0FU
+#define SPI_NAND_OP_SET_FEATURE 0x1FU
+#define SPI_NAND_OP_READ_ID 0x9FU
+#define SPI_NAND_OP_LOAD_PAGE 0x13U
+#define SPI_NAND_OP_RESET 0xFFU
+#define SPI_NAND_OP_READ_FROM_CACHE 0x03U
+#define SPI_NAND_OP_READ_FROM_CACHE_2X 0x3BU
+#define SPI_NAND_OP_READ_FROM_CACHE_4X 0x6BU
+
+/* Configuration register */
+#define SPI_NAND_REG_CFG 0xB0U
+#define SPI_NAND_CFG_ECC_EN BIT(4)
+#define SPI_NAND_CFG_QE BIT(0)
+
+/* Status register */
+#define SPI_NAND_REG_STATUS 0xC0U
+#define SPI_NAND_STATUS_BUSY BIT(0)
+#define SPI_NAND_STATUS_ECC_UNCOR BIT(5)
+
+struct spinand_device {
+ struct nand_device *nand_dev;
+ struct spi_mem_op spi_read_cache_op;
+ uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */
+};
+
+int spi_nand_init(unsigned long long *size, unsigned int *erase_size);
+
+/*
+ * Platform can implement this to override default SPI-NAND instance
+ * configuration.
+ *
+ * @device: target SPI-NAND instance.
+ * Return 0 on success, negative value otherwise.
+ */
+int plat_get_spi_nand_data(struct spinand_device *device);
+
+#endif /* DRIVERS_SPI_NAND_H */
diff --git a/include/drivers/spi_nor.h b/include/drivers/spi_nor.h
new file mode 100644
index 0000000..72cfe5b
--- /dev/null
+++ b/include/drivers/spi_nor.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DRIVERS_SPI_NOR_H
+#define DRIVERS_SPI_NOR_H
+
+#include <drivers/spi_mem.h>
+
+/* OPCODE */
+#define SPI_NOR_OP_WREN 0x06U /* Write enable */
+#define SPI_NOR_OP_WRSR 0x01U /* Write status register 1 byte */
+#define SPI_NOR_OP_READ_ID 0x9FU /* Read JEDEC ID */
+#define SPI_NOR_OP_READ_CR 0x35U /* Read configuration register */
+#define SPI_NOR_OP_READ_SR 0x05U /* Read status register */
+#define SPI_NOR_OP_READ_FSR 0x70U /* Read flag status register */
+#define SPINOR_OP_RDEAR 0xC8U /* Read Extended Address Register */
+#define SPINOR_OP_WREAR 0xC5U /* Write Extended Address Register */
+
+/* Used for Spansion flashes only. */
+#define SPINOR_OP_BRWR 0x17U /* Bank register write */
+#define SPINOR_OP_BRRD 0x16U /* Bank register read */
+
+#define SPI_NOR_OP_READ 0x03U /* Read data bytes (low frequency) */
+#define SPI_NOR_OP_READ_FAST 0x0BU /* Read data bytes (high frequency) */
+#define SPI_NOR_OP_READ_1_1_2 0x3BU /* Read data bytes (Dual Output SPI) */
+#define SPI_NOR_OP_READ_1_2_2 0xBBU /* Read data bytes (Dual I/O SPI) */
+#define SPI_NOR_OP_READ_1_1_4 0x6BU /* Read data bytes (Quad Output SPI) */
+#define SPI_NOR_OP_READ_1_4_4 0xEBU /* Read data bytes (Quad I/O SPI) */
+
+/* Flags for NOR specific configuration */
+#define SPI_NOR_USE_FSR BIT(0)
+#define SPI_NOR_USE_BANK BIT(1)
+
+struct nor_device {
+ struct spi_mem_op read_op;
+ uint32_t size;
+ uint32_t flags;
+ uint8_t selected_bank;
+ uint8_t bank_write_cmd;
+ uint8_t bank_read_cmd;
+};
+
+int spi_nor_read(unsigned int offset, uintptr_t buffer, size_t length,
+ size_t *length_read);
+int spi_nor_init(unsigned long long *device_size, unsigned int *erase_size);
+
+/*
+ * Platform can implement this to override default NOR instance configuration.
+ *
+ * @device: target NOR instance.
+ * Return 0 on success, negative value otherwise.
+ */
+int plat_get_nor_data(struct nor_device *device);
+
+#endif /* DRIVERS_SPI_NOR_H */
diff --git a/include/drivers/st/bsec.h b/include/drivers/st/bsec.h
new file mode 100644
index 0000000..60dcf3c
--- /dev/null
+++ b/include/drivers/st/bsec.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BSEC_H
+#define BSEC_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <lib/utils_def.h>
+
+/*
+ * IP configuration
+ */
+#define BSEC_OTP_MASK GENMASK(4, 0)
+#define BSEC_OTP_BANK_SHIFT 5
+#define BSEC_TIMEOUT_VALUE 0xFFFF
+
+/*
+ * Return status
+ */
+#define BSEC_OK 0U
+#define BSEC_ERROR 0xFFFFFFFFU
+#define BSEC_DISTURBED 0xFFFFFFFEU
+#define BSEC_INVALID_PARAM 0xFFFFFFFCU
+#define BSEC_PROG_FAIL 0xFFFFFFFBU
+#define BSEC_LOCK_FAIL 0xFFFFFFFAU
+#define BSEC_TIMEOUT 0xFFFFFFF9U
+#define BSEC_RETRY 0xFFFFFFF8U
+#define BSEC_NOT_SUPPORTED 0xFFFFFFF7U
+#define BSEC_WRITE_LOCKED 0xFFFFFFF6U
+#define BSEC_ERROR_INVALID_FVR 0xFFFFFFF5U
+
+/*
+ * OTP MODE
+ */
+#define BSEC_MODE_OPEN1 0x00U
+#define BSEC_MODE_SECURED 0x01U
+#define BSEC_MODE_OPEN2 0x02U
+#define BSEC_MODE_INVALID 0x04U
+
+/*
+ * OTP Lock services definition.
+ * Value must corresponding to the bit number in the register.
+ * Special case: (bit number << 1) for BSEC3.
+ */
+#define BSEC_LOCK_UPPER_OTP 0x00
+#define BSEC_LOCK_GWLOCK 0x01
+#define BSEC_LOCK_DEBUG 0x02
+#define BSEC_LOCK_PROGRAM 0x03
+#define BSEC_LOCK_KVLOCK 0x04
+
+/*
+ * Values for struct bsec_config::freq
+ */
+#define FREQ_10_20_MHZ 0x0
+#define FREQ_20_30_MHZ 0x1
+#define FREQ_30_45_MHZ 0x2
+#define FREQ_45_67_MHZ 0x3
+
+/*
+ * Device info structure, providing device-specific functions and a means of
+ * adding driver-specific state.
+ */
+struct bsec_config {
+ uint8_t den_lock; /*
+ * Debug enable sticky lock
+ * 1 debug enable is locked until next reset
+ */
+
+ /* BSEC2 only */
+ uint8_t tread; /* SAFMEM Reading current level default 0 */
+ uint8_t pulse_width; /* SAFMEM Programming pulse width default 1 */
+ uint8_t freq; /*
+ * SAFMEM CLOCK see freq value define
+ * default FREQ_45_67_MHZ
+ */
+ uint8_t power; /* Power up SAFMEM. 1 power up, 0 power off */
+ uint8_t prog_lock; /*
+ * Programming Sticky lock
+ * 1 programming is locked until next reset
+ */
+ uint8_t upper_otp_lock; /*
+ * Shadowing of upper OTP sticky lock
+ * 1 shadowing of upper OTP is locked
+ * until next reset
+ */
+};
+
+uint32_t bsec_probe(void);
+uint32_t bsec_get_base(void);
+
+uint32_t bsec_set_config(struct bsec_config *cfg);
+uint32_t bsec_get_config(struct bsec_config *cfg);
+
+uint32_t bsec_shadow_register(uint32_t otp);
+uint32_t bsec_read_otp(uint32_t *val, uint32_t otp);
+uint32_t bsec_write_otp(uint32_t val, uint32_t otp);
+uint32_t bsec_program_otp(uint32_t val, uint32_t otp);
+uint32_t bsec_permanent_lock_otp(uint32_t otp);
+
+void bsec_write_debug_conf(uint32_t val);
+uint32_t bsec_read_debug_conf(void);
+
+void bsec_write_scratch(uint32_t val);
+uint32_t bsec_read_scratch(void);
+
+uint32_t bsec_get_status(void);
+uint32_t bsec_get_hw_conf(void);
+uint32_t bsec_get_version(void);
+uint32_t bsec_get_id(void);
+uint32_t bsec_get_magic_id(void);
+
+uint32_t bsec_set_sr_lock(uint32_t otp);
+uint32_t bsec_read_sr_lock(uint32_t otp, bool *value);
+uint32_t bsec_set_sw_lock(uint32_t otp);
+uint32_t bsec_read_sw_lock(uint32_t otp, bool *value);
+uint32_t bsec_set_sp_lock(uint32_t otp);
+uint32_t bsec_read_sp_lock(uint32_t otp, bool *value);
+uint32_t bsec_read_permanent_lock(uint32_t otp, bool *value);
+uint32_t bsec_otp_lock(uint32_t service);
+
+uint32_t bsec_shadow_read_otp(uint32_t *otp_value, uint32_t word);
+uint32_t bsec_check_nsec_access_rights(uint32_t otp);
+
+#endif /* BSEC_H */
diff --git a/include/drivers/st/bsec2_reg.h b/include/drivers/st/bsec2_reg.h
new file mode 100644
index 0000000..f895020
--- /dev/null
+++ b/include/drivers/st/bsec2_reg.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BSEC2_REG_H
+#define BSEC2_REG_H
+
+#include <lib/utils_def.h>
+
+/* IP configuration */
+#define ADDR_LOWER_OTP_PERLOCK_SHIFT 0x03
+#define DATA_LOWER_OTP_PERLOCK_BIT 0x03U /* 2 significants bits are used */
+#define DATA_LOWER_OTP_PERLOCK_MASK GENMASK(2, 0)
+#define ADDR_UPPER_OTP_PERLOCK_SHIFT 0x04
+#define DATA_UPPER_OTP_PERLOCK_BIT 0x01U /* 1 significants bits are used */
+#define DATA_UPPER_OTP_PERLOCK_MASK GENMASK(3, 0)
+
+/* BSEC REGISTER OFFSET (base relative) */
+#define BSEC_OTP_CONF_OFF U(0x000)
+#define BSEC_OTP_CTRL_OFF U(0x004)
+#define BSEC_OTP_WRDATA_OFF U(0x008)
+#define BSEC_OTP_STATUS_OFF U(0x00C)
+#define BSEC_OTP_LOCK_OFF U(0x010)
+#define BSEC_DEN_OFF U(0x014)
+#define BSEC_DISTURBED_OFF U(0x01C)
+#define BSEC_DISTURBED1_OFF U(0x020)
+#define BSEC_DISTURBED2_OFF U(0x024)
+#define BSEC_ERROR_OFF U(0x034)
+#define BSEC_ERROR1_OFF U(0x038)
+#define BSEC_ERROR2_OFF U(0x03C)
+#define BSEC_WRLOCK_OFF U(0x04C) /* Safmem permanent lock */
+#define BSEC_WRLOCK1_OFF U(0x050)
+#define BSEC_WRLOCK2_OFF U(0x054)
+#define BSEC_SPLOCK_OFF U(0x064) /* Program safmem sticky lock */
+#define BSEC_SPLOCK1_OFF U(0x068)
+#define BSEC_SPLOCK2_OFF U(0x06C)
+#define BSEC_SWLOCK_OFF U(0x07C) /* Write in OTP sticky lock */
+#define BSEC_SWLOCK1_OFF U(0x080)
+#define BSEC_SWLOCK2_OFF U(0x084)
+#define BSEC_SRLOCK_OFF U(0x094) /* Shadowing sticky lock */
+#define BSEC_SRLOCK1_OFF U(0x098)
+#define BSEC_SRLOCK2_OFF U(0x09C)
+#define BSEC_JTAG_IN_OFF U(0x0AC)
+#define BSEC_JTAG_OUT_OFF U(0x0B0)
+#define BSEC_SCRATCH_OFF U(0x0B4)
+#define BSEC_OTP_DATA_OFF U(0x200)
+#define BSEC_IPHW_CFG_OFF U(0xFF0)
+#define BSEC_IPVR_OFF U(0xFF4)
+#define BSEC_IP_ID_OFF U(0xFF8)
+#define BSEC_IP_MAGIC_ID_OFF U(0xFFC)
+
+#define BSEC_WRLOCK(n) (BSEC_WRLOCK_OFF + U(0x04) * (n))
+#define BSEC_SPLOCK(n) (BSEC_SPLOCK_OFF + U(0x04) * (n))
+#define BSEC_SWLOCK(n) (BSEC_SWLOCK_OFF + U(0x04) * (n))
+#define BSEC_SRLOCK(n) (BSEC_SRLOCK_OFF + U(0x04) * (n))
+
+/* BSEC_CONFIGURATION Register */
+#define BSEC_CONF_POWER_UP_MASK BIT(0)
+#define BSEC_CONF_POWER_UP_SHIFT 0
+#define BSEC_CONF_FRQ_MASK GENMASK(2, 1)
+#define BSEC_CONF_FRQ_SHIFT 1
+#define BSEC_CONF_PRG_WIDTH_MASK GENMASK(6, 3)
+#define BSEC_CONF_PRG_WIDTH_SHIFT 3
+#define BSEC_CONF_TREAD_MASK GENMASK(8, 7)
+#define BSEC_CONF_TREAD_SHIFT 7
+
+/* BSEC_CONTROL Register */
+#define BSEC_READ 0U
+#define BSEC_WRITE BIT(8)
+#define BSEC_LOCK BIT(9)
+
+/* BSEC_OTP_LOCK register */
+#define UPPER_OTP_LOCK_MASK BIT(0)
+#define UPPER_OTP_LOCK_SHIFT 0
+#define DENREG_LOCK_MASK BIT(2)
+#define DENREG_LOCK_SHIFT 2
+#define GPLOCK_LOCK_MASK BIT(4)
+#define GPLOCK_LOCK_SHIFT 4
+
+/* BSEC_OTP_STATUS Register */
+#define BSEC_MODE_STATUS_MASK GENMASK(2, 0)
+#define BSEC_MODE_SECURE_MASK BIT(0)
+#define BSEC_MODE_FULLDBG_MASK BIT(1)
+#define BSEC_MODE_INVALID_MASK BIT(2)
+#define BSEC_MODE_BUSY_MASK BIT(3)
+#define BSEC_MODE_PROGFAIL_MASK BIT(4)
+#define BSEC_MODE_PWR_MASK BIT(5)
+#define BSEC_MODE_BIST1_LOCK_MASK BIT(6)
+#define BSEC_MODE_BIST2_LOCK_MASK BIT(7)
+
+/* BSEC_DENABLE Register */
+#define BSEC_HDPEN BIT(4)
+#define BSEC_SPIDEN BIT(5)
+#define BSEC_SPINDEN BIT(6)
+#define BSEC_DBGSWGEN BIT(10)
+#define BSEC_DEN_ALL_MSK GENMASK(10, 0)
+
+/* BSEC_FENABLE Register */
+#define BSEC_FEN_ALL_MSK GENMASK(14, 0)
+
+/* BSEC_IPVR Register */
+#define BSEC_IPVR_MSK GENMASK(7, 0)
+
+#endif /* BSEC2_REG_H */
diff --git a/include/drivers/st/etzpc.h b/include/drivers/st/etzpc.h
new file mode 100644
index 0000000..4cd2b4e
--- /dev/null
+++ b/include/drivers/st/etzpc.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DRIVERS_ST_ETZPC_H
+#define DRIVERS_ST_ETZPC_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/* Define security level for each peripheral (DECPROT) */
+enum etzpc_decprot_attributes {
+ ETZPC_DECPROT_S_RW = 0,
+ ETZPC_DECPROT_NS_R_S_W = 1,
+ ETZPC_DECPROT_MCU_ISOLATION = 2,
+ ETZPC_DECPROT_NS_RW = 3,
+ ETZPC_DECPROT_MAX = 4,
+};
+
+void etzpc_configure_decprot(uint32_t decprot_id,
+ enum etzpc_decprot_attributes decprot_attr);
+enum etzpc_decprot_attributes etzpc_get_decprot(uint32_t decprot_id);
+void etzpc_lock_decprot(uint32_t decprot_id);
+
+void etzpc_configure_tzma(uint32_t tzma_id, uint16_t tzma_value);
+uint16_t etzpc_get_tzma(uint32_t tzma_id);
+void etzpc_lock_tzma(uint32_t tzma_id);
+bool etzpc_get_lock_tzma(uint32_t tzma_id);
+
+uint8_t etzpc_get_num_per_sec(void);
+uint8_t etzpc_get_revision(void);
+uintptr_t etzpc_get_base_address(void);
+
+int etzpc_init(void);
+
+#endif /* DRIVERS_ST_ETZPC_H */
diff --git a/include/drivers/st/io_mmc.h b/include/drivers/st/io_mmc.h
new file mode 100644
index 0000000..6179e89
--- /dev/null
+++ b/include/drivers/st/io_mmc.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IO_MMC_H
+#define IO_MMC_H
+
+#include <drivers/io/io_driver.h>
+
+struct io_mmc_dev_spec {
+ bool use_boot_part;
+};
+
+int register_io_dev_mmc(const io_dev_connector_t **dev_con);
+
+#endif /* IO_MMC_H */
diff --git a/include/drivers/st/regulator.h b/include/drivers/st/regulator.h
new file mode 100644
index 0000000..bf583e2
--- /dev/null
+++ b/include/drivers/st/regulator.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef REGULATOR_H
+#define REGULATOR_H
+
+#include <platform_def.h>
+
+#ifndef PLAT_NB_RDEVS
+#error "Missing PLAT_NB_RDEVS"
+#endif
+
+/*
+ * Consumer interface
+ */
+
+/* regulator-always-on : regulator should never be disabled */
+#define REGUL_ALWAYS_ON BIT(0)
+/*
+ * regulator-boot-on:
+ * It's expected that this regulator was left on by the bootloader.
+ * The core shouldn't prevent it from being turned off later.
+ * The regulator is needed to exit from suspend so it is turned on during suspend entry.
+ */
+#define REGUL_BOOT_ON BIT(1)
+/* regulator-over-current-protection: Enable over current protection. */
+#define REGUL_OCP BIT(2)
+/* regulator-active-discharge: enable active discharge. */
+#define REGUL_ACTIVE_DISCHARGE BIT(3)
+/* regulator-pull-down: Enable pull down resistor when the regulator is disabled. */
+#define REGUL_PULL_DOWN BIT(4)
+/*
+ * st,mask-reset: set mask reset for the regulator, meaning that the regulator
+ * setting is maintained during pmic reset.
+ */
+#define REGUL_MASK_RESET BIT(5)
+/* st,regulator-sink-source: set the regulator in sink source mode */
+#define REGUL_SINK_SOURCE BIT(6)
+/* st,regulator-bypass: set the regulator in bypass mode */
+#define REGUL_ENABLE_BYPASS BIT(7)
+
+struct rdev *regulator_get_by_name(const char *node_name);
+
+struct rdev *regulator_get_by_supply_name(const void *fdt, int node, const char *name);
+
+int regulator_enable(struct rdev *rdev);
+int regulator_disable(struct rdev *rdev);
+int regulator_is_enabled(const struct rdev *rdev);
+
+int regulator_set_voltage(struct rdev *rdev, uint16_t volt);
+int regulator_set_min_voltage(struct rdev *rdev);
+int regulator_get_voltage(const struct rdev *rdev);
+
+int regulator_list_voltages(const struct rdev *rdev, const uint16_t **levels, size_t *count);
+void regulator_get_range(const struct rdev *rdev, uint16_t *min_mv, uint16_t *max_mv);
+int regulator_set_flag(struct rdev *rdev, uint16_t flag);
+
+/*
+ * Driver Interface
+ */
+
+/* set_state() arguments */
+#define STATE_DISABLE false
+#define STATE_ENABLE true
+
+struct regul_description {
+ const char *node_name;
+ const struct regul_ops *ops;
+ const void *driver_data;
+ const char *supply_name;
+ const uint32_t enable_ramp_delay;
+};
+
+struct regul_ops {
+ int (*set_state)(const struct regul_description *desc, bool state);
+ int (*get_state)(const struct regul_description *desc);
+ int (*set_voltage)(const struct regul_description *desc, uint16_t mv);
+ int (*get_voltage)(const struct regul_description *desc);
+ int (*list_voltages)(const struct regul_description *desc,
+ const uint16_t **levels, size_t *count);
+ int (*set_flag)(const struct regul_description *desc, uint16_t flag);
+ void (*lock)(const struct regul_description *desc);
+ void (*unlock)(const struct regul_description *desc);
+};
+
+int regulator_register(const struct regul_description *desc, int node);
+
+/*
+ * Internal regulator structure
+ * The structure is internal to the core, and the content should not be used
+ * by a consumer nor a driver.
+ */
+struct rdev {
+ const struct regul_description *desc;
+
+ int32_t phandle;
+
+ uint16_t min_mv;
+ uint16_t max_mv;
+
+ uint16_t flags;
+
+ uint32_t enable_ramp_delay;
+};
+
+#endif /* REGULATOR_H */
diff --git a/include/drivers/st/regulator_fixed.h b/include/drivers/st/regulator_fixed.h
new file mode 100644
index 0000000..b981262
--- /dev/null
+++ b/include/drivers/st/regulator_fixed.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef REGULATOR_FIXED_H
+#define REGULATOR_FIXED_H
+
+int fixed_regulator_register(void);
+
+#endif /* REGULATOR_FIXED_H */
diff --git a/include/drivers/st/stm32_console.h b/include/drivers/st/stm32_console.h
new file mode 100644
index 0000000..8d9187d
--- /dev/null
+++ b/include/drivers/st/stm32_console.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32_CONSOLE_H
+#define STM32_CONSOLE_H
+
+#include <drivers/console.h>
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+/*
+ * Initialize a new STM32 console instance and register it with the console
+ * framework. The |console| pointer must point to storage that will be valid
+ * for the lifetime of the console, such as a global or static local variable.
+ * Its contents will be reinitialized from scratch.
+ */
+int console_stm32_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
+ console_t *console);
+
+#endif /*__ASSEMBLER__*/
+
+#endif /* STM32_CONSOLE_H */
diff --git a/include/drivers/st/stm32_fmc2_nand.h b/include/drivers/st/stm32_fmc2_nand.h
new file mode 100644
index 0000000..81d5b9d
--- /dev/null
+++ b/include/drivers/st/stm32_fmc2_nand.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+ */
+
+#ifndef STM32_FMC2_NAND_H
+#define STM32_FMC2_NAND_H
+
+int stm32_fmc2_init(void);
+
+#endif /* STM32_FMC2_NAND_H */
diff --git a/include/drivers/st/stm32_gpio.h b/include/drivers/st/stm32_gpio.h
new file mode 100644
index 0000000..eeef9da
--- /dev/null
+++ b/include/drivers/st/stm32_gpio.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32_GPIO_H
+#define STM32_GPIO_H
+
+#include <lib/utils_def.h>
+
+#define GPIO_MODE_OFFSET U(0x00)
+#define GPIO_TYPE_OFFSET U(0x04)
+#define GPIO_SPEED_OFFSET U(0x08)
+#define GPIO_PUPD_OFFSET U(0x0C)
+#define GPIO_OD_OFFSET U(0x14)
+#define GPIO_BSRR_OFFSET U(0x18)
+#define GPIO_AFRL_OFFSET U(0x20)
+#define GPIO_AFRH_OFFSET U(0x24)
+#define GPIO_SECR_OFFSET U(0x30)
+
+#define GPIO_ALT_LOWER_LIMIT U(0x08)
+
+#define GPIO_PIN_(_x) U(_x)
+#define GPIO_PIN_MAX GPIO_PIN_(15)
+
+#define GPIO_ALTERNATE_(_x) U(_x)
+#define GPIO_ALTERNATE_MASK U(0x0F)
+
+#define GPIO_MODE_INPUT U(0x00)
+#define GPIO_MODE_OUTPUT U(0x01)
+#define GPIO_MODE_ALTERNATE U(0x02)
+#define GPIO_MODE_ANALOG U(0x03)
+#define GPIO_MODE_MASK U(0x03)
+
+#define GPIO_TYPE_PUSH_PULL U(0x00)
+#define GPIO_TYPE_OPEN_DRAIN U(0x01)
+#define GPIO_TYPE_MASK U(0x01)
+
+#define GPIO_SPEED_LOW U(0x00)
+#define GPIO_SPEED_MEDIUM U(0x01)
+#define GPIO_SPEED_HIGH U(0x02)
+#define GPIO_SPEED_VERY_HIGH U(0x03)
+#define GPIO_SPEED_MASK U(0x03)
+
+#define GPIO_NO_PULL U(0x00)
+#define GPIO_PULL_UP U(0x01)
+#define GPIO_PULL_DOWN U(0x02)
+#define GPIO_PULL_MASK U(0x03)
+
+#define GPIO_OD_OUTPUT_LOW U(0x00)
+#define GPIO_OD_OUTPUT_HIGH U(0x01)
+#define GPIO_OD_MASK U(0x01)
+
+#ifndef __ASSEMBLER__
+#include <stdint.h>
+
+int dt_set_pinctrl_config(int node);
+void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure);
+void set_gpio_reset_cfg(uint32_t bank, uint32_t pin);
+#endif /*__ASSEMBLER__*/
+
+#endif /* STM32_GPIO_H */
diff --git a/include/drivers/st/stm32_hash.h b/include/drivers/st/stm32_hash.h
new file mode 100644
index 0000000..bebb4af
--- /dev/null
+++ b/include/drivers/st/stm32_hash.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32_HASH_H
+#define STM32_HASH_H
+
+#include <stdint.h>
+
+enum stm32_hash_algo_mode {
+#if STM32_HASH_VER == 2
+ HASH_MD5SUM,
+#endif
+ HASH_SHA1,
+ HASH_SHA224,
+ HASH_SHA256,
+#if STM32_HASH_VER == 4
+ HASH_SHA384,
+ HASH_SHA512,
+#endif
+};
+
+int stm32_hash_update(const uint8_t *buffer, size_t length);
+int stm32_hash_final(uint8_t *digest);
+int stm32_hash_final_update(const uint8_t *buffer, uint32_t buf_length,
+ uint8_t *digest);
+void stm32_hash_init(enum stm32_hash_algo_mode mode);
+int stm32_hash_register(void);
+
+#endif /* STM32_HASH_H */
diff --git a/include/drivers/st/stm32_i2c.h b/include/drivers/st/stm32_i2c.h
new file mode 100644
index 0000000..170d4cf
--- /dev/null
+++ b/include/drivers/st/stm32_i2c.h
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32_I2C_H
+#define STM32_I2C_H
+
+#include <stdint.h>
+
+#include <lib/utils_def.h>
+
+/* Bit definition for I2C_CR1 register */
+#define I2C_CR1_PE BIT(0)
+#define I2C_CR1_TXIE BIT(1)
+#define I2C_CR1_RXIE BIT(2)
+#define I2C_CR1_ADDRIE BIT(3)
+#define I2C_CR1_NACKIE BIT(4)
+#define I2C_CR1_STOPIE BIT(5)
+#define I2C_CR1_TCIE BIT(6)
+#define I2C_CR1_ERRIE BIT(7)
+#define I2C_CR1_DNF GENMASK(11, 8)
+#define I2C_CR1_ANFOFF BIT(12)
+#define I2C_CR1_SWRST BIT(13)
+#define I2C_CR1_TXDMAEN BIT(14)
+#define I2C_CR1_RXDMAEN BIT(15)
+#define I2C_CR1_SBC BIT(16)
+#define I2C_CR1_NOSTRETCH BIT(17)
+#define I2C_CR1_WUPEN BIT(18)
+#define I2C_CR1_GCEN BIT(19)
+#define I2C_CR1_SMBHEN BIT(22)
+#define I2C_CR1_SMBDEN BIT(21)
+#define I2C_CR1_ALERTEN BIT(22)
+#define I2C_CR1_PECEN BIT(23)
+
+/* Bit definition for I2C_CR2 register */
+#define I2C_CR2_SADD GENMASK(9, 0)
+#define I2C_CR2_RD_WRN BIT(10)
+#define I2C_CR2_RD_WRN_OFFSET 10U
+#define I2C_CR2_ADD10 BIT(11)
+#define I2C_CR2_HEAD10R BIT(12)
+#define I2C_CR2_START BIT(13)
+#define I2C_CR2_STOP BIT(14)
+#define I2C_CR2_NACK BIT(15)
+#define I2C_CR2_NBYTES GENMASK(23, 16)
+#define I2C_CR2_NBYTES_OFFSET 16U
+#define I2C_CR2_RELOAD BIT(24)
+#define I2C_CR2_AUTOEND BIT(25)
+#define I2C_CR2_PECBYTE BIT(26)
+
+/* Bit definition for I2C_OAR1 register */
+#define I2C_OAR1_OA1 GENMASK(9, 0)
+#define I2C_OAR1_OA1MODE BIT(10)
+#define I2C_OAR1_OA1EN BIT(15)
+
+/* Bit definition for I2C_OAR2 register */
+#define I2C_OAR2_OA2 GENMASK(7, 1)
+#define I2C_OAR2_OA2MSK GENMASK(10, 8)
+#define I2C_OAR2_OA2NOMASK 0
+#define I2C_OAR2_OA2MASK01 BIT(8)
+#define I2C_OAR2_OA2MASK02 BIT(9)
+#define I2C_OAR2_OA2MASK03 GENMASK(9, 8)
+#define I2C_OAR2_OA2MASK04 BIT(10)
+#define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10))
+#define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10))
+#define I2C_OAR2_OA2MASK07 GENMASK(10, 8)
+#define I2C_OAR2_OA2EN BIT(15)
+
+/* Bit definition for I2C_TIMINGR register */
+#define I2C_TIMINGR_SCLL GENMASK(7, 0)
+#define I2C_TIMINGR_SCLH GENMASK(15, 8)
+#define I2C_TIMINGR_SDADEL GENMASK(19, 16)
+#define I2C_TIMINGR_SCLDEL GENMASK(23, 20)
+#define I2C_TIMINGR_PRESC GENMASK(31, 28)
+
+/* Bit definition for I2C_TIMEOUTR register */
+#define I2C_TIMEOUTR_TIMEOUTA GENMASK(11, 0)
+#define I2C_TIMEOUTR_TIDLE BIT(12)
+#define I2C_TIMEOUTR_TIMOUTEN BIT(15)
+#define I2C_TIMEOUTR_TIMEOUTB GENMASK(27, 16)
+#define I2C_TIMEOUTR_TEXTEN BIT(31)
+
+/* Bit definition for I2C_ISR register */
+#define I2C_ISR_TXE BIT(0)
+#define I2C_ISR_TXIS BIT(1)
+#define I2C_ISR_RXNE BIT(2)
+#define I2C_ISR_ADDR BIT(3)
+#define I2C_ISR_NACKF BIT(4)
+#define I2C_ISR_STOPF BIT(5)
+#define I2C_ISR_TC BIT(6)
+#define I2C_ISR_TCR BIT(7)
+#define I2C_ISR_BERR BIT(8)
+#define I2C_ISR_ARLO BIT(9)
+#define I2C_ISR_OVR BIT(10)
+#define I2C_ISR_PECERR BIT(11)
+#define I2C_ISR_TIMEOUT BIT(12)
+#define I2C_ISR_ALERT BIT(13)
+#define I2C_ISR_BUSY BIT(15)
+#define I2C_ISR_DIR BIT(16)
+#define I2C_ISR_ADDCODE GENMASK(23, 17)
+
+/* Bit definition for I2C_ICR register */
+#define I2C_ICR_ADDRCF BIT(3)
+#define I2C_ICR_NACKCF BIT(4)
+#define I2C_ICR_STOPCF BIT(5)
+#define I2C_ICR_BERRCF BIT(8)
+#define I2C_ICR_ARLOCF BIT(9)
+#define I2C_ICR_OVRCF BIT(10)
+#define I2C_ICR_PECCF BIT(11)
+#define I2C_ICR_TIMOUTCF BIT(12)
+#define I2C_ICR_ALERTCF BIT(13)
+
+enum i2c_speed_e {
+ I2C_SPEED_STANDARD, /* 100 kHz */
+ I2C_SPEED_FAST, /* 400 kHz */
+ I2C_SPEED_FAST_PLUS, /* 1 MHz */
+};
+
+#define STANDARD_RATE 100000
+#define FAST_RATE 400000
+#define FAST_PLUS_RATE 1000000
+
+struct stm32_i2c_init_s {
+ uint32_t own_address1; /*
+ * Specifies the first device own
+ * address. This parameter can be a
+ * 7-bit or 10-bit address.
+ */
+
+ uint32_t addressing_mode; /*
+ * Specifies if 7-bit or 10-bit
+ * addressing mode is selected.
+ * This parameter can be a value of
+ * @ref I2C_ADDRESSING_MODE.
+ */
+
+ uint32_t dual_address_mode; /*
+ * Specifies if dual addressing mode is
+ * selected.
+ * This parameter can be a value of @ref
+ * I2C_DUAL_ADDRESSING_MODE.
+ */
+
+ uint32_t own_address2; /*
+ * Specifies the second device own
+ * address if dual addressing mode is
+ * selected. This parameter can be a
+ * 7-bit address.
+ */
+
+ uint32_t own_address2_masks; /*
+ * Specifies the acknowledge mask
+ * address second device own address
+ * if dual addressing mode is selected
+ * This parameter can be a value of @ref
+ * I2C_OWN_ADDRESS2_MASKS.
+ */
+
+ uint32_t general_call_mode; /*
+ * Specifies if general call mode is
+ * selected.
+ * This parameter can be a value of @ref
+ * I2C_GENERAL_CALL_ADDRESSING_MODE.
+ */
+
+ uint32_t no_stretch_mode; /*
+ * Specifies if nostretch mode is
+ * selected.
+ * This parameter can be a value of @ref
+ * I2C_NOSTRETCH_MODE.
+ */
+
+ uint32_t rise_time; /*
+ * Specifies the SCL clock pin rising
+ * time in nanoseconds.
+ */
+
+ uint32_t fall_time; /*
+ * Specifies the SCL clock pin falling
+ * time in nanoseconds.
+ */
+
+ enum i2c_speed_e speed_mode; /*
+ * Specifies the I2C clock source
+ * frequency mode.
+ * This parameter can be a value of @ref
+ * i2c_speed_mode_e.
+ */
+
+ int analog_filter; /*
+ * Specifies if the I2C analog noise
+ * filter is selected.
+ * This parameter can be 0 (filter
+ * off), all other values mean filter
+ * on.
+ */
+
+ uint8_t digital_filter_coef; /*
+ * Specifies the I2C digital noise
+ * filter coefficient.
+ * This parameter can be a value
+ * between 0 and
+ * STM32_I2C_DIGITAL_FILTER_MAX.
+ */
+};
+
+enum i2c_state_e {
+ I2C_STATE_RESET = 0x00U, /* Not yet initialized */
+ I2C_STATE_READY = 0x20U, /* Ready for use */
+ I2C_STATE_BUSY = 0x24U, /* Internal process ongoing */
+ I2C_STATE_BUSY_TX = 0x21U, /* Data Transmission ongoing */
+ I2C_STATE_BUSY_RX = 0x22U, /* Data Reception ongoing */
+};
+
+enum i2c_mode_e {
+ I2C_MODE_NONE = 0x00U, /* No active communication */
+ I2C_MODE_MASTER = 0x10U, /* Communication in Master Mode */
+ I2C_MODE_SLAVE = 0x20U, /* Communication in Slave Mode */
+ I2C_MODE_MEM = 0x40U /* Communication in Memory Mode */
+
+};
+
+#define I2C_ERROR_NONE 0x00000000U /* No error */
+#define I2C_ERROR_BERR 0x00000001U /* BERR error */
+#define I2C_ERROR_ARLO 0x00000002U /* ARLO error */
+#define I2C_ERROR_AF 0x00000004U /* ACKF error */
+#define I2C_ERROR_OVR 0x00000008U /* OVR error */
+#define I2C_ERROR_DMA 0x00000010U /* DMA transfer error */
+#define I2C_ERROR_TIMEOUT 0x00000020U /* Timeout error */
+#define I2C_ERROR_SIZE 0x00000040U /* Size Management error */
+
+struct i2c_handle_s {
+ uint32_t i2c_base_addr; /* Registers base address */
+ unsigned int dt_status; /* DT nsec/sec status */
+ unsigned int clock; /* Clock reference */
+ uint8_t lock; /* Locking object */
+ enum i2c_state_e i2c_state; /* Communication state */
+ enum i2c_mode_e i2c_mode; /* Communication mode */
+ uint32_t i2c_err; /* Error code */
+};
+
+#define I2C_ADDRESSINGMODE_7BIT 0x00000001U
+#define I2C_ADDRESSINGMODE_10BIT 0x00000002U
+
+#define I2C_DUALADDRESS_DISABLE 0x00000000U
+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
+
+#define I2C_GENERALCALL_DISABLE 0x00000000U
+#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
+
+#define I2C_NOSTRETCH_DISABLE 0x00000000U
+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
+
+#define I2C_MEMADD_SIZE_8BIT 0x00000001U
+#define I2C_MEMADD_SIZE_16BIT 0x00000002U
+
+#define I2C_RELOAD_MODE I2C_CR2_RELOAD
+#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
+#define I2C_SOFTEND_MODE 0x00000000U
+
+#define I2C_NO_STARTSTOP 0x00000000U
+#define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP)
+#define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \
+ I2C_CR2_RD_WRN)
+#define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START)
+
+#define I2C_FLAG_TXE I2C_ISR_TXE
+#define I2C_FLAG_TXIS I2C_ISR_TXIS
+#define I2C_FLAG_RXNE I2C_ISR_RXNE
+#define I2C_FLAG_ADDR I2C_ISR_ADDR
+#define I2C_FLAG_AF I2C_ISR_NACKF
+#define I2C_FLAG_STOPF I2C_ISR_STOPF
+#define I2C_FLAG_TC I2C_ISR_TC
+#define I2C_FLAG_TCR I2C_ISR_TCR
+#define I2C_FLAG_BERR I2C_ISR_BERR
+#define I2C_FLAG_ARLO I2C_ISR_ARLO
+#define I2C_FLAG_OVR I2C_ISR_OVR
+#define I2C_FLAG_PECERR I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT I2C_ISR_ALERT
+#define I2C_FLAG_BUSY I2C_ISR_BUSY
+#define I2C_FLAG_DIR I2C_ISR_DIR
+
+#define I2C_RESET_CR2 (I2C_CR2_SADD | I2C_CR2_HEAD10R | \
+ I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
+ I2C_CR2_RD_WRN)
+
+#define I2C_TIMEOUT_BUSY_MS 25U
+
+#define I2C_ANALOGFILTER_ENABLE 0x00000000U
+#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
+
+/* STM32 specific defines */
+#define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */
+#define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */
+#define STM32_I2C_SPEED_DEFAULT I2C_SPEED_STANDARD
+#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
+#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
+#define STM32_I2C_DIGITAL_FILTER_MAX 16
+
+int stm32_i2c_get_setup_from_fdt(void *fdt, int node,
+ struct stm32_i2c_init_s *init);
+int stm32_i2c_init(struct i2c_handle_s *hi2c,
+ struct stm32_i2c_init_s *init_data);
+int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
+ uint16_t mem_addr, uint16_t mem_add_size,
+ uint8_t *p_data, uint16_t size, uint32_t timeout_ms);
+int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
+ uint16_t mem_addr, uint16_t mem_add_size,
+ uint8_t *p_data, uint16_t size, uint32_t timeout_ms);
+int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint16_t dev_addr,
+ uint8_t *p_data, uint16_t size,
+ uint32_t timeout_ms);
+int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint16_t dev_addr,
+ uint8_t *p_data, uint16_t size,
+ uint32_t timeout_ms);
+bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint16_t dev_addr,
+ uint32_t trials, uint32_t timeout_ms);
+
+#endif /* STM32_I2C_H */
diff --git a/include/drivers/st/stm32_iwdg.h b/include/drivers/st/stm32_iwdg.h
new file mode 100644
index 0000000..bad2524
--- /dev/null
+++ b/include/drivers/st/stm32_iwdg.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32_IWDG_H
+#define STM32_IWDG_H
+
+#include <stdint.h>
+
+#define IWDG_HW_ENABLED BIT(0)
+#define IWDG_DISABLE_ON_STOP BIT(1)
+#define IWDG_DISABLE_ON_STANDBY BIT(2)
+
+int stm32_iwdg_init(void);
+void stm32_iwdg_refresh(void);
+
+#endif /* STM32_IWDG_H */
diff --git a/include/drivers/st/stm32_pka.h b/include/drivers/st/stm32_pka.h
new file mode 100644
index 0000000..ad4690a
--- /dev/null
+++ b/include/drivers/st/stm32_pka.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32_PKA_H
+#define STM32_PKA_H
+
+#include <stdint.h>
+
+#if !PKA_USE_NIST_P256 && !PKA_USE_BRAINPOOL_P256R1 && !PKA_USE_BRAINPOOL_P256T1 && \
+ !PKA_USE_NIST_P521
+#error "At least one ECDSA curve needs to be selected"
+#endif
+
+enum stm32_pka_ecdsa_curve_id {
+#if PKA_USE_NIST_P256
+ PKA_NIST_P256,
+#endif
+#if PKA_USE_BRAINPOOL_P256R1
+ PKA_BRAINPOOL_P256R1,
+#endif
+#if PKA_USE_BRAINPOOL_P256T1
+ PKA_BRAINPOOL_P256T1,
+#endif
+#if PKA_USE_NIST_P521
+ PKA_NIST_P521,
+#endif
+};
+
+struct stm32_pka_platdata {
+ uintptr_t base;
+ unsigned long clock_id;
+ unsigned int reset_id;
+};
+
+int stm32_pka_init(void);
+int stm32_pka_ecdsa_verif(void *hash, unsigned int hash_size,
+ void *sig_r_ptr, unsigned int sig_r_size,
+ void *sig_s_ptr, unsigned int sig_s_size,
+ void *pk_x_ptr, unsigned int pk_x_size,
+ void *pk_y_ptr, unsigned int pk_y_size,
+ enum stm32_pka_ecdsa_curve_id cid);
+
+#endif /* STM32_PKA_H */
diff --git a/include/drivers/st/stm32_qspi.h b/include/drivers/st/stm32_qspi.h
new file mode 100644
index 0000000..f47fca4
--- /dev/null
+++ b/include/drivers/st/stm32_qspi.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+ */
+
+#ifndef STM32_QSPI_H
+#define STM32_QSPI_H
+
+int stm32_qspi_init(void);
+
+#endif /* STM32_QSPI_H */
diff --git a/include/drivers/st/stm32_rng.h b/include/drivers/st/stm32_rng.h
new file mode 100644
index 0000000..6ac064d
--- /dev/null
+++ b/include/drivers/st/stm32_rng.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32_RNG_H
+#define STM32_RNG_H
+
+#include <stdint.h>
+
+int stm32_rng_read(uint8_t *out, uint32_t size);
+int stm32_rng_init(void);
+
+#endif /* STM32_RNG_H */
diff --git a/include/drivers/st/stm32_saes.h b/include/drivers/st/stm32_saes.h
new file mode 100644
index 0000000..0a50438
--- /dev/null
+++ b/include/drivers/st/stm32_saes.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32_SAES_H
+#define STM32_SAES_H
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#define DT_SAES_COMPAT "st,stm32-saes"
+
+struct stm32_saes_platdata {
+ uintptr_t base;
+ unsigned long clock_id;
+ unsigned int reset_id;
+};
+
+enum stm32_saes_chaining_mode {
+ STM32_SAES_MODE_ECB,
+ STM32_SAES_MODE_CBC,
+ STM32_SAES_MODE_CTR,
+ STM32_SAES_MODE_GCM,
+ STM32_SAES_MODE_CCM, /* Not use in TF-A */
+};
+
+enum stm32_saes_key_selection {
+ STM32_SAES_KEY_SOFT,
+ STM32_SAES_KEY_DHU, /* Derived HW unique key */
+ STM32_SAES_KEY_BH, /* Boot HW key */
+ STM32_SAES_KEY_BHU_XOR_BH, /* XOR of DHUK and BHK */
+ STM32_SAES_KEY_WRAPPED
+};
+
+struct stm32_saes_context {
+ uintptr_t base;
+ uint32_t cr;
+ uint32_t assoc_len;
+ uint32_t load_len;
+ uint32_t key[8]; /* In HW byte order */
+ uint32_t iv[4]; /* In HW byte order */
+};
+
+int stm32_saes_driver_init(void);
+
+int stm32_saes_init(struct stm32_saes_context *ctx, bool is_decrypt,
+ enum stm32_saes_chaining_mode ch_mode, enum stm32_saes_key_selection key_select,
+ const void *key, size_t key_len, const void *iv, size_t iv_len);
+int stm32_saes_update(struct stm32_saes_context *ctx, bool last_block,
+ uint8_t *data_in, uint8_t *data_out, size_t data_len);
+int stm32_saes_update_assodata(struct stm32_saes_context *ctx, bool last_block,
+ uint8_t *data, size_t data_len);
+int stm32_saes_update_load(struct stm32_saes_context *ctx, bool last_block,
+ uint8_t *data_in, uint8_t *data_out, size_t data_len);
+int stm32_saes_final(struct stm32_saes_context *ctx, uint8_t *tag, size_t tag_len);
+#endif
diff --git a/include/drivers/st/stm32_sdmmc2.h b/include/drivers/st/stm32_sdmmc2.h
new file mode 100644
index 0000000..c83f625
--- /dev/null
+++ b/include/drivers/st/stm32_sdmmc2.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32_SDMMC2_H
+#define STM32_SDMMC2_H
+
+#include <stdbool.h>
+
+#include <drivers/mmc.h>
+#include <drivers/st/regulator.h>
+
+struct stm32_sdmmc2_params {
+ uintptr_t reg_base;
+ unsigned int clk_rate;
+ unsigned int bus_width;
+ unsigned int flags;
+ struct mmc_device_info *device_info;
+ unsigned int pin_ckin;
+ unsigned int negedge;
+ unsigned int dirpol;
+ unsigned int clock_id;
+ unsigned int reset_id;
+ unsigned int max_freq;
+ bool use_dma;
+ struct rdev *vmmc_regu;
+};
+
+unsigned long long stm32_sdmmc2_mmc_get_device_size(void);
+int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params);
+bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory);
+
+#endif /* STM32_SDMMC2_H */
diff --git a/include/drivers/st/stm32_uart.h b/include/drivers/st/stm32_uart.h
new file mode 100644
index 0000000..866e158
--- /dev/null
+++ b/include/drivers/st/stm32_uart.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32_UART_H
+#define STM32_UART_H
+
+/* UART word length */
+#define STM32_UART_WORDLENGTH_7B USART_CR1_M1
+#define STM32_UART_WORDLENGTH_8B 0x00000000U
+#define STM32_UART_WORDLENGTH_9B USART_CR1_M0
+
+/* UART number of stop bits */
+#define STM32_UART_STOPBITS_0_5 USART_CR2_STOP_0
+#define STM32_UART_STOPBITS_1 0x00000000U
+#define STM32_UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
+#define STM32_UART_STOPBITS_2 USART_CR2_STOP_1
+
+/* UART parity */
+#define STM32_UART_PARITY_NONE 0x00000000U
+#define STM32_UART_PARITY_EVEN USART_CR1_PCE
+#define STM32_UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
+
+/* UART transfer mode */
+#define STM32_UART_MODE_RX USART_CR1_RE
+#define STM32_UART_MODE_TX USART_CR1_TE
+#define STM32_UART_MODE_TX_RX (USART_CR1_TE | USART_CR1_RE)
+
+/* UART hardware flow control */
+#define STM32_UART_HWCONTROL_NONE 0x00000000U
+#define STM32_UART_HWCONTROL_RTS USART_CR3_RTSE
+#define STM32_UART_HWCONTROL_CTS USART_CR3_CTSE
+#define STM32_UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
+
+/* UART prescaler */
+#define STM32_UART_PRESCALER_DIV1 0x00000000U
+#define STM32_UART_PRESCALER_DIV2 0x00000001U
+#define STM32_UART_PRESCALER_DIV4 0x00000002U
+#define STM32_UART_PRESCALER_DIV6 0x00000003U
+#define STM32_UART_PRESCALER_DIV8 0x00000004U
+#define STM32_UART_PRESCALER_DIV10 0x00000005U
+#define STM32_UART_PRESCALER_DIV12 0x00000006U
+#define STM32_UART_PRESCALER_DIV16 0x00000007U
+#define STM32_UART_PRESCALER_DIV32 0x00000008U
+#define STM32_UART_PRESCALER_DIV64 0x00000009U
+#define STM32_UART_PRESCALER_DIV128 0x0000000AU
+#define STM32_UART_PRESCALER_DIV256 0x0000000BU
+#define STM32_UART_PRESCALER_NB 0x0000000CU
+
+/* UART fifo mode */
+#define STM32_UART_FIFOMODE_EN USART_CR1_FIFOEN
+#define STM32_UART_FIFOMODE_DIS 0x00000000U
+
+/* UART TXFIFO threshold level */
+#define STM32_UART_TXFIFO_THRESHOLD_1EIGHTHFULL 0x00000000U
+#define STM32_UART_TXFIFO_THRESHOLD_1QUARTERFUL USART_CR3_TXFTCFG_0
+#define STM32_UART_TXFIFO_THRESHOLD_HALFFULL USART_CR3_TXFTCFG_1
+#define STM32_UART_TXFIFO_THRESHOLD_3QUARTERSFULL (USART_CR3_TXFTCFG_0 | USART_CR3_TXFTCFG_1)
+#define STM32_UART_TXFIFO_THRESHOLD_7EIGHTHFULL USART_CR3_TXFTCFG_2
+#define STM32_UART_TXFIFO_THRESHOLD_EMPTY (USART_CR3_TXFTCFG_2 | USART_CR3_TXFTCFG_0)
+
+/* UART RXFIFO threshold level */
+#define STM32_UART_RXFIFO_THRESHOLD_1EIGHTHFULL 0x00000000U
+#define STM32_UART_RXFIFO_THRESHOLD_1QUARTERFULL USART_CR3_RXFTCFG_0
+#define STM32_UART_RXFIFO_THRESHOLD_HALFFULL USART_CR3_RXFTCFG_1
+#define STM32_UART_RXFIFO_THRESHOLD_3QUARTERSFULL (USART_CR3_RXFTCFG_0 | USART_CR3_RXFTCFG_1)
+#define STM32_UART_RXFIFO_THRESHOLD_7EIGHTHFULL USART_CR3_RXFTCFG_2
+#define STM32_UART_RXFIFO_THRESHOLD_FULL (USART_CR3_RXFTCFG_2 | USART_CR3_RXFTCFG_0)
+
+struct stm32_uart_init_s {
+ uint32_t baud_rate; /*
+ * Configures the UART communication
+ * baud rate.
+ */
+
+ uint32_t word_length; /*
+ * Specifies the number of data bits
+ * transmitted or received in a frame.
+ * This parameter can be a value of
+ * @ref STM32_UART_WORDLENGTH_*.
+ */
+
+ uint32_t stop_bits; /*
+ * Specifies the number of stop bits
+ * transmitted. This parameter can be
+ * a value of @ref STM32_UART_STOPBITS_*.
+ */
+
+ uint32_t parity; /*
+ * Specifies the parity mode.
+ * This parameter can be a value of
+ * @ref STM32_UART_PARITY_*.
+ */
+
+ uint32_t mode; /*
+ * Specifies whether the receive or
+ * transmit mode is enabled or
+ * disabled. This parameter can be a
+ * value of @ref @ref STM32_UART_MODE_*.
+ */
+
+ uint32_t hw_flow_control; /*
+ * Specifies whether the hardware flow
+ * control mode is enabled or
+ * disabled. This parameter can be a
+ * value of @ref STM32_UARTHWCONTROL_*.
+ */
+
+ uint32_t one_bit_sampling; /*
+ * Specifies whether a single sample
+ * or three samples' majority vote is
+ * selected. This parameter can be 0
+ * or USART_CR3_ONEBIT.
+ */
+
+ uint32_t prescaler; /*
+ * Specifies the prescaler value used
+ * to divide the UART clock source.
+ * This parameter can be a value of
+ * @ref STM32_UART_PRESCALER_*.
+ */
+
+ uint32_t fifo_mode; /*
+ * Specifies if the FIFO mode will be
+ * used. This parameter can be a value
+ * of @ref STM32_UART_FIFOMODE_*.
+ */
+
+ uint32_t tx_fifo_threshold; /*
+ * Specifies the TXFIFO threshold
+ * level. This parameter can be a
+ * value of @ref
+ * STM32_UART_TXFIFO_THRESHOLD_*.
+ */
+
+ uint32_t rx_fifo_threshold; /*
+ * Specifies the RXFIFO threshold
+ * level. This parameter can be a
+ * value of @ref
+ * STM32_UART_RXFIFO_THRESHOLD_*.
+ */
+};
+
+struct stm32_uart_handle_s {
+ uint32_t base;
+ uint32_t rdr_mask;
+};
+
+int stm32_uart_init(struct stm32_uart_handle_s *huart,
+ uintptr_t base_addr,
+ const struct stm32_uart_init_s *init);
+void stm32_uart_stop(uintptr_t base_addr);
+int stm32_uart_putc(struct stm32_uart_handle_s *huart, int c);
+int stm32_uart_flush(struct stm32_uart_handle_s *huart);
+int stm32_uart_getc(struct stm32_uart_handle_s *huart);
+
+#endif /* STM32_UART_H */
diff --git a/include/drivers/st/stm32_uart_regs.h b/include/drivers/st/stm32_uart_regs.h
new file mode 100644
index 0000000..14b296c
--- /dev/null
+++ b/include/drivers/st/stm32_uart_regs.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32_UART_REGS_H
+#define STM32_UART_REGS_H
+
+#include <lib/utils_def.h>
+
+#define USART_CR1 U(0x00)
+#define USART_CR2 U(0x04)
+#define USART_CR3 U(0x08)
+#define USART_BRR U(0x0C)
+#define USART_GTPR U(0x10)
+#define USART_RTOR U(0x14)
+#define USART_RQR U(0x18)
+#define USART_ISR U(0x1C)
+#define USART_ICR U(0x20)
+#define USART_RDR U(0x24)
+#define USART_TDR U(0x28)
+#define USART_PRESC U(0x2C)
+
+/* USART_CR1 register fields */
+#define USART_CR1_UE BIT(0)
+#define USART_CR1_UESM BIT(1)
+#define USART_CR1_RE BIT(2)
+#define USART_CR1_TE BIT(3)
+#define USART_CR1_IDLEIE BIT(4)
+#define USART_CR1_RXNEIE BIT(5)
+#define USART_CR1_TCIE BIT(6)
+#define USART_CR1_TXEIE BIT(7)
+#define USART_CR1_PEIE BIT(8)
+#define USART_CR1_PS BIT(9)
+#define USART_CR1_PCE BIT(10)
+#define USART_CR1_WAKE BIT(11)
+#define USART_CR1_M (BIT(28) | BIT(12))
+#define USART_CR1_M0 BIT(12)
+#define USART_CR1_MME BIT(13)
+#define USART_CR1_CMIE BIT(14)
+#define USART_CR1_OVER8 BIT(15)
+#define USART_CR1_DEDT GENMASK(20, 16)
+#define USART_CR1_DEDT_0 BIT(16)
+#define USART_CR1_DEDT_1 BIT(17)
+#define USART_CR1_DEDT_2 BIT(18)
+#define USART_CR1_DEDT_3 BIT(19)
+#define USART_CR1_DEDT_4 BIT(20)
+#define USART_CR1_DEAT GENMASK(25, 21)
+#define USART_CR1_DEAT_0 BIT(21)
+#define USART_CR1_DEAT_1 BIT(22)
+#define USART_CR1_DEAT_2 BIT(23)
+#define USART_CR1_DEAT_3 BIT(24)
+#define USART_CR1_DEAT_4 BIT(25)
+#define USART_CR1_RTOIE BIT(26)
+#define USART_CR1_EOBIE BIT(27)
+#define USART_CR1_M1 BIT(28)
+#define USART_CR1_FIFOEN BIT(29)
+#define USART_CR1_TXFEIE BIT(30)
+#define USART_CR1_RXFFIE BIT(31)
+
+/* USART_CR2 register fields */
+#define USART_CR2_SLVEN BIT(0)
+#define USART_CR2_DIS_NSS BIT(3)
+#define USART_CR2_ADDM7 BIT(4)
+#define USART_CR2_LBDL BIT(5)
+#define USART_CR2_LBDIE BIT(6)
+#define USART_CR2_LBCL BIT(8)
+#define USART_CR2_CPHA BIT(9)
+#define USART_CR2_CPOL BIT(10)
+#define USART_CR2_CLKEN BIT(11)
+#define USART_CR2_STOP GENMASK(13, 12)
+#define USART_CR2_STOP_0 BIT(12)
+#define USART_CR2_STOP_1 BIT(13)
+#define USART_CR2_LINEN BIT(14)
+#define USART_CR2_SWAP BIT(15)
+#define USART_CR2_RXINV BIT(16)
+#define USART_CR2_TXINV BIT(17)
+#define USART_CR2_DATAINV BIT(18)
+#define USART_CR2_MSBFIRST BIT(19)
+#define USART_CR2_ABREN BIT(20)
+#define USART_CR2_ABRMODE GENMASK(22, 21)
+#define USART_CR2_ABRMODE_0 BIT(21)
+#define USART_CR2_ABRMODE_1 BIT(22)
+#define USART_CR2_RTOEN BIT(23)
+#define USART_CR2_ADD GENMASK(31, 24)
+
+/* USART_CR3 register fields */
+#define USART_CR3_EIE BIT(0)
+#define USART_CR3_IREN BIT(1)
+#define USART_CR3_IRLP BIT(2)
+#define USART_CR3_HDSEL BIT(3)
+#define USART_CR3_NACK BIT(4)
+#define USART_CR3_SCEN BIT(5)
+#define USART_CR3_DMAR BIT(6)
+#define USART_CR3_DMAT BIT(7)
+#define USART_CR3_RTSE BIT(8)
+#define USART_CR3_CTSE BIT(9)
+#define USART_CR3_CTSIE BIT(10)
+#define USART_CR3_ONEBIT BIT(11)
+#define USART_CR3_OVRDIS BIT(12)
+#define USART_CR3_DDRE BIT(13)
+#define USART_CR3_DEM BIT(14)
+#define USART_CR3_DEP BIT(15)
+#define USART_CR3_SCARCNT GENMASK(19, 17)
+#define USART_CR3_SCARCNT_0 BIT(17)
+#define USART_CR3_SCARCNT_1 BIT(18)
+#define USART_CR3_SCARCNT_2 BIT(19)
+#define USART_CR3_WUS GENMASK(21, 20)
+#define USART_CR3_WUS_0 BIT(20)
+#define USART_CR3_WUS_1 BIT(21)
+#define USART_CR3_WUFIE BIT(22)
+#define USART_CR3_TXFTIE BIT(23)
+#define USART_CR3_TCBGTIE BIT(24)
+#define USART_CR3_RXFTCFG GENMASK(27, 25)
+#define USART_CR3_RXFTCFG_0 BIT(25)
+#define USART_CR3_RXFTCFG_1 BIT(26)
+#define USART_CR3_RXFTCFG_2 BIT(27)
+#define USART_CR3_RXFTIE BIT(28)
+#define USART_CR3_TXFTCFG GENMASK(31, 29)
+#define USART_CR3_TXFTCFG_0 BIT(29)
+#define USART_CR3_TXFTCFG_1 BIT(30)
+#define USART_CR3_TXFTCFG_2 BIT(31)
+
+/* USART_BRR register fields */
+#define USART_BRR_DIV_FRACTION GENMASK(3, 0)
+#define USART_BRR_DIV_MANTISSA GENMASK(15, 4)
+
+/* USART_GTPR register fields */
+#define USART_GTPR_PSC GENMASK(7, 0)
+#define USART_GTPR_GT GENMASK(15, 8)
+
+/* USART_RTOR register fields */
+#define USART_RTOR_RTO GENMASK(23, 0)
+#define USART_RTOR_BLEN GENMASK(31, 24)
+
+/* USART_RQR register fields */
+#define USART_RQR_ABRRQ BIT(0)
+#define USART_RQR_SBKRQ BIT(1)
+#define USART_RQR_MMRQ BIT(2)
+#define USART_RQR_RXFRQ BIT(3)
+#define USART_RQR_TXFRQ BIT(4)
+
+/* USART_ISR register fields */
+#define USART_ISR_PE BIT(0)
+#define USART_ISR_FE BIT(1)
+#define USART_ISR_NE BIT(2)
+#define USART_ISR_ORE BIT(3)
+#define USART_ISR_IDLE BIT(4)
+#define USART_ISR_RXNE BIT(5)
+#define USART_ISR_TC BIT(6)
+#define USART_ISR_TXE BIT(7)
+#define USART_ISR_LBDF BIT(8)
+#define USART_ISR_CTSIF BIT(9)
+#define USART_ISR_CTS BIT(10)
+#define USART_ISR_RTOF BIT(11)
+#define USART_ISR_EOBF BIT(12)
+#define USART_ISR_UDR BIT(13)
+#define USART_ISR_ABRE BIT(14)
+#define USART_ISR_ABRF BIT(15)
+#define USART_ISR_BUSY BIT(16)
+#define USART_ISR_CMF BIT(17)
+#define USART_ISR_SBKF BIT(18)
+#define USART_ISR_RWU BIT(19)
+#define USART_ISR_WUF BIT(20)
+#define USART_ISR_TEACK BIT(21)
+#define USART_ISR_REACK BIT(22)
+#define USART_ISR_TXFE BIT(23)
+#define USART_ISR_RXFF BIT(24)
+#define USART_ISR_TCBGT BIT(25)
+#define USART_ISR_RXFT BIT(26)
+#define USART_ISR_TXFT BIT(27)
+
+/* USART_ICR register fields */
+#define USART_ICR_PECF BIT(0)
+#define USART_ICR_FECF BIT(1)
+#define USART_ICR_NCF BIT(2)
+#define USART_ICR_ORECF BIT(3)
+#define USART_ICR_IDLECF BIT(4)
+#define USART_ICR_TCCF BIT(6)
+#define USART_ICR_TCBGT BIT(7)
+#define USART_ICR_LBDCF BIT(8)
+#define USART_ICR_CTSCF BIT(9)
+#define USART_ICR_RTOCF BIT(11)
+#define USART_ICR_EOBCF BIT(12)
+#define USART_ICR_UDRCF BIT(13)
+#define USART_ICR_CMCF BIT(17)
+#define USART_ICR_WUCF BIT(20)
+
+/* USART_RDR register fields */
+#define USART_RDR_RDR GENMASK(8, 0)
+
+/* USART_TDR register fields */
+#define USART_TDR_TDR GENMASK(8, 0)
+
+/* USART_PRESC register fields */
+#define USART_PRESC_PRESCALER GENMASK(3, 0)
+
+#endif /* STM32_UART_REGS_H */
diff --git a/include/drivers/st/stm32mp13_rcc.h b/include/drivers/st/stm32mp13_rcc.h
new file mode 100644
index 0000000..1451c9a
--- /dev/null
+++ b/include/drivers/st/stm32mp13_rcc.h
@@ -0,0 +1,1878 @@
+/*
+ * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP13_RCC_H
+#define STM32MP13_RCC_H
+
+#include <lib/utils_def.h>
+
+#define RCC_SECCFGR U(0X0)
+#define RCC_MP_SREQSETR U(0X100)
+#define RCC_MP_SREQCLRR U(0X104)
+#define RCC_MP_APRSTCR U(0X108)
+#define RCC_MP_APRSTSR U(0X10C)
+#define RCC_PWRLPDLYCR U(0X110)
+#define RCC_MP_GRSTCSETR U(0X114)
+#define RCC_BR_RSTSCLRR U(0X118)
+#define RCC_MP_RSTSSETR U(0X11C)
+#define RCC_MP_RSTSCLRR U(0X120)
+#define RCC_MP_IWDGFZSETR U(0X124)
+#define RCC_MP_IWDGFZCLRR U(0X128)
+#define RCC_MP_CIER U(0X200)
+#define RCC_MP_CIFR U(0X204)
+#define RCC_BDCR U(0X400)
+#define RCC_RDLSICR U(0X404)
+#define RCC_OCENSETR U(0X420)
+#define RCC_OCENCLRR U(0X424)
+#define RCC_OCRDYR U(0X428)
+#define RCC_HSICFGR U(0X440)
+#define RCC_CSICFGR U(0X444)
+#define RCC_MCO1CFGR U(0X460)
+#define RCC_MCO2CFGR U(0X464)
+#define RCC_DBGCFGR U(0X468)
+#define RCC_RCK12SELR U(0X480)
+#define RCC_RCK3SELR U(0X484)
+#define RCC_RCK4SELR U(0X488)
+#define RCC_PLL1CR U(0X4A0)
+#define RCC_PLL1CFGR1 U(0X4A4)
+#define RCC_PLL1CFGR2 U(0X4A8)
+#define RCC_PLL1FRACR U(0X4AC)
+#define RCC_PLL1CSGR U(0X4B0)
+#define RCC_PLL2CR U(0X4D0)
+#define RCC_PLL2CFGR1 U(0X4D4)
+#define RCC_PLL2CFGR2 U(0X4D8)
+#define RCC_PLL2FRACR U(0X4DC)
+#define RCC_PLL2CSGR U(0X4E0)
+#define RCC_PLL3CR U(0X500)
+#define RCC_PLL3CFGR1 U(0X504)
+#define RCC_PLL3CFGR2 U(0X508)
+#define RCC_PLL3FRACR U(0X50C)
+#define RCC_PLL3CSGR U(0X510)
+#define RCC_PLL4CR U(0X520)
+#define RCC_PLL4CFGR1 U(0X524)
+#define RCC_PLL4CFGR2 U(0X528)
+#define RCC_PLL4FRACR U(0X52C)
+#define RCC_PLL4CSGR U(0X530)
+#define RCC_MPCKSELR U(0X540)
+#define RCC_ASSCKSELR U(0X544)
+#define RCC_MSSCKSELR U(0X548)
+#define RCC_CPERCKSELR U(0X54C)
+#define RCC_RTCDIVR U(0X560)
+#define RCC_MPCKDIVR U(0X564)
+#define RCC_AXIDIVR U(0X568)
+#define RCC_MLAHBDIVR U(0X56C)
+#define RCC_APB1DIVR U(0X570)
+#define RCC_APB2DIVR U(0X574)
+#define RCC_APB3DIVR U(0X578)
+#define RCC_APB4DIVR U(0X57C)
+#define RCC_APB5DIVR U(0X580)
+#define RCC_APB6DIVR U(0X584)
+#define RCC_TIMG1PRER U(0X5A0)
+#define RCC_TIMG2PRER U(0X5A4)
+#define RCC_TIMG3PRER U(0X5A8)
+#define RCC_DDRITFCR U(0X5C0)
+#define RCC_I2C12CKSELR U(0X600)
+#define RCC_I2C345CKSELR U(0X604)
+#define RCC_SPI2S1CKSELR U(0X608)
+#define RCC_SPI2S23CKSELR U(0X60C)
+#define RCC_SPI45CKSELR U(0X610)
+#define RCC_UART12CKSELR U(0X614)
+#define RCC_UART35CKSELR U(0X618)
+#define RCC_UART4CKSELR U(0X61C)
+#define RCC_UART6CKSELR U(0X620)
+#define RCC_UART78CKSELR U(0X624)
+#define RCC_LPTIM1CKSELR U(0X628)
+#define RCC_LPTIM23CKSELR U(0X62C)
+#define RCC_LPTIM45CKSELR U(0X630)
+#define RCC_SAI1CKSELR U(0X634)
+#define RCC_SAI2CKSELR U(0X638)
+#define RCC_FDCANCKSELR U(0X63C)
+#define RCC_SPDIFCKSELR U(0X640)
+#define RCC_ADC12CKSELR U(0X644)
+#define RCC_SDMMC12CKSELR U(0X648)
+#define RCC_ETH12CKSELR U(0X64C)
+#define RCC_USBCKSELR U(0X650)
+#define RCC_QSPICKSELR U(0X654)
+#define RCC_FMCCKSELR U(0X658)
+#define RCC_RNG1CKSELR U(0X65C)
+#define RCC_STGENCKSELR U(0X660)
+#define RCC_DCMIPPCKSELR U(0X664)
+#define RCC_SAESCKSELR U(0X668)
+#define RCC_APB1RSTSETR U(0X6A0)
+#define RCC_APB1RSTCLRR U(0X6A4)
+#define RCC_APB2RSTSETR U(0X6A8)
+#define RCC_APB2RSTCLRR U(0X6AC)
+#define RCC_APB3RSTSETR U(0X6B0)
+#define RCC_APB3RSTCLRR U(0X6B4)
+#define RCC_APB4RSTSETR U(0X6B8)
+#define RCC_APB4RSTCLRR U(0X6BC)
+#define RCC_APB5RSTSETR U(0X6C0)
+#define RCC_APB5RSTCLRR U(0X6C4)
+#define RCC_APB6RSTSETR U(0X6C8)
+#define RCC_APB6RSTCLRR U(0X6CC)
+#define RCC_AHB2RSTSETR U(0X6D0)
+#define RCC_AHB2RSTCLRR U(0X6D4)
+#define RCC_AHB4RSTSETR U(0X6E0)
+#define RCC_AHB4RSTCLRR U(0X6E4)
+#define RCC_AHB5RSTSETR U(0X6E8)
+#define RCC_AHB5RSTCLRR U(0X6EC)
+#define RCC_AHB6RSTSETR U(0X6F0)
+#define RCC_AHB6RSTCLRR U(0X6F4)
+#define RCC_MP_APB1ENSETR U(0X700)
+#define RCC_MP_APB1ENCLRR U(0X704)
+#define RCC_MP_APB2ENSETR U(0X708)
+#define RCC_MP_APB2ENCLRR U(0X70C)
+#define RCC_MP_APB3ENSETR U(0X710)
+#define RCC_MP_APB3ENCLRR U(0X714)
+#define RCC_MP_S_APB3ENSETR U(0X718)
+#define RCC_MP_S_APB3ENCLRR U(0X71C)
+#define RCC_MP_NS_APB3ENSETR U(0X720)
+#define RCC_MP_NS_APB3ENCLRR U(0X724)
+#define RCC_MP_APB4ENSETR U(0X728)
+#define RCC_MP_APB4ENCLRR U(0X72C)
+#define RCC_MP_S_APB4ENSETR U(0X730)
+#define RCC_MP_S_APB4ENCLRR U(0X734)
+#define RCC_MP_NS_APB4ENSETR U(0X738)
+#define RCC_MP_NS_APB4ENCLRR U(0X73C)
+#define RCC_MP_APB5ENSETR U(0X740)
+#define RCC_MP_APB5ENCLRR U(0X744)
+#define RCC_MP_APB6ENSETR U(0X748)
+#define RCC_MP_APB6ENCLRR U(0X74C)
+#define RCC_MP_AHB2ENSETR U(0X750)
+#define RCC_MP_AHB2ENCLRR U(0X754)
+#define RCC_MP_AHB4ENSETR U(0X760)
+#define RCC_MP_AHB4ENCLRR U(0X764)
+#define RCC_MP_S_AHB4ENSETR U(0X768)
+#define RCC_MP_S_AHB4ENCLRR U(0X76C)
+#define RCC_MP_NS_AHB4ENSETR U(0X770)
+#define RCC_MP_NS_AHB4ENCLRR U(0X774)
+#define RCC_MP_AHB5ENSETR U(0X778)
+#define RCC_MP_AHB5ENCLRR U(0X77C)
+#define RCC_MP_AHB6ENSETR U(0X780)
+#define RCC_MP_AHB6ENCLRR U(0X784)
+#define RCC_MP_S_AHB6ENSETR U(0X788)
+#define RCC_MP_S_AHB6ENCLRR U(0X78C)
+#define RCC_MP_NS_AHB6ENSETR U(0X790)
+#define RCC_MP_NS_AHB6ENCLRR U(0X794)
+#define RCC_MP_APB1LPENSETR U(0X800)
+#define RCC_MP_APB1LPENCLRR U(0X804)
+#define RCC_MP_APB2LPENSETR U(0X808)
+#define RCC_MP_APB2LPENCLRR U(0X80C)
+#define RCC_MP_APB3LPENSETR U(0X810)
+#define RCC_MP_APB3LPENCLRR U(0X814)
+#define RCC_MP_S_APB3LPENSETR U(0X818)
+#define RCC_MP_S_APB3LPENCLRR U(0X81C)
+#define RCC_MP_NS_APB3LPENSETR U(0X820)
+#define RCC_MP_NS_APB3LPENCLRR U(0X824)
+#define RCC_MP_APB4LPENSETR U(0X828)
+#define RCC_MP_APB4LPENCLRR U(0X82C)
+#define RCC_MP_S_APB4LPENSETR U(0X830)
+#define RCC_MP_S_APB4LPENCLRR U(0X834)
+#define RCC_MP_NS_APB4LPENSETR U(0X838)
+#define RCC_MP_NS_APB4LPENCLRR U(0X83C)
+#define RCC_MP_APB5LPENSETR U(0X840)
+#define RCC_MP_APB5LPENCLRR U(0X844)
+#define RCC_MP_APB6LPENSETR U(0X848)
+#define RCC_MP_APB6LPENCLRR U(0X84C)
+#define RCC_MP_AHB2LPENSETR U(0X850)
+#define RCC_MP_AHB2LPENCLRR U(0X854)
+#define RCC_MP_AHB4LPENSETR U(0X858)
+#define RCC_MP_AHB4LPENCLRR U(0X85C)
+#define RCC_MP_S_AHB4LPENSETR U(0X868)
+#define RCC_MP_S_AHB4LPENCLRR U(0X86C)
+#define RCC_MP_NS_AHB4LPENSETR U(0X870)
+#define RCC_MP_NS_AHB4LPENCLRR U(0X874)
+#define RCC_MP_AHB5LPENSETR U(0X878)
+#define RCC_MP_AHB5LPENCLRR U(0X87C)
+#define RCC_MP_AHB6LPENSETR U(0X880)
+#define RCC_MP_AHB6LPENCLRR U(0X884)
+#define RCC_MP_S_AHB6LPENSETR U(0X888)
+#define RCC_MP_S_AHB6LPENCLRR U(0X88C)
+#define RCC_MP_NS_AHB6LPENSETR U(0X890)
+#define RCC_MP_NS_AHB6LPENCLRR U(0X894)
+#define RCC_MP_S_AXIMLPENSETR U(0X898)
+#define RCC_MP_S_AXIMLPENCLRR U(0X89C)
+#define RCC_MP_NS_AXIMLPENSETR U(0X8A0)
+#define RCC_MP_NS_AXIMLPENCLRR U(0X8A4)
+#define RCC_MP_MLAHBLPENSETR U(0X8A8)
+#define RCC_MP_MLAHBLPENCLRR U(0X8AC)
+#define RCC_APB3SECSR U(0X8C0)
+#define RCC_APB4SECSR U(0X8C4)
+#define RCC_APB5SECSR U(0X8C8)
+#define RCC_APB6SECSR U(0X8CC)
+#define RCC_AHB2SECSR U(0X8D0)
+#define RCC_AHB4SECSR U(0X8D4)
+#define RCC_AHB5SECSR U(0X8D8)
+#define RCC_AHB6SECSR U(0X8DC)
+#define RCC_VERR U(0XFF4)
+#define RCC_IDR U(0XFF8)
+#define RCC_SIDR U(0XFFC)
+
+/* RCC_SECCFGR register fields */
+#define RCC_SECCFGR_HSISEC BIT(0)
+#define RCC_SECCFGR_CSISEC BIT(1)
+#define RCC_SECCFGR_HSESEC BIT(2)
+#define RCC_SECCFGR_LSISEC BIT(3)
+#define RCC_SECCFGR_LSESEC BIT(4)
+#define RCC_SECCFGR_PLL12SEC BIT(8)
+#define RCC_SECCFGR_PLL3SEC BIT(9)
+#define RCC_SECCFGR_PLL4SEC BIT(10)
+#define RCC_SECCFGR_MPUSEC BIT(11)
+#define RCC_SECCFGR_AXISEC BIT(12)
+#define RCC_SECCFGR_MLAHBSEC BIT(13)
+#define RCC_SECCFGR_APB3DIVSEC BIT(16)
+#define RCC_SECCFGR_APB4DIVSEC BIT(17)
+#define RCC_SECCFGR_APB5DIVSEC BIT(18)
+#define RCC_SECCFGR_APB6DIVSEC BIT(19)
+#define RCC_SECCFGR_TIMG3SEC BIT(20)
+#define RCC_SECCFGR_CPERSEC BIT(21)
+#define RCC_SECCFGR_MCO1SEC BIT(22)
+#define RCC_SECCFGR_MCO2SEC BIT(23)
+#define RCC_SECCFGR_STPSEC BIT(24)
+#define RCC_SECCFGR_RSTSEC BIT(25)
+#define RCC_SECCFGR_PWRSEC BIT(31)
+
+/* RCC_MP_SREQSETR register fields */
+#define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
+
+/* RCC_MP_SREQCLRR register fields */
+#define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
+
+/* RCC_MP_APRSTCR register fields */
+#define RCC_MP_APRSTCR_RDCTLEN BIT(0)
+#define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8)
+#define RCC_MP_APRSTCR_RSTTO_SHIFT 8
+
+/* RCC_MP_APRSTSR register fields */
+#define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8)
+#define RCC_MP_APRSTSR_RSTTOV_SHIFT 8
+
+/* RCC_PWRLPDLYCR register fields */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0)
+#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0
+
+/* RCC_MP_GRSTCSETR register fields */
+#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
+#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
+
+/* RCC_BR_RSTSCLRR register fields */
+#define RCC_BR_RSTSCLRR_PORRSTF BIT(0)
+#define RCC_BR_RSTSCLRR_BORRSTF BIT(1)
+#define RCC_BR_RSTSCLRR_PADRSTF BIT(2)
+#define RCC_BR_RSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_BR_RSTSCLRR_VCORERSTF BIT(4)
+#define RCC_BR_RSTSCLRR_VCPURSTF BIT(5)
+#define RCC_BR_RSTSCLRR_MPSYSRSTF BIT(6)
+#define RCC_BR_RSTSCLRR_IWDG1RSTF BIT(8)
+#define RCC_BR_RSTSCLRR_IWDG2RSTF BIT(9)
+#define RCC_BR_RSTSCLRR_MPUP0RSTF BIT(13)
+
+/* RCC_MP_RSTSSETR register fields */
+#define RCC_MP_RSTSSETR_PORRSTF BIT(0)
+#define RCC_MP_RSTSSETR_BORRSTF BIT(1)
+#define RCC_MP_RSTSSETR_PADRSTF BIT(2)
+#define RCC_MP_RSTSSETR_HCSSRSTF BIT(3)
+#define RCC_MP_RSTSSETR_VCORERSTF BIT(4)
+#define RCC_MP_RSTSSETR_VCPURSTF BIT(5)
+#define RCC_MP_RSTSSETR_MPSYSRSTF BIT(6)
+#define RCC_MP_RSTSSETR_IWDG1RSTF BIT(8)
+#define RCC_MP_RSTSSETR_IWDG2RSTF BIT(9)
+#define RCC_MP_RSTSSETR_STP2RSTF BIT(10)
+#define RCC_MP_RSTSSETR_STDBYRSTF BIT(11)
+#define RCC_MP_RSTSSETR_CSTDBYRSTF BIT(12)
+#define RCC_MP_RSTSSETR_MPUP0RSTF BIT(13)
+#define RCC_MP_RSTSSETR_SPARE BIT(15)
+
+/* RCC_MP_RSTSCLRR register fields */
+#define RCC_MP_RSTSCLRR_PORRSTF BIT(0)
+#define RCC_MP_RSTSCLRR_BORRSTF BIT(1)
+#define RCC_MP_RSTSCLRR_PADRSTF BIT(2)
+#define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_MP_RSTSCLRR_VCORERSTF BIT(4)
+#define RCC_MP_RSTSCLRR_VCPURSTF BIT(5)
+#define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6)
+#define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8)
+#define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9)
+#define RCC_MP_RSTSCLRR_STP2RSTF BIT(10)
+#define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11)
+#define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12)
+#define RCC_MP_RSTSCLRR_MPUP0RSTF BIT(13)
+#define RCC_MP_RSTSCLRR_SPARE BIT(15)
+
+/* RCC_MP_IWDGFZSETR register fields */
+#define RCC_MP_IWDGFZSETR_FZ_IWDG1 BIT(0)
+#define RCC_MP_IWDGFZSETR_FZ_IWDG2 BIT(1)
+
+/* RCC_MP_IWDGFZCLRR register fields */
+#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 BIT(0)
+#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 BIT(1)
+
+/* RCC_MP_CIER register fields */
+#define RCC_MP_CIER_LSIRDYIE BIT(0)
+#define RCC_MP_CIER_LSERDYIE BIT(1)
+#define RCC_MP_CIER_HSIRDYIE BIT(2)
+#define RCC_MP_CIER_HSERDYIE BIT(3)
+#define RCC_MP_CIER_CSIRDYIE BIT(4)
+#define RCC_MP_CIER_PLL1DYIE BIT(8)
+#define RCC_MP_CIER_PLL2DYIE BIT(9)
+#define RCC_MP_CIER_PLL3DYIE BIT(10)
+#define RCC_MP_CIER_PLL4DYIE BIT(11)
+#define RCC_MP_CIER_LSECSSIE BIT(16)
+#define RCC_MP_CIER_WKUPIE BIT(20)
+
+/* RCC_MP_CIFR register fields */
+#define RCC_MP_CIFR_LSIRDYF BIT(0)
+#define RCC_MP_CIFR_LSERDYF BIT(1)
+#define RCC_MP_CIFR_HSIRDYF BIT(2)
+#define RCC_MP_CIFR_HSERDYF BIT(3)
+#define RCC_MP_CIFR_CSIRDYF BIT(4)
+#define RCC_MP_CIFR_PLL1DYF BIT(8)
+#define RCC_MP_CIFR_PLL2DYF BIT(9)
+#define RCC_MP_CIFR_PLL3DYF BIT(10)
+#define RCC_MP_CIFR_PLL4DYF BIT(11)
+#define RCC_MP_CIFR_LSECSSF BIT(16)
+#define RCC_MP_CIFR_WKUPF BIT(20)
+
+/* RCC_BDCR register fields */
+#define RCC_BDCR_LSEON BIT(0)
+#define RCC_BDCR_LSEBYP BIT(1)
+#define RCC_BDCR_LSERDY BIT(2)
+#define RCC_BDCR_DIGBYP BIT(3)
+#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
+#define RCC_BDCR_LSEDRV_SHIFT 4
+#define RCC_BDCR_LSECSSON BIT(8)
+#define RCC_BDCR_LSECSSD BIT(9)
+#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
+#define RCC_BDCR_RTCSRC_SHIFT 16
+#define RCC_BDCR_RTCCKEN BIT(20)
+#define RCC_BDCR_VSWRST BIT(31)
+
+#define RCC_BDCR_LSEBYP_BIT 1
+#define RCC_BDCR_LSERDY_BIT 2
+#define RCC_BDCR_DIGBYP_BIT 3
+#define RCC_BDCR_LSECSSON_BIT 8
+
+#define RCC_BDCR_LSEDRV_WIDTH 2
+
+/* RCC_RDLSICR register fields */
+#define RCC_RDLSICR_LSION BIT(0)
+#define RCC_RDLSICR_LSIRDY BIT(1)
+#define RCC_RDLSICR_MRD_MASK GENMASK(20, 16)
+#define RCC_RDLSICR_MRD_SHIFT 16
+#define RCC_RDLSICR_EADLY_MASK GENMASK(26, 24)
+#define RCC_RDLSICR_EADLY_SHIFT 24
+#define RCC_RDLSICR_SPARE_MASK GENMASK(31, 27)
+#define RCC_RDLSICR_SPARE_SHIFT 27
+
+#define RCC_RDLSICR_LSIRDY_BIT 1
+
+/* RCC_OCENSETR register fields */
+#define RCC_OCENSETR_HSION BIT(0)
+#define RCC_OCENSETR_HSIKERON BIT(1)
+#define RCC_OCENSETR_CSION BIT(4)
+#define RCC_OCENSETR_CSIKERON BIT(5)
+#define RCC_OCENSETR_DIGBYP BIT(7)
+#define RCC_OCENSETR_HSEON BIT(8)
+#define RCC_OCENSETR_HSEKERON BIT(9)
+#define RCC_OCENSETR_HSEBYP BIT(10)
+#define RCC_OCENSETR_HSECSSON BIT(11)
+
+#define RCC_OCENR_DIGBYP_BIT 7
+#define RCC_OCENR_HSEBYP_BIT 10
+#define RCC_OCENR_HSECSSON_BIT 11
+
+/* RCC_OCENCLRR register fields */
+#define RCC_OCENCLRR_HSION BIT(0)
+#define RCC_OCENCLRR_HSIKERON BIT(1)
+#define RCC_OCENCLRR_CSION BIT(4)
+#define RCC_OCENCLRR_CSIKERON BIT(5)
+#define RCC_OCENCLRR_DIGBYP BIT(7)
+#define RCC_OCENCLRR_HSEON BIT(8)
+#define RCC_OCENCLRR_HSEKERON BIT(9)
+#define RCC_OCENCLRR_HSEBYP BIT(10)
+
+/* RCC_OCRDYR register fields */
+#define RCC_OCRDYR_HSIRDY BIT(0)
+#define RCC_OCRDYR_HSIDIVRDY BIT(2)
+#define RCC_OCRDYR_CSIRDY BIT(4)
+#define RCC_OCRDYR_HSERDY BIT(8)
+#define RCC_OCRDYR_MPUCKRDY BIT(23)
+#define RCC_OCRDYR_AXICKRDY BIT(24)
+
+#define RCC_OCRDYR_HSIRDY_BIT 0
+#define RCC_OCRDYR_HSIDIVRDY_BIT 2
+#define RCC_OCRDYR_CSIRDY_BIT 4
+#define RCC_OCRDYR_HSERDY_BIT 8
+
+/* RCC_HSICFGR register fields */
+#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
+#define RCC_HSICFGR_HSIDIV_SHIFT 0
+#define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8)
+#define RCC_HSICFGR_HSITRIM_SHIFT 8
+#define RCC_HSICFGR_HSICAL_MASK GENMASK(27, 16)
+#define RCC_HSICFGR_HSICAL_SHIFT 16
+
+/* RCC_CSICFGR register fields */
+#define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8)
+#define RCC_CSICFGR_CSITRIM_SHIFT 8
+#define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16)
+#define RCC_CSICFGR_CSICAL_SHIFT 16
+
+/* RCC_MCO1CFGR register fields */
+#define RCC_MCO1CFGR_MCO1SEL_MASK GENMASK(2, 0)
+#define RCC_MCO1CFGR_MCO1SEL_SHIFT 0
+#define RCC_MCO1CFGR_MCO1DIV_MASK GENMASK(7, 4)
+#define RCC_MCO1CFGR_MCO1DIV_SHIFT 4
+#define RCC_MCO1CFGR_MCO1ON BIT(12)
+
+/* RCC_MCO2CFGR register fields */
+#define RCC_MCO2CFGR_MCO2SEL_MASK GENMASK(2, 0)
+#define RCC_MCO2CFGR_MCO2SEL_SHIFT 0
+#define RCC_MCO2CFGR_MCO2DIV_MASK GENMASK(7, 4)
+#define RCC_MCO2CFGR_MCO2DIV_SHIFT 4
+#define RCC_MCO2CFGR_MCO2ON BIT(12)
+
+/* RCC_DBGCFGR register fields */
+#define RCC_DBGCFGR_TRACEDIV_MASK GENMASK(2, 0)
+#define RCC_DBGCFGR_TRACEDIV_SHIFT 0
+#define RCC_DBGCFGR_DBGCKEN BIT(8)
+#define RCC_DBGCFGR_TRACECKEN BIT(9)
+#define RCC_DBGCFGR_DBGRST BIT(12)
+
+/* RCC_RCK12SELR register fields */
+#define RCC_RCK12SELR_PLL12SRC_MASK GENMASK(1, 0)
+#define RCC_RCK12SELR_PLL12SRC_SHIFT 0
+#define RCC_RCK12SELR_PLL12SRCRDY BIT(31)
+
+/* RCC_RCK3SELR register fields */
+#define RCC_RCK3SELR_PLL3SRC_MASK GENMASK(1, 0)
+#define RCC_RCK3SELR_PLL3SRC_SHIFT 0
+#define RCC_RCK3SELR_PLL3SRCRDY BIT(31)
+
+/* RCC_RCK4SELR register fields */
+#define RCC_RCK4SELR_PLL4SRC_MASK GENMASK(1, 0)
+#define RCC_RCK4SELR_PLL4SRC_SHIFT 0
+#define RCC_RCK4SELR_PLL4SRCRDY BIT(31)
+
+/* RCC_PLL1CR register fields */
+#define RCC_PLL1CR_PLLON BIT(0)
+#define RCC_PLL1CR_PLL1RDY BIT(1)
+#define RCC_PLL1CR_SSCG_CTRL BIT(2)
+#define RCC_PLL1CR_DIVPEN BIT(4)
+#define RCC_PLL1CR_DIVQEN BIT(5)
+#define RCC_PLL1CR_DIVREN BIT(6)
+
+/* RCC_PLL1CFGR1 register fields */
+#define RCC_PLL1CFGR1_DIVN_MASK GENMASK(8, 0)
+#define RCC_PLL1CFGR1_DIVN_SHIFT 0
+#define RCC_PLL1CFGR1_DIVM1_MASK GENMASK(21, 16)
+#define RCC_PLL1CFGR1_DIVM1_SHIFT 16
+
+/* RCC_PLL1CFGR2 register fields */
+#define RCC_PLL1CFGR2_DIVP_MASK GENMASK(6, 0)
+#define RCC_PLL1CFGR2_DIVP_SHIFT 0
+#define RCC_PLL1CFGR2_DIVQ_MASK GENMASK(14, 8)
+#define RCC_PLL1CFGR2_DIVQ_SHIFT 8
+#define RCC_PLL1CFGR2_DIVR_MASK GENMASK(22, 16)
+#define RCC_PLL1CFGR2_DIVR_SHIFT 16
+
+/* RCC_PLL1FRACR register fields */
+#define RCC_PLL1FRACR_FRACV_MASK GENMASK(15, 3)
+#define RCC_PLL1FRACR_FRACV_SHIFT 3
+#define RCC_PLL1FRACR_FRACLE BIT(16)
+
+/* RCC_PLL1CSGR register fields */
+#define RCC_PLL1CSGR_MOD_PER_MASK GENMASK(12, 0)
+#define RCC_PLL1CSGR_MOD_PER_SHIFT 0
+#define RCC_PLL1CSGR_TPDFN_DIS BIT(13)
+#define RCC_PLL1CSGR_RPDFN_DIS BIT(14)
+#define RCC_PLL1CSGR_SSCG_MODE BIT(15)
+#define RCC_PLL1CSGR_INC_STEP_MASK GENMASK(30, 16)
+#define RCC_PLL1CSGR_INC_STEP_SHIFT 16
+
+/* RCC_PLL2CR register fields */
+#define RCC_PLL2CR_PLLON BIT(0)
+#define RCC_PLL2CR_PLL2RDY BIT(1)
+#define RCC_PLL2CR_SSCG_CTRL BIT(2)
+#define RCC_PLL2CR_DIVPEN BIT(4)
+#define RCC_PLL2CR_DIVQEN BIT(5)
+#define RCC_PLL2CR_DIVREN BIT(6)
+
+/* RCC_PLL2CFGR1 register fields */
+#define RCC_PLL2CFGR1_DIVN_MASK GENMASK(8, 0)
+#define RCC_PLL2CFGR1_DIVN_SHIFT 0
+#define RCC_PLL2CFGR1_DIVM2_MASK GENMASK(21, 16)
+#define RCC_PLL2CFGR1_DIVM2_SHIFT 16
+
+/* RCC_PLL2CFGR2 register fields */
+#define RCC_PLL2CFGR2_DIVP_MASK GENMASK(6, 0)
+#define RCC_PLL2CFGR2_DIVP_SHIFT 0
+#define RCC_PLL2CFGR2_DIVQ_MASK GENMASK(14, 8)
+#define RCC_PLL2CFGR2_DIVQ_SHIFT 8
+#define RCC_PLL2CFGR2_DIVR_MASK GENMASK(22, 16)
+#define RCC_PLL2CFGR2_DIVR_SHIFT 16
+
+/* RCC_PLL2FRACR register fields */
+#define RCC_PLL2FRACR_FRACV_MASK GENMASK(15, 3)
+#define RCC_PLL2FRACR_FRACV_SHIFT 3
+#define RCC_PLL2FRACR_FRACLE BIT(16)
+
+/* RCC_PLL2CSGR register fields */
+#define RCC_PLL2CSGR_MOD_PER_MASK GENMASK(12, 0)
+#define RCC_PLL2CSGR_MOD_PER_SHIFT 0
+#define RCC_PLL2CSGR_TPDFN_DIS BIT(13)
+#define RCC_PLL2CSGR_RPDFN_DIS BIT(14)
+#define RCC_PLL2CSGR_SSCG_MODE BIT(15)
+#define RCC_PLL2CSGR_INC_STEP_MASK GENMASK(30, 16)
+#define RCC_PLL2CSGR_INC_STEP_SHIFT 16
+
+/* RCC_PLL3CR register fields */
+#define RCC_PLL3CR_PLLON BIT(0)
+#define RCC_PLL3CR_PLL3RDY BIT(1)
+#define RCC_PLL3CR_SSCG_CTRL BIT(2)
+#define RCC_PLL3CR_DIVPEN BIT(4)
+#define RCC_PLL3CR_DIVQEN BIT(5)
+#define RCC_PLL3CR_DIVREN BIT(6)
+
+/* RCC_PLL3CFGR1 register fields */
+#define RCC_PLL3CFGR1_DIVN_MASK GENMASK(8, 0)
+#define RCC_PLL3CFGR1_DIVN_SHIFT 0
+#define RCC_PLL3CFGR1_DIVM3_MASK GENMASK(21, 16)
+#define RCC_PLL3CFGR1_DIVM3_SHIFT 16
+#define RCC_PLL3CFGR1_IFRGE_MASK GENMASK(25, 24)
+#define RCC_PLL3CFGR1_IFRGE_SHIFT 24
+
+/* RCC_PLL3CFGR2 register fields */
+#define RCC_PLL3CFGR2_DIVP_MASK GENMASK(6, 0)
+#define RCC_PLL3CFGR2_DIVP_SHIFT 0
+#define RCC_PLL3CFGR2_DIVQ_MASK GENMASK(14, 8)
+#define RCC_PLL3CFGR2_DIVQ_SHIFT 8
+#define RCC_PLL3CFGR2_DIVR_MASK GENMASK(22, 16)
+#define RCC_PLL3CFGR2_DIVR_SHIFT 16
+
+/* RCC_PLL3FRACR register fields */
+#define RCC_PLL3FRACR_FRACV_MASK GENMASK(15, 3)
+#define RCC_PLL3FRACR_FRACV_SHIFT 3
+#define RCC_PLL3FRACR_FRACLE BIT(16)
+
+/* RCC_PLL3CSGR register fields */
+#define RCC_PLL3CSGR_MOD_PER_MASK GENMASK(12, 0)
+#define RCC_PLL3CSGR_MOD_PER_SHIFT 0
+#define RCC_PLL3CSGR_TPDFN_DIS BIT(13)
+#define RCC_PLL3CSGR_RPDFN_DIS BIT(14)
+#define RCC_PLL3CSGR_SSCG_MODE BIT(15)
+#define RCC_PLL3CSGR_INC_STEP_MASK GENMASK(30, 16)
+#define RCC_PLL3CSGR_INC_STEP_SHIFT 16
+
+/* RCC_PLL4CR register fields */
+#define RCC_PLL4CR_PLLON BIT(0)
+#define RCC_PLL4CR_PLL4RDY BIT(1)
+#define RCC_PLL4CR_SSCG_CTRL BIT(2)
+#define RCC_PLL4CR_DIVPEN BIT(4)
+#define RCC_PLL4CR_DIVQEN BIT(5)
+#define RCC_PLL4CR_DIVREN BIT(6)
+
+/* RCC_PLL4CFGR1 register fields */
+#define RCC_PLL4CFGR1_DIVN_MASK GENMASK(8, 0)
+#define RCC_PLL4CFGR1_DIVN_SHIFT 0
+#define RCC_PLL4CFGR1_DIVM4_MASK GENMASK(21, 16)
+#define RCC_PLL4CFGR1_DIVM4_SHIFT 16
+#define RCC_PLL4CFGR1_IFRGE_MASK GENMASK(25, 24)
+#define RCC_PLL4CFGR1_IFRGE_SHIFT 24
+
+/* RCC_PLL4CFGR2 register fields */
+#define RCC_PLL4CFGR2_DIVP_MASK GENMASK(6, 0)
+#define RCC_PLL4CFGR2_DIVP_SHIFT 0
+#define RCC_PLL4CFGR2_DIVQ_MASK GENMASK(14, 8)
+#define RCC_PLL4CFGR2_DIVQ_SHIFT 8
+#define RCC_PLL4CFGR2_DIVR_MASK GENMASK(22, 16)
+#define RCC_PLL4CFGR2_DIVR_SHIFT 16
+
+/* RCC_PLL4FRACR register fields */
+#define RCC_PLL4FRACR_FRACV_MASK GENMASK(15, 3)
+#define RCC_PLL4FRACR_FRACV_SHIFT 3
+#define RCC_PLL4FRACR_FRACLE BIT(16)
+
+/* RCC_PLL4CSGR register fields */
+#define RCC_PLL4CSGR_MOD_PER_MASK GENMASK(12, 0)
+#define RCC_PLL4CSGR_MOD_PER_SHIFT 0
+#define RCC_PLL4CSGR_TPDFN_DIS BIT(13)
+#define RCC_PLL4CSGR_RPDFN_DIS BIT(14)
+#define RCC_PLL4CSGR_SSCG_MODE BIT(15)
+#define RCC_PLL4CSGR_INC_STEP_MASK GENMASK(30, 16)
+#define RCC_PLL4CSGR_INC_STEP_SHIFT 16
+
+/* RCC_MPCKSELR register fields */
+#define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0)
+#define RCC_MPCKSELR_MPUSRC_SHIFT 0
+#define RCC_MPCKSELR_MPUSRCRDY BIT(31)
+
+/* RCC_ASSCKSELR register fields */
+#define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0)
+#define RCC_ASSCKSELR_AXISSRC_SHIFT 0
+#define RCC_ASSCKSELR_AXISSRCRDY BIT(31)
+
+/* RCC_MSSCKSELR register fields */
+#define RCC_MSSCKSELR_MLAHBSSRC_MASK GENMASK(1, 0)
+#define RCC_MSSCKSELR_MLAHBSSRC_SHIFT 0
+#define RCC_MSSCKSELR_MLAHBSSRCRDY BIT(31)
+
+/* RCC_CPERCKSELR register fields */
+#define RCC_CPERCKSELR_CKPERSRC_MASK GENMASK(1, 0)
+#define RCC_CPERCKSELR_CKPERSRC_SHIFT 0
+
+/* RCC_RTCDIVR register fields */
+#define RCC_RTCDIVR_RTCDIV_MASK GENMASK(5, 0)
+#define RCC_RTCDIVR_RTCDIV_SHIFT 0
+
+/* RCC_MPCKDIVR register fields */
+#define RCC_MPCKDIVR_MPUDIV_MASK GENMASK(3, 0)
+#define RCC_MPCKDIVR_MPUDIV_SHIFT 0
+#define RCC_MPCKDIVR_MPUDIVRDY BIT(31)
+
+/* RCC_AXIDIVR register fields */
+#define RCC_AXIDIVR_AXIDIV_MASK GENMASK(2, 0)
+#define RCC_AXIDIVR_AXIDIV_SHIFT 0
+#define RCC_AXIDIVR_AXIDIVRDY BIT(31)
+
+/* RCC_MLAHBDIVR register fields */
+#define RCC_MLAHBDIVR_MLAHBDIV_MASK GENMASK(3, 0)
+#define RCC_MLAHBDIVR_MLAHBDIV_SHIFT 0
+#define RCC_MLAHBDIVR_MLAHBDIVRDY BIT(31)
+
+/* RCC_APB1DIVR register fields */
+#define RCC_APB1DIVR_APB1DIV_MASK GENMASK(2, 0)
+#define RCC_APB1DIVR_APB1DIV_SHIFT 0
+#define RCC_APB1DIVR_APB1DIVRDY BIT(31)
+
+/* RCC_APB2DIVR register fields */
+#define RCC_APB2DIVR_APB2DIV_MASK GENMASK(2, 0)
+#define RCC_APB2DIVR_APB2DIV_SHIFT 0
+#define RCC_APB2DIVR_APB2DIVRDY BIT(31)
+
+/* RCC_APB3DIVR register fields */
+#define RCC_APB3DIVR_APB3DIV_MASK GENMASK(2, 0)
+#define RCC_APB3DIVR_APB3DIV_SHIFT 0
+#define RCC_APB3DIVR_APB3DIVRDY BIT(31)
+
+/* RCC_APB4DIVR register fields */
+#define RCC_APB4DIVR_APB4DIV_MASK GENMASK(2, 0)
+#define RCC_APB4DIVR_APB4DIV_SHIFT 0
+#define RCC_APB4DIVR_APB4DIVRDY BIT(31)
+
+/* RCC_APB5DIVR register fields */
+#define RCC_APB5DIVR_APB5DIV_MASK GENMASK(2, 0)
+#define RCC_APB5DIVR_APB5DIV_SHIFT 0
+#define RCC_APB5DIVR_APB5DIVRDY BIT(31)
+
+/* RCC_APB6DIVR register fields */
+#define RCC_APB6DIVR_APB6DIV_MASK GENMASK(2, 0)
+#define RCC_APB6DIVR_APB6DIV_SHIFT 0
+#define RCC_APB6DIVR_APB6DIVRDY BIT(31)
+
+/* RCC_TIMG1PRER register fields */
+#define RCC_TIMG1PRER_TIMG1PRE BIT(0)
+#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31)
+
+/* RCC_TIMG2PRER register fields */
+#define RCC_TIMG2PRER_TIMG2PRE BIT(0)
+#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31)
+
+/* RCC_TIMG3PRER register fields */
+#define RCC_TIMG3PRER_TIMG3PRE BIT(0)
+#define RCC_TIMG3PRER_TIMG3PRERDY BIT(31)
+
+/* RCC_DDRITFCR register fields */
+#define RCC_DDRITFCR_DDRC1EN BIT(0)
+#define RCC_DDRITFCR_DDRC1LPEN BIT(1)
+#define RCC_DDRITFCR_DDRPHYCEN BIT(4)
+#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5)
+#define RCC_DDRITFCR_DDRCAPBEN BIT(6)
+#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7)
+#define RCC_DDRITFCR_AXIDCGEN BIT(8)
+#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9)
+#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10)
+#define RCC_DDRITFCR_KERDCG_DLY_MASK GENMASK(13, 11)
+#define RCC_DDRITFCR_KERDCG_DLY_SHIFT 11
+#define RCC_DDRITFCR_DDRCAPBRST BIT(14)
+#define RCC_DDRITFCR_DDRCAXIRST BIT(15)
+#define RCC_DDRITFCR_DDRCORERST BIT(16)
+#define RCC_DDRITFCR_DPHYAPBRST BIT(17)
+#define RCC_DDRITFCR_DPHYRST BIT(18)
+#define RCC_DDRITFCR_DPHYCTLRST BIT(19)
+#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
+#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
+#define RCC_DDRITFCR_GSKPMOD BIT(23)
+#define RCC_DDRITFCR_GSKPCTRL BIT(24)
+#define RCC_DDRITFCR_DFILP_WIDTH_MASK GENMASK(27, 25)
+#define RCC_DDRITFCR_DFILP_WIDTH_SHIFT 25
+#define RCC_DDRITFCR_GSKP_DUR_MASK GENMASK(31, 28)
+#define RCC_DDRITFCR_GSKP_DUR_SHIFT 28
+
+/* RCC_I2C12CKSELR register fields */
+#define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0)
+#define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0
+
+/* RCC_I2C345CKSELR register fields */
+#define RCC_I2C345CKSELR_I2C3SRC_MASK GENMASK(2, 0)
+#define RCC_I2C345CKSELR_I2C3SRC_SHIFT 0
+#define RCC_I2C345CKSELR_I2C4SRC_MASK GENMASK(5, 3)
+#define RCC_I2C345CKSELR_I2C4SRC_SHIFT 3
+#define RCC_I2C345CKSELR_I2C5SRC_MASK GENMASK(8, 6)
+#define RCC_I2C345CKSELR_I2C5SRC_SHIFT 6
+
+/* RCC_SPI2S1CKSELR register fields */
+#define RCC_SPI2S1CKSELR_SPI1SRC_MASK GENMASK(2, 0)
+#define RCC_SPI2S1CKSELR_SPI1SRC_SHIFT 0
+
+/* RCC_SPI2S23CKSELR register fields */
+#define RCC_SPI2S23CKSELR_SPI23SRC_MASK GENMASK(2, 0)
+#define RCC_SPI2S23CKSELR_SPI23SRC_SHIFT 0
+
+/* RCC_SPI45CKSELR register fields */
+#define RCC_SPI45CKSELR_SPI4SRC_MASK GENMASK(2, 0)
+#define RCC_SPI45CKSELR_SPI4SRC_SHIFT 0
+#define RCC_SPI45CKSELR_SPI5SRC_MASK GENMASK(5, 3)
+#define RCC_SPI45CKSELR_SPI5SRC_SHIFT 3
+
+/* RCC_UART12CKSELR register fields */
+#define RCC_UART12CKSELR_UART1SRC_MASK GENMASK(2, 0)
+#define RCC_UART12CKSELR_UART1SRC_SHIFT 0
+#define RCC_UART12CKSELR_UART2SRC_MASK GENMASK(5, 3)
+#define RCC_UART12CKSELR_UART2SRC_SHIFT 3
+
+/* RCC_UART35CKSELR register fields */
+#define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0)
+#define RCC_UART35CKSELR_UART35SRC_SHIFT 0
+
+/* RCC_UART4CKSELR register fields */
+#define RCC_UART4CKSELR_UART4SRC_MASK GENMASK(2, 0)
+#define RCC_UART4CKSELR_UART4SRC_SHIFT 0
+
+/* RCC_UART6CKSELR register fields */
+#define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0)
+#define RCC_UART6CKSELR_UART6SRC_SHIFT 0
+
+/* RCC_UART78CKSELR register fields */
+#define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0)
+#define RCC_UART78CKSELR_UART78SRC_SHIFT 0
+
+/* RCC_LPTIM1CKSELR register fields */
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_MASK GENMASK(2, 0)
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_SHIFT 0
+
+/* RCC_LPTIM23CKSELR register fields */
+#define RCC_LPTIM23CKSELR_LPTIM2SRC_MASK GENMASK(2, 0)
+#define RCC_LPTIM23CKSELR_LPTIM2SRC_SHIFT 0
+#define RCC_LPTIM23CKSELR_LPTIM3SRC_MASK GENMASK(5, 3)
+#define RCC_LPTIM23CKSELR_LPTIM3SRC_SHIFT 3
+
+/* RCC_LPTIM45CKSELR register fields */
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_MASK GENMASK(2, 0)
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_SHIFT 0
+
+/* RCC_SAI1CKSELR register fields */
+#define RCC_SAI1CKSELR_SAI1SRC_MASK GENMASK(2, 0)
+#define RCC_SAI1CKSELR_SAI1SRC_SHIFT 0
+
+/* RCC_SAI2CKSELR register fields */
+#define RCC_SAI2CKSELR_SAI2SRC_MASK GENMASK(2, 0)
+#define RCC_SAI2CKSELR_SAI2SRC_SHIFT 0
+
+/* RCC_FDCANCKSELR register fields */
+#define RCC_FDCANCKSELR_FDCANSRC_MASK GENMASK(1, 0)
+#define RCC_FDCANCKSELR_FDCANSRC_SHIFT 0
+
+/* RCC_SPDIFCKSELR register fields */
+#define RCC_SPDIFCKSELR_SPDIFSRC_MASK GENMASK(1, 0)
+#define RCC_SPDIFCKSELR_SPDIFSRC_SHIFT 0
+
+/* RCC_ADC12CKSELR register fields */
+#define RCC_ADC12CKSELR_ADC1SRC_MASK GENMASK(1, 0)
+#define RCC_ADC12CKSELR_ADC1SRC_SHIFT 0
+#define RCC_ADC12CKSELR_ADC2SRC_MASK GENMASK(3, 2)
+#define RCC_ADC12CKSELR_ADC2SRC_SHIFT 2
+
+/* RCC_SDMMC12CKSELR register fields */
+#define RCC_SDMMC12CKSELR_SDMMC1SRC_MASK GENMASK(2, 0)
+#define RCC_SDMMC12CKSELR_SDMMC1SRC_SHIFT 0
+#define RCC_SDMMC12CKSELR_SDMMC2SRC_MASK GENMASK(5, 3)
+#define RCC_SDMMC12CKSELR_SDMMC2SRC_SHIFT 3
+
+/* RCC_ETH12CKSELR register fields */
+#define RCC_ETH12CKSELR_ETH1SRC_MASK GENMASK(1, 0)
+#define RCC_ETH12CKSELR_ETH1SRC_SHIFT 0
+#define RCC_ETH12CKSELR_ETH1PTPDIV_MASK GENMASK(7, 4)
+#define RCC_ETH12CKSELR_ETH1PTPDIV_SHIFT 4
+#define RCC_ETH12CKSELR_ETH2SRC_MASK GENMASK(9, 8)
+#define RCC_ETH12CKSELR_ETH2SRC_SHIFT 8
+#define RCC_ETH12CKSELR_ETH2PTPDIV_MASK GENMASK(15, 12)
+#define RCC_ETH12CKSELR_ETH2PTPDIV_SHIFT 12
+
+/* RCC_USBCKSELR register fields */
+#define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0)
+#define RCC_USBCKSELR_USBPHYSRC_SHIFT 0
+#define RCC_USBCKSELR_USBOSRC BIT(4)
+
+/* RCC_QSPICKSELR register fields */
+#define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0)
+#define RCC_QSPICKSELR_QSPISRC_SHIFT 0
+
+/* RCC_FMCCKSELR register fields */
+#define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0)
+#define RCC_FMCCKSELR_FMCSRC_SHIFT 0
+
+/* RCC_RNG1CKSELR register fields */
+#define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0)
+#define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0
+
+/* RCC_STGENCKSELR register fields */
+#define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0)
+#define RCC_STGENCKSELR_STGENSRC_SHIFT 0
+
+/* RCC_DCMIPPCKSELR register fields */
+#define RCC_DCMIPPCKSELR_DCMIPPSRC_MASK GENMASK(1, 0)
+#define RCC_DCMIPPCKSELR_DCMIPPSRC_SHIFT 0
+
+/* RCC_SAESCKSELR register fields */
+#define RCC_SAESCKSELR_SAESSRC_MASK GENMASK(1, 0)
+#define RCC_SAESCKSELR_SAESSRC_SHIFT 0
+
+/* RCC_APB1RSTSETR register fields */
+#define RCC_APB1RSTSETR_TIM2RST BIT(0)
+#define RCC_APB1RSTSETR_TIM3RST BIT(1)
+#define RCC_APB1RSTSETR_TIM4RST BIT(2)
+#define RCC_APB1RSTSETR_TIM5RST BIT(3)
+#define RCC_APB1RSTSETR_TIM6RST BIT(4)
+#define RCC_APB1RSTSETR_TIM7RST BIT(5)
+#define RCC_APB1RSTSETR_LPTIM1RST BIT(9)
+#define RCC_APB1RSTSETR_SPI2RST BIT(11)
+#define RCC_APB1RSTSETR_SPI3RST BIT(12)
+#define RCC_APB1RSTSETR_USART3RST BIT(15)
+#define RCC_APB1RSTSETR_UART4RST BIT(16)
+#define RCC_APB1RSTSETR_UART5RST BIT(17)
+#define RCC_APB1RSTSETR_UART7RST BIT(18)
+#define RCC_APB1RSTSETR_UART8RST BIT(19)
+#define RCC_APB1RSTSETR_I2C1RST BIT(21)
+#define RCC_APB1RSTSETR_I2C2RST BIT(22)
+#define RCC_APB1RSTSETR_SPDIFRST BIT(26)
+
+/* RCC_APB1RSTCLRR register fields */
+#define RCC_APB1RSTCLRR_TIM2RST BIT(0)
+#define RCC_APB1RSTCLRR_TIM3RST BIT(1)
+#define RCC_APB1RSTCLRR_TIM4RST BIT(2)
+#define RCC_APB1RSTCLRR_TIM5RST BIT(3)
+#define RCC_APB1RSTCLRR_TIM6RST BIT(4)
+#define RCC_APB1RSTCLRR_TIM7RST BIT(5)
+#define RCC_APB1RSTCLRR_LPTIM1RST BIT(9)
+#define RCC_APB1RSTCLRR_SPI2RST BIT(11)
+#define RCC_APB1RSTCLRR_SPI3RST BIT(12)
+#define RCC_APB1RSTCLRR_USART3RST BIT(15)
+#define RCC_APB1RSTCLRR_UART4RST BIT(16)
+#define RCC_APB1RSTCLRR_UART5RST BIT(17)
+#define RCC_APB1RSTCLRR_UART7RST BIT(18)
+#define RCC_APB1RSTCLRR_UART8RST BIT(19)
+#define RCC_APB1RSTCLRR_I2C1RST BIT(21)
+#define RCC_APB1RSTCLRR_I2C2RST BIT(22)
+#define RCC_APB1RSTCLRR_SPDIFRST BIT(26)
+
+/* RCC_APB2RSTSETR register fields */
+#define RCC_APB2RSTSETR_TIM1RST BIT(0)
+#define RCC_APB2RSTSETR_TIM8RST BIT(1)
+#define RCC_APB2RSTSETR_SPI1RST BIT(8)
+#define RCC_APB2RSTSETR_USART6RST BIT(13)
+#define RCC_APB2RSTSETR_SAI1RST BIT(16)
+#define RCC_APB2RSTSETR_SAI2RST BIT(17)
+#define RCC_APB2RSTSETR_DFSDMRST BIT(20)
+#define RCC_APB2RSTSETR_FDCANRST BIT(24)
+
+/* RCC_APB2RSTCLRR register fields */
+#define RCC_APB2RSTCLRR_TIM1RST BIT(0)
+#define RCC_APB2RSTCLRR_TIM8RST BIT(1)
+#define RCC_APB2RSTCLRR_SPI1RST BIT(8)
+#define RCC_APB2RSTCLRR_USART6RST BIT(13)
+#define RCC_APB2RSTCLRR_SAI1RST BIT(16)
+#define RCC_APB2RSTCLRR_SAI2RST BIT(17)
+#define RCC_APB2RSTCLRR_DFSDMRST BIT(20)
+#define RCC_APB2RSTCLRR_FDCANRST BIT(24)
+
+/* RCC_APB3RSTSETR register fields */
+#define RCC_APB3RSTSETR_LPTIM2RST BIT(0)
+#define RCC_APB3RSTSETR_LPTIM3RST BIT(1)
+#define RCC_APB3RSTSETR_LPTIM4RST BIT(2)
+#define RCC_APB3RSTSETR_LPTIM5RST BIT(3)
+#define RCC_APB3RSTSETR_SYSCFGRST BIT(11)
+#define RCC_APB3RSTSETR_VREFRST BIT(13)
+#define RCC_APB3RSTSETR_DTSRST BIT(16)
+#define RCC_APB3RSTSETR_PMBCTRLRST BIT(17)
+
+/* RCC_APB3RSTCLRR register fields */
+#define RCC_APB3RSTCLRR_LPTIM2RST BIT(0)
+#define RCC_APB3RSTCLRR_LPTIM3RST BIT(1)
+#define RCC_APB3RSTCLRR_LPTIM4RST BIT(2)
+#define RCC_APB3RSTCLRR_LPTIM5RST BIT(3)
+#define RCC_APB3RSTCLRR_SYSCFGRST BIT(11)
+#define RCC_APB3RSTCLRR_VREFRST BIT(13)
+#define RCC_APB3RSTCLRR_DTSRST BIT(16)
+#define RCC_APB3RSTCLRR_PMBCTRLRST BIT(17)
+
+/* RCC_APB4RSTSETR register fields */
+#define RCC_APB4RSTSETR_LTDCRST BIT(0)
+#define RCC_APB4RSTSETR_DCMIPPRST BIT(1)
+#define RCC_APB4RSTSETR_DDRPERFMRST BIT(8)
+#define RCC_APB4RSTSETR_USBPHYRST BIT(16)
+
+/* RCC_APB4RSTCLRR register fields */
+#define RCC_APB4RSTCLRR_LTDCRST BIT(0)
+#define RCC_APB4RSTCLRR_DCMIPPRST BIT(1)
+#define RCC_APB4RSTCLRR_DDRPERFMRST BIT(8)
+#define RCC_APB4RSTCLRR_USBPHYRST BIT(16)
+
+/* RCC_APB5RSTSETR register fields */
+#define RCC_APB5RSTSETR_STGENRST BIT(20)
+
+/* RCC_APB5RSTCLRR register fields */
+#define RCC_APB5RSTCLRR_STGENRST BIT(20)
+
+/* RCC_APB6RSTSETR register fields */
+#define RCC_APB6RSTSETR_USART1RST BIT(0)
+#define RCC_APB6RSTSETR_USART2RST BIT(1)
+#define RCC_APB6RSTSETR_SPI4RST BIT(2)
+#define RCC_APB6RSTSETR_SPI5RST BIT(3)
+#define RCC_APB6RSTSETR_I2C3RST BIT(4)
+#define RCC_APB6RSTSETR_I2C4RST BIT(5)
+#define RCC_APB6RSTSETR_I2C5RST BIT(6)
+#define RCC_APB6RSTSETR_TIM12RST BIT(7)
+#define RCC_APB6RSTSETR_TIM13RST BIT(8)
+#define RCC_APB6RSTSETR_TIM14RST BIT(9)
+#define RCC_APB6RSTSETR_TIM15RST BIT(10)
+#define RCC_APB6RSTSETR_TIM16RST BIT(11)
+#define RCC_APB6RSTSETR_TIM17RST BIT(12)
+
+/* RCC_APB6RSTCLRR register fields */
+#define RCC_APB6RSTCLRR_USART1RST BIT(0)
+#define RCC_APB6RSTCLRR_USART2RST BIT(1)
+#define RCC_APB6RSTCLRR_SPI4RST BIT(2)
+#define RCC_APB6RSTCLRR_SPI5RST BIT(3)
+#define RCC_APB6RSTCLRR_I2C3RST BIT(4)
+#define RCC_APB6RSTCLRR_I2C4RST BIT(5)
+#define RCC_APB6RSTCLRR_I2C5RST BIT(6)
+#define RCC_APB6RSTCLRR_TIM12RST BIT(7)
+#define RCC_APB6RSTCLRR_TIM13RST BIT(8)
+#define RCC_APB6RSTCLRR_TIM14RST BIT(9)
+#define RCC_APB6RSTCLRR_TIM15RST BIT(10)
+#define RCC_APB6RSTCLRR_TIM16RST BIT(11)
+#define RCC_APB6RSTCLRR_TIM17RST BIT(12)
+
+/* RCC_AHB2RSTSETR register fields */
+#define RCC_AHB2RSTSETR_DMA1RST BIT(0)
+#define RCC_AHB2RSTSETR_DMA2RST BIT(1)
+#define RCC_AHB2RSTSETR_DMAMUX1RST BIT(2)
+#define RCC_AHB2RSTSETR_DMA3RST BIT(3)
+#define RCC_AHB2RSTSETR_DMAMUX2RST BIT(4)
+#define RCC_AHB2RSTSETR_ADC1RST BIT(5)
+#define RCC_AHB2RSTSETR_ADC2RST BIT(6)
+#define RCC_AHB2RSTSETR_USBORST BIT(8)
+
+/* RCC_AHB2RSTCLRR register fields */
+#define RCC_AHB2RSTCLRR_DMA1RST BIT(0)
+#define RCC_AHB2RSTCLRR_DMA2RST BIT(1)
+#define RCC_AHB2RSTCLRR_DMAMUX1RST BIT(2)
+#define RCC_AHB2RSTCLRR_DMA3RST BIT(3)
+#define RCC_AHB2RSTCLRR_DMAMUX2RST BIT(4)
+#define RCC_AHB2RSTCLRR_ADC1RST BIT(5)
+#define RCC_AHB2RSTCLRR_ADC2RST BIT(6)
+#define RCC_AHB2RSTCLRR_USBORST BIT(8)
+
+/* RCC_AHB4RSTSETR register fields */
+#define RCC_AHB4RSTSETR_GPIOARST BIT(0)
+#define RCC_AHB4RSTSETR_GPIOBRST BIT(1)
+#define RCC_AHB4RSTSETR_GPIOCRST BIT(2)
+#define RCC_AHB4RSTSETR_GPIODRST BIT(3)
+#define RCC_AHB4RSTSETR_GPIOERST BIT(4)
+#define RCC_AHB4RSTSETR_GPIOFRST BIT(5)
+#define RCC_AHB4RSTSETR_GPIOGRST BIT(6)
+#define RCC_AHB4RSTSETR_GPIOHRST BIT(7)
+#define RCC_AHB4RSTSETR_GPIOIRST BIT(8)
+#define RCC_AHB4RSTSETR_TSCRST BIT(15)
+
+/* RCC_AHB4RSTCLRR register fields */
+#define RCC_AHB4RSTCLRR_GPIOARST BIT(0)
+#define RCC_AHB4RSTCLRR_GPIOBRST BIT(1)
+#define RCC_AHB4RSTCLRR_GPIOCRST BIT(2)
+#define RCC_AHB4RSTCLRR_GPIODRST BIT(3)
+#define RCC_AHB4RSTCLRR_GPIOERST BIT(4)
+#define RCC_AHB4RSTCLRR_GPIOFRST BIT(5)
+#define RCC_AHB4RSTCLRR_GPIOGRST BIT(6)
+#define RCC_AHB4RSTCLRR_GPIOHRST BIT(7)
+#define RCC_AHB4RSTCLRR_GPIOIRST BIT(8)
+#define RCC_AHB4RSTCLRR_TSCRST BIT(15)
+
+/* RCC_AHB5RSTSETR register fields */
+#define RCC_AHB5RSTSETR_PKARST BIT(2)
+#define RCC_AHB5RSTSETR_SAESRST BIT(3)
+#define RCC_AHB5RSTSETR_CRYP1RST BIT(4)
+#define RCC_AHB5RSTSETR_HASH1RST BIT(5)
+#define RCC_AHB5RSTSETR_RNG1RST BIT(6)
+#define RCC_AHB5RSTSETR_AXIMCRST BIT(16)
+
+/* RCC_AHB5RSTCLRR register fields */
+#define RCC_AHB5RSTCLRR_PKARST BIT(2)
+#define RCC_AHB5RSTCLRR_SAESRST BIT(3)
+#define RCC_AHB5RSTCLRR_CRYP1RST BIT(4)
+#define RCC_AHB5RSTCLRR_HASH1RST BIT(5)
+#define RCC_AHB5RSTCLRR_RNG1RST BIT(6)
+#define RCC_AHB5RSTCLRR_AXIMCRST BIT(16)
+
+/* RCC_AHB6RSTSETR register fields */
+#define RCC_AHB6RSTSETR_MDMARST BIT(0)
+#define RCC_AHB6RSTSETR_MCERST BIT(1)
+#define RCC_AHB6RSTSETR_ETH1MACRST BIT(10)
+#define RCC_AHB6RSTSETR_FMCRST BIT(12)
+#define RCC_AHB6RSTSETR_QSPIRST BIT(14)
+#define RCC_AHB6RSTSETR_SDMMC1RST BIT(16)
+#define RCC_AHB6RSTSETR_SDMMC2RST BIT(17)
+#define RCC_AHB6RSTSETR_CRC1RST BIT(20)
+#define RCC_AHB6RSTSETR_USBHRST BIT(24)
+#define RCC_AHB6RSTSETR_ETH2MACRST BIT(30)
+
+/* RCC_AHB6RSTCLRR register fields */
+#define RCC_AHB6RSTCLRR_MDMARST BIT(0)
+#define RCC_AHB6RSTCLRR_MCERST BIT(1)
+#define RCC_AHB6RSTCLRR_ETH1MACRST BIT(10)
+#define RCC_AHB6RSTCLRR_FMCRST BIT(12)
+#define RCC_AHB6RSTCLRR_QSPIRST BIT(14)
+#define RCC_AHB6RSTCLRR_SDMMC1RST BIT(16)
+#define RCC_AHB6RSTCLRR_SDMMC2RST BIT(17)
+#define RCC_AHB6RSTCLRR_CRC1RST BIT(20)
+#define RCC_AHB6RSTCLRR_USBHRST BIT(24)
+#define RCC_AHB6RSTCLRR_ETH2MACRST BIT(30)
+
+/* RCC_MP_APB1ENSETR register fields */
+#define RCC_MP_APB1ENSETR_TIM2EN BIT(0)
+#define RCC_MP_APB1ENSETR_TIM3EN BIT(1)
+#define RCC_MP_APB1ENSETR_TIM4EN BIT(2)
+#define RCC_MP_APB1ENSETR_TIM5EN BIT(3)
+#define RCC_MP_APB1ENSETR_TIM6EN BIT(4)
+#define RCC_MP_APB1ENSETR_TIM7EN BIT(5)
+#define RCC_MP_APB1ENSETR_LPTIM1EN BIT(9)
+#define RCC_MP_APB1ENSETR_SPI2EN BIT(11)
+#define RCC_MP_APB1ENSETR_SPI3EN BIT(12)
+#define RCC_MP_APB1ENSETR_USART3EN BIT(15)
+#define RCC_MP_APB1ENSETR_UART4EN BIT(16)
+#define RCC_MP_APB1ENSETR_UART5EN BIT(17)
+#define RCC_MP_APB1ENSETR_UART7EN BIT(18)
+#define RCC_MP_APB1ENSETR_UART8EN BIT(19)
+#define RCC_MP_APB1ENSETR_I2C1EN BIT(21)
+#define RCC_MP_APB1ENSETR_I2C2EN BIT(22)
+#define RCC_MP_APB1ENSETR_SPDIFEN BIT(26)
+
+/* RCC_MP_APB1ENCLRR register fields */
+#define RCC_MP_APB1ENCLRR_TIM2EN BIT(0)
+#define RCC_MP_APB1ENCLRR_TIM3EN BIT(1)
+#define RCC_MP_APB1ENCLRR_TIM4EN BIT(2)
+#define RCC_MP_APB1ENCLRR_TIM5EN BIT(3)
+#define RCC_MP_APB1ENCLRR_TIM6EN BIT(4)
+#define RCC_MP_APB1ENCLRR_TIM7EN BIT(5)
+#define RCC_MP_APB1ENCLRR_LPTIM1EN BIT(9)
+#define RCC_MP_APB1ENCLRR_SPI2EN BIT(11)
+#define RCC_MP_APB1ENCLRR_SPI3EN BIT(12)
+#define RCC_MP_APB1ENCLRR_USART3EN BIT(15)
+#define RCC_MP_APB1ENCLRR_UART4EN BIT(16)
+#define RCC_MP_APB1ENCLRR_UART5EN BIT(17)
+#define RCC_MP_APB1ENCLRR_UART7EN BIT(18)
+#define RCC_MP_APB1ENCLRR_UART8EN BIT(19)
+#define RCC_MP_APB1ENCLRR_I2C1EN BIT(21)
+#define RCC_MP_APB1ENCLRR_I2C2EN BIT(22)
+#define RCC_MP_APB1ENCLRR_SPDIFEN BIT(26)
+
+/* RCC_MP_APB2ENSETR register fields */
+#define RCC_MP_APB2ENSETR_TIM1EN BIT(0)
+#define RCC_MP_APB2ENSETR_TIM8EN BIT(1)
+#define RCC_MP_APB2ENSETR_SPI1EN BIT(8)
+#define RCC_MP_APB2ENSETR_USART6EN BIT(13)
+#define RCC_MP_APB2ENSETR_SAI1EN BIT(16)
+#define RCC_MP_APB2ENSETR_SAI2EN BIT(17)
+#define RCC_MP_APB2ENSETR_DFSDMEN BIT(20)
+#define RCC_MP_APB2ENSETR_ADFSDMEN BIT(21)
+#define RCC_MP_APB2ENSETR_FDCANEN BIT(24)
+
+/* RCC_MP_APB2ENCLRR register fields */
+#define RCC_MP_APB2ENCLRR_TIM1EN BIT(0)
+#define RCC_MP_APB2ENCLRR_TIM8EN BIT(1)
+#define RCC_MP_APB2ENCLRR_SPI1EN BIT(8)
+#define RCC_MP_APB2ENCLRR_USART6EN BIT(13)
+#define RCC_MP_APB2ENCLRR_SAI1EN BIT(16)
+#define RCC_MP_APB2ENCLRR_SAI2EN BIT(17)
+#define RCC_MP_APB2ENCLRR_DFSDMEN BIT(20)
+#define RCC_MP_APB2ENCLRR_ADFSDMEN BIT(21)
+#define RCC_MP_APB2ENCLRR_FDCANEN BIT(24)
+
+/* RCC_MP_APB3ENSETR register fields */
+#define RCC_MP_APB3ENSETR_LPTIM2EN BIT(0)
+#define RCC_MP_APB3ENSETR_LPTIM3EN BIT(1)
+#define RCC_MP_APB3ENSETR_LPTIM4EN BIT(2)
+#define RCC_MP_APB3ENSETR_LPTIM5EN BIT(3)
+#define RCC_MP_APB3ENSETR_VREFEN BIT(13)
+#define RCC_MP_APB3ENSETR_DTSEN BIT(16)
+#define RCC_MP_APB3ENSETR_PMBCTRLEN BIT(17)
+#define RCC_MP_APB3ENSETR_HDPEN BIT(20)
+
+/* RCC_MP_APB3ENCLRR register fields */
+#define RCC_MP_APB3ENCLRR_LPTIM2EN BIT(0)
+#define RCC_MP_APB3ENCLRR_LPTIM3EN BIT(1)
+#define RCC_MP_APB3ENCLRR_LPTIM4EN BIT(2)
+#define RCC_MP_APB3ENCLRR_LPTIM5EN BIT(3)
+#define RCC_MP_APB3ENCLRR_VREFEN BIT(13)
+#define RCC_MP_APB3ENCLRR_DTSEN BIT(16)
+#define RCC_MP_APB3ENCLRR_PMBCTRLEN BIT(17)
+#define RCC_MP_APB3ENCLRR_HDPEN BIT(20)
+
+/* RCC_MP_S_APB3ENSETR register fields */
+#define RCC_MP_S_APB3ENSETR_SYSCFGEN BIT(0)
+
+/* RCC_MP_S_APB3ENCLRR register fields */
+#define RCC_MP_S_APB3ENCLRR_SYSCFGEN BIT(0)
+
+/* RCC_MP_NS_APB3ENSETR register fields */
+#define RCC_MP_NS_APB3ENSETR_SYSCFGEN BIT(0)
+
+/* RCC_MP_NS_APB3ENCLRR register fields */
+#define RCC_MP_NS_APB3ENCLRR_SYSCFGEN BIT(0)
+
+/* RCC_MP_APB4ENSETR register fields */
+#define RCC_MP_APB4ENSETR_DCMIPPEN BIT(1)
+#define RCC_MP_APB4ENSETR_DDRPERFMEN BIT(8)
+#define RCC_MP_APB4ENSETR_IWDG2APBEN BIT(15)
+#define RCC_MP_APB4ENSETR_USBPHYEN BIT(16)
+#define RCC_MP_APB4ENSETR_STGENROEN BIT(20)
+
+/* RCC_MP_APB4ENCLRR register fields */
+#define RCC_MP_APB4ENCLRR_DCMIPPEN BIT(1)
+#define RCC_MP_APB4ENCLRR_DDRPERFMEN BIT(8)
+#define RCC_MP_APB4ENCLRR_IWDG2APBEN BIT(15)
+#define RCC_MP_APB4ENCLRR_USBPHYEN BIT(16)
+#define RCC_MP_APB4ENCLRR_STGENROEN BIT(20)
+
+/* RCC_MP_S_APB4ENSETR register fields */
+#define RCC_MP_S_APB4ENSETR_LTDCEN BIT(0)
+
+/* RCC_MP_S_APB4ENCLRR register fields */
+#define RCC_MP_S_APB4ENCLRR_LTDCEN BIT(0)
+
+/* RCC_MP_NS_APB4ENSETR register fields */
+#define RCC_MP_NS_APB4ENSETR_LTDCEN BIT(0)
+
+/* RCC_MP_NS_APB4ENCLRR register fields */
+#define RCC_MP_NS_APB4ENCLRR_LTDCEN BIT(0)
+
+/* RCC_MP_APB5ENSETR register fields */
+#define RCC_MP_APB5ENSETR_RTCAPBEN BIT(8)
+#define RCC_MP_APB5ENSETR_TZCEN BIT(11)
+#define RCC_MP_APB5ENSETR_ETZPCEN BIT(13)
+#define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(15)
+#define RCC_MP_APB5ENSETR_BSECEN BIT(16)
+#define RCC_MP_APB5ENSETR_STGENCEN BIT(20)
+
+/* RCC_MP_APB5ENCLRR register fields */
+#define RCC_MP_APB5ENCLRR_RTCAPBEN BIT(8)
+#define RCC_MP_APB5ENCLRR_TZCEN BIT(11)
+#define RCC_MP_APB5ENCLRR_ETZPCEN BIT(13)
+#define RCC_MP_APB5ENCLRR_IWDG1APBEN BIT(15)
+#define RCC_MP_APB5ENCLRR_BSECEN BIT(16)
+#define RCC_MP_APB5ENCLRR_STGENCEN BIT(20)
+
+/* RCC_MP_APB6ENSETR register fields */
+#define RCC_MP_APB6ENSETR_USART1EN BIT(0)
+#define RCC_MP_APB6ENSETR_USART2EN BIT(1)
+#define RCC_MP_APB6ENSETR_SPI4EN BIT(2)
+#define RCC_MP_APB6ENSETR_SPI5EN BIT(3)
+#define RCC_MP_APB6ENSETR_I2C3EN BIT(4)
+#define RCC_MP_APB6ENSETR_I2C4EN BIT(5)
+#define RCC_MP_APB6ENSETR_I2C5EN BIT(6)
+#define RCC_MP_APB6ENSETR_TIM12EN BIT(7)
+#define RCC_MP_APB6ENSETR_TIM13EN BIT(8)
+#define RCC_MP_APB6ENSETR_TIM14EN BIT(9)
+#define RCC_MP_APB6ENSETR_TIM15EN BIT(10)
+#define RCC_MP_APB6ENSETR_TIM16EN BIT(11)
+#define RCC_MP_APB6ENSETR_TIM17EN BIT(12)
+
+/* RCC_MP_APB6ENCLRR register fields */
+#define RCC_MP_APB6ENCLRR_USART1EN BIT(0)
+#define RCC_MP_APB6ENCLRR_USART2EN BIT(1)
+#define RCC_MP_APB6ENCLRR_SPI4EN BIT(2)
+#define RCC_MP_APB6ENCLRR_SPI5EN BIT(3)
+#define RCC_MP_APB6ENCLRR_I2C3EN BIT(4)
+#define RCC_MP_APB6ENCLRR_I2C4EN BIT(5)
+#define RCC_MP_APB6ENCLRR_I2C5EN BIT(6)
+#define RCC_MP_APB6ENCLRR_TIM12EN BIT(7)
+#define RCC_MP_APB6ENCLRR_TIM13EN BIT(8)
+#define RCC_MP_APB6ENCLRR_TIM14EN BIT(9)
+#define RCC_MP_APB6ENCLRR_TIM15EN BIT(10)
+#define RCC_MP_APB6ENCLRR_TIM16EN BIT(11)
+#define RCC_MP_APB6ENCLRR_TIM17EN BIT(12)
+
+/* RCC_MP_AHB2ENSETR register fields */
+#define RCC_MP_AHB2ENSETR_DMA1EN BIT(0)
+#define RCC_MP_AHB2ENSETR_DMA2EN BIT(1)
+#define RCC_MP_AHB2ENSETR_DMAMUX1EN BIT(2)
+#define RCC_MP_AHB2ENSETR_DMA3EN BIT(3)
+#define RCC_MP_AHB2ENSETR_DMAMUX2EN BIT(4)
+#define RCC_MP_AHB2ENSETR_ADC1EN BIT(5)
+#define RCC_MP_AHB2ENSETR_ADC2EN BIT(6)
+#define RCC_MP_AHB2ENSETR_USBOEN BIT(8)
+
+/* RCC_MP_AHB2ENCLRR register fields */
+#define RCC_MP_AHB2ENCLRR_DMA1EN BIT(0)
+#define RCC_MP_AHB2ENCLRR_DMA2EN BIT(1)
+#define RCC_MP_AHB2ENCLRR_DMAMUX1EN BIT(2)
+#define RCC_MP_AHB2ENCLRR_DMA3EN BIT(3)
+#define RCC_MP_AHB2ENCLRR_DMAMUX2EN BIT(4)
+#define RCC_MP_AHB2ENCLRR_ADC1EN BIT(5)
+#define RCC_MP_AHB2ENCLRR_ADC2EN BIT(6)
+#define RCC_MP_AHB2ENCLRR_USBOEN BIT(8)
+
+/* RCC_MP_AHB4ENSETR register fields */
+#define RCC_MP_AHB4ENSETR_TSCEN BIT(15)
+
+/* RCC_MP_AHB4ENCLRR register fields */
+#define RCC_MP_AHB4ENCLRR_TSCEN BIT(15)
+
+/* RCC_MP_S_AHB4ENSETR register fields */
+#define RCC_MP_S_AHB4ENSETR_GPIOAEN BIT(0)
+#define RCC_MP_S_AHB4ENSETR_GPIOBEN BIT(1)
+#define RCC_MP_S_AHB4ENSETR_GPIOCEN BIT(2)
+#define RCC_MP_S_AHB4ENSETR_GPIODEN BIT(3)
+#define RCC_MP_S_AHB4ENSETR_GPIOEEN BIT(4)
+#define RCC_MP_S_AHB4ENSETR_GPIOFEN BIT(5)
+#define RCC_MP_S_AHB4ENSETR_GPIOGEN BIT(6)
+#define RCC_MP_S_AHB4ENSETR_GPIOHEN BIT(7)
+#define RCC_MP_S_AHB4ENSETR_GPIOIEN BIT(8)
+
+/* RCC_MP_S_AHB4ENCLRR register fields */
+#define RCC_MP_S_AHB4ENCLRR_GPIOAEN BIT(0)
+#define RCC_MP_S_AHB4ENCLRR_GPIOBEN BIT(1)
+#define RCC_MP_S_AHB4ENCLRR_GPIOCEN BIT(2)
+#define RCC_MP_S_AHB4ENCLRR_GPIODEN BIT(3)
+#define RCC_MP_S_AHB4ENCLRR_GPIOEEN BIT(4)
+#define RCC_MP_S_AHB4ENCLRR_GPIOFEN BIT(5)
+#define RCC_MP_S_AHB4ENCLRR_GPIOGEN BIT(6)
+#define RCC_MP_S_AHB4ENCLRR_GPIOHEN BIT(7)
+#define RCC_MP_S_AHB4ENCLRR_GPIOIEN BIT(8)
+
+/* RCC_MP_NS_AHB4ENSETR register fields */
+#define RCC_MP_NS_AHB4ENSETR_GPIOAEN BIT(0)
+#define RCC_MP_NS_AHB4ENSETR_GPIOBEN BIT(1)
+#define RCC_MP_NS_AHB4ENSETR_GPIOCEN BIT(2)
+#define RCC_MP_NS_AHB4ENSETR_GPIODEN BIT(3)
+#define RCC_MP_NS_AHB4ENSETR_GPIOEEN BIT(4)
+#define RCC_MP_NS_AHB4ENSETR_GPIOFEN BIT(5)
+#define RCC_MP_NS_AHB4ENSETR_GPIOGEN BIT(6)
+#define RCC_MP_NS_AHB4ENSETR_GPIOHEN BIT(7)
+#define RCC_MP_NS_AHB4ENSETR_GPIOIEN BIT(8)
+
+/* RCC_MP_NS_AHB4ENCLRR register fields */
+#define RCC_MP_NS_AHB4ENCLRR_GPIOAEN BIT(0)
+#define RCC_MP_NS_AHB4ENCLRR_GPIOBEN BIT(1)
+#define RCC_MP_NS_AHB4ENCLRR_GPIOCEN BIT(2)
+#define RCC_MP_NS_AHB4ENCLRR_GPIODEN BIT(3)
+#define RCC_MP_NS_AHB4ENCLRR_GPIOEEN BIT(4)
+#define RCC_MP_NS_AHB4ENCLRR_GPIOFEN BIT(5)
+#define RCC_MP_NS_AHB4ENCLRR_GPIOGEN BIT(6)
+#define RCC_MP_NS_AHB4ENCLRR_GPIOHEN BIT(7)
+#define RCC_MP_NS_AHB4ENCLRR_GPIOIEN BIT(8)
+
+/* RCC_MP_AHB5ENSETR register fields */
+#define RCC_MP_AHB5ENSETR_PKAEN BIT(2)
+#define RCC_MP_AHB5ENSETR_SAESEN BIT(3)
+#define RCC_MP_AHB5ENSETR_CRYP1EN BIT(4)
+#define RCC_MP_AHB5ENSETR_HASH1EN BIT(5)
+#define RCC_MP_AHB5ENSETR_RNG1EN BIT(6)
+#define RCC_MP_AHB5ENSETR_BKPSRAMEN BIT(8)
+#define RCC_MP_AHB5ENSETR_AXIMCEN BIT(16)
+
+/* RCC_MP_AHB5ENCLRR register fields */
+#define RCC_MP_AHB5ENCLRR_PKAEN BIT(2)
+#define RCC_MP_AHB5ENCLRR_SAESEN BIT(3)
+#define RCC_MP_AHB5ENCLRR_CRYP1EN BIT(4)
+#define RCC_MP_AHB5ENCLRR_HASH1EN BIT(5)
+#define RCC_MP_AHB5ENCLRR_RNG1EN BIT(6)
+#define RCC_MP_AHB5ENCLRR_BKPSRAMEN BIT(8)
+#define RCC_MP_AHB5ENCLRR_AXIMCEN BIT(16)
+
+/* RCC_MP_AHB6ENSETR register fields */
+#define RCC_MP_AHB6ENSETR_MCEEN BIT(1)
+#define RCC_MP_AHB6ENSETR_ETH1CKEN BIT(7)
+#define RCC_MP_AHB6ENSETR_ETH1TXEN BIT(8)
+#define RCC_MP_AHB6ENSETR_ETH1RXEN BIT(9)
+#define RCC_MP_AHB6ENSETR_ETH1MACEN BIT(10)
+#define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
+#define RCC_MP_AHB6ENSETR_QSPIEN BIT(14)
+#define RCC_MP_AHB6ENSETR_SDMMC1EN BIT(16)
+#define RCC_MP_AHB6ENSETR_SDMMC2EN BIT(17)
+#define RCC_MP_AHB6ENSETR_CRC1EN BIT(20)
+#define RCC_MP_AHB6ENSETR_USBHEN BIT(24)
+#define RCC_MP_AHB6ENSETR_ETH2CKEN BIT(27)
+#define RCC_MP_AHB6ENSETR_ETH2TXEN BIT(28)
+#define RCC_MP_AHB6ENSETR_ETH2RXEN BIT(29)
+#define RCC_MP_AHB6ENSETR_ETH2MACEN BIT(30)
+
+/* RCC_MP_AHB6ENCLRR register fields */
+#define RCC_MP_AHB6ENCLRR_MCEEN BIT(1)
+#define RCC_MP_AHB6ENCLRR_ETH1CKEN BIT(7)
+#define RCC_MP_AHB6ENCLRR_ETH1TXEN BIT(8)
+#define RCC_MP_AHB6ENCLRR_ETH1RXEN BIT(9)
+#define RCC_MP_AHB6ENCLRR_ETH1MACEN BIT(10)
+#define RCC_MP_AHB6ENCLRR_FMCEN BIT(12)
+#define RCC_MP_AHB6ENCLRR_QSPIEN BIT(14)
+#define RCC_MP_AHB6ENCLRR_SDMMC1EN BIT(16)
+#define RCC_MP_AHB6ENCLRR_SDMMC2EN BIT(17)
+#define RCC_MP_AHB6ENCLRR_CRC1EN BIT(20)
+#define RCC_MP_AHB6ENCLRR_USBHEN BIT(24)
+#define RCC_MP_AHB6ENCLRR_ETH2CKEN BIT(27)
+#define RCC_MP_AHB6ENCLRR_ETH2TXEN BIT(28)
+#define RCC_MP_AHB6ENCLRR_ETH2RXEN BIT(29)
+#define RCC_MP_AHB6ENCLRR_ETH2MACEN BIT(30)
+
+/* RCC_MP_S_AHB6ENSETR register fields */
+#define RCC_MP_S_AHB6ENSETR_MDMAEN BIT(0)
+
+/* RCC_MP_S_AHB6ENCLRR register fields */
+#define RCC_MP_S_AHB6ENCLRR_MDMAEN BIT(0)
+
+/* RCC_MP_NS_AHB6ENSETR register fields */
+#define RCC_MP_NS_AHB6ENSETR_MDMAEN BIT(0)
+
+/* RCC_MP_NS_AHB6ENCLRR register fields */
+#define RCC_MP_NS_AHB6ENCLRR_MDMAEN BIT(0)
+
+/* RCC_MP_APB1LPENSETR register fields */
+#define RCC_MP_APB1LPENSETR_TIM2LPEN BIT(0)
+#define RCC_MP_APB1LPENSETR_TIM3LPEN BIT(1)
+#define RCC_MP_APB1LPENSETR_TIM4LPEN BIT(2)
+#define RCC_MP_APB1LPENSETR_TIM5LPEN BIT(3)
+#define RCC_MP_APB1LPENSETR_TIM6LPEN BIT(4)
+#define RCC_MP_APB1LPENSETR_TIM7LPEN BIT(5)
+#define RCC_MP_APB1LPENSETR_LPTIM1LPEN BIT(9)
+#define RCC_MP_APB1LPENSETR_SPI2LPEN BIT(11)
+#define RCC_MP_APB1LPENSETR_SPI3LPEN BIT(12)
+#define RCC_MP_APB1LPENSETR_USART3LPEN BIT(15)
+#define RCC_MP_APB1LPENSETR_UART4LPEN BIT(16)
+#define RCC_MP_APB1LPENSETR_UART5LPEN BIT(17)
+#define RCC_MP_APB1LPENSETR_UART7LPEN BIT(18)
+#define RCC_MP_APB1LPENSETR_UART8LPEN BIT(19)
+#define RCC_MP_APB1LPENSETR_I2C1LPEN BIT(21)
+#define RCC_MP_APB1LPENSETR_I2C2LPEN BIT(22)
+#define RCC_MP_APB1LPENSETR_SPDIFLPEN BIT(26)
+
+/* RCC_MP_APB1LPENCLRR register fields */
+#define RCC_MP_APB1LPENCLRR_TIM2LPEN BIT(0)
+#define RCC_MP_APB1LPENCLRR_TIM3LPEN BIT(1)
+#define RCC_MP_APB1LPENCLRR_TIM4LPEN BIT(2)
+#define RCC_MP_APB1LPENCLRR_TIM5LPEN BIT(3)
+#define RCC_MP_APB1LPENCLRR_TIM6LPEN BIT(4)
+#define RCC_MP_APB1LPENCLRR_TIM7LPEN BIT(5)
+#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN BIT(9)
+#define RCC_MP_APB1LPENCLRR_SPI2LPEN BIT(11)
+#define RCC_MP_APB1LPENCLRR_SPI3LPEN BIT(12)
+#define RCC_MP_APB1LPENCLRR_USART3LPEN BIT(15)
+#define RCC_MP_APB1LPENCLRR_UART4LPEN BIT(16)
+#define RCC_MP_APB1LPENCLRR_UART5LPEN BIT(17)
+#define RCC_MP_APB1LPENCLRR_UART7LPEN BIT(18)
+#define RCC_MP_APB1LPENCLRR_UART8LPEN BIT(19)
+#define RCC_MP_APB1LPENCLRR_I2C1LPEN BIT(21)
+#define RCC_MP_APB1LPENCLRR_I2C2LPEN BIT(22)
+#define RCC_MP_APB1LPENCLRR_SPDIFLPEN BIT(26)
+
+/* RCC_MP_APB2LPENSETR register fields */
+#define RCC_MP_APB2LPENSETR_TIM1LPEN BIT(0)
+#define RCC_MP_APB2LPENSETR_TIM8LPEN BIT(1)
+#define RCC_MP_APB2LPENSETR_SPI1LPEN BIT(8)
+#define RCC_MP_APB2LPENSETR_USART6LPEN BIT(13)
+#define RCC_MP_APB2LPENSETR_SAI1LPEN BIT(16)
+#define RCC_MP_APB2LPENSETR_SAI2LPEN BIT(17)
+#define RCC_MP_APB2LPENSETR_DFSDMLPEN BIT(20)
+#define RCC_MP_APB2LPENSETR_ADFSDMLPEN BIT(21)
+#define RCC_MP_APB2LPENSETR_FDCANLPEN BIT(24)
+
+/* RCC_MP_APB2LPENCLRR register fields */
+#define RCC_MP_APB2LPENCLRR_TIM1LPEN BIT(0)
+#define RCC_MP_APB2LPENCLRR_TIM8LPEN BIT(1)
+#define RCC_MP_APB2LPENCLRR_SPI1LPEN BIT(8)
+#define RCC_MP_APB2LPENCLRR_USART6LPEN BIT(13)
+#define RCC_MP_APB2LPENCLRR_SAI1LPEN BIT(16)
+#define RCC_MP_APB2LPENCLRR_SAI2LPEN BIT(17)
+#define RCC_MP_APB2LPENCLRR_DFSDMLPEN BIT(20)
+#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN BIT(21)
+#define RCC_MP_APB2LPENCLRR_FDCANLPEN BIT(24)
+
+/* RCC_MP_APB3LPENSETR register fields */
+#define RCC_MP_APB3LPENSETR_LPTIM2LPEN BIT(0)
+#define RCC_MP_APB3LPENSETR_LPTIM3LPEN BIT(1)
+#define RCC_MP_APB3LPENSETR_LPTIM4LPEN BIT(2)
+#define RCC_MP_APB3LPENSETR_LPTIM5LPEN BIT(3)
+#define RCC_MP_APB3LPENSETR_VREFLPEN BIT(13)
+#define RCC_MP_APB3LPENSETR_DTSLPEN BIT(16)
+#define RCC_MP_APB3LPENSETR_PMBCTRLLPEN BIT(17)
+
+/* RCC_MP_APB3LPENCLRR register fields */
+#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN BIT(0)
+#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN BIT(1)
+#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN BIT(2)
+#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN BIT(3)
+#define RCC_MP_APB3LPENCLRR_VREFLPEN BIT(13)
+#define RCC_MP_APB3LPENCLRR_DTSLPEN BIT(16)
+#define RCC_MP_APB3LPENCLRR_PMBCTRLLPEN BIT(17)
+
+/* RCC_MP_S_APB3LPENSETR register fields */
+#define RCC_MP_S_APB3LPENSETR_SYSCFGLPEN BIT(0)
+
+/* RCC_MP_S_APB3LPENCLRR register fields */
+#define RCC_MP_S_APB3LPENCLRR_SYSCFGLPEN BIT(0)
+
+/* RCC_MP_NS_APB3LPENSETR register fields */
+#define RCC_MP_NS_APB3LPENSETR_SYSCFGLPEN BIT(0)
+
+/* RCC_MP_NS_APB3LPENCLRR register fields */
+#define RCC_MP_NS_APB3LPENCLRR_SYSCFGLPEN BIT(0)
+
+/* RCC_MP_APB4LPENSETR register fields */
+#define RCC_MP_APB4LPENSETR_DCMIPPLPEN BIT(1)
+#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN BIT(8)
+#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN BIT(15)
+#define RCC_MP_APB4LPENSETR_USBPHYLPEN BIT(16)
+#define RCC_MP_APB4LPENSETR_STGENROLPEN BIT(20)
+#define RCC_MP_APB4LPENSETR_STGENROSTPEN BIT(21)
+
+/* RCC_MP_APB4LPENCLRR register fields */
+#define RCC_MP_APB4LPENCLRR_DCMIPPLPEN BIT(1)
+#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN BIT(8)
+#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN BIT(15)
+#define RCC_MP_APB4LPENCLRR_USBPHYLPEN BIT(16)
+#define RCC_MP_APB4LPENCLRR_STGENROLPEN BIT(20)
+#define RCC_MP_APB4LPENCLRR_STGENROSTPEN BIT(21)
+
+/* RCC_MP_S_APB4LPENSETR register fields */
+#define RCC_MP_S_APB4LPENSETR_LTDCLPEN BIT(0)
+
+/* RCC_MP_S_APB4LPENCLRR register fields */
+#define RCC_MP_S_APB4LPENCLRR_LTDCLPEN BIT(0)
+
+/* RCC_MP_NS_APB4LPENSETR register fields */
+#define RCC_MP_NS_APB4LPENSETR_LTDCLPEN BIT(0)
+
+/* RCC_MP_NS_APB4LPENCLRR register fields */
+#define RCC_MP_NS_APB4LPENCLRR_LTDCLPEN BIT(0)
+
+/* RCC_MP_APB5LPENSETR register fields */
+#define RCC_MP_APB5LPENSETR_RTCAPBLPEN BIT(8)
+#define RCC_MP_APB5LPENSETR_TZCLPEN BIT(11)
+#define RCC_MP_APB5LPENSETR_ETZPCLPEN BIT(13)
+#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN BIT(15)
+#define RCC_MP_APB5LPENSETR_BSECLPEN BIT(16)
+#define RCC_MP_APB5LPENSETR_STGENCLPEN BIT(20)
+#define RCC_MP_APB5LPENSETR_STGENCSTPEN BIT(21)
+
+/* RCC_MP_APB5LPENCLRR register fields */
+#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN BIT(8)
+#define RCC_MP_APB5LPENCLRR_TZCLPEN BIT(11)
+#define RCC_MP_APB5LPENCLRR_ETZPCLPEN BIT(13)
+#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN BIT(15)
+#define RCC_MP_APB5LPENCLRR_BSECLPEN BIT(16)
+#define RCC_MP_APB5LPENCLRR_STGENCLPEN BIT(20)
+#define RCC_MP_APB5LPENCLRR_STGENCSTPEN BIT(21)
+
+/* RCC_MP_APB6LPENSETR register fields */
+#define RCC_MP_APB6LPENSETR_USART1LPEN BIT(0)
+#define RCC_MP_APB6LPENSETR_USART2LPEN BIT(1)
+#define RCC_MP_APB6LPENSETR_SPI4LPEN BIT(2)
+#define RCC_MP_APB6LPENSETR_SPI5LPEN BIT(3)
+#define RCC_MP_APB6LPENSETR_I2C3LPEN BIT(4)
+#define RCC_MP_APB6LPENSETR_I2C4LPEN BIT(5)
+#define RCC_MP_APB6LPENSETR_I2C5LPEN BIT(6)
+#define RCC_MP_APB6LPENSETR_TIM12LPEN BIT(7)
+#define RCC_MP_APB6LPENSETR_TIM13LPEN BIT(8)
+#define RCC_MP_APB6LPENSETR_TIM14LPEN BIT(9)
+#define RCC_MP_APB6LPENSETR_TIM15LPEN BIT(10)
+#define RCC_MP_APB6LPENSETR_TIM16LPEN BIT(11)
+#define RCC_MP_APB6LPENSETR_TIM17LPEN BIT(12)
+
+/* RCC_MP_APB6LPENCLRR register fields */
+#define RCC_MP_APB6LPENCLRR_USART1LPEN BIT(0)
+#define RCC_MP_APB6LPENCLRR_USART2LPEN BIT(1)
+#define RCC_MP_APB6LPENCLRR_SPI4LPEN BIT(2)
+#define RCC_MP_APB6LPENCLRR_SPI5LPEN BIT(3)
+#define RCC_MP_APB6LPENCLRR_I2C3LPEN BIT(4)
+#define RCC_MP_APB6LPENCLRR_I2C4LPEN BIT(5)
+#define RCC_MP_APB6LPENCLRR_I2C5LPEN BIT(6)
+#define RCC_MP_APB6LPENCLRR_TIM12LPEN BIT(7)
+#define RCC_MP_APB6LPENCLRR_TIM13LPEN BIT(8)
+#define RCC_MP_APB6LPENCLRR_TIM14LPEN BIT(9)
+#define RCC_MP_APB6LPENCLRR_TIM15LPEN BIT(10)
+#define RCC_MP_APB6LPENCLRR_TIM16LPEN BIT(11)
+#define RCC_MP_APB6LPENCLRR_TIM17LPEN BIT(12)
+
+/* RCC_MP_AHB2LPENSETR register fields */
+#define RCC_MP_AHB2LPENSETR_DMA1LPEN BIT(0)
+#define RCC_MP_AHB2LPENSETR_DMA2LPEN BIT(1)
+#define RCC_MP_AHB2LPENSETR_DMAMUX1LPEN BIT(2)
+#define RCC_MP_AHB2LPENSETR_DMA3LPEN BIT(3)
+#define RCC_MP_AHB2LPENSETR_DMAMUX2LPEN BIT(4)
+#define RCC_MP_AHB2LPENSETR_ADC1LPEN BIT(5)
+#define RCC_MP_AHB2LPENSETR_ADC2LPEN BIT(6)
+#define RCC_MP_AHB2LPENSETR_USBOLPEN BIT(8)
+
+/* RCC_MP_AHB2LPENCLRR register fields */
+#define RCC_MP_AHB2LPENCLRR_DMA1LPEN BIT(0)
+#define RCC_MP_AHB2LPENCLRR_DMA2LPEN BIT(1)
+#define RCC_MP_AHB2LPENCLRR_DMAMUX1LPEN BIT(2)
+#define RCC_MP_AHB2LPENCLRR_DMA3LPEN BIT(3)
+#define RCC_MP_AHB2LPENCLRR_DMAMUX2LPEN BIT(4)
+#define RCC_MP_AHB2LPENCLRR_ADC1LPEN BIT(5)
+#define RCC_MP_AHB2LPENCLRR_ADC2LPEN BIT(6)
+#define RCC_MP_AHB2LPENCLRR_USBOLPEN BIT(8)
+
+/* RCC_MP_AHB4LPENSETR register fields */
+#define RCC_MP_AHB4LPENSETR_TSCLPEN BIT(15)
+
+/* RCC_MP_AHB4LPENCLRR register fields */
+#define RCC_MP_AHB4LPENCLRR_TSCLPEN BIT(15)
+
+/* RCC_MP_S_AHB4LPENSETR register fields */
+#define RCC_MP_S_AHB4LPENSETR_GPIOALPEN BIT(0)
+#define RCC_MP_S_AHB4LPENSETR_GPIOBLPEN BIT(1)
+#define RCC_MP_S_AHB4LPENSETR_GPIOCLPEN BIT(2)
+#define RCC_MP_S_AHB4LPENSETR_GPIODLPEN BIT(3)
+#define RCC_MP_S_AHB4LPENSETR_GPIOELPEN BIT(4)
+#define RCC_MP_S_AHB4LPENSETR_GPIOFLPEN BIT(5)
+#define RCC_MP_S_AHB4LPENSETR_GPIOGLPEN BIT(6)
+#define RCC_MP_S_AHB4LPENSETR_GPIOHLPEN BIT(7)
+#define RCC_MP_S_AHB4LPENSETR_GPIOILPEN BIT(8)
+
+/* RCC_MP_S_AHB4LPENCLRR register fields */
+#define RCC_MP_S_AHB4LPENCLRR_GPIOALPEN BIT(0)
+#define RCC_MP_S_AHB4LPENCLRR_GPIOBLPEN BIT(1)
+#define RCC_MP_S_AHB4LPENCLRR_GPIOCLPEN BIT(2)
+#define RCC_MP_S_AHB4LPENCLRR_GPIODLPEN BIT(3)
+#define RCC_MP_S_AHB4LPENCLRR_GPIOELPEN BIT(4)
+#define RCC_MP_S_AHB4LPENCLRR_GPIOFLPEN BIT(5)
+#define RCC_MP_S_AHB4LPENCLRR_GPIOGLPEN BIT(6)
+#define RCC_MP_S_AHB4LPENCLRR_GPIOHLPEN BIT(7)
+#define RCC_MP_S_AHB4LPENCLRR_GPIOILPEN BIT(8)
+
+/* RCC_MP_NS_AHB4LPENSETR register fields */
+#define RCC_MP_NS_AHB4LPENSETR_GPIOALPEN BIT(0)
+#define RCC_MP_NS_AHB4LPENSETR_GPIOBLPEN BIT(1)
+#define RCC_MP_NS_AHB4LPENSETR_GPIOCLPEN BIT(2)
+#define RCC_MP_NS_AHB4LPENSETR_GPIODLPEN BIT(3)
+#define RCC_MP_NS_AHB4LPENSETR_GPIOELPEN BIT(4)
+#define RCC_MP_NS_AHB4LPENSETR_GPIOFLPEN BIT(5)
+#define RCC_MP_NS_AHB4LPENSETR_GPIOGLPEN BIT(6)
+#define RCC_MP_NS_AHB4LPENSETR_GPIOHLPEN BIT(7)
+#define RCC_MP_NS_AHB4LPENSETR_GPIOILPEN BIT(8)
+
+/* RCC_MP_NS_AHB4LPENCLRR register fields */
+#define RCC_MP_NS_AHB4LPENCLRR_GPIOALPEN BIT(0)
+#define RCC_MP_NS_AHB4LPENCLRR_GPIOBLPEN BIT(1)
+#define RCC_MP_NS_AHB4LPENCLRR_GPIOCLPEN BIT(2)
+#define RCC_MP_NS_AHB4LPENCLRR_GPIODLPEN BIT(3)
+#define RCC_MP_NS_AHB4LPENCLRR_GPIOELPEN BIT(4)
+#define RCC_MP_NS_AHB4LPENCLRR_GPIOFLPEN BIT(5)
+#define RCC_MP_NS_AHB4LPENCLRR_GPIOGLPEN BIT(6)
+#define RCC_MP_NS_AHB4LPENCLRR_GPIOHLPEN BIT(7)
+#define RCC_MP_NS_AHB4LPENCLRR_GPIOILPEN BIT(8)
+
+/* RCC_MP_AHB5LPENSETR register fields */
+#define RCC_MP_AHB5LPENSETR_PKALPEN BIT(2)
+#define RCC_MP_AHB5LPENSETR_SAESLPEN BIT(3)
+#define RCC_MP_AHB5LPENSETR_CRYP1LPEN BIT(4)
+#define RCC_MP_AHB5LPENSETR_HASH1LPEN BIT(5)
+#define RCC_MP_AHB5LPENSETR_RNG1LPEN BIT(6)
+#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN BIT(8)
+
+/* RCC_MP_AHB5LPENCLRR register fields */
+#define RCC_MP_AHB5LPENCLRR_PKALPEN BIT(2)
+#define RCC_MP_AHB5LPENCLRR_SAESLPEN BIT(3)
+#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN BIT(4)
+#define RCC_MP_AHB5LPENCLRR_HASH1LPEN BIT(5)
+#define RCC_MP_AHB5LPENCLRR_RNG1LPEN BIT(6)
+#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN BIT(8)
+
+/* RCC_MP_AHB6LPENSETR register fields */
+#define RCC_MP_AHB6LPENSETR_MCELPEN BIT(1)
+#define RCC_MP_AHB6LPENSETR_ETH1CKLPEN BIT(7)
+#define RCC_MP_AHB6LPENSETR_ETH1TXLPEN BIT(8)
+#define RCC_MP_AHB6LPENSETR_ETH1RXLPEN BIT(9)
+#define RCC_MP_AHB6LPENSETR_ETH1MACLPEN BIT(10)
+#define RCC_MP_AHB6LPENSETR_ETH1STPEN BIT(11)
+#define RCC_MP_AHB6LPENSETR_FMCLPEN BIT(12)
+#define RCC_MP_AHB6LPENSETR_QSPILPEN BIT(14)
+#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN BIT(16)
+#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN BIT(17)
+#define RCC_MP_AHB6LPENSETR_CRC1LPEN BIT(20)
+#define RCC_MP_AHB6LPENSETR_USBHLPEN BIT(24)
+#define RCC_MP_AHB6LPENSETR_ETH2CKLPEN BIT(27)
+#define RCC_MP_AHB6LPENSETR_ETH2TXLPEN BIT(28)
+#define RCC_MP_AHB6LPENSETR_ETH2RXLPEN BIT(29)
+#define RCC_MP_AHB6LPENSETR_ETH2MACLPEN BIT(30)
+#define RCC_MP_AHB6LPENSETR_ETH2STPEN BIT(31)
+
+/* RCC_MP_AHB6LPENCLRR register fields */
+#define RCC_MP_AHB6LPENCLRR_MCELPEN BIT(1)
+#define RCC_MP_AHB6LPENCLRR_ETH1CKLPEN BIT(7)
+#define RCC_MP_AHB6LPENCLRR_ETH1TXLPEN BIT(8)
+#define RCC_MP_AHB6LPENCLRR_ETH1RXLPEN BIT(9)
+#define RCC_MP_AHB6LPENCLRR_ETH1MACLPEN BIT(10)
+#define RCC_MP_AHB6LPENCLRR_ETH1STPEN BIT(11)
+#define RCC_MP_AHB6LPENCLRR_FMCLPEN BIT(12)
+#define RCC_MP_AHB6LPENCLRR_QSPILPEN BIT(14)
+#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN BIT(16)
+#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN BIT(17)
+#define RCC_MP_AHB6LPENCLRR_CRC1LPEN BIT(20)
+#define RCC_MP_AHB6LPENCLRR_USBHLPEN BIT(24)
+#define RCC_MP_AHB6LPENCLRR_ETH2CKLPEN BIT(27)
+#define RCC_MP_AHB6LPENCLRR_ETH2TXLPEN BIT(28)
+#define RCC_MP_AHB6LPENCLRR_ETH2RXLPEN BIT(29)
+#define RCC_MP_AHB6LPENCLRR_ETH2MACLPEN BIT(30)
+#define RCC_MP_AHB6LPENCLRR_ETH2STPEN BIT(31)
+
+/* RCC_MP_S_AHB6LPENSETR register fields */
+#define RCC_MP_S_AHB6LPENSETR_MDMALPEN BIT(0)
+
+/* RCC_MP_S_AHB6LPENCLRR register fields */
+#define RCC_MP_S_AHB6LPENCLRR_MDMALPEN BIT(0)
+
+/* RCC_MP_NS_AHB6LPENSETR register fields */
+#define RCC_MP_NS_AHB6LPENSETR_MDMALPEN BIT(0)
+
+/* RCC_MP_NS_AHB6LPENCLRR register fields */
+#define RCC_MP_NS_AHB6LPENCLRR_MDMALPEN BIT(0)
+
+/* RCC_MP_S_AXIMLPENSETR register fields */
+#define RCC_MP_S_AXIMLPENSETR_SYSRAMLPEN BIT(0)
+
+/* RCC_MP_S_AXIMLPENCLRR register fields */
+#define RCC_MP_S_AXIMLPENCLRR_SYSRAMLPEN BIT(0)
+
+/* RCC_MP_NS_AXIMLPENSETR register fields */
+#define RCC_MP_NS_AXIMLPENSETR_SYSRAMLPEN BIT(0)
+
+/* RCC_MP_NS_AXIMLPENCLRR register fields */
+#define RCC_MP_NS_AXIMLPENCLRR_SYSRAMLPEN BIT(0)
+
+/* RCC_MP_MLAHBLPENSETR register fields */
+#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN BIT(0)
+#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN BIT(1)
+#define RCC_MP_MLAHBLPENSETR_SRAM3LPEN BIT(2)
+
+/* RCC_MP_MLAHBLPENCLRR register fields */
+#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN BIT(0)
+#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN BIT(1)
+#define RCC_MP_MLAHBLPENCLRR_SRAM3LPEN BIT(2)
+
+/* RCC_APB3SECSR register fields */
+#define RCC_APB3SECSR_LPTIM2SECF BIT(0)
+#define RCC_APB3SECSR_LPTIM3SECF BIT(1)
+#define RCC_APB3SECSR_VREFSECF BIT(13)
+
+/* RCC_APB4SECSR register fields */
+#define RCC_APB4SECSR_DCMIPPSECF BIT(1)
+#define RCC_APB4SECSR_USBPHYSECF BIT(16)
+
+/* RCC_APB5SECSR register fields */
+#define RCC_APB5SECSR_RTCSECF BIT(8)
+#define RCC_APB5SECSR_TZCSECF BIT(11)
+#define RCC_APB5SECSR_ETZPCSECF BIT(13)
+#define RCC_APB5SECSR_IWDG1SECF BIT(15)
+#define RCC_APB5SECSR_BSECSECF BIT(16)
+#define RCC_APB5SECSR_STGENCSECF_MASK GENMASK(21, 20)
+#define RCC_APB5SECSR_STGENCSECF_SHIFT 20
+
+/* RCC_APB6SECSR register fields */
+#define RCC_APB6SECSR_USART1SECF BIT(0)
+#define RCC_APB6SECSR_USART2SECF BIT(1)
+#define RCC_APB6SECSR_SPI4SECF BIT(2)
+#define RCC_APB6SECSR_SPI5SECF BIT(3)
+#define RCC_APB6SECSR_I2C3SECF BIT(4)
+#define RCC_APB6SECSR_I2C4SECF BIT(5)
+#define RCC_APB6SECSR_I2C5SECF BIT(6)
+#define RCC_APB6SECSR_TIM12SECF BIT(7)
+#define RCC_APB6SECSR_TIM13SECF BIT(8)
+#define RCC_APB6SECSR_TIM14SECF BIT(9)
+#define RCC_APB6SECSR_TIM15SECF BIT(10)
+#define RCC_APB6SECSR_TIM16SECF BIT(11)
+#define RCC_APB6SECSR_TIM17SECF BIT(12)
+
+/* RCC_AHB2SECSR register fields */
+#define RCC_AHB2SECSR_DMA3SECF BIT(3)
+#define RCC_AHB2SECSR_DMAMUX2SECF BIT(4)
+#define RCC_AHB2SECSR_ADC1SECF BIT(5)
+#define RCC_AHB2SECSR_ADC2SECF BIT(6)
+#define RCC_AHB2SECSR_USBOSECF BIT(8)
+
+/* RCC_AHB4SECSR register fields */
+#define RCC_AHB4SECSR_TSCSECF BIT(15)
+
+/* RCC_AHB5SECSR register fields */
+#define RCC_AHB5SECSR_PKASECF BIT(2)
+#define RCC_AHB5SECSR_SAESSECF BIT(3)
+#define RCC_AHB5SECSR_CRYP1SECF BIT(4)
+#define RCC_AHB5SECSR_HASH1SECF BIT(5)
+#define RCC_AHB5SECSR_RNG1SECF BIT(6)
+#define RCC_AHB5SECSR_BKPSRAMSECF BIT(8)
+
+/* RCC_AHB6SECSR register fields */
+#define RCC_AHB6SECSR_MCESECF BIT(1)
+#define RCC_AHB6SECSR_ETH1SECF_MASK GENMASK(11, 7)
+#define RCC_AHB6SECSR_ETH1SECF_SHIFT 7
+#define RCC_AHB6SECSR_FMCSECF BIT(12)
+#define RCC_AHB6SECSR_QSPISECF BIT(14)
+#define RCC_AHB6SECSR_SDMMC1SECF BIT(16)
+#define RCC_AHB6SECSR_SDMMC2SECF BIT(17)
+#define RCC_AHB6SECSR_ETH2SECF_MASK GENMASK(31, 27)
+#define RCC_AHB6SECSR_ETH2SECF_SHIFT 27
+
+/* RCC_VERR register fields */
+#define RCC_VERR_MINREV_MASK GENMASK(3, 0)
+#define RCC_VERR_MINREV_SHIFT 0
+#define RCC_VERR_MAJREV_MASK GENMASK(7, 4)
+#define RCC_VERR_MAJREV_SHIFT 4
+
+/* RCC_IDR register fields */
+#define RCC_IDR_ID_MASK GENMASK(31, 0)
+#define RCC_IDR_ID_SHIFT 0
+
+/* RCC_SIDR register fields */
+#define RCC_SIDR_SID_MASK GENMASK(31, 0)
+#define RCC_SIDR_SID_SHIFT 0
+
+/* Used for all RCC_PLL<n>CR registers */
+#define RCC_PLLNCR_PLLON BIT(0)
+#define RCC_PLLNCR_PLLRDY BIT(1)
+#define RCC_PLLNCR_SSCG_CTRL BIT(2)
+#define RCC_PLLNCR_DIVPEN BIT(4)
+#define RCC_PLLNCR_DIVQEN BIT(5)
+#define RCC_PLLNCR_DIVREN BIT(6)
+#define RCC_PLLNCR_DIVEN_SHIFT 4
+
+/* Used for all RCC_PLL<n>CFGR1 registers */
+#define RCC_PLLNCFGR1_DIVM_SHIFT 16
+#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
+#define RCC_PLLNCFGR1_DIVN_SHIFT 0
+#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
+
+/* Only for PLL3 and PLL4 */
+#define RCC_PLLNCFGR1_IFRGE_SHIFT 24
+#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
+
+/* Used for all RCC_PLL<n>CFGR2 registers */
+#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
+#define RCC_PLLNCFGR2_DIVP_SHIFT 0
+#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
+#define RCC_PLLNCFGR2_DIVQ_SHIFT 8
+#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
+#define RCC_PLLNCFGR2_DIVR_SHIFT 16
+#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
+
+/* Used for all RCC_PLL<n>FRACR registers */
+#define RCC_PLLNFRACR_FRACV_SHIFT 3
+#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
+#define RCC_PLLNFRACR_FRACLE BIT(16)
+
+/* Used for all RCC_PLL<n>CSGR registers */
+#define RCC_PLLNCSGR_INC_STEP_SHIFT 16
+#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
+#define RCC_PLLNCSGR_MOD_PER_SHIFT 0
+#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
+#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
+#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
+
+/* Used for most of RCC_<x>SELR registers */
+#define RCC_SELR_SRC_MASK GENMASK(2, 0)
+#define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0)
+#define RCC_SELR_SRCRDY BIT(31)
+
+/* Values of RCC_MPCKSELR register */
+#define RCC_MPCKSELR_HSI 0x00000000
+#define RCC_MPCKSELR_HSE 0x00000001
+#define RCC_MPCKSELR_PLL 0x00000002
+#define RCC_MPCKSELR_PLL_MPUDIV 0x00000003
+
+/* Values of RCC_ASSCKSELR register */
+#define RCC_ASSCKSELR_HSI 0x00000000
+#define RCC_ASSCKSELR_HSE 0x00000001
+#define RCC_ASSCKSELR_PLL 0x00000002
+
+/* Values of RCC_MSSCKSELR register */
+#define RCC_MSSCKSELR_HSI 0x00000000
+#define RCC_MSSCKSELR_HSE 0x00000001
+#define RCC_MSSCKSELR_CSI 0x00000002
+#define RCC_MSSCKSELR_PLL 0x00000003
+
+/* Values of RCC_CPERCKSELR register */
+#define RCC_CPERCKSELR_HSI 0x00000000
+#define RCC_CPERCKSELR_CSI 0x00000001
+#define RCC_CPERCKSELR_HSE 0x00000002
+
+/* Used for most of DIVR register: max div for RTC */
+#define RCC_DIVR_DIV_MASK GENMASK(5, 0)
+#define RCC_DIVR_DIVRDY BIT(31)
+
+/* Masks for specific DIVR registers */
+#define RCC_APBXDIV_MASK GENMASK(2, 0)
+#define RCC_MPUDIV_MASK GENMASK(2, 0)
+#define RCC_AXIDIV_MASK GENMASK(2, 0)
+#define RCC_MLAHBDIV_MASK GENMASK(3, 0)
+
+/* Used for TIMER Prescaler */
+#define RCC_TIMGXPRER_TIMGXPRE BIT(0)
+
+/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
+#define RCC_MP_ENCLRR_OFFSET U(4)
+
+/* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */
+#define RCC_RSTCLRR_OFFSET U(4)
+
+/* RCC_OCENSETR register fields */
+#define RCC_OCENR_HSION BIT(0)
+#define RCC_OCENR_HSIKERON BIT(1)
+#define RCC_OCENR_CSION BIT(4)
+#define RCC_OCENR_CSIKERON BIT(5)
+#define RCC_OCENR_DIGBYP BIT(7)
+#define RCC_OCENR_HSEON BIT(8)
+#define RCC_OCENR_HSEKERON BIT(9)
+#define RCC_OCENR_HSEBYP BIT(10)
+#define RCC_OCENR_HSECSSON BIT(11)
+
+#define RCC_OCENR_DIGBYP_BIT 7
+#define RCC_OCENR_HSEBYP_BIT 10
+#define RCC_OCENR_HSECSSON_BIT 11
+
+/* Used for RCC_MCO related operations */
+#define RCC_MCOCFG_MCOON BIT(12)
+#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
+#define RCC_MCOCFG_MCODIV_SHIFT 4
+#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
+
+#define RCC_UART4CKSELR_HSI 0x00000002
+
+#define RCC_CPERCKSELR_PERSRC_MASK GENMASK(1, 0)
+#define RCC_CPERCKSELR_PERSRC_SHIFT 0
+
+#define RCC_USBCKSELR_USBOSRC_MASK BIT(4)
+#define RCC_USBCKSELR_USBOSRC_SHIFT 4
+
+#define RCC_DDRITFCR_DDRCKMOD_SSR 0
+#define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20)
+#define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21)
+
+#define RCC_DDRITFCR_DDRC2EN BIT(0)
+#define RCC_DDRITFCR_DDRC2LPEN BIT(1)
+
+#define RCC_MP_CIFR_MASK U(0x110F1F)
+#define RCC_OFFSET_MASK GENMASK(11, 0)
+
+#endif /* STM32MP1_RCC_H */
diff --git a/include/drivers/st/stm32mp15_rcc.h b/include/drivers/st/stm32mp15_rcc.h
new file mode 100644
index 0000000..ddc0397
--- /dev/null
+++ b/include/drivers/st/stm32mp15_rcc.h
@@ -0,0 +1,2328 @@
+/*
+ * Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP1_RCC_H
+#define STM32MP1_RCC_H
+
+#include <lib/utils_def.h>
+
+#define RCC_TZCR U(0x00)
+#define RCC_OCENSETR U(0x0C)
+#define RCC_OCENCLRR U(0x10)
+#define RCC_HSICFGR U(0x18)
+#define RCC_CSICFGR U(0x1C)
+#define RCC_MPCKSELR U(0x20)
+#define RCC_ASSCKSELR U(0x24)
+#define RCC_RCK12SELR U(0x28)
+#define RCC_MPCKDIVR U(0x2C)
+#define RCC_AXIDIVR U(0x30)
+#define RCC_APB4DIVR U(0x3C)
+#define RCC_APB5DIVR U(0x40)
+#define RCC_RTCDIVR U(0x44)
+#define RCC_MSSCKSELR U(0x48)
+#define RCC_PLL1CR U(0x80)
+#define RCC_PLL1CFGR1 U(0x84)
+#define RCC_PLL1CFGR2 U(0x88)
+#define RCC_PLL1FRACR U(0x8C)
+#define RCC_PLL1CSGR U(0x90)
+#define RCC_PLL2CR U(0x94)
+#define RCC_PLL2CFGR1 U(0x98)
+#define RCC_PLL2CFGR2 U(0x9C)
+#define RCC_PLL2FRACR U(0xA0)
+#define RCC_PLL2CSGR U(0xA4)
+#define RCC_I2C46CKSELR U(0xC0)
+#define RCC_SPI6CKSELR U(0xC4)
+#define RCC_UART1CKSELR U(0xC8)
+#define RCC_RNG1CKSELR U(0xCC)
+#define RCC_CPERCKSELR U(0xD0)
+#define RCC_STGENCKSELR U(0xD4)
+#define RCC_DDRITFCR U(0xD8)
+#define RCC_MP_BOOTCR U(0x100)
+#define RCC_MP_SREQSETR U(0x104)
+#define RCC_MP_SREQCLRR U(0x108)
+#define RCC_MP_GCR U(0x10C)
+#define RCC_MP_APRSTCR U(0x110)
+#define RCC_MP_APRSTSR U(0x114)
+#define RCC_BDCR U(0x140)
+#define RCC_RDLSICR U(0x144)
+#define RCC_APB4RSTSETR U(0x180)
+#define RCC_APB4RSTCLRR U(0x184)
+#define RCC_APB5RSTSETR U(0x188)
+#define RCC_APB5RSTCLRR U(0x18C)
+#define RCC_AHB5RSTSETR U(0x190)
+#define RCC_AHB5RSTCLRR U(0x194)
+#define RCC_AHB6RSTSETR U(0x198)
+#define RCC_AHB6RSTCLRR U(0x19C)
+#define RCC_TZAHB6RSTSETR U(0x1A0)
+#define RCC_TZAHB6RSTCLRR U(0x1A4)
+#define RCC_MP_APB4ENSETR U(0x200)
+#define RCC_MP_APB4ENCLRR U(0x204)
+#define RCC_MP_APB5ENSETR U(0x208)
+#define RCC_MP_APB5ENCLRR U(0x20C)
+#define RCC_MP_AHB5ENSETR U(0x210)
+#define RCC_MP_AHB5ENCLRR U(0x214)
+#define RCC_MP_AHB6ENSETR U(0x218)
+#define RCC_MP_AHB6ENCLRR U(0x21C)
+#define RCC_MP_TZAHB6ENSETR U(0x220)
+#define RCC_MP_TZAHB6ENCLRR U(0x224)
+#define RCC_MC_APB4ENSETR U(0x280)
+#define RCC_MC_APB4ENCLRR U(0x284)
+#define RCC_MC_APB5ENSETR U(0x288)
+#define RCC_MC_APB5ENCLRR U(0x28C)
+#define RCC_MC_AHB5ENSETR U(0x290)
+#define RCC_MC_AHB5ENCLRR U(0x294)
+#define RCC_MC_AHB6ENSETR U(0x298)
+#define RCC_MC_AHB6ENCLRR U(0x29C)
+#define RCC_MP_APB4LPENSETR U(0x300)
+#define RCC_MP_APB4LPENCLRR U(0x304)
+#define RCC_MP_APB5LPENSETR U(0x308)
+#define RCC_MP_APB5LPENCLRR U(0x30C)
+#define RCC_MP_AHB5LPENSETR U(0x310)
+#define RCC_MP_AHB5LPENCLRR U(0x314)
+#define RCC_MP_AHB6LPENSETR U(0x318)
+#define RCC_MP_AHB6LPENCLRR U(0x31C)
+#define RCC_MP_TZAHB6LPENSETR U(0x320)
+#define RCC_MP_TZAHB6LPENCLRR U(0x324)
+#define RCC_MC_APB4LPENSETR U(0x380)
+#define RCC_MC_APB4LPENCLRR U(0x384)
+#define RCC_MC_APB5LPENSETR U(0x388)
+#define RCC_MC_APB5LPENCLRR U(0x38C)
+#define RCC_MC_AHB5LPENSETR U(0x390)
+#define RCC_MC_AHB5LPENCLRR U(0x394)
+#define RCC_MC_AHB6LPENSETR U(0x398)
+#define RCC_MC_AHB6LPENCLRR U(0x39C)
+#define RCC_BR_RSTSCLRR U(0x400)
+#define RCC_MP_GRSTCSETR U(0x404)
+#define RCC_MP_RSTSCLRR U(0x408)
+#define RCC_MP_IWDGFZSETR U(0x40C)
+#define RCC_MP_IWDGFZCLRR U(0x410)
+#define RCC_MP_CIER U(0x414)
+#define RCC_MP_CIFR U(0x418)
+#define RCC_PWRLPDLYCR U(0x41C)
+#define RCC_MP_RSTSSETR U(0x420)
+#define RCC_MCO1CFGR U(0x800)
+#define RCC_MCO2CFGR U(0x804)
+#define RCC_OCRDYR U(0x808)
+#define RCC_DBGCFGR U(0x80C)
+#define RCC_RCK3SELR U(0x820)
+#define RCC_RCK4SELR U(0x824)
+#define RCC_TIMG1PRER U(0x828)
+#define RCC_TIMG2PRER U(0x82C)
+#define RCC_MCUDIVR U(0x830)
+#define RCC_APB1DIVR U(0x834)
+#define RCC_APB2DIVR U(0x838)
+#define RCC_APB3DIVR U(0x83C)
+#define RCC_PLL3CR U(0x880)
+#define RCC_PLL3CFGR1 U(0x884)
+#define RCC_PLL3CFGR2 U(0x888)
+#define RCC_PLL3FRACR U(0x88C)
+#define RCC_PLL3CSGR U(0x890)
+#define RCC_PLL4CR U(0x894)
+#define RCC_PLL4CFGR1 U(0x898)
+#define RCC_PLL4CFGR2 U(0x89C)
+#define RCC_PLL4FRACR U(0x8A0)
+#define RCC_PLL4CSGR U(0x8A4)
+#define RCC_I2C12CKSELR U(0x8C0)
+#define RCC_I2C35CKSELR U(0x8C4)
+#define RCC_SAI1CKSELR U(0x8C8)
+#define RCC_SAI2CKSELR U(0x8CC)
+#define RCC_SAI3CKSELR U(0x8D0)
+#define RCC_SAI4CKSELR U(0x8D4)
+#define RCC_SPI2S1CKSELR U(0x8D8)
+#define RCC_SPI2S23CKSELR U(0x8DC)
+#define RCC_SPI45CKSELR U(0x8E0)
+#define RCC_UART6CKSELR U(0x8E4)
+#define RCC_UART24CKSELR U(0x8E8)
+#define RCC_UART35CKSELR U(0x8EC)
+#define RCC_UART78CKSELR U(0x8F0)
+#define RCC_SDMMC12CKSELR U(0x8F4)
+#define RCC_SDMMC3CKSELR U(0x8F8)
+#define RCC_ETHCKSELR U(0x8FC)
+#define RCC_QSPICKSELR U(0x900)
+#define RCC_FMCCKSELR U(0x904)
+#define RCC_FDCANCKSELR U(0x90C)
+#define RCC_SPDIFCKSELR U(0x914)
+#define RCC_CECCKSELR U(0x918)
+#define RCC_USBCKSELR U(0x91C)
+#define RCC_RNG2CKSELR U(0x920)
+#define RCC_DSICKSELR U(0x924)
+#define RCC_ADCCKSELR U(0x928)
+#define RCC_LPTIM45CKSELR U(0x92C)
+#define RCC_LPTIM23CKSELR U(0x930)
+#define RCC_LPTIM1CKSELR U(0x934)
+#define RCC_APB1RSTSETR U(0x980)
+#define RCC_APB1RSTCLRR U(0x984)
+#define RCC_APB2RSTSETR U(0x988)
+#define RCC_APB2RSTCLRR U(0x98C)
+#define RCC_APB3RSTSETR U(0x990)
+#define RCC_APB3RSTCLRR U(0x994)
+#define RCC_AHB2RSTSETR U(0x998)
+#define RCC_AHB2RSTCLRR U(0x99C)
+#define RCC_AHB3RSTSETR U(0x9A0)
+#define RCC_AHB3RSTCLRR U(0x9A4)
+#define RCC_AHB4RSTSETR U(0x9A8)
+#define RCC_AHB4RSTCLRR U(0x9AC)
+#define RCC_MP_APB1ENSETR U(0xA00)
+#define RCC_MP_APB1ENCLRR U(0xA04)
+#define RCC_MP_APB2ENSETR U(0xA08)
+#define RCC_MP_APB2ENCLRR U(0xA0C)
+#define RCC_MP_APB3ENSETR U(0xA10)
+#define RCC_MP_APB3ENCLRR U(0xA14)
+#define RCC_MP_AHB2ENSETR U(0xA18)
+#define RCC_MP_AHB2ENCLRR U(0xA1C)
+#define RCC_MP_AHB3ENSETR U(0xA20)
+#define RCC_MP_AHB3ENCLRR U(0xA24)
+#define RCC_MP_AHB4ENSETR U(0xA28)
+#define RCC_MP_AHB4ENCLRR U(0xA2C)
+#define RCC_MP_MLAHBENSETR U(0xA38)
+#define RCC_MP_MLAHBENCLRR U(0xA3C)
+#define RCC_MC_APB1ENSETR U(0xA80)
+#define RCC_MC_APB1ENCLRR U(0xA84)
+#define RCC_MC_APB2ENSETR U(0xA88)
+#define RCC_MC_APB2ENCLRR U(0xA8C)
+#define RCC_MC_APB3ENSETR U(0xA90)
+#define RCC_MC_APB3ENCLRR U(0xA94)
+#define RCC_MC_AHB2ENSETR U(0xA98)
+#define RCC_MC_AHB2ENCLRR U(0xA9C)
+#define RCC_MC_AHB3ENSETR U(0xAA0)
+#define RCC_MC_AHB3ENCLRR U(0xAA4)
+#define RCC_MC_AHB4ENSETR U(0xAA8)
+#define RCC_MC_AHB4ENCLRR U(0xAAC)
+#define RCC_MC_AXIMENSETR U(0xAB0)
+#define RCC_MC_AXIMENCLRR U(0xAB4)
+#define RCC_MC_MLAHBENSETR U(0xAB8)
+#define RCC_MC_MLAHBENCLRR U(0xABC)
+#define RCC_MP_APB1LPENSETR U(0xB00)
+#define RCC_MP_APB1LPENCLRR U(0xB04)
+#define RCC_MP_APB2LPENSETR U(0xB08)
+#define RCC_MP_APB2LPENCLRR U(0xB0C)
+#define RCC_MP_APB3LPENSETR U(0xB10)
+#define RCC_MP_APB3LPENCLRR U(0xB14)
+#define RCC_MP_AHB2LPENSETR U(0xB18)
+#define RCC_MP_AHB2LPENCLRR U(0xB1C)
+#define RCC_MP_AHB3LPENSETR U(0xB20)
+#define RCC_MP_AHB3LPENCLRR U(0xB24)
+#define RCC_MP_AHB4LPENSETR U(0xB28)
+#define RCC_MP_AHB4LPENCLRR U(0xB2C)
+#define RCC_MP_AXIMLPENSETR U(0xB30)
+#define RCC_MP_AXIMLPENCLRR U(0xB34)
+#define RCC_MP_MLAHBLPENSETR U(0xB38)
+#define RCC_MP_MLAHBLPENCLRR U(0xB3C)
+#define RCC_MC_APB1LPENSETR U(0xB80)
+#define RCC_MC_APB1LPENCLRR U(0xB84)
+#define RCC_MC_APB2LPENSETR U(0xB88)
+#define RCC_MC_APB2LPENCLRR U(0xB8C)
+#define RCC_MC_APB3LPENSETR U(0xB90)
+#define RCC_MC_APB3LPENCLRR U(0xB94)
+#define RCC_MC_AHB2LPENSETR U(0xB98)
+#define RCC_MC_AHB2LPENCLRR U(0xB9C)
+#define RCC_MC_AHB3LPENSETR U(0xBA0)
+#define RCC_MC_AHB3LPENCLRR U(0xBA4)
+#define RCC_MC_AHB4LPENSETR U(0xBA8)
+#define RCC_MC_AHB4LPENCLRR U(0xBAC)
+#define RCC_MC_AXIMLPENSETR U(0xBB0)
+#define RCC_MC_AXIMLPENCLRR U(0xBB4)
+#define RCC_MC_MLAHBLPENSETR U(0xBB8)
+#define RCC_MC_MLAHBLPENCLRR U(0xBBC)
+#define RCC_MC_RSTSCLRR U(0xC00)
+#define RCC_MC_CIER U(0xC14)
+#define RCC_MC_CIFR U(0xC18)
+#define RCC_VERR U(0xFF4)
+#define RCC_IDR U(0xFF8)
+#define RCC_SIDR U(0xFFC)
+
+/* RCC_TZCR register fields */
+#define RCC_TZCR_TZEN BIT(0)
+#define RCC_TZCR_MCKPROT BIT(1)
+
+/* RCC_OCENSETR register fields */
+#define RCC_OCENSETR_HSION BIT(0)
+#define RCC_OCENSETR_HSIKERON BIT(1)
+#define RCC_OCENSETR_CSION BIT(4)
+#define RCC_OCENSETR_CSIKERON BIT(5)
+#define RCC_OCENSETR_DIGBYP BIT(7)
+#define RCC_OCENSETR_HSEON BIT(8)
+#define RCC_OCENSETR_HSEKERON BIT(9)
+#define RCC_OCENSETR_HSEBYP BIT(10)
+#define RCC_OCENSETR_HSECSSON BIT(11)
+
+/* RCC_OCENCLRR register fields */
+#define RCC_OCENCLRR_HSION BIT(0)
+#define RCC_OCENCLRR_HSIKERON BIT(1)
+#define RCC_OCENCLRR_CSION BIT(4)
+#define RCC_OCENCLRR_CSIKERON BIT(5)
+#define RCC_OCENCLRR_DIGBYP BIT(7)
+#define RCC_OCENCLRR_HSEON BIT(8)
+#define RCC_OCENCLRR_HSEKERON BIT(9)
+#define RCC_OCENCLRR_HSEBYP BIT(10)
+
+/* RCC_HSICFGR register fields */
+#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
+#define RCC_HSICFGR_HSIDIV_SHIFT 0
+#define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8)
+#define RCC_HSICFGR_HSITRIM_SHIFT 8
+#define RCC_HSICFGR_HSICAL_MASK GENMASK(24, 16)
+#define RCC_HSICFGR_HSICAL_SHIFT 16
+#define RCC_HSICFGR_HSICAL_TEMP_MASK GENMASK(27, 25)
+
+/* RCC_CSICFGR register fields */
+#define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8)
+#define RCC_CSICFGR_CSITRIM_SHIFT 8
+#define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16)
+#define RCC_CSICFGR_CSICAL_SHIFT 16
+
+/* RCC_MPCKSELR register fields */
+#define RCC_MPCKSELR_HSI 0x00000000
+#define RCC_MPCKSELR_HSE 0x00000001
+#define RCC_MPCKSELR_PLL 0x00000002
+#define RCC_MPCKSELR_PLL_MPUDIV 0x00000003
+#define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0)
+#define RCC_MPCKSELR_MPUSRC_SHIFT 0
+#define RCC_MPCKSELR_MPUSRCRDY BIT(31)
+
+/* RCC_ASSCKSELR register fields */
+#define RCC_ASSCKSELR_HSI 0x00000000
+#define RCC_ASSCKSELR_HSE 0x00000001
+#define RCC_ASSCKSELR_PLL 0x00000002
+#define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0)
+#define RCC_ASSCKSELR_AXISSRC_SHIFT 0
+#define RCC_ASSCKSELR_AXISSRCRDY BIT(31)
+
+/* RCC_RCK12SELR register fields */
+#define RCC_RCK12SELR_PLL12SRC_MASK GENMASK(1, 0)
+#define RCC_RCK12SELR_PLL12SRC_SHIFT 0
+#define RCC_RCK12SELR_PLL12SRCRDY BIT(31)
+
+/* RCC_MPCKDIVR register fields */
+#define RCC_MPCKDIVR_MPUDIV_MASK GENMASK(2, 0)
+#define RCC_MPCKDIVR_MPUDIV_SHIFT 0
+#define RCC_MPCKDIVR_MPUDIVRDY BIT(31)
+
+/* RCC_AXIDIVR register fields */
+#define RCC_AXIDIVR_AXIDIV_MASK GENMASK(2, 0)
+#define RCC_AXIDIVR_AXIDIV_SHIFT 0
+#define RCC_AXIDIVR_AXIDIVRDY BIT(31)
+
+/* RCC_APB4DIVR register fields */
+#define RCC_APB4DIVR_APB4DIV_MASK GENMASK(2, 0)
+#define RCC_APB4DIVR_APB4DIV_SHIFT 0
+#define RCC_APB4DIVR_APB4DIVRDY BIT(31)
+
+/* RCC_APB5DIVR register fields */
+#define RCC_APB5DIVR_APB5DIV_MASK GENMASK(2, 0)
+#define RCC_APB5DIVR_APB5DIV_SHIFT 0
+#define RCC_APB5DIVR_APB5DIVRDY BIT(31)
+
+/* RCC_RTCDIVR register fields */
+#define RCC_RTCDIVR_RTCDIV_MASK GENMASK(5, 0)
+#define RCC_RTCDIVR_RTCDIV_SHIFT 0
+
+/* RCC_MSSCKSELR register fields */
+#define RCC_MSSCKSELR_HSI 0x00000000
+#define RCC_MSSCKSELR_HSE 0x00000001
+#define RCC_MSSCKSELR_CSI 0x00000002
+#define RCC_MSSCKSELR_PLL 0x00000003
+#define RCC_MSSCKSELR_MCUSSRC_MASK GENMASK(1, 0)
+#define RCC_MSSCKSELR_MCUSSRC_SHIFT 0
+#define RCC_MSSCKSELR_MCUSSRCRDY BIT(31)
+
+/* RCC_PLL1CR register fields */
+#define RCC_PLL1CR_PLLON BIT(0)
+#define RCC_PLL1CR_PLL1RDY BIT(1)
+#define RCC_PLL1CR_SSCG_CTRL BIT(2)
+#define RCC_PLL1CR_DIVPEN BIT(4)
+#define RCC_PLL1CR_DIVQEN BIT(5)
+#define RCC_PLL1CR_DIVREN BIT(6)
+
+/* RCC_PLL1CFGR1 register fields */
+#define RCC_PLL1CFGR1_DIVN_MASK GENMASK(8, 0)
+#define RCC_PLL1CFGR1_DIVN_SHIFT 0
+#define RCC_PLL1CFGR1_DIVM1_MASK GENMASK(21, 16)
+#define RCC_PLL1CFGR1_DIVM1_SHIFT 16
+
+/* RCC_PLL1CFGR2 register fields */
+#define RCC_PLL1CFGR2_DIVP_MASK GENMASK(6, 0)
+#define RCC_PLL1CFGR2_DIVP_SHIFT 0
+#define RCC_PLL1CFGR2_DIVQ_MASK GENMASK(14, 8)
+#define RCC_PLL1CFGR2_DIVQ_SHIFT 8
+#define RCC_PLL1CFGR2_DIVR_MASK GENMASK(22, 16)
+#define RCC_PLL1CFGR2_DIVR_SHIFT 16
+
+/* RCC_PLL1FRACR register fields */
+#define RCC_PLL1FRACR_FRACV_MASK GENMASK(15, 3)
+#define RCC_PLL1FRACR_FRACV_SHIFT 3
+#define RCC_PLL1FRACR_FRACLE BIT(16)
+
+/* RCC_PLL1CSGR register fields */
+#define RCC_PLL1CSGR_MOD_PER_MASK GENMASK(12, 0)
+#define RCC_PLL1CSGR_MOD_PER_SHIFT 0
+#define RCC_PLL1CSGR_TPDFN_DIS BIT(13)
+#define RCC_PLL1CSGR_RPDFN_DIS BIT(14)
+#define RCC_PLL1CSGR_SSCG_MODE BIT(15)
+#define RCC_PLL1CSGR_INC_STEP_MASK GENMASK(30, 16)
+#define RCC_PLL1CSGR_INC_STEP_SHIFT 16
+
+/* RCC_PLL2CR register fields */
+#define RCC_PLL2CR_PLLON BIT(0)
+#define RCC_PLL2CR_PLL2RDY BIT(1)
+#define RCC_PLL2CR_SSCG_CTRL BIT(2)
+#define RCC_PLL2CR_DIVPEN BIT(4)
+#define RCC_PLL2CR_DIVQEN BIT(5)
+#define RCC_PLL2CR_DIVREN BIT(6)
+
+/* RCC_PLL2CFGR1 register fields */
+#define RCC_PLL2CFGR1_DIVN_MASK GENMASK(8, 0)
+#define RCC_PLL2CFGR1_DIVN_SHIFT 0
+#define RCC_PLL2CFGR1_DIVM2_MASK GENMASK(21, 16)
+#define RCC_PLL2CFGR1_DIVM2_SHIFT 16
+
+/* RCC_PLL2CFGR2 register fields */
+#define RCC_PLL2CFGR2_DIVP_MASK GENMASK(6, 0)
+#define RCC_PLL2CFGR2_DIVP_SHIFT 0
+#define RCC_PLL2CFGR2_DIVQ_MASK GENMASK(14, 8)
+#define RCC_PLL2CFGR2_DIVQ_SHIFT 8
+#define RCC_PLL2CFGR2_DIVR_MASK GENMASK(22, 16)
+#define RCC_PLL2CFGR2_DIVR_SHIFT 16
+
+/* RCC_PLL2FRACR register fields */
+#define RCC_PLL2FRACR_FRACV_MASK GENMASK(15, 3)
+#define RCC_PLL2FRACR_FRACV_SHIFT 3
+#define RCC_PLL2FRACR_FRACLE BIT(16)
+
+/* RCC_PLL2CSGR register fields */
+#define RCC_PLL2CSGR_MOD_PER_MASK GENMASK(12, 0)
+#define RCC_PLL2CSGR_MOD_PER_SHIFT 0
+#define RCC_PLL2CSGR_TPDFN_DIS BIT(13)
+#define RCC_PLL2CSGR_RPDFN_DIS BIT(14)
+#define RCC_PLL2CSGR_SSCG_MODE BIT(15)
+#define RCC_PLL2CSGR_INC_STEP_MASK GENMASK(30, 16)
+#define RCC_PLL2CSGR_INC_STEP_SHIFT 16
+
+/* RCC_I2C46CKSELR register fields */
+#define RCC_I2C46CKSELR_I2C46SRC_MASK GENMASK(2, 0)
+#define RCC_I2C46CKSELR_I2C46SRC_SHIFT 0
+
+/* RCC_SPI6CKSELR register fields */
+#define RCC_SPI6CKSELR_SPI6SRC_MASK GENMASK(2, 0)
+#define RCC_SPI6CKSELR_SPI6SRC_SHIFT 0
+
+/* RCC_UART1CKSELR register fields */
+#define RCC_UART1CKSELR_UART1SRC_MASK GENMASK(2, 0)
+#define RCC_UART1CKSELR_UART1SRC_SHIFT 0
+
+/* RCC_RNG1CKSELR register fields */
+#define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0)
+#define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0
+
+/* RCC_CPERCKSELR register fields */
+#define RCC_CPERCKSELR_HSI 0x00000000
+#define RCC_CPERCKSELR_CSI 0x00000001
+#define RCC_CPERCKSELR_HSE 0x00000002
+#define RCC_CPERCKSELR_CKPERSRC_MASK GENMASK(1, 0)
+#define RCC_CPERCKSELR_CKPERSRC_SHIFT 0
+
+/* RCC_STGENCKSELR register fields */
+#define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0)
+#define RCC_STGENCKSELR_STGENSRC_SHIFT 0
+
+/* RCC_DDRITFCR register fields */
+#define RCC_DDRITFCR_DDRC1EN BIT(0)
+#define RCC_DDRITFCR_DDRC1LPEN BIT(1)
+#define RCC_DDRITFCR_DDRC2EN BIT(2)
+#define RCC_DDRITFCR_DDRC2LPEN BIT(3)
+#define RCC_DDRITFCR_DDRPHYCEN BIT(4)
+#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5)
+#define RCC_DDRITFCR_DDRCAPBEN BIT(6)
+#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7)
+#define RCC_DDRITFCR_AXIDCGEN BIT(8)
+#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9)
+#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10)
+#define RCC_DDRITFCR_KERDCG_DLY_MASK GENMASK(13, 11)
+#define RCC_DDRITFCR_KERDCG_DLY_SHIFT 11
+#define RCC_DDRITFCR_DDRCAPBRST BIT(14)
+#define RCC_DDRITFCR_DDRCAXIRST BIT(15)
+#define RCC_DDRITFCR_DDRCORERST BIT(16)
+#define RCC_DDRITFCR_DPHYAPBRST BIT(17)
+#define RCC_DDRITFCR_DPHYRST BIT(18)
+#define RCC_DDRITFCR_DPHYCTLRST BIT(19)
+#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
+#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
+#define RCC_DDRITFCR_DDRCKMOD_SSR 0
+#define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20)
+#define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21)
+#define RCC_DDRITFCR_GSKPMOD BIT(23)
+#define RCC_DDRITFCR_GSKPCTRL BIT(24)
+#define RCC_DDRITFCR_DFILP_WIDTH_MASK GENMASK(27, 25)
+#define RCC_DDRITFCR_DFILP_WIDTH_SHIFT 25
+#define RCC_DDRITFCR_GSKP_DUR_MASK GENMASK(31, 28)
+#define RCC_DDRITFCR_GSKP_DUR_SHIFT 28
+
+/* RCC_MP_BOOTCR register fields */
+#define RCC_MP_BOOTCR_MCU_BEN BIT(0)
+#define RCC_MP_BOOTCR_MPU_BEN BIT(1)
+
+/* RCC_MP_SREQSETR register fields */
+#define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
+#define RCC_MP_SREQSETR_STPREQ_P1 BIT(1)
+
+/* RCC_MP_SREQCLRR register fields */
+#define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
+#define RCC_MP_SREQCLRR_STPREQ_P1 BIT(1)
+
+/* RCC_MP_GCR register fields */
+#define RCC_MP_GCR_BOOT_MCU BIT(0)
+
+/* RCC_MP_APRSTCR register fields */
+#define RCC_MP_APRSTCR_RDCTLEN BIT(0)
+#define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8)
+#define RCC_MP_APRSTCR_RSTTO_SHIFT 8
+
+/* RCC_MP_APRSTSR register fields */
+#define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8)
+#define RCC_MP_APRSTSR_RSTTOV_SHIFT 8
+
+/* RCC_BDCR register fields */
+#define RCC_BDCR_LSEON BIT(0)
+#define RCC_BDCR_LSEBYP BIT(1)
+#define RCC_BDCR_LSERDY BIT(2)
+#define RCC_BDCR_DIGBYP BIT(3)
+#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
+#define RCC_BDCR_LSEDRV_SHIFT 4
+#define RCC_BDCR_LSECSSON BIT(8)
+#define RCC_BDCR_LSECSSD BIT(9)
+#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
+#define RCC_BDCR_RTCSRC_SHIFT 16
+#define RCC_BDCR_RTCCKEN BIT(20)
+#define RCC_BDCR_VSWRST BIT(31)
+
+/* RCC_RDLSICR register fields */
+#define RCC_RDLSICR_LSION BIT(0)
+#define RCC_RDLSICR_LSIRDY BIT(1)
+#define RCC_RDLSICR_MRD_MASK GENMASK(20, 16)
+#define RCC_RDLSICR_MRD_SHIFT 16
+#define RCC_RDLSICR_EADLY_MASK GENMASK(26, 24)
+#define RCC_RDLSICR_EADLY_SHIFT 24
+#define RCC_RDLSICR_SPARE_MASK GENMASK(31, 27)
+#define RCC_RDLSICR_SPARE_SHIFT 27
+
+/* RCC_APB4RSTSETR register fields */
+#define RCC_APB4RSTSETR_LTDCRST BIT(0)
+#define RCC_APB4RSTSETR_DSIRST BIT(4)
+#define RCC_APB4RSTSETR_DDRPERFMRST BIT(8)
+#define RCC_APB4RSTSETR_USBPHYRST BIT(16)
+
+/* RCC_APB4RSTCLRR register fields */
+#define RCC_APB4RSTCLRR_LTDCRST BIT(0)
+#define RCC_APB4RSTCLRR_DSIRST BIT(4)
+#define RCC_APB4RSTCLRR_DDRPERFMRST BIT(8)
+#define RCC_APB4RSTCLRR_USBPHYRST BIT(16)
+
+/* RCC_APB5RSTSETR register fields */
+#define RCC_APB5RSTSETR_SPI6RST BIT(0)
+#define RCC_APB5RSTSETR_I2C4RST BIT(2)
+#define RCC_APB5RSTSETR_I2C6RST BIT(3)
+#define RCC_APB5RSTSETR_USART1RST BIT(4)
+#define RCC_APB5RSTSETR_STGENRST BIT(20)
+
+/* RCC_APB5RSTCLRR register fields */
+#define RCC_APB5RSTCLRR_SPI6RST BIT(0)
+#define RCC_APB5RSTCLRR_I2C4RST BIT(2)
+#define RCC_APB5RSTCLRR_I2C6RST BIT(3)
+#define RCC_APB5RSTCLRR_USART1RST BIT(4)
+#define RCC_APB5RSTCLRR_STGENRST BIT(20)
+
+/* RCC_AHB5RSTSETR register fields */
+#define RCC_AHB5RSTSETR_GPIOZRST BIT(0)
+#define RCC_AHB5RSTSETR_CRYP1RST BIT(4)
+#define RCC_AHB5RSTSETR_HASH1RST BIT(5)
+#define RCC_AHB5RSTSETR_RNG1RST BIT(6)
+#define RCC_AHB5RSTSETR_AXIMCRST BIT(16)
+
+/* RCC_AHB5RSTCLRR register fields */
+#define RCC_AHB5RSTCLRR_GPIOZRST BIT(0)
+#define RCC_AHB5RSTCLRR_CRYP1RST BIT(4)
+#define RCC_AHB5RSTCLRR_HASH1RST BIT(5)
+#define RCC_AHB5RSTCLRR_RNG1RST BIT(6)
+#define RCC_AHB5RSTCLRR_AXIMCRST BIT(16)
+
+/* RCC_AHB6RSTSETR register fields */
+#define RCC_AHB6RSTSETR_GPURST BIT(5)
+#define RCC_AHB6RSTSETR_ETHMACRST BIT(10)
+#define RCC_AHB6RSTSETR_FMCRST BIT(12)
+#define RCC_AHB6RSTSETR_QSPIRST BIT(14)
+#define RCC_AHB6RSTSETR_SDMMC1RST BIT(16)
+#define RCC_AHB6RSTSETR_SDMMC2RST BIT(17)
+#define RCC_AHB6RSTSETR_CRC1RST BIT(20)
+#define RCC_AHB6RSTSETR_USBHRST BIT(24)
+
+/* RCC_AHB6RSTCLRR register fields */
+#define RCC_AHB6RSTCLRR_ETHMACRST BIT(10)
+#define RCC_AHB6RSTCLRR_FMCRST BIT(12)
+#define RCC_AHB6RSTCLRR_QSPIRST BIT(14)
+#define RCC_AHB6RSTCLRR_SDMMC1RST BIT(16)
+#define RCC_AHB6RSTCLRR_SDMMC2RST BIT(17)
+#define RCC_AHB6RSTCLRR_CRC1RST BIT(20)
+#define RCC_AHB6RSTCLRR_USBHRST BIT(24)
+
+/* RCC_TZAHB6RSTSETR register fields */
+#define RCC_TZAHB6RSTSETR_MDMARST BIT(0)
+
+/* RCC_TZAHB6RSTCLRR register fields */
+#define RCC_TZAHB6RSTCLRR_MDMARST BIT(0)
+
+/* RCC_MP_APB4ENSETR register fields */
+#define RCC_MP_APB4ENSETR_LTDCEN BIT(0)
+#define RCC_MP_APB4ENSETR_DSIEN BIT(4)
+#define RCC_MP_APB4ENSETR_DDRPERFMEN BIT(8)
+#define RCC_MP_APB4ENSETR_IWDG2APBEN BIT(15)
+#define RCC_MP_APB4ENSETR_USBPHYEN BIT(16)
+#define RCC_MP_APB4ENSETR_STGENROEN BIT(20)
+
+/* RCC_MP_APB4ENCLRR register fields */
+#define RCC_MP_APB4ENCLRR_LTDCEN BIT(0)
+#define RCC_MP_APB4ENCLRR_DSIEN BIT(4)
+#define RCC_MP_APB4ENCLRR_DDRPERFMEN BIT(8)
+#define RCC_MP_APB4ENCLRR_IWDG2APBEN BIT(15)
+#define RCC_MP_APB4ENCLRR_USBPHYEN BIT(16)
+#define RCC_MP_APB4ENCLRR_STGENROEN BIT(20)
+
+/* RCC_MP_APB5ENSETR register fields */
+#define RCC_MP_APB5ENSETR_SPI6EN BIT(0)
+#define RCC_MP_APB5ENSETR_I2C4EN BIT(2)
+#define RCC_MP_APB5ENSETR_I2C6EN BIT(3)
+#define RCC_MP_APB5ENSETR_USART1EN BIT(4)
+#define RCC_MP_APB5ENSETR_RTCAPBEN BIT(8)
+#define RCC_MP_APB5ENSETR_TZC1EN BIT(11)
+#define RCC_MP_APB5ENSETR_TZC2EN BIT(12)
+#define RCC_MP_APB5ENSETR_TZPCEN BIT(13)
+#define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(15)
+#define RCC_MP_APB5ENSETR_BSECEN BIT(16)
+#define RCC_MP_APB5ENSETR_STGENEN BIT(20)
+
+/* RCC_MP_APB5ENCLRR register fields */
+#define RCC_MP_APB5ENCLRR_SPI6EN BIT(0)
+#define RCC_MP_APB5ENCLRR_I2C4EN BIT(2)
+#define RCC_MP_APB5ENCLRR_I2C6EN BIT(3)
+#define RCC_MP_APB5ENCLRR_USART1EN BIT(4)
+#define RCC_MP_APB5ENCLRR_RTCAPBEN BIT(8)
+#define RCC_MP_APB5ENCLRR_TZC1EN BIT(11)
+#define RCC_MP_APB5ENCLRR_TZC2EN BIT(12)
+#define RCC_MP_APB5ENCLRR_TZPCEN BIT(13)
+#define RCC_MP_APB5ENCLRR_IWDG1APBEN BIT(15)
+#define RCC_MP_APB5ENCLRR_BSECEN BIT(16)
+#define RCC_MP_APB5ENCLRR_STGENEN BIT(20)
+
+/* RCC_MP_AHB5ENSETR register fields */
+#define RCC_MP_AHB5ENSETR_GPIOZEN BIT(0)
+#define RCC_MP_AHB5ENSETR_CRYP1EN BIT(4)
+#define RCC_MP_AHB5ENSETR_HASH1EN BIT(5)
+#define RCC_MP_AHB5ENSETR_RNG1EN BIT(6)
+#define RCC_MP_AHB5ENSETR_BKPSRAMEN BIT(8)
+#define RCC_MP_AHB5ENSETR_AXIMCEN BIT(16)
+
+/* RCC_MP_AHB5ENCLRR register fields */
+#define RCC_MP_AHB5ENCLRR_GPIOZEN BIT(0)
+#define RCC_MP_AHB5ENCLRR_CRYP1EN BIT(4)
+#define RCC_MP_AHB5ENCLRR_HASH1EN BIT(5)
+#define RCC_MP_AHB5ENCLRR_RNG1EN BIT(6)
+#define RCC_MP_AHB5ENCLRR_BKPSRAMEN BIT(8)
+#define RCC_MP_AHB5ENCLRR_AXIMCEN BIT(16)
+
+/* RCC_MP_AHB6ENSETR register fields */
+#define RCC_MP_AHB6ENSETR_MDMAEN BIT(0)
+#define RCC_MP_AHB6ENSETR_GPUEN BIT(5)
+#define RCC_MP_AHB6ENSETR_ETHCKEN BIT(7)
+#define RCC_MP_AHB6ENSETR_ETHTXEN BIT(8)
+#define RCC_MP_AHB6ENSETR_ETHRXEN BIT(9)
+#define RCC_MP_AHB6ENSETR_ETHMACEN BIT(10)
+#define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
+#define RCC_MP_AHB6ENSETR_QSPIEN BIT(14)
+#define RCC_MP_AHB6ENSETR_SDMMC1EN BIT(16)
+#define RCC_MP_AHB6ENSETR_SDMMC2EN BIT(17)
+#define RCC_MP_AHB6ENSETR_CRC1EN BIT(20)
+#define RCC_MP_AHB6ENSETR_USBHEN BIT(24)
+
+/* RCC_MP_AHB6ENCLRR register fields */
+#define RCC_MP_AHB6ENCLRR_MDMAEN BIT(0)
+#define RCC_MP_AHB6ENCLRR_GPUEN BIT(5)
+#define RCC_MP_AHB6ENCLRR_ETHCKEN BIT(7)
+#define RCC_MP_AHB6ENCLRR_ETHTXEN BIT(8)
+#define RCC_MP_AHB6ENCLRR_ETHRXEN BIT(9)
+#define RCC_MP_AHB6ENCLRR_ETHMACEN BIT(10)
+#define RCC_MP_AHB6ENCLRR_FMCEN BIT(12)
+#define RCC_MP_AHB6ENCLRR_QSPIEN BIT(14)
+#define RCC_MP_AHB6ENCLRR_SDMMC1EN BIT(16)
+#define RCC_MP_AHB6ENCLRR_SDMMC2EN BIT(17)
+#define RCC_MP_AHB6ENCLRR_CRC1EN BIT(20)
+#define RCC_MP_AHB6ENCLRR_USBHEN BIT(24)
+
+/* RCC_MP_TZAHB6ENSETR register fields */
+#define RCC_MP_TZAHB6ENSETR_MDMAEN BIT(0)
+
+/* RCC_MP_TZAHB6ENCLRR register fields */
+#define RCC_MP_TZAHB6ENCLRR_MDMAEN BIT(0)
+
+/* RCC_MC_APB4ENSETR register fields */
+#define RCC_MC_APB4ENSETR_LTDCEN BIT(0)
+#define RCC_MC_APB4ENSETR_DSIEN BIT(4)
+#define RCC_MC_APB4ENSETR_DDRPERFMEN BIT(8)
+#define RCC_MC_APB4ENSETR_USBPHYEN BIT(16)
+#define RCC_MC_APB4ENSETR_STGENROEN BIT(20)
+
+/* RCC_MC_APB4ENCLRR register fields */
+#define RCC_MC_APB4ENCLRR_LTDCEN BIT(0)
+#define RCC_MC_APB4ENCLRR_DSIEN BIT(4)
+#define RCC_MC_APB4ENCLRR_DDRPERFMEN BIT(8)
+#define RCC_MC_APB4ENCLRR_USBPHYEN BIT(16)
+#define RCC_MC_APB4ENCLRR_STGENROEN BIT(20)
+
+/* RCC_MC_APB5ENSETR register fields */
+#define RCC_MC_APB5ENSETR_SPI6EN BIT(0)
+#define RCC_MC_APB5ENSETR_I2C4EN BIT(2)
+#define RCC_MC_APB5ENSETR_I2C6EN BIT(3)
+#define RCC_MC_APB5ENSETR_USART1EN BIT(4)
+#define RCC_MC_APB5ENSETR_RTCAPBEN BIT(8)
+#define RCC_MC_APB5ENSETR_TZC1EN BIT(11)
+#define RCC_MC_APB5ENSETR_TZC2EN BIT(12)
+#define RCC_MC_APB5ENSETR_TZPCEN BIT(13)
+#define RCC_MC_APB5ENSETR_BSECEN BIT(16)
+#define RCC_MC_APB5ENSETR_STGENEN BIT(20)
+
+/* RCC_MC_APB5ENCLRR register fields */
+#define RCC_MC_APB5ENCLRR_SPI6EN BIT(0)
+#define RCC_MC_APB5ENCLRR_I2C4EN BIT(2)
+#define RCC_MC_APB5ENCLRR_I2C6EN BIT(3)
+#define RCC_MC_APB5ENCLRR_USART1EN BIT(4)
+#define RCC_MC_APB5ENCLRR_RTCAPBEN BIT(8)
+#define RCC_MC_APB5ENCLRR_TZC1EN BIT(11)
+#define RCC_MC_APB5ENCLRR_TZC2EN BIT(12)
+#define RCC_MC_APB5ENCLRR_TZPCEN BIT(13)
+#define RCC_MC_APB5ENCLRR_BSECEN BIT(16)
+#define RCC_MC_APB5ENCLRR_STGENEN BIT(20)
+
+/* RCC_MC_AHB5ENSETR register fields */
+#define RCC_MC_AHB5ENSETR_GPIOZEN BIT(0)
+#define RCC_MC_AHB5ENSETR_CRYP1EN BIT(4)
+#define RCC_MC_AHB5ENSETR_HASH1EN BIT(5)
+#define RCC_MC_AHB5ENSETR_RNG1EN BIT(6)
+#define RCC_MC_AHB5ENSETR_BKPSRAMEN BIT(8)
+
+/* RCC_MC_AHB5ENCLRR register fields */
+#define RCC_MC_AHB5ENCLRR_GPIOZEN BIT(0)
+#define RCC_MC_AHB5ENCLRR_CRYP1EN BIT(4)
+#define RCC_MC_AHB5ENCLRR_HASH1EN BIT(5)
+#define RCC_MC_AHB5ENCLRR_RNG1EN BIT(6)
+#define RCC_MC_AHB5ENCLRR_BKPSRAMEN BIT(8)
+
+/* RCC_MC_AHB6ENSETR register fields */
+#define RCC_MC_AHB6ENSETR_MDMAEN BIT(0)
+#define RCC_MC_AHB6ENSETR_GPUEN BIT(5)
+#define RCC_MC_AHB6ENSETR_ETHCKEN BIT(7)
+#define RCC_MC_AHB6ENSETR_ETHTXEN BIT(8)
+#define RCC_MC_AHB6ENSETR_ETHRXEN BIT(9)
+#define RCC_MC_AHB6ENSETR_ETHMACEN BIT(10)
+#define RCC_MC_AHB6ENSETR_FMCEN BIT(12)
+#define RCC_MC_AHB6ENSETR_QSPIEN BIT(14)
+#define RCC_MC_AHB6ENSETR_SDMMC1EN BIT(16)
+#define RCC_MC_AHB6ENSETR_SDMMC2EN BIT(17)
+#define RCC_MC_AHB6ENSETR_CRC1EN BIT(20)
+#define RCC_MC_AHB6ENSETR_USBHEN BIT(24)
+
+/* RCC_MC_AHB6ENCLRR register fields */
+#define RCC_MC_AHB6ENCLRR_MDMAEN BIT(0)
+#define RCC_MC_AHB6ENCLRR_GPUEN BIT(5)
+#define RCC_MC_AHB6ENCLRR_ETHCKEN BIT(7)
+#define RCC_MC_AHB6ENCLRR_ETHTXEN BIT(8)
+#define RCC_MC_AHB6ENCLRR_ETHRXEN BIT(9)
+#define RCC_MC_AHB6ENCLRR_ETHMACEN BIT(10)
+#define RCC_MC_AHB6ENCLRR_FMCEN BIT(12)
+#define RCC_MC_AHB6ENCLRR_QSPIEN BIT(14)
+#define RCC_MC_AHB6ENCLRR_SDMMC1EN BIT(16)
+#define RCC_MC_AHB6ENCLRR_SDMMC2EN BIT(17)
+#define RCC_MC_AHB6ENCLRR_CRC1EN BIT(20)
+#define RCC_MC_AHB6ENCLRR_USBHEN BIT(24)
+
+/* RCC_MP_APB4LPENSETR register fields */
+#define RCC_MP_APB4LPENSETR_LTDCLPEN BIT(0)
+#define RCC_MP_APB4LPENSETR_DSILPEN BIT(4)
+#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN BIT(8)
+#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN BIT(15)
+#define RCC_MP_APB4LPENSETR_USBPHYLPEN BIT(16)
+#define RCC_MP_APB4LPENSETR_STGENROLPEN BIT(20)
+#define RCC_MP_APB4LPENSETR_STGENROSTPEN BIT(21)
+
+/* RCC_MP_APB4LPENCLRR register fields */
+#define RCC_MP_APB4LPENCLRR_LTDCLPEN BIT(0)
+#define RCC_MP_APB4LPENCLRR_DSILPEN BIT(4)
+#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN BIT(8)
+#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN BIT(15)
+#define RCC_MP_APB4LPENCLRR_USBPHYLPEN BIT(16)
+#define RCC_MP_APB4LPENCLRR_STGENROLPEN BIT(20)
+#define RCC_MP_APB4LPENCLRR_STGENROSTPEN BIT(21)
+
+/* RCC_MP_APB5LPENSETR register fields */
+#define RCC_MP_APB5LPENSETR_SPI6LPEN BIT(0)
+#define RCC_MP_APB5LPENSETR_I2C4LPEN BIT(2)
+#define RCC_MP_APB5LPENSETR_I2C6LPEN BIT(3)
+#define RCC_MP_APB5LPENSETR_USART1LPEN BIT(4)
+#define RCC_MP_APB5LPENSETR_RTCAPBLPEN BIT(8)
+#define RCC_MP_APB5LPENSETR_TZC1LPEN BIT(11)
+#define RCC_MP_APB5LPENSETR_TZC2LPEN BIT(12)
+#define RCC_MP_APB5LPENSETR_TZPCLPEN BIT(13)
+#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN BIT(15)
+#define RCC_MP_APB5LPENSETR_BSECLPEN BIT(16)
+#define RCC_MP_APB5LPENSETR_STGENLPEN BIT(20)
+#define RCC_MP_APB5LPENSETR_STGENSTPEN BIT(21)
+
+/* RCC_MP_APB5LPENCLRR register fields */
+#define RCC_MP_APB5LPENCLRR_SPI6LPEN BIT(0)
+#define RCC_MP_APB5LPENCLRR_I2C4LPEN BIT(2)
+#define RCC_MP_APB5LPENCLRR_I2C6LPEN BIT(3)
+#define RCC_MP_APB5LPENCLRR_USART1LPEN BIT(4)
+#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN BIT(8)
+#define RCC_MP_APB5LPENCLRR_TZC1LPEN BIT(11)
+#define RCC_MP_APB5LPENCLRR_TZC2LPEN BIT(12)
+#define RCC_MP_APB5LPENCLRR_TZPCLPEN BIT(13)
+#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN BIT(15)
+#define RCC_MP_APB5LPENCLRR_BSECLPEN BIT(16)
+#define RCC_MP_APB5LPENCLRR_STGENLPEN BIT(20)
+#define RCC_MP_APB5LPENCLRR_STGENSTPEN BIT(21)
+
+/* RCC_MP_AHB5LPENSETR register fields */
+#define RCC_MP_AHB5LPENSETR_GPIOZLPEN BIT(0)
+#define RCC_MP_AHB5LPENSETR_CRYP1LPEN BIT(4)
+#define RCC_MP_AHB5LPENSETR_HASH1LPEN BIT(5)
+#define RCC_MP_AHB5LPENSETR_RNG1LPEN BIT(6)
+#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN BIT(8)
+
+/* RCC_MP_AHB5LPENCLRR register fields */
+#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN BIT(0)
+#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN BIT(4)
+#define RCC_MP_AHB5LPENCLRR_HASH1LPEN BIT(5)
+#define RCC_MP_AHB5LPENCLRR_RNG1LPEN BIT(6)
+#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN BIT(8)
+
+/* RCC_MP_AHB6LPENSETR register fields */
+#define RCC_MP_AHB6LPENSETR_MDMALPEN BIT(0)
+#define RCC_MP_AHB6LPENSETR_GPULPEN BIT(5)
+#define RCC_MP_AHB6LPENSETR_ETHCKLPEN BIT(7)
+#define RCC_MP_AHB6LPENSETR_ETHTXLPEN BIT(8)
+#define RCC_MP_AHB6LPENSETR_ETHRXLPEN BIT(9)
+#define RCC_MP_AHB6LPENSETR_ETHMACLPEN BIT(10)
+#define RCC_MP_AHB6LPENSETR_ETHSTPEN BIT(11)
+#define RCC_MP_AHB6LPENSETR_FMCLPEN BIT(12)
+#define RCC_MP_AHB6LPENSETR_QSPILPEN BIT(14)
+#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN BIT(16)
+#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN BIT(17)
+#define RCC_MP_AHB6LPENSETR_CRC1LPEN BIT(20)
+#define RCC_MP_AHB6LPENSETR_USBHLPEN BIT(24)
+
+/* RCC_MP_AHB6LPENCLRR register fields */
+#define RCC_MP_AHB6LPENCLRR_MDMALPEN BIT(0)
+#define RCC_MP_AHB6LPENCLRR_GPULPEN BIT(5)
+#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN BIT(7)
+#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN BIT(8)
+#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN BIT(9)
+#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN BIT(10)
+#define RCC_MP_AHB6LPENCLRR_ETHSTPEN BIT(11)
+#define RCC_MP_AHB6LPENCLRR_FMCLPEN BIT(12)
+#define RCC_MP_AHB6LPENCLRR_QSPILPEN BIT(14)
+#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN BIT(16)
+#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN BIT(17)
+#define RCC_MP_AHB6LPENCLRR_CRC1LPEN BIT(20)
+#define RCC_MP_AHB6LPENCLRR_USBHLPEN BIT(24)
+
+/* RCC_MP_TZAHB6LPENSETR register fields */
+#define RCC_MP_TZAHB6LPENSETR_MDMALPEN BIT(0)
+
+/* RCC_MP_TZAHB6LPENCLRR register fields */
+#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN BIT(0)
+
+/* RCC_MC_APB4LPENSETR register fields */
+#define RCC_MC_APB4LPENSETR_LTDCLPEN BIT(0)
+#define RCC_MC_APB4LPENSETR_DSILPEN BIT(4)
+#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN BIT(8)
+#define RCC_MC_APB4LPENSETR_USBPHYLPEN BIT(16)
+#define RCC_MC_APB4LPENSETR_STGENROLPEN BIT(20)
+#define RCC_MC_APB4LPENSETR_STGENROSTPEN BIT(21)
+
+/* RCC_MC_APB4LPENCLRR register fields */
+#define RCC_MC_APB4LPENCLRR_LTDCLPEN BIT(0)
+#define RCC_MC_APB4LPENCLRR_DSILPEN BIT(4)
+#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN BIT(8)
+#define RCC_MC_APB4LPENCLRR_USBPHYLPEN BIT(16)
+#define RCC_MC_APB4LPENCLRR_STGENROLPEN BIT(20)
+#define RCC_MC_APB4LPENCLRR_STGENROSTPEN BIT(21)
+
+/* RCC_MC_APB5LPENSETR register fields */
+#define RCC_MC_APB5LPENSETR_SPI6LPEN BIT(0)
+#define RCC_MC_APB5LPENSETR_I2C4LPEN BIT(2)
+#define RCC_MC_APB5LPENSETR_I2C6LPEN BIT(3)
+#define RCC_MC_APB5LPENSETR_USART1LPEN BIT(4)
+#define RCC_MC_APB5LPENSETR_RTCAPBLPEN BIT(8)
+#define RCC_MC_APB5LPENSETR_TZC1LPEN BIT(11)
+#define RCC_MC_APB5LPENSETR_TZC2LPEN BIT(12)
+#define RCC_MC_APB5LPENSETR_TZPCLPEN BIT(13)
+#define RCC_MC_APB5LPENSETR_BSECLPEN BIT(16)
+#define RCC_MC_APB5LPENSETR_STGENLPEN BIT(20)
+#define RCC_MC_APB5LPENSETR_STGENSTPEN BIT(21)
+
+/* RCC_MC_APB5LPENCLRR register fields */
+#define RCC_MC_APB5LPENCLRR_SPI6LPEN BIT(0)
+#define RCC_MC_APB5LPENCLRR_I2C4LPEN BIT(2)
+#define RCC_MC_APB5LPENCLRR_I2C6LPEN BIT(3)
+#define RCC_MC_APB5LPENCLRR_USART1LPEN BIT(4)
+#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN BIT(8)
+#define RCC_MC_APB5LPENCLRR_TZC1LPEN BIT(11)
+#define RCC_MC_APB5LPENCLRR_TZC2LPEN BIT(12)
+#define RCC_MC_APB5LPENCLRR_TZPCLPEN BIT(13)
+#define RCC_MC_APB5LPENCLRR_BSECLPEN BIT(16)
+#define RCC_MC_APB5LPENCLRR_STGENLPEN BIT(20)
+#define RCC_MC_APB5LPENCLRR_STGENSTPEN BIT(21)
+
+/* RCC_MC_AHB5LPENSETR register fields */
+#define RCC_MC_AHB5LPENSETR_GPIOZLPEN BIT(0)
+#define RCC_MC_AHB5LPENSETR_CRYP1LPEN BIT(4)
+#define RCC_MC_AHB5LPENSETR_HASH1LPEN BIT(5)
+#define RCC_MC_AHB5LPENSETR_RNG1LPEN BIT(6)
+#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN BIT(8)
+
+/* RCC_MC_AHB5LPENCLRR register fields */
+#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN BIT(0)
+#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN BIT(4)
+#define RCC_MC_AHB5LPENCLRR_HASH1LPEN BIT(5)
+#define RCC_MC_AHB5LPENCLRR_RNG1LPEN BIT(6)
+#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN BIT(8)
+
+/* RCC_MC_AHB6LPENSETR register fields */
+#define RCC_MC_AHB6LPENSETR_MDMALPEN BIT(0)
+#define RCC_MC_AHB6LPENSETR_GPULPEN BIT(5)
+#define RCC_MC_AHB6LPENSETR_ETHCKLPEN BIT(7)
+#define RCC_MC_AHB6LPENSETR_ETHTXLPEN BIT(8)
+#define RCC_MC_AHB6LPENSETR_ETHRXLPEN BIT(9)
+#define RCC_MC_AHB6LPENSETR_ETHMACLPEN BIT(10)
+#define RCC_MC_AHB6LPENSETR_ETHSTPEN BIT(11)
+#define RCC_MC_AHB6LPENSETR_FMCLPEN BIT(12)
+#define RCC_MC_AHB6LPENSETR_QSPILPEN BIT(14)
+#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN BIT(16)
+#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN BIT(17)
+#define RCC_MC_AHB6LPENSETR_CRC1LPEN BIT(20)
+#define RCC_MC_AHB6LPENSETR_USBHLPEN BIT(24)
+
+/* RCC_MC_AHB6LPENCLRR register fields */
+#define RCC_MC_AHB6LPENCLRR_MDMALPEN BIT(0)
+#define RCC_MC_AHB6LPENCLRR_GPULPEN BIT(5)
+#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN BIT(7)
+#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN BIT(8)
+#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN BIT(9)
+#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN BIT(10)
+#define RCC_MC_AHB6LPENCLRR_ETHSTPEN BIT(11)
+#define RCC_MC_AHB6LPENCLRR_FMCLPEN BIT(12)
+#define RCC_MC_AHB6LPENCLRR_QSPILPEN BIT(14)
+#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN BIT(16)
+#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN BIT(17)
+#define RCC_MC_AHB6LPENCLRR_CRC1LPEN BIT(20)
+#define RCC_MC_AHB6LPENCLRR_USBHLPEN BIT(24)
+
+/* RCC_BR_RSTSCLRR register fields */
+#define RCC_BR_RSTSCLRR_PORRSTF BIT(0)
+#define RCC_BR_RSTSCLRR_BORRSTF BIT(1)
+#define RCC_BR_RSTSCLRR_PADRSTF BIT(2)
+#define RCC_BR_RSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_BR_RSTSCLRR_VCORERSTF BIT(4)
+#define RCC_BR_RSTSCLRR_MPSYSRSTF BIT(6)
+#define RCC_BR_RSTSCLRR_MCSYSRSTF BIT(7)
+#define RCC_BR_RSTSCLRR_IWDG1RSTF BIT(8)
+#define RCC_BR_RSTSCLRR_IWDG2RSTF BIT(9)
+#define RCC_BR_RSTSCLRR_MPUP0RSTF BIT(13)
+#define RCC_BR_RSTSCLRR_MPUP1RSTF BIT(14)
+
+/* RCC_MP_GRSTCSETR register fields */
+#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
+#define RCC_MP_GRSTCSETR_MCURST BIT(1)
+#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
+#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5)
+
+/* RCC_MP_RSTSCLRR register fields */
+#define RCC_MP_RSTSCLRR_PORRSTF BIT(0)
+#define RCC_MP_RSTSCLRR_BORRSTF BIT(1)
+#define RCC_MP_RSTSCLRR_PADRSTF BIT(2)
+#define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_MP_RSTSCLRR_VCORERSTF BIT(4)
+#define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6)
+#define RCC_MP_RSTSCLRR_MCSYSRSTF BIT(7)
+#define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8)
+#define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9)
+#define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11)
+#define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12)
+#define RCC_MP_RSTSCLRR_MPUP0RSTF BIT(13)
+#define RCC_MP_RSTSCLRR_MPUP1RSTF BIT(14)
+#define RCC_MP_RSTSCLRR_SPARE BIT(15)
+
+/* RCC_MP_IWDGFZSETR register fields */
+#define RCC_MP_IWDGFZSETR_FZ_IWDG1 BIT(0)
+#define RCC_MP_IWDGFZSETR_FZ_IWDG2 BIT(1)
+
+/* RCC_MP_IWDGFZCLRR register fields */
+#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 BIT(0)
+#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 BIT(1)
+
+/* RCC_MP_CIER register fields */
+#define RCC_MP_CIER_LSIRDYIE BIT(0)
+#define RCC_MP_CIER_LSERDYIE BIT(1)
+#define RCC_MP_CIER_HSIRDYIE BIT(2)
+#define RCC_MP_CIER_HSERDYIE BIT(3)
+#define RCC_MP_CIER_CSIRDYIE BIT(4)
+#define RCC_MP_CIER_PLL1DYIE BIT(8)
+#define RCC_MP_CIER_PLL2DYIE BIT(9)
+#define RCC_MP_CIER_PLL3DYIE BIT(10)
+#define RCC_MP_CIER_PLL4DYIE BIT(11)
+#define RCC_MP_CIER_LSECSSIE BIT(16)
+#define RCC_MP_CIER_WKUPIE BIT(20)
+
+/* RCC_MP_CIFR register fields */
+#define RCC_MP_CIFR_MASK U(0x110F1F)
+#define RCC_MP_CIFR_LSIRDYF BIT(0)
+#define RCC_MP_CIFR_LSERDYF BIT(1)
+#define RCC_MP_CIFR_HSIRDYF BIT(2)
+#define RCC_MP_CIFR_HSERDYF BIT(3)
+#define RCC_MP_CIFR_CSIRDYF BIT(4)
+#define RCC_MP_CIFR_PLL1DYF BIT(8)
+#define RCC_MP_CIFR_PLL2DYF BIT(9)
+#define RCC_MP_CIFR_PLL3DYF BIT(10)
+#define RCC_MP_CIFR_PLL4DYF BIT(11)
+#define RCC_MP_CIFR_LSECSSF BIT(16)
+#define RCC_MP_CIFR_WKUPF BIT(20)
+
+/* RCC_PWRLPDLYCR register fields */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0)
+#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0
+#define RCC_PWRLPDLYCR_MCTMPSKP BIT(24)
+
+/* RCC_MP_RSTSSETR register fields */
+#define RCC_MP_RSTSSETR_PORRSTF BIT(0)
+#define RCC_MP_RSTSSETR_BORRSTF BIT(1)
+#define RCC_MP_RSTSSETR_PADRSTF BIT(2)
+#define RCC_MP_RSTSSETR_HCSSRSTF BIT(3)
+#define RCC_MP_RSTSSETR_VCORERSTF BIT(4)
+#define RCC_MP_RSTSSETR_MPSYSRSTF BIT(6)
+#define RCC_MP_RSTSSETR_MCSYSRSTF BIT(7)
+#define RCC_MP_RSTSSETR_IWDG1RSTF BIT(8)
+#define RCC_MP_RSTSSETR_IWDG2RSTF BIT(9)
+#define RCC_MP_RSTSSETR_STDBYRSTF BIT(11)
+#define RCC_MP_RSTSSETR_CSTDBYRSTF BIT(12)
+#define RCC_MP_RSTSSETR_MPUP0RSTF BIT(13)
+#define RCC_MP_RSTSSETR_MPUP1RSTF BIT(14)
+#define RCC_MP_RSTSSETR_SPARE BIT(15)
+
+/* RCC_MCO1CFGR register fields */
+#define RCC_MCO1CFGR_MCO1SEL_MASK GENMASK(2, 0)
+#define RCC_MCO1CFGR_MCO1SEL_SHIFT 0
+#define RCC_MCO1CFGR_MCO1DIV_MASK GENMASK(7, 4)
+#define RCC_MCO1CFGR_MCO1DIV_SHIFT 4
+#define RCC_MCO1CFGR_MCO1ON BIT(12)
+
+/* RCC_MCO2CFGR register fields */
+#define RCC_MCO2CFGR_MCO2SEL_MASK GENMASK(2, 0)
+#define RCC_MCO2CFGR_MCO2SEL_SHIFT 0
+#define RCC_MCO2CFGR_MCO2DIV_MASK GENMASK(7, 4)
+#define RCC_MCO2CFGR_MCO2DIV_SHIFT 4
+#define RCC_MCO2CFGR_MCO2ON BIT(12)
+
+/* RCC_OCRDYR register fields */
+#define RCC_OCRDYR_HSIRDY BIT(0)
+#define RCC_OCRDYR_HSIDIVRDY BIT(2)
+#define RCC_OCRDYR_CSIRDY BIT(4)
+#define RCC_OCRDYR_HSERDY BIT(8)
+#define RCC_OCRDYR_MPUCKRDY BIT(23)
+#define RCC_OCRDYR_AXICKRDY BIT(24)
+#define RCC_OCRDYR_CKREST BIT(25)
+
+/* RCC_DBGCFGR register fields */
+#define RCC_DBGCFGR_TRACEDIV_MASK GENMASK(2, 0)
+#define RCC_DBGCFGR_TRACEDIV_SHIFT 0
+#define RCC_DBGCFGR_DBGCKEN BIT(8)
+#define RCC_DBGCFGR_TRACECKEN BIT(9)
+#define RCC_DBGCFGR_DBGRST BIT(12)
+
+/* RCC_RCK3SELR register fields */
+#define RCC_RCK3SELR_PLL3SRC_MASK GENMASK(1, 0)
+#define RCC_RCK3SELR_PLL3SRC_SHIFT 0
+#define RCC_RCK3SELR_PLL3SRCRDY BIT(31)
+
+/* RCC_RCK4SELR register fields */
+#define RCC_RCK4SELR_PLL4SRC_MASK GENMASK(1, 0)
+#define RCC_RCK4SELR_PLL4SRC_SHIFT 0
+#define RCC_RCK4SELR_PLL4SRCRDY BIT(31)
+
+/* RCC_TIMG1PRER register fields */
+#define RCC_TIMG1PRER_TIMG1PRE BIT(0)
+#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31)
+
+/* RCC_TIMG2PRER register fields */
+#define RCC_TIMG2PRER_TIMG2PRE BIT(0)
+#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31)
+
+/* RCC_MCUDIVR register fields */
+#define RCC_MCUDIVR_MCUDIV_MASK GENMASK(3, 0)
+#define RCC_MCUDIVR_MCUDIV_SHIFT 0
+#define RCC_MCUDIVR_MCUDIVRDY BIT(31)
+
+/* RCC_APB1DIVR register fields */
+#define RCC_APB1DIVR_APB1DIV_MASK GENMASK(2, 0)
+#define RCC_APB1DIVR_APB1DIV_SHIFT 0
+#define RCC_APB1DIVR_APB1DIVRDY BIT(31)
+
+/* RCC_APB2DIVR register fields */
+#define RCC_APB2DIVR_APB2DIV_MASK GENMASK(2, 0)
+#define RCC_APB2DIVR_APB2DIV_SHIFT 0
+#define RCC_APB2DIVR_APB2DIVRDY BIT(31)
+
+/* RCC_APB3DIVR register fields */
+#define RCC_APB3DIVR_APB3DIV_MASK GENMASK(2, 0)
+#define RCC_APB3DIVR_APB3DIV_SHIFT 0
+#define RCC_APB3DIVR_APB3DIVRDY BIT(31)
+
+/* RCC_PLL3CR register fields */
+#define RCC_PLL3CR_PLLON BIT(0)
+#define RCC_PLL3CR_PLL3RDY BIT(1)
+#define RCC_PLL3CR_SSCG_CTRL BIT(2)
+#define RCC_PLL3CR_DIVPEN BIT(4)
+#define RCC_PLL3CR_DIVQEN BIT(5)
+#define RCC_PLL3CR_DIVREN BIT(6)
+
+/* RCC_PLL3CFGR1 register fields */
+#define RCC_PLL3CFGR1_DIVN_MASK GENMASK(8, 0)
+#define RCC_PLL3CFGR1_DIVN_SHIFT 0
+#define RCC_PLL3CFGR1_DIVM3_MASK GENMASK(21, 16)
+#define RCC_PLL3CFGR1_DIVM3_SHIFT 16
+#define RCC_PLL3CFGR1_IFRGE_MASK GENMASK(25, 24)
+#define RCC_PLL3CFGR1_IFRGE_SHIFT 24
+
+/* RCC_PLL3CFGR2 register fields */
+#define RCC_PLL3CFGR2_DIVP_MASK GENMASK(6, 0)
+#define RCC_PLL3CFGR2_DIVP_SHIFT 0
+#define RCC_PLL3CFGR2_DIVQ_MASK GENMASK(14, 8)
+#define RCC_PLL3CFGR2_DIVQ_SHIFT 8
+#define RCC_PLL3CFGR2_DIVR_MASK GENMASK(22, 16)
+#define RCC_PLL3CFGR2_DIVR_SHIFT 16
+
+/* RCC_PLL3FRACR register fields */
+#define RCC_PLL3FRACR_FRACV_MASK GENMASK(15, 3)
+#define RCC_PLL3FRACR_FRACV_SHIFT 3
+#define RCC_PLL3FRACR_FRACLE BIT(16)
+
+/* RCC_PLL3CSGR register fields */
+#define RCC_PLL3CSGR_MOD_PER_MASK GENMASK(12, 0)
+#define RCC_PLL3CSGR_MOD_PER_SHIFT 0
+#define RCC_PLL3CSGR_TPDFN_DIS BIT(13)
+#define RCC_PLL3CSGR_RPDFN_DIS BIT(14)
+#define RCC_PLL3CSGR_SSCG_MODE BIT(15)
+#define RCC_PLL3CSGR_INC_STEP_MASK GENMASK(30, 16)
+#define RCC_PLL3CSGR_INC_STEP_SHIFT 16
+
+/* RCC_PLL4CR register fields */
+#define RCC_PLL4CR_PLLON BIT(0)
+#define RCC_PLL4CR_PLL4RDY BIT(1)
+#define RCC_PLL4CR_SSCG_CTRL BIT(2)
+#define RCC_PLL4CR_DIVPEN BIT(4)
+#define RCC_PLL4CR_DIVQEN BIT(5)
+#define RCC_PLL4CR_DIVREN BIT(6)
+
+/* RCC_PLL4CFGR1 register fields */
+#define RCC_PLL4CFGR1_DIVN_MASK GENMASK(8, 0)
+#define RCC_PLL4CFGR1_DIVN_SHIFT 0
+#define RCC_PLL4CFGR1_DIVM4_MASK GENMASK(21, 16)
+#define RCC_PLL4CFGR1_DIVM4_SHIFT 16
+#define RCC_PLL4CFGR1_IFRGE_MASK GENMASK(25, 24)
+#define RCC_PLL4CFGR1_IFRGE_SHIFT 24
+
+/* RCC_PLL4CFGR2 register fields */
+#define RCC_PLL4CFGR2_DIVP_MASK GENMASK(6, 0)
+#define RCC_PLL4CFGR2_DIVP_SHIFT 0
+#define RCC_PLL4CFGR2_DIVQ_MASK GENMASK(14, 8)
+#define RCC_PLL4CFGR2_DIVQ_SHIFT 8
+#define RCC_PLL4CFGR2_DIVR_MASK GENMASK(22, 16)
+#define RCC_PLL4CFGR2_DIVR_SHIFT 16
+
+/* RCC_PLL4FRACR register fields */
+#define RCC_PLL4FRACR_FRACV_MASK GENMASK(15, 3)
+#define RCC_PLL4FRACR_FRACV_SHIFT 3
+#define RCC_PLL4FRACR_FRACLE BIT(16)
+
+/* RCC_PLL4CSGR register fields */
+#define RCC_PLL4CSGR_MOD_PER_MASK GENMASK(12, 0)
+#define RCC_PLL4CSGR_MOD_PER_SHIFT 0
+#define RCC_PLL4CSGR_TPDFN_DIS BIT(13)
+#define RCC_PLL4CSGR_RPDFN_DIS BIT(14)
+#define RCC_PLL4CSGR_SSCG_MODE BIT(15)
+#define RCC_PLL4CSGR_INC_STEP_MASK GENMASK(30, 16)
+#define RCC_PLL4CSGR_INC_STEP_SHIFT 16
+
+/* RCC_I2C12CKSELR register fields */
+#define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0)
+#define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0
+
+/* RCC_I2C35CKSELR register fields */
+#define RCC_I2C35CKSELR_I2C35SRC_MASK GENMASK(2, 0)
+#define RCC_I2C35CKSELR_I2C35SRC_SHIFT 0
+
+/* RCC_SAI1CKSELR register fields */
+#define RCC_SAI1CKSELR_SAI1SRC_MASK GENMASK(2, 0)
+#define RCC_SAI1CKSELR_SAI1SRC_SHIFT 0
+
+/* RCC_SAI2CKSELR register fields */
+#define RCC_SAI2CKSELR_SAI2SRC_MASK GENMASK(2, 0)
+#define RCC_SAI2CKSELR_SAI2SRC_SHIFT 0
+
+/* RCC_SAI3CKSELR register fields */
+#define RCC_SAI3CKSELR_SAI3SRC_MASK GENMASK(2, 0)
+#define RCC_SAI3CKSELR_SAI3SRC_SHIFT 0
+
+/* RCC_SAI4CKSELR register fields */
+#define RCC_SAI4CKSELR_SAI4SRC_MASK GENMASK(2, 0)
+#define RCC_SAI4CKSELR_SAI4SRC_SHIFT 0
+
+/* RCC_SPI2S1CKSELR register fields */
+#define RCC_SPI2S1CKSELR_SPI1SRC_MASK GENMASK(2, 0)
+#define RCC_SPI2S1CKSELR_SPI1SRC_SHIFT 0
+
+/* RCC_SPI2S23CKSELR register fields */
+#define RCC_SPI2S23CKSELR_SPI23SRC_MASK GENMASK(2, 0)
+#define RCC_SPI2S23CKSELR_SPI23SRC_SHIFT 0
+
+/* RCC_SPI45CKSELR register fields */
+#define RCC_SPI45CKSELR_SPI45SRC_MASK GENMASK(2, 0)
+#define RCC_SPI45CKSELR_SPI45SRC_SHIFT 0
+
+/* RCC_UART6CKSELR register fields */
+#define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0)
+#define RCC_UART6CKSELR_UART6SRC_SHIFT 0
+
+/* RCC_UART24CKSELR register fields */
+#define RCC_UART24CKSELR_HSI 0x00000002
+#define RCC_UART24CKSELR_UART24SRC_MASK GENMASK(2, 0)
+#define RCC_UART24CKSELR_UART24SRC_SHIFT 0
+
+/* RCC_UART35CKSELR register fields */
+#define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0)
+#define RCC_UART35CKSELR_UART35SRC_SHIFT 0
+
+/* RCC_UART78CKSELR register fields */
+#define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0)
+#define RCC_UART78CKSELR_UART78SRC_SHIFT 0
+
+/* RCC_SDMMC12CKSELR register fields */
+#define RCC_SDMMC12CKSELR_SDMMC12SRC_MASK GENMASK(2, 0)
+#define RCC_SDMMC12CKSELR_SDMMC12SRC_SHIFT 0
+
+/* RCC_SDMMC3CKSELR register fields */
+#define RCC_SDMMC3CKSELR_SDMMC3SRC_MASK GENMASK(2, 0)
+#define RCC_SDMMC3CKSELR_SDMMC3SRC_SHIFT 0
+
+/* RCC_ETHCKSELR register fields */
+#define RCC_ETHCKSELR_ETHSRC_MASK GENMASK(1, 0)
+#define RCC_ETHCKSELR_ETHSRC_SHIFT 0
+#define RCC_ETHCKSELR_ETHPTPDIV_MASK GENMASK(7, 4)
+#define RCC_ETHCKSELR_ETHPTPDIV_SHIFT 4
+
+/* RCC_QSPICKSELR register fields */
+#define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0)
+#define RCC_QSPICKSELR_QSPISRC_SHIFT 0
+
+/* RCC_FMCCKSELR register fields */
+#define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0)
+#define RCC_FMCCKSELR_FMCSRC_SHIFT 0
+
+/* RCC_FDCANCKSELR register fields */
+#define RCC_FDCANCKSELR_FDCANSRC_MASK GENMASK(1, 0)
+#define RCC_FDCANCKSELR_FDCANSRC_SHIFT 0
+
+/* RCC_SPDIFCKSELR register fields */
+#define RCC_SPDIFCKSELR_SPDIFSRC_MASK GENMASK(1, 0)
+#define RCC_SPDIFCKSELR_SPDIFSRC_SHIFT 0
+
+/* RCC_CECCKSELR register fields */
+#define RCC_CECCKSELR_CECSRC_MASK GENMASK(1, 0)
+#define RCC_CECCKSELR_CECSRC_SHIFT 0
+
+/* RCC_USBCKSELR register fields */
+#define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0)
+#define RCC_USBCKSELR_USBPHYSRC_SHIFT 0
+#define RCC_USBCKSELR_USBOSRC BIT(4)
+#define RCC_USBCKSELR_USBOSRC_MASK BIT(4)
+#define RCC_USBCKSELR_USBOSRC_SHIFT 4
+
+/* RCC_RNG2CKSELR register fields */
+#define RCC_RNG2CKSELR_RNG2SRC_MASK GENMASK(1, 0)
+#define RCC_RNG2CKSELR_RNG2SRC_SHIFT 0
+
+/* RCC_DSICKSELR register fields */
+#define RCC_DSICKSELR_DSISRC BIT(0)
+
+/* RCC_ADCCKSELR register fields */
+#define RCC_ADCCKSELR_ADCSRC_MASK GENMASK(1, 0)
+#define RCC_ADCCKSELR_ADCSRC_SHIFT 0
+
+/* RCC_LPTIM45CKSELR register fields */
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_MASK GENMASK(2, 0)
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_SHIFT 0
+
+/* RCC_LPTIM23CKSELR register fields */
+#define RCC_LPTIM23CKSELR_LPTIM23SRC_MASK GENMASK(2, 0)
+#define RCC_LPTIM23CKSELR_LPTIM23SRC_SHIFT 0
+
+/* RCC_LPTIM1CKSELR register fields */
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_MASK GENMASK(2, 0)
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_SHIFT 0
+
+/* RCC_APB1RSTSETR register fields */
+#define RCC_APB1RSTSETR_TIM2RST BIT(0)
+#define RCC_APB1RSTSETR_TIM3RST BIT(1)
+#define RCC_APB1RSTSETR_TIM4RST BIT(2)
+#define RCC_APB1RSTSETR_TIM5RST BIT(3)
+#define RCC_APB1RSTSETR_TIM6RST BIT(4)
+#define RCC_APB1RSTSETR_TIM7RST BIT(5)
+#define RCC_APB1RSTSETR_TIM12RST BIT(6)
+#define RCC_APB1RSTSETR_TIM13RST BIT(7)
+#define RCC_APB1RSTSETR_TIM14RST BIT(8)
+#define RCC_APB1RSTSETR_LPTIM1RST BIT(9)
+#define RCC_APB1RSTSETR_SPI2RST BIT(11)
+#define RCC_APB1RSTSETR_SPI3RST BIT(12)
+#define RCC_APB1RSTSETR_USART2RST BIT(14)
+#define RCC_APB1RSTSETR_USART3RST BIT(15)
+#define RCC_APB1RSTSETR_UART4RST BIT(16)
+#define RCC_APB1RSTSETR_UART5RST BIT(17)
+#define RCC_APB1RSTSETR_UART7RST BIT(18)
+#define RCC_APB1RSTSETR_UART8RST BIT(19)
+#define RCC_APB1RSTSETR_I2C1RST BIT(21)
+#define RCC_APB1RSTSETR_I2C2RST BIT(22)
+#define RCC_APB1RSTSETR_I2C3RST BIT(23)
+#define RCC_APB1RSTSETR_I2C5RST BIT(24)
+#define RCC_APB1RSTSETR_SPDIFRST BIT(26)
+#define RCC_APB1RSTSETR_CECRST BIT(27)
+#define RCC_APB1RSTSETR_DAC12RST BIT(29)
+#define RCC_APB1RSTSETR_MDIOSRST BIT(31)
+
+/* RCC_APB1RSTCLRR register fields */
+#define RCC_APB1RSTCLRR_TIM2RST BIT(0)
+#define RCC_APB1RSTCLRR_TIM3RST BIT(1)
+#define RCC_APB1RSTCLRR_TIM4RST BIT(2)
+#define RCC_APB1RSTCLRR_TIM5RST BIT(3)
+#define RCC_APB1RSTCLRR_TIM6RST BIT(4)
+#define RCC_APB1RSTCLRR_TIM7RST BIT(5)
+#define RCC_APB1RSTCLRR_TIM12RST BIT(6)
+#define RCC_APB1RSTCLRR_TIM13RST BIT(7)
+#define RCC_APB1RSTCLRR_TIM14RST BIT(8)
+#define RCC_APB1RSTCLRR_LPTIM1RST BIT(9)
+#define RCC_APB1RSTCLRR_SPI2RST BIT(11)
+#define RCC_APB1RSTCLRR_SPI3RST BIT(12)
+#define RCC_APB1RSTCLRR_USART2RST BIT(14)
+#define RCC_APB1RSTCLRR_USART3RST BIT(15)
+#define RCC_APB1RSTCLRR_UART4RST BIT(16)
+#define RCC_APB1RSTCLRR_UART5RST BIT(17)
+#define RCC_APB1RSTCLRR_UART7RST BIT(18)
+#define RCC_APB1RSTCLRR_UART8RST BIT(19)
+#define RCC_APB1RSTCLRR_I2C1RST BIT(21)
+#define RCC_APB1RSTCLRR_I2C2RST BIT(22)
+#define RCC_APB1RSTCLRR_I2C3RST BIT(23)
+#define RCC_APB1RSTCLRR_I2C5RST BIT(24)
+#define RCC_APB1RSTCLRR_SPDIFRST BIT(26)
+#define RCC_APB1RSTCLRR_CECRST BIT(27)
+#define RCC_APB1RSTCLRR_DAC12RST BIT(29)
+#define RCC_APB1RSTCLRR_MDIOSRST BIT(31)
+
+/* RCC_APB2RSTSETR register fields */
+#define RCC_APB2RSTSETR_TIM1RST BIT(0)
+#define RCC_APB2RSTSETR_TIM8RST BIT(1)
+#define RCC_APB2RSTSETR_TIM15RST BIT(2)
+#define RCC_APB2RSTSETR_TIM16RST BIT(3)
+#define RCC_APB2RSTSETR_TIM17RST BIT(4)
+#define RCC_APB2RSTSETR_SPI1RST BIT(8)
+#define RCC_APB2RSTSETR_SPI4RST BIT(9)
+#define RCC_APB2RSTSETR_SPI5RST BIT(10)
+#define RCC_APB2RSTSETR_USART6RST BIT(13)
+#define RCC_APB2RSTSETR_SAI1RST BIT(16)
+#define RCC_APB2RSTSETR_SAI2RST BIT(17)
+#define RCC_APB2RSTSETR_SAI3RST BIT(18)
+#define RCC_APB2RSTSETR_DFSDMRST BIT(20)
+#define RCC_APB2RSTSETR_FDCANRST BIT(24)
+
+/* RCC_APB2RSTCLRR register fields */
+#define RCC_APB2RSTCLRR_TIM1RST BIT(0)
+#define RCC_APB2RSTCLRR_TIM8RST BIT(1)
+#define RCC_APB2RSTCLRR_TIM15RST BIT(2)
+#define RCC_APB2RSTCLRR_TIM16RST BIT(3)
+#define RCC_APB2RSTCLRR_TIM17RST BIT(4)
+#define RCC_APB2RSTCLRR_SPI1RST BIT(8)
+#define RCC_APB2RSTCLRR_SPI4RST BIT(9)
+#define RCC_APB2RSTCLRR_SPI5RST BIT(10)
+#define RCC_APB2RSTCLRR_USART6RST BIT(13)
+#define RCC_APB2RSTCLRR_SAI1RST BIT(16)
+#define RCC_APB2RSTCLRR_SAI2RST BIT(17)
+#define RCC_APB2RSTCLRR_SAI3RST BIT(18)
+#define RCC_APB2RSTCLRR_DFSDMRST BIT(20)
+#define RCC_APB2RSTCLRR_FDCANRST BIT(24)
+
+/* RCC_APB3RSTSETR register fields */
+#define RCC_APB3RSTSETR_LPTIM2RST BIT(0)
+#define RCC_APB3RSTSETR_LPTIM3RST BIT(1)
+#define RCC_APB3RSTSETR_LPTIM4RST BIT(2)
+#define RCC_APB3RSTSETR_LPTIM5RST BIT(3)
+#define RCC_APB3RSTSETR_SAI4RST BIT(8)
+#define RCC_APB3RSTSETR_SYSCFGRST BIT(11)
+#define RCC_APB3RSTSETR_VREFRST BIT(13)
+#define RCC_APB3RSTSETR_TMPSENSRST BIT(16)
+#define RCC_APB3RSTSETR_PMBCTRLRST BIT(17)
+
+/* RCC_APB3RSTCLRR register fields */
+#define RCC_APB3RSTCLRR_LPTIM2RST BIT(0)
+#define RCC_APB3RSTCLRR_LPTIM3RST BIT(1)
+#define RCC_APB3RSTCLRR_LPTIM4RST BIT(2)
+#define RCC_APB3RSTCLRR_LPTIM5RST BIT(3)
+#define RCC_APB3RSTCLRR_SAI4RST BIT(8)
+#define RCC_APB3RSTCLRR_SYSCFGRST BIT(11)
+#define RCC_APB3RSTCLRR_VREFRST BIT(13)
+#define RCC_APB3RSTCLRR_TMPSENSRST BIT(16)
+#define RCC_APB3RSTCLRR_PMBCTRLRST BIT(17)
+
+/* RCC_AHB2RSTSETR register fields */
+#define RCC_AHB2RSTSETR_DMA1RST BIT(0)
+#define RCC_AHB2RSTSETR_DMA2RST BIT(1)
+#define RCC_AHB2RSTSETR_DMAMUXRST BIT(2)
+#define RCC_AHB2RSTSETR_ADC12RST BIT(5)
+#define RCC_AHB2RSTSETR_USBORST BIT(8)
+#define RCC_AHB2RSTSETR_SDMMC3RST BIT(16)
+
+/* RCC_AHB2RSTCLRR register fields */
+#define RCC_AHB2RSTCLRR_DMA1RST BIT(0)
+#define RCC_AHB2RSTCLRR_DMA2RST BIT(1)
+#define RCC_AHB2RSTCLRR_DMAMUXRST BIT(2)
+#define RCC_AHB2RSTCLRR_ADC12RST BIT(5)
+#define RCC_AHB2RSTCLRR_USBORST BIT(8)
+#define RCC_AHB2RSTCLRR_SDMMC3RST BIT(16)
+
+/* RCC_AHB3RSTSETR register fields */
+#define RCC_AHB3RSTSETR_DCMIRST BIT(0)
+#define RCC_AHB3RSTSETR_CRYP2RST BIT(4)
+#define RCC_AHB3RSTSETR_HASH2RST BIT(5)
+#define RCC_AHB3RSTSETR_RNG2RST BIT(6)
+#define RCC_AHB3RSTSETR_CRC2RST BIT(7)
+#define RCC_AHB3RSTSETR_HSEMRST BIT(11)
+#define RCC_AHB3RSTSETR_IPCCRST BIT(12)
+
+/* RCC_AHB3RSTCLRR register fields */
+#define RCC_AHB3RSTCLRR_DCMIRST BIT(0)
+#define RCC_AHB3RSTCLRR_CRYP2RST BIT(4)
+#define RCC_AHB3RSTCLRR_HASH2RST BIT(5)
+#define RCC_AHB3RSTCLRR_RNG2RST BIT(6)
+#define RCC_AHB3RSTCLRR_CRC2RST BIT(7)
+#define RCC_AHB3RSTCLRR_HSEMRST BIT(11)
+#define RCC_AHB3RSTCLRR_IPCCRST BIT(12)
+
+/* RCC_AHB4RSTSETR register fields */
+#define RCC_AHB4RSTSETR_GPIOARST BIT(0)
+#define RCC_AHB4RSTSETR_GPIOBRST BIT(1)
+#define RCC_AHB4RSTSETR_GPIOCRST BIT(2)
+#define RCC_AHB4RSTSETR_GPIODRST BIT(3)
+#define RCC_AHB4RSTSETR_GPIOERST BIT(4)
+#define RCC_AHB4RSTSETR_GPIOFRST BIT(5)
+#define RCC_AHB4RSTSETR_GPIOGRST BIT(6)
+#define RCC_AHB4RSTSETR_GPIOHRST BIT(7)
+#define RCC_AHB4RSTSETR_GPIOIRST BIT(8)
+#define RCC_AHB4RSTSETR_GPIOJRST BIT(9)
+#define RCC_AHB4RSTSETR_GPIOKRST BIT(10)
+
+/* RCC_AHB4RSTCLRR register fields */
+#define RCC_AHB4RSTCLRR_GPIOARST BIT(0)
+#define RCC_AHB4RSTCLRR_GPIOBRST BIT(1)
+#define RCC_AHB4RSTCLRR_GPIOCRST BIT(2)
+#define RCC_AHB4RSTCLRR_GPIODRST BIT(3)
+#define RCC_AHB4RSTCLRR_GPIOERST BIT(4)
+#define RCC_AHB4RSTCLRR_GPIOFRST BIT(5)
+#define RCC_AHB4RSTCLRR_GPIOGRST BIT(6)
+#define RCC_AHB4RSTCLRR_GPIOHRST BIT(7)
+#define RCC_AHB4RSTCLRR_GPIOIRST BIT(8)
+#define RCC_AHB4RSTCLRR_GPIOJRST BIT(9)
+#define RCC_AHB4RSTCLRR_GPIOKRST BIT(10)
+
+/* RCC_MP_APB1ENSETR register fields */
+#define RCC_MP_APB1ENSETR_TIM2EN BIT(0)
+#define RCC_MP_APB1ENSETR_TIM3EN BIT(1)
+#define RCC_MP_APB1ENSETR_TIM4EN BIT(2)
+#define RCC_MP_APB1ENSETR_TIM5EN BIT(3)
+#define RCC_MP_APB1ENSETR_TIM6EN BIT(4)
+#define RCC_MP_APB1ENSETR_TIM7EN BIT(5)
+#define RCC_MP_APB1ENSETR_TIM12EN BIT(6)
+#define RCC_MP_APB1ENSETR_TIM13EN BIT(7)
+#define RCC_MP_APB1ENSETR_TIM14EN BIT(8)
+#define RCC_MP_APB1ENSETR_LPTIM1EN BIT(9)
+#define RCC_MP_APB1ENSETR_SPI2EN BIT(11)
+#define RCC_MP_APB1ENSETR_SPI3EN BIT(12)
+#define RCC_MP_APB1ENSETR_USART2EN BIT(14)
+#define RCC_MP_APB1ENSETR_USART3EN BIT(15)
+#define RCC_MP_APB1ENSETR_UART4EN BIT(16)
+#define RCC_MP_APB1ENSETR_UART5EN BIT(17)
+#define RCC_MP_APB1ENSETR_UART7EN BIT(18)
+#define RCC_MP_APB1ENSETR_UART8EN BIT(19)
+#define RCC_MP_APB1ENSETR_I2C1EN BIT(21)
+#define RCC_MP_APB1ENSETR_I2C2EN BIT(22)
+#define RCC_MP_APB1ENSETR_I2C3EN BIT(23)
+#define RCC_MP_APB1ENSETR_I2C5EN BIT(24)
+#define RCC_MP_APB1ENSETR_SPDIFEN BIT(26)
+#define RCC_MP_APB1ENSETR_CECEN BIT(27)
+#define RCC_MP_APB1ENSETR_DAC12EN BIT(29)
+#define RCC_MP_APB1ENSETR_MDIOSEN BIT(31)
+
+/* RCC_MP_APB1ENCLRR register fields */
+#define RCC_MP_APB1ENCLRR_TIM2EN BIT(0)
+#define RCC_MP_APB1ENCLRR_TIM3EN BIT(1)
+#define RCC_MP_APB1ENCLRR_TIM4EN BIT(2)
+#define RCC_MP_APB1ENCLRR_TIM5EN BIT(3)
+#define RCC_MP_APB1ENCLRR_TIM6EN BIT(4)
+#define RCC_MP_APB1ENCLRR_TIM7EN BIT(5)
+#define RCC_MP_APB1ENCLRR_TIM12EN BIT(6)
+#define RCC_MP_APB1ENCLRR_TIM13EN BIT(7)
+#define RCC_MP_APB1ENCLRR_TIM14EN BIT(8)
+#define RCC_MP_APB1ENCLRR_LPTIM1EN BIT(9)
+#define RCC_MP_APB1ENCLRR_SPI2EN BIT(11)
+#define RCC_MP_APB1ENCLRR_SPI3EN BIT(12)
+#define RCC_MP_APB1ENCLRR_USART2EN BIT(14)
+#define RCC_MP_APB1ENCLRR_USART3EN BIT(15)
+#define RCC_MP_APB1ENCLRR_UART4EN BIT(16)
+#define RCC_MP_APB1ENCLRR_UART5EN BIT(17)
+#define RCC_MP_APB1ENCLRR_UART7EN BIT(18)
+#define RCC_MP_APB1ENCLRR_UART8EN BIT(19)
+#define RCC_MP_APB1ENCLRR_I2C1EN BIT(21)
+#define RCC_MP_APB1ENCLRR_I2C2EN BIT(22)
+#define RCC_MP_APB1ENCLRR_I2C3EN BIT(23)
+#define RCC_MP_APB1ENCLRR_I2C5EN BIT(24)
+#define RCC_MP_APB1ENCLRR_SPDIFEN BIT(26)
+#define RCC_MP_APB1ENCLRR_CECEN BIT(27)
+#define RCC_MP_APB1ENCLRR_DAC12EN BIT(29)
+#define RCC_MP_APB1ENCLRR_MDIOSEN BIT(31)
+
+/* RCC_MP_APB2ENSETR register fields */
+#define RCC_MP_APB2ENSETR_TIM1EN BIT(0)
+#define RCC_MP_APB2ENSETR_TIM8EN BIT(1)
+#define RCC_MP_APB2ENSETR_TIM15EN BIT(2)
+#define RCC_MP_APB2ENSETR_TIM16EN BIT(3)
+#define RCC_MP_APB2ENSETR_TIM17EN BIT(4)
+#define RCC_MP_APB2ENSETR_SPI1EN BIT(8)
+#define RCC_MP_APB2ENSETR_SPI4EN BIT(9)
+#define RCC_MP_APB2ENSETR_SPI5EN BIT(10)
+#define RCC_MP_APB2ENSETR_USART6EN BIT(13)
+#define RCC_MP_APB2ENSETR_SAI1EN BIT(16)
+#define RCC_MP_APB2ENSETR_SAI2EN BIT(17)
+#define RCC_MP_APB2ENSETR_SAI3EN BIT(18)
+#define RCC_MP_APB2ENSETR_DFSDMEN BIT(20)
+#define RCC_MP_APB2ENSETR_ADFSDMEN BIT(21)
+#define RCC_MP_APB2ENSETR_FDCANEN BIT(24)
+
+/* RCC_MP_APB2ENCLRR register fields */
+#define RCC_MP_APB2ENCLRR_TIM1EN BIT(0)
+#define RCC_MP_APB2ENCLRR_TIM8EN BIT(1)
+#define RCC_MP_APB2ENCLRR_TIM15EN BIT(2)
+#define RCC_MP_APB2ENCLRR_TIM16EN BIT(3)
+#define RCC_MP_APB2ENCLRR_TIM17EN BIT(4)
+#define RCC_MP_APB2ENCLRR_SPI1EN BIT(8)
+#define RCC_MP_APB2ENCLRR_SPI4EN BIT(9)
+#define RCC_MP_APB2ENCLRR_SPI5EN BIT(10)
+#define RCC_MP_APB2ENCLRR_USART6EN BIT(13)
+#define RCC_MP_APB2ENCLRR_SAI1EN BIT(16)
+#define RCC_MP_APB2ENCLRR_SAI2EN BIT(17)
+#define RCC_MP_APB2ENCLRR_SAI3EN BIT(18)
+#define RCC_MP_APB2ENCLRR_DFSDMEN BIT(20)
+#define RCC_MP_APB2ENCLRR_ADFSDMEN BIT(21)
+#define RCC_MP_APB2ENCLRR_FDCANEN BIT(24)
+
+/* RCC_MP_APB3ENSETR register fields */
+#define RCC_MP_APB3ENSETR_LPTIM2EN BIT(0)
+#define RCC_MP_APB3ENSETR_LPTIM3EN BIT(1)
+#define RCC_MP_APB3ENSETR_LPTIM4EN BIT(2)
+#define RCC_MP_APB3ENSETR_LPTIM5EN BIT(3)
+#define RCC_MP_APB3ENSETR_SAI4EN BIT(8)
+#define RCC_MP_APB3ENSETR_SYSCFGEN BIT(11)
+#define RCC_MP_APB3ENSETR_VREFEN BIT(13)
+#define RCC_MP_APB3ENSETR_TMPSENSEN BIT(16)
+#define RCC_MP_APB3ENSETR_PMBCTRLEN BIT(17)
+#define RCC_MP_APB3ENSETR_HDPEN BIT(20)
+
+/* RCC_MP_APB3ENCLRR register fields */
+#define RCC_MP_APB3ENCLRR_LPTIM2EN BIT(0)
+#define RCC_MP_APB3ENCLRR_LPTIM3EN BIT(1)
+#define RCC_MP_APB3ENCLRR_LPTIM4EN BIT(2)
+#define RCC_MP_APB3ENCLRR_LPTIM5EN BIT(3)
+#define RCC_MP_APB3ENCLRR_SAI4EN BIT(8)
+#define RCC_MP_APB3ENCLRR_SYSCFGEN BIT(11)
+#define RCC_MP_APB3ENCLRR_VREFEN BIT(13)
+#define RCC_MP_APB3ENCLRR_TMPSENSEN BIT(16)
+#define RCC_MP_APB3ENCLRR_PMBCTRLEN BIT(17)
+#define RCC_MP_APB3ENCLRR_HDPEN BIT(20)
+
+/* RCC_MP_AHB2ENSETR register fields */
+#define RCC_MP_AHB2ENSETR_DMA1EN BIT(0)
+#define RCC_MP_AHB2ENSETR_DMA2EN BIT(1)
+#define RCC_MP_AHB2ENSETR_DMAMUXEN BIT(2)
+#define RCC_MP_AHB2ENSETR_ADC12EN BIT(5)
+#define RCC_MP_AHB2ENSETR_USBOEN BIT(8)
+#define RCC_MP_AHB2ENSETR_SDMMC3EN BIT(16)
+
+/* RCC_MP_AHB2ENCLRR register fields */
+#define RCC_MP_AHB2ENCLRR_DMA1EN BIT(0)
+#define RCC_MP_AHB2ENCLRR_DMA2EN BIT(1)
+#define RCC_MP_AHB2ENCLRR_DMAMUXEN BIT(2)
+#define RCC_MP_AHB2ENCLRR_ADC12EN BIT(5)
+#define RCC_MP_AHB2ENCLRR_USBOEN BIT(8)
+#define RCC_MP_AHB2ENCLRR_SDMMC3EN BIT(16)
+
+/* RCC_MP_AHB3ENSETR register fields */
+#define RCC_MP_AHB3ENSETR_DCMIEN BIT(0)
+#define RCC_MP_AHB3ENSETR_CRYP2EN BIT(4)
+#define RCC_MP_AHB3ENSETR_HASH2EN BIT(5)
+#define RCC_MP_AHB3ENSETR_RNG2EN BIT(6)
+#define RCC_MP_AHB3ENSETR_CRC2EN BIT(7)
+#define RCC_MP_AHB3ENSETR_HSEMEN BIT(11)
+#define RCC_MP_AHB3ENSETR_IPCCEN BIT(12)
+
+/* RCC_MP_AHB3ENCLRR register fields */
+#define RCC_MP_AHB3ENCLRR_DCMIEN BIT(0)
+#define RCC_MP_AHB3ENCLRR_CRYP2EN BIT(4)
+#define RCC_MP_AHB3ENCLRR_HASH2EN BIT(5)
+#define RCC_MP_AHB3ENCLRR_RNG2EN BIT(6)
+#define RCC_MP_AHB3ENCLRR_CRC2EN BIT(7)
+#define RCC_MP_AHB3ENCLRR_HSEMEN BIT(11)
+#define RCC_MP_AHB3ENCLRR_IPCCEN BIT(12)
+
+/* RCC_MP_AHB4ENSETR register fields */
+#define RCC_MP_AHB4ENSETR_GPIOAEN BIT(0)
+#define RCC_MP_AHB4ENSETR_GPIOBEN BIT(1)
+#define RCC_MP_AHB4ENSETR_GPIOCEN BIT(2)
+#define RCC_MP_AHB4ENSETR_GPIODEN BIT(3)
+#define RCC_MP_AHB4ENSETR_GPIOEEN BIT(4)
+#define RCC_MP_AHB4ENSETR_GPIOFEN BIT(5)
+#define RCC_MP_AHB4ENSETR_GPIOGEN BIT(6)
+#define RCC_MP_AHB4ENSETR_GPIOHEN BIT(7)
+#define RCC_MP_AHB4ENSETR_GPIOIEN BIT(8)
+#define RCC_MP_AHB4ENSETR_GPIOJEN BIT(9)
+#define RCC_MP_AHB4ENSETR_GPIOKEN BIT(10)
+
+/* RCC_MP_AHB4ENCLRR register fields */
+#define RCC_MP_AHB4ENCLRR_GPIOAEN BIT(0)
+#define RCC_MP_AHB4ENCLRR_GPIOBEN BIT(1)
+#define RCC_MP_AHB4ENCLRR_GPIOCEN BIT(2)
+#define RCC_MP_AHB4ENCLRR_GPIODEN BIT(3)
+#define RCC_MP_AHB4ENCLRR_GPIOEEN BIT(4)
+#define RCC_MP_AHB4ENCLRR_GPIOFEN BIT(5)
+#define RCC_MP_AHB4ENCLRR_GPIOGEN BIT(6)
+#define RCC_MP_AHB4ENCLRR_GPIOHEN BIT(7)
+#define RCC_MP_AHB4ENCLRR_GPIOIEN BIT(8)
+#define RCC_MP_AHB4ENCLRR_GPIOJEN BIT(9)
+#define RCC_MP_AHB4ENCLRR_GPIOKEN BIT(10)
+
+/* RCC_MP_MLAHBENSETR register fields */
+#define RCC_MP_MLAHBENSETR_RETRAMEN BIT(4)
+
+/* RCC_MP_MLAHBENCLRR register fields */
+#define RCC_MP_MLAHBENCLRR_RETRAMEN BIT(4)
+
+/* RCC_MC_APB1ENSETR register fields */
+#define RCC_MC_APB1ENSETR_TIM2EN BIT(0)
+#define RCC_MC_APB1ENSETR_TIM3EN BIT(1)
+#define RCC_MC_APB1ENSETR_TIM4EN BIT(2)
+#define RCC_MC_APB1ENSETR_TIM5EN BIT(3)
+#define RCC_MC_APB1ENSETR_TIM6EN BIT(4)
+#define RCC_MC_APB1ENSETR_TIM7EN BIT(5)
+#define RCC_MC_APB1ENSETR_TIM12EN BIT(6)
+#define RCC_MC_APB1ENSETR_TIM13EN BIT(7)
+#define RCC_MC_APB1ENSETR_TIM14EN BIT(8)
+#define RCC_MC_APB1ENSETR_LPTIM1EN BIT(9)
+#define RCC_MC_APB1ENSETR_SPI2EN BIT(11)
+#define RCC_MC_APB1ENSETR_SPI3EN BIT(12)
+#define RCC_MC_APB1ENSETR_USART2EN BIT(14)
+#define RCC_MC_APB1ENSETR_USART3EN BIT(15)
+#define RCC_MC_APB1ENSETR_UART4EN BIT(16)
+#define RCC_MC_APB1ENSETR_UART5EN BIT(17)
+#define RCC_MC_APB1ENSETR_UART7EN BIT(18)
+#define RCC_MC_APB1ENSETR_UART8EN BIT(19)
+#define RCC_MC_APB1ENSETR_I2C1EN BIT(21)
+#define RCC_MC_APB1ENSETR_I2C2EN BIT(22)
+#define RCC_MC_APB1ENSETR_I2C3EN BIT(23)
+#define RCC_MC_APB1ENSETR_I2C5EN BIT(24)
+#define RCC_MC_APB1ENSETR_SPDIFEN BIT(26)
+#define RCC_MC_APB1ENSETR_CECEN BIT(27)
+#define RCC_MC_APB1ENSETR_WWDG1EN BIT(28)
+#define RCC_MC_APB1ENSETR_DAC12EN BIT(29)
+#define RCC_MC_APB1ENSETR_MDIOSEN BIT(31)
+
+/* RCC_MC_APB1ENCLRR register fields */
+#define RCC_MC_APB1ENCLRR_TIM2EN BIT(0)
+#define RCC_MC_APB1ENCLRR_TIM3EN BIT(1)
+#define RCC_MC_APB1ENCLRR_TIM4EN BIT(2)
+#define RCC_MC_APB1ENCLRR_TIM5EN BIT(3)
+#define RCC_MC_APB1ENCLRR_TIM6EN BIT(4)
+#define RCC_MC_APB1ENCLRR_TIM7EN BIT(5)
+#define RCC_MC_APB1ENCLRR_TIM12EN BIT(6)
+#define RCC_MC_APB1ENCLRR_TIM13EN BIT(7)
+#define RCC_MC_APB1ENCLRR_TIM14EN BIT(8)
+#define RCC_MC_APB1ENCLRR_LPTIM1EN BIT(9)
+#define RCC_MC_APB1ENCLRR_SPI2EN BIT(11)
+#define RCC_MC_APB1ENCLRR_SPI3EN BIT(12)
+#define RCC_MC_APB1ENCLRR_USART2EN BIT(14)
+#define RCC_MC_APB1ENCLRR_USART3EN BIT(15)
+#define RCC_MC_APB1ENCLRR_UART4EN BIT(16)
+#define RCC_MC_APB1ENCLRR_UART5EN BIT(17)
+#define RCC_MC_APB1ENCLRR_UART7EN BIT(18)
+#define RCC_MC_APB1ENCLRR_UART8EN BIT(19)
+#define RCC_MC_APB1ENCLRR_I2C1EN BIT(21)
+#define RCC_MC_APB1ENCLRR_I2C2EN BIT(22)
+#define RCC_MC_APB1ENCLRR_I2C3EN BIT(23)
+#define RCC_MC_APB1ENCLRR_I2C5EN BIT(24)
+#define RCC_MC_APB1ENCLRR_SPDIFEN BIT(26)
+#define RCC_MC_APB1ENCLRR_CECEN BIT(27)
+#define RCC_MC_APB1ENCLRR_DAC12EN BIT(29)
+#define RCC_MC_APB1ENCLRR_MDIOSEN BIT(31)
+
+/* RCC_MC_APB2ENSETR register fields */
+#define RCC_MC_APB2ENSETR_TIM1EN BIT(0)
+#define RCC_MC_APB2ENSETR_TIM8EN BIT(1)
+#define RCC_MC_APB2ENSETR_TIM15EN BIT(2)
+#define RCC_MC_APB2ENSETR_TIM16EN BIT(3)
+#define RCC_MC_APB2ENSETR_TIM17EN BIT(4)
+#define RCC_MC_APB2ENSETR_SPI1EN BIT(8)
+#define RCC_MC_APB2ENSETR_SPI4EN BIT(9)
+#define RCC_MC_APB2ENSETR_SPI5EN BIT(10)
+#define RCC_MC_APB2ENSETR_USART6EN BIT(13)
+#define RCC_MC_APB2ENSETR_SAI1EN BIT(16)
+#define RCC_MC_APB2ENSETR_SAI2EN BIT(17)
+#define RCC_MC_APB2ENSETR_SAI3EN BIT(18)
+#define RCC_MC_APB2ENSETR_DFSDMEN BIT(20)
+#define RCC_MC_APB2ENSETR_ADFSDMEN BIT(21)
+#define RCC_MC_APB2ENSETR_FDCANEN BIT(24)
+
+/* RCC_MC_APB2ENCLRR register fields */
+#define RCC_MC_APB2ENCLRR_TIM1EN BIT(0)
+#define RCC_MC_APB2ENCLRR_TIM8EN BIT(1)
+#define RCC_MC_APB2ENCLRR_TIM15EN BIT(2)
+#define RCC_MC_APB2ENCLRR_TIM16EN BIT(3)
+#define RCC_MC_APB2ENCLRR_TIM17EN BIT(4)
+#define RCC_MC_APB2ENCLRR_SPI1EN BIT(8)
+#define RCC_MC_APB2ENCLRR_SPI4EN BIT(9)
+#define RCC_MC_APB2ENCLRR_SPI5EN BIT(10)
+#define RCC_MC_APB2ENCLRR_USART6EN BIT(13)
+#define RCC_MC_APB2ENCLRR_SAI1EN BIT(16)
+#define RCC_MC_APB2ENCLRR_SAI2EN BIT(17)
+#define RCC_MC_APB2ENCLRR_SAI3EN BIT(18)
+#define RCC_MC_APB2ENCLRR_DFSDMEN BIT(20)
+#define RCC_MC_APB2ENCLRR_ADFSDMEN BIT(21)
+#define RCC_MC_APB2ENCLRR_FDCANEN BIT(24)
+
+/* RCC_MC_APB3ENSETR register fields */
+#define RCC_MC_APB3ENSETR_LPTIM2EN BIT(0)
+#define RCC_MC_APB3ENSETR_LPTIM3EN BIT(1)
+#define RCC_MC_APB3ENSETR_LPTIM4EN BIT(2)
+#define RCC_MC_APB3ENSETR_LPTIM5EN BIT(3)
+#define RCC_MC_APB3ENSETR_SAI4EN BIT(8)
+#define RCC_MC_APB3ENSETR_SYSCFGEN BIT(11)
+#define RCC_MC_APB3ENSETR_VREFEN BIT(13)
+#define RCC_MC_APB3ENSETR_TMPSENSEN BIT(16)
+#define RCC_MC_APB3ENSETR_PMBCTRLEN BIT(17)
+#define RCC_MC_APB3ENSETR_HDPEN BIT(20)
+
+/* RCC_MC_APB3ENCLRR register fields */
+#define RCC_MC_APB3ENCLRR_LPTIM2EN BIT(0)
+#define RCC_MC_APB3ENCLRR_LPTIM3EN BIT(1)
+#define RCC_MC_APB3ENCLRR_LPTIM4EN BIT(2)
+#define RCC_MC_APB3ENCLRR_LPTIM5EN BIT(3)
+#define RCC_MC_APB3ENCLRR_SAI4EN BIT(8)
+#define RCC_MC_APB3ENCLRR_SYSCFGEN BIT(11)
+#define RCC_MC_APB3ENCLRR_VREFEN BIT(13)
+#define RCC_MC_APB3ENCLRR_TMPSENSEN BIT(16)
+#define RCC_MC_APB3ENCLRR_PMBCTRLEN BIT(17)
+#define RCC_MC_APB3ENCLRR_HDPEN BIT(20)
+
+/* RCC_MC_AHB2ENSETR register fields */
+#define RCC_MC_AHB2ENSETR_DMA1EN BIT(0)
+#define RCC_MC_AHB2ENSETR_DMA2EN BIT(1)
+#define RCC_MC_AHB2ENSETR_DMAMUXEN BIT(2)
+#define RCC_MC_AHB2ENSETR_ADC12EN BIT(5)
+#define RCC_MC_AHB2ENSETR_USBOEN BIT(8)
+#define RCC_MC_AHB2ENSETR_SDMMC3EN BIT(16)
+
+/* RCC_MC_AHB2ENCLRR register fields */
+#define RCC_MC_AHB2ENCLRR_DMA1EN BIT(0)
+#define RCC_MC_AHB2ENCLRR_DMA2EN BIT(1)
+#define RCC_MC_AHB2ENCLRR_DMAMUXEN BIT(2)
+#define RCC_MC_AHB2ENCLRR_ADC12EN BIT(5)
+#define RCC_MC_AHB2ENCLRR_USBOEN BIT(8)
+#define RCC_MC_AHB2ENCLRR_SDMMC3EN BIT(16)
+
+/* RCC_MC_AHB3ENSETR register fields */
+#define RCC_MC_AHB3ENSETR_DCMIEN BIT(0)
+#define RCC_MC_AHB3ENSETR_CRYP2EN BIT(4)
+#define RCC_MC_AHB3ENSETR_HASH2EN BIT(5)
+#define RCC_MC_AHB3ENSETR_RNG2EN BIT(6)
+#define RCC_MC_AHB3ENSETR_CRC2EN BIT(7)
+#define RCC_MC_AHB3ENSETR_HSEMEN BIT(11)
+#define RCC_MC_AHB3ENSETR_IPCCEN BIT(12)
+
+/* RCC_MC_AHB3ENCLRR register fields */
+#define RCC_MC_AHB3ENCLRR_DCMIEN BIT(0)
+#define RCC_MC_AHB3ENCLRR_CRYP2EN BIT(4)
+#define RCC_MC_AHB3ENCLRR_HASH2EN BIT(5)
+#define RCC_MC_AHB3ENCLRR_RNG2EN BIT(6)
+#define RCC_MC_AHB3ENCLRR_CRC2EN BIT(7)
+#define RCC_MC_AHB3ENCLRR_HSEMEN BIT(11)
+#define RCC_MC_AHB3ENCLRR_IPCCEN BIT(12)
+
+/* RCC_MC_AHB4ENSETR register fields */
+#define RCC_MC_AHB4ENSETR_GPIOAEN BIT(0)
+#define RCC_MC_AHB4ENSETR_GPIOBEN BIT(1)
+#define RCC_MC_AHB4ENSETR_GPIOCEN BIT(2)
+#define RCC_MC_AHB4ENSETR_GPIODEN BIT(3)
+#define RCC_MC_AHB4ENSETR_GPIOEEN BIT(4)
+#define RCC_MC_AHB4ENSETR_GPIOFEN BIT(5)
+#define RCC_MC_AHB4ENSETR_GPIOGEN BIT(6)
+#define RCC_MC_AHB4ENSETR_GPIOHEN BIT(7)
+#define RCC_MC_AHB4ENSETR_GPIOIEN BIT(8)
+#define RCC_MC_AHB4ENSETR_GPIOJEN BIT(9)
+#define RCC_MC_AHB4ENSETR_GPIOKEN BIT(10)
+
+/* RCC_MC_AHB4ENCLRR register fields */
+#define RCC_MC_AHB4ENCLRR_GPIOAEN BIT(0)
+#define RCC_MC_AHB4ENCLRR_GPIOBEN BIT(1)
+#define RCC_MC_AHB4ENCLRR_GPIOCEN BIT(2)
+#define RCC_MC_AHB4ENCLRR_GPIODEN BIT(3)
+#define RCC_MC_AHB4ENCLRR_GPIOEEN BIT(4)
+#define RCC_MC_AHB4ENCLRR_GPIOFEN BIT(5)
+#define RCC_MC_AHB4ENCLRR_GPIOGEN BIT(6)
+#define RCC_MC_AHB4ENCLRR_GPIOHEN BIT(7)
+#define RCC_MC_AHB4ENCLRR_GPIOIEN BIT(8)
+#define RCC_MC_AHB4ENCLRR_GPIOJEN BIT(9)
+#define RCC_MC_AHB4ENCLRR_GPIOKEN BIT(10)
+
+/* RCC_MC_AXIMENSETR register fields */
+#define RCC_MC_AXIMENSETR_SYSRAMEN BIT(0)
+
+/* RCC_MC_AXIMENCLRR register fields */
+#define RCC_MC_AXIMENCLRR_SYSRAMEN BIT(0)
+
+/* RCC_MC_MLAHBENSETR register fields */
+#define RCC_MC_MLAHBENSETR_RETRAMEN BIT(4)
+
+/* RCC_MC_MLAHBENCLRR register fields */
+#define RCC_MC_MLAHBENCLRR_RETRAMEN BIT(4)
+
+/* RCC_MP_APB1LPENSETR register fields */
+#define RCC_MP_APB1LPENSETR_TIM2LPEN BIT(0)
+#define RCC_MP_APB1LPENSETR_TIM3LPEN BIT(1)
+#define RCC_MP_APB1LPENSETR_TIM4LPEN BIT(2)
+#define RCC_MP_APB1LPENSETR_TIM5LPEN BIT(3)
+#define RCC_MP_APB1LPENSETR_TIM6LPEN BIT(4)
+#define RCC_MP_APB1LPENSETR_TIM7LPEN BIT(5)
+#define RCC_MP_APB1LPENSETR_TIM12LPEN BIT(6)
+#define RCC_MP_APB1LPENSETR_TIM13LPEN BIT(7)
+#define RCC_MP_APB1LPENSETR_TIM14LPEN BIT(8)
+#define RCC_MP_APB1LPENSETR_LPTIM1LPEN BIT(9)
+#define RCC_MP_APB1LPENSETR_SPI2LPEN BIT(11)
+#define RCC_MP_APB1LPENSETR_SPI3LPEN BIT(12)
+#define RCC_MP_APB1LPENSETR_USART2LPEN BIT(14)
+#define RCC_MP_APB1LPENSETR_USART3LPEN BIT(15)
+#define RCC_MP_APB1LPENSETR_UART4LPEN BIT(16)
+#define RCC_MP_APB1LPENSETR_UART5LPEN BIT(17)
+#define RCC_MP_APB1LPENSETR_UART7LPEN BIT(18)
+#define RCC_MP_APB1LPENSETR_UART8LPEN BIT(19)
+#define RCC_MP_APB1LPENSETR_I2C1LPEN BIT(21)
+#define RCC_MP_APB1LPENSETR_I2C2LPEN BIT(22)
+#define RCC_MP_APB1LPENSETR_I2C3LPEN BIT(23)
+#define RCC_MP_APB1LPENSETR_I2C5LPEN BIT(24)
+#define RCC_MP_APB1LPENSETR_SPDIFLPEN BIT(26)
+#define RCC_MP_APB1LPENSETR_CECLPEN BIT(27)
+#define RCC_MP_APB1LPENSETR_DAC12LPEN BIT(29)
+#define RCC_MP_APB1LPENSETR_MDIOSLPEN BIT(31)
+
+/* RCC_MP_APB1LPENCLRR register fields */
+#define RCC_MP_APB1LPENCLRR_TIM2LPEN BIT(0)
+#define RCC_MP_APB1LPENCLRR_TIM3LPEN BIT(1)
+#define RCC_MP_APB1LPENCLRR_TIM4LPEN BIT(2)
+#define RCC_MP_APB1LPENCLRR_TIM5LPEN BIT(3)
+#define RCC_MP_APB1LPENCLRR_TIM6LPEN BIT(4)
+#define RCC_MP_APB1LPENCLRR_TIM7LPEN BIT(5)
+#define RCC_MP_APB1LPENCLRR_TIM12LPEN BIT(6)
+#define RCC_MP_APB1LPENCLRR_TIM13LPEN BIT(7)
+#define RCC_MP_APB1LPENCLRR_TIM14LPEN BIT(8)
+#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN BIT(9)
+#define RCC_MP_APB1LPENCLRR_SPI2LPEN BIT(11)
+#define RCC_MP_APB1LPENCLRR_SPI3LPEN BIT(12)
+#define RCC_MP_APB1LPENCLRR_USART2LPEN BIT(14)
+#define RCC_MP_APB1LPENCLRR_USART3LPEN BIT(15)
+#define RCC_MP_APB1LPENCLRR_UART4LPEN BIT(16)
+#define RCC_MP_APB1LPENCLRR_UART5LPEN BIT(17)
+#define RCC_MP_APB1LPENCLRR_UART7LPEN BIT(18)
+#define RCC_MP_APB1LPENCLRR_UART8LPEN BIT(19)
+#define RCC_MP_APB1LPENCLRR_I2C1LPEN BIT(21)
+#define RCC_MP_APB1LPENCLRR_I2C2LPEN BIT(22)
+#define RCC_MP_APB1LPENCLRR_I2C3LPEN BIT(23)
+#define RCC_MP_APB1LPENCLRR_I2C5LPEN BIT(24)
+#define RCC_MP_APB1LPENCLRR_SPDIFLPEN BIT(26)
+#define RCC_MP_APB1LPENCLRR_CECLPEN BIT(27)
+#define RCC_MP_APB1LPENCLRR_DAC12LPEN BIT(29)
+#define RCC_MP_APB1LPENCLRR_MDIOSLPEN BIT(31)
+
+/* RCC_MP_APB2LPENSETR register fields */
+#define RCC_MP_APB2LPENSETR_TIM1LPEN BIT(0)
+#define RCC_MP_APB2LPENSETR_TIM8LPEN BIT(1)
+#define RCC_MP_APB2LPENSETR_TIM15LPEN BIT(2)
+#define RCC_MP_APB2LPENSETR_TIM16LPEN BIT(3)
+#define RCC_MP_APB2LPENSETR_TIM17LPEN BIT(4)
+#define RCC_MP_APB2LPENSETR_SPI1LPEN BIT(8)
+#define RCC_MP_APB2LPENSETR_SPI4LPEN BIT(9)
+#define RCC_MP_APB2LPENSETR_SPI5LPEN BIT(10)
+#define RCC_MP_APB2LPENSETR_USART6LPEN BIT(13)
+#define RCC_MP_APB2LPENSETR_SAI1LPEN BIT(16)
+#define RCC_MP_APB2LPENSETR_SAI2LPEN BIT(17)
+#define RCC_MP_APB2LPENSETR_SAI3LPEN BIT(18)
+#define RCC_MP_APB2LPENSETR_DFSDMLPEN BIT(20)
+#define RCC_MP_APB2LPENSETR_ADFSDMLPEN BIT(21)
+#define RCC_MP_APB2LPENSETR_FDCANLPEN BIT(24)
+
+/* RCC_MP_APB2LPENCLRR register fields */
+#define RCC_MP_APB2LPENCLRR_TIM1LPEN BIT(0)
+#define RCC_MP_APB2LPENCLRR_TIM8LPEN BIT(1)
+#define RCC_MP_APB2LPENCLRR_TIM15LPEN BIT(2)
+#define RCC_MP_APB2LPENCLRR_TIM16LPEN BIT(3)
+#define RCC_MP_APB2LPENCLRR_TIM17LPEN BIT(4)
+#define RCC_MP_APB2LPENCLRR_SPI1LPEN BIT(8)
+#define RCC_MP_APB2LPENCLRR_SPI4LPEN BIT(9)
+#define RCC_MP_APB2LPENCLRR_SPI5LPEN BIT(10)
+#define RCC_MP_APB2LPENCLRR_USART6LPEN BIT(13)
+#define RCC_MP_APB2LPENCLRR_SAI1LPEN BIT(16)
+#define RCC_MP_APB2LPENCLRR_SAI2LPEN BIT(17)
+#define RCC_MP_APB2LPENCLRR_SAI3LPEN BIT(18)
+#define RCC_MP_APB2LPENCLRR_DFSDMLPEN BIT(20)
+#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN BIT(21)
+#define RCC_MP_APB2LPENCLRR_FDCANLPEN BIT(24)
+
+/* RCC_MP_APB3LPENSETR register fields */
+#define RCC_MP_APB3LPENSETR_LPTIM2LPEN BIT(0)
+#define RCC_MP_APB3LPENSETR_LPTIM3LPEN BIT(1)
+#define RCC_MP_APB3LPENSETR_LPTIM4LPEN BIT(2)
+#define RCC_MP_APB3LPENSETR_LPTIM5LPEN BIT(3)
+#define RCC_MP_APB3LPENSETR_SAI4LPEN BIT(8)
+#define RCC_MP_APB3LPENSETR_SYSCFGLPEN BIT(11)
+#define RCC_MP_APB3LPENSETR_VREFLPEN BIT(13)
+#define RCC_MP_APB3LPENSETR_TMPSENSLPEN BIT(16)
+#define RCC_MP_APB3LPENSETR_PMBCTRLLPEN BIT(17)
+
+/* RCC_MP_APB3LPENCLRR register fields */
+#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN BIT(0)
+#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN BIT(1)
+#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN BIT(2)
+#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN BIT(3)
+#define RCC_MP_APB3LPENCLRR_SAI4LPEN BIT(8)
+#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN BIT(11)
+#define RCC_MP_APB3LPENCLRR_VREFLPEN BIT(13)
+#define RCC_MP_APB3LPENCLRR_TMPSENSLPEN BIT(16)
+#define RCC_MP_APB3LPENCLRR_PMBCTRLLPEN BIT(17)
+
+/* RCC_MP_AHB2LPENSETR register fields */
+#define RCC_MP_AHB2LPENSETR_DMA1LPEN BIT(0)
+#define RCC_MP_AHB2LPENSETR_DMA2LPEN BIT(1)
+#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN BIT(2)
+#define RCC_MP_AHB2LPENSETR_ADC12LPEN BIT(5)
+#define RCC_MP_AHB2LPENSETR_USBOLPEN BIT(8)
+#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN BIT(16)
+
+/* RCC_MP_AHB2LPENCLRR register fields */
+#define RCC_MP_AHB2LPENCLRR_DMA1LPEN BIT(0)
+#define RCC_MP_AHB2LPENCLRR_DMA2LPEN BIT(1)
+#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN BIT(2)
+#define RCC_MP_AHB2LPENCLRR_ADC12LPEN BIT(5)
+#define RCC_MP_AHB2LPENCLRR_USBOLPEN BIT(8)
+#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN BIT(16)
+
+/* RCC_MP_AHB3LPENSETR register fields */
+#define RCC_MP_AHB3LPENSETR_DCMILPEN BIT(0)
+#define RCC_MP_AHB3LPENSETR_CRYP2LPEN BIT(4)
+#define RCC_MP_AHB3LPENSETR_HASH2LPEN BIT(5)
+#define RCC_MP_AHB3LPENSETR_RNG2LPEN BIT(6)
+#define RCC_MP_AHB3LPENSETR_CRC2LPEN BIT(7)
+#define RCC_MP_AHB3LPENSETR_HSEMLPEN BIT(11)
+#define RCC_MP_AHB3LPENSETR_IPCCLPEN BIT(12)
+
+/* RCC_MP_AHB3LPENCLRR register fields */
+#define RCC_MP_AHB3LPENCLRR_DCMILPEN BIT(0)
+#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN BIT(4)
+#define RCC_MP_AHB3LPENCLRR_HASH2LPEN BIT(5)
+#define RCC_MP_AHB3LPENCLRR_RNG2LPEN BIT(6)
+#define RCC_MP_AHB3LPENCLRR_CRC2LPEN BIT(7)
+#define RCC_MP_AHB3LPENCLRR_HSEMLPEN BIT(11)
+#define RCC_MP_AHB3LPENCLRR_IPCCLPEN BIT(12)
+
+/* RCC_MP_AHB4LPENSETR register fields */
+#define RCC_MP_AHB4LPENSETR_GPIOALPEN BIT(0)
+#define RCC_MP_AHB4LPENSETR_GPIOBLPEN BIT(1)
+#define RCC_MP_AHB4LPENSETR_GPIOCLPEN BIT(2)
+#define RCC_MP_AHB4LPENSETR_GPIODLPEN BIT(3)
+#define RCC_MP_AHB4LPENSETR_GPIOELPEN BIT(4)
+#define RCC_MP_AHB4LPENSETR_GPIOFLPEN BIT(5)
+#define RCC_MP_AHB4LPENSETR_GPIOGLPEN BIT(6)
+#define RCC_MP_AHB4LPENSETR_GPIOHLPEN BIT(7)
+#define RCC_MP_AHB4LPENSETR_GPIOILPEN BIT(8)
+#define RCC_MP_AHB4LPENSETR_GPIOJLPEN BIT(9)
+#define RCC_MP_AHB4LPENSETR_GPIOKLPEN BIT(10)
+
+/* RCC_MP_AHB4LPENCLRR register fields */
+#define RCC_MP_AHB4LPENCLRR_GPIOALPEN BIT(0)
+#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN BIT(1)
+#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN BIT(2)
+#define RCC_MP_AHB4LPENCLRR_GPIODLPEN BIT(3)
+#define RCC_MP_AHB4LPENCLRR_GPIOELPEN BIT(4)
+#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN BIT(5)
+#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN BIT(6)
+#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN BIT(7)
+#define RCC_MP_AHB4LPENCLRR_GPIOILPEN BIT(8)
+#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN BIT(9)
+#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN BIT(10)
+
+/* RCC_MP_AXIMLPENSETR register fields */
+#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN BIT(0)
+
+/* RCC_MP_AXIMLPENCLRR register fields */
+#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN BIT(0)
+
+/* RCC_MP_MLAHBLPENSETR register fields */
+#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN BIT(0)
+#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN BIT(1)
+#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN BIT(2)
+#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN BIT(4)
+
+/* RCC_MP_MLAHBLPENCLRR register fields */
+#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN BIT(0)
+#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN BIT(1)
+#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN BIT(2)
+#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN BIT(4)
+
+/* RCC_MC_APB1LPENSETR register fields */
+#define RCC_MC_APB1LPENSETR_TIM2LPEN BIT(0)
+#define RCC_MC_APB1LPENSETR_TIM3LPEN BIT(1)
+#define RCC_MC_APB1LPENSETR_TIM4LPEN BIT(2)
+#define RCC_MC_APB1LPENSETR_TIM5LPEN BIT(3)
+#define RCC_MC_APB1LPENSETR_TIM6LPEN BIT(4)
+#define RCC_MC_APB1LPENSETR_TIM7LPEN BIT(5)
+#define RCC_MC_APB1LPENSETR_TIM12LPEN BIT(6)
+#define RCC_MC_APB1LPENSETR_TIM13LPEN BIT(7)
+#define RCC_MC_APB1LPENSETR_TIM14LPEN BIT(8)
+#define RCC_MC_APB1LPENSETR_LPTIM1LPEN BIT(9)
+#define RCC_MC_APB1LPENSETR_SPI2LPEN BIT(11)
+#define RCC_MC_APB1LPENSETR_SPI3LPEN BIT(12)
+#define RCC_MC_APB1LPENSETR_USART2LPEN BIT(14)
+#define RCC_MC_APB1LPENSETR_USART3LPEN BIT(15)
+#define RCC_MC_APB1LPENSETR_UART4LPEN BIT(16)
+#define RCC_MC_APB1LPENSETR_UART5LPEN BIT(17)
+#define RCC_MC_APB1LPENSETR_UART7LPEN BIT(18)
+#define RCC_MC_APB1LPENSETR_UART8LPEN BIT(19)
+#define RCC_MC_APB1LPENSETR_I2C1LPEN BIT(21)
+#define RCC_MC_APB1LPENSETR_I2C2LPEN BIT(22)
+#define RCC_MC_APB1LPENSETR_I2C3LPEN BIT(23)
+#define RCC_MC_APB1LPENSETR_I2C5LPEN BIT(24)
+#define RCC_MC_APB1LPENSETR_SPDIFLPEN BIT(26)
+#define RCC_MC_APB1LPENSETR_CECLPEN BIT(27)
+#define RCC_MC_APB1LPENSETR_WWDG1LPEN BIT(28)
+#define RCC_MC_APB1LPENSETR_DAC12LPEN BIT(29)
+#define RCC_MC_APB1LPENSETR_MDIOSLPEN BIT(31)
+
+/* RCC_MC_APB1LPENCLRR register fields */
+#define RCC_MC_APB1LPENCLRR_TIM2LPEN BIT(0)
+#define RCC_MC_APB1LPENCLRR_TIM3LPEN BIT(1)
+#define RCC_MC_APB1LPENCLRR_TIM4LPEN BIT(2)
+#define RCC_MC_APB1LPENCLRR_TIM5LPEN BIT(3)
+#define RCC_MC_APB1LPENCLRR_TIM6LPEN BIT(4)
+#define RCC_MC_APB1LPENCLRR_TIM7LPEN BIT(5)
+#define RCC_MC_APB1LPENCLRR_TIM12LPEN BIT(6)
+#define RCC_MC_APB1LPENCLRR_TIM13LPEN BIT(7)
+#define RCC_MC_APB1LPENCLRR_TIM14LPEN BIT(8)
+#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN BIT(9)
+#define RCC_MC_APB1LPENCLRR_SPI2LPEN BIT(11)
+#define RCC_MC_APB1LPENCLRR_SPI3LPEN BIT(12)
+#define RCC_MC_APB1LPENCLRR_USART2LPEN BIT(14)
+#define RCC_MC_APB1LPENCLRR_USART3LPEN BIT(15)
+#define RCC_MC_APB1LPENCLRR_UART4LPEN BIT(16)
+#define RCC_MC_APB1LPENCLRR_UART5LPEN BIT(17)
+#define RCC_MC_APB1LPENCLRR_UART7LPEN BIT(18)
+#define RCC_MC_APB1LPENCLRR_UART8LPEN BIT(19)
+#define RCC_MC_APB1LPENCLRR_I2C1LPEN BIT(21)
+#define RCC_MC_APB1LPENCLRR_I2C2LPEN BIT(22)
+#define RCC_MC_APB1LPENCLRR_I2C3LPEN BIT(23)
+#define RCC_MC_APB1LPENCLRR_I2C5LPEN BIT(24)
+#define RCC_MC_APB1LPENCLRR_SPDIFLPEN BIT(26)
+#define RCC_MC_APB1LPENCLRR_CECLPEN BIT(27)
+#define RCC_MC_APB1LPENCLRR_WWDG1LPEN BIT(28)
+#define RCC_MC_APB1LPENCLRR_DAC12LPEN BIT(29)
+#define RCC_MC_APB1LPENCLRR_MDIOSLPEN BIT(31)
+
+/* RCC_MC_APB2LPENSETR register fields */
+#define RCC_MC_APB2LPENSETR_TIM1LPEN BIT(0)
+#define RCC_MC_APB2LPENSETR_TIM8LPEN BIT(1)
+#define RCC_MC_APB2LPENSETR_TIM15LPEN BIT(2)
+#define RCC_MC_APB2LPENSETR_TIM16LPEN BIT(3)
+#define RCC_MC_APB2LPENSETR_TIM17LPEN BIT(4)
+#define RCC_MC_APB2LPENSETR_SPI1LPEN BIT(8)
+#define RCC_MC_APB2LPENSETR_SPI4LPEN BIT(9)
+#define RCC_MC_APB2LPENSETR_SPI5LPEN BIT(10)
+#define RCC_MC_APB2LPENSETR_USART6LPEN BIT(13)
+#define RCC_MC_APB2LPENSETR_SAI1LPEN BIT(16)
+#define RCC_MC_APB2LPENSETR_SAI2LPEN BIT(17)
+#define RCC_MC_APB2LPENSETR_SAI3LPEN BIT(18)
+#define RCC_MC_APB2LPENSETR_DFSDMLPEN BIT(20)
+#define RCC_MC_APB2LPENSETR_ADFSDMLPEN BIT(21)
+#define RCC_MC_APB2LPENSETR_FDCANLPEN BIT(24)
+
+/* RCC_MC_APB2LPENCLRR register fields */
+#define RCC_MC_APB2LPENCLRR_TIM1LPEN BIT(0)
+#define RCC_MC_APB2LPENCLRR_TIM8LPEN BIT(1)
+#define RCC_MC_APB2LPENCLRR_TIM15LPEN BIT(2)
+#define RCC_MC_APB2LPENCLRR_TIM16LPEN BIT(3)
+#define RCC_MC_APB2LPENCLRR_TIM17LPEN BIT(4)
+#define RCC_MC_APB2LPENCLRR_SPI1LPEN BIT(8)
+#define RCC_MC_APB2LPENCLRR_SPI4LPEN BIT(9)
+#define RCC_MC_APB2LPENCLRR_SPI5LPEN BIT(10)
+#define RCC_MC_APB2LPENCLRR_USART6LPEN BIT(13)
+#define RCC_MC_APB2LPENCLRR_SAI1LPEN BIT(16)
+#define RCC_MC_APB2LPENCLRR_SAI2LPEN BIT(17)
+#define RCC_MC_APB2LPENCLRR_SAI3LPEN BIT(18)
+#define RCC_MC_APB2LPENCLRR_DFSDMLPEN BIT(20)
+#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN BIT(21)
+#define RCC_MC_APB2LPENCLRR_FDCANLPEN BIT(24)
+
+/* RCC_MC_APB3LPENSETR register fields */
+#define RCC_MC_APB3LPENSETR_LPTIM2LPEN BIT(0)
+#define RCC_MC_APB3LPENSETR_LPTIM3LPEN BIT(1)
+#define RCC_MC_APB3LPENSETR_LPTIM4LPEN BIT(2)
+#define RCC_MC_APB3LPENSETR_LPTIM5LPEN BIT(3)
+#define RCC_MC_APB3LPENSETR_SAI4LPEN BIT(8)
+#define RCC_MC_APB3LPENSETR_SYSCFGLPEN BIT(11)
+#define RCC_MC_APB3LPENSETR_VREFLPEN BIT(13)
+#define RCC_MC_APB3LPENSETR_TMPSENSLPEN BIT(16)
+#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN BIT(17)
+
+/* RCC_MC_APB3LPENCLRR register fields */
+#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN BIT(0)
+#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN BIT(1)
+#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN BIT(2)
+#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN BIT(3)
+#define RCC_MC_APB3LPENCLRR_SAI4LPEN BIT(8)
+#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN BIT(11)
+#define RCC_MC_APB3LPENCLRR_VREFLPEN BIT(13)
+#define RCC_MC_APB3LPENCLRR_TMPSENSLPEN BIT(16)
+#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN BIT(17)
+
+/* RCC_MC_AHB2LPENSETR register fields */
+#define RCC_MC_AHB2LPENSETR_DMA1LPEN BIT(0)
+#define RCC_MC_AHB2LPENSETR_DMA2LPEN BIT(1)
+#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN BIT(2)
+#define RCC_MC_AHB2LPENSETR_ADC12LPEN BIT(5)
+#define RCC_MC_AHB2LPENSETR_USBOLPEN BIT(8)
+#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN BIT(16)
+
+/* RCC_MC_AHB2LPENCLRR register fields */
+#define RCC_MC_AHB2LPENCLRR_DMA1LPEN BIT(0)
+#define RCC_MC_AHB2LPENCLRR_DMA2LPEN BIT(1)
+#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN BIT(2)
+#define RCC_MC_AHB2LPENCLRR_ADC12LPEN BIT(5)
+#define RCC_MC_AHB2LPENCLRR_USBOLPEN BIT(8)
+#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN BIT(16)
+
+/* RCC_MC_AHB3LPENSETR register fields */
+#define RCC_MC_AHB3LPENSETR_DCMILPEN BIT(0)
+#define RCC_MC_AHB3LPENSETR_CRYP2LPEN BIT(4)
+#define RCC_MC_AHB3LPENSETR_HASH2LPEN BIT(5)
+#define RCC_MC_AHB3LPENSETR_RNG2LPEN BIT(6)
+#define RCC_MC_AHB3LPENSETR_CRC2LPEN BIT(7)
+#define RCC_MC_AHB3LPENSETR_HSEMLPEN BIT(11)
+#define RCC_MC_AHB3LPENSETR_IPCCLPEN BIT(12)
+
+/* RCC_MC_AHB3LPENCLRR register fields */
+#define RCC_MC_AHB3LPENCLRR_DCMILPEN BIT(0)
+#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN BIT(4)
+#define RCC_MC_AHB3LPENCLRR_HASH2LPEN BIT(5)
+#define RCC_MC_AHB3LPENCLRR_RNG2LPEN BIT(6)
+#define RCC_MC_AHB3LPENCLRR_CRC2LPEN BIT(7)
+#define RCC_MC_AHB3LPENCLRR_HSEMLPEN BIT(11)
+#define RCC_MC_AHB3LPENCLRR_IPCCLPEN BIT(12)
+
+/* RCC_MC_AHB4LPENSETR register fields */
+#define RCC_MC_AHB4LPENSETR_GPIOALPEN BIT(0)
+#define RCC_MC_AHB4LPENSETR_GPIOBLPEN BIT(1)
+#define RCC_MC_AHB4LPENSETR_GPIOCLPEN BIT(2)
+#define RCC_MC_AHB4LPENSETR_GPIODLPEN BIT(3)
+#define RCC_MC_AHB4LPENSETR_GPIOELPEN BIT(4)
+#define RCC_MC_AHB4LPENSETR_GPIOFLPEN BIT(5)
+#define RCC_MC_AHB4LPENSETR_GPIOGLPEN BIT(6)
+#define RCC_MC_AHB4LPENSETR_GPIOHLPEN BIT(7)
+#define RCC_MC_AHB4LPENSETR_GPIOILPEN BIT(8)
+#define RCC_MC_AHB4LPENSETR_GPIOJLPEN BIT(9)
+#define RCC_MC_AHB4LPENSETR_GPIOKLPEN BIT(10)
+
+/* RCC_MC_AHB4LPENCLRR register fields */
+#define RCC_MC_AHB4LPENCLRR_GPIOALPEN BIT(0)
+#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN BIT(1)
+#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN BIT(2)
+#define RCC_MC_AHB4LPENCLRR_GPIODLPEN BIT(3)
+#define RCC_MC_AHB4LPENCLRR_GPIOELPEN BIT(4)
+#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN BIT(5)
+#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN BIT(6)
+#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN BIT(7)
+#define RCC_MC_AHB4LPENCLRR_GPIOILPEN BIT(8)
+#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN BIT(9)
+#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN BIT(10)
+
+/* RCC_MC_AXIMLPENSETR register fields */
+#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN BIT(0)
+
+/* RCC_MC_AXIMLPENCLRR register fields */
+#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN BIT(0)
+
+/* RCC_MC_MLAHBLPENSETR register fields */
+#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN BIT(0)
+#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN BIT(1)
+#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN BIT(2)
+#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN BIT(4)
+
+/* RCC_MC_MLAHBLPENCLRR register fields */
+#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN BIT(0)
+#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN BIT(1)
+#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN BIT(2)
+#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN BIT(4)
+
+/* RCC_MC_RSTSCLRR register fields */
+#define RCC_MC_RSTSCLRR_PORRSTF BIT(0)
+#define RCC_MC_RSTSCLRR_BORRSTF BIT(1)
+#define RCC_MC_RSTSCLRR_PADRSTF BIT(2)
+#define RCC_MC_RSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_MC_RSTSCLRR_VCORERSTF BIT(4)
+#define RCC_MC_RSTSCLRR_MCURSTF BIT(5)
+#define RCC_MC_RSTSCLRR_MPSYSRSTF BIT(6)
+#define RCC_MC_RSTSCLRR_MCSYSRSTF BIT(7)
+#define RCC_MC_RSTSCLRR_IWDG1RSTF BIT(8)
+#define RCC_MC_RSTSCLRR_IWDG2RSTF BIT(9)
+#define RCC_MC_RSTSCLRR_WWDG1RSTF BIT(10)
+
+/* RCC_MC_CIER register fields */
+#define RCC_MC_CIER_LSIRDYIE BIT(0)
+#define RCC_MC_CIER_LSERDYIE BIT(1)
+#define RCC_MC_CIER_HSIRDYIE BIT(2)
+#define RCC_MC_CIER_HSERDYIE BIT(3)
+#define RCC_MC_CIER_CSIRDYIE BIT(4)
+#define RCC_MC_CIER_PLL1DYIE BIT(8)
+#define RCC_MC_CIER_PLL2DYIE BIT(9)
+#define RCC_MC_CIER_PLL3DYIE BIT(10)
+#define RCC_MC_CIER_PLL4DYIE BIT(11)
+#define RCC_MC_CIER_LSECSSIE BIT(16)
+#define RCC_MC_CIER_WKUPIE BIT(20)
+
+/* RCC_MC_CIFR register fields */
+#define RCC_MC_CIFR_LSIRDYF BIT(0)
+#define RCC_MC_CIFR_LSERDYF BIT(1)
+#define RCC_MC_CIFR_HSIRDYF BIT(2)
+#define RCC_MC_CIFR_HSERDYF BIT(3)
+#define RCC_MC_CIFR_CSIRDYF BIT(4)
+#define RCC_MC_CIFR_PLL1DYF BIT(8)
+#define RCC_MC_CIFR_PLL2DYF BIT(9)
+#define RCC_MC_CIFR_PLL3DYF BIT(10)
+#define RCC_MC_CIFR_PLL4DYF BIT(11)
+#define RCC_MC_CIFR_LSECSSF BIT(16)
+#define RCC_MC_CIFR_WKUPF BIT(20)
+
+/* RCC_VERR register fields */
+#define RCC_VERR_MINREV_MASK GENMASK(3, 0)
+#define RCC_VERR_MINREV_SHIFT 0
+#define RCC_VERR_MAJREV_MASK GENMASK(7, 4)
+#define RCC_VERR_MAJREV_SHIFT 4
+
+/* Used for RCC_OCENSETR and RCC_OCENCLRR registers */
+#define RCC_OCENR_HSION BIT(0)
+#define RCC_OCENR_HSIKERON BIT(1)
+#define RCC_OCENR_CSION BIT(4)
+#define RCC_OCENR_CSIKERON BIT(5)
+#define RCC_OCENR_DIGBYP BIT(7)
+#define RCC_OCENR_HSEON BIT(8)
+#define RCC_OCENR_HSEKERON BIT(9)
+#define RCC_OCENR_HSEBYP BIT(10)
+#define RCC_OCENR_HSECSSON BIT(11)
+
+/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
+#define RCC_MP_ENCLRR_OFFSET U(4)
+
+/* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */
+#define RCC_RSTCLRR_OFFSET U(4)
+
+/* Used for most of DIVR register: max div for RTC */
+#define RCC_DIVR_DIV_MASK GENMASK(5, 0)
+#define RCC_DIVR_DIVRDY BIT(31)
+
+/* Masks for specific DIVR registers */
+#define RCC_APBXDIV_MASK GENMASK(2, 0)
+#define RCC_MPUDIV_MASK GENMASK(2, 0)
+#define RCC_AXIDIV_MASK GENMASK(2, 0)
+#define RCC_MCUDIV_MASK GENMASK(3, 0)
+
+/* Used for most of RCC_<x>SELR registers */
+#define RCC_SELR_SRC_MASK GENMASK(2, 0)
+#define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0)
+#define RCC_SELR_SRCRDY BIT(31)
+
+/* Used for all RCC_PLL<n>CR registers */
+#define RCC_PLLNCR_PLLON BIT(0)
+#define RCC_PLLNCR_PLLRDY BIT(1)
+#define RCC_PLLNCR_SSCG_CTRL BIT(2)
+#define RCC_PLLNCR_DIVPEN BIT(4)
+#define RCC_PLLNCR_DIVQEN BIT(5)
+#define RCC_PLLNCR_DIVREN BIT(6)
+#define RCC_PLLNCR_DIVEN_SHIFT 4
+
+/* Used for all RCC_PLL<n>CFGR1 registers */
+#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
+#define RCC_PLLNCFGR1_DIVM_SHIFT 16
+#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
+#define RCC_PLLNCFGR1_DIVN_SHIFT 0
+
+/* Only for PLL3 and PLL4 */
+#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
+#define RCC_PLLNCFGR1_IFRGE_SHIFT 24
+
+/* Used for all RCC_PLL<n>CFGR2 registers */
+#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
+#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
+#define RCC_PLLNCFGR2_DIVP_SHIFT 0
+#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
+#define RCC_PLLNCFGR2_DIVQ_SHIFT 8
+#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
+#define RCC_PLLNCFGR2_DIVR_SHIFT 16
+
+/* Used for all RCC_PLL<n>FRACR registers */
+#define RCC_PLLNFRACR_FRACV_SHIFT 3
+#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
+#define RCC_PLLNFRACR_FRACLE BIT(16)
+
+/* Used for all RCC_PLL<n>CSGR registers */
+#define RCC_PLLNCSGR_INC_STEP_SHIFT 16
+#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
+#define RCC_PLLNCSGR_MOD_PER_SHIFT 0
+#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
+#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
+#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
+
+/* Used for TIMER Prescaler */
+#define RCC_TIMGXPRER_TIMGXPRE BIT(0)
+
+/* Used for RCC_MCO related operations */
+#define RCC_MCOCFG_MCOON BIT(12)
+#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
+#define RCC_MCOCFG_MCODIV_SHIFT 4
+#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
+
+#endif /* STM32MP1_RCC_H */
diff --git a/include/drivers/st/stm32mp1_clk.h b/include/drivers/st/stm32mp1_clk.h
new file mode 100644
index 0000000..e2395bc
--- /dev/null
+++ b/include/drivers/st/stm32mp1_clk.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2018-2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP1_CLK_H
+#define STM32MP1_CLK_H
+
+#include <arch_helpers.h>
+
+enum stm32mp_osc_id {
+ _HSI,
+ _HSE,
+ _CSI,
+ _LSI,
+ _LSE,
+ _I2S_CKIN,
+ NB_OSC,
+ _UNKNOWN_OSC_ID = 0xFF
+};
+
+extern const char *stm32mp_osc_node_label[NB_OSC];
+
+int stm32mp1_clk_probe(void);
+int stm32mp1_clk_init(void);
+
+bool stm32mp1_rcc_is_secure(void);
+bool stm32mp1_rcc_is_mckprot(void);
+
+/* SMP protection on RCC registers access */
+void stm32mp1_clk_rcc_regs_lock(void);
+void stm32mp1_clk_rcc_regs_unlock(void);
+
+#ifdef STM32MP_SHARED_RESOURCES
+void stm32mp1_register_clock_parents_secure(unsigned long id);
+#endif
+#endif /* STM32MP1_CLK_H */
diff --git a/include/drivers/st/stm32mp1_ddr.h b/include/drivers/st/stm32mp1_ddr.h
new file mode 100644
index 0000000..df71f35
--- /dev/null
+++ b/include/drivers/st/stm32mp1_ddr.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+ */
+
+#ifndef STM32MP1_DDR_H
+#define STM32MP1_DDR_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <drivers/st/stm32mp_ddr.h>
+
+struct stm32mp1_ddrctrl_reg {
+ uint32_t mstr;
+ uint32_t mrctrl0;
+ uint32_t mrctrl1;
+ uint32_t derateen;
+ uint32_t derateint;
+ uint32_t pwrctl;
+ uint32_t pwrtmg;
+ uint32_t hwlpctl;
+ uint32_t rfshctl0;
+ uint32_t rfshctl3;
+ uint32_t crcparctl0;
+ uint32_t zqctl0;
+ uint32_t dfitmg0;
+ uint32_t dfitmg1;
+ uint32_t dfilpcfg0;
+ uint32_t dfiupd0;
+ uint32_t dfiupd1;
+ uint32_t dfiupd2;
+ uint32_t dfiphymstr;
+ uint32_t odtmap;
+ uint32_t dbg0;
+ uint32_t dbg1;
+ uint32_t dbgcmd;
+ uint32_t poisoncfg;
+ uint32_t pccfg;
+};
+
+struct stm32mp1_ddrctrl_timing {
+ uint32_t rfshtmg;
+ uint32_t dramtmg0;
+ uint32_t dramtmg1;
+ uint32_t dramtmg2;
+ uint32_t dramtmg3;
+ uint32_t dramtmg4;
+ uint32_t dramtmg5;
+ uint32_t dramtmg6;
+ uint32_t dramtmg7;
+ uint32_t dramtmg8;
+ uint32_t dramtmg14;
+ uint32_t odtcfg;
+};
+
+struct stm32mp1_ddrctrl_map {
+ uint32_t addrmap1;
+ uint32_t addrmap2;
+ uint32_t addrmap3;
+ uint32_t addrmap4;
+ uint32_t addrmap5;
+ uint32_t addrmap6;
+ uint32_t addrmap9;
+ uint32_t addrmap10;
+ uint32_t addrmap11;
+};
+
+struct stm32mp1_ddrctrl_perf {
+ uint32_t sched;
+ uint32_t sched1;
+ uint32_t perfhpr1;
+ uint32_t perflpr1;
+ uint32_t perfwr1;
+ uint32_t pcfgr_0;
+ uint32_t pcfgw_0;
+ uint32_t pcfgqos0_0;
+ uint32_t pcfgqos1_0;
+ uint32_t pcfgwqos0_0;
+ uint32_t pcfgwqos1_0;
+#if STM32MP_DDR_DUAL_AXI_PORT
+ uint32_t pcfgr_1;
+ uint32_t pcfgw_1;
+ uint32_t pcfgqos0_1;
+ uint32_t pcfgqos1_1;
+ uint32_t pcfgwqos0_1;
+ uint32_t pcfgwqos1_1;
+#endif
+};
+
+struct stm32mp1_ddrphy_reg {
+ uint32_t pgcr;
+ uint32_t aciocr;
+ uint32_t dxccr;
+ uint32_t dsgcr;
+ uint32_t dcr;
+ uint32_t odtcr;
+ uint32_t zq0cr1;
+ uint32_t dx0gcr;
+ uint32_t dx1gcr;
+#if STM32MP_DDR_32BIT_INTERFACE
+ uint32_t dx2gcr;
+ uint32_t dx3gcr;
+#endif
+};
+
+struct stm32mp1_ddrphy_timing {
+ uint32_t ptr0;
+ uint32_t ptr1;
+ uint32_t ptr2;
+ uint32_t dtpr0;
+ uint32_t dtpr1;
+ uint32_t dtpr2;
+ uint32_t mr0;
+ uint32_t mr1;
+ uint32_t mr2;
+ uint32_t mr3;
+};
+
+struct stm32mp_ddr_config {
+ struct stm32mp_ddr_info info;
+ struct stm32mp1_ddrctrl_reg c_reg;
+ struct stm32mp1_ddrctrl_timing c_timing;
+ struct stm32mp1_ddrctrl_map c_map;
+ struct stm32mp1_ddrctrl_perf c_perf;
+ struct stm32mp1_ddrphy_reg p_reg;
+ struct stm32mp1_ddrphy_timing p_timing;
+};
+
+int stm32mp1_ddr_clk_enable(struct stm32mp_ddr_priv *priv, uint32_t mem_speed);
+void stm32mp1_ddr_init(struct stm32mp_ddr_priv *priv, struct stm32mp_ddr_config *config);
+
+#endif /* STM32MP1_DDR_H */
diff --git a/include/drivers/st/stm32mp1_ddr_helpers.h b/include/drivers/st/stm32mp1_ddr_helpers.h
new file mode 100644
index 0000000..38f2415
--- /dev/null
+++ b/include/drivers/st/stm32mp1_ddr_helpers.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP1_DDR_HELPERS_H
+#define STM32MP1_DDR_HELPERS_H
+
+void ddr_enable_clock(void);
+
+#endif /* STM32MP1_DDR_HELPERS_H */
diff --git a/include/drivers/st/stm32mp1_ddr_regs.h b/include/drivers/st/stm32mp1_ddr_regs.h
new file mode 100644
index 0000000..2fbe1c8
--- /dev/null
+++ b/include/drivers/st/stm32mp1_ddr_regs.h
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+ */
+
+#ifndef STM32MP1_DDR_REGS_H
+#define STM32MP1_DDR_REGS_H
+
+#include <drivers/st/stm32mp_ddrctrl_regs.h>
+#include <lib/utils_def.h>
+
+/* DDR Physical Interface Control (DDRPHYC) registers*/
+struct stm32mp_ddrphy {
+ uint32_t ridr; /* 0x00 R Revision Identification */
+ uint32_t pir; /* 0x04 R/W PHY Initialization */
+ uint32_t pgcr; /* 0x08 R/W PHY General Configuration */
+ uint32_t pgsr; /* 0x0C PHY General Status */
+ uint32_t dllgcr; /* 0x10 R/W DLL General Control */
+ uint32_t acdllcr; /* 0x14 R/W AC DLL Control */
+ uint32_t ptr0; /* 0x18 R/W PHY Timing 0 */
+ uint32_t ptr1; /* 0x1C R/W PHY Timing 1 */
+ uint32_t ptr2; /* 0x20 R/W PHY Timing 2 */
+ uint32_t aciocr; /* 0x24 AC I/O Configuration */
+ uint32_t dxccr; /* 0x28 DATX8 Common Configuration */
+ uint32_t dsgcr; /* 0x2C DDR System General Configuration */
+ uint32_t dcr; /* 0x30 DRAM Configuration */
+ uint32_t dtpr0; /* 0x34 DRAM Timing Parameters0 */
+ uint32_t dtpr1; /* 0x38 DRAM Timing Parameters1 */
+ uint32_t dtpr2; /* 0x3C DRAM Timing Parameters2 */
+ uint32_t mr0; /* 0x40 Mode 0 */
+ uint32_t mr1; /* 0x44 Mode 1 */
+ uint32_t mr2; /* 0x48 Mode 2 */
+ uint32_t mr3; /* 0x4C Mode 3 */
+ uint32_t odtcr; /* 0x50 ODT Configuration */
+ uint32_t dtar; /* 0x54 data training address */
+ uint32_t dtdr0; /* 0x58 */
+ uint32_t dtdr1; /* 0x5c */
+ uint8_t res1[0x0c0 - 0x060]; /* 0x60 */
+ uint32_t dcuar; /* 0xc0 Address */
+ uint32_t dcudr; /* 0xc4 DCU Data */
+ uint32_t dcurr; /* 0xc8 DCU Run */
+ uint32_t dculr; /* 0xcc DCU Loop */
+ uint32_t dcugcr; /* 0xd0 DCU General Configuration */
+ uint32_t dcutpr; /* 0xd4 DCU Timing Parameters */
+ uint32_t dcusr0; /* 0xd8 DCU Status 0 */
+ uint32_t dcusr1; /* 0xdc DCU Status 1 */
+ uint8_t res2[0x100 - 0xe0]; /* 0xe0 */
+ uint32_t bistrr; /* 0x100 BIST Run */
+ uint32_t bistmskr0; /* 0x104 BIST Mask 0 */
+ uint32_t bistmskr1; /* 0x108 BIST Mask 0 */
+ uint32_t bistwcr; /* 0x10c BIST Word Count */
+ uint32_t bistlsr; /* 0x110 BIST LFSR Seed */
+ uint32_t bistar0; /* 0x114 BIST Address 0 */
+ uint32_t bistar1; /* 0x118 BIST Address 1 */
+ uint32_t bistar2; /* 0x11c BIST Address 2 */
+ uint32_t bistupdr; /* 0x120 BIST User Data Pattern */
+ uint32_t bistgsr; /* 0x124 BIST General Status */
+ uint32_t bistwer; /* 0x128 BIST Word Error */
+ uint32_t bistber0; /* 0x12c BIST Bit Error 0 */
+ uint32_t bistber1; /* 0x130 BIST Bit Error 1 */
+ uint32_t bistber2; /* 0x134 BIST Bit Error 2 */
+ uint32_t bistwcsr; /* 0x138 BIST Word Count Status */
+ uint32_t bistfwr0; /* 0x13c BIST Fail Word 0 */
+ uint32_t bistfwr1; /* 0x140 BIST Fail Word 1 */
+ uint8_t res3[0x178 - 0x144]; /* 0x144 */
+ uint32_t gpr0; /* 0x178 General Purpose 0 (GPR0) */
+ uint32_t gpr1; /* 0x17C General Purpose 1 (GPR1) */
+ uint32_t zq0cr0; /* 0x180 zq 0 control 0 */
+ uint32_t zq0cr1; /* 0x184 zq 0 control 1 */
+ uint32_t zq0sr0; /* 0x188 zq 0 status 0 */
+ uint32_t zq0sr1; /* 0x18C zq 0 status 1 */
+ uint8_t res4[0x1C0 - 0x190]; /* 0x190 */
+ uint32_t dx0gcr; /* 0x1c0 Byte lane 0 General Configuration */
+ uint32_t dx0gsr0; /* 0x1c4 Byte lane 0 General Status 0 */
+ uint32_t dx0gsr1; /* 0x1c8 Byte lane 0 General Status 1 */
+ uint32_t dx0dllcr; /* 0x1cc Byte lane 0 DLL Control */
+ uint32_t dx0dqtr; /* 0x1d0 Byte lane 0 DQ Timing */
+ uint32_t dx0dqstr; /* 0x1d4 Byte lane 0 DQS Timing */
+ uint8_t res5[0x200 - 0x1d8]; /* 0x1d8 */
+ uint32_t dx1gcr; /* 0x200 Byte lane 1 General Configuration */
+ uint32_t dx1gsr0; /* 0x204 Byte lane 1 General Status 0 */
+ uint32_t dx1gsr1; /* 0x208 Byte lane 1 General Status 1 */
+ uint32_t dx1dllcr; /* 0x20c Byte lane 1 DLL Control */
+ uint32_t dx1dqtr; /* 0x210 Byte lane 1 DQ Timing */
+ uint32_t dx1dqstr; /* 0x214 Byte lane 1 QS Timing */
+ uint8_t res6[0x240 - 0x218]; /* 0x218 */
+#if STM32MP_DDR_32BIT_INTERFACE
+ uint32_t dx2gcr; /* 0x240 Byte lane 2 General Configuration */
+ uint32_t dx2gsr0; /* 0x244 Byte lane 2 General Status 0 */
+ uint32_t dx2gsr1; /* 0x248 Byte lane 2 General Status 1 */
+ uint32_t dx2dllcr; /* 0x24c Byte lane 2 DLL Control */
+ uint32_t dx2dqtr; /* 0x250 Byte lane 2 DQ Timing */
+ uint32_t dx2dqstr; /* 0x254 Byte lane 2 QS Timing */
+ uint8_t res7[0x280 - 0x258]; /* 0x258 */
+ uint32_t dx3gcr; /* 0x280 Byte lane 3 General Configuration */
+ uint32_t dx3gsr0; /* 0x284 Byte lane 3 General Status 0 */
+ uint32_t dx3gsr1; /* 0x288 Byte lane 3 General Status 1 */
+ uint32_t dx3dllcr; /* 0x28c Byte lane 3 DLL Control */
+ uint32_t dx3dqtr; /* 0x290 Byte lane 3 DQ Timing */
+ uint32_t dx3dqstr; /* 0x294 Byte lane 3 QS Timing */
+#endif
+} __packed;
+
+/* DDR PHY registers offsets */
+#define DDRPHYC_PIR 0x004
+#define DDRPHYC_PGCR 0x008
+#define DDRPHYC_PGSR 0x00C
+#define DDRPHYC_DLLGCR 0x010
+#define DDRPHYC_ACDLLCR 0x014
+#define DDRPHYC_PTR0 0x018
+#define DDRPHYC_ACIOCR 0x024
+#define DDRPHYC_DXCCR 0x028
+#define DDRPHYC_DSGCR 0x02C
+#define DDRPHYC_ZQ0CR0 0x180
+#define DDRPHYC_DX0GCR 0x1C0
+#define DDRPHYC_DX0DLLCR 0x1CC
+#define DDRPHYC_DX1GCR 0x200
+#define DDRPHYC_DX1DLLCR 0x20C
+#if STM32MP_DDR_32BIT_INTERFACE
+#define DDRPHYC_DX2GCR 0x240
+#define DDRPHYC_DX2DLLCR 0x24C
+#define DDRPHYC_DX3GCR 0x280
+#define DDRPHYC_DX3DLLCR 0x28C
+#endif
+
+/* DDR PHY Register fields */
+#define DDRPHYC_PIR_INIT BIT(0)
+#define DDRPHYC_PIR_DLLSRST BIT(1)
+#define DDRPHYC_PIR_DLLLOCK BIT(2)
+#define DDRPHYC_PIR_ZCAL BIT(3)
+#define DDRPHYC_PIR_ITMSRST BIT(4)
+#define DDRPHYC_PIR_DRAMRST BIT(5)
+#define DDRPHYC_PIR_DRAMINIT BIT(6)
+#define DDRPHYC_PIR_QSTRN BIT(7)
+#define DDRPHYC_PIR_RVTRN BIT(8)
+#define DDRPHYC_PIR_ICPC BIT(16)
+#define DDRPHYC_PIR_ZCALBYP BIT(30)
+#define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
+
+#define DDRPHYC_PGCR_DFTCMP BIT(2)
+#define DDRPHYC_PGCR_PDDISDX BIT(24)
+#define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25)
+
+#define DDRPHYC_PGSR_IDONE BIT(0)
+#define DDRPHYC_PGSR_DTERR BIT(5)
+#define DDRPHYC_PGSR_DTIERR BIT(6)
+#define DDRPHYC_PGSR_DFTERR BIT(7)
+#define DDRPHYC_PGSR_RVERR BIT(8)
+#define DDRPHYC_PGSR_RVEIRR BIT(9)
+
+#define DDRPHYC_DLLGCR_BPS200 BIT(23)
+
+#define DDRPHYC_ACDLLCR_DLLSRST BIT(30)
+#define DDRPHYC_ACDLLCR_DLLDIS BIT(31)
+
+#define DDRPHYC_PTR0_TDLLSRST_OFFSET 0
+#define DDRPHYC_PTR0_TDLLSRST_MASK GENMASK(5, 0)
+#define DDRPHYC_PTR0_TDLLLOCK_OFFSET 6
+#define DDRPHYC_PTR0_TDLLLOCK_MASK GENMASK(17, 6)
+#define DDRPHYC_PTR0_TITMSRST_OFFSET 18
+#define DDRPHYC_PTR0_TITMSRST_MASK GENMASK(21, 18)
+
+#define DDRPHYC_ACIOCR_ACPDD BIT(3)
+#define DDRPHYC_ACIOCR_ACPDR BIT(4)
+#define DDRPHYC_ACIOCR_CKPDD_MASK GENMASK(10, 8)
+#define DDRPHYC_ACIOCR_CKPDD_0 BIT(8)
+#define DDRPHYC_ACIOCR_CKPDR_MASK GENMASK(13, 11)
+#define DDRPHYC_ACIOCR_CKPDR_0 BIT(11)
+#define DDRPHYC_ACIOCR_CSPDD_MASK GENMASK(21, 18)
+#define DDRPHYC_ACIOCR_CSPDD_0 BIT(18)
+#define DDRPHYC_ACIOCR_RSTPDD BIT(27)
+#define DDRPHYC_ACIOCR_RSTPDR BIT(28)
+
+#define DDRPHYC_DXCCR_DXPDD BIT(2)
+#define DDRPHYC_DXCCR_DXPDR BIT(3)
+
+#define DDRPHYC_DSGCR_CKEPDD_MASK GENMASK(19, 16)
+#define DDRPHYC_DSGCR_CKEPDD_0 BIT(16)
+#define DDRPHYC_DSGCR_ODTPDD_MASK GENMASK(23, 20)
+#define DDRPHYC_DSGCR_ODTPDD_0 BIT(20)
+#define DDRPHYC_DSGCR_NL2PD BIT(24)
+
+#define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0)
+#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT 0
+#define DDRPHYC_ZQ0CRN_ZDEN BIT(28)
+#define DDRPHYC_ZQ0CRN_ZQPD BIT(31)
+
+#define DDRPHYC_DXNGCR_DXEN BIT(0)
+
+#define DDRPHYC_DXNDLLCR_DLLSRST BIT(30)
+#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31)
+#define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14)
+#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT 14
+
+#endif /* STM32MP1_DDR_REGS_H */
diff --git a/include/drivers/st/stm32mp1_pwr.h b/include/drivers/st/stm32mp1_pwr.h
new file mode 100644
index 0000000..e17df44
--- /dev/null
+++ b/include/drivers/st/stm32mp1_pwr.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP1_PWR_H
+#define STM32MP1_PWR_H
+
+#include <lib/utils_def.h>
+
+#define PWR_CR1 U(0x00)
+#define PWR_CR2 U(0x08)
+#define PWR_CR3 U(0x0C)
+#define PWR_MPUCR U(0x10)
+#define PWR_WKUPCR U(0x20)
+#define PWR_MPUWKUPENR U(0x28)
+
+#define PWR_CR1_LPDS BIT(0)
+#define PWR_CR1_LPCFG BIT(1)
+#define PWR_CR1_LVDS BIT(2)
+#define PWR_CR1_DBP BIT(8)
+
+#define PWR_CR3_DDRSREN BIT(10)
+#define PWR_CR3_DDRSRDIS BIT(11)
+#define PWR_CR3_DDRRETEN BIT(12)
+
+#define PWR_MPUCR_PDDS BIT(0)
+#define PWR_MPUCR_CSTDBYDIS BIT(3)
+#define PWR_MPUCR_CSSF BIT(9)
+
+#endif /* STM32MP1_PWR_H */
diff --git a/include/drivers/st/stm32mp1_ram.h b/include/drivers/st/stm32mp1_ram.h
new file mode 100644
index 0000000..38360e7
--- /dev/null
+++ b/include/drivers/st/stm32mp1_ram.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015-2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP1_RAM_H
+#define STM32MP1_RAM_H
+
+int stm32mp1_ddr_probe(void);
+
+#endif /* STM32MP1_RAM_H */
diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h
new file mode 100644
index 0000000..d794225
--- /dev/null
+++ b/include/drivers/st/stm32mp1_rcc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if STM32MP13
+#include "stm32mp13_rcc.h"
+#endif
+#if STM32MP15
+#include "stm32mp15_rcc.h"
+#endif
diff --git a/include/drivers/st/stm32mp1_usb.h b/include/drivers/st/stm32mp1_usb.h
new file mode 100644
index 0000000..06a34cb
--- /dev/null
+++ b/include/drivers/st/stm32mp1_usb.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP1_USB_H
+#define STM32MP1_USB_H
+
+#include <drivers/usb_device.h>
+
+void stm32mp1_usb_init_driver(struct usb_handle *usb_core_handle,
+ struct pcd_handle *pcd_handle,
+ void *base_register);
+
+#endif /* STM32MP1_USB_H */
diff --git a/include/drivers/st/stm32mp_clkfunc.h b/include/drivers/st/stm32mp_clkfunc.h
new file mode 100644
index 0000000..61286b2
--- /dev/null
+++ b/include/drivers/st/stm32mp_clkfunc.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_CLKFUNC_H
+#define STM32MP_CLKFUNC_H
+
+#include <stdbool.h>
+
+#include <libfdt.h>
+
+#include <platform_def.h>
+
+int fdt_osc_read_freq(const char *name, uint32_t *freq);
+bool fdt_clk_read_bool(const char *node_label, const char *prop_name);
+uint32_t fdt_clk_read_uint32_default(const char *node_label,
+ const char *prop_name,
+ uint32_t dflt_value);
+
+int fdt_rcc_read_uint32_array(const char *prop_name, uint32_t count,
+ uint32_t *array);
+int fdt_rcc_subnode_offset(const char *name);
+const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp);
+bool fdt_get_rcc_secure_state(void);
+
+int fdt_get_clock_id(int node);
+unsigned long fdt_get_uart_clock_freq(uintptr_t instance);
+
+void stm32mp_stgen_config(unsigned long rate);
+void stm32mp_stgen_restore_counter(unsigned long long value,
+ unsigned long long offset_in_ms);
+unsigned long long stm32mp_stgen_get_counter(void);
+
+#endif /* STM32MP_CLKFUNC_H */
diff --git a/include/drivers/st/stm32mp_ddr.h b/include/drivers/st/stm32mp_ddr.h
new file mode 100644
index 0000000..1efca42
--- /dev/null
+++ b/include/drivers/st/stm32mp_ddr.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+ */
+
+#ifndef STM32MP_DDR_H
+#define STM32MP_DDR_H
+
+#include <platform_def.h>
+
+enum stm32mp_ddr_base_type {
+ DDR_BASE,
+ DDRPHY_BASE,
+ NONE_BASE
+};
+
+enum stm32mp_ddr_reg_type {
+ REG_REG,
+ REG_TIMING,
+ REG_PERF,
+ REG_MAP,
+ REGPHY_REG,
+ REGPHY_TIMING,
+ REG_TYPE_NB
+};
+
+struct stm32mp_ddr_reg_desc {
+ const char *name;
+ uint16_t offset; /* Offset for base address */
+ uint8_t par_offset; /* Offset for parameter array */
+};
+
+struct stm32mp_ddr_reg_info {
+ const char *name;
+ const struct stm32mp_ddr_reg_desc *desc;
+ uint8_t size;
+ enum stm32mp_ddr_base_type base;
+};
+
+struct stm32mp_ddr_size {
+ uint64_t base;
+ uint64_t size;
+};
+
+struct stm32mp_ddr_priv {
+ struct stm32mp_ddr_size info;
+ struct stm32mp_ddrctl *ctl;
+ struct stm32mp_ddrphy *phy;
+ uintptr_t pwr;
+ uintptr_t rcc;
+};
+
+struct stm32mp_ddr_info {
+ const char *name;
+ uint32_t speed; /* in kHZ */
+ uint32_t size; /* Memory size in byte = col * row * width */
+};
+
+#define TIMEOUT_US_1S 1000000U
+
+void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_reg_type type,
+ const void *param, const struct stm32mp_ddr_reg_info *ddr_registers);
+void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl);
+void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl);
+void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl);
+int stm32mp_board_ddr_power_init(enum ddr_type ddr_type);
+
+#endif /* STM32MP_DDR_H */
diff --git a/include/drivers/st/stm32mp_ddr_test.h b/include/drivers/st/stm32mp_ddr_test.h
new file mode 100644
index 0000000..34e522a
--- /dev/null
+++ b/include/drivers/st/stm32mp_ddr_test.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_DDR_TEST_H
+#define STM32MP_DDR_TEST_H
+
+#include <stdint.h>
+
+uint32_t stm32mp_ddr_test_rw_access(void);
+uint32_t stm32mp_ddr_test_data_bus(void);
+uint32_t stm32mp_ddr_test_addr_bus(uint64_t size);
+uint32_t stm32mp_ddr_check_size(void);
+
+#endif /* STM32MP_DDR_TEST_H */
diff --git a/include/drivers/st/stm32mp_ddrctrl_regs.h b/include/drivers/st/stm32mp_ddrctrl_regs.h
new file mode 100644
index 0000000..79de86b
--- /dev/null
+++ b/include/drivers/st/stm32mp_ddrctrl_regs.h
@@ -0,0 +1,265 @@
+/*
+ * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+ */
+
+#ifndef STM32MP_DDRCTRL_REGS_H
+#define STM32MP_DDRCTRL_REGS_H
+
+#include <cdefs.h>
+#include <stdint.h>
+
+#include <lib/utils_def.h>
+
+/* DDR Controller (DDRCTRL) registers */
+struct stm32mp_ddrctl {
+ uint32_t mstr ; /* 0x0 Master */
+ uint32_t stat; /* 0x4 Operating Mode Status */
+ uint8_t reserved008[0x10 - 0x8];
+ uint32_t mrctrl0; /* 0x10 Control 0 */
+ uint32_t mrctrl1; /* 0x14 Control 1 */
+ uint32_t mrstat; /* 0x18 Status */
+ uint32_t mrctrl2; /* 0x1c Control 2 */
+ uint32_t derateen; /* 0x20 Temperature Derate Enable */
+ uint32_t derateint; /* 0x24 Temperature Derate Interval */
+ uint32_t reserved028;
+ uint32_t deratectl; /* 0x2c Temperature Derate Control */
+ uint32_t pwrctl; /* 0x30 Low Power Control */
+ uint32_t pwrtmg; /* 0x34 Low Power Timing */
+ uint32_t hwlpctl; /* 0x38 Hardware Low Power Control */
+ uint8_t reserved03c[0x50 - 0x3c];
+ uint32_t rfshctl0; /* 0x50 Refresh Control 0 */
+ uint32_t rfshctl1; /* 0x54 Refresh Control 1 */
+ uint32_t reserved058; /* 0x58 Refresh Control 2 */
+ uint32_t reserved05C;
+ uint32_t rfshctl3; /* 0x60 Refresh Control 0 */
+ uint32_t rfshtmg; /* 0x64 Refresh Timing */
+ uint32_t rfshtmg1; /* 0x68 Refresh Timing 1 */
+ uint8_t reserved06c[0xc0 - 0x6c];
+ uint32_t crcparctl0; /* 0xc0 CRC Parity Control0 */
+ uint32_t crcparctl1; /* 0xc4 CRC Parity Control1 */
+ uint32_t reserved0c8; /* 0xc8 CRC Parity Control2 */
+ uint32_t crcparstat; /* 0xcc CRC Parity Status */
+ uint32_t init0; /* 0xd0 SDRAM Initialization 0 */
+ uint32_t init1; /* 0xd4 SDRAM Initialization 1 */
+ uint32_t init2; /* 0xd8 SDRAM Initialization 2 */
+ uint32_t init3; /* 0xdc SDRAM Initialization 3 */
+ uint32_t init4; /* 0xe0 SDRAM Initialization 4 */
+ uint32_t init5; /* 0xe4 SDRAM Initialization 5 */
+ uint32_t init6; /* 0xe8 SDRAM Initialization 6 */
+ uint32_t init7; /* 0xec SDRAM Initialization 7 */
+ uint32_t dimmctl; /* 0xf0 DIMM Control */
+ uint32_t rankctl; /* 0xf4 Rank Control */
+ uint8_t reserved0f4[0x100 - 0xf8];
+ uint32_t dramtmg0; /* 0x100 SDRAM Timing 0 */
+ uint32_t dramtmg1; /* 0x104 SDRAM Timing 1 */
+ uint32_t dramtmg2; /* 0x108 SDRAM Timing 2 */
+ uint32_t dramtmg3; /* 0x10c SDRAM Timing 3 */
+ uint32_t dramtmg4; /* 0x110 SDRAM Timing 4 */
+ uint32_t dramtmg5; /* 0x114 SDRAM Timing 5 */
+ uint32_t dramtmg6; /* 0x118 SDRAM Timing 6 */
+ uint32_t dramtmg7; /* 0x11c SDRAM Timing 7 */
+ uint32_t dramtmg8; /* 0x120 SDRAM Timing 8 */
+ uint32_t dramtmg9; /* 0x124 SDRAM Timing 9 */
+ uint32_t dramtmg10; /* 0x128 SDRAM Timing 10 */
+ uint32_t dramtmg11; /* 0x12c SDRAM Timing 11 */
+ uint32_t dramtmg12; /* 0x130 SDRAM Timing 12 */
+ uint32_t dramtmg13; /* 0x134 SDRAM Timing 13 */
+ uint32_t dramtmg14; /* 0x138 SDRAM Timing 14 */
+ uint32_t dramtmg15; /* 0x13c SDRAM Timing 15 */
+ uint8_t reserved140[0x180 - 0x140];
+ uint32_t zqctl0; /* 0x180 ZQ Control 0 */
+ uint32_t zqctl1; /* 0x184 ZQ Control 1 */
+ uint32_t zqctl2; /* 0x188 ZQ Control 2 */
+ uint32_t zqstat; /* 0x18c ZQ Status */
+ uint32_t dfitmg0; /* 0x190 DFI Timing 0 */
+ uint32_t dfitmg1; /* 0x194 DFI Timing 1 */
+ uint32_t dfilpcfg0; /* 0x198 DFI Low Power Configuration 0 */
+ uint32_t dfilpcfg1; /* 0x19c DFI Low Power Configuration 1 */
+ uint32_t dfiupd0; /* 0x1a0 DFI Update 0 */
+ uint32_t dfiupd1; /* 0x1a4 DFI Update 1 */
+ uint32_t dfiupd2; /* 0x1a8 DFI Update 2 */
+ uint32_t reserved1ac;
+ uint32_t dfimisc; /* 0x1b0 DFI Miscellaneous Control */
+ uint32_t dfitmg2; /* 0x1b4 DFI Timing 2 */
+ uint32_t dfitmg3; /* 0x1b8 DFI Timing 3 */
+ uint32_t dfistat; /* 0x1bc DFI Status */
+ uint32_t dbictl; /* 0x1c0 DM/DBI Control */
+ uint32_t dfiphymstr; /* 0x1c4 DFI PHY Master interface */
+ uint8_t reserved1c8[0x200 - 0x1c8];
+ uint32_t addrmap0; /* 0x200 Address Map 0 */
+ uint32_t addrmap1; /* 0x204 Address Map 1 */
+ uint32_t addrmap2; /* 0x208 Address Map 2 */
+ uint32_t addrmap3; /* 0x20c Address Map 3 */
+ uint32_t addrmap4; /* 0x210 Address Map 4 */
+ uint32_t addrmap5; /* 0x214 Address Map 5 */
+ uint32_t addrmap6; /* 0x218 Address Map 6 */
+ uint32_t addrmap7; /* 0x21c Address Map 7 */
+ uint32_t addrmap8; /* 0x220 Address Map 8 */
+ uint32_t addrmap9; /* 0x224 Address Map 9 */
+ uint32_t addrmap10; /* 0x228 Address Map 10 */
+ uint32_t addrmap11; /* 0x22C Address Map 11 */
+ uint8_t reserved230[0x240 - 0x230];
+ uint32_t odtcfg; /* 0x240 ODT Configuration */
+ uint32_t odtmap; /* 0x244 ODT/Rank Map */
+ uint8_t reserved248[0x250 - 0x248];
+ uint32_t sched; /* 0x250 Scheduler Control */
+ uint32_t sched1; /* 0x254 Scheduler Control 1 */
+ uint32_t reserved258;
+ uint32_t perfhpr1; /* 0x25c High Priority Read CAM 1 */
+ uint32_t reserved260;
+ uint32_t perflpr1; /* 0x264 Low Priority Read CAM 1 */
+ uint32_t reserved268;
+ uint32_t perfwr1; /* 0x26c Write CAM 1 */
+ uint8_t reserved27c[0x300 - 0x270];
+ uint32_t dbg0; /* 0x300 Debug 0 */
+ uint32_t dbg1; /* 0x304 Debug 1 */
+ uint32_t dbgcam; /* 0x308 CAM Debug */
+ uint32_t dbgcmd; /* 0x30c Command Debug */
+ uint32_t dbgstat; /* 0x310 Status Debug */
+ uint8_t reserved314[0x320 - 0x314];
+ uint32_t swctl; /* 0x320 Software Programming Control Enable */
+ uint32_t swstat; /* 0x324 Software Programming Control Status */
+ uint8_t reserved328[0x36c - 0x328];
+ uint32_t poisoncfg; /* 0x36c AXI Poison Configuration Register */
+ uint32_t poisonstat; /* 0x370 AXI Poison Status Register */
+ uint8_t reserved374[0x3f0 - 0x374];
+ uint32_t deratestat; /* 0x3f0 Temperature Derate Status */
+ uint8_t reserved3f4[0x3fc - 0x3f4];
+
+ /* Multi Port registers */
+ uint32_t pstat; /* 0x3fc Port Status */
+ uint32_t pccfg; /* 0x400 Port Common Configuration */
+
+ /* PORT 0 */
+ uint32_t pcfgr_0; /* 0x404 Configuration Read */
+ uint32_t pcfgw_0; /* 0x408 Configuration Write */
+ uint8_t reserved40c[0x490 - 0x40c];
+ uint32_t pctrl_0; /* 0x490 Port Control Register */
+ uint32_t pcfgqos0_0; /* 0x494 Read QoS Configuration 0 */
+ uint32_t pcfgqos1_0; /* 0x498 Read QoS Configuration 1 */
+ uint32_t pcfgwqos0_0; /* 0x49c Write QoS Configuration 0 */
+ uint32_t pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1 */
+ uint8_t reserved4a4[0x4b4 - 0x4a4];
+
+#if STM32MP_DDR_DUAL_AXI_PORT
+ /* PORT 1 */
+ uint32_t pcfgr_1; /* 0x4b4 Configuration Read */
+ uint32_t pcfgw_1; /* 0x4b8 Configuration Write */
+ uint8_t reserved4bc[0x540 - 0x4bc];
+ uint32_t pctrl_1; /* 0x540 Port 2 Control Register */
+ uint32_t pcfgqos0_1; /* 0x544 Read QoS Configuration 0 */
+ uint32_t pcfgqos1_1; /* 0x548 Read QoS Configuration 1 */
+ uint32_t pcfgwqos0_1; /* 0x54c Write QoS Configuration 0 */
+ uint32_t pcfgwqos1_1; /* 0x550 Write QoS Configuration 1 */
+#endif
+
+ uint8_t reserved554[0xff0 - 0x554];
+ uint32_t umctl2_ver_number; /* 0xff0 UMCTL2 Version Number */
+} __packed;
+
+/* DDR Controller registers offsets */
+#define DDRCTRL_MSTR 0x000
+#define DDRCTRL_STAT 0x004
+#define DDRCTRL_MRCTRL0 0x010
+#define DDRCTRL_MRSTAT 0x018
+#define DDRCTRL_PWRCTL 0x030
+#define DDRCTRL_PWRTMG 0x034
+#define DDRCTRL_HWLPCTL 0x038
+#define DDRCTRL_RFSHCTL3 0x060
+#define DDRCTRL_RFSHTMG 0x064
+#define DDRCTRL_INIT0 0x0D0
+#define DDRCTRL_DFIMISC 0x1B0
+#define DDRCTRL_DBG1 0x304
+#define DDRCTRL_DBGCAM 0x308
+#define DDRCTRL_DBGCMD 0x30C
+#define DDRCTRL_DBGSTAT 0x310
+#define DDRCTRL_SWCTL 0x320
+#define DDRCTRL_SWSTAT 0x324
+#define DDRCTRL_PSTAT 0x3FC
+#define DDRCTRL_PCTRL_0 0x490
+#if STM32MP_DDR_DUAL_AXI_PORT
+#define DDRCTRL_PCTRL_1 0x540
+#endif
+
+/* DDR Controller Register fields */
+#define DDRCTRL_MSTR_DDR3 BIT(0)
+#define DDRCTRL_MSTR_LPDDR2 BIT(2)
+#define DDRCTRL_MSTR_LPDDR3 BIT(3)
+#define DDRCTRL_MSTR_DDR4 BIT(4)
+#define DDRCTRL_MSTR_LPDDR4 BIT(5)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL 0
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF BIT(12)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER BIT(13)
+#define DDRCTRL_MSTR_DLL_OFF_MODE BIT(15)
+
+#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
+#define DDRCTRL_STAT_OPERATING_MODE_NORMAL BIT(0)
+#define DDRCTRL_STAT_OPERATING_MODE_SR (BIT(0) | BIT(1))
+#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
+#define DDRCTRL_STAT_SELFREF_TYPE_ASR (BIT(4) | BIT(5))
+#define DDRCTRL_STAT_SELFREF_TYPE_SR BIT(5)
+
+#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE U(0)
+/* Only one rank supported */
+#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT 4
+#define DDRCTRL_MRCTRL0_MR_RANK_ALL \
+ BIT(DDRCTRL_MRCTRL0_MR_RANK_SHIFT)
+#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT 12
+#define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12)
+#define DDRCTRL_MRCTRL0_MR_WR BIT(31)
+
+#define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0)
+
+#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0)
+#define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1)
+#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3)
+#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5)
+
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16)
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16)
+
+#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0)
+#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL BIT(1)
+
+#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0)
+
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16
+
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK GENMASK(31, 30)
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL BIT(30)
+
+#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0)
+#define DDRCTRL_DFIMISC_DFI_INIT_START BIT(5)
+
+#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE BIT(0)
+
+#define DDRCTRL_DBG1_DIS_HIF BIT(1)
+
+#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29)
+#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28)
+#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26)
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8)
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0)
+#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \
+ (DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \
+ DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY)
+#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \
+ (DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \
+ DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \
+ DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH)
+
+#define DDRCTRL_DBGCMD_RANK0_REFRESH BIT(0)
+
+#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY BIT(0)
+
+#define DDRCTRL_SWCTL_SW_DONE BIT(0)
+
+#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0)
+
+#define DDRCTRL_PCTRL_N_PORT_EN BIT(0)
+
+#endif /* STM32MP_DDRCTRL_REGS_H */
diff --git a/include/drivers/st/stm32mp_pmic.h b/include/drivers/st/stm32mp_pmic.h
new file mode 100644
index 0000000..303c571
--- /dev/null
+++ b/include/drivers/st/stm32mp_pmic.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_PMIC_H
+#define STM32MP_PMIC_H
+
+#include <stdbool.h>
+
+#include <platform_def.h>
+
+/*
+ * dt_pmic_status - Check PMIC status from device tree
+ *
+ * Returns the status of the PMIC (secure, non-secure), or a negative value on
+ * error
+ */
+int dt_pmic_status(void);
+
+/*
+ * initialize_pmic_i2c - Initialize I2C for the PMIC control
+ *
+ * Returns true if PMIC is available, false if not found, panics on errors
+ */
+bool initialize_pmic_i2c(void);
+
+/*
+ * initialize_pmic - Main PMIC initialization function, called at platform init
+ *
+ * Panics on errors
+ */
+void initialize_pmic(void);
+
+#if DEBUG
+void print_pmic_info_and_debug(void);
+#else
+static inline void print_pmic_info_and_debug(void)
+{
+}
+#endif
+
+/*
+ * pmic_ddr_power_init - Initialize regulators required for DDR
+ *
+ * Returns 0 on success, and negative values on errors
+ */
+int pmic_ddr_power_init(enum ddr_type ddr_type);
+
+/*
+ * pmic_voltages_init - Update voltages for platform init
+ *
+ * Returns 0 on success, and negative values on errors
+ */
+int pmic_voltages_init(void);
+
+#endif /* STM32MP_PMIC_H */
diff --git a/include/drivers/st/stm32mp_ram.h b/include/drivers/st/stm32mp_ram.h
new file mode 100644
index 0000000..6e1e21d
--- /dev/null
+++ b/include/drivers/st/stm32mp_ram.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef STM32MP_RAM_H
+#define STM32MP_RAM_H
+
+#include <stdbool.h>
+
+#include <drivers/st/stm32mp_ddr.h>
+
+#define PARAM(x, y) \
+ { \
+ .name = x, \
+ .offset = offsetof(struct stm32mp_ddr_config, y), \
+ .size = sizeof(config.y) / sizeof(uint32_t), \
+ }
+
+#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x)
+#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x)
+
+struct stm32mp_ddr_param {
+ const char *name; /* Name in DT */
+ const uint32_t offset; /* Offset in config struct */
+ const uint32_t size; /* Size of parameters */
+};
+
+int stm32mp_ddr_dt_get_info(void *fdt, int node, struct stm32mp_ddr_info *info);
+int stm32mp_ddr_dt_get_param(void *fdt, int node, const struct stm32mp_ddr_param *param,
+ uint32_t param_size, uintptr_t config);
+
+#endif /* STM32MP_RAM_H */
diff --git a/include/drivers/st/stm32mp_reset.h b/include/drivers/st/stm32mp_reset.h
new file mode 100644
index 0000000..8444805
--- /dev/null
+++ b/include/drivers/st/stm32mp_reset.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_RESET_H
+#define STM32MP_RESET_H
+
+#include <stdint.h>
+
+/*
+ * Assert target reset, if @to_us non null, wait until reset is asserted
+ *
+ * @reset_id: Reset controller ID
+ * @to_us: Timeout in microsecond, or 0 if not waiting
+ * Return 0 on success and -ETIMEDOUT if waiting and timeout expired
+ */
+int stm32mp_reset_assert(uint32_t reset_id, unsigned int to_us);
+
+/*
+ * Enable reset control for target resource
+ *
+ * @reset_id: Reset controller ID
+ */
+static inline void stm32mp_reset_set(uint32_t reset_id)
+{
+ (void)stm32mp_reset_assert(reset_id, 0U);
+}
+
+/*
+ * Deassert target reset, if @to_us non null, wait until reset is deasserted
+ *
+ * @reset_id: Reset controller ID
+ * @to_us: Timeout in microsecond, or 0 if not waiting
+ * Return 0 on success and -ETIMEDOUT if waiting and timeout expired
+ */
+int stm32mp_reset_deassert(uint32_t reset_id, unsigned int to_us);
+
+/*
+ * Release reset control for target resource
+ *
+ * @reset_id: Reset controller ID
+ */
+static inline void stm32mp_reset_release(uint32_t reset_id)
+{
+ (void)stm32mp_reset_deassert(reset_id, 0U);
+}
+
+#endif /* STM32MP_RESET_H */
diff --git a/include/drivers/st/stpmic1.h b/include/drivers/st/stpmic1.h
new file mode 100644
index 0000000..2dfc7f8
--- /dev/null
+++ b/include/drivers/st/stpmic1.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STPMIC1_H
+#define STPMIC1_H
+
+#include <drivers/st/stm32_i2c.h>
+#include <lib/utils_def.h>
+
+#define TURN_ON_REG 0x1U
+#define TURN_OFF_REG 0x2U
+#define ICC_LDO_TURN_OFF_REG 0x3U
+#define ICC_BUCK_TURN_OFF_REG 0x4U
+#define RESET_STATUS_REG 0x5U
+#define VERSION_STATUS_REG 0x6U
+#define MAIN_CONTROL_REG 0x10U
+#define PADS_PULL_REG 0x11U
+#define BUCK_PULL_DOWN_REG 0x12U
+#define LDO14_PULL_DOWN_REG 0x13U
+#define LDO56_PULL_DOWN_REG 0x14U
+#define VIN_CONTROL_REG 0x15U
+#define PONKEY_TIMER_REG 0x16U
+#define MASK_RANK_BUCK_REG 0x17U
+#define MASK_RESET_BUCK_REG 0x18U
+#define MASK_RANK_LDO_REG 0x19U
+#define MASK_RESET_LDO_REG 0x1AU
+#define WATCHDOG_CONTROL_REG 0x1BU
+#define WATCHDOG_TIMER_REG 0x1CU
+#define BUCK_ICC_TURNOFF_REG 0x1DU
+#define LDO_ICC_TURNOFF_REG 0x1EU
+#define BUCK_APM_CONTROL_REG 0x1FU
+#define BUCK1_CONTROL_REG 0x20U
+#define BUCK2_CONTROL_REG 0x21U
+#define BUCK3_CONTROL_REG 0x22U
+#define BUCK4_CONTROL_REG 0x23U
+#define VREF_DDR_CONTROL_REG 0x24U
+#define LDO1_CONTROL_REG 0x25U
+#define LDO2_CONTROL_REG 0x26U
+#define LDO3_CONTROL_REG 0x27U
+#define LDO4_CONTROL_REG 0x28U
+#define LDO5_CONTROL_REG 0x29U
+#define LDO6_CONTROL_REG 0x2AU
+#define BUCK1_PWRCTRL_REG 0x30U
+#define BUCK2_PWRCTRL_REG 0x31U
+#define BUCK3_PWRCTRL_REG 0x32U
+#define BUCK4_PWRCTRL_REG 0x33U
+#define VREF_DDR_PWRCTRL_REG 0x34U
+#define LDO1_PWRCTRL_REG 0x35U
+#define LDO2_PWRCTRL_REG 0x36U
+#define LDO3_PWRCTRL_REG 0x37U
+#define LDO4_PWRCTRL_REG 0x38U
+#define LDO5_PWRCTRL_REG 0x39U
+#define LDO6_PWRCTRL_REG 0x3AU
+#define FREQUENCY_SPREADING_REG 0x3BU
+#define USB_CONTROL_REG 0x40U
+#define ITLATCH1_REG 0x50U
+#define ITLATCH2_REG 0x51U
+#define ITLATCH3_REG 0x52U
+#define ITLATCH4_REG 0x53U
+#define ITSETLATCH1_REG 0x60U
+#define ITSETLATCH2_REG 0x61U
+#define ITSETLATCH3_REG 0x62U
+#define ITSETLATCH4_REG 0x63U
+#define ITCLEARLATCH1_REG 0x70U
+#define ITCLEARLATCH2_REG 0x71U
+#define ITCLEARLATCH3_REG 0x72U
+#define ITCLEARLATCH4_REG 0x73U
+#define ITMASK1_REG 0x80U
+#define ITMASK2_REG 0x81U
+#define ITMASK3_REG 0x82U
+#define ITMASK4_REG 0x83U
+#define ITSETMASK1_REG 0x90U
+#define ITSETMASK2_REG 0x91U
+#define ITSETMASK3_REG 0x92U
+#define ITSETMASK4_REG 0x93U
+#define ITCLEARMASK1_REG 0xA0U
+#define ITCLEARMASK2_REG 0xA1U
+#define ITCLEARMASK3_REG 0xA2U
+#define ITCLEARMASK4_REG 0xA3U
+#define ITSOURCE1_REG 0xB0U
+#define ITSOURCE2_REG 0xB1U
+#define ITSOURCE3_REG 0xB2U
+#define ITSOURCE4_REG 0xB3U
+
+/* Registers masks */
+#define LDO_VOLTAGE_MASK GENMASK(6, 2)
+#define BUCK_VOLTAGE_MASK GENMASK(7, 2)
+#define LDO_BUCK_VOLTAGE_SHIFT 2
+#define LDO_BUCK_ENABLE_MASK BIT(0)
+#define LDO_BUCK_HPLP_ENABLE_MASK BIT(1)
+#define LDO_BUCK_HPLP_SHIFT 1
+#define LDO_BUCK_RANK_MASK BIT(0)
+#define LDO_BUCK_RESET_MASK BIT(0)
+#define LDO_BUCK_PULL_DOWN_MASK GENMASK(1, 0)
+
+/* Pull down register */
+#define BUCK1_PULL_DOWN_SHIFT 0
+#define BUCK2_PULL_DOWN_SHIFT 2
+#define BUCK3_PULL_DOWN_SHIFT 4
+#define BUCK4_PULL_DOWN_SHIFT 6
+#define VREF_DDR_PULL_DOWN_SHIFT 4
+
+/* ICC register */
+#define BUCK1_ICC_SHIFT 0
+#define BUCK2_ICC_SHIFT 1
+#define BUCK3_ICC_SHIFT 2
+#define BUCK4_ICC_SHIFT 3
+#define PWR_SW1_ICC_SHIFT 4
+#define PWR_SW2_ICC_SHIFT 5
+#define BOOST_ICC_SHIFT 6
+
+#define LDO1_ICC_SHIFT 0
+#define LDO2_ICC_SHIFT 1
+#define LDO3_ICC_SHIFT 2
+#define LDO4_ICC_SHIFT 3
+#define LDO5_ICC_SHIFT 4
+#define LDO6_ICC_SHIFT 5
+
+/* Buck Mask reset register */
+#define BUCK1_MASK_RESET 0
+#define BUCK2_MASK_RESET 1
+#define BUCK3_MASK_RESET 2
+#define BUCK4_MASK_RESET 3
+
+/* LDO Mask reset register */
+#define LDO1_MASK_RESET 0
+#define LDO2_MASK_RESET 1
+#define LDO3_MASK_RESET 2
+#define LDO4_MASK_RESET 3
+#define LDO5_MASK_RESET 4
+#define LDO6_MASK_RESET 5
+#define VREF_DDR_MASK_RESET 6
+
+/* LDO3 Special modes */
+#define LDO3_BYPASS BIT(7)
+#define LDO3_DDR_SEL 31U
+
+/* Main PMIC Control Register (MAIN_CONTROL_REG) */
+#define ICC_EVENT_ENABLED BIT(4)
+#define PWRCTRL_POLARITY_HIGH BIT(3)
+#define PWRCTRL_PIN_VALID BIT(2)
+#define RESTART_REQUEST_ENABLED BIT(1)
+#define SOFTWARE_SWITCH_OFF_ENABLED BIT(0)
+
+/* Main PMIC PADS Control Register (PADS_PULL_REG) */
+#define WAKEUP_DETECTOR_DISABLED BIT(4)
+#define PWRCTRL_PD_ACTIVE BIT(3)
+#define PWRCTRL_PU_ACTIVE BIT(2)
+#define WAKEUP_PD_ACTIVE BIT(1)
+#define PONKEY_PU_ACTIVE BIT(0)
+
+/* Main PMIC VINLOW Control Register (VIN_CONTROL_REGC DMSC) */
+#define SWIN_DETECTOR_ENABLED BIT(7)
+#define SWOUT_DETECTOR_ENABLED BIT(6)
+#define VINLOW_HYST_MASK GENMASK(1, 0)
+#define VINLOW_HYST_SHIFT 4
+#define VINLOW_THRESHOLD_MASK GENMASK(2, 0)
+#define VINLOW_THRESHOLD_SHIFT 1
+#define VINLOW_ENABLED BIT(0)
+#define VINLOW_CTRL_REG_MASK GENMASK(7, 0)
+
+/* USB Control Register */
+#define BOOST_OVP_DISABLED BIT(7)
+#define VBUS_OTG_DETECTION_DISABLED BIT(6)
+#define SW_OUT_DISCHARGE BIT(5)
+#define VBUS_OTG_DISCHARGE BIT(4)
+#define OCP_LIMIT_HIGH BIT(3)
+#define SWIN_SWOUT_ENABLED BIT(2)
+#define USBSW_OTG_SWITCH_ENABLED BIT(1)
+#define BOOST_ENABLED BIT(0)
+
+int stpmic1_powerctrl_on(void);
+int stpmic1_switch_off(void);
+int stpmic1_register_read(uint8_t register_id, uint8_t *value);
+int stpmic1_register_write(uint8_t register_id, uint8_t value);
+int stpmic1_register_update(uint8_t register_id, uint8_t value, uint8_t mask);
+int stpmic1_regulator_enable(const char *name);
+int stpmic1_regulator_disable(const char *name);
+bool stpmic1_is_regulator_enabled(const char *name);
+int stpmic1_regulator_voltage_set(const char *name, uint16_t millivolts);
+int stpmic1_regulator_levels_mv(const char *name, const uint16_t **levels,
+ size_t *levels_count);
+int stpmic1_regulator_voltage_get(const char *name);
+int stpmic1_regulator_pull_down_set(const char *name);
+int stpmic1_regulator_mask_reset_set(const char *name);
+int stpmic1_regulator_icc_set(const char *name);
+int stpmic1_regulator_sink_mode_set(const char *name);
+int stpmic1_regulator_bypass_mode_set(const char *name);
+int stpmic1_active_discharge_mode_set(const char *name);
+void stpmic1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr);
+
+int stpmic1_get_version(unsigned long *version);
+void stpmic1_dump_regulators(void);
+
+#endif /* STPMIC1_H */
diff --git a/include/drivers/synopsys/dw_mmc.h b/include/drivers/synopsys/dw_mmc.h
new file mode 100644
index 0000000..2004355
--- /dev/null
+++ b/include/drivers/synopsys/dw_mmc.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DW_MMC_H
+#define DW_MMC_H
+
+#include <drivers/mmc.h>
+
+typedef struct dw_mmc_params {
+ uintptr_t reg_base;
+ uintptr_t desc_base;
+ size_t desc_size;
+ int clk_rate;
+ int bus_width;
+ unsigned int flags;
+ enum mmc_device_type mmc_dev_type;
+} dw_mmc_params_t;
+
+void dw_mmc_init(dw_mmc_params_t *params, struct mmc_device_info *info);
+
+#endif /* DW_MMC_H */
diff --git a/include/drivers/ti/uart/uart_16550.h b/include/drivers/ti/uart/uart_16550.h
new file mode 100644
index 0000000..bddd997
--- /dev/null
+++ b/include/drivers/ti/uart/uart_16550.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef UART_16550_H
+#define UART_16550_H
+
+#include <drivers/console.h>
+
+/* UART16550 Registers */
+#define UARTTX 0x0
+#define UARTRX 0x0
+#define UARTDLL 0x0
+#define UARTIER 0x4
+#define UARTDLLM 0x4
+#define UARTIIR 0x8
+#define UARTFCR 0x8
+#define UARTLCR 0xc
+#define UARTMCR 0x10
+#define UARTLSR 0x14
+#define UARTMSR 0x18
+#define UARTSPR 0x1c
+#define UARTCSR 0x20
+/* Some instances have MDR1 defined as well */
+#define UARTMDR1 0x20
+#define UARTRXFIFOCFG 0x24
+#define UARTMIE 0x28
+#define UARTVNDR 0x2c
+#define UARTASR 0x3c
+
+/* FIFO Control Register bits */
+#define UARTFCR_FIFOMD_16450 (0 << 6)
+#define UARTFCR_FIFOMD_16550 (1 << 6)
+#define UARTFCR_RXTRIG_1 (0 << 6)
+#define UARTFCR_RXTRIG_4 (1 << 6)
+#define UARTFCR_RXTRIG_8 (2 << 6)
+#define UARTFCR_RXTRIG_16 (3 << 6)
+#define UARTFCR_TXTRIG_1 (0 << 4)
+#define UARTFCR_TXTRIG_4 (1 << 4)
+#define UARTFCR_TXTRIG_8 (2 << 4)
+#define UARTFCR_TXTRIG_16 (3 << 4)
+#define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */
+#define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */
+#define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */
+#define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */
+
+/* Line Control Register bits */
+#define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */
+#define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */
+#define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */
+#define UARTLCR_EVEN (1 << 4) /* Even Parity Format */
+#define UARTLCR_PAR (1 << 3) /* Parity */
+#define UARTLCR_STOP (1 << 2) /* Stop Bit */
+#define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */
+#define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */
+#define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */
+#define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */
+
+/* Line Status Register bits */
+#define UARTLSR_RXFIFOEMT (1 << 9) /* Rx Fifo Empty */
+#define UARTLSR_TXFIFOFULL (1 << 8) /* Tx Fifo Full */
+#define UARTLSR_RXFIFOERR (1 << 7) /* Rx Fifo Error */
+#define UARTLSR_TEMT (1 << 6) /* Tx Shift Register Empty */
+#define UARTLSR_THRE (1 << 5) /* Tx Holding Register Empty */
+#define UARTLSR_BRK (1 << 4) /* Break Condition Detected */
+#define UARTLSR_FERR (1 << 3) /* Framing Error */
+#define UARTLSR_PERR (1 << 3) /* Parity Error */
+#define UARTLSR_OVRF (1 << 2) /* Rx Overrun Error */
+#define UARTLSR_RDR_BIT (0) /* Rx Data Ready Bit */
+#define UARTLSR_RDR (1 << UARTLSR_RDR_BIT) /* Rx Data Ready */
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+/*
+ * Initialize a new 16550 console instance and register it with the console
+ * framework. The |console| pointer must point to storage that will be valid
+ * for the lifetime of the console, such as a global or static local variable.
+ * Its contents will be reinitialized from scratch.
+ * When |clock| has a value of 0, the UART will *not* be initialised. This
+ * means the UART should already be enabled and the baudrate and clock setup
+ * should have been done already, either by platform specific code or by
+ * previous firmware stages. The |baud| parameter will be ignored in this
+ * case as well.
+ */
+int console_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
+ console_t *console);
+
+#endif /*__ASSEMBLER__*/
+
+#endif /* UART_16550_H */
diff --git a/include/drivers/ufs.h b/include/drivers/ufs.h
new file mode 100644
index 0000000..1cd1bee
--- /dev/null
+++ b/include/drivers/ufs.h
@@ -0,0 +1,569 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef UFS_H
+#define UFS_H
+
+#include <lib/utils_def.h>
+
+/* register map of UFSHCI */
+/* Controller Capabilities */
+#define CAP 0x00
+#define CAP_NUTRS_MASK 0x1F
+
+/* UFS Version */
+#define VER 0x08
+/* Host Controller Identification - Product ID */
+#define HCDDID 0x10
+/* Host Controller Identification Descriptor - Manufacturer ID */
+#define HCPMID 0x14
+/* Auto-Hibernate Idle Timer */
+#define AHIT 0x18
+/* Interrupt Status */
+#define IS 0x20
+/* Interrupt Enable */
+#define IE 0x24
+/* System Bus Fatal Error Status */
+#define UFS_INT_SBFES (1 << 17)
+/* Host Controller Fatal Error Status */
+#define UFS_INT_HCFES (1 << 16)
+/* UTP Error Status */
+#define UFS_INT_UTPES (1 << 12)
+/* Device Fatal Error Status */
+#define UFS_INT_DFES (1 << 11)
+/* UIC Command Completion Status */
+#define UFS_INT_UCCS (1 << 10)
+/* UTP Task Management Request Completion Status */
+#define UFS_INT_UTMRCS (1 << 9)
+/* UIC Link Startup Status */
+#define UFS_INT_ULSS (1 << 8)
+/* UIC Link Lost Status */
+#define UFS_INT_ULLS (1 << 7)
+/* UIC Hibernate Enter Status */
+#define UFS_INT_UHES (1 << 6)
+/* UIC Hibernate Exit Status */
+#define UFS_INT_UHXS (1 << 5)
+/* UIC Power Mode Status */
+#define UFS_INT_UPMS (1 << 4)
+/* UIC Test Mode Status */
+#define UFS_INT_UTMS (1 << 3)
+/* UIC Error */
+#define UFS_INT_UE (1 << 2)
+/* UIC DME_ENDPOINTRESET Indication */
+#define UFS_INT_UDEPRI (1 << 1)
+/* UTP Transfer Request Completion Status */
+#define UFS_INT_UTRCS (1 << 0)
+
+/* Host Controller Status */
+#define HCS 0x30
+#define HCS_UPMCRS_MASK (7 << 8)
+#define HCS_PWR_LOCAL (1 << 8)
+#define HCS_UCRDY (1 << 3)
+#define HCS_UTMRLRDY (1 << 2)
+#define HCS_UTRLRDY (1 << 1)
+#define HCS_DP (1 << 0)
+
+/* Host Controller Enable */
+#define HCE 0x34
+#define HCE_ENABLE 1
+#define HCE_DISABLE 0
+
+/* Host UIC Error Code PHY Adapter Layer */
+#define UECPA 0x38
+/* Host UIC Error Code Data Link Layer */
+#define UECDL 0x3C
+/* Host UIC Error Code Network Layer */
+#define UECN 0x40
+/* Host UIC Error Code Transport Layer */
+#define UECT 0x44
+/* Host UIC Error Code */
+#define UECDME 0x48
+/* UTP Transfer Request Interrupt Aggregation Control Register */
+#define UTRIACR 0x4C
+#define UTRIACR_IAEN (1U << 31)
+#define UTRIACR_IAPWEN (1 << 24)
+#define UTRIACR_IASB (1 << 20)
+#define UTRIACR_CTR (1 << 16)
+#define UTRIACR_IACTH(x) (((x) & 0x1F) << 8)
+#define UTRIACR_IATOVAL(x) ((x) & 0xFF)
+
+/* UTP Transfer Request List Base Address */
+#define UTRLBA 0x50
+/* UTP Transfer Request List Base Address Upper 32-bits */
+#define UTRLBAU 0x54
+/* UTP Transfer Request List Door Bell Register */
+#define UTRLDBR 0x58
+/* UTP Transfer Request List Clear Register */
+#define UTRLCLR 0x5C
+/* UTP Transfer Request List Run Stop Register */
+#define UTRLRSR 0x60
+#define UTMRLBA 0x70
+#define UTMRLBAU 0x74
+#define UTMRLDBR 0x78
+#define UTMRLCLR 0x7C
+#define UTMRLRSR 0x80
+/* UIC Command */
+#define UICCMD 0x90
+/* UIC Command Argument 1 */
+#define UCMDARG1 0x94
+/* UIC Command Argument 2 */
+#define UCMDARG2 0x98
+/* UIC Command Argument 3 */
+#define UCMDARG3 0x9C
+
+#define UFS_BLOCK_SHIFT 12 /* 4KB */
+#define UFS_BLOCK_SIZE (1 << UFS_BLOCK_SHIFT)
+#define UFS_BLOCK_MASK (UFS_BLOCK_SIZE - 1)
+#define UFS_MAX_LUNS 8
+
+/* UTP Transfer Request Descriptor */
+/* Command Type */
+#define CT_UFS_STORAGE 1
+#define CT_SCSI 0
+
+/* Data Direction */
+#define DD_OUT 2 /* Device --> Host */
+#define DD_IN 1 /* Host --> Device */
+#define DD_NO_DATA_TRANSFER 0
+
+#define UTP_TRD_SIZE 32
+
+/* Transaction Type */
+#define TRANS_TYPE_HD (1 << 7) /* E2ECRC */
+#define TRANS_TYPE_DD (1 << 6)
+#define TRANS_TYPE_CODE_MASK 0x3F
+#define QUERY_RESPONSE_UPIU (0x36 << 0)
+#define READY_TO_TRANSACTION_UPIU (0x31 << 0)
+#define DATA_IN_UPIU (0x22 << 0)
+#define RESPONSE_UPIU (0x21 << 0)
+#define NOP_IN_UPIU (0x20 << 0)
+#define QUERY_REQUEST_UPIU (0x16 << 0)
+#define DATA_OUT_UPIU (0x02 << 0)
+#define CMD_UPIU (0x01 << 0)
+#define NOP_OUT_UPIU (0x00 << 0)
+
+#define OCS_SUCCESS 0x0
+#define OCS_INVALID_FUNC_ATTRIBUTE 0x1
+#define OCS_MISMATCH_REQUEST_SIZE 0x2
+#define OCS_MISMATCH_RESPONSE_SIZE 0x3
+#define OCS_PEER_COMMUNICATION_FAILURE 0x4
+#define OCS_ABORTED 0x5
+#define OCS_FATAL_ERROR 0x6
+#define OCS_MASK 0xF
+
+/* UIC Command */
+#define DME_GET 0x01
+#define DME_SET 0x02
+#define DME_PEER_GET 0x03
+#define DME_PEER_SET 0x04
+#define DME_POWERON 0x10
+#define DME_POWEROFF 0x11
+#define DME_ENABLE 0x12
+#define DME_RESET 0x14
+#define DME_ENDPOINTRESET 0x15
+#define DME_LINKSTARTUP 0x16
+#define DME_HIBERNATE_ENTER 0x17
+#define DME_HIBERNATE_EXIT 0x18
+#define DME_TEST_MODE 0x1A
+
+#define GEN_SELECTOR_IDX(x) ((x) & 0xFFFF)
+
+#define CONFIG_RESULT_CODE_MASK 0xFF
+
+#define CDBCMD_TEST_UNIT_READY 0x00
+#define CDBCMD_READ_6 0x08
+#define CDBCMD_WRITE_6 0x0A
+#define CDBCMD_START_STOP_UNIT 0x1B
+#define CDBCMD_READ_CAPACITY_10 0x25
+#define CDBCMD_READ_10 0x28
+#define CDBCMD_WRITE_10 0x2A
+#define CDBCMD_READ_16 0x88
+#define CDBCMD_WRITE_16 0x8A
+#define CDBCMD_READ_CAPACITY_16 0x9E
+#define CDBCMD_REPORT_LUNS 0xA0
+
+#define UPIU_FLAGS_R (1 << 6)
+#define UPIU_FLAGS_W (1 << 5)
+#define UPIU_FLAGS_ATTR_MASK (3 << 0)
+#define UPIU_FLAGS_ATTR_S (0 << 0) /* Simple */
+#define UPIU_FLAGS_ATTR_O (1 << 0) /* Ordered */
+#define UPIU_FLAGS_ATTR_HQ (2 << 0) /* Head of Queue */
+#define UPIU_FLAGS_ATTR_ACA (3 << 0)
+#define UPIU_FLAGS_O (1 << 6)
+#define UPIU_FLAGS_U (1 << 5)
+#define UPIU_FLAGS_D (1 << 4)
+
+#define QUERY_FUNC_STD_READ 0x01
+#define QUERY_FUNC_STD_WRITE 0x81
+
+#define QUERY_NOP 0x00
+#define QUERY_READ_DESC 0x01
+#define QUERY_WRITE_DESC 0x02
+#define QUERY_READ_ATTR 0x03
+#define QUERY_WRITE_ATTR 0x04
+#define QUERY_READ_FLAG 0x05
+#define QUERY_SET_FLAG 0x06
+#define QUERY_CLEAR_FLAG 0x07
+#define QUERY_TOGGLE_FLAG 0x08
+
+#define RW_WITHOUT_CACHE 0x18
+
+#define DESC_TYPE_DEVICE 0x00
+#define DESC_TYPE_CONFIGURATION 0x01
+#define DESC_TYPE_UNIT 0x02
+#define DESC_TYPE_INTERCONNECT 0x04
+#define DESC_TYPE_STRING 0x05
+
+#define DESC_DEVICE_MAX_SIZE 0x1F
+#define DEVICE_DESC_PARAM_MANF_ID 0x18
+
+#define ATTR_CUR_PWR_MODE 0x02 /* bCurrentPowerMode */
+#define ATTR_ACTIVECC 0x03 /* bActiveICCLevel */
+
+#define DEVICE_DESCRIPTOR_LEN 0x40
+#define UNIT_DESCRIPTOR_LEN 0x23
+
+#define QUERY_RESP_SUCCESS 0x00
+#define QUERY_RESP_OPCODE 0xFE
+#define QUERY_RESP_GENERAL_FAIL 0xFF
+
+#define SENSE_KEY_NO_SENSE 0x00
+#define SENSE_KEY_RECOVERED_ERROR 0x01
+#define SENSE_KEY_NOT_READY 0x02
+#define SENSE_KEY_MEDIUM_ERROR 0x03
+#define SENSE_KEY_HARDWARE_ERROR 0x04
+#define SENSE_KEY_ILLEGAL_REQUEST 0x05
+#define SENSE_KEY_UNIT_ATTENTION 0x06
+#define SENSE_KEY_DATA_PROTECT 0x07
+#define SENSE_KEY_BLANK_CHECK 0x08
+#define SENSE_KEY_VENDOR_SPECIFIC 0x09
+#define SENSE_KEY_COPY_ABORTED 0x0A
+#define SENSE_KEY_ABORTED_COMMAND 0x0B
+#define SENSE_KEY_VOLUME_OVERFLOW 0x0D
+#define SENSE_KEY_MISCOMPARE 0x0E
+
+#define SENSE_DATA_VALID 0x70
+#define SENSE_DATA_LENGTH 18
+
+#define READ_CAPACITY_LENGTH 8
+
+#define FLAG_DEVICE_INIT 0x01
+
+#define UFS_VENDOR_SKHYNIX U(0x1AD)
+
+#define MAX_MODEL_LEN 16
+
+/* maximum number of retries for a general UIC command */
+#define UFS_UIC_COMMAND_RETRIES 3
+
+/* maximum number of retries for a transfer command */
+#define UFS_CMD_RETRIES 3
+
+/* maximum number of retries for reading UFS capacity */
+#define UFS_READ_CAPACITY_RETRIES 10
+
+/* maximum number of link-startup retries */
+#define DME_LINKSTARTUP_RETRIES 10
+
+#define HCE_ENABLE_OUTER_RETRIES 3
+#define HCE_ENABLE_INNER_RETRIES 50
+#define HCE_ENABLE_TIMEOUT_US 100
+#define HCE_DISABLE_TIMEOUT_US 1000
+
+#define FDEVICEINIT_TIMEOUT_MS 1500
+
+/**
+ * ufs_dev_desc - ufs device details from the device descriptor
+ * @wmanufacturerid: card details
+ * @model: card model
+ */
+struct ufs_dev_desc {
+ uint16_t wmanufacturerid;
+ int8_t model[MAX_MODEL_LEN + 1];
+};
+
+/* UFS Driver Flags */
+#define UFS_FLAGS_SKIPINIT (1 << 0)
+#define UFS_FLAGS_VENDOR_SKHYNIX (U(1) << 2)
+
+typedef struct sense_data {
+ uint8_t resp_code : 7;
+ uint8_t valid : 1;
+ uint8_t reserved0;
+ uint8_t sense_key : 4;
+ uint8_t reserved1 : 1;
+ uint8_t ili : 1;
+ uint8_t eom : 1;
+ uint8_t file_mark : 1;
+ uint8_t info[4];
+ uint8_t asl;
+ uint8_t cmd_spec_len[4];
+ uint8_t asc;
+ uint8_t ascq;
+ uint8_t fruc;
+ uint8_t sense_key_spec0 : 7;
+ uint8_t sksv : 1;
+ uint8_t sense_key_spec1;
+ uint8_t sense_key_spec2;
+} sense_data_t;
+
+/* UTP Transfer Request Descriptor */
+typedef struct utrd_header {
+ uint32_t reserved0 : 24;
+ uint32_t i : 1; /* interrupt */
+ uint32_t dd : 2; /* data direction */
+ uint32_t reserved1 : 1;
+ uint32_t ct : 4; /* command type */
+ uint32_t reserved2;
+ uint32_t ocs : 8; /* Overall Command Status */
+ uint32_t reserved3 : 24;
+ uint32_t reserved4;
+ uint32_t ucdba; /* aligned to 128-byte */
+ uint32_t ucdbau; /* Upper 32-bits */
+ uint32_t rul : 16; /* Response UPIU Length */
+ uint32_t ruo : 16; /* Response UPIU Offset */
+ uint32_t prdtl : 16; /* PRDT Length */
+ uint32_t prdto : 16; /* PRDT Offset */
+} utrd_header_t; /* 8 words with little endian */
+
+/* UTP Task Management Request Descriptor */
+typedef struct utp_utmrd {
+ /* 4 words with little endian */
+ uint32_t reserved0 : 24;
+ uint32_t i : 1; /* interrupt */
+ uint32_t reserved1 : 7;
+ uint32_t reserved2;
+ uint32_t ocs : 8; /* Overall Command Status */
+ uint32_t reserved3 : 24;
+ uint32_t reserved4;
+
+ /* followed by 8 words UPIU with big endian */
+
+ /* followed by 8 words Response UPIU with big endian */
+} utp_utmrd_t;
+
+/* NOP OUT UPIU */
+typedef struct nop_out_upiu {
+ uint8_t trans_type;
+ uint8_t flags;
+ uint8_t reserved0;
+ uint8_t task_tag;
+ uint8_t reserved1;
+ uint8_t reserved2;
+ uint8_t reserved3;
+ uint8_t reserved4;
+ uint8_t total_ehs_len;
+ uint8_t reserved5;
+ uint16_t data_segment_len;
+ uint32_t reserved6;
+ uint32_t reserved7;
+ uint32_t reserved8;
+ uint32_t reserved9;
+ uint32_t reserved10;
+ uint32_t e2ecrc;
+} nop_out_upiu_t; /* 36 bytes with big endian */
+
+/* NOP IN UPIU */
+typedef struct nop_in_upiu {
+ uint8_t trans_type;
+ uint8_t flags;
+ uint8_t reserved0;
+ uint8_t task_tag;
+ uint8_t reserved1;
+ uint8_t reserved2;
+ uint8_t response;
+ uint8_t reserved3;
+ uint8_t total_ehs_len;
+ uint8_t dev_info;
+ uint16_t data_segment_len;
+ uint32_t reserved4;
+ uint32_t reserved5;
+ uint32_t reserved6;
+ uint32_t reserved7;
+ uint32_t reserved8;
+ uint32_t e2ecrc;
+} nop_in_upiu_t; /* 36 bytes with big endian */
+
+/* Command UPIU */
+typedef struct cmd_upiu {
+ uint8_t trans_type;
+ uint8_t flags;
+ uint8_t lun;
+ uint8_t task_tag;
+ uint8_t cmd_set_type;
+ uint8_t reserved0;
+ uint8_t reserved1;
+ uint8_t reserved2;
+ uint8_t total_ehs_len;
+ uint8_t reserved3;
+ uint16_t data_segment_len;
+ uint32_t exp_data_trans_len;
+ /*
+ * A CDB has a fixed length of 16bytes or a variable length
+ * of between 12 and 260 bytes
+ */
+ uint8_t cdb[16]; /* little endian */
+} cmd_upiu_t; /* 32 bytes with big endian except for cdb[] */
+
+typedef struct query_desc {
+ uint8_t opcode;
+ uint8_t idn;
+ uint8_t index;
+ uint8_t selector;
+ uint8_t reserved0[2];
+ uint16_t length;
+ uint32_t reserved2[2];
+} query_desc_t; /* 16 bytes with big endian */
+
+typedef struct query_flag {
+ uint8_t opcode;
+ uint8_t idn;
+ uint8_t index;
+ uint8_t selector;
+ uint8_t reserved0[7];
+ uint8_t value;
+ uint32_t reserved8;
+} query_flag_t; /* 16 bytes with big endian */
+
+typedef struct query_attr {
+ uint8_t opcode;
+ uint8_t idn;
+ uint8_t index;
+ uint8_t selector;
+ uint8_t reserved0[4];
+ uint32_t value; /* little endian */
+ uint32_t reserved4;
+} query_attr_t; /* 16 bytes with big endian except for value */
+
+/* Query Request UPIU */
+typedef struct query_upiu {
+ uint8_t trans_type;
+ uint8_t flags;
+ uint8_t reserved0;
+ uint8_t task_tag;
+ uint8_t reserved1;
+ uint8_t query_func;
+ uint8_t reserved2;
+ uint8_t reserved3;
+ uint8_t total_ehs_len;
+ uint8_t reserved4;
+ uint16_t data_segment_len;
+ /* Transaction Specific Fields */
+ union {
+ query_desc_t desc;
+ query_flag_t flag;
+ query_attr_t attr;
+ } ts;
+ uint32_t reserved5;
+} query_upiu_t; /* 32 bytes with big endian */
+
+/* Query Response UPIU */
+typedef struct query_resp_upiu {
+ uint8_t trans_type;
+ uint8_t flags;
+ uint8_t reserved0;
+ uint8_t task_tag;
+ uint8_t reserved1;
+ uint8_t query_func;
+ uint8_t query_resp;
+ uint8_t reserved2;
+ uint8_t total_ehs_len;
+ uint8_t dev_info;
+ uint16_t data_segment_len;
+ union {
+ query_desc_t desc;
+ query_flag_t flag;
+ query_attr_t attr;
+ } ts;
+ uint32_t reserved3;
+} query_resp_upiu_t; /* 32 bytes with big endian */
+
+/* Response UPIU */
+typedef struct resp_upiu {
+ uint8_t trans_type;
+ uint8_t flags;
+ uint8_t lun;
+ uint8_t task_tag;
+ uint8_t cmd_set_type;
+ uint8_t reserved0;
+ uint8_t reserved1;
+ uint8_t status;
+ uint8_t total_ehs_len;
+ uint8_t dev_info;
+ uint16_t data_segment_len;
+ uint32_t res_trans_cnt; /* Residual Transfer Count */
+ uint32_t reserved2[4];
+ uint16_t sense_data_len;
+ union {
+ uint8_t sense_data[18];
+ sense_data_t sense;
+ } sd;
+} resp_upiu_t; /* 52 bytes with big endian */
+
+typedef struct cmd_info {
+ uintptr_t buf;
+ size_t length;
+ int lba;
+ uint8_t op;
+ uint8_t direction;
+ uint8_t lun;
+} cmd_info_t;
+
+typedef struct utp_utrd {
+ uintptr_t header; /* utrd_header_t */
+ uintptr_t upiu;
+ uintptr_t resp_upiu;
+ uintptr_t prdt;
+ size_t size_upiu;
+ size_t size_resp_upiu;
+ size_t size_prdt;
+ int task_tag;
+} utp_utrd_t;
+
+/* Physical Region Description Table */
+typedef struct prdt {
+ uint32_t dba; /* Data Base Address */
+ uint32_t dbau; /* Data Base Address Upper 32-bits */
+ uint32_t reserved0;
+ uint32_t dbc : 18; /* Data Byte Count */
+ uint32_t reserved1 : 14;
+} prdt_t;
+
+typedef struct uic_cmd {
+ uint32_t op;
+ uint32_t arg1;
+ uint32_t arg2;
+ uint32_t arg3;
+} uic_cmd_t;
+
+typedef struct ufs_params {
+ uintptr_t reg_base;
+ uintptr_t desc_base;
+ size_t desc_size;
+ unsigned long flags;
+} ufs_params_t;
+
+typedef struct ufs_ops {
+ int (*phy_init)(ufs_params_t *params);
+ int (*phy_set_pwr_mode)(ufs_params_t *params);
+} ufs_ops_t;
+
+int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd);
+int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val);
+int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val);
+
+unsigned int ufs_read_attr(int idn);
+void ufs_write_attr(int idn, unsigned int value);
+unsigned int ufs_read_flag(int idn);
+void ufs_set_flag(int idn);
+void ufs_clear_flag(int idn);
+void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size);
+void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size);
+size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size);
+size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size);
+int ufs_init(const ufs_ops_t *ops, ufs_params_t *params);
+
+#endif /* UFS_H */
diff --git a/include/drivers/usb_device.h b/include/drivers/usb_device.h
new file mode 100644
index 0000000..8fdb6ae
--- /dev/null
+++ b/include/drivers/usb_device.h
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef USB_DEVICE_H
+#define USB_DEVICE_H
+
+#include <stdint.h>
+
+#include <lib/utils_def.h>
+
+#define USBD_MAX_NUM_INTERFACES 1U
+#define USBD_MAX_NUM_CONFIGURATION 1U
+
+#define USB_LEN_DEV_QUALIFIER_DESC 0x0AU
+#define USB_LEN_DEV_DESC 0x12U
+#define USB_LEN_CFG_DESC 0x09U
+#define USB_LEN_IF_DESC 0x09U
+#define USB_LEN_EP_DESC 0x07U
+#define USB_LEN_OTG_DESC 0x03U
+#define USB_LEN_LANGID_STR_DESC 0x04U
+#define USB_LEN_OTHER_SPEED_DESC_SIZ 0x09U
+
+#define USBD_IDX_LANGID_STR 0x00U
+#define USBD_IDX_MFC_STR 0x01U
+#define USBD_IDX_PRODUCT_STR 0x02U
+#define USBD_IDX_SERIAL_STR 0x03U
+#define USBD_IDX_CONFIG_STR 0x04U
+#define USBD_IDX_INTERFACE_STR 0x05U
+#define USBD_IDX_USER0_STR 0x06U
+
+#define USB_REQ_TYPE_STANDARD 0x00U
+#define USB_REQ_TYPE_CLASS 0x20U
+#define USB_REQ_TYPE_VENDOR 0x40U
+#define USB_REQ_TYPE_MASK 0x60U
+
+#define USB_REQ_RECIPIENT_DEVICE 0x00U
+#define USB_REQ_RECIPIENT_INTERFACE 0x01U
+#define USB_REQ_RECIPIENT_ENDPOINT 0x02U
+#define USB_REQ_RECIPIENT_MASK 0x1FU
+
+#define USB_REQ_DIRECTION 0x80U
+
+#define USB_REQ_GET_STATUS 0x00U
+#define USB_REQ_CLEAR_FEATURE 0x01U
+#define USB_REQ_SET_FEATURE 0x03U
+#define USB_REQ_SET_ADDRESS 0x05U
+#define USB_REQ_GET_DESCRIPTOR 0x06U
+#define USB_REQ_SET_DESCRIPTOR 0x07U
+#define USB_REQ_GET_CONFIGURATION 0x08U
+#define USB_REQ_SET_CONFIGURATION 0x09U
+#define USB_REQ_GET_INTERFACE 0x0AU
+#define USB_REQ_SET_INTERFACE 0x0BU
+#define USB_REQ_SYNCH_FRAME 0x0CU
+
+#define USB_DESC_TYPE_DEVICE 0x01U
+#define USB_DESC_TYPE_CONFIGURATION 0x02U
+#define USB_DESC_TYPE_STRING 0x03U
+#define USB_DESC_TYPE_INTERFACE 0x04U
+#define USB_DESC_TYPE_ENDPOINT 0x05U
+#define USB_DESC_TYPE_DEVICE_QUALIFIER 0x06U
+#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 0x07U
+#define USB_DESC_TYPE_BOS 0x0FU
+
+#define USB_CONFIG_REMOTE_WAKEUP 2U
+#define USB_CONFIG_SELF_POWERED 1U
+
+#define USB_MAX_EP0_SIZE 64U
+
+/* Device Status */
+#define USBD_STATE_DEFAULT 1U
+#define USBD_STATE_ADDRESSED 2U
+#define USBD_STATE_CONFIGURED 3U
+#define USBD_STATE_SUSPENDED 4U
+
+/* EP0 State */
+#define USBD_EP0_IDLE 0U
+#define USBD_EP0_SETUP 1U
+#define USBD_EP0_DATA_IN 2U
+#define USBD_EP0_DATA_OUT 3U
+#define USBD_EP0_STATUS_IN 4U
+#define USBD_EP0_STATUS_OUT 5U
+#define USBD_EP0_STALL 6U
+
+#define USBD_EP_TYPE_CTRL 0U
+#define USBD_EP_TYPE_ISOC 1U
+#define USBD_EP_TYPE_BULK 2U
+#define USBD_EP_TYPE_INTR 3U
+
+#define USBD_OUT_EPNUM_MASK GENMASK(15, 0)
+#define USBD_OUT_COUNT_MASK GENMASK(31, 16)
+#define USBD_OUT_COUNT_SHIFT 16U
+
+/* Number of EP supported, allow to reduce footprint: default max = 15 */
+#ifndef CONFIG_USBD_EP_NB
+#define USBD_EP_NB 15U
+#else
+#define USBD_EP_NB CONFIG_USBD_EP_NB
+#endif
+
+#define LOBYTE(x) ((uint8_t)((x) & 0x00FF))
+#define HIBYTE(x) ((uint8_t)(((x) & 0xFF00) >> 8))
+
+struct usb_setup_req {
+ uint8_t bm_request;
+ uint8_t b_request;
+ uint16_t value;
+ uint16_t index;
+ uint16_t length;
+};
+
+struct usb_handle;
+
+struct usb_class {
+ uint8_t (*init)(struct usb_handle *pdev, uint8_t cfgidx);
+ uint8_t (*de_init)(struct usb_handle *pdev, uint8_t cfgidx);
+ /* Control Endpoints */
+ uint8_t (*setup)(struct usb_handle *pdev, struct usb_setup_req *req);
+ uint8_t (*ep0_tx_sent)(struct usb_handle *pdev);
+ uint8_t (*ep0_rx_ready)(struct usb_handle *pdev);
+ /* Class Specific Endpoints */
+ uint8_t (*data_in)(struct usb_handle *pdev, uint8_t epnum);
+ uint8_t (*data_out)(struct usb_handle *pdev, uint8_t epnum);
+ uint8_t (*sof)(struct usb_handle *pdev);
+ uint8_t (*iso_in_incomplete)(struct usb_handle *pdev, uint8_t epnum);
+ uint8_t (*iso_out_incomplete)(struct usb_handle *pdev, uint8_t epnum);
+};
+
+/* Following USB Device status */
+enum usb_status {
+ USBD_OK = 0U,
+ USBD_BUSY,
+ USBD_FAIL,
+ USBD_TIMEOUT
+};
+
+/* Action to do after IT handling */
+enum usb_action {
+ USB_NOTHING = 0U,
+ USB_DATA_OUT,
+ USB_DATA_IN,
+ USB_SETUP,
+ USB_ENUM_DONE,
+ USB_READ_DATA_PACKET,
+ USB_READ_SETUP_PACKET,
+ USB_RESET,
+ USB_RESUME,
+ USB_SUSPEND,
+ USB_LPM,
+ USB_SOF,
+ USB_DISCONNECT,
+ USB_WRITE_EMPTY
+};
+
+/* USB Device descriptors structure */
+struct usb_desc {
+ uint8_t *(*get_device_desc)(uint16_t *length);
+ uint8_t *(*get_lang_id_desc)(uint16_t *length);
+ uint8_t *(*get_manufacturer_desc)(uint16_t *length);
+ uint8_t *(*get_product_desc)(uint16_t *length);
+ uint8_t *(*get_serial_desc)(uint16_t *length);
+ uint8_t *(*get_configuration_desc)(uint16_t *length);
+ uint8_t *(*get_interface_desc)(uint16_t *length);
+ uint8_t *(*get_usr_desc)(uint8_t index, uint16_t *length);
+ uint8_t *(*get_config_desc)(uint16_t *length);
+ uint8_t *(*get_device_qualifier_desc)(uint16_t *length);
+ /* optional: high speed capable device operating at its other speed */
+ uint8_t *(*get_other_speed_config_desc)(uint16_t *length);
+};
+
+/* USB Device handle structure */
+struct usb_endpoint {
+ uint32_t status;
+ uint32_t total_length;
+ uint32_t rem_length;
+ uint32_t maxpacket;
+};
+
+/*
+ * EndPoint descriptor
+ * num : Endpoint number, between 0 and 15 (limited by USBD_EP_NB)
+ * is_in: Endpoint direction
+ * type : Endpoint type
+ * maxpacket: Endpoint Max packet size: between 0 and 64KB
+ * xfer_buff: Pointer to transfer buffer
+ * xfer_len: Current transfer lengt
+ * hxfer_count: Partial transfer length in case of multi packet transfer
+ */
+struct usbd_ep {
+ uint8_t num;
+ bool is_in;
+ uint8_t type;
+ uint32_t maxpacket;
+ uint8_t *xfer_buff;
+ uint32_t xfer_len;
+ uint32_t xfer_count;
+};
+
+enum pcd_lpm_state {
+ LPM_L0 = 0x00U, /* on */
+ LPM_L1 = 0x01U, /* LPM L1 sleep */
+ LPM_L2 = 0x02U, /* suspend */
+ LPM_L3 = 0x03U, /* off */
+};
+
+/* USB Device descriptors structure */
+struct usb_driver {
+ enum usb_status (*ep0_out_start)(void *handle);
+ enum usb_status (*ep_start_xfer)(void *handle, struct usbd_ep *ep);
+ enum usb_status (*ep0_start_xfer)(void *handle, struct usbd_ep *ep);
+ enum usb_status (*write_packet)(void *handle, uint8_t *src,
+ uint8_t ch_ep_num, uint16_t len);
+ void *(*read_packet)(void *handle, uint8_t *dest, uint16_t len);
+ enum usb_status (*ep_set_stall)(void *handle, struct usbd_ep *ep);
+ enum usb_status (*start_device)(void *handle);
+ enum usb_status (*stop_device)(void *handle);
+ enum usb_status (*set_address)(void *handle, uint8_t address);
+ enum usb_status (*write_empty_tx_fifo)(void *handle,
+ uint32_t epnum, uint32_t xfer_len,
+ uint32_t *xfer_count,
+ uint32_t maxpacket,
+ uint8_t **xfer_buff);
+ enum usb_action (*it_handler)(void *handle, uint32_t *param);
+};
+
+/* USB Peripheral Controller Drivers */
+struct pcd_handle {
+ void *instance; /* Register base address */
+ struct usbd_ep in_ep[USBD_EP_NB]; /* IN endpoint parameters */
+ struct usbd_ep out_ep[USBD_EP_NB]; /* OUT endpoint parameters */
+ uint32_t setup[12]; /* Setup packet buffer */
+ enum pcd_lpm_state lpm_state; /* LPM State */
+};
+
+/* USB Device handle structure */
+struct usb_handle {
+ uint8_t id;
+ uint32_t dev_config;
+ uint32_t dev_config_status;
+ struct usb_endpoint ep_in[USBD_EP_NB];
+ struct usb_endpoint ep_out[USBD_EP_NB];
+ uint32_t ep0_state;
+ uint32_t ep0_data_len;
+ uint8_t dev_state;
+ uint8_t dev_old_state;
+ uint8_t dev_address;
+ uint32_t dev_remote_wakeup;
+ struct usb_setup_req request;
+ const struct usb_desc *desc;
+ struct usb_class *class;
+ void *class_data;
+ void *user_data;
+ struct pcd_handle *data;
+ const struct usb_driver *driver;
+};
+
+enum usb_status usb_core_handle_it(struct usb_handle *pdev);
+enum usb_status usb_core_receive(struct usb_handle *pdev, uint8_t ep_addr,
+ uint8_t *p_buf, uint32_t len);
+enum usb_status usb_core_transmit(struct usb_handle *pdev, uint8_t ep_addr,
+ uint8_t *p_buf, uint32_t len);
+enum usb_status usb_core_receive_ep0(struct usb_handle *pdev, uint8_t *p_buf,
+ uint32_t len);
+enum usb_status usb_core_transmit_ep0(struct usb_handle *pdev, uint8_t *p_buf,
+ uint32_t len);
+void usb_core_ctl_error(struct usb_handle *pdev);
+enum usb_status usb_core_start(struct usb_handle *pdev);
+enum usb_status usb_core_stop(struct usb_handle *pdev);
+enum usb_status register_usb_driver(struct usb_handle *pdev,
+ struct pcd_handle *pcd_handle,
+ const struct usb_driver *driver,
+ void *driver_handle);
+enum usb_status register_platform(struct usb_handle *pdev,
+ const struct usb_desc *plat_call_back);
+
+#endif /* USB_DEVICE_H */