diff options
Diffstat (limited to 'debian/grub-extras/disabled/gpxe/src/drivers')
80 files changed, 67397 insertions, 0 deletions
diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/bitbash/bitbash.c b/debian/grub-extras/disabled/gpxe/src/drivers/bitbash/bitbash.c new file mode 100644 index 0000000..3e558d5 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/bitbash/bitbash.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2006 Michael Brown <mbrown@fensystems.co.uk>. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <gpxe/bitbash.h> + +/** @file + * + * Bit-bashing interfaces + * + */ + +/** + * Set/clear output bit + * + * @v basher Bit-bashing interface + * @v bit_id Bit number + * @v data Value to write + * + * If @c data is 0, a logic 0 will be written. If @c data is + * non-zero, a logic 1 will be written. + */ +void write_bit ( struct bit_basher *basher, unsigned int bit_id, + unsigned long data ) { + basher->op->write ( basher, bit_id, ( data ? -1UL : 0 ) ); +} + +/** + * Read input bit + * + * @v basher Bit-bashing interface + * @v bit_id Bit number + * @ret data Value read + * + * @c data will always be either 0 or -1UL. The idea is that the + * caller can simply binary-AND the returned value with whatever mask + * it needs to apply. + */ +int read_bit ( struct bit_basher *basher, unsigned int bit_id ) { + return ( basher->op->read ( basher, bit_id ) ? -1UL : 0 ); +} diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/bitbash/i2c_bit.c b/debian/grub-extras/disabled/gpxe/src/drivers/bitbash/i2c_bit.c new file mode 100644 index 0000000..1319727 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/bitbash/i2c_bit.c @@ -0,0 +1,393 @@ +/* + * Copyright (C) 2006 Michael Brown <mbrown@fensystems.co.uk>. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <stddef.h> +#include <stdint.h> +#include <errno.h> +#include <string.h> +#include <assert.h> +#include <unistd.h> +#include <gpxe/bitbash.h> +#include <gpxe/i2c.h> + +/** @file + * + * I2C bit-bashing interface + * + * This implements a simple I2C master via a bit-bashing interface + * that provides two lines: SCL (clock) and SDA (data). + */ + +/** + * Delay between output state changes + * + * Max rated i2c speed (for the basic i2c protocol) is 100kbps, + * i.e. 200k clock transitions per second. + */ +static void i2c_delay ( void ) { + udelay ( I2C_UDELAY ); +} + +/** + * Set state of I2C SCL line + * + * @v basher Bit-bashing interface + * @v state New state of SCL + */ +static void setscl ( struct bit_basher *basher, int state ) { + DBG2 ( "%c", ( state ? '/' : '\\' ) ); + write_bit ( basher, I2C_BIT_SCL, state ); + i2c_delay(); +} + +/** + * Set state of I2C SDA line + * + * @v basher Bit-bashing interface + * @v state New state of SDA + */ +static void setsda ( struct bit_basher *basher, int state ) { + DBG2 ( "%c", ( state ? '1' : '0' ) ); + write_bit ( basher, I2C_BIT_SDA, state ); + i2c_delay(); +} + +/** + * Get state of I2C SDA line + * + * @v basher Bit-bashing interface + * @ret state State of SDA + */ +static int getsda ( struct bit_basher *basher ) { + int state; + state = read_bit ( basher, I2C_BIT_SDA ); + DBG2 ( "%c", ( state ? '+' : '-' ) ); + return state; +} + +/** + * Send an I2C start condition + * + * @v basher Bit-bashing interface + */ +static void i2c_start ( struct bit_basher *basher ) { + setscl ( basher, 1 ); + setsda ( basher, 0 ); + setscl ( basher, 0 ); + setsda ( basher, 1 ); +} + +/** + * Send an I2C data bit + * + * @v basher Bit-bashing interface + * @v bit Bit to send + */ +static void i2c_send_bit ( struct bit_basher *basher, int bit ) { + setsda ( basher, bit ); + setscl ( basher, 1 ); + setscl ( basher, 0 ); + setsda ( basher, 1 ); +} + +/** + * Receive an I2C data bit + * + * @v basher Bit-bashing interface + * @ret bit Received bit + */ +static int i2c_recv_bit ( struct bit_basher *basher ) { + int bit; + + setscl ( basher, 1 ); + bit = getsda ( basher ); + setscl ( basher, 0 ); + return bit; +} + +/** + * Send an I2C stop condition + * + * @v basher Bit-bashing interface + */ +static void i2c_stop ( struct bit_basher *basher ) { + setsda ( basher, 0 ); + setscl ( basher, 1 ); + setsda ( basher, 1 ); +} + +/** + * Send byte via I2C bus and check for acknowledgement + * + * @v basher Bit-bashing interface + * @v byte Byte to send + * @ret rc Return status code + * + * Sends a byte via the I2C bus and checks for an acknowledgement from + * the slave device. + */ +static int i2c_send_byte ( struct bit_basher *basher, uint8_t byte ) { + int i; + int ack; + + /* Send byte */ + DBG2 ( "[send %02x]", byte ); + for ( i = 8 ; i ; i-- ) { + i2c_send_bit ( basher, byte & 0x80 ); + byte <<= 1; + } + + /* Check for acknowledgement from slave */ + ack = ( i2c_recv_bit ( basher ) == 0 ); + DBG2 ( "%s", ( ack ? "[acked]" : "[not acked]" ) ); + + return ( ack ? 0 : -EIO ); +} + +/** + * Receive byte via I2C bus + * + * @v basher Bit-bashing interface + * @ret byte Received byte + * + * Receives a byte via the I2C bus and sends NACK to the slave device. + */ +static uint8_t i2c_recv_byte ( struct bit_basher *basher ) { + uint8_t byte = 0; + int i; + + /* Receive byte */ + for ( i = 8 ; i ; i-- ) { + byte <<= 1; + byte |= ( i2c_recv_bit ( basher ) & 0x1 ); + } + + /* Send NACK */ + i2c_send_bit ( basher, 1 ); + + DBG2 ( "[rcvd %02x]", byte ); + return byte; +} + +/** + * Select I2C device for reading or writing + * + * @v basher Bit-bashing interface + * @v i2cdev I2C device + * @v offset Starting offset within the device + * @v direction I2C_READ or I2C_WRITE + * @ret rc Return status code + */ +static int i2c_select ( struct bit_basher *basher, struct i2c_device *i2cdev, + unsigned int offset, unsigned int direction ) { + unsigned int address; + int shift; + unsigned int byte; + int rc; + + i2c_start ( basher ); + + /* Calculate address to appear on bus */ + address = ( ( ( i2cdev->dev_addr | + ( offset >> ( 8 * i2cdev->word_addr_len ) ) ) << 1 ) + | direction ); + + /* Send address a byte at a time */ + for ( shift = ( 8 * ( i2cdev->dev_addr_len - 1 ) ) ; + shift >= 0 ; shift -= 8 ) { + byte = ( ( address >> shift ) & 0xff ); + if ( ( rc = i2c_send_byte ( basher, byte ) ) != 0 ) + return rc; + } + + return 0; +} + +/** + * Reset I2C bus + * + * @v basher Bit-bashing interface + * @ret rc Return status code + * + * i2c devices often don't have a reset line, so even a reboot or + * system power cycle is sometimes not enough to bring them back to a + * known state. + */ +static int i2c_reset ( struct bit_basher *basher ) { + unsigned int i; + int sda; + + /* Clock through several cycles, waiting for an opportunity to + * pull SDA low while SCL is high (which creates a start + * condition). + */ + setscl ( basher, 0 ); + setsda ( basher, 1 ); + for ( i = 0 ; i < I2C_RESET_MAX_CYCLES ; i++ ) { + setscl ( basher, 1 ); + sda = getsda ( basher ); + if ( sda ) { + /* Now that the device will see a start, issue it */ + i2c_start ( basher ); + /* Stop the bus to leave it in a known good state */ + i2c_stop ( basher ); + DBGC ( basher, "I2CBIT %p reset after %d attempts\n", + basher, ( i + 1 ) ); + return 0; + } + setscl ( basher, 0 ); + } + + DBGC ( basher, "I2CBIT %p could not reset after %d attempts\n", + basher, i ); + return -ETIMEDOUT; +} + +/** + * Read data from I2C device via bit-bashing interface + * + * @v i2c I2C interface + * @v i2cdev I2C device + * @v offset Starting offset within the device + * @v data Data buffer + * @v len Length of data buffer + * @ret rc Return status code + * + * Note that attempting to read zero bytes of data is a valid way to + * check for I2C device presence. + */ +static int i2c_bit_read ( struct i2c_interface *i2c, + struct i2c_device *i2cdev, unsigned int offset, + uint8_t *data, unsigned int len ) { + struct i2c_bit_basher *i2cbit + = container_of ( i2c, struct i2c_bit_basher, i2c ); + struct bit_basher *basher = &i2cbit->basher; + int rc = 0; + + DBGC ( basher, "I2CBIT %p reading from device %x: ", + basher, i2cdev->dev_addr ); + + for ( ; ; data++, offset++ ) { + + /* Select device for writing */ + if ( ( rc = i2c_select ( basher, i2cdev, offset, + I2C_WRITE ) ) != 0 ) + break; + + /* Abort at end of data */ + if ( ! ( len-- ) ) + break; + + /* Select offset */ + if ( ( rc = i2c_send_byte ( basher, offset ) ) != 0 ) + break; + + /* Select device for reading */ + if ( ( rc = i2c_select ( basher, i2cdev, offset, + I2C_READ ) ) != 0 ) + break; + + /* Read byte */ + *data = i2c_recv_byte ( basher ); + DBGC ( basher, "%02x ", *data ); + } + + DBGC ( basher, "%s\n", ( rc ? "failed" : "" ) ); + i2c_stop ( basher ); + return rc; +} + +/** + * Write data to I2C device via bit-bashing interface + * + * @v i2c I2C interface + * @v i2cdev I2C device + * @v offset Starting offset within the device + * @v data Data buffer + * @v len Length of data buffer + * @ret rc Return status code + * + * Note that attempting to write zero bytes of data is a valid way to + * check for I2C device presence. + */ +static int i2c_bit_write ( struct i2c_interface *i2c, + struct i2c_device *i2cdev, unsigned int offset, + const uint8_t *data, unsigned int len ) { + struct i2c_bit_basher *i2cbit + = container_of ( i2c, struct i2c_bit_basher, i2c ); + struct bit_basher *basher = &i2cbit->basher; + int rc = 0; + + DBGC ( basher, "I2CBIT %p writing to device %x: ", + basher, i2cdev->dev_addr ); + + for ( ; ; data++, offset++ ) { + + /* Select device for writing */ + if ( ( rc = i2c_select ( basher, i2cdev, offset, + I2C_WRITE ) ) != 0 ) + break; + + /* Abort at end of data */ + if ( ! ( len-- ) ) + break; + + /* Select offset */ + if ( ( rc = i2c_send_byte ( basher, offset ) ) != 0 ) + break; + + /* Write data to device */ + DBGC ( basher, "%02x ", *data ); + if ( ( rc = i2c_send_byte ( basher, *data ) ) != 0 ) + break; + } + + DBGC ( basher, "%s\n", ( rc ? "failed" : "" ) ); + i2c_stop ( basher ); + return rc; +} + +/** + * Initialise I2C bit-bashing interface + * + * @v i2cbit I2C bit-bashing interface + * @v bash_op Bit-basher operations + */ +int init_i2c_bit_basher ( struct i2c_bit_basher *i2cbit, + struct bit_basher_operations *bash_op ) { + struct bit_basher *basher = &i2cbit->basher; + int rc; + + /* Initialise data structures */ + basher->op = bash_op; + assert ( basher->op->read != NULL ); + assert ( basher->op->write != NULL ); + i2cbit->i2c.read = i2c_bit_read; + i2cbit->i2c.write = i2c_bit_write; + + /* Reset I2C bus */ + if ( ( rc = i2c_reset ( basher ) ) != 0 ) { + DBGC ( basher, "I2CBIT %p could not reset I2C bus: %s\n", + basher, strerror ( rc ) ); + return rc; + } + + return 0; +} diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/bitbash/spi_bit.c b/debian/grub-extras/disabled/gpxe/src/drivers/bitbash/spi_bit.c new file mode 100644 index 0000000..8e70393 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/bitbash/spi_bit.c @@ -0,0 +1,225 @@ +/* + * Copyright (C) 2006 Michael Brown <mbrown@fensystems.co.uk>. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <stddef.h> +#include <stdint.h> +#include <string.h> +#include <byteswap.h> +#include <errno.h> +#include <assert.h> +#include <unistd.h> +#include <gpxe/bitbash.h> +#include <gpxe/spi_bit.h> + +/** @file + * + * SPI bit-bashing interface + * + */ + +/** Delay between SCLK changes and around SS changes */ +static void spi_bit_delay ( void ) { + udelay ( SPI_BIT_UDELAY ); +} + +/** Chip select line will be asserted */ +#define SELECT_SLAVE 0 + +/** Chip select line will be deasserted */ +#define DESELECT_SLAVE SPI_MODE_SSPOL + +/** + * Select/deselect slave + * + * @v spibit SPI bit-bashing interface + * @v slave Slave number + * @v state Slave select state + * + * @c state must be @c SELECT_SLAVE or @c DESELECT_SLAVE. + */ +static void spi_bit_set_slave_select ( struct spi_bit_basher *spibit, + unsigned int slave, + unsigned int state ) { + struct bit_basher *basher = &spibit->basher; + + state ^= ( spibit->bus.mode & SPI_MODE_SSPOL ); + DBGC2 ( spibit, "SPIBIT %p setting slave %d select %s\n", + spibit, slave, ( state ? "high" : "low" ) ); + + spi_bit_delay(); + write_bit ( basher, SPI_BIT_SS ( slave ), state ); + spi_bit_delay(); +} + +/** + * Transfer bits over SPI bit-bashing bus + * + * @v bus SPI bus + * @v data_out TX data buffer (or NULL) + * @v data_in RX data buffer (or NULL) + * @v len Length of transfer (in @b bits) + * @v endianness Endianness of this data transfer + * + * This issues @c len clock cycles on the SPI bus, shifting out data + * from the @c data_out buffer to the MOSI line and shifting in data + * from the MISO line to the @c data_in buffer. If @c data_out is + * NULL, then the data sent will be all zeroes. If @c data_in is + * NULL, then the incoming data will be discarded. + */ +static void spi_bit_transfer ( struct spi_bit_basher *spibit, + const void *data_out, void *data_in, + unsigned int len, int endianness ) { + struct spi_bus *bus = &spibit->bus; + struct bit_basher *basher = &spibit->basher; + unsigned int sclk = ( ( bus->mode & SPI_MODE_CPOL ) ? 1 : 0 ); + unsigned int cpha = ( ( bus->mode & SPI_MODE_CPHA ) ? 1 : 0 ); + unsigned int bit_offset; + unsigned int byte_offset; + unsigned int byte_mask; + unsigned int bit; + unsigned int step; + + DBGC2 ( spibit, "SPIBIT %p transferring %d bits in mode %#x\n", + spibit, len, bus->mode ); + + for ( step = 0 ; step < ( len * 2 ) ; step++ ) { + /* Calculate byte offset and byte mask */ + bit_offset = ( ( endianness == SPI_BIT_BIG_ENDIAN ) ? + ( len - ( step / 2 ) - 1 ) : ( step / 2 ) ); + byte_offset = ( bit_offset / 8 ); + byte_mask = ( 1 << ( bit_offset % 8 ) ); + + /* Shift data in or out */ + if ( sclk == cpha ) { + const uint8_t *byte; + + /* Shift data out */ + if ( data_out ) { + byte = ( data_out + byte_offset ); + bit = ( *byte & byte_mask ); + DBGCP ( spibit, "SPIBIT %p wrote bit %d\n", + spibit, ( bit ? 1 : 0 ) ); + } else { + bit = 0; + } + write_bit ( basher, SPI_BIT_MOSI, bit ); + } else { + uint8_t *byte; + + /* Shift data in */ + bit = read_bit ( basher, SPI_BIT_MISO ); + if ( data_in ) { + DBGCP ( spibit, "SPIBIT %p read bit %d\n", + spibit, ( bit ? 1 : 0 ) ); + byte = ( data_in + byte_offset ); + *byte &= ~byte_mask; + *byte |= ( bit & byte_mask ); + } + } + + /* Toggle clock line */ + spi_bit_delay(); + sclk ^= 1; + write_bit ( basher, SPI_BIT_SCLK, sclk ); + } +} + +/** + * Read/write data via SPI bit-bashing bus + * + * @v bus SPI bus + * @v device SPI device + * @v command Command + * @v address Address to read/write (<0 for no address) + * @v data_out TX data buffer (or NULL) + * @v data_in RX data buffer (or NULL) + * @v len Length of transfer + * @ret rc Return status code + */ +static int spi_bit_rw ( struct spi_bus *bus, struct spi_device *device, + unsigned int command, int address, + const void *data_out, void *data_in, size_t len ) { + struct spi_bit_basher *spibit + = container_of ( bus, struct spi_bit_basher, bus ); + uint32_t tmp_command; + uint32_t tmp_address; + uint32_t tmp_address_detect; + + /* Set clock line to idle state */ + write_bit ( &spibit->basher, SPI_BIT_SCLK, + ( bus->mode & SPI_MODE_CPOL ) ); + + /* Assert chip select on specified slave */ + spi_bit_set_slave_select ( spibit, device->slave, SELECT_SLAVE ); + + /* Transmit command */ + assert ( device->command_len <= ( 8 * sizeof ( tmp_command ) ) ); + tmp_command = cpu_to_le32 ( command ); + spi_bit_transfer ( spibit, &tmp_command, NULL, device->command_len, + SPI_BIT_BIG_ENDIAN ); + + /* Transmit address, if present */ + if ( address >= 0 ) { + assert ( device->address_len <= ( 8 * sizeof ( tmp_address ))); + tmp_address = cpu_to_le32 ( address ); + if ( device->address_len == SPI_AUTODETECT_ADDRESS_LEN ) { + /* Autodetect address length. This relies on + * the device responding with a dummy zero + * data bit before the first real data bit. + */ + DBGC ( spibit, "SPIBIT %p autodetecting device " + "address length\n", spibit ); + assert ( address == 0 ); + device->address_len = 0; + do { + spi_bit_transfer ( spibit, &tmp_address, + &tmp_address_detect, 1, + SPI_BIT_BIG_ENDIAN ); + device->address_len++; + } while ( le32_to_cpu ( tmp_address_detect ) & 1 ); + DBGC ( spibit, "SPIBIT %p autodetected device address " + "length %d\n", spibit, device->address_len ); + } else { + spi_bit_transfer ( spibit, &tmp_address, NULL, + device->address_len, + SPI_BIT_BIG_ENDIAN ); + } + } + + /* Transmit/receive data */ + spi_bit_transfer ( spibit, data_out, data_in, ( len * 8 ), + spibit->endianness ); + + /* Deassert chip select on specified slave */ + spi_bit_set_slave_select ( spibit, device->slave, DESELECT_SLAVE ); + + return 0; +} + +/** + * Initialise SPI bit-bashing interface + * + * @v spibit SPI bit-bashing interface + */ +void init_spi_bit_basher ( struct spi_bit_basher *spibit ) { + assert ( &spibit->basher.op->read != NULL ); + assert ( &spibit->basher.op->write != NULL ); + spibit->bus.rw = spi_bit_rw; +} diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/block/scsi.c b/debian/grub-extras/disabled/gpxe/src/drivers/block/scsi.c new file mode 100644 index 0000000..a51b3af --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/block/scsi.c @@ -0,0 +1,366 @@ +/* + * Copyright (C) 2006 Michael Brown <mbrown@fensystems.co.uk>. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <stddef.h> +#include <stdlib.h> +#include <string.h> +#include <byteswap.h> +#include <errno.h> +#include <gpxe/blockdev.h> +#include <gpxe/process.h> +#include <gpxe/scsi.h> + +/** @file + * + * SCSI block device + * + */ + +/** Maximum number of dummy "read capacity (10)" operations + * + * These are issued at connection setup to draw out various useless + * power-on messages. + */ +#define SCSI_MAX_DUMMY_READ_CAP 10 + +static inline __attribute__ (( always_inline )) struct scsi_device * +block_to_scsi ( struct block_device *blockdev ) { + return container_of ( blockdev, struct scsi_device, blockdev ); +} + +/** + * Handle SCSI command with no backing device + * + * @v scsi SCSI device + * @v command SCSI command + * @ret rc Return status code + */ +int scsi_detached_command ( struct scsi_device *scsi __unused, + struct scsi_command *command __unused ) { + return -ENODEV; +} + +/** + * Issue SCSI command + * + * @v scsi SCSI device + * @v command SCSI command + * @ret rc Return status code + */ +static int scsi_command ( struct scsi_device *scsi, + struct scsi_command *command ) { + int rc; + + DBGC2 ( scsi, "SCSI %p " SCSI_CDB_FORMAT "\n", + scsi, SCSI_CDB_DATA ( command->cdb ) ); + + /* Clear sense response code before issuing command */ + command->sense_response = 0; + + /* Flag command as in-progress */ + command->rc = -EINPROGRESS; + + /* Issue SCSI command */ + if ( ( rc = scsi->command ( scsi, command ) ) != 0 ) { + /* Something went wrong with the issuing mechanism */ + DBGC ( scsi, "SCSI %p " SCSI_CDB_FORMAT " err %s\n", + scsi, SCSI_CDB_DATA ( command->cdb ), strerror ( rc ) ); + return rc; + } + + /* Wait for command to complete */ + while ( command->rc == -EINPROGRESS ) + step(); + if ( ( rc = command->rc ) != 0 ) { + /* Something went wrong with the command execution */ + DBGC ( scsi, "SCSI %p " SCSI_CDB_FORMAT " err %s\n", + scsi, SCSI_CDB_DATA ( command->cdb ), strerror ( rc ) ); + return rc; + } + + /* Check for SCSI errors */ + if ( command->status != 0 ) { + DBGC ( scsi, "SCSI %p " SCSI_CDB_FORMAT " status %02x sense " + "%02x\n", scsi, SCSI_CDB_DATA ( command->cdb ), + command->status, command->sense_response ); + return -EIO; + } + + return 0; +} + +/** + * Read block from SCSI device using READ (10) + * + * @v blockdev Block device + * @v block LBA block number + * @v count Block count + * @v buffer Data buffer + * @ret rc Return status code + */ +static int scsi_read_10 ( struct block_device *blockdev, uint64_t block, + unsigned long count, userptr_t buffer ) { + struct scsi_device *scsi = block_to_scsi ( blockdev ); + struct scsi_command command; + struct scsi_cdb_read_10 *cdb = &command.cdb.read10; + + /* Issue READ (10) */ + memset ( &command, 0, sizeof ( command ) ); + cdb->opcode = SCSI_OPCODE_READ_10; + cdb->lba = cpu_to_be32 ( block ); + cdb->len = cpu_to_be16 ( count ); + command.data_in = buffer; + command.data_in_len = ( count * blockdev->blksize ); + return scsi_command ( scsi, &command ); +} + +/** + * Read block from SCSI device using READ (16) + * + * @v blockdev Block device + * @v block LBA block number + * @v count Block count + * @v buffer Data buffer + * @ret rc Return status code + */ +static int scsi_read_16 ( struct block_device *blockdev, uint64_t block, + unsigned long count, userptr_t buffer ) { + struct scsi_device *scsi = block_to_scsi ( blockdev ); + struct scsi_command command; + struct scsi_cdb_read_16 *cdb = &command.cdb.read16; + + /* Issue READ (16) */ + memset ( &command, 0, sizeof ( command ) ); + cdb->opcode = SCSI_OPCODE_READ_16; + cdb->lba = cpu_to_be64 ( block ); + cdb->len = cpu_to_be32 ( count ); + command.data_in = buffer; + command.data_in_len = ( count * blockdev->blksize ); + return scsi_command ( scsi, &command ); +} + +/** + * Write block to SCSI device using WRITE (10) + * + * @v blockdev Block device + * @v block LBA block number + * @v count Block count + * @v buffer Data buffer + * @ret rc Return status code + */ +static int scsi_write_10 ( struct block_device *blockdev, uint64_t block, + unsigned long count, userptr_t buffer ) { + struct scsi_device *scsi = block_to_scsi ( blockdev ); + struct scsi_command command; + struct scsi_cdb_write_10 *cdb = &command.cdb.write10; + + /* Issue WRITE (10) */ + memset ( &command, 0, sizeof ( command ) ); + cdb->opcode = SCSI_OPCODE_WRITE_10; + cdb->lba = cpu_to_be32 ( block ); + cdb->len = cpu_to_be16 ( count ); + command.data_out = buffer; + command.data_out_len = ( count * blockdev->blksize ); + return scsi_command ( scsi, &command ); +} + +/** + * Write block to SCSI device using WRITE (16) + * + * @v blockdev Block device + * @v block LBA block number + * @v count Block count + * @v buffer Data buffer + * @ret rc Return status code + */ +static int scsi_write_16 ( struct block_device *blockdev, uint64_t block, + unsigned long count, userptr_t buffer ) { + struct scsi_device *scsi = block_to_scsi ( blockdev ); + struct scsi_command command; + struct scsi_cdb_write_16 *cdb = &command.cdb.write16; + + /* Issue WRITE (16) */ + memset ( &command, 0, sizeof ( command ) ); + cdb->opcode = SCSI_OPCODE_WRITE_16; + cdb->lba = cpu_to_be64 ( block ); + cdb->len = cpu_to_be32 ( count ); + command.data_out = buffer; + command.data_out_len = ( count * blockdev->blksize ); + return scsi_command ( scsi, &command ); +} + +/** + * Read capacity of SCSI device via READ CAPACITY (10) + * + * @v blockdev Block device + * @ret rc Return status code + */ +static int scsi_read_capacity_10 ( struct block_device *blockdev ) { + struct scsi_device *scsi = block_to_scsi ( blockdev ); + struct scsi_command command; + struct scsi_cdb_read_capacity_10 *cdb = &command.cdb.readcap10; + struct scsi_capacity_10 capacity; + int rc; + + /* Issue READ CAPACITY (10) */ + memset ( &command, 0, sizeof ( command ) ); + cdb->opcode = SCSI_OPCODE_READ_CAPACITY_10; + command.data_in = virt_to_user ( &capacity ); + command.data_in_len = sizeof ( capacity ); + + if ( ( rc = scsi_command ( scsi, &command ) ) != 0 ) + return rc; + + /* Fill in block device fields */ + blockdev->blksize = be32_to_cpu ( capacity.blksize ); + blockdev->blocks = ( be32_to_cpu ( capacity.lba ) + 1 ); + + return 0; +} + +/** + * Read capacity of SCSI device via READ CAPACITY (16) + * + * @v blockdev Block device + * @ret rc Return status code + */ +static int scsi_read_capacity_16 ( struct block_device *blockdev ) { + struct scsi_device *scsi = block_to_scsi ( blockdev ); + struct scsi_command command; + struct scsi_cdb_read_capacity_16 *cdb = &command.cdb.readcap16; + struct scsi_capacity_16 capacity; + int rc; + + /* Issue READ CAPACITY (16) */ + memset ( &command, 0, sizeof ( command ) ); + cdb->opcode = SCSI_OPCODE_SERVICE_ACTION_IN; + cdb->service_action = SCSI_SERVICE_ACTION_READ_CAPACITY_16; + cdb->len = cpu_to_be32 ( sizeof ( capacity ) ); + command.data_in = virt_to_user ( &capacity ); + command.data_in_len = sizeof ( capacity ); + + if ( ( rc = scsi_command ( scsi, &command ) ) != 0 ) + return rc; + + /* Fill in block device fields */ + blockdev->blksize = be32_to_cpu ( capacity.blksize ); + blockdev->blocks = ( be64_to_cpu ( capacity.lba ) + 1 ); + return 0; +} + +static struct block_device_operations scsi_operations_16 = { + .read = scsi_read_16, + .write = scsi_write_16, +}; + +static struct block_device_operations scsi_operations_10 = { + .read = scsi_read_10, + .write = scsi_write_10, +}; + +/** + * Initialise SCSI device + * + * @v scsi SCSI device + * @ret rc Return status code + * + * Initialises a SCSI device. The scsi_device::command and + * scsi_device::lun fields must already be filled in. This function + * will configure scsi_device::blockdev, including issuing a READ + * CAPACITY call to determine the block size and total device size. + */ +int init_scsidev ( struct scsi_device *scsi ) { + unsigned int i; + int rc; + + /* Issue some theoretically extraneous READ CAPACITY (10) + * commands, solely in order to draw out the "CHECK CONDITION + * (power-on occurred)", "CHECK CONDITION (reported LUNs data + * has changed)" etc. that some dumb targets insist on sending + * as an error at start of day. The precise command that we + * use is unimportant; we just need to provide the target with + * an opportunity to send its responses. + */ + for ( i = 0 ; i < SCSI_MAX_DUMMY_READ_CAP ; i++ ) { + if ( ( rc = scsi_read_capacity_10 ( &scsi->blockdev ) ) == 0 ) + break; + DBGC ( scsi, "SCSI %p ignoring start-of-day error (#%d)\n", + scsi, ( i + 1 ) ); + } + + /* Try READ CAPACITY (10), which is a mandatory command, first. */ + scsi->blockdev.op = &scsi_operations_10; + if ( ( rc = scsi_read_capacity_10 ( &scsi->blockdev ) ) != 0 ) { + DBGC ( scsi, "SCSI %p could not READ CAPACITY (10): %s\n", + scsi, strerror ( rc ) ); + return rc; + } + + /* If capacity range was exceeded (i.e. capacity.lba was + * 0xffffffff, meaning that blockdev->blocks is now zero), use + * READ CAPACITY (16) instead. READ CAPACITY (16) is not + * mandatory, so we can't just use it straight off. + */ + if ( scsi->blockdev.blocks == 0 ) { + scsi->blockdev.op = &scsi_operations_16; + if ( ( rc = scsi_read_capacity_16 ( &scsi->blockdev ) ) != 0 ){ + DBGC ( scsi, "SCSI %p could not READ CAPACITY (16): " + "%s\n", scsi, strerror ( rc ) ); + return rc; + } + } + + DBGC ( scsi, "SCSI %p using READ/WRITE (%d) commands\n", scsi, + ( ( scsi->blockdev.op == &scsi_operations_10 ) ? 10 : 16 ) ); + DBGC ( scsi, "SCSI %p capacity is %ld MB (%#llx blocks)\n", scsi, + ( ( unsigned long ) ( scsi->blockdev.blocks >> 11 ) ), + scsi->blockdev.blocks ); + + return 0; +} + +/** + * Parse SCSI LUN + * + * @v lun_string LUN string representation + * @v lun LUN to fill in + * @ret rc Return status code + */ +int scsi_parse_lun ( const char *lun_string, struct scsi_lun *lun ) { + char *p; + int i; + + memset ( lun, 0, sizeof ( *lun ) ); + if ( lun_string ) { + p = ( char * ) lun_string; + for ( i = 0 ; i < 4 ; i++ ) { + lun->u16[i] = htons ( strtoul ( p, &p, 16 ) ); + if ( *p == '\0' ) + break; + if ( *p != '-' ) + return -EINVAL; + p++; + } + if ( *p ) + return -EINVAL; + } + + return 0; +} diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/3c509.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c509.c new file mode 100644 index 0000000..1c58f77 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c509.c @@ -0,0 +1,432 @@ +/* + * Split out into 3c509.c and 3c5x9.c, to make it possible to build a + * 3c529 module without including ISA, ISAPnP and EISA code. + * + */ + +FILE_LICENCE ( BSD2 ); + +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <errno.h> +#include <gpxe/io.h> +#include <unistd.h> +#include <gpxe/device.h> +#include <gpxe/isa.h> +#include "3c509.h" + +/* + * 3c509 cards have their own method of contention resolution; this + * effectively defines another bus type similar to ISAPnP. Even the + * original ISA cards can be programatically mapped to any I/O address + * in the range 0x200-0x3e0. + * + * However, there is a small problem: once you've activated a card, + * the only ways to deactivate it will also wipe its tag, meaning that + * you won't be able to subsequently reactivate it without going + * through the whole ID sequence again. The solution we adopt is to + * isolate and tag all cards at the start, and to immediately + * re-isolate and re-tag a card after disabling it. + * + */ + +static void t509bus_remove ( struct root_device *rootdev ); + +static unsigned int t509_id_port = 0; +static unsigned int t509_max_tag = 0; + +/** A 3c509 device */ +struct t509_device { + /** Generic device */ + struct device dev; + /** Tag */ + unsigned int tag; + /** I/O address */ + uint16_t ioaddr; + /** Driver-private data + * + * Use t509_set_drvdata() and t509_get_drvdata() to access + * this field. + */ + void *priv; +}; + +/** + * Set 3c509 driver-private data + * + * @v t509 3c509 device + * @v priv Private data + */ +static inline void t509_set_drvdata ( struct t509_device *t509, void *priv ) { + t509->priv = priv; +} + +/** + * Get 3c509 driver-private data + * + * @v t509 3c509 device + * @ret priv Private data + */ +static inline void * t509_get_drvdata ( struct t509_device *t509 ) { + return t509->priv; +} + +/* + * t509 utility functions + * + */ + +static inline void t509_set_id_port ( void ) { + outb ( 0x00, t509_id_port ); +} + +static inline void t509_wait_for_id_sequence ( void ) { + outb ( 0x00, t509_id_port ); +} + +static inline void t509_global_reset ( void ) { + outb ( 0xc0, t509_id_port ); +} + +static inline void t509_reset_tag ( void ) { + outb ( 0xd0, t509_id_port ); +} + +static inline void t509_set_tag ( uint8_t tag ) { + outb ( 0xd0 | tag, t509_id_port ); +} + +static inline void t509_select_tag ( uint8_t tag ) { + outb ( 0xd8 | tag, t509_id_port ); +} + +static inline void t509_activate ( uint16_t ioaddr ) { + outb ( 0xe0 | ( ioaddr >> 4 ), t509_id_port ); +} + +static inline void t509_deactivate_and_reset_tag ( uint16_t ioaddr ) { + outb ( GLOBAL_RESET, ioaddr + EP_COMMAND ); +} + +static inline void t509_load_eeprom_word ( uint8_t offset ) { + outb ( 0x80 | offset, t509_id_port ); +} + +/* + * Find a suitable ID port + * + */ +static inline int t509_find_id_port ( void ) { + + for ( t509_id_port = EP_ID_PORT_START ; + t509_id_port < EP_ID_PORT_END ; + t509_id_port += EP_ID_PORT_INC ) { + t509_set_id_port (); + /* See if anything's listening */ + outb ( 0xff, t509_id_port ); + if ( inb ( t509_id_port ) & 0x01 ) { + /* Found a suitable port */ + DBG ( "T509 using ID port at %04x\n", t509_id_port ); + return 0; + } + } + /* No id port available */ + DBG ( "T509 found no available ID port\n" ); + return -ENOENT; +} + +/* + * Send ID sequence to the ID port + * + */ +static void t509_send_id_sequence ( void ) { + unsigned short lrs_state, i; + + t509_set_id_port (); + /* Reset IDS on cards */ + t509_wait_for_id_sequence (); + lrs_state = 0xff; + for ( i = 0; i < 255; i++ ) { + outb ( lrs_state, t509_id_port ); + lrs_state <<= 1; + lrs_state = lrs_state & 0x100 ? lrs_state ^ 0xcf : lrs_state; + } +} + +/* + * We get eeprom data from the id_port given an offset into the eeprom. + * Basically; after the ID_sequence is sent to all of the cards; they enter + * the ID_CMD state where they will accept command requests. 0x80-0xbf loads + * the eeprom data. We then read the port 16 times and with every read; the + * cards check for contention (ie: if one card writes a 0 bit and another + * writes a 1 bit then the host sees a 0. At the end of the cycle; each card + * compares the data on the bus; if there is a difference then that card goes + * into ID_WAIT state again). In the meantime; one bit of data is returned in + * the AX register which is conveniently returned to us by inb(). Hence; we + * read 16 times getting one bit of data with each read. + */ +static uint16_t t509_id_read_eeprom ( int offset ) { + int i, data = 0; + + t509_load_eeprom_word ( offset ); + /* Do we really need this wait? Won't be noticeable anyway */ + udelay(10000); + + for ( i = 0; i < 16; i++ ) { + data = ( data << 1 ) | ( inw ( t509_id_port ) & 1 ); + } + return data; +} + +/* + * Isolate and tag all t509 cards + * + */ +static int t509_isolate ( void ) { + unsigned int i; + uint16_t contend[3]; + int rc; + + /* Find a suitable ID port */ + if ( ( rc = t509_find_id_port() ) != 0 ) + return rc; + + while ( 1 ) { + + /* All cards are in ID_WAIT state each time we go + * through this loop. + */ + + /* Send the ID sequence */ + t509_send_id_sequence(); + + /* First time through, reset all tags. On subsequent + * iterations, kill off any already-tagged cards + */ + if ( t509_max_tag == 0 ) { + t509_reset_tag(); + } else { + t509_select_tag ( 0 ); + } + + /* Read the manufacturer ID, to see if there are any + * more cards + */ + if ( t509_id_read_eeprom ( EEPROM_MFG_ID ) != MFG_ID ) { + DBG ( "T509 saw %s signs of life\n", + t509_max_tag ? "no further" : "no" ); + break; + } + + /* Perform contention selection on the MAC address */ + for ( i = 0 ; i < 3 ; i++ ) { + contend[i] = t509_id_read_eeprom ( i ); + } + + /* Only one device will still be left alive. Tag it. */ + ++t509_max_tag; + DBG ( "T509 found card %04x%04x%04x, assigning tag %02x\n", + contend[0], contend[1], contend[2], t509_max_tag ); + t509_set_tag ( t509_max_tag ); + + /* Return all cards back to ID_WAIT state */ + t509_wait_for_id_sequence(); + } + + DBG ( "T509 found %d cards using ID port %04x\n", + t509_max_tag, t509_id_port ); + return 0; +} + +/* + * Activate a T509 device + * + * The device will be enabled at whatever ioaddr is specified in the + * struct t509_device; there is no need to stick with the default + * ioaddr read from the EEPROM. + * + */ +static inline void activate_t509_device ( struct t509_device *t509 ) { + t509_send_id_sequence (); + t509_select_tag ( t509->tag ); + t509_activate ( t509->ioaddr ); + DBG ( "T509 activated device %02x at ioaddr %04x\n", + t509->tag, t509->ioaddr ); +} + +/* + * Deactivate a T509 device + * + * Disabling also clears the tag, so we immediately isolate and re-tag + * this card. + * + */ +static inline void deactivate_t509_device ( struct t509_device *t509 ) { + t509_deactivate_and_reset_tag ( t509->ioaddr ); + udelay ( 1000 ); + t509_send_id_sequence (); + t509_select_tag ( 0 ); + t509_set_tag ( t509->tag ); + t509_wait_for_id_sequence (); + DBG ( "T509 deactivated device at %04x and re-tagged as %02x\n", + t509->ioaddr, t509->tag ); +} + +/* + * The ISA probe function + * + */ +static int legacy_t509_probe ( struct nic *nic, void *hwdev ) { + struct t509_device *t509 = hwdev; + + /* We could change t509->ioaddr if we wanted to */ + activate_t509_device ( t509 ); + nic->ioaddr = t509->ioaddr; + + /* Hand off to generic t5x9 probe routine */ + return t5x9_probe ( nic, ISA_PROD_ID ( PROD_ID ), ISA_PROD_ID_MASK ); +} + +static void legacy_t509_disable ( struct nic *nic, void *hwdev ) { + struct t509_device *t509 = hwdev; + + t5x9_disable ( nic ); + deactivate_t509_device ( t509 ); +} + +static inline void legacy_t509_set_drvdata ( void *hwdev, void *priv ) { + t509_set_drvdata ( hwdev, priv ); +} + +static inline void * legacy_t509_get_drvdata ( void *hwdev ) { + return t509_get_drvdata ( hwdev ); +} + +/** + * Probe a 3c509 device + * + * @v t509 3c509 device + * @ret rc Return status code + * + * Searches for a driver for the 3c509 device. If a driver is found, + * its probe() routine is called. + */ +static int t509_probe ( struct t509_device *t509 ) { + DBG ( "Adding 3c509 device %02x (I/O %04x)\n", + t509->tag, t509->ioaddr ); + return legacy_probe ( t509, legacy_t509_set_drvdata, &t509->dev, + legacy_t509_probe, legacy_t509_disable ); +} + +/** + * Remove a 3c509 device + * + * @v t509 3c509 device + */ +static void t509_remove ( struct t509_device *t509 ) { + legacy_remove ( t509, legacy_t509_get_drvdata, legacy_t509_disable ); + DBG ( "Removed 3c509 device %02x\n", t509->tag ); +} + +/** + * Probe 3c509 root bus + * + * @v rootdev 3c509 bus root device + * + * Scans the 3c509 bus for devices and registers all devices it can + * find. + */ +static int t509bus_probe ( struct root_device *rootdev ) { + struct t509_device *t509 = NULL; + unsigned int tag; + unsigned int iobase; + int rc; + + /* Perform isolation and tagging */ + if ( ( rc = t509_isolate() ) != 0 ) + return rc; + + for ( tag = 1 ; tag <= t509_max_tag ; tag++ ) { + /* Allocate struct t509_device */ + if ( ! t509 ) + t509 = malloc ( sizeof ( *t509 ) ); + if ( ! t509 ) { + rc = -ENOMEM; + goto err; + } + memset ( t509, 0, sizeof ( *t509 ) ); + t509->tag = tag; + + /* Send the ID sequence */ + t509_send_id_sequence (); + + /* Select the specified tag */ + t509_select_tag ( t509->tag ); + + /* Read the default I/O address */ + iobase = t509_id_read_eeprom ( EEPROM_ADDR_CFG ); + t509->ioaddr = 0x200 + ( ( iobase & 0x1f ) << 4 ); + + /* Send card back to ID_WAIT */ + t509_wait_for_id_sequence(); + + /* Add to device hierarchy */ + snprintf ( t509->dev.name, sizeof ( t509->dev.name ), + "t509%02x", tag ); + t509->dev.desc.bus_type = BUS_TYPE_ISA; + t509->dev.desc.vendor = MFG_ID; + t509->dev.desc.device = PROD_ID; + t509->dev.parent = &rootdev->dev; + list_add ( &t509->dev.siblings, &rootdev->dev.children ); + INIT_LIST_HEAD ( &t509->dev.children ); + + /* Look for a driver */ + if ( t509_probe ( t509 ) == 0 ) { + /* t509dev registered, we can drop our ref */ + t509 = NULL; + } else { + /* Not registered; re-use struct */ + list_del ( &t509->dev.siblings ); + } + } + + free ( t509 ); + return 0; + + err: + free ( t509 ); + t509bus_remove ( rootdev ); + return rc; +} + +/** + * Remove 3c509 root bus + * + * @v rootdev 3c509 bus root device + */ +static void t509bus_remove ( struct root_device *rootdev ) { + struct t509_device *t509; + struct t509_device *tmp; + + list_for_each_entry_safe ( t509, tmp, &rootdev->dev.children, + dev.siblings ) { + t509_remove ( t509 ); + list_del ( &t509->dev.siblings ); + free ( t509 ); + } +} + +/** 3c509 bus root device driver */ +static struct root_driver t509_root_driver = { + .probe = t509bus_probe, + .remove = t509bus_remove, +}; + +/** 3c509 bus root device */ +struct root_device t509_root_device __root_device = { + .dev = { .name = "3c509" }, + .driver = &t509_root_driver, +}; + +ISA_ROM ( "3c509", "3c509" ); diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/3c509.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c509.h new file mode 100644 index 0000000..f030d4b --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c509.h @@ -0,0 +1,394 @@ +/* + * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. 2. The name + * of the author may not be used to endorse or promote products derived from + * this software withough specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by: + * + October 2, 1994 + + Modified by: Andres Vega Garcia + + INRIA - Sophia Antipolis, France + e-mail: avega@sophia.inria.fr + finger: avega@pax.inria.fr + + */ + +FILE_LICENCE ( BSD3 ); + +#include "nic.h" + +/* + * Ethernet software status per interface. + */ +/* + * Some global constants + */ + +#define TX_INIT_RATE 16 +#define TX_INIT_MAX_RATE 64 +#define RX_INIT_LATENCY 64 +#define RX_INIT_EARLY_THRESH 64 +#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */ +#define MIN_RX_EARLY_THRESHL 4 + +#define EEPROMSIZE 0x40 +#define MAX_EEPROMBUSY 1000 +#define EP_ID_PORT_START 0x110 /* avoid 0x100 to avoid conflict with SB16 */ +#define EP_ID_PORT_INC 0x10 +#define EP_ID_PORT_END 0x200 +#define EP_TAG_MAX 0x7 /* must be 2^n - 1 */ + +/* + * Commands to read/write EEPROM trough EEPROM command register (Window 0, + * Offset 0xa) + */ +#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ +#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ +#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ +#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ + +#define EEPROM_BUSY (1<<15) +#define EEPROM_TST_MODE (1<<14) + +/* + * Some short functions, worth to let them be a macro + */ +#define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY) +#define GO_WINDOW(b,x) outw(WINDOW_SELECT|(x), (b)+EP_COMMAND) + +/************************************************************************** + * + * These define the EEPROM data structure. They are used in the probe + * function to verify the existance of the adapter after having sent + * the ID_Sequence. + * + * There are others but only the ones we use are defined here. + * + **************************************************************************/ + +#define EEPROM_NODE_ADDR_0 0x0 /* Word */ +#define EEPROM_NODE_ADDR_1 0x1 /* Word */ +#define EEPROM_NODE_ADDR_2 0x2 /* Word */ +#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ +#define EEPROM_MFG_ID 0x7 /* 0x6d50 */ +#define EEPROM_ADDR_CFG 0x8 /* Base addr */ +#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ + +/************************************************************************** + * + * These are the registers for the 3Com 3c509 and their bit patterns when + * applicable. They have been taken out the the "EtherLink III Parallel + * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual + * from 3com. + * + * Getting this document out of 3Com is almost impossible. However, + * archived copies are available at + * http://www.osdever.net/cottontail/downloads/docs/3c5x9b.zip and + * several other places on the web (search for 3c5x9b.pdf). + * + **************************************************************************/ + +#define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a + * command reg. */ +#define EP_STATUS 0x0e /* Read. BASE+0x0e is always status + * reg. */ +#define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window + * reg. */ +/* + * Window 0 registers. Setup. + */ +/* Write */ +#define EP_W0_EEPROM_DATA 0x0c +#define EP_W0_EEPROM_COMMAND 0x0a +#define EP_W0_RESOURCE_CFG 0x08 +#define EP_W0_ADDRESS_CFG 0x06 +#define EP_W0_CONFIG_CTRL 0x04 +/* Read */ +#define EP_W0_PRODUCT_ID 0x02 +#define EP_W0_MFG_ID 0x00 + +/* + * Window 1 registers. Operating Set. + */ +/* Write */ +#define EP_W1_TX_PIO_WR_2 0x02 +#define EP_W1_TX_PIO_WR_1 0x00 +/* Read */ +#define EP_W1_FREE_TX 0x0c +#define EP_W1_TX_STATUS 0x0b /* byte */ +#define EP_W1_TIMER 0x0a /* byte */ +#define EP_W1_RX_STATUS 0x08 +#define EP_W1_RX_PIO_RD_2 0x02 +#define EP_W1_RX_PIO_RD_1 0x00 + +/* + * Window 2 registers. Station Address Setup/Read + */ +/* Read/Write */ +#define EP_W2_ADDR_5 0x05 +#define EP_W2_ADDR_4 0x04 +#define EP_W2_ADDR_3 0x03 +#define EP_W2_ADDR_2 0x02 +#define EP_W2_ADDR_1 0x01 +#define EP_W2_ADDR_0 0x00 + +/* + * Window 3 registers. FIFO Management. + */ +/* Read */ +#define EP_W3_FREE_TX 0x0c +#define EP_W3_FREE_RX 0x0a + +/* + * Window 4 registers. Diagnostics. + */ +/* Read/Write */ +#define EP_W4_MEDIA_TYPE 0x0a +#define EP_W4_CTRLR_STATUS 0x08 +#define EP_W4_NET_DIAG 0x06 +#define EP_W4_FIFO_DIAG 0x04 +#define EP_W4_HOST_DIAG 0x02 +#define EP_W4_TX_DIAG 0x00 + +/* + * Window 5 Registers. Results and Internal status. + */ +/* Read */ +#define EP_W5_READ_0_MASK 0x0c +#define EP_W5_INTR_MASK 0x0a +#define EP_W5_RX_FILTER 0x08 +#define EP_W5_RX_EARLY_THRESH 0x06 +#define EP_W5_TX_AVAIL_THRESH 0x02 +#define EP_W5_TX_START_THRESH 0x00 + +/* + * Window 6 registers. Statistics. + */ +/* Read/Write */ +#define TX_TOTAL_OK 0x0c +#define RX_TOTAL_OK 0x0a +#define TX_DEFERRALS 0x08 +#define RX_FRAMES_OK 0x07 +#define TX_FRAMES_OK 0x06 +#define RX_OVERRUNS 0x05 +#define TX_COLLISIONS 0x04 +#define TX_AFTER_1_COLLISION 0x03 +#define TX_AFTER_X_COLLISIONS 0x02 +#define TX_NO_SQE 0x01 +#define TX_CD_LOST 0x00 + +/**************************************** + * + * Register definitions. + * + ****************************************/ + +/* + * Command register. All windows. + * + * 16 bit register. + * 15-11: 5-bit code for command to be executed. + * 10-0: 11-bit arg if any. For commands with no args; + * this can be set to anything. + */ +#define GLOBAL_RESET (unsigned short) 0x0000 /* Wait at least 1ms + * after issuing */ +#define WINDOW_SELECT (unsigned short) (0x1<<11) +#define START_TRANSCEIVER (unsigned short) (0x2<<11) /* Read ADDR_CFG reg to + * determine whether + * this is needed. If + * so; wait 800 uSec + * before using trans- + * ceiver. */ +#define RX_DISABLE (unsigned short) (0x3<<11) /* state disabled on + * power-up */ +#define RX_ENABLE (unsigned short) (0x4<<11) +#define RX_RESET (unsigned short) (0x5<<11) +#define RX_DISCARD_TOP_PACK (unsigned short) (0x8<<11) +#define TX_ENABLE (unsigned short) (0x9<<11) +#define TX_DISABLE (unsigned short) (0xa<<11) +#define TX_RESET (unsigned short) (0xb<<11) +#define REQ_INTR (unsigned short) (0xc<<11) +#define SET_INTR_MASK (unsigned short) (0xe<<11) +#define SET_RD_0_MASK (unsigned short) (0xf<<11) +#define SET_RX_FILTER (unsigned short) (0x10<<11) +#define FIL_INDIVIDUAL (unsigned short) (0x1) +#define FIL_GROUP (unsigned short) (0x2) +#define FIL_BRDCST (unsigned short) (0x4) +#define FIL_ALL (unsigned short) (0x8) +#define SET_RX_EARLY_THRESH (unsigned short) (0x11<<11) +#define SET_TX_AVAIL_THRESH (unsigned short) (0x12<<11) +#define SET_TX_START_THRESH (unsigned short) (0x13<<11) +#define STATS_ENABLE (unsigned short) (0x15<<11) +#define STATS_DISABLE (unsigned short) (0x16<<11) +#define STOP_TRANSCEIVER (unsigned short) (0x17<<11) +/* + * The following C_* acknowledge the various interrupts. Some of them don't + * do anything. See the manual. + */ +#define ACK_INTR (unsigned short) (0x6800) +#define C_INTR_LATCH (unsigned short) (ACK_INTR|0x1) +#define C_CARD_FAILURE (unsigned short) (ACK_INTR|0x2) +#define C_TX_COMPLETE (unsigned short) (ACK_INTR|0x4) +#define C_TX_AVAIL (unsigned short) (ACK_INTR|0x8) +#define C_RX_COMPLETE (unsigned short) (ACK_INTR|0x10) +#define C_RX_EARLY (unsigned short) (ACK_INTR|0x20) +#define C_INT_RQD (unsigned short) (ACK_INTR|0x40) +#define C_UPD_STATS (unsigned short) (ACK_INTR|0x80) + +/* + * Status register. All windows. + * + * 15-13: Window number(0-7). + * 12: Command_in_progress. + * 11: reserved. + * 10: reserved. + * 9: reserved. + * 8: reserved. + * 7: Update Statistics. + * 6: Interrupt Requested. + * 5: RX Early. + * 4: RX Complete. + * 3: TX Available. + * 2: TX Complete. + * 1: Adapter Failure. + * 0: Interrupt Latch. + */ +#define S_INTR_LATCH (unsigned short) (0x1) +#define S_CARD_FAILURE (unsigned short) (0x2) +#define S_TX_COMPLETE (unsigned short) (0x4) +#define S_TX_AVAIL (unsigned short) (0x8) +#define S_RX_COMPLETE (unsigned short) (0x10) +#define S_RX_EARLY (unsigned short) (0x20) +#define S_INT_RQD (unsigned short) (0x40) +#define S_UPD_STATS (unsigned short) (0x80) +#define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\ + S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY) +#define S_COMMAND_IN_PROGRESS (unsigned short) (0x1000) + +/* + * FIFO Registers. + * RX Status. Window 1/Port 08 + * + * 15: Incomplete or FIFO empty. + * 14: 1: Error in RX Packet 0: Incomplete or no error. + * 13-11: Type of error. + * 1000 = Overrun. + * 1011 = Run Packet Error. + * 1100 = Alignment Error. + * 1101 = CRC Error. + * 1001 = Oversize Packet Error (>1514 bytes) + * 0010 = Dribble Bits. + * (all other error codes, no errors.) + * + * 10-0: RX Bytes (0-1514) + */ +#define ERR_RX_INCOMPLETE (unsigned short) (0x1<<15) +#define ERR_RX (unsigned short) (0x1<<14) +#define ERR_RX_OVERRUN (unsigned short) (0x8<<11) +#define ERR_RX_RUN_PKT (unsigned short) (0xb<<11) +#define ERR_RX_ALIGN (unsigned short) (0xc<<11) +#define ERR_RX_CRC (unsigned short) (0xd<<11) +#define ERR_RX_OVERSIZE (unsigned short) (0x9<<11) +#define ERR_RX_DRIBBLE (unsigned short) (0x2<<11) + +/* + * FIFO Registers. + * TX Status. Window 1/Port 0B + * + * Reports the transmit status of a completed transmission. Writing this + * register pops the transmit completion stack. + * + * Window 1/Port 0x0b. + * + * 7: Complete + * 6: Interrupt on successful transmission requested. + * 5: Jabber Error (TP Only, TX Reset required. ) + * 4: Underrun (TX Reset required. ) + * 3: Maximum Collisions. + * 2: TX Status Overflow. + * 1-0: Undefined. + * + */ +#define TXS_COMPLETE 0x80 +#define TXS_SUCCES_INTR_REQ 0x40 +#define TXS_JABBER 0x20 +#define TXS_UNDERRUN 0x10 +#define TXS_MAX_COLLISION 0x8 +#define TXS_STATUS_OVERFLOW 0x4 + +/* + * Configuration control register. + * Window 0/Port 04 + */ +/* Read */ +#define IS_AUI (1<<13) +#define IS_BNC (1<<12) +#define IS_UTP (1<<9) +/* Write */ +#define ENABLE_DRQ_IRQ 0x0001 +#define W0_P4_CMD_RESET_ADAPTER 0x4 +#define W0_P4_CMD_ENABLE_ADAPTER 0x1 +/* + * Media type and status. + * Window 4/Port 0A + */ +#define ENABLE_UTP 0xc0 +#define DISABLE_UTP 0x0 + +/* + * Resource control register + */ + +#define SET_IRQ(i) ( ((i)<<12) | 0xF00) /* set IRQ i */ + +/* + * Receive status register + */ + +#define RX_BYTES_MASK (unsigned short) (0x07ff) +#define RX_ERROR 0x4000 +#define RX_INCOMPLETE 0x8000 + +/* + * Misc defines for various things. + */ +#define MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */ +#define PROD_ID 0x9150 + +#define AUI 0x1 +#define BNC 0x2 +#define UTP 0x4 + +#define RX_BYTES_MASK (unsigned short) (0x07ff) + +/* + * Function shared between 3c509.c and 3c529.c + */ +extern int t5x9_probe ( struct nic *nic, + uint16_t prod_id_check, uint16_t prod_id_mask ); +extern void t5x9_disable ( struct nic *nic ); + +/* + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/3c515.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c515.c new file mode 100644 index 0000000..eb9569f --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c515.c @@ -0,0 +1,763 @@ +/* +* 3c515.c -- 3COM 3C515 Fast Etherlink ISA 10/100BASE-TX driver for etherboot +* Copyright (C) 2002 Timothy Legge <tlegge@rogers.com> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +* +* Portions of this code: +* Copyright (C) 1997-2002 Donald Becker 3c515.c: A 3Com ISA EtherLink XL "Corkscrew" ethernet driver for linux. +* Copyright (C) 2001 P.J.H.Fox (fox@roestock.demon.co.uk) ISAPNP Tools +* Copyright (c) 2002 Jaroslav Kysela <perex@suse.cz> ISA Plug & Play support Linux Kernel +* Copyright (C) 2000 Shusuke Nisiyama <shu@athena.qe.eng.hokudai.ac.jp> etherboot-5.0.5 3c595.c +* Coptright (C) 1995 Martin Renters etherboot-5.0.5 3c509.c +* Copyright (C) 1999 LightSys Technology Services, Inc. etherboot-5.0.5 3c90x.c +* Portions Copyright (C) 1999 Steve Smith etherboot-5.0.5 3c90x.c +* +* The probe and reset functions and defines are direct copies from the +* Becker code modified where necessary to make it work for etherboot +* +* The poll and transmit functions either contain code from or were written by referencing +* the above referenced etherboot drivers. This driver would not have been +* possible without this prior work +* +* REVISION HISTORY: +* ================ +* v0.10 4-17-2002 TJL Initial implementation. +* v0.11 4-17-2002 TJL Cleanup of the code +* v0.12 4-26-2002 TJL Added ISA Plug and Play for Non-PNP Bioses +* v0.13 6-10-2002 TJL Fixed ISA_PNP MAC Address problem +* v0.14 9-23-2003 TJL Replaced delay with currticks +* +* Indent Options: indent -kr -i8 +* *********************************************************/ + +FILE_LICENCE ( GPL2_OR_LATER ); + +/* to get some global routines like printf */ +#include "etherboot.h" +/* to get the interface to the body of the program */ +#include "nic.h" +#include <gpxe/isapnp.h> +#include <gpxe/isa.h> /* for ISA_ROM */ +#include <gpxe/ethernet.h> + +static void t3c515_wait(unsigned int nticks) +{ + unsigned int to = currticks() + nticks; + while (currticks() < to) + /* wait */ ; +} + +/* TJL definations */ +#define HZ 100 +static int if_port; +static struct corkscrew_private *vp; +/* Brought directly from 3c515.c by Becker */ +#define CORKSCREW 1 + +/* Maximum events (Rx packets, etc.) to handle at each interrupt. +static int max_interrupt_work = 20; +*/ + +/* Enable the automatic media selection code -- usually set. */ +#define AUTOMEDIA 1 + +/* Allow the use of fragment bus master transfers instead of only + programmed-I/O for Vortex cards. Full-bus-master transfers are always + enabled by default on Boomerang cards. If VORTEX_BUS_MASTER is defined, + the feature may be turned on using 'options'. */ +#define VORTEX_BUS_MASTER + +/* A few values that may be tweaked. */ +/* Keep the ring sizes a power of two for efficiency. */ +#define TX_RING_SIZE 16 +#define RX_RING_SIZE 16 +#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */ + +/* "Knobs" for adjusting internal parameters. */ +/* Put out somewhat more debugging messages. (0 - no msg, 1 minimal msgs). */ +#define DRIVER_DEBUG 1 +/* Some values here only for performance evaluation and path-coverage + debugging. +static int rx_nocopy, rx_copy, queued_packet; +*/ + +#define CORKSCREW_ID 10 + +#define EL3WINDOW(win_num) \ + outw(SelectWindow + (win_num), nic->ioaddr + EL3_CMD) +#define EL3_CMD 0x0e +#define EL3_STATUS 0x0e +#define RX_BYTES_MASK (unsigned short) (0x07ff) + +enum corkscrew_cmd { + TotalReset = 0 << 11, SelectWindow = 1 << 11, StartCoax = 2 << 11, + RxDisable = 3 << 11, RxEnable = 4 << 11, RxReset = 5 << 11, + UpStall = 6 << 11, UpUnstall = (6 << 11) + 1, + DownStall = (6 << 11) + 2, DownUnstall = (6 << 11) + 3, + RxDiscard = 8 << 11, TxEnable = 9 << 11, TxDisable = + 10 << 11, TxReset = 11 << 11, + FakeIntr = 12 << 11, AckIntr = 13 << 11, SetIntrEnb = 14 << 11, + SetStatusEnb = 15 << 11, SetRxFilter = 16 << 11, SetRxThreshold = + 17 << 11, + SetTxThreshold = 18 << 11, SetTxStart = 19 << 11, + StartDMAUp = 20 << 11, StartDMADown = (20 << 11) + 1, StatsEnable = + 21 << 11, + StatsDisable = 22 << 11, StopCoax = 23 << 11, +}; + +/* The SetRxFilter command accepts the following classes: */ +enum RxFilter { + RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 +}; + +/* Bits in the general status register. */ +enum corkscrew_status { + IntLatch = 0x0001, AdapterFailure = 0x0002, TxComplete = 0x0004, + TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020, + IntReq = 0x0040, StatsFull = 0x0080, + DMADone = 1 << 8, DownComplete = 1 << 9, UpComplete = 1 << 10, + DMAInProgress = 1 << 11, /* DMA controller is still busy. */ + CmdInProgress = 1 << 12, /* EL3_CMD is still busy. */ +}; + +/* Register window 1 offsets, the window used in normal operation. + On the Corkscrew this window is always mapped at offsets 0x10-0x1f. */ +enum Window1 { + TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14, + RxStatus = 0x18, Timer = 0x1A, TxStatus = 0x1B, + TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */ +}; +enum Window0 { + Wn0IRQ = 0x08, +#if defined(CORKSCREW) + Wn0EepromCmd = 0x200A, /* Corkscrew EEPROM command register. */ + Wn0EepromData = 0x200C, /* Corkscrew EEPROM results register. */ +#else + Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */ + Wn0EepromData = 12, /* Window 0: EEPROM results register. */ +#endif +}; +enum Win0_EEPROM_bits { + EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0, + EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */ + EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */ +}; + +enum Window3 { /* Window 3: MAC/config bits. */ + Wn3_Config = 0, Wn3_MAC_Ctrl = 6, Wn3_Options = 8, +}; +union wn3_config { + int i; + struct w3_config_fields { + unsigned int ram_size:3, ram_width:1, ram_speed:2, + rom_size:2; + int pad8:8; + unsigned int ram_split:2, pad18:2, xcvr:3, pad21:1, + autoselect:1; + int pad24:7; + } u; +}; + +enum Window4 { + Wn4_NetDiag = 6, Wn4_Media = 10, /* Window 4: Xcvr/media bits. */ +}; +enum Win4_Media_bits { + Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */ + Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */ + Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */ + Media_LnkBeat = 0x0800, +}; +enum Window7 { /* Window 7: Bus Master control. */ + Wn7_MasterAddr = 0, Wn7_MasterLen = 6, Wn7_MasterStatus = 12, +}; + +/* Boomerang-style bus master control registers. Note ISA aliases! */ +enum MasterCtrl { + PktStatus = 0x400, DownListPtr = 0x404, FragAddr = 0x408, FragLen = + 0x40c, + TxFreeThreshold = 0x40f, UpPktStatus = 0x410, UpListPtr = 0x418, +}; + +/* The Rx and Tx descriptor lists. + Caution Alpha hackers: these types are 32 bits! Note also the 8 byte + alignment contraint on tx_ring[] and rx_ring[]. */ +struct boom_rx_desc { + u32 next; + s32 status; + u32 addr; + s32 length; +}; + +/* Values for the Rx status entry. */ +enum rx_desc_status { + RxDComplete = 0x00008000, RxDError = 0x4000, + /* See boomerang_rx() for actual error bits */ +}; + +struct boom_tx_desc { + u32 next; + s32 status; + u32 addr; + s32 length; +}; + +struct corkscrew_private { + const char *product_name; + struct net_device *next_module; + /* The Rx and Tx rings are here to keep them quad-word-aligned. */ + struct boom_rx_desc rx_ring[RX_RING_SIZE]; + struct boom_tx_desc tx_ring[TX_RING_SIZE]; + /* The addresses of transmit- and receive-in-place skbuffs. */ + struct sk_buff *rx_skbuff[RX_RING_SIZE]; + struct sk_buff *tx_skbuff[TX_RING_SIZE]; + unsigned int cur_rx, cur_tx; /* The next free ring entry */ + unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */ + struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */ + int capabilities; /* Adapter capabilities word. */ + int options; /* User-settable misc. driver options. */ + int last_rx_packets; /* For media autoselection. */ + unsigned int available_media:8, /* From Wn3_Options */ + media_override:3, /* Passed-in media type. */ + default_media:3, /* Read from the EEPROM. */ + full_duplex:1, autoselect:1, bus_master:1, /* Vortex can only do a fragment bus-m. */ + full_bus_master_tx:1, full_bus_master_rx:1, /* Boomerang */ + tx_full:1; +}; + +/* The action to take with a media selection timer tick. + Note that we deviate from the 3Com order by checking 10base2 before AUI. + */ +enum xcvr_types { + XCVR_10baseT = + 0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx, + XCVR_100baseFx, XCVR_MII = 6, XCVR_Default = 8, +}; + +static struct media_table { + char *name; + unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */ + mask:8, /* The transceiver-present bit in Wn3_Config. */ + next:8; /* The media type to try next. */ + short wait; /* Time before we check media status. */ +} media_tbl[] = { + { + "10baseT", Media_10TP, 0x08, XCVR_10base2, (14 * HZ) / 10} + , { + "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1 * HZ) / 10} + , { + "undefined", 0, 0x80, XCVR_10baseT, 10000} + , { + "10base2", 0, 0x10, XCVR_AUI, (1 * HZ) / 10} + , { + "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, + (14 * HZ) / 10} + , { + "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14 * HZ) / 10} + , { + "MII", 0, 0x40, XCVR_10baseT, 3 * HZ} + , { + "undefined", 0, 0x01, XCVR_10baseT, 10000} + , { + "Default", 0, 0xFF, XCVR_10baseT, 10000} +,}; + +/* TILEG Modified to remove reference to dev */ +static int corkscrew_found_device(int ioaddr, int irq, int product_index, + int options, struct nic *nic); +static int corkscrew_probe1(int ioaddr, int irq, int product_index, + struct nic *nic); + +/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */ +/* Note: this is the only limit on the number of cards supported!! */ +static int options = -1; + +/* End Brought directly from 3c515.c by Becker */ + +/************************************************************************** +RESET - Reset adapter +***************************************************************************/ +static void t515_reset(struct nic *nic) +{ + union wn3_config config; + int i; + + /* Before initializing select the active media port. */ + EL3WINDOW(3); + if (vp->full_duplex) + outb(0x20, nic->ioaddr + Wn3_MAC_Ctrl); /* Set the full-duplex bit. */ + config.i = inl(nic->ioaddr + Wn3_Config); + + if (vp->media_override != 7) { + DBG ( "Media override to transceiver %d (%s).\n", + vp->media_override, + media_tbl[vp->media_override].name); + if_port = vp->media_override; + } else if (vp->autoselect) { + /* Find first available media type, starting with 100baseTx. */ + if_port = 4; + while (!(vp->available_media & media_tbl[if_port].mask)) + if_port = media_tbl[if_port].next; + + DBG ( "Initial media type %s.\n", + media_tbl[if_port].name); + } else + if_port = vp->default_media; + + config.u.xcvr = if_port; + outl(config.i, nic->ioaddr + Wn3_Config); + + DBG ( "corkscrew_open() InternalConfig 0x%hX.\n", + config.i); + + outw(TxReset, nic->ioaddr + EL3_CMD); + for (i = 20; i >= 0; i--) + if (!(inw(nic->ioaddr + EL3_STATUS) & CmdInProgress)) + break; + + outw(RxReset, nic->ioaddr + EL3_CMD); + /* Wait a few ticks for the RxReset command to complete. */ + for (i = 20; i >= 0; i--) + if (!(inw(nic->ioaddr + EL3_STATUS) & CmdInProgress)) + break; + + outw(SetStatusEnb | 0x00, nic->ioaddr + EL3_CMD); + +#ifdef debug_3c515 + EL3WINDOW(4); + DBG ( "FIXME: fix print for irq, not 9" ); + DBG ( "corkscrew_open() irq %d media status 0x%hX.\n", + 9, inw(nic->ioaddr + Wn4_Media) ); +#endif + + /* Set the station address and mask in window 2 each time opened. */ + EL3WINDOW(2); + for (i = 0; i < 6; i++) + outb(nic->node_addr[i], nic->ioaddr + i); + for (; i < 12; i += 2) + outw(0, nic->ioaddr + i); + + if (if_port == 3) + /* Start the thinnet transceiver. We should really wait 50ms... */ + outw(StartCoax, nic->ioaddr + EL3_CMD); + EL3WINDOW(4); + outw((inw(nic->ioaddr + Wn4_Media) & ~(Media_10TP | Media_SQE)) | + media_tbl[if_port].media_bits, nic->ioaddr + Wn4_Media); + + /* Switch to the stats window, and clear all stats by reading. */ +/* outw(StatsDisable, nic->ioaddr + EL3_CMD);*/ + EL3WINDOW(6); + for (i = 0; i < 10; i++) + inb(nic->ioaddr + i); + inw(nic->ioaddr + 10); + inw(nic->ioaddr + 12); + /* New: On the Vortex we must also clear the BadSSD counter. */ + EL3WINDOW(4); + inb(nic->ioaddr + 12); + /* ..and on the Boomerang we enable the extra statistics bits. */ + outw(0x0040, nic->ioaddr + Wn4_NetDiag); + + /* Switch to register set 7 for normal use. */ + EL3WINDOW(7); + + /* Temporarily left in place. If these FIXMEs are printed + it meand that special logic for that card may need to be added + see Becker's 3c515.c driver */ + if (vp->full_bus_master_rx) { /* Boomerang bus master. */ + printf("FIXME: Is this if necessary"); + vp->cur_rx = vp->dirty_rx = 0; + DBG ( " Filling in the Rx ring.\n" ); + for (i = 0; i < RX_RING_SIZE; i++) { + printf("FIXME: Is this if necessary"); + } + } + if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */ + vp->cur_tx = vp->dirty_tx = 0; + outb(PKT_BUF_SZ >> 8, nic->ioaddr + TxFreeThreshold); /* Room for a packet. */ + /* Clear the Tx ring. */ + for (i = 0; i < TX_RING_SIZE; i++) + vp->tx_skbuff[i] = 0; + outl(0, nic->ioaddr + DownListPtr); + } + /* Set receiver mode: presumably accept b-case and phys addr only. */ + outw(SetRxFilter | RxStation | RxMulticast | RxBroadcast | RxProm, + nic->ioaddr + EL3_CMD); + + outw(RxEnable, nic->ioaddr + EL3_CMD); /* Enable the receiver. */ + outw(TxEnable, nic->ioaddr + EL3_CMD); /* Enable transmitter. */ + /* Allow status bits to be seen. */ + outw(SetStatusEnb | AdapterFailure | IntReq | StatsFull | + (vp->full_bus_master_tx ? DownComplete : TxAvailable) | + (vp->full_bus_master_rx ? UpComplete : RxComplete) | + (vp->bus_master ? DMADone : 0), nic->ioaddr + EL3_CMD); + /* Ack all pending events, and set active indicator mask. */ + outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq, + nic->ioaddr + EL3_CMD); + outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | StatsFull + | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete, + nic->ioaddr + EL3_CMD); + +} + +/************************************************************************** +POLL - Wait for a frame +***************************************************************************/ +static int t515_poll(struct nic *nic, int retrieve) +{ + short status, cst; + register short rx_fifo; + + cst = inw(nic->ioaddr + EL3_STATUS); + + if ((cst & RxComplete) == 0) { + /* Ack all pending events, and set active indicator mask. */ + outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq, + nic->ioaddr + EL3_CMD); + outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | + StatsFull | (vp-> + bus_master ? DMADone : 0) | UpComplete | + DownComplete, nic->ioaddr + EL3_CMD); + return 0; + } + status = inw(nic->ioaddr + RxStatus); + + if (status & RxDError) { + printf("RxDError\n"); + outw(RxDiscard, nic->ioaddr + EL3_CMD); + return 0; + } + + rx_fifo = status & RX_BYTES_MASK; + if (rx_fifo == 0) + return 0; + + if ( ! retrieve ) return 1; + + DBG ( "[l=%d", rx_fifo ); + insw(nic->ioaddr + RX_FIFO, nic->packet, rx_fifo / 2); + if (rx_fifo & 1) + nic->packet[rx_fifo - 1] = inb(nic->ioaddr + RX_FIFO); + nic->packetlen = rx_fifo; + + while (1) { + status = inw(nic->ioaddr + RxStatus); + DBG ( "0x%hX*", status ); + rx_fifo = status & RX_BYTES_MASK; + + if (rx_fifo > 0) { + insw(nic->ioaddr + RX_FIFO, nic->packet + nic->packetlen, + rx_fifo / 2); + if (rx_fifo & 1) + nic->packet[nic->packetlen + rx_fifo - 1] = + inb(nic->ioaddr + RX_FIFO); + nic->packetlen += rx_fifo; + DBG ( "+%d", rx_fifo ); + } + if ((status & RxComplete) == 0) { + DBG ( "=%d", nic->packetlen ); + break; + } + udelay(1000); + } + + /* acknowledge reception of packet */ + outw(RxDiscard, nic->ioaddr + EL3_CMD); + while (inw(nic->ioaddr + EL3_STATUS) & CmdInProgress); +#ifdef debug_3c515 + { + unsigned short type = 0; + type = (nic->packet[12] << 8) | nic->packet[13]; + if (nic->packet[0] + nic->packet[1] + nic->packet[2] + + nic->packet[3] + nic->packet[4] + nic->packet[5] == + 0xFF * ETH_ALEN) + DBG ( ",t=0x%hX,b]", type ); + else + DBG ( ",t=0x%hX]", type ); + } +#endif + + return 1; +} + +/************************************************************************* + 3Com 515 - specific routines +**************************************************************************/ +static char padmap[] = { + 0, 3, 2, 1 +}; +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static void t515_transmit(struct nic *nic, const char *d, /* Destination */ + unsigned int t, /* Type */ + unsigned int s, /* size */ + const char *p) +{ /* Packet */ + register int len; + int pad; + int status; + + DBG ( "{l=%d,t=0x%hX}", s + ETH_HLEN, t ); + + /* swap bytes of type */ + t = htons(t); + + len = s + ETH_HLEN; /* actual length of packet */ + pad = padmap[len & 3]; + + /* + * The 3c515 automatically pads short packets to minimum ethernet length, + * but we drop packets that are too large. Perhaps we should truncate + * them instead? + Copied from 3c595. Is this true for the 3c515? + */ + if (len + pad > ETH_FRAME_LEN) { + return; + } + /* drop acknowledgements */ + while ((status = inb(nic->ioaddr + TxStatus)) & TxComplete) { + /*if(status & (TXS_UNDERRUN|0x88|TXS_STATUS_OVERFLOW)) { */ + outw(TxReset, nic->ioaddr + EL3_CMD); + outw(TxEnable, nic->ioaddr + EL3_CMD); +/* } */ + + outb(0x0, nic->ioaddr + TxStatus); + } + + while (inw(nic->ioaddr + TxFree) < len + pad + 4) { + /* no room in FIFO */ + } + + outw(len, nic->ioaddr + TX_FIFO); + outw(0x0, nic->ioaddr + TX_FIFO); /* Second dword meaningless */ + + /* write packet */ + outsw(nic->ioaddr + TX_FIFO, d, ETH_ALEN / 2); + outsw(nic->ioaddr + TX_FIFO, nic->node_addr, ETH_ALEN / 2); + outw(t, nic->ioaddr + TX_FIFO); + outsw(nic->ioaddr + TX_FIFO, p, s / 2); + + if (s & 1) + outb(*(p + s - 1), nic->ioaddr + TX_FIFO); + + while (pad--) + outb(0, nic->ioaddr + TX_FIFO); /* Padding */ + + /* wait for Tx complete */ + while ((inw(nic->ioaddr + EL3_STATUS) & CmdInProgress) != 0); +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void t515_disable ( struct nic *nic, + struct isapnp_device *isapnp ) { + + t515_reset(nic); + + /* This is a hack. Since ltsp worked on my + system without any disable functionality I + have no way to determine if this works */ + + /* Disable the receiver and transmitter. */ + outw(RxDisable, nic->ioaddr + EL3_CMD); + outw(TxDisable, nic->ioaddr + EL3_CMD); + + if (if_port == XCVR_10base2) + /* Turn off thinnet power. Green! */ + outw(StopCoax, nic->ioaddr + EL3_CMD); + + + outw(SetIntrEnb | 0x0000, nic->ioaddr + EL3_CMD); + + deactivate_isapnp_device ( isapnp ); + return; +} + +static void t515_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + +static struct nic_operations t515_operations = { + .connect = dummy_connect, + .poll = t515_poll, + .transmit = t515_transmit, + .irq = t515_irq, + +}; + +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +You should omit the last argument struct pci_device * for a non-PCI NIC +***************************************************************************/ +static int t515_probe ( struct nic *nic, struct isapnp_device *isapnp ) { + + /* Direct copy from Beckers 3c515.c removing any ISAPNP sections */ + + nic->ioaddr = isapnp->ioaddr; + nic->irqno = isapnp->irqno; + activate_isapnp_device ( isapnp ); + + /* Check the resource configuration for a matching ioaddr. */ + if ((unsigned)(inw(nic->ioaddr + 0x2002) & 0x1f0) + != (nic->ioaddr & 0x1f0)) { + DBG ( "3c515 ioaddr mismatch\n" ); + return 0; + } + + /* Verify by reading the device ID from the EEPROM. */ + { + int timer; + outw(EEPROM_Read + 7, nic->ioaddr + Wn0EepromCmd); + /* Pause for at least 162 us. for the read to take place. */ + for (timer = 4; timer >= 0; timer--) { + t3c515_wait(1); + if ((inw(nic->ioaddr + Wn0EepromCmd) & 0x0200) == 0) + break; + } + if (inw(nic->ioaddr + Wn0EepromData) != 0x6d50) { + DBG ( "3c515 read incorrect vendor ID from EEPROM" ); + return 0; + } + + } + DBG ( "3c515 Resource configuration register 0x%X, DCR 0x%hX.\n", + inl(nic->ioaddr + 0x2002), inw(nic->ioaddr + 0x2000) ); + corkscrew_found_device(nic->ioaddr, nic->irqno, CORKSCREW_ID, + options, nic); + + t515_reset(nic); + nic->nic_op = &t515_operations; + return 1; +} + +static int +corkscrew_found_device(int ioaddr, int irq, + int product_index, int options, struct nic *nic) +{ + /* Direct copy from Becker 3c515.c with unecessary parts removed */ + vp->product_name = "3c515"; + vp->options = options; + if (options >= 0) { + vp->media_override = + ((options & 7) == 2) ? 0 : options & 7; + vp->full_duplex = (options & 8) ? 1 : 0; + vp->bus_master = (options & 16) ? 1 : 0; + } else { + vp->media_override = 7; + vp->full_duplex = 0; + vp->bus_master = 0; + } + + corkscrew_probe1(ioaddr, irq, product_index, nic); + return 0; +} + +static int +corkscrew_probe1(int ioaddr, int irq, int product_index __unused, + struct nic *nic) +{ + unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */ + int i; + + printf("3Com %s at 0x%hX, ", vp->product_name, ioaddr); + + /* Read the station address from the EEPROM. */ + EL3WINDOW(0); + for (i = 0; i < 0x18; i++) { + short *phys_addr = (short *) nic->node_addr; + int timer; + outw(EEPROM_Read + i, ioaddr + Wn0EepromCmd); + /* Pause for at least 162 us. for the read to take place. */ + for (timer = 4; timer >= 0; timer--) { + t3c515_wait(1); + if ((inw(ioaddr + Wn0EepromCmd) & 0x0200) == 0) + break; + } + eeprom[i] = inw(ioaddr + Wn0EepromData); + DBG ( "Value %d: %hX ", i, eeprom[i] ); + checksum ^= eeprom[i]; + if (i < 3) + phys_addr[i] = htons(eeprom[i]); + } + checksum = (checksum ^ (checksum >> 8)) & 0xff; + if (checksum != 0x00) + printf(" ***INVALID CHECKSUM 0x%hX*** ", checksum); + + DBG ( "%s", eth_ntoa ( nic->node_addr ) ); + + if (eeprom[16] == 0x11c7) { /* Corkscrew */ + + } + printf(", IRQ %d\n", irq); + /* Tell them about an invalid IRQ. */ + if ( (irq <= 0 || irq > 15) ) { + DBG (" *** Warning: this IRQ is unlikely to work! ***\n" ); + } + + { + char *ram_split[] = { "5:3", "3:1", "1:1", "3:5" }; + union wn3_config config; + EL3WINDOW(3); + vp->available_media = inw(ioaddr + Wn3_Options); + config.i = inl(ioaddr + Wn3_Config); + DBG ( " Internal config register is %4.4x, " + "transceivers 0x%hX.\n", + config.i, inw(ioaddr + Wn3_Options) ); + printf + (" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n", + 8 << config.u.ram_size, + config.u.ram_width ? "word" : "byte", + ram_split[config.u.ram_split], + config.u.autoselect ? "autoselect/" : "", + media_tbl[config.u.xcvr].name); + if_port = config.u.xcvr; + vp->default_media = config.u.xcvr; + vp->autoselect = config.u.autoselect; + } + if (vp->media_override != 7) { + printf(" Media override to transceiver type %d (%s).\n", + vp->media_override, + media_tbl[vp->media_override].name); + if_port = vp->media_override; + } + + vp->capabilities = eeprom[16]; + vp->full_bus_master_tx = (vp->capabilities & 0x20) ? 1 : 0; + /* Rx is broken at 10mbps, so we always disable it. */ + /* vp->full_bus_master_rx = 0; */ + vp->full_bus_master_rx = (vp->capabilities & 0x20) ? 1 : 0; + + return 0; +} + +static struct isapnp_device_id t515_adapters[] = { + { "3c515 (ISAPnP)", ISAPNP_VENDOR('T','C','M'), 0x5051 }, +}; + +ISAPNP_DRIVER ( t515_driver, t515_adapters ); + +DRIVER ( "3c515", nic_driver, isapnp_driver, t515_driver, + t515_probe, t515_disable ); + +ISA_ROM ( "3c515", "3c515 Fast EtherLink ISAPnP" ); diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/3c529.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c529.c new file mode 100644 index 0000000..4282464 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c529.c @@ -0,0 +1,62 @@ +/* + * Split out from 3c509.c to make build process more sane + * + */ + +FILE_LICENCE ( BSD2 ); + +#include "etherboot.h" +#include <gpxe/mca.h> +#include <gpxe/isa.h> /* for ISA_ROM */ +#include "nic.h" +#include "3c509.h" + +/* + * Several other pieces of the MCA support code were shamelessly + * borrowed from the Linux kernel source. + * + * MCA support added by Adam Fritzler (mid@auk.cx) + * + * Generalised out of the 3c529 driver and into a bus type by Michael + * Brown <mbrown@fensystems.co.uk> + * + */ + +static int t529_probe ( struct nic *nic, struct mca_device *mca ) { + + /* Retrieve NIC parameters from MCA device parameters */ + nic->ioaddr = ( ( mca->pos[4] & 0xfc ) | 0x02 ) << 8; + nic->irqno = mca->pos[5] & 0x0f; + printf ( "3c529 board found on MCA at %#hx IRQ %d -", + nic->ioaddr, nic->irqno ); + + /* Hand off to generic t5x9 probe routine */ + return t5x9_probe ( nic, MCA_ID ( mca ), 0xffff ); +} + +static void t529_disable ( struct nic *nic, struct mca_device *mca __unused ) { + t5x9_disable ( nic ); +} + +static struct mca_device_id el3_mca_adapters[] = { + { "3Com 3c529 EtherLink III (10base2)", 0x627c }, + { "3Com 3c529 EtherLink III (10baseT)", 0x627d }, + { "3Com 3c529 EtherLink III (test mode)", 0x62db }, + { "3Com 3c529 EtherLink III (TP or coax)", 0x62f6 }, + { "3Com 3c529 EtherLink III (TP)", 0x62f7 }, +}; + +MCA_DRIVER ( t529_driver, el3_mca_adapters ); + +DRIVER ( "3c529", nic_driver, mca_driver, t529_driver, + t529_probe, t529_disable ); + +ISA_ROM( "3c529", "3c529 == MCA 3c509" ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/3c595.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c595.c new file mode 100644 index 0000000..07c85d0 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c595.c @@ -0,0 +1,553 @@ +/* +* 3c595.c -- 3COM 3C595 Fast Etherlink III PCI driver for etherboot +* +* Copyright (C) 2000 Shusuke Nisiyama <shu@athena.qe.eng.hokudai.ac.jp> +* All rights reserved. +* Mar. 14, 2000 +* +* This software may be used, modified, copied, distributed, and sold, in +* both source and binary form provided that the above copyright and these +* terms are retained. Under no circumstances are the authors responsible for +* the proper functioning of this software, nor do the authors assume any +* responsibility for damages incurred with its use. +* +* This code is based on Martin Renters' etherboot-4.4.3 3c509.c and +* Herb Peyerl's FreeBSD 3.4-RELEASE if_vx.c driver. +* +* Copyright (C) 1993-1994, David Greenman, Martin Renters. +* Copyright (C) 1993-1995, Andres Vega Garcia. +* Copyright (C) 1995, Serge Babkin. +* +* Copyright (c) 1994 Herb Peyerl <hpeyerl@novatel.ca> +* +* timlegge 08-24-2003 Add Multicast Support +*/ + +FILE_LICENCE ( BSD2 ); + +/* #define EDEBUG */ + +#include "etherboot.h" +#include "nic.h" +#include <gpxe/pci.h> +#include <gpxe/ethernet.h> +#include "3c595.h" + +static struct nic_operations t595_operations; + +static unsigned short eth_nic_base; +static unsigned short vx_connector, vx_connectors; + +static struct connector_entry { + int bit; + char *name; +} conn_tab[VX_CONNECTORS] = { +#define CONNECTOR_UTP 0 + { 0x08, "utp"}, +#define CONNECTOR_AUI 1 + { 0x20, "aui"}, +/* dummy */ + { 0, "???"}, +#define CONNECTOR_BNC 3 + { 0x10, "bnc"}, +#define CONNECTOR_TX 4 + { 0x02, "tx"}, +#define CONNECTOR_FX 5 + { 0x04, "fx"}, +#define CONNECTOR_MII 6 + { 0x40, "mii"}, + { 0, "???"} +}; + +static void vxgetlink(void); +static void vxsetlink(void); + +/************************************************************************** +ETH_RESET - Reset adapter +***************************************************************************/ +static void t595_reset(struct nic *nic) +{ + int i; + + /*********************************************************** + Reset 3Com 595 card + *************************************************************/ + + /* stop card */ + outw(RX_DISABLE, BASE + VX_COMMAND); + outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND); + VX_BUSY_WAIT; + outw(TX_DISABLE, BASE + VX_COMMAND); + outw(STOP_TRANSCEIVER, BASE + VX_COMMAND); + udelay(8000); + outw(RX_RESET, BASE + VX_COMMAND); + VX_BUSY_WAIT; + outw(TX_RESET, BASE + VX_COMMAND); + VX_BUSY_WAIT; + outw(C_INTR_LATCH, BASE + VX_COMMAND); + outw(SET_RD_0_MASK, BASE + VX_COMMAND); + outw(SET_INTR_MASK, BASE + VX_COMMAND); + outw(SET_RX_FILTER, BASE + VX_COMMAND); + + /* + * initialize card + */ + VX_BUSY_WAIT; + + GO_WINDOW(0); + + /* Disable the card */ +/* outw(0, BASE + VX_W0_CONFIG_CTRL); */ + + /* Configure IRQ to none */ +/* outw(SET_IRQ(0), BASE + VX_W0_RESOURCE_CFG); */ + + /* Enable the card */ +/* outw(ENABLE_DRQ_IRQ, BASE + VX_W0_CONFIG_CTRL); */ + + GO_WINDOW(2); + + /* Reload the ether_addr. */ + for (i = 0; i < ETH_ALEN; i++) + outb(nic->node_addr[i], BASE + VX_W2_ADDR_0 + i); + + outw(RX_RESET, BASE + VX_COMMAND); + VX_BUSY_WAIT; + outw(TX_RESET, BASE + VX_COMMAND); + VX_BUSY_WAIT; + + /* Window 1 is operating window */ + GO_WINDOW(1); + for (i = 0; i < 31; i++) + inb(BASE + VX_W1_TX_STATUS); + + outw(SET_RD_0_MASK | S_CARD_FAILURE | S_RX_COMPLETE | + S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND); + outw(SET_INTR_MASK | S_CARD_FAILURE | S_RX_COMPLETE | + S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND); + +/* + * Attempt to get rid of any stray interrupts that occured during + * configuration. On the i386 this isn't possible because one may + * already be queued. However, a single stray interrupt is + * unimportant. + */ + + outw(ACK_INTR | 0xff, BASE + VX_COMMAND); + + outw(SET_RX_FILTER | FIL_INDIVIDUAL | + FIL_BRDCST|FIL_MULTICAST, BASE + VX_COMMAND); + + vxsetlink(); +/*{ + int i,j; + i = CONNECTOR_TX; + GO_WINDOW(3); + j = inl(BASE + VX_W3_INTERNAL_CFG) & ~INTERNAL_CONNECTOR_MASK; + outl(BASE + VX_W3_INTERNAL_CFG, j | (i <<INTERNAL_CONNECTOR_BITS)); + GO_WINDOW(4); + outw(LINKBEAT_ENABLE, BASE + VX_W4_MEDIA_TYPE); + GO_WINDOW(1); +}*/ + + /* start tranciever and receiver */ + outw(RX_ENABLE, BASE + VX_COMMAND); + outw(TX_ENABLE, BASE + VX_COMMAND); + +} + +/************************************************************************** +ETH_TRANSMIT - Transmit a frame +***************************************************************************/ +static char padmap[] = { + 0, 3, 2, 1}; + +static void t595_transmit( +struct nic *nic, +const char *d, /* Destination */ +unsigned int t, /* Type */ +unsigned int s, /* size */ +const char *p) /* Packet */ +{ + register int len; + int pad; + int status; + +#ifdef EDEBUG + printf("{l=%d,t=%hX}",s+ETH_HLEN,t); +#endif + + /* swap bytes of type */ + t= htons(t); + + len=s+ETH_HLEN; /* actual length of packet */ + pad = padmap[len & 3]; + + /* + * The 3c595 automatically pads short packets to minimum ethernet length, + * but we drop packets that are too large. Perhaps we should truncate + * them instead? + */ + if (len + pad > ETH_FRAME_LEN) { + return; + } + + /* drop acknowledgements */ + while(( status=inb(BASE + VX_W1_TX_STATUS) )& TXS_COMPLETE ) { + if(status & (TXS_UNDERRUN|TXS_MAX_COLLISION|TXS_STATUS_OVERFLOW)) { + outw(TX_RESET, BASE + VX_COMMAND); + outw(TX_ENABLE, BASE + VX_COMMAND); + } + + outb(0x0, BASE + VX_W1_TX_STATUS); + } + + while (inw(BASE + VX_W1_FREE_TX) < len + pad + 4) { + /* no room in FIFO */ + } + + outw(len, BASE + VX_W1_TX_PIO_WR_1); + outw(0x0, BASE + VX_W1_TX_PIO_WR_1); /* Second dword meaningless */ + + /* write packet */ + outsw(BASE + VX_W1_TX_PIO_WR_1, d, ETH_ALEN/2); + outsw(BASE + VX_W1_TX_PIO_WR_1, nic->node_addr, ETH_ALEN/2); + outw(t, BASE + VX_W1_TX_PIO_WR_1); + outsw(BASE + VX_W1_TX_PIO_WR_1, p, s / 2); + if (s & 1) + outb(*(p+s - 1), BASE + VX_W1_TX_PIO_WR_1); + + while (pad--) + outb(0, BASE + VX_W1_TX_PIO_WR_1); /* Padding */ + + /* wait for Tx complete */ + while((inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS) != 0) + ; +} + +/************************************************************************** +ETH_POLL - Wait for a frame +***************************************************************************/ +static int t595_poll(struct nic *nic, int retrieve) +{ + /* common variables */ + /* variables for 3C595 */ + short status, cst; + register short rx_fifo; + + cst=inw(BASE + VX_STATUS); + +#ifdef EDEBUG + if(cst & 0x1FFF) + printf("-%hX-",cst); +#endif + + if( (cst & S_RX_COMPLETE)==0 ) { + /* acknowledge everything */ + outw(ACK_INTR | cst, BASE + VX_COMMAND); + outw(C_INTR_LATCH, BASE + VX_COMMAND); + + return 0; + } + + status = inw(BASE + VX_W1_RX_STATUS); +#ifdef EDEBUG + printf("*%hX*",status); +#endif + + if (status & ERR_RX) { + outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND); + return 0; + } + + rx_fifo = status & RX_BYTES_MASK; + if (rx_fifo==0) + return 0; + + if ( ! retrieve ) return 1; + + /* read packet */ +#ifdef EDEBUG + printf("[l=%d",rx_fifo); +#endif + insw(BASE + VX_W1_RX_PIO_RD_1, nic->packet, rx_fifo / 2); + if(rx_fifo & 1) + nic->packet[rx_fifo-1]=inb(BASE + VX_W1_RX_PIO_RD_1); + nic->packetlen=rx_fifo; + + while(1) { + status = inw(BASE + VX_W1_RX_STATUS); +#ifdef EDEBUG + printf("*%hX*",status); +#endif + rx_fifo = status & RX_BYTES_MASK; + + if(rx_fifo>0) { + insw(BASE + VX_W1_RX_PIO_RD_1, nic->packet+nic->packetlen, rx_fifo / 2); + if(rx_fifo & 1) + nic->packet[nic->packetlen+rx_fifo-1]=inb(BASE + VX_W1_RX_PIO_RD_1); + nic->packetlen+=rx_fifo; +#ifdef EDEBUG + printf("+%d",rx_fifo); +#endif + } + if(( status & RX_INCOMPLETE )==0) { +#ifdef EDEBUG + printf("=%d",nic->packetlen); +#endif + break; + } + udelay(1000); + } + + /* acknowledge reception of packet */ + outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND); + while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS); +#ifdef EDEBUG +{ + unsigned short type = 0; /* used by EDEBUG */ + type = (nic->packet[12]<<8) | nic->packet[13]; + if(nic->packet[0]+nic->packet[1]+nic->packet[2]+nic->packet[3]+nic->packet[4]+ + nic->packet[5] == 0xFF*ETH_ALEN) + printf(",t=%hX,b]",type); + else + printf(",t=%hX]",type); +} +#endif + return 1; +} + + +/************************************************************************* + 3Com 595 - specific routines +**************************************************************************/ + +static int +eeprom_rdy() +{ + int i; + + for (i = 0; is_eeprom_busy(BASE) && i < MAX_EEPROMBUSY; i++) + udelay(1000); + if (i >= MAX_EEPROMBUSY) { + /* printf("3c595: eeprom failed to come ready.\n"); */ + printf("3c595: eeprom is busy.\n"); /* memory in EPROM is tight */ + return (0); + } + return (1); +} + +/* + * get_e: gets a 16 bits word from the EEPROM. we must have set the window + * before + */ +static int +get_e(offset) +int offset; +{ + if (!eeprom_rdy()) + return (0xffff); + outw(EEPROM_CMD_RD | offset, BASE + VX_W0_EEPROM_COMMAND); + if (!eeprom_rdy()) + return (0xffff); + return (inw(BASE + VX_W0_EEPROM_DATA)); +} + +static void +vxgetlink(void) +{ + int n, k; + + GO_WINDOW(3); + vx_connectors = inw(BASE + VX_W3_RESET_OPT) & 0x7f; + for (n = 0, k = 0; k < VX_CONNECTORS; k++) { + if (vx_connectors & conn_tab[k].bit) { + if (n > 0) { + printf("/"); + } + printf("%s", conn_tab[k].name ); + n++; + } + } + if (vx_connectors == 0) { + printf("no connectors!"); + return; + } + GO_WINDOW(3); + vx_connector = (inl(BASE + VX_W3_INTERNAL_CFG) + & INTERNAL_CONNECTOR_MASK) + >> INTERNAL_CONNECTOR_BITS; + if (vx_connector & 0x10) { + vx_connector &= 0x0f; + printf("[*%s*]", conn_tab[vx_connector].name); + printf(": disable 'auto select' with DOS util!"); + } else { + printf("[*%s*]", conn_tab[vx_connector].name); + } +} + +static void +vxsetlink(void) +{ + int i, j; + char *reason, *warning; + static char prev_conn = -1; + + if (prev_conn == -1) { + prev_conn = vx_connector; + } + + i = vx_connector; /* default in EEPROM */ + reason = "default"; + warning = 0; + + if ((vx_connectors & conn_tab[vx_connector].bit) == 0) { + warning = "strange connector type in EEPROM."; + reason = "forced"; + i = CONNECTOR_UTP; + } + + if (warning != 0) { + printf("warning: %s\n", warning); + } + printf("selected %s. (%s)\n", conn_tab[i].name, reason); + + /* Set the selected connector. */ + GO_WINDOW(3); + j = inl(BASE + VX_W3_INTERNAL_CFG) & ~INTERNAL_CONNECTOR_MASK; + outl(j | (i <<INTERNAL_CONNECTOR_BITS), BASE + VX_W3_INTERNAL_CFG); + + /* First, disable all. */ + outw(STOP_TRANSCEIVER, BASE + VX_COMMAND); + udelay(8000); + GO_WINDOW(4); + outw(0, BASE + VX_W4_MEDIA_TYPE); + + /* Second, enable the selected one. */ + switch(i) { + case CONNECTOR_UTP: + GO_WINDOW(4); + outw(ENABLE_UTP, BASE + VX_W4_MEDIA_TYPE); + break; + case CONNECTOR_BNC: + outw(START_TRANSCEIVER,BASE + VX_COMMAND); + udelay(8000); + break; + case CONNECTOR_TX: + case CONNECTOR_FX: + GO_WINDOW(4); + outw(LINKBEAT_ENABLE, BASE + VX_W4_MEDIA_TYPE); + break; + default: /* AUI and MII fall here */ + break; + } + GO_WINDOW(1); +} + +static void t595_disable ( struct nic *nic ) { + + t595_reset(nic); + + outw(STOP_TRANSCEIVER, BASE + VX_COMMAND); + udelay(8000); + GO_WINDOW(4); + outw(0, BASE + VX_W4_MEDIA_TYPE); + GO_WINDOW(1); +} + +static void t595_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + +/************************************************************************** +ETH_PROBE - Look for an adapter +***************************************************************************/ +static int t595_probe ( struct nic *nic, struct pci_device *pci ) { + + int i; + unsigned short *p; + + if (pci->ioaddr == 0) + return 0; + eth_nic_base = pci->ioaddr; + + nic->irqno = 0; + nic->ioaddr = pci->ioaddr; + + GO_WINDOW(0); + outw(GLOBAL_RESET, BASE + VX_COMMAND); + VX_BUSY_WAIT; + + vxgetlink(); + +/* + printf("\nEEPROM:"); + for (i = 0; i < (EEPROMSIZE/2); i++) { + printf("%hX:", get_e(i)); + } + printf("\n"); +*/ + /* + * Read the station address from the eeprom + */ + p = (unsigned short *) nic->node_addr; + for (i = 0; i < 3; i++) { + GO_WINDOW(0); + p[i] = htons(get_e(EEPROM_OEM_ADDR_0 + i)); + GO_WINDOW(2); + outw(ntohs(p[i]), BASE + VX_W2_ADDR_0 + (i * 2)); + } + + DBG ( "Ethernet address: %s\n", eth_ntoa (nic->node_addr) ); + + t595_reset(nic); + nic->nic_op = &t595_operations; + return 1; + +} + +static struct nic_operations t595_operations = { + .connect = dummy_connect, + .poll = t595_poll, + .transmit = t595_transmit, + .irq = t595_irq, + +}; + +static struct pci_device_id t595_nics[] = { +PCI_ROM(0x10b7, 0x5900, "3c590", "3Com590", 0), /* Vortex 10Mbps */ +PCI_ROM(0x10b7, 0x5950, "3c595", "3Com595", 0), /* Vortex 100baseTx */ +PCI_ROM(0x10b7, 0x5951, "3c595-1", "3Com595", 0), /* Vortex 100baseT4 */ +PCI_ROM(0x10b7, 0x5952, "3c595-2", "3Com595", 0), /* Vortex 100base-MII */ +PCI_ROM(0x10b7, 0x9000, "3c900-tpo", "3Com900-TPO", 0), /* 10 Base TPO */ +PCI_ROM(0x10b7, 0x9001, "3c900-t4", "3Com900-Combo", 0), /* 10/100 T4 */ +PCI_ROM(0x10b7, 0x9004, "3c900b-tpo", "3Com900B-TPO", 0), /* 10 Base TPO */ +PCI_ROM(0x10b7, 0x9005, "3c900b-combo", "3Com900B-Combo", 0), /* 10 Base Combo */ +PCI_ROM(0x10b7, 0x9006, "3c900b-tpb2", "3Com900B-2/T", 0), /* 10 Base TP and Base2 */ +PCI_ROM(0x10b7, 0x900a, "3c900b-fl", "3Com900B-FL", 0), /* 10 Base F */ +PCI_ROM(0x10b7, 0x9800, "3c980-cyclone-1", "3Com980-Cyclone", 0), /* Cyclone */ +PCI_ROM(0x10b7, 0x9805, "3c9805-1", "3Com9805", 0), /* Dual Port Server Cyclone */ +PCI_ROM(0x10b7, 0x7646, "3csoho100-tx-1", "3CSOHO100-TX", 0), /* Hurricane */ +PCI_ROM(0x10b7, 0x4500, "3c450-1", "3Com450 HomePNA Tornado", 0), +}; + +PCI_DRIVER ( t595_driver, t595_nics, PCI_NO_CLASS ); + +DRIVER ( "3C595", nic_driver, pci_driver, t595_driver, + t595_probe, t595_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/3c595.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c595.h new file mode 100644 index 0000000..e27d204 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c595.h @@ -0,0 +1,437 @@ +/* + * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. 2. The name + * of the author may not be used to endorse or promote products derived from + * this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + October 2, 1994 + + Modified by: Andres Vega Garcia + + INRIA - Sophia Antipolis, France + e-mail: avega@sophia.inria.fr + finger: avega@pax.inria.fr + + */ + +FILE_LICENCE ( BSD3 ); + +/* + * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the + * 3c590 family. + */ + +/* + * Modified by Shusuke Nisiyama <shu@athena.qe.eng.hokudai.ac.jp> + * for etherboot + * Mar. 14, 2000 +*/ + +/* + * Ethernet software status per interface. + */ + +/* + * Some global constants + */ + +#define TX_INIT_RATE 16 +#define TX_INIT_MAX_RATE 64 +#define RX_INIT_LATENCY 64 +#define RX_INIT_EARLY_THRESH 64 +#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */ +#define MIN_RX_EARLY_THRESHL 4 + +#define EEPROMSIZE 0x40 +#define MAX_EEPROMBUSY 1000 +#define VX_LAST_TAG 0xd7 +#define VX_MAX_BOARDS 16 +#define VX_ID_PORT 0x100 + +/* + * some macros to acces long named fields + */ +#define BASE (eth_nic_base) + +/* + * Commands to read/write EEPROM trough EEPROM command register (Window 0, + * Offset 0xa) + */ +#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ +#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ +#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ +#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ + +#define EEPROM_BUSY (1<<15) + +/* + * Some short functions, worth to let them be a macro + */ + +/************************************************************************** + * * + * These define the EEPROM data structure. They are used in the probe + * function to verify the existence of the adapter after having sent + * the ID_Sequence. + * + * There are others but only the ones we use are defined here. + * + **************************************************************************/ + +#define EEPROM_NODE_ADDR_0 0x0 /* Word */ +#define EEPROM_NODE_ADDR_1 0x1 /* Word */ +#define EEPROM_NODE_ADDR_2 0x2 /* Word */ +#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ +#define EEPROM_MFG_ID 0x7 /* 0x6d50 */ +#define EEPROM_ADDR_CFG 0x8 /* Base addr */ +#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ +#define EEPROM_OEM_ADDR_0 0xa /* Word */ +#define EEPROM_OEM_ADDR_1 0xb /* Word */ +#define EEPROM_OEM_ADDR_2 0xc /* Word */ +#define EEPROM_SOFT_INFO_2 0xf /* Software information 2 */ + +#define NO_RX_OVN_ANOMALY (1<<5) + +/************************************************************************** + * * + * These are the registers for the 3Com 3c509 and their bit patterns when * + * applicable. They have been taken out the the "EtherLink III Parallel * + * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * + * from 3com. * + * * + **************************************************************************/ + +#define VX_COMMAND 0x0e /* Write. BASE+0x0e is always a + * command reg. */ +#define VX_STATUS 0x0e /* Read. BASE+0x0e is always status + * reg. */ +#define VX_WINDOW 0x0f /* Read. BASE+0x0f is always window + * reg. */ +/* + * Window 0 registers. Setup. + */ +/* Write */ +#define VX_W0_EEPROM_DATA 0x0c +#define VX_W0_EEPROM_COMMAND 0x0a +#define VX_W0_RESOURCE_CFG 0x08 +#define VX_W0_ADDRESS_CFG 0x06 +#define VX_W0_CONFIG_CTRL 0x04 + /* Read */ +#define VX_W0_PRODUCT_ID 0x02 +#define VX_W0_MFG_ID 0x00 + + +/* + * Window 1 registers. Operating Set. + */ +/* Write */ +#define VX_W1_TX_PIO_WR_2 0x02 +#define VX_W1_TX_PIO_WR_1 0x00 +/* Read */ +#define VX_W1_FREE_TX 0x0c +#define VX_W1_TX_STATUS 0x0b /* byte */ +#define VX_W1_TIMER 0x0a /* byte */ +#define VX_W1_RX_STATUS 0x08 +#define VX_W1_RX_PIO_RD_2 0x02 +#define VX_W1_RX_PIO_RD_1 0x00 + +/* + * Window 2 registers. Station Address Setup/Read + */ +/* Read/Write */ +#define VX_W2_ADDR_5 0x05 +#define VX_W2_ADDR_4 0x04 +#define VX_W2_ADDR_3 0x03 +#define VX_W2_ADDR_2 0x02 +#define VX_W2_ADDR_1 0x01 +#define VX_W2_ADDR_0 0x00 + +/* + * Window 3 registers. FIFO Management. + */ +/* Read */ +#define VX_W3_INTERNAL_CFG 0x00 +#define VX_W3_RESET_OPT 0x08 +#define VX_W3_FREE_TX 0x0c +#define VX_W3_FREE_RX 0x0a + +/* + * Window 4 registers. Diagnostics. + */ +/* Read/Write */ +#define VX_W4_MEDIA_TYPE 0x0a +#define VX_W4_CTRLR_STATUS 0x08 +#define VX_W4_NET_DIAG 0x06 +#define VX_W4_FIFO_DIAG 0x04 +#define VX_W4_HOST_DIAG 0x02 +#define VX_W4_TX_DIAG 0x00 + +/* + * Window 5 Registers. Results and Internal status. + */ +/* Read */ +#define VX_W5_READ_0_MASK 0x0c +#define VX_W5_INTR_MASK 0x0a +#define VX_W5_RX_FILTER 0x08 +#define VX_W5_RX_EARLY_THRESH 0x06 +#define VX_W5_TX_AVAIL_THRESH 0x02 +#define VX_W5_TX_START_THRESH 0x00 + +/* + * Window 6 registers. Statistics. + */ +/* Read/Write */ +#define TX_TOTAL_OK 0x0c +#define RX_TOTAL_OK 0x0a +#define TX_DEFERRALS 0x08 +#define RX_FRAMES_OK 0x07 +#define TX_FRAMES_OK 0x06 +#define RX_OVERRUNS 0x05 +#define TX_COLLISIONS 0x04 +#define TX_AFTER_1_COLLISION 0x03 +#define TX_AFTER_X_COLLISIONS 0x02 +#define TX_NO_SQE 0x01 +#define TX_CD_LOST 0x00 + +/**************************************** + * + * Register definitions. + * + ****************************************/ + +/* + * Command register. All windows. + * + * 16 bit register. + * 15-11: 5-bit code for command to be executed. + * 10-0: 11-bit arg if any. For commands with no args; + * this can be set to anything. + */ +#define GLOBAL_RESET (unsigned short) 0x0000 /* Wait at least 1ms + * after issuing */ +#define WINDOW_SELECT (unsigned short) (0x1<<11) +#define START_TRANSCEIVER (unsigned short) (0x2<<11) /* Read ADDR_CFG reg to + * determine whether + * this is needed. If + * so; wait 800 uSec + * before using trans- + * ceiver. */ +#define RX_DISABLE (unsigned short) (0x3<<11) /* state disabled on + * power-up */ +#define RX_ENABLE (unsigned short) (0x4<<11) +#define RX_RESET (unsigned short) (0x5<<11) +#define RX_DISCARD_TOP_PACK (unsigned short) (0x8<<11) +#define TX_ENABLE (unsigned short) (0x9<<11) +#define TX_DISABLE (unsigned short) (0xa<<11) +#define TX_RESET (unsigned short) (0xb<<11) +#define REQ_INTR (unsigned short) (0xc<<11) +/* + * The following C_* acknowledge the various interrupts. Some of them don't + * do anything. See the manual. + */ +#define ACK_INTR (unsigned short) (0x6800) +# define C_INTR_LATCH (unsigned short) (ACK_INTR|0x1) +# define C_CARD_FAILURE (unsigned short) (ACK_INTR|0x2) +# define C_TX_COMPLETE (unsigned short) (ACK_INTR|0x4) +# define C_TX_AVAIL (unsigned short) (ACK_INTR|0x8) +# define C_RX_COMPLETE (unsigned short) (ACK_INTR|0x10) +# define C_RX_EARLY (unsigned short) (ACK_INTR|0x20) +# define C_INT_RQD (unsigned short) (ACK_INTR|0x40) +# define C_UPD_STATS (unsigned short) (ACK_INTR|0x80) +#define SET_INTR_MASK (unsigned short) (0xe<<11) +#define SET_RD_0_MASK (unsigned short) (0xf<<11) +#define SET_RX_FILTER (unsigned short) (0x10<<11) +# define FIL_INDIVIDUAL (unsigned short) (0x1) +# define FIL_MULTICAST (unsigned short) (0x02) +# define FIL_BRDCST (unsigned short) (0x04) +# define FIL_PROMISC (unsigned short) (0x08) +#define SET_RX_EARLY_THRESH (unsigned short) (0x11<<11) +#define SET_TX_AVAIL_THRESH (unsigned short) (0x12<<11) +#define SET_TX_START_THRESH (unsigned short) (0x13<<11) +#define STATS_ENABLE (unsigned short) (0x15<<11) +#define STATS_DISABLE (unsigned short) (0x16<<11) +#define STOP_TRANSCEIVER (unsigned short) (0x17<<11) + +/* + * Status register. All windows. + * + * 15-13: Window number(0-7). + * 12: Command_in_progress. + * 11: reserved. + * 10: reserved. + * 9: reserved. + * 8: reserved. + * 7: Update Statistics. + * 6: Interrupt Requested. + * 5: RX Early. + * 4: RX Complete. + * 3: TX Available. + * 2: TX Complete. + * 1: Adapter Failure. + * 0: Interrupt Latch. + */ +#define S_INTR_LATCH (unsigned short) (0x1) +#define S_CARD_FAILURE (unsigned short) (0x2) +#define S_TX_COMPLETE (unsigned short) (0x4) +#define S_TX_AVAIL (unsigned short) (0x8) +#define S_RX_COMPLETE (unsigned short) (0x10) +#define S_RX_EARLY (unsigned short) (0x20) +#define S_INT_RQD (unsigned short) (0x40) +#define S_UPD_STATS (unsigned short) (0x80) +#define S_COMMAND_IN_PROGRESS (unsigned short) (0x1000) + +#define VX_BUSY_WAIT while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS) + +/* Address Config. Register. + * Window 0/Port 06 + */ + +#define ACF_CONNECTOR_BITS 14 +#define ACF_CONNECTOR_UTP 0 +#define ACF_CONNECTOR_AUI 1 +#define ACF_CONNECTOR_BNC 3 + +#define INTERNAL_CONNECTOR_BITS 20 +#define INTERNAL_CONNECTOR_MASK 0x01700000 + +/* + * FIFO Registers. RX Status. + * + * 15: Incomplete or FIFO empty. + * 14: 1: Error in RX Packet 0: Incomplete or no error. + * 13-11: Type of error. + * 1000 = Overrun. + * 1011 = Run Packet Error. + * 1100 = Alignment Error. + * 1101 = CRC Error. + * 1001 = Oversize Packet Error (>1514 bytes) + * 0010 = Dribble Bits. + * (all other error codes, no errors.) + * + * 10-0: RX Bytes (0-1514) + */ +#define ERR_INCOMPLETE (unsigned short) (0x8000) +#define ERR_RX (unsigned short) (0x4000) +#define ERR_MASK (unsigned short) (0x7800) +#define ERR_OVERRUN (unsigned short) (0x4000) +#define ERR_RUNT (unsigned short) (0x5800) +#define ERR_ALIGNMENT (unsigned short) (0x6000) +#define ERR_CRC (unsigned short) (0x6800) +#define ERR_OVERSIZE (unsigned short) (0x4800) +#define ERR_DRIBBLE (unsigned short) (0x1000) + +/* + * TX Status. + * + * Reports the transmit status of a completed transmission. Writing this + * register pops the transmit completion stack. + * + * Window 1/Port 0x0b. + * + * 7: Complete + * 6: Interrupt on successful transmission requested. + * 5: Jabber Error (TP Only, TX Reset required. ) + * 4: Underrun (TX Reset required. ) + * 3: Maximum Collisions. + * 2: TX Status Overflow. + * 1-0: Undefined. + * + */ +#define TXS_COMPLETE 0x80 +#define TXS_INTR_REQ 0x40 +#define TXS_JABBER 0x20 +#define TXS_UNDERRUN 0x10 +#define TXS_MAX_COLLISION 0x8 +#define TXS_STATUS_OVERFLOW 0x4 + +#define RS_AUI (1<<5) +#define RS_BNC (1<<4) +#define RS_UTP (1<<3) +#define RS_T4 (1<<0) +#define RS_TX (1<<1) +#define RS_FX (1<<2) +#define RS_MII (1<<6) + + +/* + * FIFO Status (Window 4) + * + * Supports FIFO diagnostics + * + * Window 4/Port 0x04.1 + * + * 15: 1=RX receiving (RO). Set when a packet is being received + * into the RX FIFO. + * 14: Reserved + * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. + * Requires RX Reset or Global Reset command to recover. + * It is generated when you read past the end of a packet - + * reading past what has been received so far will give bad + * data. + * 12: 1=RX status overrun (RO). Set when there are already 8 + * packets in the RX FIFO. While this bit is set, no additional + * packets are received. Requires no action on the part of + * the host. The condition is cleared once a packet has been + * read out of the RX FIFO. + * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there + * may not be an overrun packet yet). While this bit is set, + * no additional packets will be received (some additional + * bytes can still be pending between the wire and the RX + * FIFO). Requires no action on the part of the host. The + * condition is cleared once a few bytes have been read out + * from the RX FIFO. + * 10: 1=TX overrun (RO). Generates adapter failure interrupt. + * Requires TX Reset or Global Reset command to recover. + * Disables Transmitter. + * 9-8: Unassigned. + * 7-0: Built in self test bits for the RX and TX FIFO's. + */ +#define FIFOS_RX_RECEIVING (unsigned short) 0x8000 +#define FIFOS_RX_UNDERRUN (unsigned short) 0x2000 +#define FIFOS_RX_STATUS_OVERRUN (unsigned short) 0x1000 +#define FIFOS_RX_OVERRUN (unsigned short) 0x0800 +#define FIFOS_TX_OVERRUN (unsigned short) 0x0400 + +/* + * Misc defines for various things. + */ +#define TAG_ADAPTER 0xd0 +#define ACTIVATE_ADAPTER_TO_CONFIG 0xff +#define ENABLE_DRQ_IRQ 0x0001 +#define MFG_ID 0x506d /* `TCM' */ +#define PROD_ID 0x5090 +#define GO_WINDOW(x) outw(WINDOW_SELECT|(x),BASE+VX_COMMAND) +#define JABBER_GUARD_ENABLE 0x40 +#define LINKBEAT_ENABLE 0x80 +#define ENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE) +#define DISABLE_UTP 0x0 +#define RX_BYTES_MASK (unsigned short) (0x07ff) +#define RX_ERROR 0x4000 +#define RX_INCOMPLETE 0x8000 +#define TX_INDICATE 1<<15 +#define is_eeprom_busy(b) (inw((b)+VX_W0_EEPROM_COMMAND)&EEPROM_BUSY) + +#define VX_IOSIZE 0x20 + +#define VX_CONNECTORS 8 + +/* + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/3c5x9.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c5x9.c new file mode 100644 index 0000000..87c9f29 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c5x9.c @@ -0,0 +1,416 @@ +/************************************************************************** +ETHERBOOT - BOOTP/TFTP Bootstrap Program + +Author: Martin Renters. + Date: Mar 22 1995 + + This code is based heavily on David Greenman's if_ed.c driver and + Andres Vega Garcia's if_ep.c driver. + + Copyright (C) 1993-1994, David Greenman, Martin Renters. + Copyright (C) 1993-1995, Andres Vega Garcia. + Copyright (C) 1995, Serge Babkin. + This software may be used, modified, copied, distributed, and sold, in + both source and binary form provided that the above copyright and these + terms are retained. Under no circumstances are the authors responsible for + the proper functioning of this software, nor do the authors assume any + responsibility for damages incurred with its use. + +3c509 support added by Serge Babkin (babkin@hq.icb.chel.su) + +$Id$ + +***************************************************************************/ + +FILE_LICENCE ( BSD2 ); + +/* #define EDEBUG */ + +#include <gpxe/ethernet.h> +#include "etherboot.h" +#include "nic.h" +#include <gpxe/isa.h> +#include "3c509.h" + +static enum { none, bnc, utp } connector = none; /* for 3C509 */ + +/************************************************************************** +ETH_RESET - Reset adapter +***************************************************************************/ +void t5x9_disable ( struct nic *nic ) { + /* stop card */ + outw(RX_DISABLE, nic->ioaddr + EP_COMMAND); + outw(RX_DISCARD_TOP_PACK, nic->ioaddr + EP_COMMAND); + while (inw(nic->ioaddr + EP_STATUS) & S_COMMAND_IN_PROGRESS) + ; + outw(TX_DISABLE, nic->ioaddr + EP_COMMAND); + outw(STOP_TRANSCEIVER, nic->ioaddr + EP_COMMAND); + udelay(1000); + outw(RX_RESET, nic->ioaddr + EP_COMMAND); + outw(TX_RESET, nic->ioaddr + EP_COMMAND); + outw(C_INTR_LATCH, nic->ioaddr + EP_COMMAND); + outw(SET_RD_0_MASK, nic->ioaddr + EP_COMMAND); + outw(SET_INTR_MASK, nic->ioaddr + EP_COMMAND); + outw(SET_RX_FILTER, nic->ioaddr + EP_COMMAND); + + /* + * wait for reset to complete + */ + while (inw(nic->ioaddr + EP_STATUS) & S_COMMAND_IN_PROGRESS) + ; + + GO_WINDOW(nic->ioaddr,0); + + /* Disable the card */ + outw(0, nic->ioaddr + EP_W0_CONFIG_CTRL); + + /* Configure IRQ to none */ + outw(SET_IRQ(0), nic->ioaddr + EP_W0_RESOURCE_CFG); +} + +static void t509_enable ( struct nic *nic ) { + int i; + + /* Enable the card */ + GO_WINDOW(nic->ioaddr,0); + outw(ENABLE_DRQ_IRQ, nic->ioaddr + EP_W0_CONFIG_CTRL); + + GO_WINDOW(nic->ioaddr,2); + + /* Reload the ether_addr. */ + for (i = 0; i < ETH_ALEN; i++) + outb(nic->node_addr[i], nic->ioaddr + EP_W2_ADDR_0 + i); + + outw(RX_RESET, nic->ioaddr + EP_COMMAND); + outw(TX_RESET, nic->ioaddr + EP_COMMAND); + + /* Window 1 is operating window */ + GO_WINDOW(nic->ioaddr,1); + for (i = 0; i < 31; i++) + inb(nic->ioaddr + EP_W1_TX_STATUS); + + /* get rid of stray intr's */ + outw(ACK_INTR | 0xff, nic->ioaddr + EP_COMMAND); + + outw(SET_RD_0_MASK | S_5_INTS, nic->ioaddr + EP_COMMAND); + + outw(SET_INTR_MASK, nic->ioaddr + EP_COMMAND); + + outw(SET_RX_FILTER | FIL_GROUP | FIL_INDIVIDUAL | FIL_BRDCST, + nic->ioaddr + EP_COMMAND); + + /* configure BNC */ + if (connector == bnc) { + outw(START_TRANSCEIVER, nic->ioaddr + EP_COMMAND); + udelay(1000); + } + /* configure UTP */ + else if (connector == utp) { + GO_WINDOW(nic->ioaddr,4); + outw(ENABLE_UTP, nic->ioaddr + EP_W4_MEDIA_TYPE); + sleep(2); /* Give time for media to negotiate */ + GO_WINDOW(nic->ioaddr,1); + } + + /* start transceiver and receiver */ + outw(RX_ENABLE, nic->ioaddr + EP_COMMAND); + outw(TX_ENABLE, nic->ioaddr + EP_COMMAND); + + /* set early threshold for minimal packet length */ + outw(SET_RX_EARLY_THRESH | ETH_ZLEN, nic->ioaddr + EP_COMMAND); + outw(SET_TX_START_THRESH | 16, nic->ioaddr + EP_COMMAND); +} + +static void t509_reset ( struct nic *nic ) { + t5x9_disable ( nic ); + t509_enable ( nic ); +} + +/************************************************************************** +ETH_TRANSMIT - Transmit a frame +***************************************************************************/ +static char padmap[] = { + 0, 3, 2, 1}; + +static void t509_transmit( +struct nic *nic, +const char *d, /* Destination */ +unsigned int t, /* Type */ +unsigned int s, /* size */ +const char *p) /* Packet */ +{ + register unsigned int len; + int pad; + int status; + +#ifdef EDEBUG + printf("{l=%d,t=%hX}",s+ETH_HLEN,t); +#endif + + /* swap bytes of type */ + t= htons(t); + + len=s+ETH_HLEN; /* actual length of packet */ + pad = padmap[len & 3]; + + /* + * The 3c509 automatically pads short packets to minimum ethernet length, + * but we drop packets that are too large. Perhaps we should truncate + * them instead? + */ + if (len + pad > ETH_FRAME_LEN) { + return; + } + + /* drop acknowledgements */ + while ((status=inb(nic->ioaddr + EP_W1_TX_STATUS)) & TXS_COMPLETE ) { + if (status & (TXS_UNDERRUN|TXS_MAX_COLLISION|TXS_STATUS_OVERFLOW)) { + outw(TX_RESET, nic->ioaddr + EP_COMMAND); + outw(TX_ENABLE, nic->ioaddr + EP_COMMAND); + } + outb(0x0, nic->ioaddr + EP_W1_TX_STATUS); + } + + while (inw(nic->ioaddr + EP_W1_FREE_TX) < (unsigned short)len + pad + 4) + ; /* no room in FIFO */ + + outw(len, nic->ioaddr + EP_W1_TX_PIO_WR_1); + outw(0x0, nic->ioaddr + EP_W1_TX_PIO_WR_1); /* Second dword meaningless */ + + /* write packet */ + outsw(nic->ioaddr + EP_W1_TX_PIO_WR_1, d, ETH_ALEN/2); + outsw(nic->ioaddr + EP_W1_TX_PIO_WR_1, nic->node_addr, ETH_ALEN/2); + outw(t, nic->ioaddr + EP_W1_TX_PIO_WR_1); + outsw(nic->ioaddr + EP_W1_TX_PIO_WR_1, p, s / 2); + if (s & 1) + outb(*(p+s - 1), nic->ioaddr + EP_W1_TX_PIO_WR_1); + + while (pad--) + outb(0, nic->ioaddr + EP_W1_TX_PIO_WR_1); /* Padding */ + + /* wait for Tx complete */ + while((inw(nic->ioaddr + EP_STATUS) & S_COMMAND_IN_PROGRESS) != 0) + ; +} + +/************************************************************************** +ETH_POLL - Wait for a frame +***************************************************************************/ +static int t509_poll(struct nic *nic, int retrieve) +{ + /* common variables */ + /* variables for 3C509 */ + short status, cst; + register short rx_fifo; + + cst=inw(nic->ioaddr + EP_STATUS); + +#ifdef EDEBUG + if(cst & 0x1FFF) + printf("-%hX-",cst); +#endif + + if( (cst & S_RX_COMPLETE)==0 ) { + /* acknowledge everything */ + outw(ACK_INTR| (cst & S_5_INTS), nic->ioaddr + EP_COMMAND); + outw(C_INTR_LATCH, nic->ioaddr + EP_COMMAND); + + return 0; + } + + status = inw(nic->ioaddr + EP_W1_RX_STATUS); +#ifdef EDEBUG + printf("*%hX*",status); +#endif + + if (status & ERR_RX) { + outw(RX_DISCARD_TOP_PACK, nic->ioaddr + EP_COMMAND); + return 0; + } + + rx_fifo = status & RX_BYTES_MASK; + if (rx_fifo==0) + return 0; + + if ( ! retrieve ) return 1; + + /* read packet */ +#ifdef EDEBUG + printf("[l=%d",rx_fifo); +#endif + insw(nic->ioaddr + EP_W1_RX_PIO_RD_1, nic->packet, rx_fifo / 2); + if(rx_fifo & 1) + nic->packet[rx_fifo-1]=inb(nic->ioaddr + EP_W1_RX_PIO_RD_1); + nic->packetlen=rx_fifo; + + while(1) { + status = inw(nic->ioaddr + EP_W1_RX_STATUS); +#ifdef EDEBUG + printf("*%hX*",status); +#endif + rx_fifo = status & RX_BYTES_MASK; + if(rx_fifo>0) { + insw(nic->ioaddr + EP_W1_RX_PIO_RD_1, nic->packet+nic->packetlen, rx_fifo / 2); + if(rx_fifo & 1) + nic->packet[nic->packetlen+rx_fifo-1]=inb(nic->ioaddr + EP_W1_RX_PIO_RD_1); + nic->packetlen+=rx_fifo; +#ifdef EDEBUG + printf("+%d",rx_fifo); +#endif + } + if(( status & RX_INCOMPLETE )==0) { +#ifdef EDEBUG + printf("=%d",nic->packetlen); +#endif + break; + } + udelay(1000); /* if incomplete wait 1 ms */ + } + /* acknowledge reception of packet */ + outw(RX_DISCARD_TOP_PACK, nic->ioaddr + EP_COMMAND); + while (inw(nic->ioaddr + EP_STATUS) & S_COMMAND_IN_PROGRESS) + ; +#ifdef EDEBUG +{ + unsigned short type = 0; /* used by EDEBUG */ + type = (nic->packet[12]<<8) | nic->packet[13]; + if(nic->packet[0]+nic->packet[1]+nic->packet[2]+nic->packet[3]+nic->packet[4]+ + nic->packet[5] == 0xFF*ETH_ALEN) + printf(",t=%hX,b]",type); + else + printf(",t=%hX]",type); +} +#endif + return (1); +} + +/************************************************************************** +ETH_IRQ - interrupt handling +***************************************************************************/ +static void t509_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + +/************************************************************************* + 3Com 509 - specific routines +**************************************************************************/ + +static int eeprom_rdy ( uint16_t ioaddr ) { + int i; + + for (i = 0; is_eeprom_busy(ioaddr) && i < MAX_EEPROMBUSY; i++); + if (i >= MAX_EEPROMBUSY) { + /* printf("3c509: eeprom failed to come ready.\n"); */ + /* memory in EPROM is tight */ + /* printf("3c509: eeprom busy.\n"); */ + return (0); + } + return (1); +} + +/* + * get_e: gets a 16 bits word from the EEPROM. + */ +static int get_e ( uint16_t ioaddr, int offset ) { + GO_WINDOW(ioaddr,0); + if (!eeprom_rdy(ioaddr)) + return (0xffff); + outw(EEPROM_CMD_RD | offset, ioaddr + EP_W0_EEPROM_COMMAND); + if (!eeprom_rdy(ioaddr)) + return (0xffff); + return (inw(ioaddr + EP_W0_EEPROM_DATA)); +} + +static struct nic_operations t509_operations = { + .connect = dummy_connect, + .poll = t509_poll, + .transmit = t509_transmit, + .irq = t509_irq, +}; + +/************************************************************************** +ETH_PROBE - Look for an adapter +***************************************************************************/ +int t5x9_probe ( struct nic *nic, + uint16_t prod_id_check, uint16_t prod_id_mask ) { + uint16_t prod_id; + int i,j; + unsigned short *p; + + /* Check product ID */ + prod_id = get_e ( nic->ioaddr, EEPROM_PROD_ID ); + if ( ( prod_id & prod_id_mask ) != prod_id_check ) { + printf ( "EEPROM Product ID is incorrect (%hx & %hx != %hx)\n", + prod_id, prod_id_mask, prod_id_check ); + return 0; + } + + /* test for presence of connectors */ + GO_WINDOW(nic->ioaddr,0); + i = inw(nic->ioaddr + EP_W0_CONFIG_CTRL); + j = (inw(nic->ioaddr + EP_W0_ADDRESS_CFG) >> 14) & 0x3; + + switch(j) { + case 0: + if (i & IS_UTP) { + printf("10baseT\n"); + connector = utp; + } else { + printf("10baseT not present\n"); + return 0; + } + break; + case 1: + if (i & IS_AUI) { + printf("10base5\n"); + } else { + printf("10base5 not present\n"); + return 0; + } + break; + case 3: + if (i & IS_BNC) { + printf("10base2\n"); + connector = bnc; + } else { + printf("10base2 not present\n"); + return 0; + } + break; + default: + printf("unknown connector\n"); + return 0; + } + + /* + * Read the station address from the eeprom + */ + p = (unsigned short *) nic->node_addr; + for (i = 0; i < ETH_ALEN / 2; i++) { + p[i] = htons(get_e(nic->ioaddr,i)); + GO_WINDOW(nic->ioaddr,2); + outw(ntohs(p[i]), nic->ioaddr + EP_W2_ADDR_0 + (i * 2)); + } + + DBG ( "Ethernet Address: %s\n", eth_ntoa ( nic->node_addr ) ); + + t509_reset(nic); + + nic->nic_op = &t509_operations; + return 1; + +} + +/* + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/3c90x.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c90x.c new file mode 100644 index 0000000..9c1879b --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c90x.c @@ -0,0 +1,994 @@ +/* + * 3c90x.c -- This file implements a gPXE API 3c90x driver + * + * Originally written for etherboot by: + * Greg Beeley, Greg.Beeley@LightSys.org + * Modified by Steve Smith, + * Steve.Smith@Juno.Com. Alignment bug fix Neil Newell (nn@icenoir.net). + * Almost totally Rewritten to use gPXE API, implementation of tx/rx ring support + * by Thomas Miletich, thomas.miletich@gmail.com + * Thanks to Marty Connor and Stefan Hajnoczi for their help and feedback, + * and to Daniel Verkamp for his help with testing. + * + * Copyright (c) 2009 Thomas Miletich + * + * Copyright (c) 1999 LightSys Technology Services, Inc. + * Portions Copyright (c) 1999 Steve Smith + * + * This program may be re-distributed in source or binary form, modified, + * sold, or copied for any purpose, provided that the above copyright message + * and this text are included with all source copies or derivative works, and + * provided that the above copyright message and this text are included in the + * documentation of any binary-only distributions. This program is distributed + * WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR + * PURPOSE or MERCHANTABILITY. Please read the associated documentation + * "3c90x.txt" before compiling and using this driver. + * + * [ --mdc 20090313 The 3c90x.txt file is now at: + * http://etherboot.org/wiki/appnotes/3c90x_issues ] + * + * This program was written with the assistance of the 3com documentation for + * the 3c905B-TX card, as well as with some assistance from the 3c59x + * driver Donald Becker wrote for the Linux kernel, and with some assistance + * from the remainder of the Etherboot distribution. + * + * Indented with unix 'indent' command: + * $ indent -kr -i8 3c90x.c + */ + +FILE_LICENCE ( BSD2 ); + +#include <stdint.h> +#include <stdio.h> +#include <stdlib.h> +#include <stddef.h> +#include <string.h> +#include <unistd.h> +#include <assert.h> +#include <byteswap.h> +#include <errno.h> +#include <gpxe/ethernet.h> +#include <gpxe/if_ether.h> +#include <gpxe/io.h> +#include <gpxe/iobuf.h> +#include <gpxe/malloc.h> +#include <gpxe/netdevice.h> +#include <gpxe/pci.h> +#include <gpxe/timer.h> +#include <gpxe/nvs.h> + +#include "3c90x.h" + +/** + * a3c90x_internal_IssueCommand: sends a command to the 3c90x card + * and waits for it's completion + * + * @v ioaddr IOAddress of the NIC + * @v cmd Command to be issued + * @v param Command parameter + */ +static void a3c90x_internal_IssueCommand(int ioaddr, int cmd, int param) +{ + unsigned int val = (cmd << 11) | param; + int cnt = 0; + + DBGP("a3c90x_internal_IssueCommand\n"); + + /* Send the cmd to the cmd register */ + outw(val, ioaddr + regCommandIntStatus_w); + + /* Wait for the cmd to complete */ + for (cnt = 0; cnt < 100000; cnt++) { + if (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS) { + continue; + } else { + DBG2("Command 0x%04X finished in time. cnt = %d.\n", cmd, cnt); + return; + } + } + + DBG("Command 0x%04X DID NOT finish in time. cnt = %d.\n", cmd, cnt); +} + +/** + * a3c90x_internal_SetWindow: selects a register window set. + * + * @v inf_3c90x private NIC data + * @v window window to be selected + */ +static void a3c90x_internal_SetWindow(struct INF_3C90X *inf_3c90x, int window) +{ + DBGP("a3c90x_internal_SetWindow\n"); + /* Window already as set? */ + if (inf_3c90x->CurrentWindow == window) + return; + + /* Issue the window command. */ + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, + cmdSelectRegisterWindow, window); + inf_3c90x->CurrentWindow = window; + + return; +} + +static void a3c90x_internal_WaitForEeprom(struct INF_3C90X *inf_3c90x) +{ + int cnt = 0; + + DBGP("a3c90x_internal_WaitForEeprom\n"); + + while (eepromBusy & inw(inf_3c90x->IOAddr + regEepromCommand_0_w)) { + if (cnt == EEPROM_TIMEOUT) { + DBG("Read from eeprom failed: timeout\n"); + return; + } + udelay(1); + cnt++; + } +} + +/** + * a3c90x_internal_ReadEeprom - nvs routine to read eeprom data + * We only support reading one word(2 byte). The nvs subsystem will make sure + * that the routine will never be called with len != 2. + * + * @v nvs nvs data. + * @v address eeprom address to read data from. + * @v data data is put here. + * @v len number of bytes to read. + */ +static int +a3c90x_internal_ReadEeprom(struct nvs_device *nvs, unsigned int address, void *data, size_t len) +{ + unsigned short *dest = (unsigned short *) data; + struct INF_3C90X *inf_3c90x = + container_of(nvs, struct INF_3C90X, nvs); + + DBGP("a3c90x_internal_ReadEeprom\n"); + + /* we support reading 2 bytes only */ + assert(len == 2); + + /* Select correct window */ + a3c90x_internal_SetWindow(inf_3c90x, winEepromBios0); + + /* set eepromRead bits in command sent to NIC */ + address += (inf_3c90x->is3c556 ? eepromRead_556 : eepromRead); + + a3c90x_internal_WaitForEeprom(inf_3c90x); + /* send address to NIC */ + outw(address, inf_3c90x->IOAddr + regEepromCommand_0_w); + a3c90x_internal_WaitForEeprom(inf_3c90x); + + /* read value */ + *dest = inw(inf_3c90x->IOAddr + regEepromData_0_w); + + return 0; +} + +/** + * a3c90x_internal_WriteEeprom - nvs routine to write eeprom data + * currently not implemented + * + * @v nvs nvs data. + * @v address eeprom address to read data from. + * @v data data is put here. + * @v len number of bytes to read. + */ +static int +a3c90x_internal_WriteEeprom(struct nvs_device *nvs __unused, + unsigned int address __unused, + const void *data __unused, size_t len __unused) +{ + return -ENOTSUP; +} + +static void a3c90x_internal_ReadEepromContents(struct INF_3C90X *inf_3c90x) +{ + int eeprom_size = (inf_3c90x->isBrev ? 0x20 : 0x17) * 2; + + DBGP("a3c90x_internal_ReadEepromContents\n"); + + nvs_read(&inf_3c90x->nvs, 0, inf_3c90x->eeprom, eeprom_size); +} + +/** + * a3c90x_reset: exported function that resets the card to its default + * state. This is so the Linux driver can re-set the card up the way + * it wants to. If CFG_3C90X_PRESERVE_XCVR is defined, then the reset will + * not alter the selected transceiver that we used to download the boot + * image. + * + * @v inf_3c90x Private NIC data + */ +static void a3c90x_reset(struct INF_3C90X *inf_3c90x) +{ + DBGP("a3c90x_reset\n"); + /* Send the reset command to the card */ + DBG("3c90x: Issuing RESET\n"); + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, cmdGlobalReset, 0); + + /* global reset command resets station mask, non-B revision cards + * require explicit reset of values + */ + a3c90x_internal_SetWindow(inf_3c90x, winAddressing2); + outw(0, inf_3c90x->IOAddr + regStationMask_2_3w + 0); + outw(0, inf_3c90x->IOAddr + regStationMask_2_3w + 2); + outw(0, inf_3c90x->IOAddr + regStationMask_2_3w + 4); + + /* Issue transmit reset, wait for command completion */ + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, cmdTxReset, 0); + + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, cmdTxEnable, 0); + + /* + * reset of the receiver on B-revision cards re-negotiates the link + * takes several seconds (a computer eternity) + */ + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, cmdRxReset, + inf_3c90x->isBrev ? 0x04 : 0x00); + + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, cmdRxEnable, 0); + + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, + cmdSetInterruptEnable, 0); + /* enable rxComplete and txComplete */ + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, + cmdSetIndicationEnable, + INT_TXCOMPLETE | INT_UPCOMPLETE); + /* acknowledge any pending status flags */ + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, + cmdAcknowledgeInterrupt, 0x661); + + return; +} + +/** + * a3c90x_setup_tx_ring - Allocates TX ring, initialize tx_desc values + * + * @v p Private NIC data + * + * @ret Returns 0 on success, negative on failure + */ +static int a3c90x_setup_tx_ring(struct INF_3C90X *p) +{ + DBGP("a3c90x_setup_tx_ring\n"); + p->tx_ring = + malloc_dma(TX_RING_SIZE * sizeof(struct TXD), TX_RING_ALIGN); + + if (!p->tx_ring) { + DBG("Could not allocate TX-ring\n"); + return -ENOMEM; + } + + memset(p->tx_ring, 0, TX_RING_SIZE * sizeof(struct TXD)); + p->tx_cur = 0; + p->tx_cnt = 0; + p->tx_tail = 0; + + return 0; +} + +/** + * a3c90x_process_tx_packets - Checks for successfully sent packets, + * reports them to gPXE with netdev_tx_complete(); + * + * @v netdev Network device info + */ +static void a3c90x_process_tx_packets(struct net_device *netdev) +{ + struct INF_3C90X *p = netdev_priv(netdev); + unsigned int downlist_ptr; + + DBGP("a3c90x_process_tx_packets\n"); + + DBG(" tx_cnt: %d\n", p->tx_cnt); + + while (p->tx_tail != p->tx_cur) { + + downlist_ptr = inl(p->IOAddr + regDnListPtr_l); + + DBG(" downlist_ptr: %#08x\n", downlist_ptr); + DBG(" tx_tail: %d tx_cur: %d\n", p->tx_tail, p->tx_cur); + + /* NIC is currently working on this tx desc */ + if(downlist_ptr == virt_to_bus(p->tx_ring + p->tx_tail)) + return; + + netdev_tx_complete(netdev, p->tx_iobuf[p->tx_tail]); + + DBG("transmitted packet\n"); + DBG(" size: %zd\n", iob_len(p->tx_iobuf[p->tx_tail])); + + p->tx_tail = (p->tx_tail + 1) % TX_RING_SIZE; + p->tx_cnt--; + } +} + +static void a3c90x_free_tx_ring(struct INF_3C90X *p) +{ + DBGP("a3c90x_free_tx_ring\n"); + + free_dma(p->tx_ring, TX_RING_SIZE * sizeof(struct TXD)); + p->tx_ring = NULL; + /* io_buffers are free()ed by netdev_tx_complete[,_err]() */ +} + +/** + * a3c90x_transmit - Transmits a packet. + * + * @v netdev Network device info + * @v iob io_buffer containing the data to be send + * + * @ret Returns 0 on success, negative on failure + */ +static int a3c90x_transmit(struct net_device *netdev, + struct io_buffer *iob) +{ + struct INF_3C90X *inf_3c90x = netdev_priv(netdev); + struct TXD *tx_cur_desc; + struct TXD *tx_prev_desc; + + unsigned int len; + unsigned int downlist_ptr; + + DBGP("a3c90x_transmit\n"); + + if (inf_3c90x->tx_cnt == TX_RING_SIZE) { + DBG("TX-Ring overflow\n"); + return -ENOBUFS; + } + + inf_3c90x->tx_iobuf[inf_3c90x->tx_cur] = iob; + tx_cur_desc = inf_3c90x->tx_ring + inf_3c90x->tx_cur; + + tx_prev_desc = inf_3c90x->tx_ring + + (((inf_3c90x->tx_cur + TX_RING_SIZE) - 1) % TX_RING_SIZE); + + len = iob_len(iob); + + /* Setup the DPD (download descriptor) */ + tx_cur_desc->DnNextPtr = 0; + + /* FrameStartHeader differs in 90x and >= 90xB + * It contains length in 90x and a round up boundary and packet ID for + * 90xB and 90xC. We can leave this to 0 for 90xB and 90xC. + */ + tx_cur_desc->FrameStartHeader = + fshTxIndicate | (inf_3c90x->isBrev ? 0x00 : len); + + tx_cur_desc->DataAddr = virt_to_bus(iob->data); + tx_cur_desc->DataLength = len | downLastFrag; + + /* We have to stall the download engine, so the NIC won't access the + * tx descriptor while we modify it. There is a way around this + * from revision B and upwards. To stay compatible with older revisions + * we don't use it here. + */ + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, cmdStallCtl, + dnStall); + + tx_prev_desc->DnNextPtr = virt_to_bus(tx_cur_desc); + + downlist_ptr = inl(inf_3c90x->IOAddr + regDnListPtr_l); + if (downlist_ptr == 0) { + /* currently no DownList, sending a new one */ + outl(virt_to_bus(tx_cur_desc), + inf_3c90x->IOAddr + regDnListPtr_l); + } + + /* End Stall */ + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, cmdStallCtl, + dnUnStall); + + inf_3c90x->tx_cur = (inf_3c90x->tx_cur + 1) % TX_RING_SIZE; + inf_3c90x->tx_cnt++; + + return 0; +} + +/** + * a3c90x_prepare_rx_desc - fills the rx desc with initial data + * + * @v p NIC private data + * @v index Index for rx_iobuf and rx_ring array + */ + +static void a3c90x_prepare_rx_desc(struct INF_3C90X *p, unsigned int index) +{ + DBGP("a3c90x_prepare_rx_desc\n"); + DBG("Populating rx_desc %d\n", index); + + /* We have to stall the upload engine, so the NIC won't access the + * rx descriptor while we modify it. There is a way around this + * from revision B and upwards. To stay compatible with older revisions + * we don't use it here. + */ + a3c90x_internal_IssueCommand(p->IOAddr, cmdStallCtl, upStall); + + p->rx_ring[index].DataAddr = virt_to_bus(p->rx_iobuf[index]->data); + p->rx_ring[index].DataLength = RX_BUF_SIZE | upLastFrag; + p->rx_ring[index].UpPktStatus = 0; + + /* unstall upload engine */ + a3c90x_internal_IssueCommand(p->IOAddr, cmdStallCtl, upUnStall); +} + +/** + * a3c90x_refill_rx_ring -checks every entry in the rx ring and reallocates + * them as necessary. Then it calls a3c90x_prepare_rx_desc to fill the rx desc + * with initial data. + * + * @v p NIC private data + */ +static void a3c90x_refill_rx_ring(struct INF_3C90X *p) +{ + int i; + unsigned int status; + struct RXD *rx_cur_desc; + + DBGP("a3c90x_refill_rx_ring\n"); + + for (i = 0; i < RX_RING_SIZE; i++) { + rx_cur_desc = p->rx_ring + i; + status = rx_cur_desc->UpPktStatus; + + /* only refill used descriptor */ + if (!(status & upComplete)) + continue; + + /* we still need to process this descriptor */ + if (p->rx_iobuf[i] != NULL) + continue; + + p->rx_iobuf[i] = alloc_iob(RX_BUF_SIZE); + if (p->rx_iobuf[i] == NULL) { + DBG("alloc_iob() failed\n"); + break; + } + + a3c90x_prepare_rx_desc(p, i); + } +} + +/** + * a3c90x_setup_rx_ring - Allocates RX ring, initialize rx_desc values + * + * @v p Private NIC data + * + * @ret Returns 0 on success, negative on failure + */ +static int a3c90x_setup_rx_ring(struct INF_3C90X *p) +{ + int i; + + DBGP("a3c90x_setup_rx_ring\n"); + + p->rx_ring = + malloc_dma(RX_RING_SIZE * sizeof(struct RXD), RX_RING_ALIGN); + + if (!p->rx_ring) { + DBG("Could not allocate RX-ring\n"); + return -ENOMEM; + } + + p->rx_cur = 0; + + for (i = 0; i < RX_RING_SIZE; i++) { + p->rx_ring[i].UpNextPtr = + virt_to_bus(p->rx_ring + (i + 1)); + + /* these are needed so refill_rx_ring initializes the ring */ + p->rx_ring[i].UpPktStatus = upComplete; + p->rx_iobuf[i] = NULL; + } + + /* Loop the ring */ + p->rx_ring[i - 1].UpNextPtr = virt_to_bus(p->rx_ring); + + a3c90x_refill_rx_ring(p); + + return 0; +} + +static void a3c90x_free_rx_ring(struct INF_3C90X *p) +{ + DBGP("a3c90x_free_rx_ring\n"); + + free_dma(p->rx_ring, RX_RING_SIZE * sizeof(struct RXD)); + p->rx_ring = NULL; +} + +static void a3c90x_free_rx_iobuf(struct INF_3C90X *p) +{ + int i; + + DBGP("a3c90x_free_rx_iobuf\n"); + + for (i = 0; i < RX_RING_SIZE; i++) { + free_iob(p->rx_iobuf[i]); + p->rx_iobuf[i] = NULL; + } +} + +/** + * a3c90x_process_rx_packets - Checks for received packets, + * reports them to gPXE with netdev_rx() or netdev_rx_err() if there was an + * error while receiving the packet + * + * @v netdev Network device info + */ +static void a3c90x_process_rx_packets(struct net_device *netdev) +{ + int i; + unsigned int rx_status; + struct INF_3C90X *p = netdev_priv(netdev); + struct RXD *rx_cur_desc; + + DBGP("a3c90x_process_rx_packets\n"); + + for (i = 0; i < RX_RING_SIZE; i++) { + rx_cur_desc = p->rx_ring + p->rx_cur; + rx_status = rx_cur_desc->UpPktStatus; + + if (!(rx_status & upComplete) && !(rx_status & upError)) + break; + + if (p->rx_iobuf[p->rx_cur] == NULL) + break; + + if (rx_status & upError) { + DBG("Corrupted packet received\n"); + netdev_rx_err(netdev, p->rx_iobuf[p->rx_cur], + -EINVAL); + } else { + /* if we're here, we've got good packet */ + int packet_len; + + packet_len = rx_status & 0x1FFF; + iob_put(p->rx_iobuf[p->rx_cur], packet_len); + + DBG("received packet\n"); + DBG(" size: %d\n", packet_len); + + netdev_rx(netdev, p->rx_iobuf[p->rx_cur]); + } + + p->rx_iobuf[p->rx_cur] = NULL; /* invalidate rx desc */ + p->rx_cur = (p->rx_cur + 1) % RX_RING_SIZE; + } + a3c90x_refill_rx_ring(p); + +} + +/** + * a3c90x_poll - Routine that gets called periodically. + * Here we hanle transmitted and received packets. + * We could also check the link status from time to time, which we + * currently don't do. + * + * @v netdev Network device info + */ +static void a3c90x_poll(struct net_device *netdev) +{ + struct INF_3C90X *p = netdev_priv(netdev); + uint16_t raw_status, int_status; + + DBGP("a3c90x_poll\n"); + + raw_status = inw(p->IOAddr + regCommandIntStatus_w); + int_status = (raw_status & 0x0FFF); + + if ( int_status == 0 ) + return; + + a3c90x_internal_IssueCommand(p->IOAddr, cmdAcknowledgeInterrupt, + int_status); + + if (int_status & INT_TXCOMPLETE) + outb(0x00, p->IOAddr + regTxStatus_b); + + DBG("poll: status = %#04x\n", raw_status); + + a3c90x_process_tx_packets(netdev); + + a3c90x_process_rx_packets(netdev); +} + + + +static void a3c90x_free_resources(struct INF_3C90X *p) +{ + DBGP("a3c90x_free_resources\n"); + + a3c90x_free_tx_ring(p); + a3c90x_free_rx_ring(p); + a3c90x_free_rx_iobuf(p); +} + +/** + * a3c90x_remove - Routine to remove the card. Unregisters + * the NIC from gPXE, disables RX/TX and resets the card. + * + * @v pci PCI device info + */ +static void a3c90x_remove(struct pci_device *pci) +{ + struct net_device *netdev = pci_get_drvdata(pci); + struct INF_3C90X *inf_3c90x = netdev_priv(netdev); + + DBGP("a3c90x_remove\n"); + + a3c90x_reset(inf_3c90x); + + /* Disable the receiver and transmitter. */ + outw(cmdRxDisable, inf_3c90x->IOAddr + regCommandIntStatus_w); + outw(cmdTxDisable, inf_3c90x->IOAddr + regCommandIntStatus_w); + + unregister_netdev(netdev); + netdev_nullify(netdev); + netdev_put(netdev); +} + +static void a3c90x_irq(struct net_device *netdev, int enable) +{ + struct INF_3C90X *p = netdev_priv(netdev); + + DBGP("a3c90x_irq\n"); + + if (enable == 0) { + /* disable interrupts */ + a3c90x_internal_IssueCommand(p->IOAddr, + cmdSetInterruptEnable, 0); + } else { + a3c90x_internal_IssueCommand(p->IOAddr, + cmdSetInterruptEnable, + INT_TXCOMPLETE | + INT_UPCOMPLETE); + a3c90x_internal_IssueCommand(p->IOAddr, + cmdAcknowledgeInterrupt, + 0x661); + } +} + +/** + * a3c90x_hw_start - Initialize hardware, copy MAC address + * to NIC registers, set default receiver + */ +static void a3c90x_hw_start(struct net_device *netdev) +{ + int i, c; + unsigned int cfg; + unsigned int mopt; + unsigned short linktype; + struct INF_3C90X *inf_3c90x = netdev_priv(netdev); + + DBGP("a3c90x_hw_start\n"); + + /* 3C556: Invert MII power */ + if (inf_3c90x->is3c556) { + unsigned int tmp; + a3c90x_internal_SetWindow(inf_3c90x, winAddressing2); + tmp = inw(inf_3c90x->IOAddr + regResetOptions_2_w); + tmp |= 0x4000; + outw(tmp, inf_3c90x->IOAddr + regResetOptions_2_w); + } + + /* Copy MAC address into the NIC registers */ + a3c90x_internal_SetWindow(inf_3c90x, winAddressing2); + for (i = 0; i < ETH_ALEN; i++) + outb(netdev->ll_addr[i], + inf_3c90x->IOAddr + regStationAddress_2_3w + i); + for (i = 0; i < ETH_ALEN; i++) + outb(0, inf_3c90x->IOAddr + regStationMask_2_3w + i); + + /* Read the media options register, print a message and set default + * xcvr. + * + * Uses Media Option command on B revision, Reset Option on non-B + * revision cards -- same register address + */ + a3c90x_internal_SetWindow(inf_3c90x, winTxRxOptions3); + mopt = inw(inf_3c90x->IOAddr + regResetMediaOptions_3_w); + + /* mask out VCO bit that is defined as 10baseFL bit on B-rev cards */ + if (!inf_3c90x->isBrev) { + mopt &= 0x7F; + } + + DBG("Connectors present: "); + c = 0; + linktype = 0x0008; + if (mopt & 0x01) { + DBG("%s100Base-T4", (c++) ? ", " : ""); + linktype = linkMII; + } + if (mopt & 0x04) { + DBG("%s100Base-FX", (c++) ? ", " : ""); + linktype = link100BaseFX; + } + if (mopt & 0x10) { + DBG("%s10Base-2", (c++) ? ", " : ""); + linktype = link10Base2; + } + if (mopt & 0x20) { + DBG("%sAUI", (c++) ? ", " : ""); + linktype = linkAUI; + } + if (mopt & 0x40) { + DBG("%sMII", (c++) ? ", " : ""); + linktype = linkMII; + } + if ((mopt & 0xA) == 0xA) { + DBG("%s10Base-T / 100Base-TX", (c++) ? ", " : ""); + linktype = linkAutoneg; + } else if ((mopt & 0xA) == 0x2) { + DBG("%s100Base-TX", (c++) ? ", " : ""); + linktype = linkAutoneg; + } else if ((mopt & 0xA) == 0x8) { + DBG("%s10Base-T", (c++) ? ", " : ""); + linktype = linkAutoneg; + } + DBG(".\n"); + + /* Determine transceiver type to use, depending on value stored in + * eeprom 0x16 + */ + if (inf_3c90x->isBrev) { + if ((inf_3c90x->eeprom[0x16] & 0xFF00) == XCVR_MAGIC) { + /* User-defined */ + linktype = inf_3c90x->eeprom[0x16] & 0x000F; + } + } else { + /* I don't know what MII MAC only mode is!!! */ + if (linktype == linkExternalMII) { + if (inf_3c90x->isBrev) + DBG("WARNING: MII External MAC Mode only supported on B-revision " "cards!!!!\nFalling Back to MII Mode\n"); + linktype = linkMII; + } + } + + /* enable DC converter for 10-Base-T */ + if (linktype == link10Base2) { + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, + cmdEnableDcConverter, 0); + } + + /* Set the link to the type we just determined. */ + a3c90x_internal_SetWindow(inf_3c90x, winTxRxOptions3); + cfg = inl(inf_3c90x->IOAddr + regInternalConfig_3_l); + cfg &= ~(0xF << 20); + cfg |= (linktype << 20); + + DBG("Setting internal cfg register: 0x%08X (linktype: 0x%02X)\n", + cfg, linktype); + + outl(cfg, inf_3c90x->IOAddr + regInternalConfig_3_l); + + /* Now that we set the xcvr type, reset the Tx and Rx */ + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, cmdTxReset, 0x00); + + if (!inf_3c90x->isBrev) + outb(0x01, inf_3c90x->IOAddr + regTxFreeThresh_b); + + /* Set the RX filter = receive only individual pkts & multicast & bcast. */ + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, cmdSetRxFilter, + 0x01 + 0x02 + 0x04); + + + /* + * set Indication and Interrupt flags , acknowledge any IRQ's + */ + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, + cmdSetInterruptEnable, + INT_TXCOMPLETE | INT_UPCOMPLETE); + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, + cmdSetIndicationEnable, + INT_TXCOMPLETE | INT_UPCOMPLETE); + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, + cmdAcknowledgeInterrupt, 0x661); +} + +/** + * a3c90x_open - Routine to initialize the card. Initialize hardware, + * allocate TX and RX ring, send RX ring address to the NIC. + * + * @v netdev Network device info + * + * @ret Returns 0 on success, negative on failure + */ +static int a3c90x_open(struct net_device *netdev) +{ + int rc; + struct INF_3C90X *inf_3c90x = netdev_priv(netdev); + + DBGP("a3c90x_open\n"); + + a3c90x_hw_start(netdev); + + rc = a3c90x_setup_tx_ring(inf_3c90x); + if (rc != 0) { + DBG("Error setting up TX Ring\n"); + goto error; + } + + rc = a3c90x_setup_rx_ring(inf_3c90x); + if (rc != 0) { + DBG("Error setting up RX Ring\n"); + goto error; + } + + /* send rx_ring address to NIC */ + outl(virt_to_bus(inf_3c90x->rx_ring), + inf_3c90x->IOAddr + regUpListPtr_l); + + /* enable packet transmission and reception */ + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, cmdTxEnable, 0); + a3c90x_internal_IssueCommand(inf_3c90x->IOAddr, cmdRxEnable, 0); + + return 0; + + error: + a3c90x_free_resources(inf_3c90x); + a3c90x_reset(inf_3c90x); + return rc; +} + +/** + * a3c90x_close - free()s TX and RX ring, disablex RX/TX, resets NIC + * + * @v netdev Network device info + */ +static void a3c90x_close(struct net_device *netdev) +{ + struct INF_3C90X *inf_3c90x = netdev_priv(netdev); + + DBGP("a3c90x_close\n"); + + a3c90x_reset(inf_3c90x); + outw(cmdRxDisable, inf_3c90x->IOAddr + regCommandIntStatus_w); + outw(cmdTxDisable, inf_3c90x->IOAddr + regCommandIntStatus_w); + a3c90x_free_resources(inf_3c90x); +} + +static struct net_device_operations a3c90x_operations = { + .open = a3c90x_open, + .close = a3c90x_close, + .poll = a3c90x_poll, + .transmit = a3c90x_transmit, + .irq = a3c90x_irq, +}; + +/** + * a3c90x_probe: exported routine to probe for the 3c905 card. + * If this routine is called, the pci functions did find the + * card. We read the eeprom here and get the MAC address. + * Initialization is done in a3c90x_open(). + * + * @v pci PCI device info + * @ pci_id PCI device IDs + * + * @ret rc Returns 0 on success, negative on failure + */ +static int a3c90x_probe(struct pci_device *pci, + const struct pci_device_id *pci_id __unused) +{ + + struct net_device *netdev; + struct INF_3C90X *inf_3c90x; + unsigned char *HWAddr; + int rc; + + DBGP("a3c90x_probe\n"); + + if (pci->ioaddr == 0) + return -EINVAL; + + netdev = alloc_etherdev(sizeof(*inf_3c90x)); + if (!netdev) + return -ENOMEM; + + netdev_init(netdev, &a3c90x_operations); + pci_set_drvdata(pci, netdev); + netdev->dev = &pci->dev; + + inf_3c90x = netdev_priv(netdev); + memset(inf_3c90x, 0, sizeof(*inf_3c90x)); + + adjust_pci_device(pci); + + inf_3c90x->is3c556 = (pci->device == 0x6055); + inf_3c90x->IOAddr = pci->ioaddr; + inf_3c90x->CurrentWindow = winNone; + + inf_3c90x->isBrev = 1; + switch (pci->device) { + case 0x9000: /* 10 Base TPO */ + case 0x9001: /* 10/100 T4 */ + case 0x9050: /* 10/100 TPO */ + case 0x9051: /* 10 Base Combo */ + inf_3c90x->isBrev = 0; + break; + } + + DBG("[3c90x]: found NIC(0x%04X, 0x%04X), isBrev=%d, is3c556=%d\n", + pci->vendor, pci->device, inf_3c90x->isBrev, + inf_3c90x->is3c556); + + /* initialize nvs device */ + inf_3c90x->nvs.word_len_log2 = 1; /* word */ + inf_3c90x->nvs.size = (inf_3c90x->isBrev ? 0x20 : 0x17); + inf_3c90x->nvs.block_size = 1; + inf_3c90x->nvs.read = a3c90x_internal_ReadEeprom; + inf_3c90x->nvs.write = a3c90x_internal_WriteEeprom; + + /* reset NIC before accessing any data from it */ + a3c90x_reset(inf_3c90x); + + /* load eeprom contents to inf_3c90x->eeprom */ + a3c90x_internal_ReadEepromContents(inf_3c90x); + + HWAddr = netdev->hw_addr; + + /* Retrieve the Hardware address */ + HWAddr[0] = inf_3c90x->eeprom[eepromHwAddrOffset + 0] >> 8; + HWAddr[1] = inf_3c90x->eeprom[eepromHwAddrOffset + 0] & 0xFF; + HWAddr[2] = inf_3c90x->eeprom[eepromHwAddrOffset + 1] >> 8; + HWAddr[3] = inf_3c90x->eeprom[eepromHwAddrOffset + 1] & 0xFF; + HWAddr[4] = inf_3c90x->eeprom[eepromHwAddrOffset + 2] >> 8; + HWAddr[5] = inf_3c90x->eeprom[eepromHwAddrOffset + 2] & 0xFF; + + /* we don't handle linkstates yet, so we're always up */ + netdev_link_up(netdev); + + if ((rc = register_netdev(netdev)) != 0) { + DBG("3c90x: register_netdev() failed\n"); + netdev_put(netdev); + return rc; + } + + return 0; +} + +static struct pci_device_id a3c90x_nics[] = { +/* Original 90x revisions: */ + PCI_ROM(0x10b7, 0x6055, "3c556", "3C556", 0), /* Huricane */ + PCI_ROM(0x10b7, 0x9000, "3c905-tpo", "3Com900-TPO", 0), /* 10 Base TPO */ + PCI_ROM(0x10b7, 0x9001, "3c905-t4", "3Com900-Combo", 0), /* 10/100 T4 */ + PCI_ROM(0x10b7, 0x9050, "3c905-tpo100", "3Com905-TX", 0), /* 100 Base TX / 10/100 TPO */ + PCI_ROM(0x10b7, 0x9051, "3c905-combo", "3Com905-T4", 0), /* 100 Base T4 / 10 Base Combo */ +/* Newer 90xB revisions: */ + PCI_ROM(0x10b7, 0x9004, "3c905b-tpo", "3Com900B-TPO", 0), /* 10 Base TPO */ + PCI_ROM(0x10b7, 0x9005, "3c905b-combo", "3Com900B-Combo", 0), /* 10 Base Combo */ + PCI_ROM(0x10b7, 0x9006, "3c905b-tpb2", "3Com900B-2/T", 0), /* 10 Base TP and Base2 */ + PCI_ROM(0x10b7, 0x900a, "3c905b-fl", "3Com900B-FL", 0), /* 10 Base FL */ + PCI_ROM(0x10b7, 0x9055, "3c905b-tpo100", "3Com905B-TX", 0), /* 10/100 TPO */ + PCI_ROM(0x10b7, 0x9056, "3c905b-t4", "3Com905B-T4", 0), /* 10/100 T4 */ + PCI_ROM(0x10b7, 0x9058, "3c905b-9058", "3Com905B-9058", 0), /* Cyclone 10/100/BNC */ + PCI_ROM(0x10b7, 0x905a, "3c905b-fx", "3Com905B-FL", 0), /* 100 Base FX / 10 Base FX */ +/* Newer 90xC revision: */ + PCI_ROM(0x10b7, 0x9200, "3c905c-tpo", "3Com905C-TXM", 0), /* 10/100 TPO (3C905C-TXM) */ + PCI_ROM(0x10b7, 0x9202, "3c920b-emb-ati", "3c920B-EMB-WNM (ATI Radeon 9100 IGP)", 0), /* 3c920B-EMB-WNM (ATI Radeon 9100 IGP) */ + PCI_ROM(0x10b7, 0x9210, "3c920b-emb-wnm", "3Com20B-EMB WNM", 0), + PCI_ROM(0x10b7, 0x9800, "3c980", "3Com980-Cyclone", 0), /* Cyclone */ + PCI_ROM(0x10b7, 0x9805, "3c9805", "3Com9805", 0), /* Dual Port Server Cyclone */ + PCI_ROM(0x10b7, 0x7646, "3csoho100-tx", "3CSOHO100-TX", 0), /* Hurricane */ + PCI_ROM(0x10b7, 0x4500, "3c450", "3Com450 HomePNA Tornado", 0), + PCI_ROM(0x10b7, 0x1201, "3c982a", "3Com982A", 0), + PCI_ROM(0x10b7, 0x1202, "3c982b", "3Com982B", 0), +}; + +struct pci_driver a3c90x_driver __pci_driver = { + .ids = a3c90x_nics, + .id_count = (sizeof(a3c90x_nics) / sizeof(a3c90x_nics[0])), + .probe = a3c90x_probe, + .remove = a3c90x_remove, +}; + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/3c90x.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c90x.h new file mode 100644 index 0000000..acbb29d --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/3c90x.h @@ -0,0 +1,302 @@ +/* + * 3c90x.c -- This file implements the 3c90x driver for etherboot. Written + * by Greg Beeley, Greg.Beeley@LightSys.org. Modified by Steve Smith, + * Steve.Smith@Juno.Com. Alignment bug fix Neil Newell (nn@icenoir.net). + * + * Port from etherboot to gPXE API, implementation of tx/rx ring support + * by Thomas Miletich, thomas.miletich@gmail.com + * Thanks to Marty Connor and Stefan Hajnoczi for their help and feedback. + * + * This program Copyright (C) 1999 LightSys Technology Services, Inc. + * Portions Copyright (C) 1999 Steve Smith + * + * This program may be re-distributed in source or binary form, modified, + * sold, or copied for any purpose, provided that the above copyright message + * and this text are included with all source copies or derivative works, and + * provided that the above copyright message and this text are included in the + * documentation of any binary-only distributions. This program is distributed + * WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR + * PURPOSE or MERCHANTABILITY. Please read the associated documentation + * "3c90x.txt" before compiling and using this driver. + * + * -------- + * + * Program written with the assistance of the 3com documentation for + * the 3c905B-TX card, as well as with some assistance from the 3c59x + * driver Donald Becker wrote for the Linux kernel, and with some assistance + * from the remainder of the Etherboot distribution. + * + * REVISION HISTORY: + * + * v0.10 1-26-1998 GRB Initial implementation. + * v0.90 1-27-1998 GRB System works. + * v1.00pre1 2-11-1998 GRB Got prom boot issue fixed. + * v2.0 9-24-1999 SCS Modified for 3c905 (from 3c905b code) + * Re-wrote poll and transmit for + * better error recovery and heavy + * network traffic operation + * v2.01 5-26-2003 NN Fixed driver alignment issue which + * caused system lockups if driver structures + * not 8-byte aligned. + * v2.02 11-28-2007 GSt Got polling working again by replacing + * "for(i=0;i<40000;i++);" with "mdelay(1);" + * + * + * indent options: indent -kr -i8 3c90x.c + */ + +FILE_LICENCE ( BSD2 ); + +#ifndef __3C90X_H_ +#define __3C90X_H_ + +static struct net_device_operations a3c90x_operations; + +#define XCVR_MAGIC (0x5A00) + +/* Register definitions for the 3c905 */ +enum Registers { + regPowerMgmtCtrl_w = 0x7c, /* 905B Revision Only */ + regUpMaxBurst_w = 0x7a, /* 905B Revision Only */ + regDnMaxBurst_w = 0x78, /* 905B Revision Only */ + regDebugControl_w = 0x74, /* 905B Revision Only */ + regDebugData_l = 0x70, /* 905B Revision Only */ + regRealTimeCnt_l = 0x40, /* Universal */ + regUpBurstThresh_b = 0x3e, /* 905B Revision Only */ + regUpPoll_b = 0x3d, /* 905B Revision Only */ + regUpPriorityThresh_b = 0x3c, /* 905B Revision Only */ + regUpListPtr_l = 0x38, /* Universal */ + regCountdown_w = 0x36, /* Universal */ + regFreeTimer_w = 0x34, /* Universal */ + regUpPktStatus_l = 0x30, /* Universal with Exception, pg 130 */ + regTxFreeThresh_b = 0x2f, /* 90X Revision Only */ + regDnPoll_b = 0x2d, /* 905B Revision Only */ + regDnPriorityThresh_b = 0x2c, /* 905B Revision Only */ + regDnBurstThresh_b = 0x2a, /* 905B Revision Only */ + regDnListPtr_l = 0x24, /* Universal with Exception, pg 107 */ + regDmaCtrl_l = 0x20, /* Universal with Exception, pg 106 */ + /* */ + regIntStatusAuto_w = 0x1e, /* 905B Revision Only */ + regTxStatus_b = 0x1b, /* Universal with Exception, pg 113 */ + regTimer_b = 0x1a, /* Universal */ + regTxPktId_b = 0x18, /* 905B Revision Only */ + regCommandIntStatus_w = 0x0e, /* Universal (Command Variations) */ +}; + +/* following are windowed registers */ +enum Registers7 { + regPowerMgmtEvent_7_w = 0x0c, /* 905B Revision Only */ + regVlanEtherType_7_w = 0x04, /* 905B Revision Only */ + regVlanMask_7_w = 0x00, /* 905B Revision Only */ +}; + +enum Registers6 { + regBytesXmittedOk_6_w = 0x0c, /* Universal */ + regBytesRcvdOk_6_w = 0x0a, /* Universal */ + regUpperFramesOk_6_b = 0x09, /* Universal */ + regFramesDeferred_6_b = 0x08, /* Universal */ + regFramesRecdOk_6_b = 0x07, /* Universal with Exceptions, pg 142 */ + regFramesXmittedOk_6_b = 0x06, /* Universal */ + regRxOverruns_6_b = 0x05, /* Universal */ + regLateCollisions_6_b = 0x04, /* Universal */ + regSingleCollisions_6_b = 0x03, /* Universal */ + regMultipleCollisions_6_b = 0x02, /* Universal */ + regSqeErrors_6_b = 0x01, /* Universal */ + regCarrierLost_6_b = 0x00, /* Universal */ +}; + +enum Registers5 { + regIndicationEnable_5_w = 0x0c, /* Universal */ + regInterruptEnable_5_w = 0x0a, /* Universal */ + regTxReclaimThresh_5_b = 0x09, /* 905B Revision Only */ + regRxFilter_5_b = 0x08, /* Universal */ + regRxEarlyThresh_5_w = 0x06, /* Universal */ + regTxStartThresh_5_w = 0x00, /* Universal */ +}; + +enum Registers4 { + regUpperBytesOk_4_b = 0x0d, /* Universal */ + regBadSSD_4_b = 0x0c, /* Universal */ + regMediaStatus_4_w = 0x0a, /* Universal with Exceptions, pg 201 */ + regPhysicalMgmt_4_w = 0x08, /* Universal */ + regNetworkDiagnostic_4_w = 0x06, /* Universal with Exceptions, pg 203 */ + regFifoDiagnostic_4_w = 0x04, /* Universal with Exceptions, pg 196 */ + regVcoDiagnostic_4_w = 0x02, /* Undocumented? */ +}; + +enum Registers3 { + regTxFree_3_w = 0x0c, /* Universal */ + regRxFree_3_w = 0x0a, /* Universal with Exceptions, pg 125 */ + regResetMediaOptions_3_w = 0x08, /* Media Options on B Revision, */ + /* Reset Options on Non-B Revision */ + regMacControl_3_w = 0x06, /* Universal with Exceptions, pg 199 */ + regMaxPktSize_3_w = 0x04, /* 905B Revision Only */ + regInternalConfig_3_l = 0x00, /* Universal, different bit */ + /* definitions, pg 59 */ +}; + +enum Registers2 { + regResetOptions_2_w = 0x0c, /* 905B Revision Only */ + regStationMask_2_3w = 0x06, /* Universal with Exceptions, pg 127 */ + regStationAddress_2_3w = 0x00, /* Universal with Exceptions, pg 127 */ +}; + +enum Registers1 { + regRxStatus_1_w = 0x0a, /* 90X Revision Only, Pg 126 */ +}; + +enum Registers0 { + regEepromData_0_w = 0x0c, /* Universal */ + regEepromCommand_0_w = 0x0a, /* Universal */ + regBiosRomData_0_b = 0x08, /* 905B Revision Only */ + regBiosRomAddr_0_l = 0x04, /* 905B Revision Only */ +}; + + +/* The names for the eight register windows */ +enum Windows { + winNone = 0xff, + winPowerVlan7 = 0x07, + winStatistics6 = 0x06, + winTxRxControl5 = 0x05, + winDiagnostics4 = 0x04, + winTxRxOptions3 = 0x03, + winAddressing2 = 0x02, + winUnused1 = 0x01, + winEepromBios0 = 0x00, +}; + + +/* Command definitions for the 3c90X */ +enum Commands { + cmdGlobalReset = 0x00, /* Universal with Exceptions, pg 151 */ + cmdSelectRegisterWindow = 0x01, /* Universal */ + cmdEnableDcConverter = 0x02, /* */ + cmdRxDisable = 0x03, /* */ + cmdRxEnable = 0x04, /* Universal */ + cmdRxReset = 0x05, /* Universal */ + cmdStallCtl = 0x06, /* Universal */ + cmdTxEnable = 0x09, /* Universal */ + cmdTxDisable = 0x0A, /* */ + cmdTxReset = 0x0B, /* Universal */ + cmdRequestInterrupt = 0x0C, /* */ + cmdAcknowledgeInterrupt = 0x0D, /* Universal */ + cmdSetInterruptEnable = 0x0E, /* Universal */ + cmdSetIndicationEnable = 0x0F, /* Universal */ + cmdSetRxFilter = 0x10, /* Universal */ + cmdSetRxEarlyThresh = 0x11, /* */ + cmdSetTxStartThresh = 0x13, /* */ + cmdStatisticsEnable = 0x15, /* */ + cmdStatisticsDisable = 0x16, /* */ + cmdDisableDcConverter = 0x17, /* */ + cmdSetTxReclaimThresh = 0x18, /* */ + cmdSetHashFilterBit = 0x19, /* */ +}; + +enum FrameStartHeader { + fshTxIndicate = 0x8000, + fshDnComplete = 0x10000, +}; + +enum UpDownDesc { + upLastFrag = (1 << 31), + downLastFrag = (1 << 31), +}; + +enum UpPktStatus { + upComplete = (1 << 15), + upError = (1 << 14), +}; + +enum Stalls { + upStall = 0x00, + upUnStall = 0x01, + + dnStall = 0x02, + dnUnStall = 0x03, +}; + +enum Resources { + resRxRing = 0x00, + resTxRing = 0x02, + resRxIOBuf = 0x04 +}; + +enum eeprom { + eepromBusy = (1 << 15), + eepromRead = ((0x02) << 6), + eepromRead_556 = 0x230, + eepromHwAddrOffset = 0x0a, +}; + +/* Bit 4 is only used in revison B and upwards */ +enum linktype { + link10BaseT = 0x00, + linkAUI = 0x01, + link10Base2 = 0x03, + link100BaseFX = 0x05, + linkMII = 0x06, + linkAutoneg = 0x08, + linkExternalMII = 0x09, +}; + +/* Values for int status register bitmask */ +#define INT_INTERRUPTLATCH (1<<0) +#define INT_HOSTERROR (1<<1) +#define INT_TXCOMPLETE (1<<2) +#define INT_RXCOMPLETE (1<<4) +#define INT_RXEARLY (1<<5) +#define INT_INTREQUESTED (1<<6) +#define INT_UPDATESTATS (1<<7) +#define INT_LINKEVENT (1<<8) +#define INT_DNCOMPLETE (1<<9) +#define INT_UPCOMPLETE (1<<10) +#define INT_CMDINPROGRESS (1<<12) +#define INT_WINDOWNUMBER (7<<13) + +/* Buffer sizes */ +#define TX_RING_SIZE 8 +#define RX_RING_SIZE 8 +#define TX_RING_ALIGN 16 +#define RX_RING_ALIGN 16 +#define RX_BUF_SIZE 1536 + +/* Timeouts for eeprom and command completion */ +/* Timeout 1 second, to be save */ +#define EEPROM_TIMEOUT 1 * 1000 * 1000 + +/* TX descriptor */ +struct TXD { + volatile unsigned int DnNextPtr; + volatile unsigned int FrameStartHeader; + volatile unsigned int DataAddr; + volatile unsigned int DataLength; +} __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */ + +/* RX descriptor */ +struct RXD { + volatile unsigned int UpNextPtr; + volatile unsigned int UpPktStatus; + volatile unsigned int DataAddr; + volatile unsigned int DataLength; +} __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */ + +/* Private NIC dats */ +struct INF_3C90X { + unsigned int is3c556; + unsigned char isBrev; + unsigned char CurrentWindow; + unsigned int IOAddr; + unsigned short eeprom[0x21]; + unsigned int tx_cur; /* current entry in tx_ring */ + unsigned int tx_cnt; /* current number of used tx descriptors */ + unsigned int tx_tail; /* entry of last finished packet */ + unsigned int rx_cur; + struct TXD *tx_ring; + struct RXD *rx_ring; + struct io_buffer *tx_iobuf[TX_RING_SIZE]; + struct io_buffer *rx_iobuf[RX_RING_SIZE]; + struct nvs_device nvs; +}; + +#endif diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/amd8111e.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/amd8111e.c new file mode 100644 index 0000000..1b1fdc1 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/amd8111e.c @@ -0,0 +1,693 @@ +/* Advanced Micro Devices Inc. AMD8111E Linux Network Driver + * Copyright (C) 2004 Advanced Micro Devices + * Copyright (C) 2005 Liu Tao <liutao1980@gmail.com> [etherboot port] + * + * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ] + * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c] + * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ] + * Derived from the lance driver written 1993,1994,1995 by Donald Becker. + * Copyright 1993 United States Government as represented by the + * Director, National Security Agency.[ pcnet32.c ] + * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ] + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include "etherboot.h" +#include "nic.h" +#include "mii.h" +#include <gpxe/pci.h> +#include <gpxe/ethernet.h> +#include "string.h" +#include "stdint.h" +#include "amd8111e.h" + + +/* driver definitions */ +#define NUM_TX_SLOTS 2 +#define NUM_RX_SLOTS 4 +#define TX_SLOTS_MASK 1 +#define RX_SLOTS_MASK 3 + +#define TX_BUF_LEN 1536 +#define RX_BUF_LEN 1536 + +#define TX_PKT_LEN_MAX (ETH_FRAME_LEN - ETH_HLEN) +#define RX_PKT_LEN_MIN 60 +#define RX_PKT_LEN_MAX ETH_FRAME_LEN + +#define TX_TIMEOUT 3000 +#define TX_PROCESS_TIME 10 +#define TX_RETRY (TX_TIMEOUT / TX_PROCESS_TIME) + +#define PHY_RW_RETRY 10 + + +struct amd8111e_tx_desc { + u16 buf_len; + u16 tx_flags; + u16 tag_ctrl_info; + u16 tag_ctrl_cmd; + u32 buf_phy_addr; + u32 reserved; +}; + +struct amd8111e_rx_desc { + u32 reserved; + u16 msg_len; + u16 tag_ctrl_info; + u16 buf_len; + u16 rx_flags; + u32 buf_phy_addr; +}; + +struct eth_frame { + u8 dst_addr[ETH_ALEN]; + u8 src_addr[ETH_ALEN]; + u16 type; + u8 data[ETH_FRAME_LEN - ETH_HLEN]; +} __attribute__((packed)); + +struct amd8111e_priv { + struct amd8111e_tx_desc tx_ring[NUM_TX_SLOTS]; + struct amd8111e_rx_desc rx_ring[NUM_RX_SLOTS]; + unsigned char tx_buf[NUM_TX_SLOTS][TX_BUF_LEN]; + unsigned char rx_buf[NUM_RX_SLOTS][RX_BUF_LEN]; + unsigned long tx_idx, rx_idx; + int tx_consistent; + + char opened; + char link; + char speed; + char duplex; + int ext_phy_addr; + u32 ext_phy_id; + + struct pci_device *pdev; + struct nic *nic; + void *mmio; +}; + +static struct amd8111e_priv amd8111e; + + +/******************************************************** + * locale functions * + ********************************************************/ +static void amd8111e_init_hw_default(struct amd8111e_priv *lp); +static int amd8111e_start(struct amd8111e_priv *lp); +static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val); +#if 0 +static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val); +#endif +static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp); +static void amd8111e_disable_interrupt(struct amd8111e_priv *lp); +static void amd8111e_enable_interrupt(struct amd8111e_priv *lp); +static void amd8111e_force_interrupt(struct amd8111e_priv *lp); +static int amd8111e_get_mac_address(struct amd8111e_priv *lp); +static int amd8111e_init_rx_ring(struct amd8111e_priv *lp); +static int amd8111e_init_tx_ring(struct amd8111e_priv *lp); +static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index); +static void amd8111e_wait_link(struct amd8111e_priv *lp); +static void amd8111e_poll_link(struct amd8111e_priv *lp); +static void amd8111e_restart(struct amd8111e_priv *lp); + + +/* + * This function clears necessary the device registers. + */ +static void amd8111e_init_hw_default(struct amd8111e_priv *lp) +{ + unsigned int reg_val; + void *mmio = lp->mmio; + + /* stop the chip */ + writel(RUN, mmio + CMD0); + + /* Clear RCV_RING_BASE_ADDR */ + writel(0, mmio + RCV_RING_BASE_ADDR0); + + /* Clear XMT_RING_BASE_ADDR */ + writel(0, mmio + XMT_RING_BASE_ADDR0); + writel(0, mmio + XMT_RING_BASE_ADDR1); + writel(0, mmio + XMT_RING_BASE_ADDR2); + writel(0, mmio + XMT_RING_BASE_ADDR3); + + /* Clear CMD0 */ + writel(CMD0_CLEAR, mmio + CMD0); + + /* Clear CMD2 */ + writel(CMD2_CLEAR, mmio + CMD2); + + /* Clear CMD7 */ + writel(CMD7_CLEAR, mmio + CMD7); + + /* Clear DLY_INT_A and DLY_INT_B */ + writel(0x0, mmio + DLY_INT_A); + writel(0x0, mmio + DLY_INT_B); + + /* Clear FLOW_CONTROL */ + writel(0x0, mmio + FLOW_CONTROL); + + /* Clear INT0 write 1 to clear register */ + reg_val = readl(mmio + INT0); + writel(reg_val, mmio + INT0); + + /* Clear STVAL */ + writel(0x0, mmio + STVAL); + + /* Clear INTEN0 */ + writel(INTEN0_CLEAR, mmio + INTEN0); + + /* Clear LADRF */ + writel(0x0, mmio + LADRF); + + /* Set SRAM_SIZE & SRAM_BOUNDARY registers */ + writel(0x80010, mmio + SRAM_SIZE); + + /* Clear RCV_RING0_LEN */ + writel(0x0, mmio + RCV_RING_LEN0); + + /* Clear XMT_RING0/1/2/3_LEN */ + writel(0x0, mmio + XMT_RING_LEN0); + writel(0x0, mmio + XMT_RING_LEN1); + writel(0x0, mmio + XMT_RING_LEN2); + writel(0x0, mmio + XMT_RING_LEN3); + + /* Clear XMT_RING_LIMIT */ + writel(0x0, mmio + XMT_RING_LIMIT); + + /* Clear MIB */ + writew(MIB_CLEAR, mmio + MIB_ADDR); + + /* Clear LARF */ + writel( 0, mmio + LADRF); + writel( 0, mmio + LADRF + 4); + + /* SRAM_SIZE register */ + reg_val = readl(mmio + SRAM_SIZE); + + /* Set default value to CTRL1 Register */ + writel(CTRL1_DEFAULT, mmio + CTRL1); + + /* To avoid PCI posting bug */ + readl(mmio + CMD2); +} + +/* + * This function initializes the device registers and starts the device. + */ +static int amd8111e_start(struct amd8111e_priv *lp) +{ + struct nic *nic = lp->nic; + void *mmio = lp->mmio; + int i, reg_val; + + /* stop the chip */ + writel(RUN, mmio + CMD0); + + /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */ + writew(0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0); + + /* enable the port manager and set auto negotiation always */ + writel(VAL1 | EN_PMGR, mmio + CMD3 ); + writel(XPHYANE | XPHYRST, mmio + CTRL2); + + /* set control registers */ + reg_val = readl(mmio + CTRL1); + reg_val &= ~XMTSP_MASK; + writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1); + + /* initialize tx and rx ring base addresses */ + amd8111e_init_tx_ring(lp); + amd8111e_init_rx_ring(lp); + writel(virt_to_bus(lp->tx_ring), mmio + XMT_RING_BASE_ADDR0); + writel(virt_to_bus(lp->rx_ring), mmio + RCV_RING_BASE_ADDR0); + writew(NUM_TX_SLOTS, mmio + XMT_RING_LEN0); + writew(NUM_RX_SLOTS, mmio + RCV_RING_LEN0); + + /* set default IPG to 96 */ + writew(DEFAULT_IPG, mmio + IPG); + writew(DEFAULT_IPG - IFS1_DELTA, mmio + IFS1); + + /* AutoPAD transmit, Retransmit on Underflow */ + writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2); + + /* JUMBO disabled */ + writel(JUMBO, mmio + CMD3); + + /* Setting the MAC address to the device */ + for(i = 0; i < ETH_ALEN; i++) + writeb(nic->node_addr[i], mmio + PADR + i); + + /* set RUN bit to start the chip, interrupt not enabled */ + writel(VAL2 | RDMD0 | VAL0 | RUN, mmio + CMD0); + + /* To avoid PCI posting bug */ + readl(mmio + CMD0); + return 0; +} + +/* +This function will read the PHY registers. +*/ +static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val) +{ + void *mmio = lp->mmio; + unsigned int reg_val; + unsigned int retry = PHY_RW_RETRY; + + reg_val = readl(mmio + PHY_ACCESS); + while (reg_val & PHY_CMD_ACTIVE) + reg_val = readl(mmio + PHY_ACCESS); + + writel(PHY_RD_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16), + mmio + PHY_ACCESS); + do { + reg_val = readl(mmio + PHY_ACCESS); + udelay(30); /* It takes 30 us to read/write data */ + } while (--retry && (reg_val & PHY_CMD_ACTIVE)); + + if (reg_val & PHY_RD_ERR) { + *val = 0; + return -1; + } + + *val = reg_val & 0xffff; + return 0; +} + +/* +This function will write into PHY registers. +*/ +#if 0 +static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val) +{ + void *mmio = lp->mmio; + unsigned int reg_val; + unsigned int retry = PHY_RW_RETRY; + + reg_val = readl(mmio + PHY_ACCESS); + while (reg_val & PHY_CMD_ACTIVE) + reg_val = readl(mmio + PHY_ACCESS); + + writel(PHY_WR_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16) | val, + mmio + PHY_ACCESS); + do { + reg_val = readl(mmio + PHY_ACCESS); + udelay(30); /* It takes 30 us to read/write the data */ + } while (--retry && (reg_val & PHY_CMD_ACTIVE)); + + if(reg_val & PHY_RD_ERR) + return -1; + + return 0; +} +#endif + +static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp) +{ + int i; + + lp->ext_phy_id = 0; + lp->ext_phy_addr = 1; + + for (i = 0x1e; i >= 0; i--) { + u32 id1, id2; + + if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1)) + continue; + if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2)) + continue; + lp->ext_phy_id = (id1 << 16) | id2; + lp->ext_phy_addr = i; + break; + } + + if (lp->ext_phy_id) + printf("Found MII PHY ID 0x%08x at address 0x%02x\n", + (unsigned int) lp->ext_phy_id, lp->ext_phy_addr); + else + printf("Couldn't detect MII PHY, assuming address 0x01\n"); +} + +static void amd8111e_disable_interrupt(struct amd8111e_priv *lp) +{ + void *mmio = lp->mmio; + unsigned int int0; + + writel(INTREN, mmio + CMD0); + writel(INTEN0_CLEAR, mmio + INTEN0); + int0 = readl(mmio + INT0); + writel(int0, mmio + INT0); + readl(mmio + INT0); +} + +static void amd8111e_enable_interrupt(struct amd8111e_priv *lp) +{ + void *mmio = lp->mmio; + + writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0); + writel(VAL0 | INTREN, mmio + CMD0); + readl(mmio + CMD0); +} + +static void amd8111e_force_interrupt(struct amd8111e_priv *lp) +{ + void *mmio = lp->mmio; + + writel(VAL0 | UINTCMD, mmio + CMD0); + readl(mmio + CMD0); +} + +static int amd8111e_get_mac_address(struct amd8111e_priv *lp) +{ + struct nic *nic = lp->nic; + void *mmio = lp->mmio; + int i; + + /* BIOS should have set mac address to PADR register, + * so we read PADR to get it. + */ + for (i = 0; i < ETH_ALEN; i++) + nic->node_addr[i] = readb(mmio + PADR + i); + + DBG ( "Ethernet addr: %s\n", eth_ntoa ( nic->node_addr ) ); + + return 0; +} + +static int amd8111e_init_rx_ring(struct amd8111e_priv *lp) +{ + int i; + + lp->rx_idx = 0; + + /* Initilaizing receive descriptors */ + for (i = 0; i < NUM_RX_SLOTS; i++) { + lp->rx_ring[i].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[i])); + lp->rx_ring[i].buf_len = cpu_to_le16(RX_BUF_LEN); + wmb(); + lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT); + } + + return 0; +} + +static int amd8111e_init_tx_ring(struct amd8111e_priv *lp) +{ + int i; + + lp->tx_idx = 0; + lp->tx_consistent = 1; + + /* Initializing transmit descriptors */ + for (i = 0; i < NUM_TX_SLOTS; i++) { + lp->tx_ring[i].tx_flags = 0; + lp->tx_ring[i].buf_phy_addr = 0; + lp->tx_ring[i].buf_len = 0; + } + + return 0; +} + +static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index) +{ + volatile u16 status; + int retry = TX_RETRY; + + status = le16_to_cpu(lp->tx_ring[index].tx_flags); + while (--retry && (status & OWN_BIT)) { + mdelay(TX_PROCESS_TIME); + status = le16_to_cpu(lp->tx_ring[index].tx_flags); + } + if (status & OWN_BIT) { + printf("Error: tx slot %d timeout, stat = 0x%x\n", index, status); + amd8111e_restart(lp); + return -1; + } + + return 0; +} + +static void amd8111e_wait_link(struct amd8111e_priv *lp) +{ + unsigned int status; + u32 reg_val; + + do { + /* read phy to update STAT0 register */ + amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, ®_val); + amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, ®_val); + amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, ®_val); + amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, ®_val); + status = readl(lp->mmio + STAT0); + } while (!(status & AUTONEG_COMPLETE) || !(status & LINK_STATS)); +} + +static void amd8111e_poll_link(struct amd8111e_priv *lp) +{ + unsigned int status, speed; + u32 reg_val; + + if (!lp->link) { + /* read phy to update STAT0 register */ + amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, ®_val); + amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, ®_val); + amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, ®_val); + amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, ®_val); + status = readl(lp->mmio + STAT0); + + if (status & LINK_STATS) { + lp->link = 1; + speed = (status & SPEED_MASK) >> 7; + if (speed == PHY_SPEED_100) + lp->speed = 1; + else + lp->speed = 0; + if (status & FULL_DPLX) + lp->duplex = 1; + else + lp->duplex = 0; + + printf("Link is up: %s Mbps %s duplex\n", + lp->speed ? "100" : "10", lp->duplex ? "full" : "half"); + } + } else { + status = readl(lp->mmio + STAT0); + if (!(status & LINK_STATS)) { + lp->link = 0; + printf("Link is down\n"); + } + } +} + +static void amd8111e_restart(struct amd8111e_priv *lp) +{ + printf("\nStarting nic...\n"); + amd8111e_disable_interrupt(lp); + amd8111e_init_hw_default(lp); + amd8111e_probe_ext_phy(lp); + amd8111e_get_mac_address(lp); + amd8111e_start(lp); + + printf("Waiting link up...\n"); + lp->link = 0; + amd8111e_wait_link(lp); + amd8111e_poll_link(lp); +} + + +/******************************************************** + * Interface Functions * + ********************************************************/ + +static void amd8111e_transmit(struct nic *nic, const char *dst_addr, + unsigned int type, unsigned int size, const char *packet) +{ + struct amd8111e_priv *lp = nic->priv_data; + struct eth_frame *frame; + unsigned int index; + + /* check packet size */ + if (size > TX_PKT_LEN_MAX) { + printf("amd8111e_transmit(): too large packet, drop\n"); + return; + } + + /* get tx slot */ + index = lp->tx_idx; + if (amd8111e_wait_tx_ring(lp, index)) + return; + + /* fill frame */ + frame = (struct eth_frame *)lp->tx_buf[index]; + memset(frame->data, 0, TX_PKT_LEN_MAX); + memcpy(frame->dst_addr, dst_addr, ETH_ALEN); + memcpy(frame->src_addr, nic->node_addr, ETH_ALEN); + frame->type = htons(type); + memcpy(frame->data, packet, size); + + /* start xmit */ + lp->tx_ring[index].buf_len = cpu_to_le16(ETH_HLEN + size); + lp->tx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(frame)); + wmb(); + lp->tx_ring[index].tx_flags = + cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT | ADD_FCS_BIT | LTINT_BIT); + writel(VAL1 | TDMD0, lp->mmio + CMD0); + readl(lp->mmio + CMD0); + + /* update slot pointer */ + lp->tx_idx = (lp->tx_idx + 1) & TX_SLOTS_MASK; +} + +static int amd8111e_poll(struct nic *nic, int retrieve) +{ + /* return true if there's an ethernet packet ready to read */ + /* nic->packet should contain data on return */ + /* nic->packetlen should contain length of data */ + + struct amd8111e_priv *lp = nic->priv_data; + u16 status, pkt_len; + unsigned int index, pkt_ok; + + amd8111e_poll_link(lp); + + index = lp->rx_idx; + status = le16_to_cpu(lp->rx_ring[index].rx_flags); + pkt_len = le16_to_cpu(lp->rx_ring[index].msg_len) - 4; /* remove 4bytes FCS */ + + if (status & OWN_BIT) + return 0; + + if (status & ERR_BIT) + pkt_ok = 0; + else if (!(status & STP_BIT)) + pkt_ok = 0; + else if (!(status & ENP_BIT)) + pkt_ok = 0; + else if (pkt_len < RX_PKT_LEN_MIN) + pkt_ok = 0; + else if (pkt_len > RX_PKT_LEN_MAX) + pkt_ok = 0; + else + pkt_ok = 1; + + if (pkt_ok) { + if (!retrieve) + return 1; + nic->packetlen = pkt_len; + memcpy(nic->packet, lp->rx_buf[index], nic->packetlen); + } + + lp->rx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[index])); + lp->rx_ring[index].buf_len = cpu_to_le16(RX_BUF_LEN); + wmb(); + lp->rx_ring[index].rx_flags = cpu_to_le16(OWN_BIT); + writel(VAL2 | RDMD0, lp->mmio + CMD0); + readl(lp->mmio + CMD0); + + lp->rx_idx = (lp->rx_idx + 1) & RX_SLOTS_MASK; + return pkt_ok; +} + +static void amd8111e_disable(struct nic *nic) +{ + struct amd8111e_priv *lp = nic->priv_data; + + /* disable interrupt */ + amd8111e_disable_interrupt(lp); + + /* stop chip */ + amd8111e_init_hw_default(lp); + + /* unmap mmio */ + iounmap(lp->mmio); + + /* update status */ + lp->opened = 0; +} + +static void amd8111e_irq(struct nic *nic, irq_action_t action) +{ + struct amd8111e_priv *lp = nic->priv_data; + + switch (action) { + case DISABLE: + amd8111e_disable_interrupt(lp); + break; + case ENABLE: + amd8111e_enable_interrupt(lp); + break; + case FORCE: + amd8111e_force_interrupt(lp); + break; + } +} + +static struct nic_operations amd8111e_operations = { + .connect = dummy_connect, + .poll = amd8111e_poll, + .transmit = amd8111e_transmit, + .irq = amd8111e_irq, +}; + +static int amd8111e_probe(struct nic *nic, struct pci_device *pdev) +{ + struct amd8111e_priv *lp = &amd8111e; + unsigned long mmio_start, mmio_len; + + nic->ioaddr = pdev->ioaddr; + nic->irqno = pdev->irq; + + mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_0); + mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_0); + + memset(lp, 0, sizeof(*lp)); + lp->pdev = pdev; + lp->nic = nic; + lp->mmio = ioremap(mmio_start, mmio_len); + lp->opened = 1; + adjust_pci_device(pdev); + + nic->priv_data = lp; + + amd8111e_restart(lp); + + nic->nic_op = &amd8111e_operations; + return 1; +} + +static struct pci_device_id amd8111e_nics[] = { + PCI_ROM(0x1022, 0x7462, "amd8111e", "AMD8111E", 0), +}; + +PCI_DRIVER ( amd8111e_driver, amd8111e_nics, PCI_NO_CLASS ); + +DRIVER ( "AMD8111E", nic_driver, pci_driver, amd8111e_driver, + amd8111e_probe, amd8111e_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/amd8111e.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/amd8111e.h new file mode 100644 index 0000000..a402a63 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/amd8111e.h @@ -0,0 +1,631 @@ +/* + * Advanced Micro Devices Inc. AMD8111E Linux Network Driver + * Copyright (C) 2003 Advanced Micro Devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + +Module Name: + + amd8111e.h + +Abstract: + + AMD8111 based 10/100 Ethernet Controller driver definitions. + +Environment: + + Kernel Mode + +Revision History: + 3.0.0 + Initial Revision. + 3.0.1 +*/ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#ifndef _AMD811E_H +#define _AMD811E_H + +/* Command style register access + +Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register. + +eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered. + +*/ + +/* Offset for Memory Mapped Registers. */ +/* 32 bit registers */ + +#define ASF_STAT 0x00 /* ASF status register */ +#define CHIPID 0x04 /* Chip ID regsiter */ +#define MIB_DATA 0x10 /* MIB data register */ +#define MIB_ADDR 0x14 /* MIB address register */ +#define STAT0 0x30 /* Status0 register */ +#define INT0 0x38 /* Interrupt0 register */ +#define INTEN0 0x40 /* Interrupt0 enable register*/ +#define CMD0 0x48 /* Command0 register */ +#define CMD2 0x50 /* Command2 register */ +#define CMD3 0x54 /* Command3 resiter */ +#define CMD7 0x64 /* Command7 register */ + +#define CTRL1 0x6C /* Control1 register */ +#define CTRL2 0x70 /* Control2 register */ + +#define XMT_RING_LIMIT 0x7C /* Transmit ring limit register */ + +#define AUTOPOLL0 0x88 /* Auto-poll0 register */ +#define AUTOPOLL1 0x8A /* Auto-poll1 register */ +#define AUTOPOLL2 0x8C /* Auto-poll2 register */ +#define AUTOPOLL3 0x8E /* Auto-poll3 register */ +#define AUTOPOLL4 0x90 /* Auto-poll4 register */ +#define AUTOPOLL5 0x92 /* Auto-poll5 register */ + +#define AP_VALUE 0x98 /* Auto-poll value register */ +#define DLY_INT_A 0xA8 /* Group A delayed interrupt register */ +#define DLY_INT_B 0xAC /* Group B delayed interrupt register */ + +#define FLOW_CONTROL 0xC8 /* Flow control register */ +#define PHY_ACCESS 0xD0 /* PHY access register */ + +#define STVAL 0xD8 /* Software timer value register */ + +#define XMT_RING_BASE_ADDR0 0x100 /* Transmit ring0 base addr register */ +#define XMT_RING_BASE_ADDR1 0x108 /* Transmit ring1 base addr register */ +#define XMT_RING_BASE_ADDR2 0x110 /* Transmit ring2 base addr register */ +#define XMT_RING_BASE_ADDR3 0x118 /* Transmit ring2 base addr register */ + +#define RCV_RING_BASE_ADDR0 0x120 /* Transmit ring0 base addr register */ + +#define PMAT0 0x190 /* OnNow pattern register0 */ +#define PMAT1 0x194 /* OnNow pattern register1 */ + +/* 16bit registers */ + +#define XMT_RING_LEN0 0x140 /* Transmit Ring0 length register */ +#define XMT_RING_LEN1 0x144 /* Transmit Ring1 length register */ +#define XMT_RING_LEN2 0x148 /* Transmit Ring2 length register */ +#define XMT_RING_LEN3 0x14C /* Transmit Ring3 length register */ + +#define RCV_RING_LEN0 0x150 /* Receive Ring0 length register */ + +#define SRAM_SIZE 0x178 /* SRAM size register */ +#define SRAM_BOUNDARY 0x17A /* SRAM boundary register */ + +/* 48bit register */ + +#define PADR 0x160 /* Physical address register */ + +#define IFS1 0x18C /* Inter-frame spacing Part1 register */ +#define IFS 0x18D /* Inter-frame spacing register */ +#define IPG 0x18E /* Inter-frame gap register */ +/* 64bit register */ + +#define LADRF 0x168 /* Logical address filter register */ + + +/* Register Bit Definitions */ +typedef enum { + + ASF_INIT_DONE = (1 << 1), + ASF_INIT_PRESENT = (1 << 0), + +}STAT_ASF_BITS; + +typedef enum { + + MIB_CMD_ACTIVE = (1 << 15 ), + MIB_RD_CMD = (1 << 13 ), + MIB_CLEAR = (1 << 12 ), + MIB_ADDRESS = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)| + (1 << 4) | (1 << 5), +}MIB_ADDR_BITS; + + +typedef enum { + + PMAT_DET = (1 << 12), + MP_DET = (1 << 11), + LC_DET = (1 << 10), + SPEED_MASK = (1 << 9)|(1 << 8)|(1 << 7), + FULL_DPLX = (1 << 6), + LINK_STATS = (1 << 5), + AUTONEG_COMPLETE = (1 << 4), + MIIPD = (1 << 3), + RX_SUSPENDED = (1 << 2), + TX_SUSPENDED = (1 << 1), + RUNNING = (1 << 0), + +}STAT0_BITS; + +#define PHY_SPEED_10 0x2 +#define PHY_SPEED_100 0x3 + +/* INT0 0x38, 32bit register */ +typedef enum { + + INTR = (1 << 31), + PCSINT = (1 << 28), + LCINT = (1 << 27), + APINT5 = (1 << 26), + APINT4 = (1 << 25), + APINT3 = (1 << 24), + TINT_SUM = (1 << 23), + APINT2 = (1 << 22), + APINT1 = (1 << 21), + APINT0 = (1 << 20), + MIIPDTINT = (1 << 19), + MCCINT = (1 << 17), + MREINT = (1 << 16), + RINT_SUM = (1 << 15), + SPNDINT = (1 << 14), + MPINT = (1 << 13), + SINT = (1 << 12), + TINT3 = (1 << 11), + TINT2 = (1 << 10), + TINT1 = (1 << 9), + TINT0 = (1 << 8), + UINT = (1 << 7), + STINT = (1 << 4), + RINT0 = (1 << 0), + +}INT0_BITS; + +typedef enum { + + VAL3 = (1 << 31), /* VAL bit for byte 3 */ + VAL2 = (1 << 23), /* VAL bit for byte 2 */ + VAL1 = (1 << 15), /* VAL bit for byte 1 */ + VAL0 = (1 << 7), /* VAL bit for byte 0 */ + +}VAL_BITS; + +typedef enum { + + /* VAL3 */ + LCINTEN = (1 << 27), + APINT5EN = (1 << 26), + APINT4EN = (1 << 25), + APINT3EN = (1 << 24), + /* VAL2 */ + APINT2EN = (1 << 22), + APINT1EN = (1 << 21), + APINT0EN = (1 << 20), + MIIPDTINTEN = (1 << 19), + MCCIINTEN = (1 << 18), + MCCINTEN = (1 << 17), + MREINTEN = (1 << 16), + /* VAL1 */ + SPNDINTEN = (1 << 14), + MPINTEN = (1 << 13), + TINTEN3 = (1 << 11), + SINTEN = (1 << 12), + TINTEN2 = (1 << 10), + TINTEN1 = (1 << 9), + TINTEN0 = (1 << 8), + /* VAL0 */ + STINTEN = (1 << 4), + RINTEN0 = (1 << 0), + + INTEN0_CLEAR = 0x1F7F7F1F, /* Command style register */ + +}INTEN0_BITS; + +typedef enum { + /* VAL2 */ + RDMD0 = (1 << 16), + /* VAL1 */ + TDMD3 = (1 << 11), + TDMD2 = (1 << 10), + TDMD1 = (1 << 9), + TDMD0 = (1 << 8), + /* VAL0 */ + UINTCMD = (1 << 6), + RX_FAST_SPND = (1 << 5), + TX_FAST_SPND = (1 << 4), + RX_SPND = (1 << 3), + TX_SPND = (1 << 2), + INTREN = (1 << 1), + RUN = (1 << 0), + + CMD0_CLEAR = 0x000F0F7F, /* Command style register */ + +}CMD0_BITS; + +typedef enum { + + /* VAL3 */ + CONDUIT_MODE = (1 << 29), + /* VAL2 */ + RPA = (1 << 19), + DRCVPA = (1 << 18), + DRCVBC = (1 << 17), + PROM = (1 << 16), + /* VAL1 */ + ASTRP_RCV = (1 << 13), + RCV_DROP0 = (1 << 12), + EMBA = (1 << 11), + DXMT2PD = (1 << 10), + LTINTEN = (1 << 9), + DXMTFCS = (1 << 8), + /* VAL0 */ + APAD_XMT = (1 << 6), + DRTY = (1 << 5), + INLOOP = (1 << 4), + EXLOOP = (1 << 3), + REX_RTRY = (1 << 2), + REX_UFLO = (1 << 1), + REX_LCOL = (1 << 0), + + CMD2_CLEAR = 0x3F7F3F7F, /* Command style register */ + +}CMD2_BITS; + +typedef enum { + + /* VAL3 */ + ASF_INIT_DONE_ALIAS = (1 << 29), + /* VAL2 */ + JUMBO = (1 << 21), + VSIZE = (1 << 20), + VLONLY = (1 << 19), + VL_TAG_DEL = (1 << 18), + /* VAL1 */ + EN_PMGR = (1 << 14), + INTLEVEL = (1 << 13), + FORCE_FULL_DUPLEX = (1 << 12), + FORCE_LINK_STATUS = (1 << 11), + APEP = (1 << 10), + MPPLBA = (1 << 9), + /* VAL0 */ + RESET_PHY_PULSE = (1 << 2), + RESET_PHY = (1 << 1), + PHY_RST_POL = (1 << 0), + +}CMD3_BITS; + + +typedef enum { + + /* VAL0 */ + PMAT_SAVE_MATCH = (1 << 4), + PMAT_MODE = (1 << 3), + MPEN_SW = (1 << 1), + LCMODE_SW = (1 << 0), + + CMD7_CLEAR = 0x0000001B /* Command style register */ + +}CMD7_BITS; + + +typedef enum { + + RESET_PHY_WIDTH = (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */ + XMTSP_MASK = (1 << 9) | (1 << 8), /* 9:8 */ + XMTSP_128 = (1 << 9), /* 9 */ + XMTSP_64 = (1 << 8), + CACHE_ALIGN = (1 << 4), + BURST_LIMIT_MASK = (0xF << 0 ), + CTRL1_DEFAULT = 0x00010111, + +}CTRL1_BITS; + +typedef enum { + + FMDC_MASK = (1 << 9)|(1 << 8), /* 9:8 */ + XPHYRST = (1 << 7), + XPHYANE = (1 << 6), + XPHYFD = (1 << 5), + XPHYSP = (1 << 4) | (1 << 3), /* 4:3 */ + APDW_MASK = (1 << 2) | (1 << 1) | (1 << 0), /* 2:0 */ + +}CTRL2_BITS; + +/* XMT_RING_LIMIT 0x7C, 32bit register */ +typedef enum { + + XMT_RING2_LIMIT = (0xFF << 16), /* 23:16 */ + XMT_RING1_LIMIT = (0xFF << 8), /* 15:8 */ + XMT_RING0_LIMIT = (0xFF << 0), /* 7:0 */ + +}XMT_RING_LIMIT_BITS; + +typedef enum { + + AP_REG0_EN = (1 << 15), + AP_REG0_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */ + AP_PHY0_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */ + +}AUTOPOLL0_BITS; + +/* AUTOPOLL1 0x8A, 16bit register */ +typedef enum { + + AP_REG1_EN = (1 << 15), + AP_REG1_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */ + AP_PRE_SUP1 = (1 << 6), + AP_PHY1_DFLT = (1 << 5), + AP_PHY1_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */ + +}AUTOPOLL1_BITS; + + +typedef enum { + + AP_REG2_EN = (1 << 15), + AP_REG2_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */ + AP_PRE_SUP2 = (1 << 6), + AP_PHY2_DFLT = (1 << 5), + AP_PHY2_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */ + +}AUTOPOLL2_BITS; + +typedef enum { + + AP_REG3_EN = (1 << 15), + AP_REG3_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */ + AP_PRE_SUP3 = (1 << 6), + AP_PHY3_DFLT = (1 << 5), + AP_PHY3_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */ + +}AUTOPOLL3_BITS; + + +typedef enum { + + AP_REG4_EN = (1 << 15), + AP_REG4_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */ + AP_PRE_SUP4 = (1 << 6), + AP_PHY4_DFLT = (1 << 5), + AP_PHY4_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */ + +}AUTOPOLL4_BITS; + + +typedef enum { + + AP_REG5_EN = (1 << 15), + AP_REG5_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */ + AP_PRE_SUP5 = (1 << 6), + AP_PHY5_DFLT = (1 << 5), + AP_PHY5_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */ + +}AUTOPOLL5_BITS; + + + + +/* AP_VALUE 0x98, 32bit ragister */ +typedef enum { + + AP_VAL_ACTIVE = (1 << 31), + AP_VAL_RD_CMD = ( 1 << 29), + AP_ADDR = (1 << 18)|(1 << 17)|(1 << 16), /* 18:16 */ + AP_VAL = (0xF << 0) | (0xF << 4) |( 0xF << 8) | + (0xF << 12), /* 15:0 */ + +}AP_VALUE_BITS; + +typedef enum { + + DLY_INT_A_R3 = (1 << 31), + DLY_INT_A_R2 = (1 << 30), + DLY_INT_A_R1 = (1 << 29), + DLY_INT_A_R0 = (1 << 28), + DLY_INT_A_T3 = (1 << 27), + DLY_INT_A_T2 = (1 << 26), + DLY_INT_A_T1 = (1 << 25), + DLY_INT_A_T0 = ( 1 << 24), + EVENT_COUNT_A = (0xF << 16) | (0x1 << 20),/* 20:16 */ + MAX_DELAY_TIME_A = (0xF << 0) | (0xF << 4) | (1 << 8)| + (1 << 9) | (1 << 10), /* 10:0 */ + +}DLY_INT_A_BITS; + +typedef enum { + + DLY_INT_B_R3 = (1 << 31), + DLY_INT_B_R2 = (1 << 30), + DLY_INT_B_R1 = (1 << 29), + DLY_INT_B_R0 = (1 << 28), + DLY_INT_B_T3 = (1 << 27), + DLY_INT_B_T2 = (1 << 26), + DLY_INT_B_T1 = (1 << 25), + DLY_INT_B_T0 = ( 1 << 24), + EVENT_COUNT_B = (0xF << 16) | (0x1 << 20),/* 20:16 */ + MAX_DELAY_TIME_B = (0xF << 0) | (0xF << 4) | (1 << 8)| + (1 << 9) | (1 << 10), /* 10:0 */ +}DLY_INT_B_BITS; + + +/* FLOW_CONTROL 0xC8, 32bit register */ +typedef enum { + + PAUSE_LEN_CHG = (1 << 30), + FTPE = (1 << 22), + FRPE = (1 << 21), + NAPA = (1 << 20), + NPA = (1 << 19), + FIXP = ( 1 << 18), + FCCMD = ( 1 << 16), + PAUSE_LEN = (0xF << 0) | (0xF << 4) |( 0xF << 8) | (0xF << 12), /* 15:0 */ + +}FLOW_CONTROL_BITS; + +/* PHY_ ACCESS 0xD0, 32bit register */ +typedef enum { + + PHY_CMD_ACTIVE = (1 << 31), + PHY_WR_CMD = (1 << 30), + PHY_RD_CMD = (1 << 29), + PHY_RD_ERR = (1 << 28), + PHY_PRE_SUP = (1 << 27), + PHY_ADDR = (1 << 21) | (1 << 22) | (1 << 23)| + (1 << 24) |(1 << 25),/* 25:21 */ + PHY_REG_ADDR = (1 << 16) | (1 << 17) | (1 << 18)| (1 << 19) | (1 << 20),/* 20:16 */ + PHY_DATA = (0xF << 0)|(0xF << 4) |(0xF << 8)| + (0xF << 12),/* 15:0 */ + +}PHY_ACCESS_BITS; + + +/* PMAT0 0x190, 32bit register */ +typedef enum { + PMR_ACTIVE = (1 << 31), + PMR_WR_CMD = (1 << 30), + PMR_RD_CMD = (1 << 29), + PMR_BANK = (1 <<28), + PMR_ADDR = (0xF << 16)|(1 << 20)|(1 << 21)| + (1 << 22),/* 22:16 */ + PMR_B4 = (0xF << 0) | (0xF << 4),/* 15:0 */ +}PMAT0_BITS; + + +/* PMAT1 0x194, 32bit register */ +typedef enum { + PMR_B3 = (0xF << 24) | (0xF <<28),/* 31:24 */ + PMR_B2 = (0xF << 16) |(0xF << 20),/* 23:16 */ + PMR_B1 = (0xF << 8) | (0xF <<12), /* 15:8 */ + PMR_B0 = (0xF << 0)|(0xF << 4),/* 7:0 */ +}PMAT1_BITS; + +/************************************************************************/ +/* */ +/* MIB counter definitions */ +/* */ +/************************************************************************/ + +#define rcv_miss_pkts 0x00 +#define rcv_octets 0x01 +#define rcv_broadcast_pkts 0x02 +#define rcv_multicast_pkts 0x03 +#define rcv_undersize_pkts 0x04 +#define rcv_oversize_pkts 0x05 +#define rcv_fragments 0x06 +#define rcv_jabbers 0x07 +#define rcv_unicast_pkts 0x08 +#define rcv_alignment_errors 0x09 +#define rcv_fcs_errors 0x0A +#define rcv_good_octets 0x0B +#define rcv_mac_ctrl 0x0C +#define rcv_flow_ctrl 0x0D +#define rcv_pkts_64_octets 0x0E +#define rcv_pkts_65to127_octets 0x0F +#define rcv_pkts_128to255_octets 0x10 +#define rcv_pkts_256to511_octets 0x11 +#define rcv_pkts_512to1023_octets 0x12 +#define rcv_pkts_1024to1518_octets 0x13 +#define rcv_unsupported_opcode 0x14 +#define rcv_symbol_errors 0x15 +#define rcv_drop_pkts_ring1 0x16 +#define rcv_drop_pkts_ring2 0x17 +#define rcv_drop_pkts_ring3 0x18 +#define rcv_drop_pkts_ring4 0x19 +#define rcv_jumbo_pkts 0x1A + +#define xmt_underrun_pkts 0x20 +#define xmt_octets 0x21 +#define xmt_packets 0x22 +#define xmt_broadcast_pkts 0x23 +#define xmt_multicast_pkts 0x24 +#define xmt_collisions 0x25 +#define xmt_unicast_pkts 0x26 +#define xmt_one_collision 0x27 +#define xmt_multiple_collision 0x28 +#define xmt_deferred_transmit 0x29 +#define xmt_late_collision 0x2A +#define xmt_excessive_defer 0x2B +#define xmt_loss_carrier 0x2C +#define xmt_excessive_collision 0x2D +#define xmt_back_pressure 0x2E +#define xmt_flow_ctrl 0x2F +#define xmt_pkts_64_octets 0x30 +#define xmt_pkts_65to127_octets 0x31 +#define xmt_pkts_128to255_octets 0x32 +#define xmt_pkts_256to511_octets 0x33 +#define xmt_pkts_512to1023_octets 0x34 +#define xmt_pkts_1024to1518_octet 0x35 +#define xmt_oversize_pkts 0x36 +#define xmt_jumbo_pkts 0x37 + +/* ipg parameters */ +#define DEFAULT_IPG 0x60 +#define IFS1_DELTA 36 +#define IPG_CONVERGE_JIFFIES (HZ/2) +#define IPG_STABLE_TIME 5 +#define MIN_IPG 96 +#define MAX_IPG 255 +#define IPG_STEP 16 +#define CSTATE 1 +#define SSTATE 2 + +/* amd8111e decriptor flag definitions */ +typedef enum { + + OWN_BIT = (1 << 15), + ADD_FCS_BIT = (1 << 13), + LTINT_BIT = (1 << 12), + STP_BIT = (1 << 9), + ENP_BIT = (1 << 8), + KILL_BIT = (1 << 6), + TCC_VLAN_INSERT = (1 << 1), + TCC_VLAN_REPLACE = (1 << 1) |( 1<< 0), + +}TX_FLAG_BITS; + +typedef enum { + ERR_BIT = (1 << 14), + FRAM_BIT = (1 << 13), + OFLO_BIT = (1 << 12), + CRC_BIT = (1 << 11), + PAM_BIT = (1 << 6), + LAFM_BIT = (1 << 5), + BAM_BIT = (1 << 4), + TT_VLAN_TAGGED = (1 << 3) |(1 << 2),/* 0x000 */ + TT_PRTY_TAGGED = (1 << 3),/* 0x0008 */ + +}RX_FLAG_BITS; + +#define RESET_RX_FLAGS 0x0000 +#define TT_MASK 0x000c +#define TCC_MASK 0x0003 + +/* driver ioctl parameters */ +#define AMD8111E_REG_DUMP_LEN 13*sizeof(u32) + +/* crc generator constants */ +#define CRC32 0xedb88320 +#define INITCRC 0xFFFFFFFF + +/* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register. +BUG? */ +#define amd8111e_writeq(_UlData,_memMap) \ + writel(*(u32*)(&_UlData), _memMap); \ + writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4) + +/* maps the external speed options to internal value */ +typedef enum { + SPEED_AUTONEG, + SPEED10_HALF, + SPEED10_FULL, + SPEED100_HALF, + SPEED100_FULL, +}EXT_PHY_OPTION; + + +#endif /* _AMD8111E_H */ + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k.c new file mode 100644 index 0000000..5101a54 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k.c @@ -0,0 +1,1694 @@ +/* + * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting + * Copyright (c) 2004-2005 Atheros Communications, Inc. + * Copyright (c) 2006 Devicescape Software, Inc. + * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> + * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> + * + * Modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net> + * Original from Linux kernel 2.6.30. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + */ + +FILE_LICENCE ( BSD3 ); + +#include <stdlib.h> +#include <gpxe/malloc.h> +#include <gpxe/timer.h> +#include <gpxe/netdevice.h> +#include <gpxe/pci.h> +#include <gpxe/pci_io.h> + +#include "base.h" +#include "reg.h" + +#define ATH5K_CALIB_INTERVAL 10 /* Calibrate PHY every 10 seconds */ +#define ATH5K_RETRIES 4 /* Number of times to retry packet sends */ +#define ATH5K_DESC_ALIGN 16 /* Alignment for TX/RX descriptors */ + +/******************\ +* Internal defines * +\******************/ + +/* Known PCI ids */ +static struct pci_device_id ath5k_nics[] = { + PCI_ROM(0x168c, 0x0207, "ath5210e", "Atheros 5210 early", AR5K_AR5210), + PCI_ROM(0x168c, 0x0007, "ath5210", "Atheros 5210", AR5K_AR5210), + PCI_ROM(0x168c, 0x0011, "ath5311", "Atheros 5311 (AHB)", AR5K_AR5211), + PCI_ROM(0x168c, 0x0012, "ath5211", "Atheros 5211", AR5K_AR5211), + PCI_ROM(0x168c, 0x0013, "ath5212", "Atheros 5212", AR5K_AR5212), + PCI_ROM(0xa727, 0x0013, "ath5212c","3com Ath 5212", AR5K_AR5212), + PCI_ROM(0x10b7, 0x0013, "rdag675", "3com 3CRDAG675", AR5K_AR5212), + PCI_ROM(0x168c, 0x1014, "ath5212m", "Ath 5212 miniPCI", AR5K_AR5212), + PCI_ROM(0x168c, 0x0014, "ath5212x14", "Atheros 5212 x14", AR5K_AR5212), + PCI_ROM(0x168c, 0x0015, "ath5212x15", "Atheros 5212 x15", AR5K_AR5212), + PCI_ROM(0x168c, 0x0016, "ath5212x16", "Atheros 5212 x16", AR5K_AR5212), + PCI_ROM(0x168c, 0x0017, "ath5212x17", "Atheros 5212 x17", AR5K_AR5212), + PCI_ROM(0x168c, 0x0018, "ath5212x18", "Atheros 5212 x18", AR5K_AR5212), + PCI_ROM(0x168c, 0x0019, "ath5212x19", "Atheros 5212 x19", AR5K_AR5212), + PCI_ROM(0x168c, 0x001a, "ath2413", "Atheros 2413 Griffin", AR5K_AR5212), + PCI_ROM(0x168c, 0x001b, "ath5413", "Atheros 5413 Eagle", AR5K_AR5212), + PCI_ROM(0x168c, 0x001c, "ath5212e", "Atheros 5212 PCI-E", AR5K_AR5212), + PCI_ROM(0x168c, 0x001d, "ath2417", "Atheros 2417 Nala", AR5K_AR5212), +}; + +/* Known SREVs */ +static const struct ath5k_srev_name srev_names[] = { + { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, + { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, + { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, + { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, + { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, + { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, + { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, + { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, + { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, + { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, + { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, + { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, + { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, + { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, + { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, + { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, + { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, + { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, + { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, + { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, + { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, + { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, + { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, + { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, + { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, + { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, + { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, + { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, + { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, + { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, + { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, + { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, + { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, + { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, + { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, + { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, +}; + +#define ATH5K_SPMBL_NO 1 +#define ATH5K_SPMBL_YES 2 +#define ATH5K_SPMBL_BOTH 3 + +static const struct { + u16 bitrate; + u8 short_pmbl; + u8 hw_code; +} ath5k_rates[] = { + { 10, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_1M }, + { 20, ATH5K_SPMBL_NO, ATH5K_RATE_CODE_2M }, + { 55, ATH5K_SPMBL_NO, ATH5K_RATE_CODE_5_5M }, + { 110, ATH5K_SPMBL_NO, ATH5K_RATE_CODE_11M }, + { 60, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_6M }, + { 90, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_9M }, + { 120, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_12M }, + { 180, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_18M }, + { 240, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_24M }, + { 360, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_36M }, + { 480, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_48M }, + { 540, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_54M }, + { 20, ATH5K_SPMBL_YES, ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE }, + { 55, ATH5K_SPMBL_YES, ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE }, + { 110, ATH5K_SPMBL_YES, ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE }, + { 0, 0, 0 }, +}; + +#define ATH5K_NR_RATES 15 + +/* + * Prototypes - PCI stack related functions + */ +static int ath5k_probe(struct pci_device *pdev, + const struct pci_device_id *id); +static void ath5k_remove(struct pci_device *pdev); + +struct pci_driver ath5k_pci_driver __pci_driver = { + .ids = ath5k_nics, + .id_count = sizeof(ath5k_nics) / sizeof(ath5k_nics[0]), + .probe = ath5k_probe, + .remove = ath5k_remove, +}; + + + +/* + * Prototypes - MAC 802.11 stack related functions + */ +static int ath5k_tx(struct net80211_device *dev, struct io_buffer *skb); +static int ath5k_reset(struct ath5k_softc *sc, struct net80211_channel *chan); +static int ath5k_reset_wake(struct ath5k_softc *sc); +static int ath5k_start(struct net80211_device *dev); +static void ath5k_stop(struct net80211_device *dev); +static int ath5k_config(struct net80211_device *dev, int changed); +static void ath5k_poll(struct net80211_device *dev); +static void ath5k_irq(struct net80211_device *dev, int enable); + +static struct net80211_device_operations ath5k_ops = { + .open = ath5k_start, + .close = ath5k_stop, + .transmit = ath5k_tx, + .poll = ath5k_poll, + .irq = ath5k_irq, + .config = ath5k_config, +}; + +/* + * Prototypes - Internal functions + */ +/* Attach detach */ +static int ath5k_attach(struct net80211_device *dev); +static void ath5k_detach(struct net80211_device *dev); +/* Channel/mode setup */ +static unsigned int ath5k_copy_channels(struct ath5k_hw *ah, + struct net80211_channel *channels, + unsigned int mode, + unsigned int max); +static int ath5k_setup_bands(struct net80211_device *dev); +static int ath5k_chan_set(struct ath5k_softc *sc, + struct net80211_channel *chan); +static void ath5k_setcurmode(struct ath5k_softc *sc, + unsigned int mode); +static void ath5k_mode_setup(struct ath5k_softc *sc); + +/* Descriptor setup */ +static int ath5k_desc_alloc(struct ath5k_softc *sc); +static void ath5k_desc_free(struct ath5k_softc *sc); +/* Buffers setup */ +static int ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf); +static int ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf); + +static inline void ath5k_txbuf_free(struct ath5k_softc *sc, + struct ath5k_buf *bf) +{ + if (!bf->iob) + return; + + net80211_tx_complete(sc->dev, bf->iob, 0, ECANCELED); + bf->iob = NULL; +} + +static inline void ath5k_rxbuf_free(struct ath5k_softc *sc __unused, + struct ath5k_buf *bf) +{ + free_iob(bf->iob); + bf->iob = NULL; +} + +/* Queues setup */ +static int ath5k_txq_setup(struct ath5k_softc *sc, + int qtype, int subtype); +static void ath5k_txq_drainq(struct ath5k_softc *sc, + struct ath5k_txq *txq); +static void ath5k_txq_cleanup(struct ath5k_softc *sc); +static void ath5k_txq_release(struct ath5k_softc *sc); +/* Rx handling */ +static int ath5k_rx_start(struct ath5k_softc *sc); +static void ath5k_rx_stop(struct ath5k_softc *sc); +/* Tx handling */ +static void ath5k_tx_processq(struct ath5k_softc *sc, + struct ath5k_txq *txq); + +/* Interrupt handling */ +static int ath5k_init(struct ath5k_softc *sc); +static int ath5k_stop_hw(struct ath5k_softc *sc); + +static void ath5k_calibrate(struct ath5k_softc *sc); + +/* Filter */ +static void ath5k_configure_filter(struct ath5k_softc *sc); + +/********************\ +* PCI Initialization * +\********************/ + +#if DBGLVL_MAX +static const char * +ath5k_chip_name(enum ath5k_srev_type type, u16 val) +{ + const char *name = "xxxxx"; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(srev_names); i++) { + if (srev_names[i].sr_type != type) + continue; + + if ((val & 0xf0) == srev_names[i].sr_val) + name = srev_names[i].sr_name; + + if ((val & 0xff) == srev_names[i].sr_val) { + name = srev_names[i].sr_name; + break; + } + } + + return name; +} +#endif + +static int ath5k_probe(struct pci_device *pdev, + const struct pci_device_id *id) +{ + void *mem; + struct ath5k_softc *sc; + struct net80211_device *dev; + int ret; + u8 csz; + + adjust_pci_device(pdev); + + /* + * Cache line size is used to size and align various + * structures used to communicate with the hardware. + */ + pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); + if (csz == 0) { + /* + * We must have this setup properly for rx buffer + * DMA to work so force a reasonable value here if it + * comes up zero. + */ + pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 16); + } + /* + * The default setting of latency timer yields poor results, + * set it to the value used by other systems. It may be worth + * tweaking this setting more. + */ + pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); + + /* + * Disable the RETRY_TIMEOUT register (0x41) to keep + * PCI Tx retries from interfering with C3 CPU state. + */ + pci_write_config_byte(pdev, 0x41, 0); + + mem = ioremap(pdev->membase, 0x10000); + if (!mem) { + DBG("ath5k: cannot remap PCI memory region\n"); + ret = -EIO; + goto err; + } + + /* + * Allocate dev (net80211 main struct) + * and dev->priv (driver private data) + */ + dev = net80211_alloc(sizeof(*sc)); + if (!dev) { + DBG("ath5k: cannot allocate 802.11 device\n"); + ret = -ENOMEM; + goto err_map; + } + + /* Initialize driver private data */ + sc = dev->priv; + sc->dev = dev; + sc->pdev = pdev; + + sc->hwinfo = zalloc(sizeof(*sc->hwinfo)); + if (!sc->hwinfo) { + DBG("ath5k: cannot allocate 802.11 hardware info structure\n"); + ret = -ENOMEM; + goto err_free; + } + + sc->hwinfo->flags = NET80211_HW_RX_HAS_FCS; + sc->hwinfo->signal_type = NET80211_SIGNAL_DB; + sc->hwinfo->signal_max = 40; /* 35dB should give perfect 54Mbps */ + sc->hwinfo->channel_change_time = 5000; + + /* Avoid working with the device until setup is complete */ + sc->status |= ATH_STAT_INVALID; + + sc->iobase = mem; + sc->cachelsz = csz * 4; /* convert to bytes */ + + DBG("ath5k: register base at %p (%08lx)\n", sc->iobase, pdev->membase); + DBG("ath5k: cache line size %d\n", sc->cachelsz); + + /* Set private data */ + pci_set_drvdata(pdev, dev); + dev->netdev->dev = (struct device *)pdev; + + /* Initialize device */ + ret = ath5k_hw_attach(sc, id->driver_data, &sc->ah); + if (ret) + goto err_free_hwinfo; + + /* Finish private driver data initialization */ + ret = ath5k_attach(dev); + if (ret) + goto err_ah; + +#if DBGLVL_MAX + DBG("Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", + ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev), + sc->ah->ah_mac_srev, sc->ah->ah_phy_revision); + + if (!sc->ah->ah_single_chip) { + /* Single chip radio (!RF5111) */ + if (sc->ah->ah_radio_5ghz_revision && + !sc->ah->ah_radio_2ghz_revision) { + /* No 5GHz support -> report 2GHz radio */ + if (!(sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11A)) { + DBG("RF%s 2GHz radio found (0x%x)\n", + ath5k_chip_name(AR5K_VERSION_RAD, + sc->ah->ah_radio_5ghz_revision), + sc->ah->ah_radio_5ghz_revision); + /* No 2GHz support (5110 and some + * 5Ghz only cards) -> report 5Ghz radio */ + } else if (!(sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11B)) { + DBG("RF%s 5GHz radio found (0x%x)\n", + ath5k_chip_name(AR5K_VERSION_RAD, + sc->ah->ah_radio_5ghz_revision), + sc->ah->ah_radio_5ghz_revision); + /* Multiband radio */ + } else { + DBG("RF%s multiband radio found (0x%x)\n", + ath5k_chip_name(AR5K_VERSION_RAD, + sc->ah->ah_radio_5ghz_revision), + sc->ah->ah_radio_5ghz_revision); + } + } + /* Multi chip radio (RF5111 - RF2111) -> + * report both 2GHz/5GHz radios */ + else if (sc->ah->ah_radio_5ghz_revision && + sc->ah->ah_radio_2ghz_revision) { + DBG("RF%s 5GHz radio found (0x%x)\n", + ath5k_chip_name(AR5K_VERSION_RAD, + sc->ah->ah_radio_5ghz_revision), + sc->ah->ah_radio_5ghz_revision); + DBG("RF%s 2GHz radio found (0x%x)\n", + ath5k_chip_name(AR5K_VERSION_RAD, + sc->ah->ah_radio_2ghz_revision), + sc->ah->ah_radio_2ghz_revision); + } + } +#endif + + /* Ready to go */ + sc->status &= ~ATH_STAT_INVALID; + + return 0; +err_ah: + ath5k_hw_detach(sc->ah); +err_free_hwinfo: + free(sc->hwinfo); +err_free: + net80211_free(dev); +err_map: + iounmap(mem); +err: + return ret; +} + +static void ath5k_remove(struct pci_device *pdev) +{ + struct net80211_device *dev = pci_get_drvdata(pdev); + struct ath5k_softc *sc = dev->priv; + + ath5k_detach(dev); + ath5k_hw_detach(sc->ah); + iounmap(sc->iobase); + free(sc->hwinfo); + net80211_free(dev); +} + + +/***********************\ +* Driver Initialization * +\***********************/ + +static int +ath5k_attach(struct net80211_device *dev) +{ + struct ath5k_softc *sc = dev->priv; + struct ath5k_hw *ah = sc->ah; + int ret; + + /* + * Collect the channel list. The 802.11 layer + * is resposible for filtering this list based + * on settings like the phy mode and regulatory + * domain restrictions. + */ + ret = ath5k_setup_bands(dev); + if (ret) { + DBG("ath5k: can't get channels\n"); + goto err; + } + + /* NB: setup here so ath5k_rate_update is happy */ + if (ah->ah_modes & AR5K_MODE_BIT_11A) + ath5k_setcurmode(sc, AR5K_MODE_11A); + else + ath5k_setcurmode(sc, AR5K_MODE_11B); + + /* + * Allocate tx+rx descriptors and populate the lists. + */ + ret = ath5k_desc_alloc(sc); + if (ret) { + DBG("ath5k: can't allocate descriptors\n"); + goto err; + } + + /* + * Allocate hardware transmit queues. Note that hw functions + * handle reseting these queues at the needed time. + */ + ret = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); + if (ret) { + DBG("ath5k: can't setup xmit queue\n"); + goto err_desc; + } + + sc->last_calib_ticks = currticks(); + + ret = ath5k_eeprom_read_mac(ah, sc->hwinfo->hwaddr); + if (ret) { + DBG("ath5k: unable to read address from EEPROM: 0x%04x\n", + sc->pdev->device); + goto err_queues; + } + + memset(sc->bssidmask, 0xff, ETH_ALEN); + ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask); + + ret = net80211_register(sc->dev, &ath5k_ops, sc->hwinfo); + if (ret) { + DBG("ath5k: can't register ieee80211 hw\n"); + goto err_queues; + } + + return 0; +err_queues: + ath5k_txq_release(sc); +err_desc: + ath5k_desc_free(sc); +err: + return ret; +} + +static void +ath5k_detach(struct net80211_device *dev) +{ + struct ath5k_softc *sc = dev->priv; + + net80211_unregister(dev); + ath5k_desc_free(sc); + ath5k_txq_release(sc); +} + + + + +/********************\ +* Channel/mode setup * +\********************/ + +/* + * Convert IEEE channel number to MHz frequency. + */ +static inline short +ath5k_ieee2mhz(short chan) +{ + if (chan < 14) + return 2407 + 5 * chan; + if (chan == 14) + return 2484; + if (chan < 27) + return 2212 + 20 * chan; + return 5000 + 5 * chan; +} + +static unsigned int +ath5k_copy_channels(struct ath5k_hw *ah, + struct net80211_channel *channels, + unsigned int mode, unsigned int max) +{ + unsigned int i, count, size, chfreq, freq, ch; + + if (!(ah->ah_modes & (1 << mode))) + return 0; + + switch (mode) { + case AR5K_MODE_11A: + case AR5K_MODE_11A_TURBO: + /* 1..220, but 2GHz frequencies are filtered by check_channel */ + size = 220; + chfreq = CHANNEL_5GHZ; + break; + case AR5K_MODE_11B: + case AR5K_MODE_11G: + case AR5K_MODE_11G_TURBO: + size = 26; + chfreq = CHANNEL_2GHZ; + break; + default: + return 0; + } + + for (i = 0, count = 0; i < size && max > 0; i++) { + ch = i + 1 ; + freq = ath5k_ieee2mhz(ch); + + /* Check if channel is supported by the chipset */ + if (!ath5k_channel_ok(ah, freq, chfreq)) + continue; + + /* Write channel info and increment counter */ + channels[count].center_freq = freq; + channels[count].maxpower = 0; /* use regulatory */ + channels[count].band = (chfreq == CHANNEL_2GHZ) ? + NET80211_BAND_2GHZ : NET80211_BAND_5GHZ; + switch (mode) { + case AR5K_MODE_11A: + case AR5K_MODE_11G: + channels[count].hw_value = chfreq | CHANNEL_OFDM; + break; + case AR5K_MODE_11A_TURBO: + case AR5K_MODE_11G_TURBO: + channels[count].hw_value = chfreq | + CHANNEL_OFDM | CHANNEL_TURBO; + break; + case AR5K_MODE_11B: + channels[count].hw_value = CHANNEL_B; + } + + count++; + max--; + } + + return count; +} + +static int +ath5k_setup_bands(struct net80211_device *dev) +{ + struct ath5k_softc *sc = dev->priv; + struct ath5k_hw *ah = sc->ah; + int max_c, count_c = 0; + int i; + int band; + + max_c = sizeof(sc->hwinfo->channels) / sizeof(sc->hwinfo->channels[0]); + + /* 2GHz band */ + if (sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11G) { + /* G mode */ + band = NET80211_BAND_2GHZ; + sc->hwinfo->bands = NET80211_BAND_BIT_2GHZ; + sc->hwinfo->modes = (NET80211_MODE_G | NET80211_MODE_B); + + for (i = 0; i < 12; i++) + sc->hwinfo->rates[band][i] = ath5k_rates[i].bitrate; + sc->hwinfo->nr_rates[band] = 12; + + sc->hwinfo->nr_channels = + ath5k_copy_channels(ah, sc->hwinfo->channels, + AR5K_MODE_11G, max_c); + count_c = sc->hwinfo->nr_channels; + max_c -= count_c; + } else if (sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11B) { + /* B mode */ + band = NET80211_BAND_2GHZ; + sc->hwinfo->bands = NET80211_BAND_BIT_2GHZ; + sc->hwinfo->modes = NET80211_MODE_B; + + for (i = 0; i < 4; i++) + sc->hwinfo->rates[band][i] = ath5k_rates[i].bitrate; + sc->hwinfo->nr_rates[band] = 4; + + sc->hwinfo->nr_channels = + ath5k_copy_channels(ah, sc->hwinfo->channels, + AR5K_MODE_11B, max_c); + count_c = sc->hwinfo->nr_channels; + max_c -= count_c; + } + + /* 5GHz band, A mode */ + if (sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11A) { + band = NET80211_BAND_5GHZ; + sc->hwinfo->bands |= NET80211_BAND_BIT_5GHZ; + sc->hwinfo->modes |= NET80211_MODE_A; + + for (i = 0; i < 8; i++) + sc->hwinfo->rates[band][i] = ath5k_rates[i+4].bitrate; + sc->hwinfo->nr_rates[band] = 8; + + sc->hwinfo->nr_channels = + ath5k_copy_channels(ah, sc->hwinfo->channels, + AR5K_MODE_11B, max_c); + count_c = sc->hwinfo->nr_channels; + max_c -= count_c; + } + + return 0; +} + +/* + * Set/change channels. If the channel is really being changed, + * it's done by reseting the chip. To accomplish this we must + * first cleanup any pending DMA, then restart stuff after a la + * ath5k_init. + */ +static int +ath5k_chan_set(struct ath5k_softc *sc, struct net80211_channel *chan) +{ + if (chan->center_freq != sc->curchan->center_freq || + chan->hw_value != sc->curchan->hw_value) { + /* + * To switch channels clear any pending DMA operations; + * wait long enough for the RX fifo to drain, reset the + * hardware at the new frequency, and then re-enable + * the relevant bits of the h/w. + */ + DBG2("ath5k: resetting for channel change (%d -> %d MHz)\n", + sc->curchan->center_freq, chan->center_freq); + return ath5k_reset(sc, chan); + } + + return 0; +} + +static void +ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode) +{ + sc->curmode = mode; + + if (mode == AR5K_MODE_11A) { + sc->curband = NET80211_BAND_5GHZ; + } else { + sc->curband = NET80211_BAND_2GHZ; + } +} + +static void +ath5k_mode_setup(struct ath5k_softc *sc) +{ + struct ath5k_hw *ah = sc->ah; + u32 rfilt; + + /* configure rx filter */ + rfilt = sc->filter_flags; + ath5k_hw_set_rx_filter(ah, rfilt); + + if (ath5k_hw_hasbssidmask(ah)) + ath5k_hw_set_bssid_mask(ah, sc->bssidmask); + + /* configure operational mode */ + ath5k_hw_set_opmode(ah); + + ath5k_hw_set_mcast_filter(ah, 0, 0); +} + +static inline int +ath5k_hw_rix_to_bitrate(int hw_rix) +{ + int i; + + for (i = 0; i < ATH5K_NR_RATES; i++) { + if (ath5k_rates[i].hw_code == hw_rix) + return ath5k_rates[i].bitrate; + } + + DBG("ath5k: invalid rix %02x\n", hw_rix); + return 10; /* use lowest rate */ +} + +int ath5k_bitrate_to_hw_rix(int bitrate) +{ + int i; + + for (i = 0; i < ATH5K_NR_RATES; i++) { + if (ath5k_rates[i].bitrate == bitrate) + return ath5k_rates[i].hw_code; + } + + DBG("ath5k: invalid bitrate %d\n", bitrate); + return ATH5K_RATE_CODE_1M; /* use lowest rate */ +} + +/***************\ +* Buffers setup * +\***************/ + +static struct io_buffer * +ath5k_rx_iob_alloc(struct ath5k_softc *sc, u32 *iob_addr) +{ + struct io_buffer *iob; + unsigned int off; + + /* + * Allocate buffer with headroom_needed space for the + * fake physical layer header at the start. + */ + iob = alloc_iob(sc->rxbufsize + sc->cachelsz - 1); + + if (!iob) { + DBG("ath5k: can't alloc iobuf of size %d\n", + sc->rxbufsize + sc->cachelsz - 1); + return NULL; + } + + *iob_addr = virt_to_bus(iob->data); + + /* + * Cache-line-align. This is important (for the + * 5210 at least) as not doing so causes bogus data + * in rx'd frames. + */ + off = *iob_addr % sc->cachelsz; + if (off != 0) { + iob_reserve(iob, sc->cachelsz - off); + *iob_addr += sc->cachelsz - off; + } + + return iob; +} + +static int +ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) +{ + struct ath5k_hw *ah = sc->ah; + struct io_buffer *iob = bf->iob; + struct ath5k_desc *ds; + + if (!iob) { + iob = ath5k_rx_iob_alloc(sc, &bf->iobaddr); + if (!iob) + return -ENOMEM; + bf->iob = iob; + } + + /* + * Setup descriptors. For receive we always terminate + * the descriptor list with a self-linked entry so we'll + * not get overrun under high load (as can happen with a + * 5212 when ANI processing enables PHY error frames). + * + * To insure the last descriptor is self-linked we create + * each descriptor as self-linked and add it to the end. As + * each additional descriptor is added the previous self-linked + * entry is ``fixed'' naturally. This should be safe even + * if DMA is happening. When processing RX interrupts we + * never remove/process the last, self-linked, entry on the + * descriptor list. This insures the hardware always has + * someplace to write a new frame. + */ + ds = bf->desc; + ds->ds_link = bf->daddr; /* link to self */ + ds->ds_data = bf->iobaddr; + if (ah->ah_setup_rx_desc(ah, ds, + iob_tailroom(iob), /* buffer size */ + 0) != 0) { + DBG("ath5k: error setting up RX descriptor for %d bytes\n", iob_tailroom(iob)); + return -EINVAL; + } + + if (sc->rxlink != NULL) + *sc->rxlink = bf->daddr; + sc->rxlink = &ds->ds_link; + return 0; +} + +static int +ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) +{ + struct ath5k_hw *ah = sc->ah; + struct ath5k_txq *txq = &sc->txq; + struct ath5k_desc *ds = bf->desc; + struct io_buffer *iob = bf->iob; + unsigned int pktlen, flags; + int ret; + u16 duration = 0; + u16 cts_rate = 0; + + flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; + bf->iobaddr = virt_to_bus(iob->data); + pktlen = iob_len(iob); + + /* FIXME: If we are in g mode and rate is a CCK rate + * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta + * from tx power (value is in dB units already) */ + if (sc->dev->phy_flags & NET80211_PHY_USE_PROTECTION) { + struct net80211_device *dev = sc->dev; + + flags |= AR5K_TXDESC_CTSENA; + cts_rate = sc->hw_rtscts_rate; + duration = net80211_cts_duration(dev, pktlen); + } + ret = ah->ah_setup_tx_desc(ah, ds, pktlen, + IEEE80211_TYP_FRAME_HEADER_LEN, + AR5K_PKT_TYPE_NORMAL, sc->power_level * 2, + sc->hw_rate, ATH5K_RETRIES, + AR5K_TXKEYIX_INVALID, 0, flags, + cts_rate, duration); + if (ret) + return ret; + + ds->ds_link = 0; + ds->ds_data = bf->iobaddr; + + list_add_tail(&bf->list, &txq->q); + if (txq->link == NULL) /* is this first packet? */ + ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); + else /* no, so only link it */ + *txq->link = bf->daddr; + + txq->link = &ds->ds_link; + ath5k_hw_start_tx_dma(ah, txq->qnum); + mb(); + + return 0; +} + +/*******************\ +* Descriptors setup * +\*******************/ + +static int +ath5k_desc_alloc(struct ath5k_softc *sc) +{ + struct ath5k_desc *ds; + struct ath5k_buf *bf; + u32 da; + unsigned int i; + int ret; + + /* allocate descriptors */ + sc->desc_len = sizeof(struct ath5k_desc) * (ATH_TXBUF + ATH_RXBUF + 1); + sc->desc = malloc_dma(sc->desc_len, ATH5K_DESC_ALIGN); + if (sc->desc == NULL) { + DBG("ath5k: can't allocate descriptors\n"); + ret = -ENOMEM; + goto err; + } + memset(sc->desc, 0, sc->desc_len); + sc->desc_daddr = virt_to_bus(sc->desc); + + ds = sc->desc; + da = sc->desc_daddr; + + bf = calloc(ATH_TXBUF + ATH_RXBUF + 1, sizeof(struct ath5k_buf)); + if (bf == NULL) { + DBG("ath5k: can't allocate buffer pointers\n"); + ret = -ENOMEM; + goto err_free; + } + sc->bufptr = bf; + + INIT_LIST_HEAD(&sc->rxbuf); + for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { + bf->desc = ds; + bf->daddr = da; + list_add_tail(&bf->list, &sc->rxbuf); + } + + INIT_LIST_HEAD(&sc->txbuf); + sc->txbuf_len = ATH_TXBUF; + for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) { + bf->desc = ds; + bf->daddr = da; + list_add_tail(&bf->list, &sc->txbuf); + } + + return 0; + +err_free: + free_dma(sc->desc, sc->desc_len); +err: + sc->desc = NULL; + return ret; +} + +static void +ath5k_desc_free(struct ath5k_softc *sc) +{ + struct ath5k_buf *bf; + + list_for_each_entry(bf, &sc->txbuf, list) + ath5k_txbuf_free(sc, bf); + list_for_each_entry(bf, &sc->rxbuf, list) + ath5k_rxbuf_free(sc, bf); + + /* Free memory associated with all descriptors */ + free_dma(sc->desc, sc->desc_len); + + free(sc->bufptr); + sc->bufptr = NULL; +} + + + + + +/**************\ +* Queues setup * +\**************/ + +static int +ath5k_txq_setup(struct ath5k_softc *sc, int qtype, int subtype) +{ + struct ath5k_hw *ah = sc->ah; + struct ath5k_txq *txq; + struct ath5k_txq_info qi = { + .tqi_subtype = subtype, + .tqi_aifs = AR5K_TXQ_USEDEFAULT, + .tqi_cw_min = AR5K_TXQ_USEDEFAULT, + .tqi_cw_max = AR5K_TXQ_USEDEFAULT + }; + int qnum; + + /* + * Enable interrupts only for EOL and DESC conditions. + * We mark tx descriptors to receive a DESC interrupt + * when a tx queue gets deep; otherwise waiting for the + * EOL to reap descriptors. Note that this is done to + * reduce interrupt load and this only defers reaping + * descriptors, never transmitting frames. Aside from + * reducing interrupts this also permits more concurrency. + * The only potential downside is if the tx queue backs + * up in which case the top half of the kernel may backup + * due to a lack of tx descriptors. + */ + qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | + AR5K_TXQ_FLAG_TXDESCINT_ENABLE; + qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); + if (qnum < 0) { + DBG("ath5k: can't set up a TX queue\n"); + return -EIO; + } + + txq = &sc->txq; + if (!txq->setup) { + txq->qnum = qnum; + txq->link = NULL; + INIT_LIST_HEAD(&txq->q); + txq->setup = 1; + } + return 0; +} + +static void +ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq) +{ + struct ath5k_buf *bf, *bf0; + + list_for_each_entry_safe(bf, bf0, &txq->q, list) { + ath5k_txbuf_free(sc, bf); + + list_del(&bf->list); + list_add_tail(&bf->list, &sc->txbuf); + sc->txbuf_len++; + } + txq->link = NULL; +} + +/* + * Drain the transmit queues and reclaim resources. + */ +static void +ath5k_txq_cleanup(struct ath5k_softc *sc) +{ + struct ath5k_hw *ah = sc->ah; + + if (!(sc->status & ATH_STAT_INVALID)) { + /* don't touch the hardware if marked invalid */ + if (sc->txq.setup) { + ath5k_hw_stop_tx_dma(ah, sc->txq.qnum); + DBG("ath5k: txq [%d] %x, link %p\n", + sc->txq.qnum, + ath5k_hw_get_txdp(ah, sc->txq.qnum), + sc->txq.link); + } + } + + if (sc->txq.setup) + ath5k_txq_drainq(sc, &sc->txq); +} + +static void +ath5k_txq_release(struct ath5k_softc *sc) +{ + if (sc->txq.setup) { + ath5k_hw_release_tx_queue(sc->ah); + sc->txq.setup = 0; + } +} + + + + +/*************\ +* RX Handling * +\*************/ + +/* + * Enable the receive h/w following a reset. + */ +static int +ath5k_rx_start(struct ath5k_softc *sc) +{ + struct ath5k_hw *ah = sc->ah; + struct ath5k_buf *bf; + int ret; + + sc->rxbufsize = IEEE80211_MAX_LEN; + if (sc->rxbufsize % sc->cachelsz != 0) + sc->rxbufsize += sc->cachelsz - (sc->rxbufsize % sc->cachelsz); + + sc->rxlink = NULL; + + list_for_each_entry(bf, &sc->rxbuf, list) { + ret = ath5k_rxbuf_setup(sc, bf); + if (ret != 0) + return ret; + } + + bf = list_entry(sc->rxbuf.next, struct ath5k_buf, list); + + ath5k_hw_set_rxdp(ah, bf->daddr); + ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ + ath5k_mode_setup(sc); /* set filters, etc. */ + ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ + + return 0; +} + +/* + * Disable the receive h/w in preparation for a reset. + */ +static void +ath5k_rx_stop(struct ath5k_softc *sc) +{ + struct ath5k_hw *ah = sc->ah; + + ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ + ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ + ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ + + sc->rxlink = NULL; /* just in case */ +} + +static void +ath5k_handle_rx(struct ath5k_softc *sc) +{ + struct ath5k_rx_status rs; + struct io_buffer *iob, *next_iob; + u32 next_iob_addr; + struct ath5k_buf *bf, *bf_last; + struct ath5k_desc *ds; + int ret; + + memset(&rs, 0, sizeof(rs)); + + if (list_empty(&sc->rxbuf)) { + DBG("ath5k: empty rx buf pool\n"); + return; + } + + bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list); + + do { + bf = list_entry(sc->rxbuf.next, struct ath5k_buf, list); + assert(bf->iob != NULL); + iob = bf->iob; + ds = bf->desc; + + /* + * last buffer must not be freed to ensure proper hardware + * function. When the hardware finishes also a packet next to + * it, we are sure, it doesn't use it anymore and we can go on. + */ + if (bf_last == bf) + bf->flags |= 1; + if (bf->flags) { + struct ath5k_buf *bf_next = list_entry(bf->list.next, + struct ath5k_buf, list); + ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc, + &rs); + if (ret) + break; + bf->flags &= ~1; + /* skip the overwritten one (even status is martian) */ + goto next; + } + + ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs); + if (ret) { + if (ret != -EINPROGRESS) { + DBG("ath5k: error in processing rx desc: %s\n", + strerror(ret)); + net80211_rx_err(sc->dev, NULL, -ret); + } else { + /* normal return, reached end of + available descriptors */ + } + return; + } + + if (rs.rs_more) { + DBG("ath5k: unsupported fragmented rx\n"); + goto next; + } + + if (rs.rs_status) { + if (rs.rs_status & AR5K_RXERR_PHY) { + DBG("ath5k: rx PHY error\n"); + goto next; + } + if (rs.rs_status & AR5K_RXERR_CRC) { + net80211_rx_err(sc->dev, NULL, EIO); + goto next; + } + if (rs.rs_status & AR5K_RXERR_DECRYPT) { + /* + * Decrypt error. If the error occurred + * because there was no hardware key, then + * let the frame through so the upper layers + * can process it. This is necessary for 5210 + * parts which have no way to setup a ``clear'' + * key cache entry. + * + * XXX do key cache faulting + */ + if (rs.rs_keyix == AR5K_RXKEYIX_INVALID && + !(rs.rs_status & AR5K_RXERR_CRC)) + goto accept; + } + + /* any other error, unhandled */ + DBG("ath5k: packet rx status %x\n", rs.rs_status); + goto next; + } +accept: + next_iob = ath5k_rx_iob_alloc(sc, &next_iob_addr); + + /* + * If we can't replace bf->iob with a new iob under memory + * pressure, just skip this packet + */ + if (!next_iob) { + DBG("ath5k: dropping packet under memory pressure\n"); + goto next; + } + + iob_put(iob, rs.rs_datalen); + + /* The MAC header is padded to have 32-bit boundary if the + * packet payload is non-zero. However, gPXE only + * supports standard 802.11 packets with 24-byte + * header, so no padding correction should be needed. + */ + + DBG2("ath5k: rx %d bytes, signal %d\n", rs.rs_datalen, + rs.rs_rssi); + + net80211_rx(sc->dev, iob, rs.rs_rssi, + ath5k_hw_rix_to_bitrate(rs.rs_rate)); + + bf->iob = next_iob; + bf->iobaddr = next_iob_addr; +next: + list_del(&bf->list); + list_add_tail(&bf->list, &sc->rxbuf); + } while (ath5k_rxbuf_setup(sc, bf) == 0); +} + + + + +/*************\ +* TX Handling * +\*************/ + +static void +ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) +{ + struct ath5k_tx_status ts; + struct ath5k_buf *bf, *bf0; + struct ath5k_desc *ds; + struct io_buffer *iob; + int ret; + + memset(&ts, 0, sizeof(ts)); + + list_for_each_entry_safe(bf, bf0, &txq->q, list) { + ds = bf->desc; + + ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts); + if (ret) { + if (ret != -EINPROGRESS) { + DBG("ath5k: error in processing tx desc: %s\n", + strerror(ret)); + } else { + /* normal return, reached end of tx completions */ + } + break; + } + + iob = bf->iob; + bf->iob = NULL; + + DBG2("ath5k: tx %d bytes complete, %d retries\n", + iob_len(iob), ts.ts_retry[0]); + + net80211_tx_complete(sc->dev, iob, ts.ts_retry[0], + ts.ts_status ? EIO : 0); + + list_del(&bf->list); + list_add_tail(&bf->list, &sc->txbuf); + sc->txbuf_len++; + } + + if (list_empty(&txq->q)) + txq->link = NULL; +} + +static void +ath5k_handle_tx(struct ath5k_softc *sc) +{ + ath5k_tx_processq(sc, &sc->txq); +} + + +/********************\ +* Interrupt handling * +\********************/ + +static void +ath5k_irq(struct net80211_device *dev, int enable) +{ + struct ath5k_softc *sc = dev->priv; + struct ath5k_hw *ah = sc->ah; + + sc->irq_ena = enable; + ah->ah_ier = enable ? AR5K_IER_ENABLE : AR5K_IER_DISABLE; + + ath5k_hw_reg_write(ah, ah->ah_ier, AR5K_IER); + ath5k_hw_set_imr(ah, sc->imask); +} + +static int +ath5k_init(struct ath5k_softc *sc) +{ + struct ath5k_hw *ah = sc->ah; + int ret, i; + + /* + * Stop anything previously setup. This is safe + * no matter this is the first time through or not. + */ + ath5k_stop_hw(sc); + + /* + * The basic interface to setting the hardware in a good + * state is ``reset''. On return the hardware is known to + * be powered up and with interrupts disabled. This must + * be followed by initialization of the appropriate bits + * and then setup of the interrupt mask. + */ + sc->curchan = sc->dev->channels + sc->dev->channel; + sc->curband = sc->curchan->band; + sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL | + AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL | + AR5K_INT_FATAL | AR5K_INT_GLOBAL; + ret = ath5k_reset(sc, NULL); + if (ret) + goto done; + + /* + * Reset the key cache since some parts do not reset the + * contents on initial power up or resume from suspend. + */ + for (i = 0; i < AR5K_KEYTABLE_SIZE; i++) + ath5k_hw_reset_key(ah, i); + + /* Set ack to be sent at low bit-rates */ + ath5k_hw_set_ack_bitrate_high(ah, 0); + + ret = 0; +done: + mb(); + return ret; +} + +static int +ath5k_stop_hw(struct ath5k_softc *sc) +{ + struct ath5k_hw *ah = sc->ah; + + /* + * Shutdown the hardware and driver: + * stop output from above + * disable interrupts + * turn off timers + * turn off the radio + * clear transmit machinery + * clear receive machinery + * drain and release tx queues + * reclaim beacon resources + * power down hardware + * + * Note that some of this work is not possible if the + * hardware is gone (invalid). + */ + + if (!(sc->status & ATH_STAT_INVALID)) { + ath5k_hw_set_imr(ah, 0); + } + ath5k_txq_cleanup(sc); + if (!(sc->status & ATH_STAT_INVALID)) { + ath5k_rx_stop(sc); + ath5k_hw_phy_disable(ah); + } else + sc->rxlink = NULL; + + return 0; +} + +static void +ath5k_poll(struct net80211_device *dev) +{ + struct ath5k_softc *sc = dev->priv; + struct ath5k_hw *ah = sc->ah; + enum ath5k_int status; + unsigned int counter = 1000; + + if (currticks() - sc->last_calib_ticks > + ATH5K_CALIB_INTERVAL * ticks_per_sec()) { + ath5k_calibrate(sc); + sc->last_calib_ticks = currticks(); + } + + if ((sc->status & ATH_STAT_INVALID) || + (sc->irq_ena && !ath5k_hw_is_intr_pending(ah))) + return; + + do { + ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ + DBGP("ath5k: status %#x/%#x\n", status, sc->imask); + if (status & AR5K_INT_FATAL) { + /* + * Fatal errors are unrecoverable. + * Typically these are caused by DMA errors. + */ + DBG("ath5k: fatal error, resetting\n"); + ath5k_reset_wake(sc); + } else if (status & AR5K_INT_RXORN) { + DBG("ath5k: rx overrun, resetting\n"); + ath5k_reset_wake(sc); + } else { + if (status & AR5K_INT_RXEOL) { + /* + * NB: the hardware should re-read the link when + * RXE bit is written, but it doesn't work at + * least on older hardware revs. + */ + DBG("ath5k: rx EOL\n"); + sc->rxlink = NULL; + } + if (status & AR5K_INT_TXURN) { + /* bump tx trigger level */ + DBG("ath5k: tx underrun\n"); + ath5k_hw_update_tx_triglevel(ah, 1); + } + if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) + ath5k_handle_rx(sc); + if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC + | AR5K_INT_TXERR | AR5K_INT_TXEOL)) + ath5k_handle_tx(sc); + } + } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0); + + if (!counter) + DBG("ath5k: too many interrupts, giving up for now\n"); +} + +/* + * Periodically recalibrate the PHY to account + * for temperature/environment changes. + */ +static void +ath5k_calibrate(struct ath5k_softc *sc) +{ + struct ath5k_hw *ah = sc->ah; + + if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { + /* + * Rfgain is out of bounds, reset the chip + * to load new gain values. + */ + DBG("ath5k: resetting for calibration\n"); + ath5k_reset_wake(sc); + } + if (ath5k_hw_phy_calibrate(ah, sc->curchan)) + DBG("ath5k: calibration of channel %d failed\n", + sc->curchan->channel_nr); +} + + +/********************\ +* Net80211 functions * +\********************/ + +static int +ath5k_tx(struct net80211_device *dev, struct io_buffer *iob) +{ + struct ath5k_softc *sc = dev->priv; + struct ath5k_buf *bf; + int rc; + + /* + * The hardware expects the header padded to 4 byte boundaries. + * gPXE only ever sends 24-byte headers, so no action necessary. + */ + + if (list_empty(&sc->txbuf)) { + DBG("ath5k: dropping packet because no tx bufs available\n"); + return -ENOBUFS; + } + + bf = list_entry(sc->txbuf.next, struct ath5k_buf, list); + list_del(&bf->list); + sc->txbuf_len--; + + bf->iob = iob; + + if ((rc = ath5k_txbuf_setup(sc, bf)) != 0) { + bf->iob = NULL; + list_add_tail(&bf->list, &sc->txbuf); + sc->txbuf_len++; + return rc; + } + return 0; +} + +/* + * Reset the hardware. If chan is not NULL, then also pause rx/tx + * and change to the given channel. + */ +static int +ath5k_reset(struct ath5k_softc *sc, struct net80211_channel *chan) +{ + struct ath5k_hw *ah = sc->ah; + int ret; + + if (chan) { + ath5k_hw_set_imr(ah, 0); + ath5k_txq_cleanup(sc); + ath5k_rx_stop(sc); + + sc->curchan = chan; + sc->curband = chan->band; + } + + ret = ath5k_hw_reset(ah, sc->curchan, 1); + if (ret) { + DBG("ath5k: can't reset hardware: %s\n", strerror(ret)); + return ret; + } + + ret = ath5k_rx_start(sc); + if (ret) { + DBG("ath5k: can't start rx logic: %s\n", strerror(ret)); + return ret; + } + + /* + * Change channels and update the h/w rate map if we're switching; + * e.g. 11a to 11b/g. + * + * We may be doing a reset in response to an ioctl that changes the + * channel so update any state that might change as a result. + * + * XXX needed? + */ +/* ath5k_chan_change(sc, c); */ + + /* Reenable interrupts if necessary */ + ath5k_irq(sc->dev, sc->irq_ena); + + return 0; +} + +static int ath5k_reset_wake(struct ath5k_softc *sc) +{ + return ath5k_reset(sc, sc->curchan); +} + +static int ath5k_start(struct net80211_device *dev) +{ + struct ath5k_softc *sc = dev->priv; + int ret; + + if ((ret = ath5k_init(sc)) != 0) + return ret; + + sc->assoc = 0; + ath5k_configure_filter(sc); + ath5k_hw_set_lladdr(sc->ah, dev->netdev->ll_addr); + + return 0; +} + +static void ath5k_stop(struct net80211_device *dev) +{ + struct ath5k_softc *sc = dev->priv; + u8 mac[ETH_ALEN] = {}; + + ath5k_hw_set_lladdr(sc->ah, mac); + + ath5k_stop_hw(sc); +} + +static int +ath5k_config(struct net80211_device *dev, int changed) +{ + struct ath5k_softc *sc = dev->priv; + struct ath5k_hw *ah = sc->ah; + struct net80211_channel *chan = &dev->channels[dev->channel]; + int ret; + + if (changed & NET80211_CFG_CHANNEL) { + sc->power_level = chan->maxpower; + if ((ret = ath5k_chan_set(sc, chan)) != 0) + return ret; + } + + if ((changed & NET80211_CFG_RATE) || + (changed & NET80211_CFG_PHY_PARAMS)) { + int spmbl = ATH5K_SPMBL_NO; + u16 rate = dev->rates[dev->rate]; + u16 slowrate = dev->rates[dev->rtscts_rate]; + int i; + + if (dev->phy_flags & NET80211_PHY_USE_SHORT_PREAMBLE) + spmbl = ATH5K_SPMBL_YES; + + for (i = 0; i < ATH5K_NR_RATES; i++) { + if (ath5k_rates[i].bitrate == rate && + (ath5k_rates[i].short_pmbl & spmbl)) + sc->hw_rate = ath5k_rates[i].hw_code; + + if (ath5k_rates[i].bitrate == slowrate && + (ath5k_rates[i].short_pmbl & spmbl)) + sc->hw_rtscts_rate = ath5k_rates[i].hw_code; + } + } + + if (changed & NET80211_CFG_ASSOC) { + sc->assoc = !!(dev->state & NET80211_ASSOCIATED); + if (sc->assoc) { + memcpy(ah->ah_bssid, dev->bssid, ETH_ALEN); + } else { + memset(ah->ah_bssid, 0xff, ETH_ALEN); + } + ath5k_hw_set_associd(ah, ah->ah_bssid, 0); + } + + return 0; +} + +/* + * o always accept unicast, broadcast, and multicast traffic + * o multicast traffic for all BSSIDs will be enabled if mac80211 + * says it should be + * o maintain current state of phy ofdm or phy cck error reception. + * If the hardware detects any of these type of errors then + * ath5k_hw_get_rx_filter() will pass to us the respective + * hardware filters to be able to receive these type of frames. + * o probe request frames are accepted only when operating in + * hostap, adhoc, or monitor modes + * o enable promiscuous mode according to the interface state + * o accept beacons: + * - when operating in adhoc mode so the 802.11 layer creates + * node table entries for peers, + * - when operating in station mode for collecting rssi data when + * the station is otherwise quiet, or + * - when scanning + */ +static void ath5k_configure_filter(struct ath5k_softc *sc) +{ + struct ath5k_hw *ah = sc->ah; + u32 mfilt[2], rfilt; + + /* Enable all multicast */ + mfilt[0] = ~0; + mfilt[1] = ~0; + + /* Enable data frames and beacons */ + rfilt = (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | + AR5K_RX_FILTER_MCAST | AR5K_RX_FILTER_BEACON); + + /* Set filters */ + ath5k_hw_set_rx_filter(ah, rfilt); + + /* Set multicast bits */ + ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]); + + /* Set the cached hw filter flags, this will alter actually + * be set in HW */ + sc->filter_flags = rfilt; +} diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k.h new file mode 100644 index 0000000..c79fbec --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k.h @@ -0,0 +1,1275 @@ +/* + * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> + * + * Modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net> + * Original from Linux kernel 2.6.30. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _ATH5K_H +#define _ATH5K_H + +FILE_LICENCE ( MIT ); + +#include <stddef.h> +#include <byteswap.h> +#include <gpxe/io.h> +#include <gpxe/netdevice.h> +#include <gpxe/net80211.h> +#include <errno.h> + +/* Keep all ath5k files under one errfile ID */ +#undef ERRFILE +#define ERRFILE ERRFILE_ath5k + +#define ARRAY_SIZE(a) (sizeof(a)/sizeof((a)[0])) + +/* RX/TX descriptor hw structs */ +#include "desc.h" + +/* EEPROM structs/offsets */ +#include "eeprom.h" + +/* PCI IDs */ +#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ +#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ +#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ +#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ +#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ +#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ +#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ +#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ +#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ +#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ +#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ +#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ +#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ +#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ +#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ +#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ + +/****************************\ + GENERIC DRIVER DEFINITIONS +\****************************/ + +/* + * AR5K REGISTER ACCESS + */ + +/* Some macros to read/write fields */ + +/* First shift, then mask */ +#define AR5K_REG_SM(_val, _flags) \ + (((_val) << _flags##_S) & (_flags)) + +/* First mask, then shift */ +#define AR5K_REG_MS(_val, _flags) \ + (((_val) & (_flags)) >> _flags##_S) + +/* Some registers can hold multiple values of interest. For this + * reason when we want to write to these registers we must first + * retrieve the values which we do not want to clear (lets call this + * old_data) and then set the register with this and our new_value: + * ( old_data | new_value) */ +#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ + ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ + (((_val) << _flags##_S) & (_flags)), _reg) + +#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ + ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ + (_mask)) | (_flags), _reg) + +#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ + ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) + +#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ + ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) + +/* Access to PHY registers */ +#define AR5K_PHY_READ(ah, _reg) \ + ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) + +#define AR5K_PHY_WRITE(ah, _reg, _val) \ + ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) + +/* Access QCU registers per queue */ +#define AR5K_REG_READ_Q(ah, _reg, _queue) \ + (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ + +#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ + ath5k_hw_reg_write(ah, (1 << _queue), _reg) + +#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ + _reg |= 1 << _queue; \ +} while (0) + +#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ + _reg &= ~(1 << _queue); \ +} while (0) + +/* Used while writing initvals */ +#define AR5K_REG_WAIT(_i) do { \ + if (_i % 64) \ + udelay(1); \ +} while (0) + +/* Register dumps are done per operation mode */ +#define AR5K_INI_RFGAIN_5GHZ 0 +#define AR5K_INI_RFGAIN_2GHZ 1 + +/* TODO: Clean this up */ +#define AR5K_INI_VAL_11A 0 +#define AR5K_INI_VAL_11A_TURBO 1 +#define AR5K_INI_VAL_11B 2 +#define AR5K_INI_VAL_11G 3 +#define AR5K_INI_VAL_11G_TURBO 4 +#define AR5K_INI_VAL_XR 0 +#define AR5K_INI_VAL_MAX 5 + +/* Used for BSSID etc manipulation */ +#define AR5K_LOW_ID(_a)( \ +(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \ +) + +#define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8) + +#define IEEE80211_MAX_LEN 2352 + +/* + * Some tuneable values (these should be changeable by the user) + */ +#define AR5K_TUNE_DMA_BEACON_RESP 2 +#define AR5K_TUNE_SW_BEACON_RESP 10 +#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 +#define AR5K_TUNE_RADAR_ALERT 0 +#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 +#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1) +#define AR5K_TUNE_REGISTER_TIMEOUT 20000 +/* Register for RSSI threshold has a mask of 0xff, so 255 seems to + * be the max value. */ +#define AR5K_TUNE_RSSI_THRES 129 +/* This must be set when setting the RSSI threshold otherwise it can + * prevent a reset. If AR5K_RSSI_THR is read after writing to it + * the BMISS_THRES will be seen as 0, seems harware doesn't keep + * track of it. Max value depends on harware. For AR5210 this is just 7. + * For AR5211+ this seems to be up to 255. */ +#define AR5K_TUNE_BMISS_THRES 7 +#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 +#define AR5K_TUNE_BEACON_INTERVAL 100 +#define AR5K_TUNE_AIFS 2 +#define AR5K_TUNE_AIFS_11B 2 +#define AR5K_TUNE_AIFS_XR 0 +#define AR5K_TUNE_CWMIN 15 +#define AR5K_TUNE_CWMIN_11B 31 +#define AR5K_TUNE_CWMIN_XR 3 +#define AR5K_TUNE_CWMAX 1023 +#define AR5K_TUNE_CWMAX_11B 1023 +#define AR5K_TUNE_CWMAX_XR 7 +#define AR5K_TUNE_NOISE_FLOOR -72 +#define AR5K_TUNE_MAX_TXPOWER 63 +#define AR5K_TUNE_DEFAULT_TXPOWER 25 +#define AR5K_TUNE_TPC_TXPOWER 0 +#define AR5K_TUNE_ANT_DIVERSITY 1 +#define AR5K_TUNE_HWTXTRIES 4 + +#define AR5K_INIT_CARR_SENSE_EN 1 + +/*Swap RX/TX Descriptor for big endian archs*/ +#if __BYTE_ORDER == __BIG_ENDIAN +#define AR5K_INIT_CFG ( \ + AR5K_CFG_SWTD | AR5K_CFG_SWRD \ +) +#else +#define AR5K_INIT_CFG 0x00000000 +#endif + +/* Initial values */ +#define AR5K_INIT_CYCRSSI_THR1 2 +#define AR5K_INIT_TX_LATENCY 502 +#define AR5K_INIT_USEC 39 +#define AR5K_INIT_USEC_TURBO 79 +#define AR5K_INIT_USEC_32 31 +#define AR5K_INIT_SLOT_TIME 396 +#define AR5K_INIT_SLOT_TIME_TURBO 480 +#define AR5K_INIT_ACK_CTS_TIMEOUT 1024 +#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 +#define AR5K_INIT_PROG_IFS 920 +#define AR5K_INIT_PROG_IFS_TURBO 960 +#define AR5K_INIT_EIFS 3440 +#define AR5K_INIT_EIFS_TURBO 6880 +#define AR5K_INIT_SIFS 560 +#define AR5K_INIT_SIFS_TURBO 480 +#define AR5K_INIT_SH_RETRY 10 +#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY +#define AR5K_INIT_SSH_RETRY 32 +#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY +#define AR5K_INIT_TX_RETRY 10 + +#define AR5K_INIT_TRANSMIT_LATENCY ( \ + (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ + (AR5K_INIT_USEC) \ +) +#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \ + (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ + (AR5K_INIT_USEC_TURBO) \ +) +#define AR5K_INIT_PROTO_TIME_CNTRL ( \ + (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ + (AR5K_INIT_PROG_IFS) \ +) +#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ + (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \ + (AR5K_INIT_PROG_IFS_TURBO) \ +) + +/* token to use for aifs, cwmin, cwmax in MadWiFi */ +#define AR5K_TXQ_USEDEFAULT ((u32) -1) + +/* GENERIC CHIPSET DEFINITIONS */ + +/* MAC Chips */ +enum ath5k_version { + AR5K_AR5210 = 0, + AR5K_AR5211 = 1, + AR5K_AR5212 = 2, +}; + +/* PHY Chips */ +enum ath5k_radio { + AR5K_RF5110 = 0, + AR5K_RF5111 = 1, + AR5K_RF5112 = 2, + AR5K_RF2413 = 3, + AR5K_RF5413 = 4, + AR5K_RF2316 = 5, + AR5K_RF2317 = 6, + AR5K_RF2425 = 7, +}; + +/* + * Common silicon revision/version values + */ + +enum ath5k_srev_type { + AR5K_VERSION_MAC, + AR5K_VERSION_RAD, +}; + +struct ath5k_srev_name { + const char *sr_name; + enum ath5k_srev_type sr_type; + unsigned sr_val; +}; + +#define AR5K_SREV_UNKNOWN 0xffff + +#define AR5K_SREV_AR5210 0x00 /* Crete */ +#define AR5K_SREV_AR5311 0x10 /* Maui 1 */ +#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */ +#define AR5K_SREV_AR5311B 0x30 /* Spirit */ +#define AR5K_SREV_AR5211 0x40 /* Oahu */ +#define AR5K_SREV_AR5212 0x50 /* Venice */ +#define AR5K_SREV_AR5213 0x55 /* ??? */ +#define AR5K_SREV_AR5213A 0x59 /* Hainan */ +#define AR5K_SREV_AR2413 0x78 /* Griffin lite */ +#define AR5K_SREV_AR2414 0x70 /* Griffin */ +#define AR5K_SREV_AR5424 0x90 /* Condor */ +#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */ +#define AR5K_SREV_AR5414 0xa0 /* Eagle */ +#define AR5K_SREV_AR2415 0xb0 /* Talon */ +#define AR5K_SREV_AR5416 0xc0 /* PCI-E */ +#define AR5K_SREV_AR5418 0xca /* PCI-E */ +#define AR5K_SREV_AR2425 0xe0 /* Swan */ +#define AR5K_SREV_AR2417 0xf0 /* Nala */ + +#define AR5K_SREV_RAD_5110 0x00 +#define AR5K_SREV_RAD_5111 0x10 +#define AR5K_SREV_RAD_5111A 0x15 +#define AR5K_SREV_RAD_2111 0x20 +#define AR5K_SREV_RAD_5112 0x30 +#define AR5K_SREV_RAD_5112A 0x35 +#define AR5K_SREV_RAD_5112B 0x36 +#define AR5K_SREV_RAD_2112 0x40 +#define AR5K_SREV_RAD_2112A 0x45 +#define AR5K_SREV_RAD_2112B 0x46 +#define AR5K_SREV_RAD_2413 0x50 +#define AR5K_SREV_RAD_5413 0x60 +#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */ +#define AR5K_SREV_RAD_2317 0x80 +#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */ +#define AR5K_SREV_RAD_2425 0xa2 +#define AR5K_SREV_RAD_5133 0xc0 + +#define AR5K_SREV_PHY_5211 0x30 +#define AR5K_SREV_PHY_5212 0x41 +#define AR5K_SREV_PHY_5212A 0x42 +#define AR5K_SREV_PHY_5212B 0x43 +#define AR5K_SREV_PHY_2413 0x45 +#define AR5K_SREV_PHY_5413 0x61 +#define AR5K_SREV_PHY_2425 0x70 + +/* + * Some of this information is based on Documentation from: + * + * http://madwifi.org/wiki/ChipsetFeatures/SuperAG + * + * Modulation for Atheros' eXtended Range - range enhancing extension that is + * supposed to double the distance an Atheros client device can keep a + * connection with an Atheros access point. This is achieved by increasing + * the receiver sensitivity up to, -105dBm, which is about 20dB above what + * the 802.11 specifications demand. In addition, new (proprietary) data rates + * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s. + * + * Please note that can you either use XR or TURBO but you cannot use both, + * they are exclusive. + * + */ +#define MODULATION_XR 0x00000200 + +/* + * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a + * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s + * signaling rate achieved through the bonding of two 54Mbit/s 802.11g + * channels. To use this feature your Access Point must also suport it. + * There is also a distinction between "static" and "dynamic" turbo modes: + * + * - Static: is the dumb version: devices set to this mode stick to it until + * the mode is turned off. + * - Dynamic: is the intelligent version, the network decides itself if it + * is ok to use turbo. As soon as traffic is detected on adjacent channels + * (which would get used in turbo mode), or when a non-turbo station joins + * the network, turbo mode won't be used until the situation changes again. + * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which + * monitors the used radio band in order to decide whether turbo mode may + * be used or not. + * + * This article claims Super G sticks to bonding of channels 5 and 6 for + * USA: + * + * http://www.pcworld.com/article/id,113428-page,1/article.html + * + * The channel bonding seems to be driver specific though. In addition to + * deciding what channels will be used, these "Turbo" modes are accomplished + * by also enabling the following features: + * + * - Bursting: allows multiple frames to be sent at once, rather than pausing + * after each frame. Bursting is a standards-compliant feature that can be + * used with any Access Point. + * - Fast frames: increases the amount of information that can be sent per + * frame, also resulting in a reduction of transmission overhead. It is a + * proprietary feature that needs to be supported by the Access Point. + * - Compression: data frames are compressed in real time using a Lempel Ziv + * algorithm. This is done transparently. Once this feature is enabled, + * compression and decompression takes place inside the chipset, without + * putting additional load on the host CPU. + * + */ +#define MODULATION_TURBO 0x00000080 + +enum ath5k_driver_mode { + AR5K_MODE_11A = 0, + AR5K_MODE_11A_TURBO = 1, + AR5K_MODE_11B = 2, + AR5K_MODE_11G = 3, + AR5K_MODE_11G_TURBO = 4, + AR5K_MODE_XR = 5, +}; + +enum { + AR5K_MODE_BIT_11A = (1 << AR5K_MODE_11A), + AR5K_MODE_BIT_11A_TURBO = (1 << AR5K_MODE_11A_TURBO), + AR5K_MODE_BIT_11B = (1 << AR5K_MODE_11B), + AR5K_MODE_BIT_11G = (1 << AR5K_MODE_11G), + AR5K_MODE_BIT_11G_TURBO = (1 << AR5K_MODE_11G_TURBO), + AR5K_MODE_BIT_XR = (1 << AR5K_MODE_XR), +}; + +/****************\ + TX DEFINITIONS +\****************/ + +/* + * TX Status descriptor + */ +struct ath5k_tx_status { + u16 ts_seqnum; + u16 ts_tstamp; + u8 ts_status; + u8 ts_rate[4]; + u8 ts_retry[4]; + u8 ts_final_idx; + s8 ts_rssi; + u8 ts_shortretry; + u8 ts_longretry; + u8 ts_virtcol; + u8 ts_antenna; +} __attribute__ ((packed)); + +#define AR5K_TXSTAT_ALTRATE 0x80 +#define AR5K_TXERR_XRETRY 0x01 +#define AR5K_TXERR_FILT 0x02 +#define AR5K_TXERR_FIFO 0x04 + +/** + * enum ath5k_tx_queue - Queue types used to classify tx queues. + * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue + * @AR5K_TX_QUEUE_DATA: A normal data queue + * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue + * @AR5K_TX_QUEUE_BEACON: The beacon queue + * @AR5K_TX_QUEUE_CAB: The after-beacon queue + * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue + */ +enum ath5k_tx_queue { + AR5K_TX_QUEUE_INACTIVE = 0, + AR5K_TX_QUEUE_DATA, + AR5K_TX_QUEUE_XR_DATA, + AR5K_TX_QUEUE_BEACON, + AR5K_TX_QUEUE_CAB, + AR5K_TX_QUEUE_UAPSD, +}; + +/* + * Queue syb-types to classify normal data queues. + * These are the 4 Access Categories as defined in + * WME spec. 0 is the lowest priority and 4 is the + * highest. Normal data that hasn't been classified + * goes to the Best Effort AC. + */ +enum ath5k_tx_queue_subtype { + AR5K_WME_AC_BK = 0, /*Background traffic*/ + AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ + AR5K_WME_AC_VI, /*Video traffic*/ + AR5K_WME_AC_VO, /*Voice traffic*/ +}; + +/* + * Queue ID numbers as returned by the hw functions, each number + * represents a hw queue. If hw does not support hw queues + * (eg 5210) all data goes in one queue. These match + * d80211 definitions (net80211/MadWiFi don't use them). + */ +enum ath5k_tx_queue_id { + AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, + AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, + AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ + AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ + AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ + AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ + AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ + AR5K_TX_QUEUE_ID_UAPSD = 8, + AR5K_TX_QUEUE_ID_XR_DATA = 9, +}; + +/* + * Flags to set hw queue's parameters... + */ +#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */ +#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */ +#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */ +#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */ +#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */ +#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */ +#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */ +#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */ +#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */ +#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */ +#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/ +#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */ +#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ +#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ + +/* + * A struct to hold tx queue's parameters + */ +struct ath5k_txq_info { + enum ath5k_tx_queue tqi_type; + enum ath5k_tx_queue_subtype tqi_subtype; + u16 tqi_flags; /* Tx queue flags (see above) */ + u32 tqi_aifs; /* Arbitrated Interframe Space */ + s32 tqi_cw_min; /* Minimum Contention Window */ + s32 tqi_cw_max; /* Maximum Contention Window */ + u32 tqi_cbr_period; /* Constant bit rate period */ + u32 tqi_cbr_overflow_limit; + u32 tqi_burst_time; + u32 tqi_ready_time; /* Not used */ +}; + +/* + * Transmit packet types. + * used on tx control descriptor + * TODO: Use them inside base.c corectly + */ +enum ath5k_pkt_type { + AR5K_PKT_TYPE_NORMAL = 0, + AR5K_PKT_TYPE_ATIM = 1, + AR5K_PKT_TYPE_PSPOLL = 2, + AR5K_PKT_TYPE_BEACON = 3, + AR5K_PKT_TYPE_PROBE_RESP = 4, + AR5K_PKT_TYPE_PIFS = 5, +}; + +/* + * TX power and TPC settings + */ +#define AR5K_TXPOWER_OFDM(_r, _v) ( \ + ((0 & 1) << ((_v) + 6)) | \ + (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \ +) + +#define AR5K_TXPOWER_CCK(_r, _v) ( \ + (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \ +) + +/* + * DMA size definitions (2^n+2) + */ +enum ath5k_dmasize { + AR5K_DMASIZE_4B = 0, + AR5K_DMASIZE_8B, + AR5K_DMASIZE_16B, + AR5K_DMASIZE_32B, + AR5K_DMASIZE_64B, + AR5K_DMASIZE_128B, + AR5K_DMASIZE_256B, + AR5K_DMASIZE_512B +}; + + +/****************\ + RX DEFINITIONS +\****************/ + +/* + * RX Status descriptor + */ +struct ath5k_rx_status { + u16 rs_datalen; + u16 rs_tstamp; + u8 rs_status; + u8 rs_phyerr; + s8 rs_rssi; + u8 rs_keyix; + u8 rs_rate; + u8 rs_antenna; + u8 rs_more; +}; + +#define AR5K_RXERR_CRC 0x01 +#define AR5K_RXERR_PHY 0x02 +#define AR5K_RXERR_FIFO 0x04 +#define AR5K_RXERR_DECRYPT 0x08 +#define AR5K_RXERR_MIC 0x10 +#define AR5K_RXKEYIX_INVALID ((u8) - 1) +#define AR5K_TXKEYIX_INVALID ((u32) - 1) + + +/* + * TSF to TU conversion: + * + * TSF is a 64bit value in usec (microseconds). + * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of + * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024). + */ +#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) + + +/*******************************\ + GAIN OPTIMIZATION DEFINITIONS +\*******************************/ + +enum ath5k_rfgain { + AR5K_RFGAIN_INACTIVE = 0, + AR5K_RFGAIN_ACTIVE, + AR5K_RFGAIN_READ_REQUESTED, + AR5K_RFGAIN_NEED_CHANGE, +}; + +struct ath5k_gain { + u8 g_step_idx; + u8 g_current; + u8 g_target; + u8 g_low; + u8 g_high; + u8 g_f_corr; + u8 g_state; +}; + +/********************\ + COMMON DEFINITIONS +\********************/ + +#define AR5K_SLOT_TIME_9 396 +#define AR5K_SLOT_TIME_20 880 +#define AR5K_SLOT_TIME_MAX 0xffff + +/* channel_flags */ +#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ +#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ +#define CHANNEL_CCK 0x0020 /* CCK channel */ +#define CHANNEL_OFDM 0x0040 /* OFDM channel */ +#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ +#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ +#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ +#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ +#define CHANNEL_XR 0x0800 /* XR channel */ + +#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) +#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) +#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) +#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_108A CHANNEL_T +#define CHANNEL_108G CHANNEL_TG +#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) + +#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \ + CHANNEL_TURBO) + +#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO) +#define CHANNEL_MODES CHANNEL_ALL + +/* + * Used internaly for reset_tx_queue). + * Also see struct struct net80211_channel. + */ +#define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0) +#define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0) + +/* + * The following structure is used to map 2GHz channels to + * 5GHz Atheros channels. + * TODO: Clean up + */ +struct ath5k_athchan_2ghz { + u32 a2_flags; + u16 a2_athchan; +}; + + +/******************\ + RATE DEFINITIONS +\******************/ + +/** + * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32. + * + * The rate code is used to get the RX rate or set the TX rate on the + * hardware descriptors. It is also used for internal modulation control + * and settings. + * + * This is the hardware rate map we are aware of: + * + * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 + * rate_kbps 3000 1000 ? ? ? 2000 500 48000 + * + * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 + * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ? + * + * rate_code 17 18 19 20 21 22 23 24 + * rate_kbps ? ? ? ? ? ? ? 11000 + * + * rate_code 25 26 27 28 29 30 31 32 + * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ? + * + * "S" indicates CCK rates with short preamble. + * + * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the + * lowest 4 bits, so they are the same as below with a 0xF mask. + * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). + * We handle this in ath5k_setup_bands(). + */ +#define AR5K_MAX_RATES 32 + +/* B */ +#define ATH5K_RATE_CODE_1M 0x1B +#define ATH5K_RATE_CODE_2M 0x1A +#define ATH5K_RATE_CODE_5_5M 0x19 +#define ATH5K_RATE_CODE_11M 0x18 +/* A and G */ +#define ATH5K_RATE_CODE_6M 0x0B +#define ATH5K_RATE_CODE_9M 0x0F +#define ATH5K_RATE_CODE_12M 0x0A +#define ATH5K_RATE_CODE_18M 0x0E +#define ATH5K_RATE_CODE_24M 0x09 +#define ATH5K_RATE_CODE_36M 0x0D +#define ATH5K_RATE_CODE_48M 0x08 +#define ATH5K_RATE_CODE_54M 0x0C +/* XR */ +#define ATH5K_RATE_CODE_XR_500K 0x07 +#define ATH5K_RATE_CODE_XR_1M 0x02 +#define ATH5K_RATE_CODE_XR_2M 0x06 +#define ATH5K_RATE_CODE_XR_3M 0x01 + +/* adding this flag to rate_code enables short preamble */ +#define AR5K_SET_SHORT_PREAMBLE 0x04 + +/* + * Crypto definitions + */ + +#define AR5K_KEYCACHE_SIZE 8 + +/***********************\ + HW RELATED DEFINITIONS +\***********************/ + +/* + * Misc definitions + */ +#define AR5K_RSSI_EP_MULTIPLIER (1<<7) + +#define AR5K_ASSERT_ENTRY(_e, _s) do { \ + if (_e >= _s) \ + return 0; \ +} while (0) + +/* + * Hardware interrupt abstraction + */ + +/** + * enum ath5k_int - Hardware interrupt masks helpers + * + * @AR5K_INT_RX: mask to identify received frame interrupts, of type + * AR5K_ISR_RXOK or AR5K_ISR_RXERR + * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) + * @AR5K_INT_RXNOFRM: No frame received (?) + * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The + * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's + * LinkPtr is NULL. For more details, refer to: + * http://www.freepatentsonline.com/20030225739.html + * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). + * Note that Rx overrun is not always fatal, on some chips we can continue + * operation without reseting the card, that's why int_fatal is not + * common for all chips. + * @AR5K_INT_TX: mask to identify received frame interrupts, of type + * AR5K_ISR_TXOK or AR5K_ISR_TXERR + * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) + * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold + * We currently do increments on interrupt by + * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 + * @AR5K_INT_MIB: Indicates the Management Information Base counters should be + * checked. We should do this with ath5k_hw_update_mib_counters() but + * it seems we should also then do some noise immunity work. + * @AR5K_INT_RXPHY: RX PHY Error + * @AR5K_INT_RXKCM: RX Key cache miss + * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a + * beacon that must be handled in software. The alternative is if you + * have VEOL support, in that case you let the hardware deal with things. + * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing + * beacons from the AP have associated with, we should probably try to + * reassociate. When in IBSS mode this might mean we have not received + * any beacons from any local stations. Note that every station in an + * IBSS schedules to send beacons at the Target Beacon Transmission Time + * (TBTT) with a random backoff. + * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? + * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now + * until properly handled + * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA + * errors. These types of errors we can enable seem to be of type + * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. + * @AR5K_INT_GLOBAL: Used to clear and set the IER + * @AR5K_INT_NOCARD: signals the card has been removed + * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same + * bit value + * + * These are mapped to take advantage of some common bits + * between the MACs, to be able to set intr properties + * easier. Some of them are not used yet inside hw.c. Most map + * to the respective hw interrupt value as they are common amogst different + * MACs. + */ +enum ath5k_int { + AR5K_INT_RXOK = 0x00000001, + AR5K_INT_RXDESC = 0x00000002, + AR5K_INT_RXERR = 0x00000004, + AR5K_INT_RXNOFRM = 0x00000008, + AR5K_INT_RXEOL = 0x00000010, + AR5K_INT_RXORN = 0x00000020, + AR5K_INT_TXOK = 0x00000040, + AR5K_INT_TXDESC = 0x00000080, + AR5K_INT_TXERR = 0x00000100, + AR5K_INT_TXNOFRM = 0x00000200, + AR5K_INT_TXEOL = 0x00000400, + AR5K_INT_TXURN = 0x00000800, + AR5K_INT_MIB = 0x00001000, + AR5K_INT_SWI = 0x00002000, + AR5K_INT_RXPHY = 0x00004000, + AR5K_INT_RXKCM = 0x00008000, + AR5K_INT_SWBA = 0x00010000, + AR5K_INT_BRSSI = 0x00020000, + AR5K_INT_BMISS = 0x00040000, + AR5K_INT_FATAL = 0x00080000, /* Non common */ + AR5K_INT_BNR = 0x00100000, /* Non common */ + AR5K_INT_TIM = 0x00200000, /* Non common */ + AR5K_INT_DTIM = 0x00400000, /* Non common */ + AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */ + AR5K_INT_GPIO = 0x01000000, + AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */ + AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */ + AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */ + AR5K_INT_QCBRORN = 0x10000000, /* Non common */ + AR5K_INT_QCBRURN = 0x20000000, /* Non common */ + AR5K_INT_QTRIG = 0x40000000, /* Non common */ + AR5K_INT_GLOBAL = 0x80000000, + + AR5K_INT_COMMON = AR5K_INT_RXOK + | AR5K_INT_RXDESC + | AR5K_INT_RXERR + | AR5K_INT_RXNOFRM + | AR5K_INT_RXEOL + | AR5K_INT_RXORN + | AR5K_INT_TXOK + | AR5K_INT_TXDESC + | AR5K_INT_TXERR + | AR5K_INT_TXNOFRM + | AR5K_INT_TXEOL + | AR5K_INT_TXURN + | AR5K_INT_MIB + | AR5K_INT_SWI + | AR5K_INT_RXPHY + | AR5K_INT_RXKCM + | AR5K_INT_SWBA + | AR5K_INT_BRSSI + | AR5K_INT_BMISS + | AR5K_INT_GPIO + | AR5K_INT_GLOBAL, + + AR5K_INT_NOCARD = 0xffffffff +}; + +/* + * Power management + */ +enum ath5k_power_mode { + AR5K_PM_UNDEFINED = 0, + AR5K_PM_AUTO, + AR5K_PM_AWAKE, + AR5K_PM_FULL_SLEEP, + AR5K_PM_NETWORK_SLEEP, +}; + +/* GPIO-controlled software LED */ +#define AR5K_SOFTLED_PIN 0 +#define AR5K_SOFTLED_ON 0 +#define AR5K_SOFTLED_OFF 1 + +/* + * Chipset capabilities -see ath5k_hw_get_capability- + * get_capability function is not yet fully implemented + * in ath5k so most of these don't work yet... + * TODO: Implement these & merge with _TUNE_ stuff above + */ +enum ath5k_capability_type { + AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ + AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ + AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ + AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ + AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ + AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ + AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ + AR5K_CAP_COMPRESSION = 8, /* Supports compression */ + AR5K_CAP_BURST = 9, /* Supports packet bursting */ + AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ + AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ + AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ + AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ + AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ + AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ + AR5K_CAP_XR = 16, /* Supports XR mode */ + AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ + AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ + AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ + AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ +}; + + +/* XXX: we *may* move cap_range stuff to struct wiphy */ +struct ath5k_capabilities { + /* + * Supported PHY modes + * (ie. CHANNEL_A, CHANNEL_B, ...) + */ + u16 cap_mode; + + /* + * Frequency range (without regulation restrictions) + */ + struct { + u16 range_2ghz_min; + u16 range_2ghz_max; + u16 range_5ghz_min; + u16 range_5ghz_max; + } cap_range; + + /* + * Values stored in the EEPROM (some of them...) + */ + struct ath5k_eeprom_info cap_eeprom; + + /* + * Queue information + */ + struct { + u8 q_tx_num; + } cap_queues; +}; + + +/***************************************\ + HARDWARE ABSTRACTION LAYER STRUCTURE +\***************************************/ + +/* + * Misc defines + */ + +#define AR5K_MAX_GPIO 10 +#define AR5K_MAX_RF_BANKS 8 + +/* TODO: Clean up and merge with ath5k_softc */ +struct ath5k_hw { + struct ath5k_softc *ah_sc; + void *ah_iobase; + + enum ath5k_int ah_imr; + int ah_ier; + + struct net80211_channel *ah_current_channel; + int ah_turbo; + int ah_calibration; + int ah_running; + int ah_single_chip; + int ah_combined_mic; + + u32 ah_mac_srev; + u16 ah_mac_version; + u16 ah_mac_revision; + u16 ah_phy_revision; + u16 ah_radio_5ghz_revision; + u16 ah_radio_2ghz_revision; + + enum ath5k_version ah_version; + enum ath5k_radio ah_radio; + u32 ah_phy; + + int ah_5ghz; + int ah_2ghz; + +#define ah_regdomain ah_capabilities.cap_regdomain.reg_current +#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw +#define ah_modes ah_capabilities.cap_mode +#define ah_ee_version ah_capabilities.cap_eeprom.ee_version + + u32 ah_atim_window; + u32 ah_aifs; + u32 ah_cw_min; + u32 ah_cw_max; + int ah_software_retry; + u32 ah_limit_tx_retries; + + u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; + int ah_ant_diversity; + + u8 ah_sta_id[ETH_ALEN]; + + /* Current BSSID we are trying to assoc to / create. + * This is passed by mac80211 on config_interface() and cached here for + * use in resets */ + u8 ah_bssid[ETH_ALEN]; + u8 ah_bssid_mask[ETH_ALEN]; + + u32 ah_gpio[AR5K_MAX_GPIO]; + int ah_gpio_npins; + + struct ath5k_capabilities ah_capabilities; + + struct ath5k_txq_info ah_txq; + u32 ah_txq_status; + u32 ah_txq_imr_txok; + u32 ah_txq_imr_txerr; + u32 ah_txq_imr_txurn; + u32 ah_txq_imr_txdesc; + u32 ah_txq_imr_txeol; + u32 ah_txq_imr_cbrorn; + u32 ah_txq_imr_cbrurn; + u32 ah_txq_imr_qtrig; + u32 ah_txq_imr_nofrm; + u32 ah_txq_isr; + u32 *ah_rf_banks; + size_t ah_rf_banks_size; + size_t ah_rf_regs_count; + struct ath5k_gain ah_gain; + u8 ah_offset[AR5K_MAX_RF_BANKS]; + + + struct { + /* Temporary tables used for interpolation */ + u8 tmpL[AR5K_EEPROM_N_PD_GAINS] + [AR5K_EEPROM_POWER_TABLE_SIZE]; + u8 tmpR[AR5K_EEPROM_N_PD_GAINS] + [AR5K_EEPROM_POWER_TABLE_SIZE]; + u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2]; + u16 txp_rates_power_table[AR5K_MAX_RATES]; + u8 txp_min_idx; + int txp_tpc; + /* Values in 0.25dB units */ + s16 txp_min_pwr; + s16 txp_max_pwr; + s16 txp_offset; + s16 txp_ofdm; + /* Values in dB units */ + s16 txp_cck_ofdm_pwr_delta; + s16 txp_cck_ofdm_gainf_delta; + } ah_txpower; + + /* noise floor from last periodic calibration */ + s32 ah_noise_floor; + + /* + * Function pointers + */ + int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc, + u32 size, unsigned int flags); + int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, + unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int); + int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, + struct ath5k_tx_status *); + int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, + struct ath5k_rx_status *); +}; + +/* + * Prototypes + */ + +extern int ath5k_bitrate_to_hw_rix(int bitrate); + +/* Attach/Detach Functions */ +extern int ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version, struct ath5k_hw **ah); +extern void ath5k_hw_detach(struct ath5k_hw *ah); + +/* LED functions */ +extern int ath5k_init_leds(struct ath5k_softc *sc); +extern void ath5k_led_enable(struct ath5k_softc *sc); +extern void ath5k_led_off(struct ath5k_softc *sc); +extern void ath5k_unregister_leds(struct ath5k_softc *sc); + +/* Reset Functions */ +extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, int initial); +extern int ath5k_hw_reset(struct ath5k_hw *ah, struct net80211_channel *channel, int change_channel); +/* Power management functions */ +extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, int set_chip, u16 sleep_duration); + +/* DMA Related Functions */ +extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah); +extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah); +extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah); +extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr); +extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue); +extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue); +extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue); +extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, + u32 phys_addr); +extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, int increase); +/* Interrupt handling */ +extern int ath5k_hw_is_intr_pending(struct ath5k_hw *ah); +extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); +extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask); + +/* EEPROM access functions */ +extern int ath5k_eeprom_init(struct ath5k_hw *ah); +extern void ath5k_eeprom_detach(struct ath5k_hw *ah); +extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac); +extern int ath5k_eeprom_is_hb63(struct ath5k_hw *ah); + +/* Protocol Control Unit Functions */ +extern int ath5k_hw_set_opmode(struct ath5k_hw *ah); +/* BSSID Functions */ +extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac); +extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); +extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id); +extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); +/* Receive start/stop functions */ +extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah); +extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah); +/* RX Filter functions */ +extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1); +extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah); +extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter); +/* ACK bit rate */ +void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, int high); +/* ACK/CTS Timeouts */ +extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout); +extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah); +extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout); +extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah); +/* Key table (WEP) functions */ +extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry); + +/* Queue Control Unit, DFS Control Unit Functions */ +extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, const struct ath5k_txq_info *queue_info); +extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, + enum ath5k_tx_queue queue_type, + struct ath5k_txq_info *queue_info); +extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah); +extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah); +extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah); +extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time); + +/* Hardware Descriptor Functions */ +extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); + +/* GPIO Functions */ +extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); +extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio); +extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); +extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); +extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level); + +/* Misc functions */ +int ath5k_hw_set_capabilities(struct ath5k_hw *ah); +extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result); +extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); +extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); + +/* Initial register settings functions */ +extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, int change_channel); + +/* Initialize RF */ +extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah, + struct net80211_channel *channel, + unsigned int mode); +extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq); +extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah); +extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah); +/* PHY/RF channel functions */ +extern int ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags); +extern int ath5k_hw_channel(struct ath5k_hw *ah, struct net80211_channel *channel); +/* PHY calibration */ +extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct net80211_channel *channel); +extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq); +/* Misc PHY functions */ +extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan); +extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant); +extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah); +extern int ath5k_hw_phy_disable(struct ath5k_hw *ah); +/* TX power setup */ +extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct net80211_channel *channel, u8 ee_mode, u8 txpower); +extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 ee_mode, u8 txpower); + +/* + * Functions used internaly + */ + +/* + * Translate usec to hw clock units + * TODO: Half/quarter rate + */ +static inline unsigned int ath5k_hw_htoclock(unsigned int usec, int turbo) +{ + return turbo ? (usec * 80) : (usec * 40); +} + +/* + * Translate hw clock units to usec + * TODO: Half/quarter rate + */ +static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, int turbo) +{ + return turbo ? (clock / 80) : (clock / 40); +} + +/* + * Read from a register + */ +static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) +{ + return readl(ah->ah_iobase + reg); +} + +/* + * Write to a register + */ +static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) +{ + writel(val, ah->ah_iobase + reg); +} + +#if defined(_ATH5K_RESET) || defined(_ATH5K_PHY) +/* + * Check if a register write has been completed + */ +static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, + u32 val, int is_set) +{ + int i; + u32 data; + + for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { + data = ath5k_hw_reg_read(ah, reg); + if (is_set && (data & flag)) + break; + else if ((data & flag) == val) + break; + udelay(15); + } + + return (i <= 0) ? -EAGAIN : 0; +} + +/* + * Convert channel frequency to channel number + */ +static inline int ath5k_freq_to_channel(int freq) +{ + if (freq == 2484) + return 14; + + if (freq < 2484) + return (freq - 2407) / 5; + + return freq/5 - 1000; +} + +#endif + +static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) +{ + u32 retval = 0, bit, i; + + for (i = 0; i < bits; i++) { + bit = (val >> i) & 1; + retval = (retval << 1) | bit; + } + + return retval; +} + +#endif diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_attach.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_attach.c new file mode 100644 index 0000000..36dc243 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_attach.c @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> + * + * Modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net> + * Original from Linux kernel 2.6.30. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +FILE_LICENCE ( MIT ); + +/*************************************\ +* Attach/Detach Functions and helpers * +\*************************************/ + +#include <gpxe/pci.h> +#include <unistd.h> +#include <stdlib.h> +#include "ath5k.h" +#include "reg.h" +#include "base.h" + +/** + * ath5k_hw_post - Power On Self Test helper function + * + * @ah: The &struct ath5k_hw + */ +static int ath5k_hw_post(struct ath5k_hw *ah) +{ + + static const u32 static_pattern[4] = { + 0x55555555, 0xaaaaaaaa, + 0x66666666, 0x99999999 + }; + static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) }; + int i, c; + u16 cur_reg; + u32 var_pattern; + u32 init_val; + u32 cur_val; + + for (c = 0; c < 2; c++) { + + cur_reg = regs[c]; + + /* Save previous value */ + init_val = ath5k_hw_reg_read(ah, cur_reg); + + for (i = 0; i < 256; i++) { + var_pattern = i << 16 | i; + ath5k_hw_reg_write(ah, var_pattern, cur_reg); + cur_val = ath5k_hw_reg_read(ah, cur_reg); + + if (cur_val != var_pattern) { + DBG("ath5k: POST failed!\n"); + return -EAGAIN; + } + + /* Found on ndiswrapper dumps */ + var_pattern = 0x0039080f; + ath5k_hw_reg_write(ah, var_pattern, cur_reg); + } + + for (i = 0; i < 4; i++) { + var_pattern = static_pattern[i]; + ath5k_hw_reg_write(ah, var_pattern, cur_reg); + cur_val = ath5k_hw_reg_read(ah, cur_reg); + + if (cur_val != var_pattern) { + DBG("ath5k: POST failed!\n"); + return -EAGAIN; + } + + /* Found on ndiswrapper dumps */ + var_pattern = 0x003b080f; + ath5k_hw_reg_write(ah, var_pattern, cur_reg); + } + + /* Restore previous value */ + ath5k_hw_reg_write(ah, init_val, cur_reg); + + } + + return 0; + +} + +/** + * ath5k_hw_attach - Check if hw is supported and init the needed structs + * + * @sc: The &struct ath5k_softc we got from the driver's attach function + * @mac_version: The mac version id (check out ath5k.h) based on pci id + * @hw: Returned newly allocated hardware structure, on success + * + * Check if the device is supported, perform a POST and initialize the needed + * structs. Returns -ENOMEM if we don't have memory for the needed structs, + * -ENODEV if the device is not supported or prints an error msg if something + * else went wrong. + */ +int ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version, + struct ath5k_hw **hw) +{ + struct ath5k_hw *ah; + struct pci_device *pdev = sc->pdev; + int ret; + u32 srev; + + ah = zalloc(sizeof(struct ath5k_hw)); + if (ah == NULL) { + ret = -ENOMEM; + DBG("ath5k: out of memory\n"); + goto err; + } + + ah->ah_sc = sc; + ah->ah_iobase = sc->iobase; + + /* + * HW information + */ + ah->ah_turbo = 0; + ah->ah_txpower.txp_tpc = 0; + ah->ah_imr = 0; + ah->ah_atim_window = 0; + ah->ah_aifs = AR5K_TUNE_AIFS; + ah->ah_cw_min = AR5K_TUNE_CWMIN; + ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; + ah->ah_software_retry = 0; + ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY; + + /* + * Set the mac version based on the pci id + */ + ah->ah_version = mac_version; + + /*Fill the ath5k_hw struct with the needed functions*/ + ret = ath5k_hw_init_desc_functions(ah); + if (ret) + goto err_free; + + /* Bring device out of sleep and reset it's units */ + ret = ath5k_hw_nic_wakeup(ah, CHANNEL_B, 1); + if (ret) + goto err_free; + + /* Get MAC, PHY and RADIO revisions */ + srev = ath5k_hw_reg_read(ah, AR5K_SREV); + ah->ah_mac_srev = srev; + ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); + ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV); + ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID); + ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah, CHANNEL_5GHZ); + ah->ah_phy = AR5K_PHY(0); + + /* Try to identify radio chip based on it's srev */ + switch (ah->ah_radio_5ghz_revision & 0xf0) { + case AR5K_SREV_RAD_5111: + ah->ah_radio = AR5K_RF5111; + ah->ah_single_chip = 0; + ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, + CHANNEL_2GHZ); + break; + case AR5K_SREV_RAD_5112: + case AR5K_SREV_RAD_2112: + ah->ah_radio = AR5K_RF5112; + ah->ah_single_chip = 0; + ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, + CHANNEL_2GHZ); + break; + case AR5K_SREV_RAD_2413: + ah->ah_radio = AR5K_RF2413; + ah->ah_single_chip = 1; + break; + case AR5K_SREV_RAD_5413: + ah->ah_radio = AR5K_RF5413; + ah->ah_single_chip = 1; + break; + case AR5K_SREV_RAD_2316: + ah->ah_radio = AR5K_RF2316; + ah->ah_single_chip = 1; + break; + case AR5K_SREV_RAD_2317: + ah->ah_radio = AR5K_RF2317; + ah->ah_single_chip = 1; + break; + case AR5K_SREV_RAD_5424: + if (ah->ah_mac_version == AR5K_SREV_AR2425 || + ah->ah_mac_version == AR5K_SREV_AR2417) { + ah->ah_radio = AR5K_RF2425; + } else { + ah->ah_radio = AR5K_RF5413; + } + ah->ah_single_chip = 1; + break; + default: + /* Identify radio based on mac/phy srev */ + if (ah->ah_version == AR5K_AR5210) { + ah->ah_radio = AR5K_RF5110; + ah->ah_single_chip = 0; + } else if (ah->ah_version == AR5K_AR5211) { + ah->ah_radio = AR5K_RF5111; + ah->ah_single_chip = 0; + ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, + CHANNEL_2GHZ); + } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) || + ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) || + ah->ah_phy_revision == AR5K_SREV_PHY_2425) { + ah->ah_radio = AR5K_RF2425; + ah->ah_single_chip = 1; + ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425; + } else if (srev == AR5K_SREV_AR5213A && + ah->ah_phy_revision == AR5K_SREV_PHY_5212B) { + ah->ah_radio = AR5K_RF5112; + ah->ah_single_chip = 0; + ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B; + } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) { + ah->ah_radio = AR5K_RF2316; + ah->ah_single_chip = 1; + ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316; + } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) || + ah->ah_phy_revision == AR5K_SREV_PHY_5413) { + ah->ah_radio = AR5K_RF5413; + ah->ah_single_chip = 1; + ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413; + } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) || + ah->ah_phy_revision == AR5K_SREV_PHY_2413) { + ah->ah_radio = AR5K_RF2413; + ah->ah_single_chip = 1; + ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413; + } else { + DBG("ath5k: Couldn't identify radio revision.\n"); + ret = -ENOTSUP; + goto err_free; + } + } + + /* Return on unsuported chips (unsupported eeprom etc) */ + if ((srev >= AR5K_SREV_AR5416) && + (srev < AR5K_SREV_AR2425)) { + DBG("ath5k: Device not yet supported.\n"); + ret = -ENOTSUP; + goto err_free; + } + + /* + * Write PCI-E power save settings + */ + if ((ah->ah_version == AR5K_AR5212) && + pci_find_capability(pdev, PCI_CAP_ID_EXP)) { + ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES); + ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES); + /* Shut off RX when elecidle is asserted */ + ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES); + ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES); + /* TODO: EEPROM work */ + ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES); + /* Shut off PLL and CLKREQ active in L1 */ + ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES); + /* Preserce other settings */ + ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES); + ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES); + ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES); + /* Reset SERDES to load new settings */ + ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET); + mdelay(1); + } + + /* + * POST + */ + ret = ath5k_hw_post(ah); + if (ret) + goto err_free; + + /* Enable pci core retry fix on Hainan (5213A) and later chips */ + if (srev >= AR5K_SREV_AR5213A) + ath5k_hw_reg_write(ah, AR5K_PCICFG_RETRY_FIX, AR5K_PCICFG); + + /* + * Get card capabilities, calibration values etc + * TODO: EEPROM work + */ + ret = ath5k_eeprom_init(ah); + if (ret) { + DBG("ath5k: unable to init EEPROM\n"); + goto err_free; + } + + /* Get misc capabilities */ + ret = ath5k_hw_set_capabilities(ah); + if (ret) { + DBG("ath5k: unable to get device capabilities: 0x%04x\n", + sc->pdev->device); + goto err_free; + } + + if (srev >= AR5K_SREV_AR2414) { + ah->ah_combined_mic = 1; + AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE, + AR5K_MISC_MODE_COMBINED_MIC); + } + + /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */ + memset(ah->ah_bssid, 0xff, ETH_ALEN); + ath5k_hw_set_associd(ah, ah->ah_bssid, 0); + ath5k_hw_set_opmode(ah); + + ath5k_hw_rfgain_opt_init(ah); + + *hw = ah; + return 0; +err_free: + free(ah); +err: + return ret; +} + +/** + * ath5k_hw_detach - Free the ath5k_hw struct + * + * @ah: The &struct ath5k_hw + */ +void ath5k_hw_detach(struct ath5k_hw *ah) +{ + free(ah->ah_rf_banks); + ath5k_eeprom_detach(ah); + free(ah); +} diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_caps.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_caps.c new file mode 100644 index 0000000..1d60d74 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_caps.c @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> + * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> + * + * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +FILE_LICENCE ( MIT ); + +/**************\ +* Capabilities * +\**************/ + +#include "ath5k.h" +#include "reg.h" +#include "base.h" + +/* + * Fill the capabilities struct + * TODO: Merge this with EEPROM code when we are done with it + */ +int ath5k_hw_set_capabilities(struct ath5k_hw *ah) +{ + u16 ee_header; + + /* Capabilities stored in the EEPROM */ + ee_header = ah->ah_capabilities.cap_eeprom.ee_header; + + if (ah->ah_version == AR5K_AR5210) { + /* + * Set radio capabilities + * (The AR5110 only supports the middle 5GHz band) + */ + ah->ah_capabilities.cap_range.range_5ghz_min = 5120; + ah->ah_capabilities.cap_range.range_5ghz_max = 5430; + ah->ah_capabilities.cap_range.range_2ghz_min = 0; + ah->ah_capabilities.cap_range.range_2ghz_max = 0; + + /* Set supported modes */ + ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A; + ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A_TURBO; + } else { + /* + * XXX The tranceiver supports frequencies from 4920 to 6100GHz + * XXX and from 2312 to 2732GHz. There are problems with the + * XXX current ieee80211 implementation because the IEEE + * XXX channel mapping does not support negative channel + * XXX numbers (2312MHz is channel -19). Of course, this + * XXX doesn't matter because these channels are out of range + * XXX but some regulation domains like MKK (Japan) will + * XXX support frequencies somewhere around 4.8GHz. + */ + + /* + * Set radio capabilities + */ + + if (AR5K_EEPROM_HDR_11A(ee_header)) { + /* 4920 */ + ah->ah_capabilities.cap_range.range_5ghz_min = 5005; + ah->ah_capabilities.cap_range.range_5ghz_max = 6100; + + /* Set supported modes */ + ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A; + ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A_TURBO; + if (ah->ah_version == AR5K_AR5212) + ah->ah_capabilities.cap_mode |= + AR5K_MODE_BIT_11G_TURBO; + } + + /* Enable 802.11b if a 2GHz capable radio (2111/5112) is + * connected */ + if (AR5K_EEPROM_HDR_11B(ee_header) || + (AR5K_EEPROM_HDR_11G(ee_header) && + ah->ah_version != AR5K_AR5211)) { + /* 2312 */ + ah->ah_capabilities.cap_range.range_2ghz_min = 2412; + ah->ah_capabilities.cap_range.range_2ghz_max = 2732; + + if (AR5K_EEPROM_HDR_11B(ee_header)) + ah->ah_capabilities.cap_mode |= + AR5K_MODE_BIT_11B; + + if (AR5K_EEPROM_HDR_11G(ee_header) && + ah->ah_version != AR5K_AR5211) + ah->ah_capabilities.cap_mode |= + AR5K_MODE_BIT_11G; + } + } + + /* GPIO */ + ah->ah_gpio_npins = AR5K_NUM_GPIO; + + /* Set number of supported TX queues */ + ah->ah_capabilities.cap_queues.q_tx_num = 1; + + return 0; +} + +/* Main function used by the driver part to check caps */ +int ath5k_hw_get_capability(struct ath5k_hw *ah, + enum ath5k_capability_type cap_type, + u32 capability __unused, u32 *result) +{ + switch (cap_type) { + case AR5K_CAP_NUM_TXQUEUES: + if (result) { + *result = 1; + goto yes; + } + case AR5K_CAP_VEOL: + goto yes; + case AR5K_CAP_COMPRESSION: + if (ah->ah_version == AR5K_AR5212) + goto yes; + else + goto no; + case AR5K_CAP_BURST: + goto yes; + case AR5K_CAP_TPC: + goto yes; + case AR5K_CAP_BSSIDMASK: + if (ah->ah_version == AR5K_AR5212) + goto yes; + else + goto no; + case AR5K_CAP_XR: + if (ah->ah_version == AR5K_AR5212) + goto yes; + else + goto no; + default: + goto no; + } + +no: + return -EINVAL; +yes: + return 0; +} diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_desc.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_desc.c new file mode 100644 index 0000000..76d0c1e --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_desc.c @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> + * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> + * + * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +FILE_LICENCE ( MIT ); + +/******************************\ + Hardware Descriptor Functions +\******************************/ + +#include "ath5k.h" +#include "reg.h" +#include "base.h" + +/* + * TX Descriptors + */ + +#define FCS_LEN 4 + +/* + * Initialize the 2-word tx control descriptor on 5210/5211 + */ +static int +ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, + unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type, + unsigned int tx_power __unused, unsigned int tx_rate0, unsigned int tx_tries0, + unsigned int key_index __unused, unsigned int antenna_mode, unsigned int flags, + unsigned int rtscts_rate __unused, unsigned int rtscts_duration) +{ + u32 frame_type; + struct ath5k_hw_2w_tx_ctl *tx_ctl; + unsigned int frame_len; + + tx_ctl = &desc->ud.ds_tx5210.tx_ctl; + + /* + * Validate input + * - Zero retries don't make sense. + * - A zero rate will put the HW into a mode where it continously sends + * noise on the channel, so it is important to avoid this. + */ + if (tx_tries0 == 0) { + DBG("ath5k: zero retries\n"); + return -EINVAL; + } + if (tx_rate0 == 0) { + DBG("ath5k: zero rate\n"); + return -EINVAL; + } + + /* Clear descriptor */ + memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc)); + + /* Setup control descriptor */ + + /* Verify and set frame length */ + + frame_len = pkt_len + FCS_LEN; + + if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN) + return -EINVAL; + + tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN; + + /* Verify and set buffer length */ + + if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN) + return -EINVAL; + + tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN; + + /* + * Verify and set header length + * XXX: I only found that on 5210 code, does it work on 5211 ? + */ + if (ah->ah_version == AR5K_AR5210) { + if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN) + return -EINVAL; + tx_ctl->tx_control_0 |= + AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN); + } + + /*Diferences between 5210-5211*/ + if (ah->ah_version == AR5K_AR5210) { + switch (type) { + case AR5K_PKT_TYPE_BEACON: + case AR5K_PKT_TYPE_PROBE_RESP: + frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY; + case AR5K_PKT_TYPE_PIFS: + frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS; + default: + frame_type = type /*<< 2 ?*/; + } + + tx_ctl->tx_control_0 |= + AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) | + AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE); + + } else { + tx_ctl->tx_control_0 |= + AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) | + AR5K_REG_SM(antenna_mode, + AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT); + tx_ctl->tx_control_1 |= + AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE); + } +#define _TX_FLAGS(_c, _flag) \ + if (flags & AR5K_TXDESC_##_flag) { \ + tx_ctl->tx_control_##_c |= \ + AR5K_2W_TX_DESC_CTL##_c##_##_flag; \ + } + + _TX_FLAGS(0, CLRDMASK); + _TX_FLAGS(0, VEOL); + _TX_FLAGS(0, INTREQ); + _TX_FLAGS(0, RTSENA); + _TX_FLAGS(1, NOACK); + +#undef _TX_FLAGS + + /* + * RTS/CTS Duration [5210 ?] + */ + if ((ah->ah_version == AR5K_AR5210) && + (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA))) + tx_ctl->tx_control_1 |= rtscts_duration & + AR5K_2W_TX_DESC_CTL1_RTS_DURATION; + + return 0; +} + +/* + * Initialize the 4-word tx control descriptor on 5212 + */ +static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah, + struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len __unused, + enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0, + unsigned int tx_tries0, unsigned int key_index __unused, + unsigned int antenna_mode, unsigned int flags, + unsigned int rtscts_rate, + unsigned int rtscts_duration) +{ + struct ath5k_hw_4w_tx_ctl *tx_ctl; + unsigned int frame_len; + + tx_ctl = &desc->ud.ds_tx5212.tx_ctl; + + /* + * Validate input + * - Zero retries don't make sense. + * - A zero rate will put the HW into a mode where it continously sends + * noise on the channel, so it is important to avoid this. + */ + if (tx_tries0 == 0) { + DBG("ath5k: zero retries\n"); + return -EINVAL; + } + if (tx_rate0 == 0) { + DBG("ath5k: zero rate\n"); + return -EINVAL; + } + + tx_power += ah->ah_txpower.txp_offset; + if (tx_power > AR5K_TUNE_MAX_TXPOWER) + tx_power = AR5K_TUNE_MAX_TXPOWER; + + /* Clear descriptor */ + memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc)); + + /* Setup control descriptor */ + + /* Verify and set frame length */ + + frame_len = pkt_len + FCS_LEN; + + if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN) + return -EINVAL; + + tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN; + + /* Verify and set buffer length */ + + if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN) + return -EINVAL; + + tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN; + + tx_ctl->tx_control_0 |= + AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) | + AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT); + tx_ctl->tx_control_1 |= AR5K_REG_SM(type, + AR5K_4W_TX_DESC_CTL1_FRAME_TYPE); + tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES, + AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0); + tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; + +#define _TX_FLAGS(_c, _flag) \ + if (flags & AR5K_TXDESC_##_flag) { \ + tx_ctl->tx_control_##_c |= \ + AR5K_4W_TX_DESC_CTL##_c##_##_flag; \ + } + + _TX_FLAGS(0, CLRDMASK); + _TX_FLAGS(0, VEOL); + _TX_FLAGS(0, INTREQ); + _TX_FLAGS(0, RTSENA); + _TX_FLAGS(0, CTSENA); + _TX_FLAGS(1, NOACK); + +#undef _TX_FLAGS + + /* + * RTS/CTS + */ + if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { + if ((flags & AR5K_TXDESC_RTSENA) && + (flags & AR5K_TXDESC_CTSENA)) + return -EINVAL; + tx_ctl->tx_control_2 |= rtscts_duration & + AR5K_4W_TX_DESC_CTL2_RTS_DURATION; + tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate, + AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE); + } + + return 0; +} + +/* + * Proccess the tx status descriptor on 5210/5211 + */ +static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah __unused, + struct ath5k_desc *desc, struct ath5k_tx_status *ts) +{ + struct ath5k_hw_2w_tx_ctl *tx_ctl; + struct ath5k_hw_tx_status *tx_status; + + tx_ctl = &desc->ud.ds_tx5210.tx_ctl; + tx_status = &desc->ud.ds_tx5210.tx_stat; + + /* No frame has been send or error */ + if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0) + return -EINPROGRESS; + + /* + * Get descriptor status + */ + ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); + ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); + ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); + /*TODO: ts->ts_virtcol + test*/ + ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_SEQ_NUM); + ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); + ts->ts_antenna = 1; + ts->ts_status = 0; + ts->ts_rate[0] = AR5K_REG_MS(tx_ctl->tx_control_0, + AR5K_2W_TX_DESC_CTL0_XMIT_RATE); + ts->ts_retry[0] = ts->ts_longretry; + ts->ts_final_idx = 0; + + if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) { + if (tx_status->tx_status_0 & + AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) + ts->ts_status |= AR5K_TXERR_XRETRY; + + if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) + ts->ts_status |= AR5K_TXERR_FIFO; + + if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) + ts->ts_status |= AR5K_TXERR_FILT; + } + + return 0; +} + +/* + * Proccess a tx status descriptor on 5212 + */ +static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah __unused, + struct ath5k_desc *desc, struct ath5k_tx_status *ts) +{ + struct ath5k_hw_4w_tx_ctl *tx_ctl; + struct ath5k_hw_tx_status *tx_status; + + tx_ctl = &desc->ud.ds_tx5212.tx_ctl; + tx_status = &desc->ud.ds_tx5212.tx_stat; + + /* No frame has been send or error */ + if (!(tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE)) + return -EINPROGRESS; + + /* + * Get descriptor status + */ + ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); + ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); + ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, + AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); + ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_SEQ_NUM); + ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); + ts->ts_antenna = (tx_status->tx_status_1 & + AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1; + ts->ts_status = 0; + + ts->ts_final_idx = AR5K_REG_MS(tx_status->tx_status_1, + AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX); + + ts->ts_retry[0] = ts->ts_longretry; + ts->ts_rate[0] = tx_ctl->tx_control_3 & + AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; + + /* TX error */ + if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) { + if (tx_status->tx_status_0 & + AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) + ts->ts_status |= AR5K_TXERR_XRETRY; + + if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) + ts->ts_status |= AR5K_TXERR_FIFO; + + if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) + ts->ts_status |= AR5K_TXERR_FILT; + } + + return 0; +} + +/* + * RX Descriptors + */ + +/* + * Initialize an rx control descriptor + */ +static int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah __unused, + struct ath5k_desc *desc, + u32 size, unsigned int flags) +{ + struct ath5k_hw_rx_ctl *rx_ctl; + + rx_ctl = &desc->ud.ds_rx.rx_ctl; + + /* + * Clear the descriptor + * If we don't clean the status descriptor, + * while scanning we get too many results, + * most of them virtual, after some secs + * of scanning system hangs. M.F. + */ + memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc)); + + /* Setup descriptor */ + rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN; + if (rx_ctl->rx_control_1 != size) + return -EINVAL; + + if (flags & AR5K_RXDESC_INTREQ) + rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ; + + return 0; +} + +/* + * Proccess the rx status descriptor on 5210/5211 + */ +static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah __unused, + struct ath5k_desc *desc, struct ath5k_rx_status *rs) +{ + struct ath5k_hw_rx_status *rx_status; + + rx_status = &desc->ud.ds_rx.u.rx_stat; + + /* No frame received / not ready */ + if (!(rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_DONE)) + return -EINPROGRESS; + + /* + * Frame receive status + */ + rs->rs_datalen = rx_status->rx_status_0 & + AR5K_5210_RX_DESC_STATUS0_DATA_LEN; + rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, + AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL); + rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0, + AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE); + rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0, + AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA); + rs->rs_more = !!(rx_status->rx_status_0 & + AR5K_5210_RX_DESC_STATUS0_MORE); + /* TODO: this timestamp is 13 bit, later on we assume 15 bit */ + rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, + AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); + rs->rs_status = 0; + rs->rs_phyerr = 0; + rs->rs_keyix = AR5K_RXKEYIX_INVALID; + + /* + * Receive/descriptor errors + */ + if (!(rx_status->rx_status_1 & + AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) { + if (rx_status->rx_status_1 & + AR5K_5210_RX_DESC_STATUS1_CRC_ERROR) + rs->rs_status |= AR5K_RXERR_CRC; + + if (rx_status->rx_status_1 & + AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN) + rs->rs_status |= AR5K_RXERR_FIFO; + + if (rx_status->rx_status_1 & + AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) { + rs->rs_status |= AR5K_RXERR_PHY; + rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1, + AR5K_5210_RX_DESC_STATUS1_PHY_ERROR); + } + + if (rx_status->rx_status_1 & + AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) + rs->rs_status |= AR5K_RXERR_DECRYPT; + } + + return 0; +} + +/* + * Proccess the rx status descriptor on 5212 + */ +static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah __unused, + struct ath5k_desc *desc, struct ath5k_rx_status *rs) +{ + struct ath5k_hw_rx_status *rx_status; + struct ath5k_hw_rx_error *rx_err; + + rx_status = &desc->ud.ds_rx.u.rx_stat; + + /* Overlay on error */ + rx_err = &desc->ud.ds_rx.u.rx_err; + + /* No frame received / not ready */ + if (!(rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_DONE)) + return -EINPROGRESS; + + /* + * Frame receive status + */ + rs->rs_datalen = rx_status->rx_status_0 & + AR5K_5212_RX_DESC_STATUS0_DATA_LEN; + rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, + AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL); + rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0, + AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE); + rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0, + AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA); + rs->rs_more = !!(rx_status->rx_status_0 & + AR5K_5212_RX_DESC_STATUS0_MORE); + rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, + AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); + rs->rs_status = 0; + rs->rs_phyerr = 0; + rs->rs_keyix = AR5K_RXKEYIX_INVALID; + + /* + * Receive/descriptor errors + */ + if (!(rx_status->rx_status_1 & + AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) { + if (rx_status->rx_status_1 & + AR5K_5212_RX_DESC_STATUS1_CRC_ERROR) + rs->rs_status |= AR5K_RXERR_CRC; + + if (rx_status->rx_status_1 & + AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) { + rs->rs_status |= AR5K_RXERR_PHY; + rs->rs_phyerr |= AR5K_REG_MS(rx_err->rx_error_1, + AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE); + } + + if (rx_status->rx_status_1 & + AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) + rs->rs_status |= AR5K_RXERR_DECRYPT; + + if (rx_status->rx_status_1 & + AR5K_5212_RX_DESC_STATUS1_MIC_ERROR) + rs->rs_status |= AR5K_RXERR_MIC; + } + + return 0; +} + +/* + * Init function pointers inside ath5k_hw struct + */ +int ath5k_hw_init_desc_functions(struct ath5k_hw *ah) +{ + + if (ah->ah_version != AR5K_AR5210 && + ah->ah_version != AR5K_AR5211 && + ah->ah_version != AR5K_AR5212) + return -ENOTSUP; + + if (ah->ah_version == AR5K_AR5212) { + ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc; + ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc; + ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status; + } else { + ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc; + ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc; + ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status; + } + + if (ah->ah_version == AR5K_AR5212) + ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status; + else if (ah->ah_version <= AR5K_AR5211) + ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status; + + return 0; +} + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_dma.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_dma.c new file mode 100644 index 0000000..23c4cf9 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_dma.c @@ -0,0 +1,631 @@ +/* + * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> + * + * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +FILE_LICENCE ( MIT ); + +/*************************************\ +* DMA and interrupt masking functions * +\*************************************/ + +/* + * dma.c - DMA and interrupt masking functions + * + * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and + * handle queue setup for 5210 chipset (rest are handled on qcu.c). + * Also we setup interrupt mask register (IMR) and read the various iterrupt + * status registers (ISR). + * + * TODO: Handle SISR on 5211+ and introduce a function to return the queue + * number that resulted the interrupt. + */ + +#include <unistd.h> + +#include "ath5k.h" +#include "reg.h" +#include "base.h" + +/*********\ +* Receive * +\*********/ + +/** + * ath5k_hw_start_rx_dma - Start DMA receive + * + * @ah: The &struct ath5k_hw + */ +void ath5k_hw_start_rx_dma(struct ath5k_hw *ah) +{ + ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR); + ath5k_hw_reg_read(ah, AR5K_CR); +} + +/** + * ath5k_hw_stop_rx_dma - Stop DMA receive + * + * @ah: The &struct ath5k_hw + */ +int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah) +{ + unsigned int i; + + ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR); + + /* + * It may take some time to disable the DMA receive unit + */ + for (i = 1000; i > 0 && + (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0; + i--) + udelay(10); + + return i ? 0 : -EBUSY; +} + +/** + * ath5k_hw_get_rxdp - Get RX Descriptor's address + * + * @ah: The &struct ath5k_hw + * + * XXX: Is RXDP read and clear ? + */ +u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah) +{ + return ath5k_hw_reg_read(ah, AR5K_RXDP); +} + +/** + * ath5k_hw_set_rxdp - Set RX Descriptor's address + * + * @ah: The &struct ath5k_hw + * @phys_addr: RX descriptor address + * + * XXX: Should we check if rx is enabled before setting rxdp ? + */ +void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr) +{ + ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP); +} + + +/**********\ +* Transmit * +\**********/ + +/** + * ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue + * + * @ah: The &struct ath5k_hw + * @queue: The hw queue number + * + * Start DMA transmit for a specific queue and since 5210 doesn't have + * QCU/DCU, set up queue parameters for 5210 here based on queue type (one + * queue for normal data and one queue for beacons). For queue setup + * on newer chips check out qcu.c. Returns -EINVAL if queue number is out + * of range or if queue is already disabled. + * + * NOTE: Must be called after setting up tx control descriptor for that + * queue (see below). + */ +int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue) +{ + u32 tx_queue; + + /* Return if queue is declared inactive */ + if (ah->ah_txq.tqi_type == AR5K_TX_QUEUE_INACTIVE) + return -EIO; + + if (ah->ah_version == AR5K_AR5210) { + tx_queue = ath5k_hw_reg_read(ah, AR5K_CR); + + /* Assume always a data queue */ + tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0; + + /* Start queue */ + ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); + ath5k_hw_reg_read(ah, AR5K_CR); + } else { + /* Return if queue is disabled */ + if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue)) + return -EIO; + + /* Start queue */ + AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue); + } + + return 0; +} + +/** + * ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue + * + * @ah: The &struct ath5k_hw + * @queue: The hw queue number + * + * Stop DMA transmit on a specific hw queue and drain queue so we don't + * have any pending frames. Returns -EBUSY if we still have pending frames, + * -EINVAL if queue number is out of range. + * + */ +int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue) +{ + unsigned int i = 40; + u32 tx_queue, pending; + + /* Return if queue is declared inactive */ + if (ah->ah_txq.tqi_type == AR5K_TX_QUEUE_INACTIVE) + return -EIO; + + if (ah->ah_version == AR5K_AR5210) { + tx_queue = ath5k_hw_reg_read(ah, AR5K_CR); + + /* Assume a data queue */ + tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0; + + /* Stop queue */ + ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); + ath5k_hw_reg_read(ah, AR5K_CR); + } else { + /* + * Schedule TX disable and wait until queue is empty + */ + AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue); + + /*Check for pending frames*/ + do { + pending = ath5k_hw_reg_read(ah, + AR5K_QUEUE_STATUS(queue)) & + AR5K_QCU_STS_FRMPENDCNT; + udelay(100); + } while (--i && pending); + + /* For 2413+ order PCU to drop packets using + * QUIET mechanism */ + if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) && pending) { + /* Set periodicity and duration */ + ath5k_hw_reg_write(ah, + AR5K_REG_SM(100, AR5K_QUIET_CTL2_QT_PER)| + AR5K_REG_SM(10, AR5K_QUIET_CTL2_QT_DUR), + AR5K_QUIET_CTL2); + + /* Enable quiet period for current TSF */ + ath5k_hw_reg_write(ah, + AR5K_QUIET_CTL1_QT_EN | + AR5K_REG_SM(ath5k_hw_reg_read(ah, + AR5K_TSF_L32_5211) >> 10, + AR5K_QUIET_CTL1_NEXT_QT_TSF), + AR5K_QUIET_CTL1); + + /* Force channel idle high */ + AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211, + AR5K_DIAG_SW_CHANEL_IDLE_HIGH); + + /* Wait a while and disable mechanism */ + udelay(200); + AR5K_REG_DISABLE_BITS(ah, AR5K_QUIET_CTL1, + AR5K_QUIET_CTL1_QT_EN); + + /* Re-check for pending frames */ + i = 40; + do { + pending = ath5k_hw_reg_read(ah, + AR5K_QUEUE_STATUS(queue)) & + AR5K_QCU_STS_FRMPENDCNT; + udelay(100); + } while (--i && pending); + + AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211, + AR5K_DIAG_SW_CHANEL_IDLE_HIGH); + } + + /* Clear register */ + ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD); + if (pending) + return -EBUSY; + } + + /* TODO: Check for success on 5210 else return error */ + return 0; +} + +/** + * ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue + * + * @ah: The &struct ath5k_hw + * @queue: The hw queue number + * + * Get TX descriptor's address for a specific queue. For 5210 we ignore + * the queue number and use tx queue type since we only have 2 queues. + * We use TXDP0 for normal data queue and TXDP1 for beacon queue. + * For newer chips with QCU/DCU we just read the corresponding TXDP register. + * + * XXX: Is TXDP read and clear ? + */ +u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue) +{ + u16 tx_reg; + + /* + * Get the transmit queue descriptor pointer from the selected queue + */ + /*5210 doesn't have QCU*/ + if (ah->ah_version == AR5K_AR5210) { + /* Assume a data queue */ + tx_reg = AR5K_NOQCU_TXDP0; + } else { + tx_reg = AR5K_QUEUE_TXDP(queue); + } + + return ath5k_hw_reg_read(ah, tx_reg); +} + +/** + * ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue + * + * @ah: The &struct ath5k_hw + * @queue: The hw queue number + * + * Set TX descriptor's address for a specific queue. For 5210 we ignore + * the queue number and we use tx queue type since we only have 2 queues + * so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue. + * For newer chips with QCU/DCU we just set the corresponding TXDP register. + * Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still + * active. + */ +int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr) +{ + u16 tx_reg; + + /* + * Set the transmit queue descriptor pointer register by type + * on 5210 + */ + if (ah->ah_version == AR5K_AR5210) { + /* Assume a data queue */ + tx_reg = AR5K_NOQCU_TXDP0; + } else { + /* + * Set the transmit queue descriptor pointer for + * the selected queue on QCU for 5211+ + * (this won't work if the queue is still active) + */ + if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue)) + return -EIO; + + tx_reg = AR5K_QUEUE_TXDP(queue); + } + + /* Set descriptor pointer */ + ath5k_hw_reg_write(ah, phys_addr, tx_reg); + + return 0; +} + +/** + * ath5k_hw_update_tx_triglevel - Update tx trigger level + * + * @ah: The &struct ath5k_hw + * @increase: Flag to force increase of trigger level + * + * This function increases/decreases the tx trigger level for the tx fifo + * buffer (aka FIFO threshold) that is used to indicate when PCU flushes + * the buffer and transmits it's data. Lowering this results sending small + * frames more quickly but can lead to tx underruns, raising it a lot can + * result other problems (i think bmiss is related). Right now we start with + * the lowest possible (64Bytes) and if we get tx underrun we increase it using + * the increase flag. Returns -EIO if we have have reached maximum/minimum. + * + * XXX: Link this with tx DMA size ? + * XXX: Use it to save interrupts ? + * TODO: Needs testing, i think it's related to bmiss... + */ +int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, int increase) +{ + u32 trigger_level, imr; + int ret = -EIO; + + /* + * Disable interrupts by setting the mask + */ + imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL); + + trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG), + AR5K_TXCFG_TXFULL); + + if (!increase) { + if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) + goto done; + } else + trigger_level += + ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); + + /* + * Update trigger level on success + */ + if (ah->ah_version == AR5K_AR5210) + ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL); + else + AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, + AR5K_TXCFG_TXFULL, trigger_level); + + ret = 0; + +done: + /* + * Restore interrupt mask + */ + ath5k_hw_set_imr(ah, imr); + + return ret; +} + +/*******************\ +* Interrupt masking * +\*******************/ + +/** + * ath5k_hw_is_intr_pending - Check if we have pending interrupts + * + * @ah: The &struct ath5k_hw + * + * Check if we have pending interrupts to process. Returns 1 if we + * have pending interrupts and 0 if we haven't. + */ +int ath5k_hw_is_intr_pending(struct ath5k_hw *ah) +{ + return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0; +} + +/** + * ath5k_hw_get_isr - Get interrupt status + * + * @ah: The @struct ath5k_hw + * @interrupt_mask: Driver's interrupt mask used to filter out + * interrupts in sw. + * + * This function is used inside our interrupt handler to determine the reason + * for the interrupt by reading Primary Interrupt Status Register. Returns an + * abstract interrupt status mask which is mostly ISR with some uncommon bits + * being mapped on some standard non hw-specific positions + * (check out &ath5k_int). + * + * NOTE: We use read-and-clear register, so after this function is called ISR + * is zeroed. + */ +int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask) +{ + u32 data; + + /* + * Read interrupt status from the Interrupt Status register + * on 5210 + */ + if (ah->ah_version == AR5K_AR5210) { + data = ath5k_hw_reg_read(ah, AR5K_ISR); + if (data == AR5K_INT_NOCARD) { + *interrupt_mask = data; + return -ENODEV; + } + } else { + /* + * Read interrupt status from Interrupt + * Status Register shadow copy (Read And Clear) + * + * Note: PISR/SISR Not available on 5210 + */ + data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR); + if (data == AR5K_INT_NOCARD) { + *interrupt_mask = data; + return -ENODEV; + } + } + + /* + * Get abstract interrupt mask (driver-compatible) + */ + *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr; + + if (ah->ah_version != AR5K_AR5210) { + u32 sisr2 = ath5k_hw_reg_read(ah, AR5K_RAC_SISR2); + + /*HIU = Host Interface Unit (PCI etc)*/ + if (data & (AR5K_ISR_HIUERR)) + *interrupt_mask |= AR5K_INT_FATAL; + + /*Beacon Not Ready*/ + if (data & (AR5K_ISR_BNR)) + *interrupt_mask |= AR5K_INT_BNR; + + if (sisr2 & (AR5K_SISR2_SSERR | AR5K_SISR2_DPERR | + AR5K_SISR2_MCABT)) + *interrupt_mask |= AR5K_INT_FATAL; + + if (data & AR5K_ISR_TIM) + *interrupt_mask |= AR5K_INT_TIM; + + if (data & AR5K_ISR_BCNMISC) { + if (sisr2 & AR5K_SISR2_TIM) + *interrupt_mask |= AR5K_INT_TIM; + if (sisr2 & AR5K_SISR2_DTIM) + *interrupt_mask |= AR5K_INT_DTIM; + if (sisr2 & AR5K_SISR2_DTIM_SYNC) + *interrupt_mask |= AR5K_INT_DTIM_SYNC; + if (sisr2 & AR5K_SISR2_BCN_TIMEOUT) + *interrupt_mask |= AR5K_INT_BCN_TIMEOUT; + if (sisr2 & AR5K_SISR2_CAB_TIMEOUT) + *interrupt_mask |= AR5K_INT_CAB_TIMEOUT; + } + + if (data & AR5K_ISR_RXDOPPLER) + *interrupt_mask |= AR5K_INT_RX_DOPPLER; + if (data & AR5K_ISR_QCBRORN) { + *interrupt_mask |= AR5K_INT_QCBRORN; + ah->ah_txq_isr |= AR5K_REG_MS( + ath5k_hw_reg_read(ah, AR5K_RAC_SISR3), + AR5K_SISR3_QCBRORN); + } + if (data & AR5K_ISR_QCBRURN) { + *interrupt_mask |= AR5K_INT_QCBRURN; + ah->ah_txq_isr |= AR5K_REG_MS( + ath5k_hw_reg_read(ah, AR5K_RAC_SISR3), + AR5K_SISR3_QCBRURN); + } + if (data & AR5K_ISR_QTRIG) { + *interrupt_mask |= AR5K_INT_QTRIG; + ah->ah_txq_isr |= AR5K_REG_MS( + ath5k_hw_reg_read(ah, AR5K_RAC_SISR4), + AR5K_SISR4_QTRIG); + } + + if (data & AR5K_ISR_TXOK) + ah->ah_txq_isr |= AR5K_REG_MS( + ath5k_hw_reg_read(ah, AR5K_RAC_SISR0), + AR5K_SISR0_QCU_TXOK); + + if (data & AR5K_ISR_TXDESC) + ah->ah_txq_isr |= AR5K_REG_MS( + ath5k_hw_reg_read(ah, AR5K_RAC_SISR0), + AR5K_SISR0_QCU_TXDESC); + + if (data & AR5K_ISR_TXERR) + ah->ah_txq_isr |= AR5K_REG_MS( + ath5k_hw_reg_read(ah, AR5K_RAC_SISR1), + AR5K_SISR1_QCU_TXERR); + + if (data & AR5K_ISR_TXEOL) + ah->ah_txq_isr |= AR5K_REG_MS( + ath5k_hw_reg_read(ah, AR5K_RAC_SISR1), + AR5K_SISR1_QCU_TXEOL); + + if (data & AR5K_ISR_TXURN) + ah->ah_txq_isr |= AR5K_REG_MS( + ath5k_hw_reg_read(ah, AR5K_RAC_SISR2), + AR5K_SISR2_QCU_TXURN); + } else { + if (data & (AR5K_ISR_SSERR | AR5K_ISR_MCABT | + AR5K_ISR_HIUERR | AR5K_ISR_DPERR)) + *interrupt_mask |= AR5K_INT_FATAL; + + /* + * XXX: BMISS interrupts may occur after association. + * I found this on 5210 code but it needs testing. If this is + * true we should disable them before assoc and re-enable them + * after a successful assoc + some jiffies. + interrupt_mask &= ~AR5K_INT_BMISS; + */ + } + + return 0; +} + +/** + * ath5k_hw_set_imr - Set interrupt mask + * + * @ah: The &struct ath5k_hw + * @new_mask: The new interrupt mask to be set + * + * Set the interrupt mask in hw to save interrupts. We do that by mapping + * ath5k_int bits to hw-specific bits to remove abstraction and writing + * Interrupt Mask Register. + */ +enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask) +{ + enum ath5k_int old_mask, int_mask; + + old_mask = ah->ah_imr; + + /* + * Disable card interrupts to prevent any race conditions + * (they will be re-enabled afterwards if AR5K_INT GLOBAL + * is set again on the new mask). + */ + if (old_mask & AR5K_INT_GLOBAL) { + ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER); + ath5k_hw_reg_read(ah, AR5K_IER); + } + + /* + * Add additional, chipset-dependent interrupt mask flags + * and write them to the IMR (interrupt mask register). + */ + int_mask = new_mask & AR5K_INT_COMMON; + + if (ah->ah_version != AR5K_AR5210) { + /* Preserve per queue TXURN interrupt mask */ + u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2) + & AR5K_SIMR2_QCU_TXURN; + + if (new_mask & AR5K_INT_FATAL) { + int_mask |= AR5K_IMR_HIUERR; + simr2 |= (AR5K_SIMR2_MCABT | AR5K_SIMR2_SSERR + | AR5K_SIMR2_DPERR); + } + + /*Beacon Not Ready*/ + if (new_mask & AR5K_INT_BNR) + int_mask |= AR5K_INT_BNR; + + if (new_mask & AR5K_INT_TIM) + int_mask |= AR5K_IMR_TIM; + + if (new_mask & AR5K_INT_TIM) + simr2 |= AR5K_SISR2_TIM; + if (new_mask & AR5K_INT_DTIM) + simr2 |= AR5K_SISR2_DTIM; + if (new_mask & AR5K_INT_DTIM_SYNC) + simr2 |= AR5K_SISR2_DTIM_SYNC; + if (new_mask & AR5K_INT_BCN_TIMEOUT) + simr2 |= AR5K_SISR2_BCN_TIMEOUT; + if (new_mask & AR5K_INT_CAB_TIMEOUT) + simr2 |= AR5K_SISR2_CAB_TIMEOUT; + + if (new_mask & AR5K_INT_RX_DOPPLER) + int_mask |= AR5K_IMR_RXDOPPLER; + + /* Note: Per queue interrupt masks + * are set via reset_tx_queue (qcu.c) */ + ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR); + ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2); + + } else { + if (new_mask & AR5K_INT_FATAL) + int_mask |= (AR5K_IMR_SSERR | AR5K_IMR_MCABT + | AR5K_IMR_HIUERR | AR5K_IMR_DPERR); + + ath5k_hw_reg_write(ah, int_mask, AR5K_IMR); + } + + /* If RXNOFRM interrupt is masked disable it + * by setting AR5K_RXNOFRM to zero */ + if (!(new_mask & AR5K_INT_RXNOFRM)) + ath5k_hw_reg_write(ah, 0, AR5K_RXNOFRM); + + /* Store new interrupt mask */ + ah->ah_imr = new_mask; + + /* ..re-enable interrupts if AR5K_INT_GLOBAL is set */ + if (new_mask & AR5K_INT_GLOBAL) { + ath5k_hw_reg_write(ah, ah->ah_ier, AR5K_IER); + ath5k_hw_reg_read(ah, AR5K_IER); + } + + return old_mask; +} + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_eeprom.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_eeprom.c new file mode 100644 index 0000000..592714d --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_eeprom.c @@ -0,0 +1,1749 @@ +/* + * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> + * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> + * + * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +FILE_LICENCE ( MIT ); + +/*************************************\ +* EEPROM access functions and helpers * +\*************************************/ + +#include <unistd.h> +#include <stdlib.h> + +#include "ath5k.h" +#include "reg.h" +#include "base.h" + +/* + * Read from eeprom + */ +static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data) +{ + u32 status, timeout; + + /* + * Initialize EEPROM access + */ + if (ah->ah_version == AR5K_AR5210) { + AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE); + (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset)); + } else { + ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE); + AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD, + AR5K_EEPROM_CMD_READ); + } + + for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { + status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS); + if (status & AR5K_EEPROM_STAT_RDDONE) { + if (status & AR5K_EEPROM_STAT_RDERR) + return -EIO; + *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) & + 0xffff); + return 0; + } + udelay(15); + } + + return -ETIMEDOUT; +} + +/* + * Translate binary channel representation in EEPROM to frequency + */ +static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin, + unsigned int mode) +{ + u16 val; + + if (bin == AR5K_EEPROM_CHANNEL_DIS) + return bin; + + if (mode == AR5K_EEPROM_MODE_11A) { + if (ee->ee_version > AR5K_EEPROM_VERSION_3_2) + val = (5 * bin) + 4800; + else + val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : + (bin * 10) + 5100; + } else { + if (ee->ee_version > AR5K_EEPROM_VERSION_3_2) + val = bin + 2300; + else + val = bin + 2400; + } + + return val; +} + +/* + * Initialize eeprom & capabilities structs + */ +static int +ath5k_eeprom_init_header(struct ath5k_hw *ah) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + int ret; + u16 val; + + /* + * Read values from EEPROM and store them in the capability structure + */ + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header); + + /* Return if we have an old EEPROM */ + if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0) + return 0; + + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version), + ee_ant_gain); + + if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1); + + /* XXX: Don't know which versions include these two */ + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC2, ee_misc2); + + if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC3, ee_misc3); + + if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) { + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC4, ee_misc4); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC5, ee_misc5); + AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC6, ee_misc6); + } + } + + if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) { + AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val); + ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7; + ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7; + + AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val); + ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7; + ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7; + } + + return 0; +} + + +/* + * Read antenna infos from eeprom + */ +static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset, + unsigned int mode) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + u32 o = *offset; + u16 val; + int ret, i = 0; + + AR5K_EEPROM_READ(o++, val); + ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; + ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f; + ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; + + AR5K_EEPROM_READ(o++, val); + ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; + ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; + ee->ee_ant_control[mode][i++] = val & 0x3f; + + AR5K_EEPROM_READ(o++, val); + ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; + ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; + ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; + + AR5K_EEPROM_READ(o++, val); + ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; + ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; + ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; + ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; + + AR5K_EEPROM_READ(o++, val); + ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; + ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; + ee->ee_ant_control[mode][i++] = val & 0x3f; + + /* Get antenna modes */ + ah->ah_antenna[mode][0] = + (ee->ee_ant_control[mode][0] << 4); + ah->ah_antenna[mode][AR5K_ANT_FIXED_A] = + ee->ee_ant_control[mode][1] | + (ee->ee_ant_control[mode][2] << 6) | + (ee->ee_ant_control[mode][3] << 12) | + (ee->ee_ant_control[mode][4] << 18) | + (ee->ee_ant_control[mode][5] << 24); + ah->ah_antenna[mode][AR5K_ANT_FIXED_B] = + ee->ee_ant_control[mode][6] | + (ee->ee_ant_control[mode][7] << 6) | + (ee->ee_ant_control[mode][8] << 12) | + (ee->ee_ant_control[mode][9] << 18) | + (ee->ee_ant_control[mode][10] << 24); + + /* return new offset */ + *offset = o; + + return 0; +} + +/* + * Read supported modes and some mode-specific calibration data + * from eeprom + */ +static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset, + unsigned int mode) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + u32 o = *offset; + u16 val; + int ret; + + ee->ee_n_piers[mode] = 0; + AR5K_EEPROM_READ(o++, val); + ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); + switch(mode) { + case AR5K_EEPROM_MODE_11A: + ee->ee_ob[mode][3] = (val >> 5) & 0x7; + ee->ee_db[mode][3] = (val >> 2) & 0x7; + ee->ee_ob[mode][2] = (val << 1) & 0x7; + + AR5K_EEPROM_READ(o++, val); + ee->ee_ob[mode][2] |= (val >> 15) & 0x1; + ee->ee_db[mode][2] = (val >> 12) & 0x7; + ee->ee_ob[mode][1] = (val >> 9) & 0x7; + ee->ee_db[mode][1] = (val >> 6) & 0x7; + ee->ee_ob[mode][0] = (val >> 3) & 0x7; + ee->ee_db[mode][0] = val & 0x7; + break; + case AR5K_EEPROM_MODE_11G: + case AR5K_EEPROM_MODE_11B: + ee->ee_ob[mode][1] = (val >> 4) & 0x7; + ee->ee_db[mode][1] = val & 0x7; + break; + } + + AR5K_EEPROM_READ(o++, val); + ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; + ee->ee_thr_62[mode] = val & 0xff; + + if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) + ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28; + + AR5K_EEPROM_READ(o++, val); + ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; + ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; + + AR5K_EEPROM_READ(o++, val); + ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; + + if ((val & 0xff) & 0x80) + ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); + else + ee->ee_noise_floor_thr[mode] = val & 0xff; + + if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) + ee->ee_noise_floor_thr[mode] = + mode == AR5K_EEPROM_MODE_11A ? -54 : -1; + + AR5K_EEPROM_READ(o++, val); + ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; + ee->ee_x_gain[mode] = (val >> 1) & 0xf; + ee->ee_xpd[mode] = val & 0x1; + + if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) + ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; + + if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) { + AR5K_EEPROM_READ(o++, val); + ee->ee_false_detect[mode] = (val >> 6) & 0x7f; + + if (mode == AR5K_EEPROM_MODE_11A) + ee->ee_xr_power[mode] = val & 0x3f; + else { + ee->ee_ob[mode][0] = val & 0x7; + ee->ee_db[mode][0] = (val >> 3) & 0x7; + } + } + + if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) { + ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN; + ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA; + } else { + ee->ee_i_gain[mode] = (val >> 13) & 0x7; + + AR5K_EEPROM_READ(o++, val); + ee->ee_i_gain[mode] |= (val << 3) & 0x38; + + if (mode == AR5K_EEPROM_MODE_11G) { + ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff; + if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6) + ee->ee_scaled_cck_delta = (val >> 11) & 0x1f; + } + } + + if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 && + mode == AR5K_EEPROM_MODE_11A) { + ee->ee_i_cal[mode] = (val >> 8) & 0x3f; + ee->ee_q_cal[mode] = (val >> 3) & 0x1f; + } + + if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0) + goto done; + + /* Note: >= v5 have bg freq piers on another location + * so these freq piers are ignored for >= v5 (should be 0xff + * anyway) */ + switch(mode) { + case AR5K_EEPROM_MODE_11A: + if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1) + break; + + AR5K_EEPROM_READ(o++, val); + ee->ee_margin_tx_rx[mode] = val & 0x3f; + break; + case AR5K_EEPROM_MODE_11B: + AR5K_EEPROM_READ(o++, val); + + ee->ee_pwr_cal_b[0].freq = + ath5k_eeprom_bin2freq(ee, val & 0xff, mode); + if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS) + ee->ee_n_piers[mode]++; + + ee->ee_pwr_cal_b[1].freq = + ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); + if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS) + ee->ee_n_piers[mode]++; + + AR5K_EEPROM_READ(o++, val); + ee->ee_pwr_cal_b[2].freq = + ath5k_eeprom_bin2freq(ee, val & 0xff, mode); + if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS) + ee->ee_n_piers[mode]++; + + if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) + ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; + break; + case AR5K_EEPROM_MODE_11G: + AR5K_EEPROM_READ(o++, val); + + ee->ee_pwr_cal_g[0].freq = + ath5k_eeprom_bin2freq(ee, val & 0xff, mode); + if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS) + ee->ee_n_piers[mode]++; + + ee->ee_pwr_cal_g[1].freq = + ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); + if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS) + ee->ee_n_piers[mode]++; + + AR5K_EEPROM_READ(o++, val); + ee->ee_turbo_max_power[mode] = val & 0x7f; + ee->ee_xr_power[mode] = (val >> 7) & 0x3f; + + AR5K_EEPROM_READ(o++, val); + ee->ee_pwr_cal_g[2].freq = + ath5k_eeprom_bin2freq(ee, val & 0xff, mode); + if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS) + ee->ee_n_piers[mode]++; + + if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) + ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; + + AR5K_EEPROM_READ(o++, val); + ee->ee_i_cal[mode] = (val >> 8) & 0x3f; + ee->ee_q_cal[mode] = (val >> 3) & 0x1f; + + if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) { + AR5K_EEPROM_READ(o++, val); + ee->ee_cck_ofdm_gain_delta = val & 0xff; + } + break; + } + +done: + /* return new offset */ + *offset = o; + + return 0; +} + +/* + * Read turbo mode information on newer EEPROM versions + */ +static int +ath5k_eeprom_read_turbo_modes(struct ath5k_hw *ah, + u32 *offset, unsigned int mode) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + u32 o = *offset; + u16 val; + int ret; + + if (ee->ee_version < AR5K_EEPROM_VERSION_5_0) + return 0; + + switch (mode){ + case AR5K_EEPROM_MODE_11A: + ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f; + + ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7; + AR5K_EEPROM_READ(o++, val); + ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3; + ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f; + + ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f; + AR5K_EEPROM_READ(o++, val); + ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7; + ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff; + + if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2) + ee->ee_pd_gain_overlap = (val >> 9) & 0xf; + break; + case AR5K_EEPROM_MODE_11G: + ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f; + + ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7; + AR5K_EEPROM_READ(o++, val); + ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1; + ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f; + + ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f; + AR5K_EEPROM_READ(o++, val); + ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5; + ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff; + break; + } + + /* return new offset */ + *offset = o; + + return 0; +} + +/* Read mode-specific data (except power calibration data) */ +static int +ath5k_eeprom_init_modes(struct ath5k_hw *ah) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + u32 mode_offset[3]; + unsigned int mode; + u32 offset; + int ret; + + /* + * Get values for all modes + */ + mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version); + mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version); + mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version); + + ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] = + AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); + + for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) { + offset = mode_offset[mode]; + + ret = ath5k_eeprom_read_ants(ah, &offset, mode); + if (ret) + return ret; + + ret = ath5k_eeprom_read_modes(ah, &offset, mode); + if (ret) + return ret; + + ret = ath5k_eeprom_read_turbo_modes(ah, &offset, mode); + if (ret) + return ret; + } + + /* override for older eeprom versions for better performance */ + if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) { + ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15; + ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28; + ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28; + } + + return 0; +} + +/* Read the frequency piers for each mode (mostly used on newer eeproms with 0xff + * frequency mask) */ +static inline int +ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max, + struct ath5k_chan_pcal_info *pc, unsigned int mode) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + int o = *offset; + int i = 0; + u8 freq1, freq2; + int ret; + u16 val; + + ee->ee_n_piers[mode] = 0; + while(i < max) { + AR5K_EEPROM_READ(o++, val); + + freq1 = val & 0xff; + if (!freq1) + break; + + pc[i++].freq = ath5k_eeprom_bin2freq(ee, + freq1, mode); + ee->ee_n_piers[mode]++; + + freq2 = (val >> 8) & 0xff; + if (!freq2) + break; + + pc[i++].freq = ath5k_eeprom_bin2freq(ee, + freq2, mode); + ee->ee_n_piers[mode]++; + } + + /* return new offset */ + *offset = o; + + return 0; +} + +/* Read frequency piers for 802.11a */ +static int +ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a; + int i, ret; + u16 val; + u8 mask; + + if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) { + ath5k_eeprom_read_freq_list(ah, &offset, + AR5K_EEPROM_N_5GHZ_CHAN, pcal, + AR5K_EEPROM_MODE_11A); + } else { + mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version); + + AR5K_EEPROM_READ(offset++, val); + pcal[0].freq = (val >> 9) & mask; + pcal[1].freq = (val >> 2) & mask; + pcal[2].freq = (val << 5) & mask; + + AR5K_EEPROM_READ(offset++, val); + pcal[2].freq |= (val >> 11) & 0x1f; + pcal[3].freq = (val >> 4) & mask; + pcal[4].freq = (val << 3) & mask; + + AR5K_EEPROM_READ(offset++, val); + pcal[4].freq |= (val >> 13) & 0x7; + pcal[5].freq = (val >> 6) & mask; + pcal[6].freq = (val << 1) & mask; + + AR5K_EEPROM_READ(offset++, val); + pcal[6].freq |= (val >> 15) & 0x1; + pcal[7].freq = (val >> 8) & mask; + pcal[8].freq = (val >> 1) & mask; + pcal[9].freq = (val << 6) & mask; + + AR5K_EEPROM_READ(offset++, val); + pcal[9].freq |= (val >> 10) & 0x3f; + + /* Fixed number of piers */ + ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10; + + for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) { + pcal[i].freq = ath5k_eeprom_bin2freq(ee, + pcal[i].freq, AR5K_EEPROM_MODE_11A); + } + } + + return 0; +} + +/* Read frequency piers for 802.11bg on eeprom versions >= 5 and eemap >= 2 */ +static inline int +ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + struct ath5k_chan_pcal_info *pcal; + + switch(mode) { + case AR5K_EEPROM_MODE_11B: + pcal = ee->ee_pwr_cal_b; + break; + case AR5K_EEPROM_MODE_11G: + pcal = ee->ee_pwr_cal_g; + break; + default: + return -EINVAL; + } + + ath5k_eeprom_read_freq_list(ah, &offset, + AR5K_EEPROM_N_2GHZ_CHAN_2413, pcal, + mode); + + return 0; +} + +/* + * Read power calibration for RF5111 chips + * + * For RF5111 we have an XPD -eXternal Power Detector- curve + * for each calibrated channel. Each curve has 0,5dB Power steps + * on x axis and PCDAC steps (offsets) on y axis and looks like an + * exponential function. To recreate the curve we read 11 points + * here and interpolate later. + */ + +/* Used to match PCDAC steps with power values on RF5111 chips + * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC + * steps that match with the power values we read from eeprom. On + * older eeprom versions (< 3.2) these steps are equaly spaced at + * 10% of the pcdac curve -until the curve reaches it's maximum- + * (11 steps from 0 to 100%) but on newer eeprom versions (>= 3.2) + * these 11 steps are spaced in a different way. This function returns + * the pcdac steps based on eeprom version and curve min/max so that we + * can have pcdac/pwr points. + */ +static inline void +ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp) +{ + static const u16 intercepts3[] = + { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 }; + static const u16 intercepts3_2[] = + { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 }; + const u16 *ip; + unsigned i; + + if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2) + ip = intercepts3_2; + else + ip = intercepts3; + + for (i = 0; i < ARRAY_SIZE(intercepts3); i++) + vp[i] = (ip[i] * max + (100 - ip[i]) * min) / 100; +} + +/* Convert RF5111 specific data to generic raw data + * used by interpolation code */ +static int +ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode, + struct ath5k_chan_pcal_info *chinfo) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + struct ath5k_chan_pcal_info_rf5111 *pcinfo; + struct ath5k_pdgain_info *pd; + u8 pier, point, idx; + u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; + + /* Fill raw data for each calibration pier */ + for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { + + pcinfo = &chinfo[pier].rf5111_info; + + /* Allocate pd_curves for this cal pier */ + chinfo[pier].pd_curves = + calloc(AR5K_EEPROM_N_PD_CURVES, + sizeof(struct ath5k_pdgain_info)); + + if (!chinfo[pier].pd_curves) + return -ENOMEM; + + /* Only one curve for RF5111 + * find out which one and place + * in in pd_curves. + * Note: ee_x_gain is reversed here */ + for (idx = 0; idx < AR5K_EEPROM_N_PD_CURVES; idx++) { + + if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) { + pdgain_idx[0] = idx; + break; + } + } + + ee->ee_pd_gains[mode] = 1; + + pd = &chinfo[pier].pd_curves[idx]; + + pd->pd_points = AR5K_EEPROM_N_PWR_POINTS_5111; + + /* Allocate pd points for this curve */ + pd->pd_step = calloc(AR5K_EEPROM_N_PWR_POINTS_5111, sizeof(u8)); + if (!pd->pd_step) + return -ENOMEM; + + pd->pd_pwr = calloc(AR5K_EEPROM_N_PWR_POINTS_5111, sizeof(s16)); + if (!pd->pd_pwr) + return -ENOMEM; + + /* Fill raw dataset + * (convert power to 0.25dB units + * for RF5112 combatibility) */ + for (point = 0; point < pd->pd_points; point++) { + + /* Absolute values */ + pd->pd_pwr[point] = 2 * pcinfo->pwr[point]; + + /* Already sorted */ + pd->pd_step[point] = pcinfo->pcdac[point]; + } + + /* Set min/max pwr */ + chinfo[pier].min_pwr = pd->pd_pwr[0]; + chinfo[pier].max_pwr = pd->pd_pwr[10]; + + } + + return 0; +} + +/* Parse EEPROM data */ +static int +ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + struct ath5k_chan_pcal_info *pcal; + int offset, ret; + int i; + u16 val; + + offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); + switch(mode) { + case AR5K_EEPROM_MODE_11A: + if (!AR5K_EEPROM_HDR_11A(ee->ee_header)) + return 0; + + ret = ath5k_eeprom_init_11a_pcal_freq(ah, + offset + AR5K_EEPROM_GROUP1_OFFSET); + if (ret < 0) + return ret; + + offset += AR5K_EEPROM_GROUP2_OFFSET; + pcal = ee->ee_pwr_cal_a; + break; + case AR5K_EEPROM_MODE_11B: + if (!AR5K_EEPROM_HDR_11B(ee->ee_header) && + !AR5K_EEPROM_HDR_11G(ee->ee_header)) + return 0; + + pcal = ee->ee_pwr_cal_b; + offset += AR5K_EEPROM_GROUP3_OFFSET; + + /* fixed piers */ + pcal[0].freq = 2412; + pcal[1].freq = 2447; + pcal[2].freq = 2484; + ee->ee_n_piers[mode] = 3; + break; + case AR5K_EEPROM_MODE_11G: + if (!AR5K_EEPROM_HDR_11G(ee->ee_header)) + return 0; + + pcal = ee->ee_pwr_cal_g; + offset += AR5K_EEPROM_GROUP4_OFFSET; + + /* fixed piers */ + pcal[0].freq = 2312; + pcal[1].freq = 2412; + pcal[2].freq = 2484; + ee->ee_n_piers[mode] = 3; + break; + default: + return -EINVAL; + } + + for (i = 0; i < ee->ee_n_piers[mode]; i++) { + struct ath5k_chan_pcal_info_rf5111 *cdata = + &pcal[i].rf5111_info; + + AR5K_EEPROM_READ(offset++, val); + cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M); + cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M); + cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M); + + AR5K_EEPROM_READ(offset++, val); + cdata->pwr[0] |= ((val >> 14) & 0x3); + cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M); + cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M); + cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M); + + AR5K_EEPROM_READ(offset++, val); + cdata->pwr[3] |= ((val >> 12) & 0xf); + cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M); + cdata->pwr[5] = (val & AR5K_EEPROM_POWER_M); + + AR5K_EEPROM_READ(offset++, val); + cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M); + cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M); + cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M); + + AR5K_EEPROM_READ(offset++, val); + cdata->pwr[8] |= ((val >> 14) & 0x3); + cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M); + cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M); + + ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min, + cdata->pcdac_max, cdata->pcdac); + } + + return ath5k_eeprom_convert_pcal_info_5111(ah, mode, pcal); +} + + +/* + * Read power calibration for RF5112 chips + * + * For RF5112 we have 4 XPD -eXternal Power Detector- curves + * for each calibrated channel on 0, -6, -12 and -18dbm but we only + * use the higher (3) and the lower (0) curves. Each curve has 0.5dB + * power steps on x axis and PCDAC steps on y axis and looks like a + * linear function. To recreate the curve and pass the power values + * on hw, we read 4 points for xpd 0 (lower gain -> max power) + * and 3 points for xpd 3 (higher gain -> lower power) here and + * interpolate later. + * + * Note: Many vendors just use xpd 0 so xpd 3 is zeroed. + */ + +/* Convert RF5112 specific data to generic raw data + * used by interpolation code */ +static int +ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode, + struct ath5k_chan_pcal_info *chinfo) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + struct ath5k_chan_pcal_info_rf5112 *pcinfo; + u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; + unsigned int pier, pdg, point; + + /* Fill raw data for each calibration pier */ + for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { + + pcinfo = &chinfo[pier].rf5112_info; + + /* Allocate pd_curves for this cal pier */ + chinfo[pier].pd_curves = + calloc(AR5K_EEPROM_N_PD_CURVES, + sizeof(struct ath5k_pdgain_info)); + + if (!chinfo[pier].pd_curves) + return -ENOMEM; + + /* Fill pd_curves */ + for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) { + + u8 idx = pdgain_idx[pdg]; + struct ath5k_pdgain_info *pd = + &chinfo[pier].pd_curves[idx]; + + /* Lowest gain curve (max power) */ + if (pdg == 0) { + /* One more point for better accuracy */ + pd->pd_points = AR5K_EEPROM_N_XPD0_POINTS; + + /* Allocate pd points for this curve */ + pd->pd_step = calloc(pd->pd_points, sizeof(u8)); + + if (!pd->pd_step) + return -ENOMEM; + + pd->pd_pwr = calloc(pd->pd_points, sizeof(s16)); + + if (!pd->pd_pwr) + return -ENOMEM; + + + /* Fill raw dataset + * (all power levels are in 0.25dB units) */ + pd->pd_step[0] = pcinfo->pcdac_x0[0]; + pd->pd_pwr[0] = pcinfo->pwr_x0[0]; + + for (point = 1; point < pd->pd_points; + point++) { + /* Absolute values */ + pd->pd_pwr[point] = + pcinfo->pwr_x0[point]; + + /* Deltas */ + pd->pd_step[point] = + pd->pd_step[point - 1] + + pcinfo->pcdac_x0[point]; + } + + /* Set min power for this frequency */ + chinfo[pier].min_pwr = pd->pd_pwr[0]; + + /* Highest gain curve (min power) */ + } else if (pdg == 1) { + + pd->pd_points = AR5K_EEPROM_N_XPD3_POINTS; + + /* Allocate pd points for this curve */ + pd->pd_step = calloc(pd->pd_points, sizeof(u8)); + + if (!pd->pd_step) + return -ENOMEM; + + pd->pd_pwr = calloc(pd->pd_points, sizeof(s16)); + + if (!pd->pd_pwr) + return -ENOMEM; + + /* Fill raw dataset + * (all power levels are in 0.25dB units) */ + for (point = 0; point < pd->pd_points; + point++) { + /* Absolute values */ + pd->pd_pwr[point] = + pcinfo->pwr_x3[point]; + + /* Fixed points */ + pd->pd_step[point] = + pcinfo->pcdac_x3[point]; + } + + /* Since we have a higher gain curve + * override min power */ + chinfo[pier].min_pwr = pd->pd_pwr[0]; + } + } + } + + return 0; +} + +/* Parse EEPROM data */ +static int +ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info; + struct ath5k_chan_pcal_info *gen_chan_info; + u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; + u32 offset; + u8 i, c; + u16 val; + int ret; + u8 pd_gains = 0; + + /* Count how many curves we have and + * identify them (which one of the 4 + * available curves we have on each count). + * Curves are stored from lower (x0) to + * higher (x3) gain */ + for (i = 0; i < AR5K_EEPROM_N_PD_CURVES; i++) { + /* ee_x_gain[mode] is x gain mask */ + if ((ee->ee_x_gain[mode] >> i) & 0x1) + pdgain_idx[pd_gains++] = i; + } + ee->ee_pd_gains[mode] = pd_gains; + + if (pd_gains == 0 || pd_gains > 2) + return -EINVAL; + + switch (mode) { + case AR5K_EEPROM_MODE_11A: + /* + * Read 5GHz EEPROM channels + */ + offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); + ath5k_eeprom_init_11a_pcal_freq(ah, offset); + + offset += AR5K_EEPROM_GROUP2_OFFSET; + gen_chan_info = ee->ee_pwr_cal_a; + break; + case AR5K_EEPROM_MODE_11B: + offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); + if (AR5K_EEPROM_HDR_11A(ee->ee_header)) + offset += AR5K_EEPROM_GROUP3_OFFSET; + + /* NB: frequency piers parsed during mode init */ + gen_chan_info = ee->ee_pwr_cal_b; + break; + case AR5K_EEPROM_MODE_11G: + offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); + if (AR5K_EEPROM_HDR_11A(ee->ee_header)) + offset += AR5K_EEPROM_GROUP4_OFFSET; + else if (AR5K_EEPROM_HDR_11B(ee->ee_header)) + offset += AR5K_EEPROM_GROUP2_OFFSET; + + /* NB: frequency piers parsed during mode init */ + gen_chan_info = ee->ee_pwr_cal_g; + break; + default: + return -EINVAL; + } + + for (i = 0; i < ee->ee_n_piers[mode]; i++) { + chan_pcal_info = &gen_chan_info[i].rf5112_info; + + /* Power values in quarter dB + * for the lower xpd gain curve + * (0 dBm -> higher output power) */ + for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) { + AR5K_EEPROM_READ(offset++, val); + chan_pcal_info->pwr_x0[c] = (s8) (val & 0xff); + chan_pcal_info->pwr_x0[++c] = (s8) ((val >> 8) & 0xff); + } + + /* PCDAC steps + * corresponding to the above power + * measurements */ + AR5K_EEPROM_READ(offset++, val); + chan_pcal_info->pcdac_x0[1] = (val & 0x1f); + chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f); + chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f); + + /* Power values in quarter dB + * for the higher xpd gain curve + * (18 dBm -> lower output power) */ + AR5K_EEPROM_READ(offset++, val); + chan_pcal_info->pwr_x3[0] = (s8) (val & 0xff); + chan_pcal_info->pwr_x3[1] = (s8) ((val >> 8) & 0xff); + + AR5K_EEPROM_READ(offset++, val); + chan_pcal_info->pwr_x3[2] = (val & 0xff); + + /* PCDAC steps + * corresponding to the above power + * measurements (fixed) */ + chan_pcal_info->pcdac_x3[0] = 20; + chan_pcal_info->pcdac_x3[1] = 35; + chan_pcal_info->pcdac_x3[2] = 63; + + if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) { + chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0x3f); + + /* Last xpd0 power level is also channel maximum */ + gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3]; + } else { + chan_pcal_info->pcdac_x0[0] = 1; + gen_chan_info[i].max_pwr = (s8) ((val >> 8) & 0xff); + } + + } + + return ath5k_eeprom_convert_pcal_info_5112(ah, mode, gen_chan_info); +} + + +/* + * Read power calibration for RF2413 chips + * + * For RF2413 we have a Power to PDDAC table (Power Detector) + * instead of a PCDAC and 4 pd gain curves for each calibrated channel. + * Each curve has power on x axis in 0.5 db steps and PDDADC steps on y + * axis and looks like an exponential function like the RF5111 curve. + * + * To recreate the curves we read here the points and interpolate + * later. Note that in most cases only 2 (higher and lower) curves are + * used (like RF5112) but vendors have the oportunity to include all + * 4 curves on eeprom. The final curve (higher power) has an extra + * point for better accuracy like RF5112. + */ + +/* For RF2413 power calibration data doesn't start on a fixed location and + * if a mode is not supported, it's section is missing -not zeroed-. + * So we need to calculate the starting offset for each section by using + * these two functions */ + +/* Return the size of each section based on the mode and the number of pd + * gains available (maximum 4). */ +static inline unsigned int +ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode) +{ + static const unsigned int pdgains_size[] = { 4, 6, 9, 12 }; + unsigned int sz; + + sz = pdgains_size[ee->ee_pd_gains[mode] - 1]; + sz *= ee->ee_n_piers[mode]; + + return sz; +} + +/* Return the starting offset for a section based on the modes supported + * and each section's size. */ +static unsigned int +ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode) +{ + u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4); + + switch(mode) { + case AR5K_EEPROM_MODE_11G: + if (AR5K_EEPROM_HDR_11B(ee->ee_header)) + offset += ath5k_pdgains_size_2413(ee, + AR5K_EEPROM_MODE_11B) + + AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2; + /* fall through */ + case AR5K_EEPROM_MODE_11B: + if (AR5K_EEPROM_HDR_11A(ee->ee_header)) + offset += ath5k_pdgains_size_2413(ee, + AR5K_EEPROM_MODE_11A) + + AR5K_EEPROM_N_5GHZ_CHAN / 2; + /* fall through */ + case AR5K_EEPROM_MODE_11A: + break; + default: + break; + } + + return offset; +} + +/* Convert RF2413 specific data to generic raw data + * used by interpolation code */ +static int +ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode, + struct ath5k_chan_pcal_info *chinfo) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + struct ath5k_chan_pcal_info_rf2413 *pcinfo; + u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; + unsigned int pier, point; + int pdg; + + /* Fill raw data for each calibration pier */ + for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { + + pcinfo = &chinfo[pier].rf2413_info; + + /* Allocate pd_curves for this cal pier */ + chinfo[pier].pd_curves = + calloc(AR5K_EEPROM_N_PD_CURVES, + sizeof(struct ath5k_pdgain_info)); + + if (!chinfo[pier].pd_curves) + return -ENOMEM; + + /* Fill pd_curves */ + for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) { + + u8 idx = pdgain_idx[pdg]; + struct ath5k_pdgain_info *pd = + &chinfo[pier].pd_curves[idx]; + + /* One more point for the highest power + * curve (lowest gain) */ + if (pdg == ee->ee_pd_gains[mode] - 1) + pd->pd_points = AR5K_EEPROM_N_PD_POINTS; + else + pd->pd_points = AR5K_EEPROM_N_PD_POINTS - 1; + + /* Allocate pd points for this curve */ + pd->pd_step = calloc(pd->pd_points, sizeof(u8)); + + if (!pd->pd_step) + return -ENOMEM; + + pd->pd_pwr = calloc(pd->pd_points, sizeof(s16)); + + if (!pd->pd_pwr) + return -ENOMEM; + + /* Fill raw dataset + * convert all pwr levels to + * quarter dB for RF5112 combatibility */ + pd->pd_step[0] = pcinfo->pddac_i[pdg]; + pd->pd_pwr[0] = 4 * pcinfo->pwr_i[pdg]; + + for (point = 1; point < pd->pd_points; point++) { + + pd->pd_pwr[point] = pd->pd_pwr[point - 1] + + 2 * pcinfo->pwr[pdg][point - 1]; + + pd->pd_step[point] = pd->pd_step[point - 1] + + pcinfo->pddac[pdg][point - 1]; + + } + + /* Highest gain curve -> min power */ + if (pdg == 0) + chinfo[pier].min_pwr = pd->pd_pwr[0]; + + /* Lowest gain curve -> max power */ + if (pdg == ee->ee_pd_gains[mode] - 1) + chinfo[pier].max_pwr = + pd->pd_pwr[pd->pd_points - 1]; + } + } + + return 0; +} + +/* Parse EEPROM data */ +static int +ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + struct ath5k_chan_pcal_info_rf2413 *pcinfo; + struct ath5k_chan_pcal_info *chinfo; + u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; + u32 offset; + int idx, i, ret; + u16 val; + u8 pd_gains = 0; + + /* Count how many curves we have and + * identify them (which one of the 4 + * available curves we have on each count). + * Curves are stored from higher to + * lower gain so we go backwards */ + for (idx = AR5K_EEPROM_N_PD_CURVES - 1; idx >= 0; idx--) { + /* ee_x_gain[mode] is x gain mask */ + if ((ee->ee_x_gain[mode] >> idx) & 0x1) + pdgain_idx[pd_gains++] = idx; + + } + ee->ee_pd_gains[mode] = pd_gains; + + if (pd_gains == 0) + return -EINVAL; + + offset = ath5k_cal_data_offset_2413(ee, mode); + switch (mode) { + case AR5K_EEPROM_MODE_11A: + if (!AR5K_EEPROM_HDR_11A(ee->ee_header)) + return 0; + + ath5k_eeprom_init_11a_pcal_freq(ah, offset); + offset += AR5K_EEPROM_N_5GHZ_CHAN / 2; + chinfo = ee->ee_pwr_cal_a; + break; + case AR5K_EEPROM_MODE_11B: + if (!AR5K_EEPROM_HDR_11B(ee->ee_header)) + return 0; + + ath5k_eeprom_init_11bg_2413(ah, mode, offset); + offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2; + chinfo = ee->ee_pwr_cal_b; + break; + case AR5K_EEPROM_MODE_11G: + if (!AR5K_EEPROM_HDR_11G(ee->ee_header)) + return 0; + + ath5k_eeprom_init_11bg_2413(ah, mode, offset); + offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2; + chinfo = ee->ee_pwr_cal_g; + break; + default: + return -EINVAL; + } + + for (i = 0; i < ee->ee_n_piers[mode]; i++) { + pcinfo = &chinfo[i].rf2413_info; + + /* + * Read pwr_i, pddac_i and the first + * 2 pd points (pwr, pddac) + */ + AR5K_EEPROM_READ(offset++, val); + pcinfo->pwr_i[0] = val & 0x1f; + pcinfo->pddac_i[0] = (val >> 5) & 0x7f; + pcinfo->pwr[0][0] = (val >> 12) & 0xf; + + AR5K_EEPROM_READ(offset++, val); + pcinfo->pddac[0][0] = val & 0x3f; + pcinfo->pwr[0][1] = (val >> 6) & 0xf; + pcinfo->pddac[0][1] = (val >> 10) & 0x3f; + + AR5K_EEPROM_READ(offset++, val); + pcinfo->pwr[0][2] = val & 0xf; + pcinfo->pddac[0][2] = (val >> 4) & 0x3f; + + pcinfo->pwr[0][3] = 0; + pcinfo->pddac[0][3] = 0; + + if (pd_gains > 1) { + /* + * Pd gain 0 is not the last pd gain + * so it only has 2 pd points. + * Continue wih pd gain 1. + */ + pcinfo->pwr_i[1] = (val >> 10) & 0x1f; + + pcinfo->pddac_i[1] = (val >> 15) & 0x1; + AR5K_EEPROM_READ(offset++, val); + pcinfo->pddac_i[1] |= (val & 0x3F) << 1; + + pcinfo->pwr[1][0] = (val >> 6) & 0xf; + pcinfo->pddac[1][0] = (val >> 10) & 0x3f; + + AR5K_EEPROM_READ(offset++, val); + pcinfo->pwr[1][1] = val & 0xf; + pcinfo->pddac[1][1] = (val >> 4) & 0x3f; + pcinfo->pwr[1][2] = (val >> 10) & 0xf; + + pcinfo->pddac[1][2] = (val >> 14) & 0x3; + AR5K_EEPROM_READ(offset++, val); + pcinfo->pddac[1][2] |= (val & 0xF) << 2; + + pcinfo->pwr[1][3] = 0; + pcinfo->pddac[1][3] = 0; + } else if (pd_gains == 1) { + /* + * Pd gain 0 is the last one so + * read the extra point. + */ + pcinfo->pwr[0][3] = (val >> 10) & 0xf; + + pcinfo->pddac[0][3] = (val >> 14) & 0x3; + AR5K_EEPROM_READ(offset++, val); + pcinfo->pddac[0][3] |= (val & 0xF) << 2; + } + + /* + * Proceed with the other pd_gains + * as above. + */ + if (pd_gains > 2) { + pcinfo->pwr_i[2] = (val >> 4) & 0x1f; + pcinfo->pddac_i[2] = (val >> 9) & 0x7f; + + AR5K_EEPROM_READ(offset++, val); + pcinfo->pwr[2][0] = (val >> 0) & 0xf; + pcinfo->pddac[2][0] = (val >> 4) & 0x3f; + pcinfo->pwr[2][1] = (val >> 10) & 0xf; + + pcinfo->pddac[2][1] = (val >> 14) & 0x3; + AR5K_EEPROM_READ(offset++, val); + pcinfo->pddac[2][1] |= (val & 0xF) << 2; + + pcinfo->pwr[2][2] = (val >> 4) & 0xf; + pcinfo->pddac[2][2] = (val >> 8) & 0x3f; + + pcinfo->pwr[2][3] = 0; + pcinfo->pddac[2][3] = 0; + } else if (pd_gains == 2) { + pcinfo->pwr[1][3] = (val >> 4) & 0xf; + pcinfo->pddac[1][3] = (val >> 8) & 0x3f; + } + + if (pd_gains > 3) { + pcinfo->pwr_i[3] = (val >> 14) & 0x3; + AR5K_EEPROM_READ(offset++, val); + pcinfo->pwr_i[3] |= ((val >> 0) & 0x7) << 2; + + pcinfo->pddac_i[3] = (val >> 3) & 0x7f; + pcinfo->pwr[3][0] = (val >> 10) & 0xf; + pcinfo->pddac[3][0] = (val >> 14) & 0x3; + + AR5K_EEPROM_READ(offset++, val); + pcinfo->pddac[3][0] |= (val & 0xF) << 2; + pcinfo->pwr[3][1] = (val >> 4) & 0xf; + pcinfo->pddac[3][1] = (val >> 8) & 0x3f; + + pcinfo->pwr[3][2] = (val >> 14) & 0x3; + AR5K_EEPROM_READ(offset++, val); + pcinfo->pwr[3][2] |= ((val >> 0) & 0x3) << 2; + + pcinfo->pddac[3][2] = (val >> 2) & 0x3f; + pcinfo->pwr[3][3] = (val >> 8) & 0xf; + + pcinfo->pddac[3][3] = (val >> 12) & 0xF; + AR5K_EEPROM_READ(offset++, val); + pcinfo->pddac[3][3] |= ((val >> 0) & 0x3) << 4; + } else if (pd_gains == 3) { + pcinfo->pwr[2][3] = (val >> 14) & 0x3; + AR5K_EEPROM_READ(offset++, val); + pcinfo->pwr[2][3] |= ((val >> 0) & 0x3) << 2; + + pcinfo->pddac[2][3] = (val >> 2) & 0x3f; + } + } + + return ath5k_eeprom_convert_pcal_info_2413(ah, mode, chinfo); +} + + +/* + * Read per rate target power (this is the maximum tx power + * supported by the card). This info is used when setting + * tx power, no matter the channel. + * + * This also works for v5 EEPROMs. + */ +static int +ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + struct ath5k_rate_pcal_info *rate_pcal_info; + u8 *rate_target_pwr_num; + u32 offset; + u16 val; + int ret, i; + + offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1); + rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode]; + switch (mode) { + case AR5K_EEPROM_MODE_11A: + offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version); + rate_pcal_info = ee->ee_rate_tpwr_a; + ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_CHAN; + break; + case AR5K_EEPROM_MODE_11B: + offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version); + rate_pcal_info = ee->ee_rate_tpwr_b; + ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */ + break; + case AR5K_EEPROM_MODE_11G: + offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version); + rate_pcal_info = ee->ee_rate_tpwr_g; + ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN; + break; + default: + return -EINVAL; + } + + /* Different freq mask for older eeproms (<= v3.2) */ + if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) { + for (i = 0; i < (*rate_target_pwr_num); i++) { + AR5K_EEPROM_READ(offset++, val); + rate_pcal_info[i].freq = + ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode); + + rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f); + rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f; + + AR5K_EEPROM_READ(offset++, val); + + if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS || + val == 0) { + (*rate_target_pwr_num) = i; + break; + } + + rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7); + rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f); + rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f); + } + } else { + for (i = 0; i < (*rate_target_pwr_num); i++) { + AR5K_EEPROM_READ(offset++, val); + rate_pcal_info[i].freq = + ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); + + rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f); + rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f; + + AR5K_EEPROM_READ(offset++, val); + + if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS || + val == 0) { + (*rate_target_pwr_num) = i; + break; + } + + rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf; + rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f); + rate_pcal_info[i].target_power_54 = (val & 0x3f); + } + } + + return 0; +} + +/* + * Read per channel calibration info from EEPROM + * + * This info is used to calibrate the baseband power table. Imagine + * that for each channel there is a power curve that's hw specific + * (depends on amplifier etc) and we try to "correct" this curve using + * offests we pass on to phy chip (baseband -> before amplifier) so that + * it can use accurate power values when setting tx power (takes amplifier's + * performance on each channel into account). + * + * EEPROM provides us with the offsets for some pre-calibrated channels + * and we have to interpolate to create the full table for these channels and + * also the table for any channel. + */ +static int +ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + int (*read_pcal)(struct ath5k_hw *hw, int mode); + int mode; + int err; + + if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) && + (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1)) + read_pcal = ath5k_eeprom_read_pcal_info_5112; + else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) && + (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2)) + read_pcal = ath5k_eeprom_read_pcal_info_2413; + else + read_pcal = ath5k_eeprom_read_pcal_info_5111; + + + for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; + mode++) { + err = read_pcal(ah, mode); + if (err) + return err; + + err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode); + if (err < 0) + return err; + } + + return 0; +} + +static int +ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + struct ath5k_chan_pcal_info *chinfo; + u8 pier, pdg; + + switch (mode) { + case AR5K_EEPROM_MODE_11A: + if (!AR5K_EEPROM_HDR_11A(ee->ee_header)) + return 0; + chinfo = ee->ee_pwr_cal_a; + break; + case AR5K_EEPROM_MODE_11B: + if (!AR5K_EEPROM_HDR_11B(ee->ee_header)) + return 0; + chinfo = ee->ee_pwr_cal_b; + break; + case AR5K_EEPROM_MODE_11G: + if (!AR5K_EEPROM_HDR_11G(ee->ee_header)) + return 0; + chinfo = ee->ee_pwr_cal_g; + break; + default: + return -EINVAL; + } + + for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { + if (!chinfo[pier].pd_curves) + continue; + + for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) { + struct ath5k_pdgain_info *pd = + &chinfo[pier].pd_curves[pdg]; + + if (pd != NULL) { + free(pd->pd_step); + free(pd->pd_pwr); + } + } + + free(chinfo[pier].pd_curves); + } + + return 0; +} + +void +ath5k_eeprom_detach(struct ath5k_hw *ah) +{ + u8 mode; + + for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) + ath5k_eeprom_free_pcal_info(ah, mode); +} + +/* Read conformance test limits used for regulatory control */ +static int +ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + struct ath5k_edge_power *rep; + unsigned int fmask, pmask; + unsigned int ctl_mode; + int ret, i, j; + u32 offset; + u16 val; + + pmask = AR5K_EEPROM_POWER_M; + fmask = AR5K_EEPROM_FREQ_M(ee->ee_version); + offset = AR5K_EEPROM_CTL(ee->ee_version); + ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version); + for (i = 0; i < ee->ee_ctls; i += 2) { + AR5K_EEPROM_READ(offset++, val); + ee->ee_ctl[i] = (val >> 8) & 0xff; + ee->ee_ctl[i + 1] = val & 0xff; + } + + offset = AR5K_EEPROM_GROUP8_OFFSET; + if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0) + offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) - + AR5K_EEPROM_GROUP5_OFFSET; + else + offset += AR5K_EEPROM_GROUPS_START(ee->ee_version); + + rep = ee->ee_ctl_pwr; + for(i = 0; i < ee->ee_ctls; i++) { + switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) { + case AR5K_CTL_11A: + case AR5K_CTL_TURBO: + ctl_mode = AR5K_EEPROM_MODE_11A; + break; + default: + ctl_mode = AR5K_EEPROM_MODE_11G; + break; + } + if (ee->ee_ctl[i] == 0) { + if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) + offset += 8; + else + offset += 7; + rep += AR5K_EEPROM_N_EDGES; + continue; + } + if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) { + for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) { + AR5K_EEPROM_READ(offset++, val); + rep[j].freq = (val >> 8) & fmask; + rep[j + 1].freq = val & fmask; + } + for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) { + AR5K_EEPROM_READ(offset++, val); + rep[j].edge = (val >> 8) & pmask; + rep[j].flag = (val >> 14) & 1; + rep[j + 1].edge = val & pmask; + rep[j + 1].flag = (val >> 6) & 1; + } + } else { + AR5K_EEPROM_READ(offset++, val); + rep[0].freq = (val >> 9) & fmask; + rep[1].freq = (val >> 2) & fmask; + rep[2].freq = (val << 5) & fmask; + + AR5K_EEPROM_READ(offset++, val); + rep[2].freq |= (val >> 11) & 0x1f; + rep[3].freq = (val >> 4) & fmask; + rep[4].freq = (val << 3) & fmask; + + AR5K_EEPROM_READ(offset++, val); + rep[4].freq |= (val >> 13) & 0x7; + rep[5].freq = (val >> 6) & fmask; + rep[6].freq = (val << 1) & fmask; + + AR5K_EEPROM_READ(offset++, val); + rep[6].freq |= (val >> 15) & 0x1; + rep[7].freq = (val >> 8) & fmask; + + rep[0].edge = (val >> 2) & pmask; + rep[1].edge = (val << 4) & pmask; + + AR5K_EEPROM_READ(offset++, val); + rep[1].edge |= (val >> 12) & 0xf; + rep[2].edge = (val >> 6) & pmask; + rep[3].edge = val & pmask; + + AR5K_EEPROM_READ(offset++, val); + rep[4].edge = (val >> 10) & pmask; + rep[5].edge = (val >> 4) & pmask; + rep[6].edge = (val << 2) & pmask; + + AR5K_EEPROM_READ(offset++, val); + rep[6].edge |= (val >> 14) & 0x3; + rep[7].edge = (val >> 8) & pmask; + } + for (j = 0; j < AR5K_EEPROM_N_EDGES; j++) { + rep[j].freq = ath5k_eeprom_bin2freq(ee, + rep[j].freq, ctl_mode); + } + rep += AR5K_EEPROM_N_EDGES; + } + + return 0; +} + + +/* + * Initialize eeprom power tables + */ +int +ath5k_eeprom_init(struct ath5k_hw *ah) +{ + int err; + + err = ath5k_eeprom_init_header(ah); + if (err < 0) + return err; + + err = ath5k_eeprom_init_modes(ah); + if (err < 0) + return err; + + err = ath5k_eeprom_read_pcal_info(ah); + if (err < 0) + return err; + + err = ath5k_eeprom_read_ctl_info(ah); + if (err < 0) + return err; + + return 0; +} + +/* + * Read the MAC address from eeprom + */ +int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac) +{ + u8 mac_d[ETH_ALEN] = {}; + u32 total, offset; + u16 data; + int octet, ret; + + ret = ath5k_hw_eeprom_read(ah, 0x20, &data); + if (ret) + return ret; + + for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { + ret = ath5k_hw_eeprom_read(ah, offset, &data); + if (ret) + return ret; + + total += data; + mac_d[octet + 1] = data & 0xff; + mac_d[octet] = data >> 8; + octet += 2; + } + + if (!total || total == 3 * 0xffff) + return -EINVAL; + + memcpy(mac, mac_d, ETH_ALEN); + + return 0; +} + +int ath5k_eeprom_is_hb63(struct ath5k_hw *ah) +{ + u16 data; + + ath5k_hw_eeprom_read(ah, AR5K_EEPROM_IS_HB63, &data); + + if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && data) + return 1; + else + return 0; +} + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_gpio.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_gpio.c new file mode 100644 index 0000000..0e8a3e6 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_gpio.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> + * + * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +FILE_LICENCE ( MIT ); + +/****************\ + GPIO Functions +\****************/ + +#include "ath5k.h" +#include "reg.h" +#include "base.h" + +/* + * Set GPIO inputs + */ +int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio) +{ + if (gpio >= AR5K_NUM_GPIO) + return -EINVAL; + + ath5k_hw_reg_write(ah, + (ath5k_hw_reg_read(ah, AR5K_GPIOCR) & ~AR5K_GPIOCR_OUT(gpio)) + | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR); + + return 0; +} + +/* + * Set GPIO outputs + */ +int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio) +{ + if (gpio >= AR5K_NUM_GPIO) + return -EINVAL; + + ath5k_hw_reg_write(ah, + (ath5k_hw_reg_read(ah, AR5K_GPIOCR) & ~AR5K_GPIOCR_OUT(gpio)) + | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR); + + return 0; +} + +/* + * Get GPIO state + */ +u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio) +{ + if (gpio >= AR5K_NUM_GPIO) + return 0xffffffff; + + /* GPIO input magic */ + return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) & + 0x1; +} + +/* + * Set GPIO state + */ +int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val) +{ + u32 data; + + if (gpio >= AR5K_NUM_GPIO) + return -EINVAL; + + /* GPIO output magic */ + data = ath5k_hw_reg_read(ah, AR5K_GPIODO); + + data &= ~(1 << gpio); + data |= (val & 1) << gpio; + + ath5k_hw_reg_write(ah, data, AR5K_GPIODO); + + return 0; +} + +/* + * Initialize the GPIO interrupt (RFKill switch) + */ +void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, + u32 interrupt_level) +{ + u32 data; + + if (gpio >= AR5K_NUM_GPIO) + return; + + /* + * Set the GPIO interrupt + */ + data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) & + ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH | + AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) | + (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA); + + ath5k_hw_reg_write(ah, interrupt_level ? data : + (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR); + + ah->ah_imr |= AR5K_IMR_GPIO; + + /* Enable GPIO interrupts */ + AR5K_REG_ENABLE_BITS(ah, AR5K_PIMR, AR5K_IMR_GPIO); +} + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_initvals.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_initvals.c new file mode 100644 index 0000000..5911be8 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_initvals.c @@ -0,0 +1,1560 @@ +/* + * Initial register settings functions + * + * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> + * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> + * + * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +FILE_LICENCE ( MIT ); + +#include <unistd.h> + +#include "ath5k.h" +#include "reg.h" +#include "base.h" + +/* + * Mode-independent initial register writes + */ + +struct ath5k_ini { + u16 ini_register; + u32 ini_value; + + enum { + AR5K_INI_WRITE = 0, /* Default */ + AR5K_INI_READ = 1, /* Cleared on read */ + } ini_mode; +}; + +/* + * Mode specific initial register values + */ + +struct ath5k_ini_mode { + u16 mode_register; + u32 mode_value[5]; +}; + +/* Initial register settings for AR5210 */ +static const struct ath5k_ini ar5210_ini[] = { + /* PCU and MAC registers */ + { AR5K_NOQCU_TXDP0, 0, AR5K_INI_WRITE }, + { AR5K_NOQCU_TXDP1, 0, AR5K_INI_WRITE }, + { AR5K_RXDP, 0, AR5K_INI_WRITE }, + { AR5K_CR, 0, AR5K_INI_WRITE }, + { AR5K_ISR, 0, AR5K_INI_READ }, + { AR5K_IMR, 0, AR5K_INI_WRITE }, + { AR5K_IER, AR5K_IER_DISABLE, AR5K_INI_WRITE }, + { AR5K_BSR, 0, AR5K_INI_READ }, + { AR5K_TXCFG, AR5K_DMASIZE_128B, AR5K_INI_WRITE }, + { AR5K_RXCFG, AR5K_DMASIZE_128B, AR5K_INI_WRITE }, + { AR5K_CFG, AR5K_INIT_CFG, AR5K_INI_WRITE }, + { AR5K_TOPS, 8, AR5K_INI_WRITE }, + { AR5K_RXNOFRM, 8, AR5K_INI_WRITE }, + { AR5K_RPGTO, 0, AR5K_INI_WRITE }, + { AR5K_TXNOFRM, 0, AR5K_INI_WRITE }, + { AR5K_SFR, 0, AR5K_INI_WRITE }, + { AR5K_MIBC, 0, AR5K_INI_WRITE }, + { AR5K_MISC, 0, AR5K_INI_WRITE }, + { AR5K_RX_FILTER_5210, 0, AR5K_INI_WRITE }, + { AR5K_MCAST_FILTER0_5210, 0, AR5K_INI_WRITE }, + { AR5K_MCAST_FILTER1_5210, 0, AR5K_INI_WRITE }, + { AR5K_TX_MASK0, 0, AR5K_INI_WRITE }, + { AR5K_TX_MASK1, 0, AR5K_INI_WRITE }, + { AR5K_CLR_TMASK, 0, AR5K_INI_WRITE }, + { AR5K_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES, AR5K_INI_WRITE }, + { AR5K_DIAG_SW_5210, 0, AR5K_INI_WRITE }, + { AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES, AR5K_INI_WRITE }, + { AR5K_TSF_L32_5210, 0, AR5K_INI_WRITE }, + { AR5K_TIMER0_5210, 0, AR5K_INI_WRITE }, + { AR5K_TIMER1_5210, 0xffffffff, AR5K_INI_WRITE }, + { AR5K_TIMER2_5210, 0xffffffff, AR5K_INI_WRITE }, + { AR5K_TIMER3_5210, 1, AR5K_INI_WRITE }, + { AR5K_CFP_DUR_5210, 0, AR5K_INI_WRITE }, + { AR5K_CFP_PERIOD_5210, 0, AR5K_INI_WRITE }, + /* PHY registers */ + { AR5K_PHY(0), 0x00000047, AR5K_INI_WRITE }, + { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(3), 0x09848ea6, AR5K_INI_WRITE }, + { AR5K_PHY(4), 0x3d32e000, AR5K_INI_WRITE }, + { AR5K_PHY(5), 0x0000076b, AR5K_INI_WRITE }, + { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE, AR5K_INI_WRITE }, + { AR5K_PHY(8), 0x02020200, AR5K_INI_WRITE }, + { AR5K_PHY(9), 0x00000e0e, AR5K_INI_WRITE }, + { AR5K_PHY(10), 0x0a020201, AR5K_INI_WRITE }, + { AR5K_PHY(11), 0x00036ffc, AR5K_INI_WRITE }, + { AR5K_PHY(12), 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(13), 0x00000e0e, AR5K_INI_WRITE }, + { AR5K_PHY(14), 0x00000007, AR5K_INI_WRITE }, + { AR5K_PHY(15), 0x00020100, AR5K_INI_WRITE }, + { AR5K_PHY(16), 0x89630000, AR5K_INI_WRITE }, + { AR5K_PHY(17), 0x1372169c, AR5K_INI_WRITE }, + { AR5K_PHY(18), 0x0018b633, AR5K_INI_WRITE }, + { AR5K_PHY(19), 0x1284613c, AR5K_INI_WRITE }, + { AR5K_PHY(20), 0x0de8b8e0, AR5K_INI_WRITE }, + { AR5K_PHY(21), 0x00074859, AR5K_INI_WRITE }, + { AR5K_PHY(22), 0x7e80beba, AR5K_INI_WRITE }, + { AR5K_PHY(23), 0x313a665e, AR5K_INI_WRITE }, + { AR5K_PHY_AGCCTL, 0x00001d08, AR5K_INI_WRITE }, + { AR5K_PHY(25), 0x0001ce00, AR5K_INI_WRITE }, + { AR5K_PHY(26), 0x409a4190, AR5K_INI_WRITE }, + { AR5K_PHY(28), 0x0000000f, AR5K_INI_WRITE }, + { AR5K_PHY(29), 0x00000080, AR5K_INI_WRITE }, + { AR5K_PHY(30), 0x00000004, AR5K_INI_WRITE }, + { AR5K_PHY(31), 0x00000018, AR5K_INI_WRITE }, /* 0x987c */ + { AR5K_PHY(64), 0x00000000, AR5K_INI_WRITE }, /* 0x9900 */ + { AR5K_PHY(65), 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(66), 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(67), 0x00800000, AR5K_INI_WRITE }, + { AR5K_PHY(68), 0x00000003, AR5K_INI_WRITE }, + /* BB gain table (64bytes) */ + { AR5K_BB_GAIN(0), 0x00000000, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(1), 0x00000020, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(2), 0x00000010, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(3), 0x00000030, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(4), 0x00000008, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(5), 0x00000028, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(6), 0x00000028, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(7), 0x00000004, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(8), 0x00000024, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(9), 0x00000014, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(10), 0x00000034, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(11), 0x0000000c, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(12), 0x0000002c, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(13), 0x00000002, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(14), 0x00000022, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(15), 0x00000012, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(16), 0x00000032, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(17), 0x0000000a, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(18), 0x0000002a, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(19), 0x00000001, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(20), 0x00000021, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(21), 0x00000011, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(22), 0x00000031, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(23), 0x00000009, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(24), 0x00000029, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(25), 0x00000005, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(26), 0x00000025, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(27), 0x00000015, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(28), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(29), 0x0000000d, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(30), 0x0000002d, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(31), 0x00000003, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(32), 0x00000023, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(33), 0x00000013, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(34), 0x00000033, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(35), 0x0000000b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(36), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(37), 0x00000007, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(38), 0x00000027, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(39), 0x00000017, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(40), 0x00000037, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(41), 0x0000000f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(42), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(43), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(44), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(45), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(46), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(47), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(48), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(49), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(50), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(51), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(52), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(53), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(54), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(55), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(56), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(57), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(58), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(59), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(60), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(61), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(62), 0x0000002f, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(63), 0x0000002f, AR5K_INI_WRITE }, + /* 5110 RF gain table (64btes) */ + { AR5K_RF_GAIN(0), 0x0000001d, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(1), 0x0000005d, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(2), 0x0000009d, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(3), 0x000000dd, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(4), 0x0000011d, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(5), 0x00000021, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(6), 0x00000061, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(7), 0x000000a1, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(8), 0x000000e1, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(9), 0x00000031, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(10), 0x00000071, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(11), 0x000000b1, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(12), 0x0000001c, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(13), 0x0000005c, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(14), 0x00000029, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(15), 0x00000069, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(16), 0x000000a9, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(17), 0x00000020, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(18), 0x00000019, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(19), 0x00000059, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(20), 0x00000099, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(21), 0x00000030, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(22), 0x00000005, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(23), 0x00000025, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(24), 0x00000065, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(25), 0x000000a5, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(26), 0x00000028, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(27), 0x00000068, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(28), 0x0000001f, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(29), 0x0000001e, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(30), 0x00000018, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(31), 0x00000058, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(32), 0x00000098, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(33), 0x00000003, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(34), 0x00000004, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(35), 0x00000044, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(36), 0x00000084, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(37), 0x00000013, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(38), 0x00000012, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(39), 0x00000052, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(40), 0x00000092, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(41), 0x000000d2, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(42), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(43), 0x0000002a, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(44), 0x0000006a, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(45), 0x000000aa, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(46), 0x0000001b, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(47), 0x0000001a, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(48), 0x0000005a, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(49), 0x0000009a, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(50), 0x000000da, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(51), 0x00000006, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(52), 0x00000006, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(53), 0x00000006, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(54), 0x00000006, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(55), 0x00000006, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(56), 0x00000006, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(57), 0x00000006, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(58), 0x00000006, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(59), 0x00000006, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(60), 0x00000006, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(61), 0x00000006, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(62), 0x00000006, AR5K_INI_WRITE }, + { AR5K_RF_GAIN(63), 0x00000006, AR5K_INI_WRITE }, + /* PHY activation */ + { AR5K_PHY(53), 0x00000020, AR5K_INI_WRITE }, + { AR5K_PHY(51), 0x00000004, AR5K_INI_WRITE }, + { AR5K_PHY(50), 0x00060106, AR5K_INI_WRITE }, + { AR5K_PHY(39), 0x0000006d, AR5K_INI_WRITE }, + { AR5K_PHY(48), 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(52), 0x00000014, AR5K_INI_WRITE }, + { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE, AR5K_INI_WRITE }, +}; + +/* Initial register settings for AR5211 */ +static const struct ath5k_ini ar5211_ini[] = { + { AR5K_RXDP, 0x00000000, AR5K_INI_WRITE }, + { AR5K_RTSD0, 0x84849c9c, AR5K_INI_WRITE }, + { AR5K_RTSD1, 0x7c7c7c7c, AR5K_INI_WRITE }, + { AR5K_RXCFG, 0x00000005, AR5K_INI_WRITE }, + { AR5K_MIBC, 0x00000000, AR5K_INI_WRITE }, + { AR5K_TOPS, 0x00000008, AR5K_INI_WRITE }, + { AR5K_RXNOFRM, 0x00000008, AR5K_INI_WRITE }, + { AR5K_TXNOFRM, 0x00000010, AR5K_INI_WRITE }, + { AR5K_RPGTO, 0x00000000, AR5K_INI_WRITE }, + { AR5K_RFCNT, 0x0000001f, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(0), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(1), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(2), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(3), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(4), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(5), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(6), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(7), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(8), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(9), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE }, + { AR5K_STA_ID1, 0x00000000, AR5K_INI_WRITE }, + { AR5K_BSS_ID0, 0x00000000, AR5K_INI_WRITE }, + { AR5K_BSS_ID1, 0x00000000, AR5K_INI_WRITE }, + { AR5K_RSSI_THR, 0x00000000, AR5K_INI_WRITE }, + { AR5K_CFP_PERIOD_5211, 0x00000000, AR5K_INI_WRITE }, + { AR5K_TIMER0_5211, 0x00000030, AR5K_INI_WRITE }, + { AR5K_TIMER1_5211, 0x0007ffff, AR5K_INI_WRITE }, + { AR5K_TIMER2_5211, 0x01ffffff, AR5K_INI_WRITE }, + { AR5K_TIMER3_5211, 0x00000031, AR5K_INI_WRITE }, + { AR5K_CFP_DUR_5211, 0x00000000, AR5K_INI_WRITE }, + { AR5K_RX_FILTER_5211, 0x00000000, AR5K_INI_WRITE }, + { AR5K_MCAST_FILTER0_5211, 0x00000000, AR5K_INI_WRITE }, + { AR5K_MCAST_FILTER1_5211, 0x00000002, AR5K_INI_WRITE }, + { AR5K_DIAG_SW_5211, 0x00000000, AR5K_INI_WRITE }, + { AR5K_ADDAC_TEST, 0x00000000, AR5K_INI_WRITE }, + { AR5K_DEFAULT_ANTENNA, 0x00000000, AR5K_INI_WRITE }, + /* PHY registers */ + { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(3), 0x2d849093, AR5K_INI_WRITE }, + { AR5K_PHY(4), 0x7d32e000, AR5K_INI_WRITE }, + { AR5K_PHY(5), 0x00000f6b, AR5K_INI_WRITE }, + { AR5K_PHY_ACT, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(11), 0x00026ffe, AR5K_INI_WRITE }, + { AR5K_PHY(12), 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(15), 0x00020100, AR5K_INI_WRITE }, + { AR5K_PHY(16), 0x206a017a, AR5K_INI_WRITE }, + { AR5K_PHY(19), 0x1284613c, AR5K_INI_WRITE }, + { AR5K_PHY(21), 0x00000859, AR5K_INI_WRITE }, + { AR5K_PHY(26), 0x409a4190, AR5K_INI_WRITE }, /* 0x9868 */ + { AR5K_PHY(27), 0x050cb081, AR5K_INI_WRITE }, + { AR5K_PHY(28), 0x0000000f, AR5K_INI_WRITE }, + { AR5K_PHY(29), 0x00000080, AR5K_INI_WRITE }, + { AR5K_PHY(30), 0x0000000c, AR5K_INI_WRITE }, + { AR5K_PHY(64), 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(65), 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(66), 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(67), 0x00800000, AR5K_INI_WRITE }, + { AR5K_PHY(68), 0x00000001, AR5K_INI_WRITE }, + { AR5K_PHY(71), 0x0000092a, AR5K_INI_WRITE }, + { AR5K_PHY_IQ, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(73), 0x00058a05, AR5K_INI_WRITE }, + { AR5K_PHY(74), 0x00000001, AR5K_INI_WRITE }, + { AR5K_PHY(75), 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_PAPD_PROBE, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(77), 0x00000000, AR5K_INI_WRITE }, /* 0x9934 */ + { AR5K_PHY(78), 0x00000000, AR5K_INI_WRITE }, /* 0x9938 */ + { AR5K_PHY(79), 0x0000003f, AR5K_INI_WRITE }, /* 0x993c */ + { AR5K_PHY(80), 0x00000004, AR5K_INI_WRITE }, + { AR5K_PHY(82), 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(83), 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(84), 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_RADAR, 0x5d50f14c, AR5K_INI_WRITE }, + { AR5K_PHY(86), 0x00000018, AR5K_INI_WRITE }, + { AR5K_PHY(87), 0x004b6a8e, AR5K_INI_WRITE }, + /* Initial Power table (32bytes) + * common on all cards/modes. + * Note: Table is rewritten during + * txpower setup later using calibration + * data etc. so next write is non-common */ + { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff, AR5K_INI_WRITE }, + { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff, AR5K_INI_WRITE }, + { AR5K_PHY_CCKTXCTL, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(642), 0x503e4646, AR5K_INI_WRITE }, + { AR5K_PHY_GAIN_2GHZ, 0x6480416c, AR5K_INI_WRITE }, + { AR5K_PHY(644), 0x0199a003, AR5K_INI_WRITE }, + { AR5K_PHY(645), 0x044cd610, AR5K_INI_WRITE }, + { AR5K_PHY(646), 0x13800040, AR5K_INI_WRITE }, + { AR5K_PHY(647), 0x1be00060, AR5K_INI_WRITE }, + { AR5K_PHY(648), 0x0c53800a, AR5K_INI_WRITE }, + { AR5K_PHY(649), 0x0014df3b, AR5K_INI_WRITE }, + { AR5K_PHY(650), 0x000001b5, AR5K_INI_WRITE }, + { AR5K_PHY(651), 0x00000020, AR5K_INI_WRITE }, +}; + +/* Initial mode-specific settings for AR5211 + * 5211 supports OFDM-only g (draft g) but we + * need to test it ! + */ +static const struct ath5k_ini_mode ar5211_ini_mode[] = { + { AR5K_TXCFG, + /* a aTurbo b g (OFDM) */ + { 0x00000015, 0x00000015, 0x0000001d, 0x00000015 } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(0), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(1), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(2), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(3), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(4), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(5), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(6), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(7), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(8), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(9), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, + { AR5K_DCU_GBL_IFS_SLOT, + { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } }, + { AR5K_DCU_GBL_IFS_SIFS, + { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } }, + { AR5K_DCU_GBL_IFS_EIFS, + { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } }, + { AR5K_DCU_GBL_IFS_MISC, + { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } }, + { AR5K_TIME_OUT, + { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } }, + { AR5K_USEC_5211, + { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } }, + { AR5K_PHY_TURBO, + { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } }, + { AR5K_PHY(8), + { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } }, + { AR5K_PHY(9), + { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } }, + { AR5K_PHY(10), + { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } }, + { AR5K_PHY(13), + { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, + { AR5K_PHY(14), + { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } }, + { AR5K_PHY(17), + { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } }, + { AR5K_PHY(18), + { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } }, + { AR5K_PHY(20), + { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } }, + { AR5K_PHY_SIG, + { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } }, + { AR5K_PHY_AGCCOARSE, + { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } }, + { AR5K_PHY_AGCCTL, + { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } }, + { AR5K_PHY_NF, + { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, + { AR5K_PHY_RX_DELAY, + { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } }, + { AR5K_PHY(70), + { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } }, + { AR5K_PHY_FRAME_CTL_5211, + { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } }, + { AR5K_PHY_PCDAC_TXPOWER_BASE, + { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } }, + { AR5K_RF_BUFFER_CONTROL_4, + { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } }, +}; + +/* Initial register settings for AR5212 */ +static const struct ath5k_ini ar5212_ini_common_start[] = { + { AR5K_RXDP, 0x00000000, AR5K_INI_WRITE }, + { AR5K_RXCFG, 0x00000005, AR5K_INI_WRITE }, + { AR5K_MIBC, 0x00000000, AR5K_INI_WRITE }, + { AR5K_TOPS, 0x00000008, AR5K_INI_WRITE }, + { AR5K_RXNOFRM, 0x00000008, AR5K_INI_WRITE }, + { AR5K_TXNOFRM, 0x00000010, AR5K_INI_WRITE }, + { AR5K_RPGTO, 0x00000000, AR5K_INI_WRITE }, + { AR5K_RFCNT, 0x0000001f, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(0), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(1), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(2), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(3), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(4), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(5), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(6), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(7), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(8), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUEUE_TXDP(9), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TXP, 0x00000000, AR5K_INI_WRITE }, + /* Tx filter table 0 (32 entries) */ + { AR5K_DCU_TX_FILTER_0(0), 0x00000000, AR5K_INI_WRITE }, /* DCU 0 */ + { AR5K_DCU_TX_FILTER_0(1), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(2), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(3), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(4), 0x00000000, AR5K_INI_WRITE }, /* DCU 1 */ + { AR5K_DCU_TX_FILTER_0(5), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(6), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(7), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(8), 0x00000000, AR5K_INI_WRITE }, /* DCU 2 */ + { AR5K_DCU_TX_FILTER_0(9), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(10), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(11), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(12), 0x00000000, AR5K_INI_WRITE }, /* DCU 3 */ + { AR5K_DCU_TX_FILTER_0(13), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(14), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(15), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(16), 0x00000000, AR5K_INI_WRITE }, /* DCU 4 */ + { AR5K_DCU_TX_FILTER_0(17), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(18), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(19), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(20), 0x00000000, AR5K_INI_WRITE }, /* DCU 5 */ + { AR5K_DCU_TX_FILTER_0(21), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(22), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(23), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(24), 0x00000000, AR5K_INI_WRITE }, /* DCU 6 */ + { AR5K_DCU_TX_FILTER_0(25), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(26), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(27), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(28), 0x00000000, AR5K_INI_WRITE }, /* DCU 7 */ + { AR5K_DCU_TX_FILTER_0(29), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(30), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_0(31), 0x00000000, AR5K_INI_WRITE }, + /* Tx filter table 1 (16 entries) */ + { AR5K_DCU_TX_FILTER_1(0), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_1(1), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_1(2), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_1(3), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_1(4), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_1(5), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_1(6), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_1(7), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_1(8), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_1(9), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_1(10), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_1(11), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_1(12), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_1(13), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_1(14), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_1(15), 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_CLR, 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_SET, 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_CLR, 0x00000000, AR5K_INI_WRITE }, + { AR5K_DCU_TX_FILTER_SET, 0x00000000, AR5K_INI_WRITE }, + { AR5K_STA_ID1, 0x00000000, AR5K_INI_WRITE }, + { AR5K_BSS_ID0, 0x00000000, AR5K_INI_WRITE }, + { AR5K_BSS_ID1, 0x00000000, AR5K_INI_WRITE }, + { AR5K_BEACON_5211, 0x00000000, AR5K_INI_WRITE }, + { AR5K_CFP_PERIOD_5211, 0x00000000, AR5K_INI_WRITE }, + { AR5K_TIMER0_5211, 0x00000030, AR5K_INI_WRITE }, + { AR5K_TIMER1_5211, 0x0007ffff, AR5K_INI_WRITE }, + { AR5K_TIMER2_5211, 0x01ffffff, AR5K_INI_WRITE }, + { AR5K_TIMER3_5211, 0x00000031, AR5K_INI_WRITE }, + { AR5K_CFP_DUR_5211, 0x00000000, AR5K_INI_WRITE }, + { AR5K_RX_FILTER_5211, 0x00000000, AR5K_INI_WRITE }, + { AR5K_DIAG_SW_5211, 0x00000000, AR5K_INI_WRITE }, + { AR5K_ADDAC_TEST, 0x00000000, AR5K_INI_WRITE }, + { AR5K_DEFAULT_ANTENNA, 0x00000000, AR5K_INI_WRITE }, + { AR5K_FRAME_CTL_QOSM, 0x000fc78f, AR5K_INI_WRITE }, + { AR5K_XRMODE, 0x2a82301a, AR5K_INI_WRITE }, + { AR5K_XRDELAY, 0x05dc01e0, AR5K_INI_WRITE }, + { AR5K_XRTIMEOUT, 0x1f402710, AR5K_INI_WRITE }, + { AR5K_XRCHIRP, 0x01f40000, AR5K_INI_WRITE }, + { AR5K_XRSTOMP, 0x00001e1c, AR5K_INI_WRITE }, + { AR5K_SLEEP0, 0x0002aaaa, AR5K_INI_WRITE }, + { AR5K_SLEEP1, 0x02005555, AR5K_INI_WRITE }, + { AR5K_SLEEP2, 0x00000000, AR5K_INI_WRITE }, + { AR5K_BSS_IDM0, 0xffffffff, AR5K_INI_WRITE }, + { AR5K_BSS_IDM1, 0x0000ffff, AR5K_INI_WRITE }, + { AR5K_TXPC, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PROFCNT_TX, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PROFCNT_RX, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PROFCNT_RXCLR, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PROFCNT_CYCLE, 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUIET_CTL1, 0x00000088, AR5K_INI_WRITE }, + /* Initial rate duration table (32 entries )*/ + { AR5K_RATE_DUR(0), 0x00000000, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(1), 0x0000008c, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(2), 0x000000e4, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(3), 0x000002d5, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(4), 0x00000000, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(5), 0x00000000, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(6), 0x000000a0, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(7), 0x000001c9, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(8), 0x0000002c, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(9), 0x0000002c, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(10), 0x00000030, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(11), 0x0000003c, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(12), 0x0000002c, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(13), 0x0000002c, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(14), 0x00000030, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(15), 0x0000003c, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(16), 0x00000000, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(17), 0x00000000, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(18), 0x00000000, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(19), 0x00000000, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(20), 0x00000000, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(21), 0x00000000, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(22), 0x00000000, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(23), 0x00000000, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(24), 0x000000d5, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(25), 0x000000df, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(26), 0x00000102, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(27), 0x0000013a, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(28), 0x00000075, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(29), 0x0000007f, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(30), 0x000000a2, AR5K_INI_WRITE }, + { AR5K_RATE_DUR(31), 0x00000000, AR5K_INI_WRITE }, + { AR5K_QUIET_CTL2, 0x00010002, AR5K_INI_WRITE }, + { AR5K_TSF_PARM, 0x00000001, AR5K_INI_WRITE }, + { AR5K_QOS_NOACK, 0x000000c0, AR5K_INI_WRITE }, + { AR5K_PHY_ERR_FIL, 0x00000000, AR5K_INI_WRITE }, + { AR5K_XRLAT_TX, 0x00000168, AR5K_INI_WRITE }, + { AR5K_ACKSIFS, 0x00000000, AR5K_INI_WRITE }, + /* Rate -> db table + * notice ...03<-02<-01<-00 ! */ + { AR5K_RATE2DB(0), 0x03020100, AR5K_INI_WRITE }, + { AR5K_RATE2DB(1), 0x07060504, AR5K_INI_WRITE }, + { AR5K_RATE2DB(2), 0x0b0a0908, AR5K_INI_WRITE }, + { AR5K_RATE2DB(3), 0x0f0e0d0c, AR5K_INI_WRITE }, + { AR5K_RATE2DB(4), 0x13121110, AR5K_INI_WRITE }, + { AR5K_RATE2DB(5), 0x17161514, AR5K_INI_WRITE }, + { AR5K_RATE2DB(6), 0x1b1a1918, AR5K_INI_WRITE }, + { AR5K_RATE2DB(7), 0x1f1e1d1c, AR5K_INI_WRITE }, + /* Db -> Rate table */ + { AR5K_DB2RATE(0), 0x03020100, AR5K_INI_WRITE }, + { AR5K_DB2RATE(1), 0x07060504, AR5K_INI_WRITE }, + { AR5K_DB2RATE(2), 0x0b0a0908, AR5K_INI_WRITE }, + { AR5K_DB2RATE(3), 0x0f0e0d0c, AR5K_INI_WRITE }, + { AR5K_DB2RATE(4), 0x13121110, AR5K_INI_WRITE }, + { AR5K_DB2RATE(5), 0x17161514, AR5K_INI_WRITE }, + { AR5K_DB2RATE(6), 0x1b1a1918, AR5K_INI_WRITE }, + { AR5K_DB2RATE(7), 0x1f1e1d1c, AR5K_INI_WRITE }, + /* PHY registers (Common settings + * for all chips/modes) */ + { AR5K_PHY(3), 0xad848e19, AR5K_INI_WRITE }, + { AR5K_PHY(4), 0x7d28e000, AR5K_INI_WRITE }, + { AR5K_PHY_TIMING_3, 0x9c0a9f6b, AR5K_INI_WRITE }, + { AR5K_PHY_ACT, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY(16), 0x206a017a, AR5K_INI_WRITE }, + { AR5K_PHY(21), 0x00000859, AR5K_INI_WRITE }, + { AR5K_PHY_BIN_MASK_1, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_BIN_MASK_2, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_BIN_MASK_3, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_BIN_MASK_CTL, 0x00800000, AR5K_INI_WRITE }, + { AR5K_PHY_ANT_CTL, 0x00000001, AR5K_INI_WRITE }, + /*{ AR5K_PHY(71), 0x0000092a, AR5K_INI_WRITE },*/ /* Old value */ + { AR5K_PHY_MAX_RX_LEN, 0x00000c80, AR5K_INI_WRITE }, + { AR5K_PHY_IQ, 0x05100000, AR5K_INI_WRITE }, + { AR5K_PHY_WARM_RESET, 0x00000001, AR5K_INI_WRITE }, + { AR5K_PHY_CTL, 0x00000004, AR5K_INI_WRITE }, + { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022, AR5K_INI_WRITE }, + { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d, AR5K_INI_WRITE }, + { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f, AR5K_INI_WRITE }, + { AR5K_PHY(82), 0x9280b212, AR5K_INI_WRITE }, + { AR5K_PHY_RADAR, 0x5d50e188, AR5K_INI_WRITE }, + /*{ AR5K_PHY(86), 0x000000ff, AR5K_INI_WRITE },*/ + { AR5K_PHY(87), 0x004b6a8e, AR5K_INI_WRITE }, + { AR5K_PHY_NFTHRES, 0x000003ce, AR5K_INI_WRITE }, + { AR5K_PHY_RESTART, 0x192fb515, AR5K_INI_WRITE }, + { AR5K_PHY(94), 0x00000001, AR5K_INI_WRITE }, + { AR5K_PHY_RFBUS_REQ, 0x00000000, AR5K_INI_WRITE }, + /*{ AR5K_PHY(644), 0x0080a333, AR5K_INI_WRITE },*/ /* Old value */ + /*{ AR5K_PHY(645), 0x00206c10, AR5K_INI_WRITE },*/ /* Old value */ + { AR5K_PHY(644), 0x00806333, AR5K_INI_WRITE }, + { AR5K_PHY(645), 0x00106c10, AR5K_INI_WRITE }, + { AR5K_PHY(646), 0x009c4060, AR5K_INI_WRITE }, + /* { AR5K_PHY(647), 0x1483800a, AR5K_INI_WRITE }, */ + /* { AR5K_PHY(648), 0x01831061, AR5K_INI_WRITE }, */ /* Old value */ + { AR5K_PHY(648), 0x018830c6, AR5K_INI_WRITE }, + { AR5K_PHY(649), 0x00000400, AR5K_INI_WRITE }, + /*{ AR5K_PHY(650), 0x000001b5, AR5K_INI_WRITE },*/ + { AR5K_PHY(651), 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_TXPOWER_RATE3, 0x20202020, AR5K_INI_WRITE }, + { AR5K_PHY_TXPOWER_RATE2, 0x20202020, AR5K_INI_WRITE }, + /*{ AR5K_PHY(655), 0x13c889af, AR5K_INI_WRITE },*/ + { AR5K_PHY(656), 0x38490a20, AR5K_INI_WRITE }, + { AR5K_PHY(657), 0x00007bb6, AR5K_INI_WRITE }, + { AR5K_PHY(658), 0x0fff3ffc, AR5K_INI_WRITE }, +}; + +/* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */ +static const struct ath5k_ini_mode ar5212_ini_mode_start[] = { + { AR5K_QUEUE_DFS_LOCAL_IFS(0), + /* a/XR aTurbo b g (DYN) gTurbo */ + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(1), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(2), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(3), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(4), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(5), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(6), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(7), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(8), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, + { AR5K_QUEUE_DFS_LOCAL_IFS(9), + { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, + { AR5K_DCU_GBL_IFS_SIFS, + { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } }, + { AR5K_DCU_GBL_IFS_SLOT, + { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } }, + { AR5K_DCU_GBL_IFS_EIFS, + { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } }, + { AR5K_DCU_GBL_IFS_MISC, + { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } }, + { AR5K_TIME_OUT, + { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } }, + { AR5K_PHY_TURBO, + { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } }, + { AR5K_PHY(8), + { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } }, + { AR5K_PHY_RF_CTL2, + { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } }, + { AR5K_PHY_SETTLING, + { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } }, + { AR5K_PHY_AGCCTL, + { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d18 } }, + { AR5K_PHY_NF, + { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, + { AR5K_PHY_WEAK_OFDM_HIGH_THR, + { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } }, + { AR5K_PHY(70), + { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } }, + { AR5K_PHY_OFDM_SELFCORR, + { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } }, + { 0xa230, + { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } }, +}; + +/* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */ +static const struct ath5k_ini_mode rf5111_ini_mode_end[] = { + { AR5K_TXCFG, + /* a/XR aTurbo b g (DYN) gTurbo */ + { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } }, + { AR5K_USEC_5211, + { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } }, + { AR5K_PHY_RF_CTL3, + { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } }, + { AR5K_PHY_RF_CTL4, + { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, + { AR5K_PHY_PA_CTL, + { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } }, + { AR5K_PHY_GAIN, + { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } }, + { AR5K_PHY_DESIRED_SIZE, + { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } }, + { AR5K_PHY_SIG, + { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } }, + { AR5K_PHY_AGCCOARSE, + { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } }, + { AR5K_PHY_WEAK_OFDM_LOW_THR, + { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } }, + { AR5K_PHY_RX_DELAY, + { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } }, + { AR5K_PHY_FRAME_CTL_5211, + { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } }, + { AR5K_PHY_GAIN_2GHZ, + { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } }, + { AR5K_PHY_CCK_RX_CTL_4, + { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } }, +}; + +static const struct ath5k_ini rf5111_ini_common_end[] = { + { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_ADC_CTL, 0x00022ffe, AR5K_INI_WRITE }, + { 0x983c, 0x00020100, AR5K_INI_WRITE }, + { AR5K_PHY_GAIN_OFFSET, 0x1284613c, AR5K_INI_WRITE }, + { AR5K_PHY_PAPD_PROBE, 0x00004883, AR5K_INI_WRITE }, + { 0x9940, 0x00000004, AR5K_INI_WRITE }, + { 0x9958, 0x000000ff, AR5K_INI_WRITE }, + { 0x9974, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_SPENDING, 0x00000018, AR5K_INI_WRITE }, + { AR5K_PHY_CCKTXCTL, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788, AR5K_INI_WRITE }, + { AR5K_PHY_DAG_CCK_CTL, 0x000001b5, AR5K_INI_WRITE }, + { 0xa23c, 0x13c889af, AR5K_INI_WRITE }, +}; + +/* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */ +static const struct ath5k_ini_mode rf5112_ini_mode_end[] = { + { AR5K_TXCFG, + /* a/XR aTurbo b g (DYN) gTurbo */ + { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } }, + { AR5K_USEC_5211, + { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } }, + { AR5K_PHY_RF_CTL3, + { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } }, + { AR5K_PHY_RF_CTL4, + { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, + { AR5K_PHY_PA_CTL, + { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } }, + { AR5K_PHY_GAIN, + { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } }, + { AR5K_PHY_DESIRED_SIZE, + { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } }, + { AR5K_PHY_SIG, + { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7ee80d2e } }, + { AR5K_PHY_AGCCOARSE, + { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } }, + { AR5K_PHY_WEAK_OFDM_LOW_THR, + { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } }, + { AR5K_PHY_RX_DELAY, + { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } }, + { AR5K_PHY_FRAME_CTL_5211, + { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } }, + { AR5K_PHY_CCKTXCTL, + { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } }, + { AR5K_PHY_CCK_CROSSCORR, + { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, + { AR5K_PHY_GAIN_2GHZ, + { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } }, + { AR5K_PHY_CCK_RX_CTL_4, + { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } }, +}; + +static const struct ath5k_ini rf5112_ini_common_end[] = { + { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_ADC_CTL, 0x00022ffe, AR5K_INI_WRITE }, + { 0x983c, 0x00020100, AR5K_INI_WRITE }, + { AR5K_PHY_GAIN_OFFSET, 0x1284613c, AR5K_INI_WRITE }, + { AR5K_PHY_PAPD_PROBE, 0x00004882, AR5K_INI_WRITE }, + { 0x9940, 0x00000004, AR5K_INI_WRITE }, + { 0x9958, 0x000000ff, AR5K_INI_WRITE }, + { 0x9974, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_DAG_CCK_CTL, 0x000001b5, AR5K_INI_WRITE }, + { 0xa23c, 0x13c889af, AR5K_INI_WRITE }, +}; + +/* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */ +static const struct ath5k_ini_mode rf5413_ini_mode_end[] = { + { AR5K_TXCFG, + /* a/XR aTurbo b g (DYN) gTurbo */ + { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } }, + { AR5K_USEC_5211, + { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } }, + { AR5K_PHY_RF_CTL3, + { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } }, + { AR5K_PHY_RF_CTL4, + { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, + { AR5K_PHY_PA_CTL, + { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } }, + { AR5K_PHY_GAIN, + { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } }, + { AR5K_PHY_DESIRED_SIZE, + { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } }, + { AR5K_PHY_SIG, + { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } }, + { AR5K_PHY_AGCCOARSE, + { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } }, + { AR5K_PHY_WEAK_OFDM_LOW_THR, + { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } }, + { AR5K_PHY_RX_DELAY, + { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } }, + { AR5K_PHY_FRAME_CTL_5211, + { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } }, + { AR5K_PHY_CCKTXCTL, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { AR5K_PHY_CCK_CROSSCORR, + { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, + { AR5K_PHY_GAIN_2GHZ, + { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } }, + { AR5K_PHY_CCK_RX_CTL_4, + { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } }, + { 0xa300, + { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } }, + { 0xa304, + { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } }, + { 0xa308, + { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } }, + { 0xa30c, + { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } }, + { 0xa310, + { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } }, + { 0xa314, + { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } }, + { 0xa318, + { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } }, + { 0xa31c, + { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } }, + { 0xa320, + { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } }, + { 0xa324, + { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } }, + { 0xa328, + { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } }, + { 0xa32c, + { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } }, + { 0xa330, + { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } }, + { 0xa334, + { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } }, +}; + +static const struct ath5k_ini rf5413_ini_common_end[] = { + { AR5K_DCU_FP, 0x000003e0, AR5K_INI_WRITE }, + { AR5K_5414_CBCFG, 0x00000010, AR5K_INI_WRITE }, + { AR5K_SEQ_MASK, 0x0000000f, AR5K_INI_WRITE }, + { 0x809c, 0x00000000, AR5K_INI_WRITE }, + { 0x80a0, 0x00000000, AR5K_INI_WRITE }, + { AR5K_MIC_QOS_CTL, 0x00000000, AR5K_INI_WRITE }, + { AR5K_MIC_QOS_SEL, 0x00000000, AR5K_INI_WRITE }, + { AR5K_MISC_MODE, 0x00000000, AR5K_INI_WRITE }, + { AR5K_OFDM_FIL_CNT, 0x00000000, AR5K_INI_WRITE }, + { AR5K_CCK_FIL_CNT, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHYERR_CNT1, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHYERR_CNT1_MASK, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHYERR_CNT2, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHYERR_CNT2_MASK, 0x00000000, AR5K_INI_WRITE }, + { AR5K_TSF_THRES, 0x00000000, AR5K_INI_WRITE }, + { 0x8140, 0x800003f9, AR5K_INI_WRITE }, + { 0x8144, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_ADC_CTL, 0x0000a000, AR5K_INI_WRITE }, + { 0x983c, 0x00200400, AR5K_INI_WRITE }, + { AR5K_PHY_GAIN_OFFSET, 0x1284233c, AR5K_INI_WRITE }, + { AR5K_PHY_SCR, 0x0000001f, AR5K_INI_WRITE }, + { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE }, + { AR5K_PHY_SCAL, 0x0000000e, AR5K_INI_WRITE }, + { 0x9958, 0x00081fff, AR5K_INI_WRITE }, + { AR5K_PHY_TIMING_7, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_TIMING_8, 0x02800000, AR5K_INI_WRITE }, + { AR5K_PHY_TIMING_11, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000, AR5K_INI_WRITE }, + { 0x99e4, 0xaaaaaaaa, AR5K_INI_WRITE }, + { 0x99e8, 0x3c466478, AR5K_INI_WRITE }, + { 0x99ec, 0x000000aa, AR5K_INI_WRITE }, + { AR5K_PHY_SCLOCK, 0x0000000c, AR5K_INI_WRITE }, + { AR5K_PHY_SDELAY, 0x000000ff, AR5K_INI_WRITE }, + { AR5K_PHY_SPENDING, 0x00000014, AR5K_INI_WRITE }, + { AR5K_PHY_DAG_CCK_CTL, 0x000009b5, AR5K_INI_WRITE }, + { 0xa23c, 0x93c889af, AR5K_INI_WRITE }, + { AR5K_PHY_FAST_ADC, 0x00000001, AR5K_INI_WRITE }, + { 0xa250, 0x0000a000, AR5K_INI_WRITE }, + { AR5K_PHY_BLUETOOTH, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_TPC_RG1, 0x0cc75380, AR5K_INI_WRITE }, + { 0xa25c, 0x0f0f0f01, AR5K_INI_WRITE }, + { 0xa260, 0x5f690f01, AR5K_INI_WRITE }, + { 0xa264, 0x00418a11, AR5K_INI_WRITE }, + { 0xa268, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_TPC_RG5, 0x0c30c16a, AR5K_INI_WRITE }, + { 0xa270, 0x00820820, AR5K_INI_WRITE }, + { 0xa274, 0x081b7caa, AR5K_INI_WRITE }, + { 0xa278, 0x1ce739ce, AR5K_INI_WRITE }, + { 0xa27c, 0x051701ce, AR5K_INI_WRITE }, + { 0xa338, 0x00000000, AR5K_INI_WRITE }, + { 0xa33c, 0x00000000, AR5K_INI_WRITE }, + { 0xa340, 0x00000000, AR5K_INI_WRITE }, + { 0xa344, 0x00000000, AR5K_INI_WRITE }, + { 0xa348, 0x3fffffff, AR5K_INI_WRITE }, + { 0xa34c, 0x3fffffff, AR5K_INI_WRITE }, + { 0xa350, 0x3fffffff, AR5K_INI_WRITE }, + { 0xa354, 0x0003ffff, AR5K_INI_WRITE }, + { 0xa358, 0x79a8aa1f, AR5K_INI_WRITE }, + { 0xa35c, 0x066c420f, AR5K_INI_WRITE }, + { 0xa360, 0x0f282207, AR5K_INI_WRITE }, + { 0xa364, 0x17601685, AR5K_INI_WRITE }, + { 0xa368, 0x1f801104, AR5K_INI_WRITE }, + { 0xa36c, 0x37a00c03, AR5K_INI_WRITE }, + { 0xa370, 0x3fc40883, AR5K_INI_WRITE }, + { 0xa374, 0x57c00803, AR5K_INI_WRITE }, + { 0xa378, 0x5fd80682, AR5K_INI_WRITE }, + { 0xa37c, 0x7fe00482, AR5K_INI_WRITE }, + { 0xa380, 0x7f3c7bba, AR5K_INI_WRITE }, + { 0xa384, 0xf3307ff0, AR5K_INI_WRITE }, +}; + +/* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */ +/* XXX: a mode ? */ +static const struct ath5k_ini_mode rf2413_ini_mode_end[] = { + { AR5K_TXCFG, + /* a/XR aTurbo b g (DYN) gTurbo */ + { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } }, + { AR5K_USEC_5211, + { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } }, + { AR5K_PHY_RF_CTL3, + { 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 } }, + { AR5K_PHY_RF_CTL4, + { 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 } }, + { AR5K_PHY_PA_CTL, + { 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a } }, + { AR5K_PHY_GAIN, + { 0x0018da6d, 0x0018da6d, 0x001a6a64, 0x001a6a64, 0x001a6a64 } }, + { AR5K_PHY_DESIRED_SIZE, + { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da } }, + { AR5K_PHY_SIG, + { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e } }, + { AR5K_PHY_AGCCOARSE, + { 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e } }, + { AR5K_PHY_WEAK_OFDM_LOW_THR, + { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } }, + { AR5K_PHY_RX_DELAY, + { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } }, + { AR5K_PHY_FRAME_CTL_5211, + { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } }, + { AR5K_PHY_CCKTXCTL, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { AR5K_PHY_CCK_CROSSCORR, + { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, + { AR5K_PHY_GAIN_2GHZ, + { 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 } }, + { AR5K_PHY_CCK_RX_CTL_4, + { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } }, +}; + +static const struct ath5k_ini rf2413_ini_common_end[] = { + { AR5K_DCU_FP, 0x000003e0, AR5K_INI_WRITE }, + { AR5K_SEQ_MASK, 0x0000000f, AR5K_INI_WRITE }, + { AR5K_MIC_QOS_CTL, 0x00000000, AR5K_INI_WRITE }, + { AR5K_MIC_QOS_SEL, 0x00000000, AR5K_INI_WRITE }, + { AR5K_MISC_MODE, 0x00000000, AR5K_INI_WRITE }, + { AR5K_OFDM_FIL_CNT, 0x00000000, AR5K_INI_WRITE }, + { AR5K_CCK_FIL_CNT, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHYERR_CNT1, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHYERR_CNT1_MASK, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHYERR_CNT2, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHYERR_CNT2_MASK, 0x00000000, AR5K_INI_WRITE }, + { AR5K_TSF_THRES, 0x00000000, AR5K_INI_WRITE }, + { 0x8140, 0x800000a8, AR5K_INI_WRITE }, + { 0x8144, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_ADC_CTL, 0x0000a000, AR5K_INI_WRITE }, + { 0x983c, 0x00200400, AR5K_INI_WRITE }, + { AR5K_PHY_GAIN_OFFSET, 0x1284233c, AR5K_INI_WRITE }, + { AR5K_PHY_SCR, 0x0000001f, AR5K_INI_WRITE }, + { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE }, + { AR5K_PHY_SCAL, 0x0000000e, AR5K_INI_WRITE }, + { 0x9958, 0x000000ff, AR5K_INI_WRITE }, + { AR5K_PHY_TIMING_7, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_TIMING_8, 0x02800000, AR5K_INI_WRITE }, + { AR5K_PHY_TIMING_11, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000, AR5K_INI_WRITE }, + { 0x99e4, 0xaaaaaaaa, AR5K_INI_WRITE }, + { 0x99e8, 0x3c466478, AR5K_INI_WRITE }, + { 0x99ec, 0x000000aa, AR5K_INI_WRITE }, + { AR5K_PHY_SCLOCK, 0x0000000c, AR5K_INI_WRITE }, + { AR5K_PHY_SDELAY, 0x000000ff, AR5K_INI_WRITE }, + { AR5K_PHY_SPENDING, 0x00000014, AR5K_INI_WRITE }, + { AR5K_PHY_DAG_CCK_CTL, 0x000009b5, AR5K_INI_WRITE }, + { 0xa23c, 0x93c889af, AR5K_INI_WRITE }, + { AR5K_PHY_FAST_ADC, 0x00000001, AR5K_INI_WRITE }, + { 0xa250, 0x0000a000, AR5K_INI_WRITE }, + { AR5K_PHY_BLUETOOTH, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_TPC_RG1, 0x0cc75380, AR5K_INI_WRITE }, + { 0xa25c, 0x0f0f0f01, AR5K_INI_WRITE }, + { 0xa260, 0x5f690f01, AR5K_INI_WRITE }, + { 0xa264, 0x00418a11, AR5K_INI_WRITE }, + { 0xa268, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_TPC_RG5, 0x0c30c16a, AR5K_INI_WRITE }, + { 0xa270, 0x00820820, AR5K_INI_WRITE }, + { 0xa274, 0x001b7caa, AR5K_INI_WRITE }, + { 0xa278, 0x1ce739ce, AR5K_INI_WRITE }, + { 0xa27c, 0x051701ce, AR5K_INI_WRITE }, + { 0xa300, 0x18010000, AR5K_INI_WRITE }, + { 0xa304, 0x30032602, AR5K_INI_WRITE }, + { 0xa308, 0x48073e06, AR5K_INI_WRITE }, + { 0xa30c, 0x560b4c0a, AR5K_INI_WRITE }, + { 0xa310, 0x641a600f, AR5K_INI_WRITE }, + { 0xa314, 0x784f6e1b, AR5K_INI_WRITE }, + { 0xa318, 0x868f7c5a, AR5K_INI_WRITE }, + { 0xa31c, 0x8ecf865b, AR5K_INI_WRITE }, + { 0xa320, 0x9d4f970f, AR5K_INI_WRITE }, + { 0xa324, 0xa5cfa18f, AR5K_INI_WRITE }, + { 0xa328, 0xb55faf1f, AR5K_INI_WRITE }, + { 0xa32c, 0xbddfb99f, AR5K_INI_WRITE }, + { 0xa330, 0xcd7fc73f, AR5K_INI_WRITE }, + { 0xa334, 0xd5ffd1bf, AR5K_INI_WRITE }, + { 0xa338, 0x00000000, AR5K_INI_WRITE }, + { 0xa33c, 0x00000000, AR5K_INI_WRITE }, + { 0xa340, 0x00000000, AR5K_INI_WRITE }, + { 0xa344, 0x00000000, AR5K_INI_WRITE }, + { 0xa348, 0x3fffffff, AR5K_INI_WRITE }, + { 0xa34c, 0x3fffffff, AR5K_INI_WRITE }, + { 0xa350, 0x3fffffff, AR5K_INI_WRITE }, + { 0xa354, 0x0003ffff, AR5K_INI_WRITE }, + { 0xa358, 0x79a8aa1f, AR5K_INI_WRITE }, + { 0xa35c, 0x066c420f, AR5K_INI_WRITE }, + { 0xa360, 0x0f282207, AR5K_INI_WRITE }, + { 0xa364, 0x17601685, AR5K_INI_WRITE }, + { 0xa368, 0x1f801104, AR5K_INI_WRITE }, + { 0xa36c, 0x37a00c03, AR5K_INI_WRITE }, + { 0xa370, 0x3fc40883, AR5K_INI_WRITE }, + { 0xa374, 0x57c00803, AR5K_INI_WRITE }, + { 0xa378, 0x5fd80682, AR5K_INI_WRITE }, + { 0xa37c, 0x7fe00482, AR5K_INI_WRITE }, + { 0xa380, 0x7f3c7bba, AR5K_INI_WRITE }, + { 0xa384, 0xf3307ff0, AR5K_INI_WRITE }, +}; + +/* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */ +/* XXX: a mode ? */ +static const struct ath5k_ini_mode rf2425_ini_mode_end[] = { + { AR5K_TXCFG, + /* a/XR aTurbo b g (DYN) gTurbo */ + { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } }, + { AR5K_USEC_5211, + { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } }, + { AR5K_PHY_TURBO, + { 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001 } }, + { AR5K_PHY_RF_CTL3, + { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } }, + { AR5K_PHY_RF_CTL4, + { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, + { AR5K_PHY_PA_CTL, + { 0x00000003, 0x00000003, 0x0000000b, 0x0000000b, 0x0000000b } }, + { AR5K_PHY_SETTLING, + { 0x1372161c, 0x13721c25, 0x13721722, 0x13721422, 0x13721c25 } }, + { AR5K_PHY_GAIN, + { 0x0018fa61, 0x0018fa61, 0x00199a65, 0x00199a65, 0x00199a65 } }, + { AR5K_PHY_DESIRED_SIZE, + { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } }, + { AR5K_PHY_SIG, + { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } }, + { AR5K_PHY_AGCCOARSE, + { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } }, + { AR5K_PHY_WEAK_OFDM_LOW_THR, + { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } }, + { AR5K_PHY_RX_DELAY, + { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } }, + { AR5K_PHY_FRAME_CTL_5211, + { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } }, + { AR5K_PHY_CCKTXCTL, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { AR5K_PHY_CCK_CROSSCORR, + { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, + { AR5K_PHY_GAIN_2GHZ, + { 0x00000140, 0x00000140, 0x0052c140, 0x0052c140, 0x0052c140 } }, + { AR5K_PHY_CCK_RX_CTL_4, + { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } }, + { 0xa324, + { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } }, + { 0xa328, + { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } }, + { 0xa32c, + { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } }, + { 0xa330, + { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } }, + { 0xa334, + { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } }, +}; + +static const struct ath5k_ini rf2425_ini_common_end[] = { + { AR5K_DCU_FP, 0x000003e0, AR5K_INI_WRITE }, + { AR5K_SEQ_MASK, 0x0000000f, AR5K_INI_WRITE }, + { 0x809c, 0x00000000, AR5K_INI_WRITE }, + { 0x80a0, 0x00000000, AR5K_INI_WRITE }, + { AR5K_MIC_QOS_CTL, 0x00000000, AR5K_INI_WRITE }, + { AR5K_MIC_QOS_SEL, 0x00000000, AR5K_INI_WRITE }, + { AR5K_MISC_MODE, 0x00000000, AR5K_INI_WRITE }, + { AR5K_OFDM_FIL_CNT, 0x00000000, AR5K_INI_WRITE }, + { AR5K_CCK_FIL_CNT, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHYERR_CNT1, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHYERR_CNT1_MASK, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHYERR_CNT2, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHYERR_CNT2_MASK, 0x00000000, AR5K_INI_WRITE }, + { AR5K_TSF_THRES, 0x00000000, AR5K_INI_WRITE }, + { 0x8140, 0x800003f9, AR5K_INI_WRITE }, + { 0x8144, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_ADC_CTL, 0x0000a000, AR5K_INI_WRITE }, + { 0x983c, 0x00200400, AR5K_INI_WRITE }, + { AR5K_PHY_GAIN_OFFSET, 0x1284233c, AR5K_INI_WRITE }, + { AR5K_PHY_SCR, 0x0000001f, AR5K_INI_WRITE }, + { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE }, + { AR5K_PHY_SCAL, 0x0000000e, AR5K_INI_WRITE }, + { 0x9958, 0x00081fff, AR5K_INI_WRITE }, + { AR5K_PHY_TIMING_7, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_TIMING_8, 0x02800000, AR5K_INI_WRITE }, + { AR5K_PHY_TIMING_11, 0x00000000, AR5K_INI_WRITE }, + { 0x99dc, 0xfebadbe8, AR5K_INI_WRITE }, + { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000, AR5K_INI_WRITE }, + { 0x99e4, 0xaaaaaaaa, AR5K_INI_WRITE }, + { 0x99e8, 0x3c466478, AR5K_INI_WRITE }, + { 0x99ec, 0x000000aa, AR5K_INI_WRITE }, + { AR5K_PHY_SCLOCK, 0x0000000c, AR5K_INI_WRITE }, + { AR5K_PHY_SDELAY, 0x000000ff, AR5K_INI_WRITE }, + { AR5K_PHY_SPENDING, 0x00000014, AR5K_INI_WRITE }, + { AR5K_PHY_DAG_CCK_CTL, 0x000009b5, AR5K_INI_WRITE }, + { AR5K_PHY_TXPOWER_RATE3, 0x20202020, AR5K_INI_WRITE }, + { AR5K_PHY_TXPOWER_RATE4, 0x20202020, AR5K_INI_WRITE }, + { 0xa23c, 0x93c889af, AR5K_INI_WRITE }, + { AR5K_PHY_FAST_ADC, 0x00000001, AR5K_INI_WRITE }, + { 0xa250, 0x0000a000, AR5K_INI_WRITE }, + { AR5K_PHY_BLUETOOTH, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_TPC_RG1, 0x0cc75380, AR5K_INI_WRITE }, + { 0xa25c, 0x0f0f0f01, AR5K_INI_WRITE }, + { 0xa260, 0x5f690f01, AR5K_INI_WRITE }, + { 0xa264, 0x00418a11, AR5K_INI_WRITE }, + { 0xa268, 0x00000000, AR5K_INI_WRITE }, + { AR5K_PHY_TPC_RG5, 0x0c30c166, AR5K_INI_WRITE }, + { 0xa270, 0x00820820, AR5K_INI_WRITE }, + { 0xa274, 0x081a3caa, AR5K_INI_WRITE }, + { 0xa278, 0x1ce739ce, AR5K_INI_WRITE }, + { 0xa27c, 0x051701ce, AR5K_INI_WRITE }, + { 0xa300, 0x16010000, AR5K_INI_WRITE }, + { 0xa304, 0x2c032402, AR5K_INI_WRITE }, + { 0xa308, 0x48433e42, AR5K_INI_WRITE }, + { 0xa30c, 0x5a0f500b, AR5K_INI_WRITE }, + { 0xa310, 0x6c4b624a, AR5K_INI_WRITE }, + { 0xa314, 0x7e8b748a, AR5K_INI_WRITE }, + { 0xa318, 0x96cf8ccb, AR5K_INI_WRITE }, + { 0xa31c, 0xa34f9d0f, AR5K_INI_WRITE }, + { 0xa320, 0xa7cfa58f, AR5K_INI_WRITE }, + { 0xa348, 0x3fffffff, AR5K_INI_WRITE }, + { 0xa34c, 0x3fffffff, AR5K_INI_WRITE }, + { 0xa350, 0x3fffffff, AR5K_INI_WRITE }, + { 0xa354, 0x0003ffff, AR5K_INI_WRITE }, + { 0xa358, 0x79a8aa1f, AR5K_INI_WRITE }, + { 0xa35c, 0x066c420f, AR5K_INI_WRITE }, + { 0xa360, 0x0f282207, AR5K_INI_WRITE }, + { 0xa364, 0x17601685, AR5K_INI_WRITE }, + { 0xa368, 0x1f801104, AR5K_INI_WRITE }, + { 0xa36c, 0x37a00c03, AR5K_INI_WRITE }, + { 0xa370, 0x3fc40883, AR5K_INI_WRITE }, + { 0xa374, 0x57c00803, AR5K_INI_WRITE }, + { 0xa378, 0x5fd80682, AR5K_INI_WRITE }, + { 0xa37c, 0x7fe00482, AR5K_INI_WRITE }, + { 0xa380, 0x7f3c7bba, AR5K_INI_WRITE }, + { 0xa384, 0xf3307ff0, AR5K_INI_WRITE }, +}; + +/* + * Initial BaseBand Gain settings for RF5111/5112 (AR5210 comes with + * RF5110 only so initial BB Gain settings are included in AR5K_AR5210_INI) + */ + +/* RF5111 Initial BaseBand Gain settings */ +static const struct ath5k_ini rf5111_ini_bbgain[] = { + { AR5K_BB_GAIN(0), 0x00000000, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(1), 0x00000020, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(2), 0x00000010, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(3), 0x00000030, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(4), 0x00000008, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(5), 0x00000028, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(6), 0x00000004, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(7), 0x00000024, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(8), 0x00000014, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(9), 0x00000034, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(10), 0x0000000c, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(11), 0x0000002c, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(12), 0x00000002, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(13), 0x00000022, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(14), 0x00000012, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(15), 0x00000032, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(16), 0x0000000a, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(17), 0x0000002a, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(18), 0x00000006, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(19), 0x00000026, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(20), 0x00000016, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(21), 0x00000036, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(22), 0x0000000e, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(23), 0x0000002e, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(24), 0x00000001, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(25), 0x00000021, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(26), 0x00000011, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(27), 0x00000031, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(28), 0x00000009, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(29), 0x00000029, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(30), 0x00000005, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(31), 0x00000025, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(32), 0x00000015, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(33), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(34), 0x0000000d, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(35), 0x0000002d, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(36), 0x00000003, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(37), 0x00000023, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(38), 0x00000013, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(39), 0x00000033, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(40), 0x0000000b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(41), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(42), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(43), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(44), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(45), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(46), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(47), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(48), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(49), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(50), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(51), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(52), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(53), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(54), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(55), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(56), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(57), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(58), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(59), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(60), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(61), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(62), 0x00000002, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(63), 0x00000016, AR5K_INI_WRITE }, +}; + +/* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414+) */ +static const struct ath5k_ini rf5112_ini_bbgain[] = { + { AR5K_BB_GAIN(0), 0x00000000, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(1), 0x00000001, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(2), 0x00000002, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(3), 0x00000003, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(4), 0x00000004, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(5), 0x00000005, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(6), 0x00000008, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(7), 0x00000009, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(8), 0x0000000a, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(9), 0x0000000b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(10), 0x0000000c, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(11), 0x0000000d, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(12), 0x00000010, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(13), 0x00000011, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(14), 0x00000012, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(15), 0x00000013, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(16), 0x00000014, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(17), 0x00000015, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(18), 0x00000018, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(19), 0x00000019, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(20), 0x0000001a, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(21), 0x0000001b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(22), 0x0000001c, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(23), 0x0000001d, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(24), 0x00000020, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(25), 0x00000021, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(26), 0x00000022, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(27), 0x00000023, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(28), 0x00000024, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(29), 0x00000025, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(30), 0x00000028, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(31), 0x00000029, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(32), 0x0000002a, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(33), 0x0000002b, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(34), 0x0000002c, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(35), 0x0000002d, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(36), 0x00000030, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(37), 0x00000031, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(38), 0x00000032, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(39), 0x00000033, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(40), 0x00000034, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(41), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(42), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(43), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(44), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(45), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(46), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(47), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(48), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(49), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(50), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(51), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(52), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(53), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(54), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(55), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(56), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(57), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(58), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(59), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(60), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(61), 0x00000035, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(62), 0x00000010, AR5K_INI_WRITE }, + { AR5K_BB_GAIN(63), 0x0000001a, AR5K_INI_WRITE }, +}; + + +/* + * Write initial register dump + */ +static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size, + const struct ath5k_ini *ini_regs, int change_channel) +{ + unsigned int i; + + /* Write initial registers */ + for (i = 0; i < size; i++) { + /* On channel change there is + * no need to mess with PCU */ + if (change_channel && + ini_regs[i].ini_register >= AR5K_PCU_MIN && + ini_regs[i].ini_register <= AR5K_PCU_MAX) + continue; + + switch (ini_regs[i].ini_mode) { + case AR5K_INI_READ: + /* Cleared on read */ + ath5k_hw_reg_read(ah, ini_regs[i].ini_register); + break; + case AR5K_INI_WRITE: + default: + AR5K_REG_WAIT(i); + ath5k_hw_reg_write(ah, ini_regs[i].ini_value, + ini_regs[i].ini_register); + } + } +} + +static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah, + unsigned int size, const struct ath5k_ini_mode *ini_mode, + u8 mode) +{ + unsigned int i; + + for (i = 0; i < size; i++) { + AR5K_REG_WAIT(i); + ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode], + (u32)ini_mode[i].mode_register); + } +} + +int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, int change_channel) +{ + /* + * Write initial register settings + */ + + /* For AR5212 and combatible */ + if (ah->ah_version == AR5K_AR5212) { + + /* First set of mode-specific settings */ + ath5k_hw_ini_mode_registers(ah, + ARRAY_SIZE(ar5212_ini_mode_start), + ar5212_ini_mode_start, mode); + + /* + * Write initial settings common for all modes + */ + ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start), + ar5212_ini_common_start, change_channel); + + /* Second set of mode-specific settings */ + switch (ah->ah_radio) { + case AR5K_RF5111: + + ath5k_hw_ini_mode_registers(ah, + ARRAY_SIZE(rf5111_ini_mode_end), + rf5111_ini_mode_end, mode); + + ath5k_hw_ini_registers(ah, + ARRAY_SIZE(rf5111_ini_common_end), + rf5111_ini_common_end, change_channel); + + /* Baseband gain table */ + ath5k_hw_ini_registers(ah, + ARRAY_SIZE(rf5111_ini_bbgain), + rf5111_ini_bbgain, change_channel); + + break; + case AR5K_RF5112: + + ath5k_hw_ini_mode_registers(ah, + ARRAY_SIZE(rf5112_ini_mode_end), + rf5112_ini_mode_end, mode); + + ath5k_hw_ini_registers(ah, + ARRAY_SIZE(rf5112_ini_common_end), + rf5112_ini_common_end, change_channel); + + ath5k_hw_ini_registers(ah, + ARRAY_SIZE(rf5112_ini_bbgain), + rf5112_ini_bbgain, change_channel); + + break; + case AR5K_RF5413: + + ath5k_hw_ini_mode_registers(ah, + ARRAY_SIZE(rf5413_ini_mode_end), + rf5413_ini_mode_end, mode); + + ath5k_hw_ini_registers(ah, + ARRAY_SIZE(rf5413_ini_common_end), + rf5413_ini_common_end, change_channel); + + ath5k_hw_ini_registers(ah, + ARRAY_SIZE(rf5112_ini_bbgain), + rf5112_ini_bbgain, change_channel); + + break; + case AR5K_RF2316: + case AR5K_RF2413: + + ath5k_hw_ini_mode_registers(ah, + ARRAY_SIZE(rf2413_ini_mode_end), + rf2413_ini_mode_end, mode); + + ath5k_hw_ini_registers(ah, + ARRAY_SIZE(rf2413_ini_common_end), + rf2413_ini_common_end, change_channel); + + /* Override settings from rf2413_ini_common_end */ + if (ah->ah_radio == AR5K_RF2316) { + ath5k_hw_reg_write(ah, 0x00004000, + AR5K_PHY_AGC); + ath5k_hw_reg_write(ah, 0x081b7caa, + 0xa274); + } + + ath5k_hw_ini_registers(ah, + ARRAY_SIZE(rf5112_ini_bbgain), + rf5112_ini_bbgain, change_channel); + break; + case AR5K_RF2317: + case AR5K_RF2425: + + ath5k_hw_ini_mode_registers(ah, + ARRAY_SIZE(rf2425_ini_mode_end), + rf2425_ini_mode_end, mode); + + ath5k_hw_ini_registers(ah, + ARRAY_SIZE(rf2425_ini_common_end), + rf2425_ini_common_end, change_channel); + + ath5k_hw_ini_registers(ah, + ARRAY_SIZE(rf5112_ini_bbgain), + rf5112_ini_bbgain, change_channel); + break; + default: + return -EINVAL; + + } + + /* For AR5211 */ + } else if (ah->ah_version == AR5K_AR5211) { + + /* AR5K_MODE_11B */ + if (mode > 2) { + DBG("ath5k: unsupported channel mode %d\n", mode); + return -EINVAL; + } + + /* Mode-specific settings */ + ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode), + ar5211_ini_mode, mode); + + /* + * Write initial settings common for all modes + */ + ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini), + ar5211_ini, change_channel); + + /* AR5211 only comes with 5111 */ + + /* Baseband gain table */ + ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain), + rf5111_ini_bbgain, change_channel); + /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */ + } else if (ah->ah_version == AR5K_AR5210) { + ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini), + ar5210_ini, change_channel); + } + + return 0; +} diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_pcu.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_pcu.c new file mode 100644 index 0000000..1e90a94 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_pcu.c @@ -0,0 +1,534 @@ +/* + * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> + * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org> + * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> + * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> + * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> + * + * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +FILE_LICENCE ( MIT ); + +/*********************************\ +* Protocol Control Unit Functions * +\*********************************/ + +#include "ath5k.h" +#include "reg.h" +#include "base.h" + +/*******************\ +* Generic functions * +\*******************/ + +/** + * ath5k_hw_set_opmode - Set PCU operating mode + * + * @ah: The &struct ath5k_hw + * + * Initialize PCU for the various operating modes (AP/STA etc) + * + * For gPXE we always assume STA mode. + */ +int ath5k_hw_set_opmode(struct ath5k_hw *ah) +{ + u32 pcu_reg, beacon_reg, low_id, high_id; + + + /* Preserve rest settings */ + pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; + pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP + | AR5K_STA_ID1_KEYSRCH_MODE + | (ah->ah_version == AR5K_AR5210 ? + (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0)); + + beacon_reg = 0; + + pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE + | (ah->ah_version == AR5K_AR5210 ? + AR5K_STA_ID1_PWR_SV : 0); + + /* + * Set PCU registers + */ + low_id = AR5K_LOW_ID(ah->ah_sta_id); + high_id = AR5K_HIGH_ID(ah->ah_sta_id); + ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); + ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); + + /* + * Set Beacon Control Register on 5210 + */ + if (ah->ah_version == AR5K_AR5210) + ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR); + + return 0; +} + +/** + * ath5k_hw_set_ack_bitrate - set bitrate for ACKs + * + * @ah: The &struct ath5k_hw + * @high: Flag to determine if we want to use high transmition rate + * for ACKs or not + * + * If high flag is set, we tell hw to use a set of control rates based on + * the current transmition rate (check out control_rates array inside reset.c). + * If not hw just uses the lowest rate available for the current modulation + * scheme being used (1Mbit for CCK and 6Mbits for OFDM). + */ +void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, int high) +{ + if (ah->ah_version != AR5K_AR5212) + return; + else { + u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB; + if (high) + AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); + else + AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); + } +} + + +/******************\ +* ACK/CTS Timeouts * +\******************/ + +/** + * ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec + * + * @ah: The &struct ath5k_hw + */ +unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah) +{ + return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah, + AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), ah->ah_turbo); +} + +/** + * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU + * + * @ah: The &struct ath5k_hw + * @timeout: Timeout in usec + */ +int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) +{ + if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), + ah->ah_turbo) <= timeout) + return -EINVAL; + + AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, + ath5k_hw_htoclock(timeout, ah->ah_turbo)); + + return 0; +} + +/** + * ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec + * + * @ah: The &struct ath5k_hw + */ +unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah) +{ + return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah, + AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), ah->ah_turbo); +} + +/** + * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU + * + * @ah: The &struct ath5k_hw + * @timeout: Timeout in usec + */ +int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) +{ + if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), + ah->ah_turbo) <= timeout) + return -EINVAL; + + AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, + ath5k_hw_htoclock(timeout, ah->ah_turbo)); + + return 0; +} + + +/****************\ +* BSSID handling * +\****************/ + +/** + * ath5k_hw_get_lladdr - Get station id + * + * @ah: The &struct ath5k_hw + * @mac: The card's mac address + * + * Initialize ah->ah_sta_id using the mac address provided + * (just a memcpy). + * + * TODO: Remove it once we merge ath5k_softc and ath5k_hw + */ +void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac) +{ + memcpy(mac, ah->ah_sta_id, ETH_ALEN); +} + +/** + * ath5k_hw_set_lladdr - Set station id + * + * @ah: The &struct ath5k_hw + * @mac: The card's mac address + * + * Set station id on hw using the provided mac address + */ +int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac) +{ + u32 low_id, high_id; + u32 pcu_reg; + + /* Set new station ID */ + memcpy(ah->ah_sta_id, mac, ETH_ALEN); + + pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; + + low_id = AR5K_LOW_ID(mac); + high_id = AR5K_HIGH_ID(mac); + + ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); + ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); + + return 0; +} + +/** + * ath5k_hw_set_associd - Set BSSID for association + * + * @ah: The &struct ath5k_hw + * @bssid: BSSID + * @assoc_id: Assoc id + * + * Sets the BSSID which trigers the "SME Join" operation + */ +void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id) +{ + u32 low_id, high_id; + + /* + * Set simple BSSID mask on 5212 + */ + if (ah->ah_version == AR5K_AR5212) { + ath5k_hw_reg_write(ah, AR5K_LOW_ID(ah->ah_bssid_mask), + AR5K_BSS_IDM0); + ath5k_hw_reg_write(ah, AR5K_HIGH_ID(ah->ah_bssid_mask), + AR5K_BSS_IDM1); + } + + /* + * Set BSSID which triggers the "SME Join" operation + */ + low_id = AR5K_LOW_ID(bssid); + high_id = AR5K_HIGH_ID(bssid); + ath5k_hw_reg_write(ah, low_id, AR5K_BSS_ID0); + ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) << + AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1); +} + +/** + * ath5k_hw_set_bssid_mask - filter out bssids we listen + * + * @ah: the &struct ath5k_hw + * @mask: the bssid_mask, a u8 array of size ETH_ALEN + * + * BSSID masking is a method used by AR5212 and newer hardware to inform PCU + * which bits of the interface's MAC address should be looked at when trying + * to decide which packets to ACK. In station mode and AP mode with a single + * BSS every bit matters since we lock to only one BSS. In AP mode with + * multiple BSSes (virtual interfaces) not every bit matters because hw must + * accept frames for all BSSes and so we tweak some bits of our mac address + * in order to have multiple BSSes. + * + * NOTE: This is a simple filter and does *not* filter out all + * relevant frames. Some frames that are not for us might get ACKed from us + * by PCU because they just match the mask. + * + * When handling multiple BSSes you can get the BSSID mask by computing the + * set of ~ ( MAC XOR BSSID ) for all bssids we handle. + * + * When you do this you are essentially computing the common bits of all your + * BSSes. Later it is assumed the harware will "and" (&) the BSSID mask with + * the MAC address to obtain the relevant bits and compare the result with + * (frame's BSSID & mask) to see if they match. + */ +/* + * Simple example: on your card you have have two BSSes you have created with + * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address. + * There is another BSSID-03 but you are not part of it. For simplicity's sake, + * assuming only 4 bits for a mac address and for BSSIDs you can then have: + * + * \ + * MAC: 0001 | + * BSSID-01: 0100 | --> Belongs to us + * BSSID-02: 1001 | + * / + * ------------------- + * BSSID-03: 0110 | --> External + * ------------------- + * + * Our bssid_mask would then be: + * + * On loop iteration for BSSID-01: + * ~(0001 ^ 0100) -> ~(0101) + * -> 1010 + * bssid_mask = 1010 + * + * On loop iteration for BSSID-02: + * bssid_mask &= ~(0001 ^ 1001) + * bssid_mask = (1010) & ~(0001 ^ 1001) + * bssid_mask = (1010) & ~(1001) + * bssid_mask = (1010) & (0110) + * bssid_mask = 0010 + * + * A bssid_mask of 0010 means "only pay attention to the second least + * significant bit". This is because its the only bit common + * amongst the MAC and all BSSIDs we support. To findout what the real + * common bit is we can simply "&" the bssid_mask now with any BSSID we have + * or our MAC address (we assume the hardware uses the MAC address). + * + * Now, suppose there's an incoming frame for BSSID-03: + * + * IFRAME-01: 0110 + * + * An easy eye-inspeciton of this already should tell you that this frame + * will not pass our check. This is beacuse the bssid_mask tells the + * hardware to only look at the second least significant bit and the + * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB + * as 1, which does not match 0. + * + * So with IFRAME-01 we *assume* the hardware will do: + * + * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0; + * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0; + * --> allow = (0010) == 0000 ? 1 : 0; + * --> allow = 0 + * + * Lets now test a frame that should work: + * + * IFRAME-02: 0001 (we should allow) + * + * allow = (0001 & 1010) == 1010 + * + * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0; + * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0; + * --> allow = (0010) == (0010) + * --> allow = 1 + * + * Other examples: + * + * IFRAME-03: 0100 --> allowed + * IFRAME-04: 1001 --> allowed + * IFRAME-05: 1101 --> allowed but its not for us!!! + * + */ +int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) +{ + u32 low_id, high_id; + + /* Cache bssid mask so that we can restore it + * on reset */ + memcpy(ah->ah_bssid_mask, mask, ETH_ALEN); + if (ah->ah_version == AR5K_AR5212) { + low_id = AR5K_LOW_ID(mask); + high_id = AR5K_HIGH_ID(mask); + + ath5k_hw_reg_write(ah, low_id, AR5K_BSS_IDM0); + ath5k_hw_reg_write(ah, high_id, AR5K_BSS_IDM1); + + return 0; + } + + return -EIO; +} + + +/************\ +* RX Control * +\************/ + +/** + * ath5k_hw_start_rx_pcu - Start RX engine + * + * @ah: The &struct ath5k_hw + * + * Starts RX engine on PCU so that hw can process RXed frames + * (ACK etc). + * + * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma + * TODO: Init ANI here + */ +void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) +{ + AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); +} + +/** + * at5k_hw_stop_rx_pcu - Stop RX engine + * + * @ah: The &struct ath5k_hw + * + * Stops RX engine on PCU + * + * TODO: Detach ANI here + */ +void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah) +{ + AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); +} + +/* + * Set multicast filter + */ +void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1) +{ + /* Set the multicat filter */ + ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); + ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); +} + +/** + * ath5k_hw_get_rx_filter - Get current rx filter + * + * @ah: The &struct ath5k_hw + * + * Returns the RX filter by reading rx filter and + * phy error filter registers. RX filter is used + * to set the allowed frame types that PCU will accept + * and pass to the driver. For a list of frame types + * check out reg.h. + */ +u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah) +{ + u32 data, filter = 0; + + filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); + + /*Radar detection for 5212*/ + if (ah->ah_version == AR5K_AR5212) { + data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); + + if (data & AR5K_PHY_ERR_FIL_RADAR) + filter |= AR5K_RX_FILTER_RADARERR; + if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) + filter |= AR5K_RX_FILTER_PHYERR; + } + + return filter; +} + +/** + * ath5k_hw_set_rx_filter - Set rx filter + * + * @ah: The &struct ath5k_hw + * @filter: RX filter mask (see reg.h) + * + * Sets RX filter register and also handles PHY error filter + * register on 5212 and newer chips so that we have proper PHY + * error reporting. + */ +void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter) +{ + u32 data = 0; + + /* Set PHY error filter register on 5212*/ + if (ah->ah_version == AR5K_AR5212) { + if (filter & AR5K_RX_FILTER_RADARERR) + data |= AR5K_PHY_ERR_FIL_RADAR; + if (filter & AR5K_RX_FILTER_PHYERR) + data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; + } + + /* + * The AR5210 uses promiscous mode to detect radar activity + */ + if (ah->ah_version == AR5K_AR5210 && + (filter & AR5K_RX_FILTER_RADARERR)) { + filter &= ~AR5K_RX_FILTER_RADARERR; + filter |= AR5K_RX_FILTER_PROM; + } + + /*Zero length DMA (phy error reporting) */ + if (data) + AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); + else + AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); + + /*Write RX Filter register*/ + ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); + + /*Write PHY error filter register on 5212*/ + if (ah->ah_version == AR5K_AR5212) + ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); + +} + +/*********************\ +* Key table functions * +\*********************/ + +/* + * Reset a key entry on the table + */ +int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry) +{ + unsigned int i, type; + u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET; + + type = ath5k_hw_reg_read(ah, AR5K_KEYTABLE_TYPE(entry)); + + for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) + ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i)); + + /* Reset associated MIC entry if TKIP + * is enabled located at offset (entry + 64) */ + if (type == AR5K_KEYTABLE_TYPE_TKIP) { + for (i = 0; i < AR5K_KEYCACHE_SIZE / 2 ; i++) + ath5k_hw_reg_write(ah, 0, + AR5K_KEYTABLE_OFF(micentry, i)); + } + + /* + * Set NULL encryption on AR5212+ + * + * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5) + * AR5K_KEYTABLE_TYPE_NULL -> 0x00000007 + * + * Note2: Windows driver (ndiswrapper) sets this to + * 0x00000714 instead of 0x00000007 + */ + if (ah->ah_version > AR5K_AR5211) { + ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, + AR5K_KEYTABLE_TYPE(entry)); + + if (type == AR5K_KEYTABLE_TYPE_TKIP) { + ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, + AR5K_KEYTABLE_TYPE(micentry)); + } + } + + return 0; +} diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_phy.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_phy.c new file mode 100644 index 0000000..8856fa3 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_phy.c @@ -0,0 +1,2586 @@ +/* + * PHY functions + * + * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> + * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> + * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> + * + * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +FILE_LICENCE ( MIT ); + +#define _ATH5K_PHY + +#include <unistd.h> +#include <stdlib.h> + +#include "ath5k.h" +#include "reg.h" +#include "base.h" +#include "rfbuffer.h" +#include "rfgain.h" + +static inline int min(int x, int y) +{ + return (x < y) ? x : y; +} + +static inline int max(int x, int y) +{ + return (x > y) ? x : y; +} + +/* + * Used to modify RF Banks before writing them to AR5K_RF_BUFFER + */ +static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, + const struct ath5k_rf_reg *rf_regs, + u32 val, u8 reg_id, int set) +{ + const struct ath5k_rf_reg *rfreg = NULL; + u8 offset, bank, num_bits, col, position; + u16 entry; + u32 mask, data, last_bit, bits_shifted, first_bit; + u32 *rfb; + s32 bits_left; + unsigned i; + + data = 0; + rfb = ah->ah_rf_banks; + + for (i = 0; i < ah->ah_rf_regs_count; i++) { + if (rf_regs[i].index == reg_id) { + rfreg = &rf_regs[i]; + break; + } + } + + if (rfb == NULL || rfreg == NULL) { + DBG("ath5k: RF register not found!\n"); + /* should not happen */ + return 0; + } + + bank = rfreg->bank; + num_bits = rfreg->field.len; + first_bit = rfreg->field.pos; + col = rfreg->field.col; + + /* first_bit is an offset from bank's + * start. Since we have all banks on + * the same array, we use this offset + * to mark each bank's start */ + offset = ah->ah_offset[bank]; + + /* Boundary check */ + if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { + DBG("ath5k: RF invalid values at offset %d\n", offset); + return 0; + } + + entry = ((first_bit - 1) / 8) + offset; + position = (first_bit - 1) % 8; + + if (set) + data = ath5k_hw_bitswap(val, num_bits); + + for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; + position = 0, entry++) { + + last_bit = (position + bits_left > 8) ? 8 : + position + bits_left; + + mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << + (col * 8); + + if (set) { + rfb[entry] &= ~mask; + rfb[entry] |= ((data << position) << (col * 8)) & mask; + data >>= (8 - position); + } else { + data |= (((rfb[entry] & mask) >> (col * 8)) >> position) + << bits_shifted; + bits_shifted += last_bit - position; + } + + bits_left -= 8 - position; + } + + data = set ? 1 : ath5k_hw_bitswap(data, num_bits); + + return data; +} + +/**********************\ +* RF Gain optimization * +\**********************/ + +/* + * This code is used to optimize rf gain on different environments + * (temprature mostly) based on feedback from a power detector. + * + * It's only used on RF5111 and RF5112, later RF chips seem to have + * auto adjustment on hw -notice they have a much smaller BANK 7 and + * no gain optimization ladder-. + * + * For more infos check out this patent doc + * http://www.freepatentsonline.com/7400691.html + * + * This paper describes power drops as seen on the receiver due to + * probe packets + * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues + * %20of%20Power%20Control.pdf + * + * And this is the MadWiFi bug entry related to the above + * http://madwifi-project.org/ticket/1659 + * with various measurements and diagrams + * + * TODO: Deal with power drops due to probes by setting an apropriate + * tx power on the probe packets ! Make this part of the calibration process. + */ + +/* Initialize ah_gain durring attach */ +int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) +{ + /* Initialize the gain optimization values */ + switch (ah->ah_radio) { + case AR5K_RF5111: + ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; + ah->ah_gain.g_low = 20; + ah->ah_gain.g_high = 35; + ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; + break; + case AR5K_RF5112: + ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; + ah->ah_gain.g_low = 20; + ah->ah_gain.g_high = 85; + ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; + break; + default: + return -EINVAL; + } + + return 0; +} + +/* Schedule a gain probe check on the next transmited packet. + * That means our next packet is going to be sent with lower + * tx power and a Peak to Average Power Detector (PAPD) will try + * to measure the gain. + * + * TODO: Use propper tx power setting for the probe packet so + * that we don't observe a serious power drop on the receiver + * + * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) + * just after we enable the probe so that we don't mess with + * standard traffic ? Maybe it's time to use sw interrupts and + * a probe tasklet !!! + */ +static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) +{ + + /* Skip if gain calibration is inactive or + * we already handle a probe request */ + if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) + return; + + /* Send the packet with 2dB below max power as + * patent doc suggest */ + ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max_pwr - 4, + AR5K_PHY_PAPD_PROBE_TXPOWER) | + AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); + + ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; + +} + +/* Calculate gain_F measurement correction + * based on the current step for RF5112 rev. 2 */ +static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) +{ + u32 mix, step; + u32 *rf; + const struct ath5k_gain_opt *go; + const struct ath5k_gain_opt_step *g_step; + const struct ath5k_rf_reg *rf_regs; + + /* Only RF5112 Rev. 2 supports it */ + if ((ah->ah_radio != AR5K_RF5112) || + (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) + return 0; + + go = &rfgain_opt_5112; + rf_regs = rf_regs_5112a; + ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); + + g_step = &go->go_step[ah->ah_gain.g_step_idx]; + + if (ah->ah_rf_banks == NULL) + return 0; + + rf = ah->ah_rf_banks; + ah->ah_gain.g_f_corr = 0; + + /* No VGA (Variable Gain Amplifier) override, skip */ + if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 0) != 1) + return 0; + + /* Mix gain stepping */ + step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, 0); + + /* Mix gain override */ + mix = g_step->gos_param[0]; + + switch (mix) { + case 3: + ah->ah_gain.g_f_corr = step * 2; + break; + case 2: + ah->ah_gain.g_f_corr = (step - 5) * 2; + break; + case 1: + ah->ah_gain.g_f_corr = step; + break; + default: + ah->ah_gain.g_f_corr = 0; + break; + } + + return ah->ah_gain.g_f_corr; +} + +/* Check if current gain_F measurement is in the range of our + * power detector windows. If we get a measurement outside range + * we know it's not accurate (detectors can't measure anything outside + * their detection window) so we must ignore it */ +static int ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) +{ + const struct ath5k_rf_reg *rf_regs; + u32 step, mix_ovr, level[4]; + u32 *rf; + + if (ah->ah_rf_banks == NULL) + return 0; + + rf = ah->ah_rf_banks; + + if (ah->ah_radio == AR5K_RF5111) { + + rf_regs = rf_regs_5111; + ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); + + step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, + 0); + + level[0] = 0; + level[1] = (step == 63) ? 50 : step + 4; + level[2] = (step != 63) ? 64 : level[0]; + level[3] = level[2] + 50 ; + + ah->ah_gain.g_high = level[3] - + (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); + ah->ah_gain.g_low = level[0] + + (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); + } else { + + rf_regs = rf_regs_5112; + ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); + + mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, + 0); + + level[0] = level[2] = 0; + + if (mix_ovr == 1) { + level[1] = level[3] = 83; + } else { + level[1] = level[3] = 107; + ah->ah_gain.g_high = 55; + } + } + + return (ah->ah_gain.g_current >= level[0] && + ah->ah_gain.g_current <= level[1]) || + (ah->ah_gain.g_current >= level[2] && + ah->ah_gain.g_current <= level[3]); +} + +/* Perform gain_F adjustment by choosing the right set + * of parameters from rf gain optimization ladder */ +static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) +{ + const struct ath5k_gain_opt *go; + const struct ath5k_gain_opt_step *g_step; + int ret = 0; + + switch (ah->ah_radio) { + case AR5K_RF5111: + go = &rfgain_opt_5111; + break; + case AR5K_RF5112: + go = &rfgain_opt_5112; + break; + default: + return 0; + } + + g_step = &go->go_step[ah->ah_gain.g_step_idx]; + + if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { + + /* Reached maximum */ + if (ah->ah_gain.g_step_idx == 0) + return -1; + + for (ah->ah_gain.g_target = ah->ah_gain.g_current; + ah->ah_gain.g_target >= ah->ah_gain.g_high && + ah->ah_gain.g_step_idx > 0; + g_step = &go->go_step[ah->ah_gain.g_step_idx]) + ah->ah_gain.g_target -= 2 * + (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - + g_step->gos_gain); + + ret = 1; + goto done; + } + + if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { + + /* Reached minimum */ + if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) + return -2; + + for (ah->ah_gain.g_target = ah->ah_gain.g_current; + ah->ah_gain.g_target <= ah->ah_gain.g_low && + ah->ah_gain.g_step_idx < go->go_steps_count-1; + g_step = &go->go_step[ah->ah_gain.g_step_idx]) + ah->ah_gain.g_target -= 2 * + (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - + g_step->gos_gain); + + ret = 2; + goto done; + } + +done: + DBG2("ath5k RF adjust: ret %d, gain step %d, current gain %d, " + "target gain %d\n", ret, ah->ah_gain.g_step_idx, + ah->ah_gain.g_current, ah->ah_gain.g_target); + + return ret; +} + +/* Main callback for thermal rf gain calibration engine + * Check for a new gain reading and schedule an adjustment + * if needed. + * + * TODO: Use sw interrupt to schedule reset if gain_F needs + * adjustment */ +enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) +{ + u32 data, type; + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + + if (ah->ah_rf_banks == NULL || + ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) + return AR5K_RFGAIN_INACTIVE; + + /* No check requested, either engine is inactive + * or an adjustment is already requested */ + if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) + goto done; + + /* Read the PAPD (Peak to Average Power Detector) + * register */ + data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); + + /* No probe is scheduled, read gain_F measurement */ + if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { + ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; + type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); + + /* If tx packet is CCK correct the gain_F measurement + * by cck ofdm gain delta */ + if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { + if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) + ah->ah_gain.g_current += + ee->ee_cck_ofdm_gain_delta; + else + ah->ah_gain.g_current += + AR5K_GAIN_CCK_PROBE_CORR; + } + + /* Further correct gain_F measurement for + * RF5112A radios */ + if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { + ath5k_hw_rf_gainf_corr(ah); + ah->ah_gain.g_current = + ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? + (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : + 0; + } + + /* Check if measurement is ok and if we need + * to adjust gain, schedule a gain adjustment, + * else switch back to the acive state */ + if (ath5k_hw_rf_check_gainf_readback(ah) && + AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && + ath5k_hw_rf_gainf_adjust(ah)) { + ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; + } else { + ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; + } + } + +done: + return ah->ah_gain.g_state; +} + +/* Write initial rf gain table to set the RF sensitivity + * this one works on all RF chips and has nothing to do + * with gain_F calibration */ +int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq) +{ + const struct ath5k_ini_rfgain *ath5k_rfg; + unsigned int i, size; + + switch (ah->ah_radio) { + case AR5K_RF5111: + ath5k_rfg = rfgain_5111; + size = ARRAY_SIZE(rfgain_5111); + break; + case AR5K_RF5112: + ath5k_rfg = rfgain_5112; + size = ARRAY_SIZE(rfgain_5112); + break; + case AR5K_RF2413: + ath5k_rfg = rfgain_2413; + size = ARRAY_SIZE(rfgain_2413); + break; + case AR5K_RF2316: + ath5k_rfg = rfgain_2316; + size = ARRAY_SIZE(rfgain_2316); + break; + case AR5K_RF5413: + ath5k_rfg = rfgain_5413; + size = ARRAY_SIZE(rfgain_5413); + break; + case AR5K_RF2317: + case AR5K_RF2425: + ath5k_rfg = rfgain_2425; + size = ARRAY_SIZE(rfgain_2425); + break; + default: + return -EINVAL; + } + + switch (freq) { + case AR5K_INI_RFGAIN_2GHZ: + case AR5K_INI_RFGAIN_5GHZ: + break; + default: + return -EINVAL; + } + + for (i = 0; i < size; i++) { + AR5K_REG_WAIT(i); + ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq], + (u32)ath5k_rfg[i].rfg_register); + } + + return 0; +} + + + +/********************\ +* RF Registers setup * +\********************/ + + +/* + * Setup RF registers by writing rf buffer on hw + */ +int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct net80211_channel *channel, + unsigned int mode) +{ + const struct ath5k_rf_reg *rf_regs; + const struct ath5k_ini_rfbuffer *ini_rfb; + const struct ath5k_gain_opt *go = NULL; + const struct ath5k_gain_opt_step *g_step; + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + u8 ee_mode = 0; + u32 *rfb; + int obdb = -1, bank = -1; + unsigned i; + + switch (ah->ah_radio) { + case AR5K_RF5111: + rf_regs = rf_regs_5111; + ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); + ini_rfb = rfb_5111; + ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); + go = &rfgain_opt_5111; + break; + case AR5K_RF5112: + if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { + rf_regs = rf_regs_5112a; + ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); + ini_rfb = rfb_5112a; + ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); + } else { + rf_regs = rf_regs_5112; + ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); + ini_rfb = rfb_5112; + ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); + } + go = &rfgain_opt_5112; + break; + case AR5K_RF2413: + rf_regs = rf_regs_2413; + ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); + ini_rfb = rfb_2413; + ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); + break; + case AR5K_RF2316: + rf_regs = rf_regs_2316; + ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); + ini_rfb = rfb_2316; + ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); + break; + case AR5K_RF5413: + rf_regs = rf_regs_5413; + ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); + ini_rfb = rfb_5413; + ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); + break; + case AR5K_RF2317: + rf_regs = rf_regs_2425; + ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); + ini_rfb = rfb_2317; + ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); + break; + case AR5K_RF2425: + rf_regs = rf_regs_2425; + ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); + if (ah->ah_mac_srev < AR5K_SREV_AR2417) { + ini_rfb = rfb_2425; + ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); + } else { + ini_rfb = rfb_2417; + ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); + } + break; + default: + return -EINVAL; + } + + /* If it's the first time we set rf buffer, allocate + * ah->ah_rf_banks based on ah->ah_rf_banks_size + * we set above */ + if (ah->ah_rf_banks == NULL) { + ah->ah_rf_banks = malloc(sizeof(u32) * ah->ah_rf_banks_size); + if (ah->ah_rf_banks == NULL) { + return -ENOMEM; + } + } + + /* Copy values to modify them */ + rfb = ah->ah_rf_banks; + + for (i = 0; i < ah->ah_rf_banks_size; i++) { + if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { + DBG("ath5k: invalid RF register bank\n"); + return -EINVAL; + } + + /* Bank changed, write down the offset */ + if (bank != ini_rfb[i].rfb_bank) { + bank = ini_rfb[i].rfb_bank; + ah->ah_offset[bank] = i; + } + + rfb[i] = ini_rfb[i].rfb_mode_data[mode]; + } + + /* Set Output and Driver bias current (OB/DB) */ + if (channel->hw_value & CHANNEL_2GHZ) { + + if (channel->hw_value & CHANNEL_CCK) + ee_mode = AR5K_EEPROM_MODE_11B; + else + ee_mode = AR5K_EEPROM_MODE_11G; + + /* For RF511X/RF211X combination we + * use b_OB and b_DB parameters stored + * in eeprom on ee->ee_ob[ee_mode][0] + * + * For all other chips we use OB/DB for 2Ghz + * stored in the b/g modal section just like + * 802.11a on ee->ee_ob[ee_mode][1] */ + if ((ah->ah_radio == AR5K_RF5111) || + (ah->ah_radio == AR5K_RF5112)) + obdb = 0; + else + obdb = 1; + + ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], + AR5K_RF_OB_2GHZ, 1); + + ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], + AR5K_RF_DB_2GHZ, 1); + + /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ + } else if ((channel->hw_value & CHANNEL_5GHZ) || + (ah->ah_radio == AR5K_RF5111)) { + + /* For 11a, Turbo and XR we need to choose + * OB/DB based on frequency range */ + ee_mode = AR5K_EEPROM_MODE_11A; + obdb = channel->center_freq >= 5725 ? 3 : + (channel->center_freq >= 5500 ? 2 : + (channel->center_freq >= 5260 ? 1 : + (channel->center_freq > 4000 ? 0 : -1))); + + if (obdb < 0) + return -EINVAL; + + ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], + AR5K_RF_OB_5GHZ, 1); + + ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], + AR5K_RF_DB_5GHZ, 1); + } + + g_step = &go->go_step[ah->ah_gain.g_step_idx]; + + /* Bank Modifications (chip-specific) */ + if (ah->ah_radio == AR5K_RF5111) { + + /* Set gain_F settings according to current step */ + if (channel->hw_value & CHANNEL_OFDM) { + + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, + AR5K_PHY_FRAME_CTL_TX_CLIP, + g_step->gos_param[0]); + + ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], + AR5K_RF_PWD_90, 1); + + ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], + AR5K_RF_PWD_84, 1); + + ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], + AR5K_RF_RFGAIN_SEL, 1); + + /* We programmed gain_F parameters, switch back + * to active state */ + ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; + + } + + /* Bank 6/7 setup */ + + ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], + AR5K_RF_PWD_XPD, 1); + + ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], + AR5K_RF_XPD_GAIN, 1); + + ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], + AR5K_RF_GAIN_I, 1); + + ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], + AR5K_RF_PLO_SEL, 1); + + /* TODO: Half/quarter channel support */ + } + + if (ah->ah_radio == AR5K_RF5112) { + + /* Set gain_F settings according to current step */ + if (channel->hw_value & CHANNEL_OFDM) { + + ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], + AR5K_RF_MIXGAIN_OVR, 1); + + ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], + AR5K_RF_PWD_138, 1); + + ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], + AR5K_RF_PWD_137, 1); + + ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], + AR5K_RF_PWD_136, 1); + + ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], + AR5K_RF_PWD_132, 1); + + ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], + AR5K_RF_PWD_131, 1); + + ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], + AR5K_RF_PWD_130, 1); + + /* We programmed gain_F parameters, switch back + * to active state */ + ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; + } + + /* Bank 6/7 setup */ + + ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], + AR5K_RF_XPD_SEL, 1); + + if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { + /* Rev. 1 supports only one xpd */ + ath5k_hw_rfb_op(ah, rf_regs, + ee->ee_x_gain[ee_mode], + AR5K_RF_XPD_GAIN, 1); + + } else { + /* TODO: Set high and low gain bits */ + ath5k_hw_rfb_op(ah, rf_regs, + ee->ee_x_gain[ee_mode], + AR5K_RF_PD_GAIN_LO, 1); + ath5k_hw_rfb_op(ah, rf_regs, + ee->ee_x_gain[ee_mode], + AR5K_RF_PD_GAIN_HI, 1); + + /* Lower synth voltage on Rev 2 */ + ath5k_hw_rfb_op(ah, rf_regs, 2, + AR5K_RF_HIGH_VC_CP, 1); + + ath5k_hw_rfb_op(ah, rf_regs, 2, + AR5K_RF_MID_VC_CP, 1); + + ath5k_hw_rfb_op(ah, rf_regs, 2, + AR5K_RF_LOW_VC_CP, 1); + + ath5k_hw_rfb_op(ah, rf_regs, 2, + AR5K_RF_PUSH_UP, 1); + + /* Decrease power consumption on 5213+ BaseBand */ + if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { + ath5k_hw_rfb_op(ah, rf_regs, 1, + AR5K_RF_PAD2GND, 1); + + ath5k_hw_rfb_op(ah, rf_regs, 1, + AR5K_RF_XB2_LVL, 1); + + ath5k_hw_rfb_op(ah, rf_regs, 1, + AR5K_RF_XB5_LVL, 1); + + ath5k_hw_rfb_op(ah, rf_regs, 1, + AR5K_RF_PWD_167, 1); + + ath5k_hw_rfb_op(ah, rf_regs, 1, + AR5K_RF_PWD_166, 1); + } + } + + ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], + AR5K_RF_GAIN_I, 1); + + /* TODO: Half/quarter channel support */ + + } + + if (ah->ah_radio == AR5K_RF5413 && + channel->hw_value & CHANNEL_2GHZ) { + + ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, + 1); + + /* Set optimum value for early revisions (on pci-e chips) */ + if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && + ah->ah_mac_srev < AR5K_SREV_AR5413) + ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), + AR5K_RF_PWD_ICLOBUF_2G, 1); + + } + + /* Write RF banks on hw */ + for (i = 0; i < ah->ah_rf_banks_size; i++) { + AR5K_REG_WAIT(i); + ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); + } + + return 0; +} + + +/**************************\ + PHY/RF channel functions +\**************************/ + +/* + * Check if a channel is supported + */ +int ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags) +{ + /* Check if the channel is in our supported range */ + if (flags & CHANNEL_2GHZ) { + if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && + (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) + return 1; + } else if (flags & CHANNEL_5GHZ) + if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && + (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) + return 1; + + return 0; +} + +/* + * Convertion needed for RF5110 + */ +static u32 ath5k_hw_rf5110_chan2athchan(struct net80211_channel *channel) +{ + u32 athchan; + + /* + * Convert IEEE channel/MHz to an internal channel value used + * by the AR5210 chipset. This has not been verified with + * newer chipsets like the AR5212A who have a completely + * different RF/PHY part. + */ + athchan = (ath5k_hw_bitswap((ath5k_freq_to_channel(channel->center_freq) + - 24) / 2, 5) << 1) + | (1 << 6) | 0x1; + return athchan; +} + +/* + * Set channel on RF5110 + */ +static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, + struct net80211_channel *channel) +{ + u32 data; + + /* + * Set the channel and wait + */ + data = ath5k_hw_rf5110_chan2athchan(channel); + ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); + ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); + mdelay(1); + + return 0; +} + +/* + * Convertion needed for 5111 + */ +static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, + struct ath5k_athchan_2ghz *athchan) +{ + int channel; + + /* Cast this value to catch negative channel numbers (>= -19) */ + channel = (int)ieee; + + /* + * Map 2GHz IEEE channel to 5GHz Atheros channel + */ + if (channel <= 13) { + athchan->a2_athchan = 115 + channel; + athchan->a2_flags = 0x46; + } else if (channel == 14) { + athchan->a2_athchan = 124; + athchan->a2_flags = 0x44; + } else if (channel >= 15 && channel <= 26) { + athchan->a2_athchan = ((channel - 14) * 4) + 132; + athchan->a2_flags = 0x46; + } else + return -EINVAL; + + return 0; +} + +/* + * Set channel on 5111 + */ +static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, + struct net80211_channel *channel) +{ + struct ath5k_athchan_2ghz ath5k_channel_2ghz; + unsigned int ath5k_channel = ath5k_freq_to_channel(channel->center_freq); + u32 data0, data1, clock; + int ret; + + /* + * Set the channel on the RF5111 radio + */ + data0 = data1 = 0; + + if (channel->hw_value & CHANNEL_2GHZ) { + /* Map 2GHz channel to 5GHz Atheros channel ID */ + ret = ath5k_hw_rf5111_chan2athchan(ath5k_channel, + &ath5k_channel_2ghz); + if (ret) + return ret; + + ath5k_channel = ath5k_channel_2ghz.a2_athchan; + data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) + << 5) | (1 << 4); + } + + if (ath5k_channel < 145 || !(ath5k_channel & 1)) { + clock = 1; + data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | + (clock << 1) | (1 << 10) | 1; + } else { + clock = 0; + data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) + << 2) | (clock << 1) | (1 << 10) | 1; + } + + ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), + AR5K_RF_BUFFER); + ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), + AR5K_RF_BUFFER_CONTROL_3); + + return 0; +} + +/* + * Set channel on 5112 and newer + */ +static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, + struct net80211_channel *channel) +{ + u32 data, data0, data1, data2; + u16 c; + + data = data0 = data1 = data2 = 0; + c = channel->center_freq; + + if (c < 4800) { + if (!((c - 2224) % 5)) { + data0 = ((2 * (c - 704)) - 3040) / 10; + data1 = 1; + } else if (!((c - 2192) % 5)) { + data0 = ((2 * (c - 672)) - 3040) / 10; + data1 = 0; + } else + return -EINVAL; + + data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); + } else if ((c - (c % 5)) != 2 || c > 5435) { + if (!(c % 20) && c >= 5120) { + data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); + data2 = ath5k_hw_bitswap(3, 2); + } else if (!(c % 10)) { + data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); + data2 = ath5k_hw_bitswap(2, 2); + } else if (!(c % 5)) { + data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); + data2 = ath5k_hw_bitswap(1, 2); + } else + return -EINVAL; + } else { + data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); + data2 = ath5k_hw_bitswap(0, 2); + } + + data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; + + ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); + ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); + + return 0; +} + +/* + * Set the channel on the RF2425 + */ +static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, + struct net80211_channel *channel) +{ + u32 data, data0, data2; + u16 c; + + data = data0 = data2 = 0; + c = channel->center_freq; + + if (c < 4800) { + data0 = ath5k_hw_bitswap((c - 2272), 8); + data2 = 0; + /* ? 5GHz ? */ + } else if ((c - (c % 5)) != 2 || c > 5435) { + if (!(c % 20) && c < 5120) + data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); + else if (!(c % 10)) + data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); + else if (!(c % 5)) + data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); + else + return -EINVAL; + data2 = ath5k_hw_bitswap(1, 2); + } else { + data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); + data2 = ath5k_hw_bitswap(0, 2); + } + + data = (data0 << 4) | data2 << 2 | 0x1001; + + ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); + ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); + + return 0; +} + +/* + * Set a channel on the radio chip + */ +int ath5k_hw_channel(struct ath5k_hw *ah, struct net80211_channel *channel) +{ + int ret; + /* + * Check bounds supported by the PHY (we don't care about regultory + * restrictions at this point). Note: hw_value already has the band + * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() + * of the band by that */ + if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { + DBG("ath5k: channel frequency (%d MHz) out of supported " + "range\n", channel->center_freq); + return -EINVAL; + } + + /* + * Set the channel and wait + */ + switch (ah->ah_radio) { + case AR5K_RF5110: + ret = ath5k_hw_rf5110_channel(ah, channel); + break; + case AR5K_RF5111: + ret = ath5k_hw_rf5111_channel(ah, channel); + break; + case AR5K_RF2425: + ret = ath5k_hw_rf2425_channel(ah, channel); + break; + default: + ret = ath5k_hw_rf5112_channel(ah, channel); + break; + } + + if (ret) { + DBG("ath5k: setting channel failed: %s\n", strerror(ret)); + return ret; + } + + /* Set JAPAN setting for channel 14 */ + if (channel->center_freq == 2484) { + AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, + AR5K_PHY_CCKTXCTL_JAPAN); + } else { + AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, + AR5K_PHY_CCKTXCTL_WORLD); + } + + ah->ah_current_channel = channel; + ah->ah_turbo = (channel->hw_value == CHANNEL_T ? 1 : 0); + + return 0; +} + +/*****************\ + PHY calibration +\*****************/ + +/** + * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration + * + * @ah: struct ath5k_hw pointer we are operating on + * @freq: the channel frequency, just used for error logging + * + * This function performs a noise floor calibration of the PHY and waits for + * it to complete. Then the noise floor value is compared to some maximum + * noise floor we consider valid. + * + * Note that this is different from what the madwifi HAL does: it reads the + * noise floor and afterwards initiates the calibration. Since the noise floor + * calibration can take some time to finish, depending on the current channel + * use, that avoids the occasional timeout warnings we are seeing now. + * + * See the following link for an Atheros patent on noise floor calibration: + * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \ + * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7 + * + * XXX: Since during noise floor calibration antennas are detached according to + * the patent, we should stop tx queues here. + */ +int +ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq) +{ + int ret; + unsigned int i; + s32 noise_floor; + + /* + * Enable noise floor calibration + */ + AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_NF); + + ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_NF, 0, 0); + + if (ret) { + DBG("ath5k: noise floor calibration timeout (%d MHz)\n", freq); + return -EAGAIN; + } + + /* Wait until the noise floor is calibrated and read the value */ + for (i = 20; i > 0; i--) { + mdelay(1); + noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF); + noise_floor = AR5K_PHY_NF_RVAL(noise_floor); + if (noise_floor & AR5K_PHY_NF_ACTIVE) { + noise_floor = AR5K_PHY_NF_AVAL(noise_floor); + + if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) + break; + } + } + + DBG2("ath5k: noise floor %d\n", noise_floor); + + if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { + DBG("ath5k: noise floor calibration failed (%d MHz)\n", freq); + return -EAGAIN; + } + + ah->ah_noise_floor = noise_floor; + + return 0; +} + +/* + * Perform a PHY calibration on RF5110 + * -Fix BPSK/QAM Constellation (I/Q correction) + * -Calculate Noise Floor + */ +static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, + struct net80211_channel *channel) +{ + u32 phy_sig, phy_agc, phy_sat, beacon; + int ret; + + /* + * Disable beacons and RX/TX queues, wait + */ + AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, + AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); + beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); + ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); + + mdelay(2); + + /* + * Set the channel (with AGC turned off) + */ + AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); + udelay(10); + ret = ath5k_hw_channel(ah, channel); + + /* + * Activate PHY and wait + */ + ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); + mdelay(1); + + AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); + + if (ret) + return ret; + + /* + * Calibrate the radio chip + */ + + /* Remember normal state */ + phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); + phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); + phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); + + /* Update radio registers */ + ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | + AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); + + ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | + AR5K_PHY_AGCCOARSE_LO)) | + AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | + AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); + + ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | + AR5K_PHY_ADCSAT_THR)) | + AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | + AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); + + udelay(20); + + AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); + udelay(10); + ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); + AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); + + mdelay(1); + + /* + * Enable calibration and wait until completion + */ + AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); + + ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_CAL, 0, 0); + + /* Reset to normal state */ + ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); + ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); + ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); + + if (ret) { + DBG("ath5k: calibration timeout (%d MHz)\n", + channel->center_freq); + return ret; + } + + ath5k_hw_noise_floor_calibration(ah, channel->center_freq); + + /* + * Re-enable RX/TX and beacons + */ + AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, + AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); + ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); + + return 0; +} + +/* + * Perform a PHY calibration on RF5111/5112 and newer chips + */ +static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, + struct net80211_channel *channel) +{ + u32 i_pwr, q_pwr; + s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; + int i; + + if (!ah->ah_calibration || + ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) + goto done; + + /* Calibration has finished, get the results and re-run */ + for (i = 0; i <= 10; i++) { + iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); + i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); + q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); + } + + i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; + q_coffd = q_pwr >> 7; + + /* No correction */ + if (i_coffd == 0 || q_coffd == 0) + goto done; + + i_coff = ((-iq_corr) / i_coffd) & 0x3f; + + /* Boundary check */ + if (i_coff > 31) + i_coff = 31; + if (i_coff < -32) + i_coff = -32; + + q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f; + + /* Boundary check */ + if (q_coff > 15) + q_coff = 15; + if (q_coff < -16) + q_coff = -16; + + /* Commit new I/Q value */ + AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | + ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); + + /* Re-enable calibration -if we don't we'll commit + * the same values again and again */ + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, + AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); + AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); + +done: + + /* TODO: Separate noise floor calibration from I/Q calibration + * since noise floor calibration interrupts rx path while I/Q + * calibration doesn't. We don't need to run noise floor calibration + * as often as I/Q calibration.*/ + ath5k_hw_noise_floor_calibration(ah, channel->center_freq); + + /* Initiate a gain_F calibration */ + ath5k_hw_request_rfgain_probe(ah); + + return 0; +} + +/* + * Perform a PHY calibration + */ +int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, + struct net80211_channel *channel) +{ + int ret; + + if (ah->ah_radio == AR5K_RF5110) + ret = ath5k_hw_rf5110_calibrate(ah, channel); + else + ret = ath5k_hw_rf511x_calibrate(ah, channel); + + return ret; +} + +int ath5k_hw_phy_disable(struct ath5k_hw *ah) +{ + ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); + + return 0; +} + +/********************\ + Misc PHY functions +\********************/ + +/* + * Get the PHY Chip revision + */ +u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan) +{ + unsigned int i; + u32 srev; + u16 ret; + + /* + * Set the radio chip access register + */ + switch (chan) { + case CHANNEL_2GHZ: + ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); + break; + case CHANNEL_5GHZ: + ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); + break; + default: + return 0; + } + + mdelay(2); + + /* ...wait until PHY is ready and read the selected radio revision */ + ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); + + for (i = 0; i < 8; i++) + ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); + + if (ah->ah_version == AR5K_AR5210) { + srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; + ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; + } else { + srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; + ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | + ((srev & 0x0f) << 4), 8); + } + + /* Reset to the 5GHz mode */ + ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); + + return ret; +} + +void /*TODO:Boundary check*/ +ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant) +{ + if (ah->ah_version != AR5K_AR5210) + ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA); +} + +unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah) +{ + if (ah->ah_version != AR5K_AR5210) + return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA); + + return 0; /*XXX: What do we return for 5210 ?*/ +} + + +/****************\ +* TX power setup * +\****************/ + +/* + * Helper functions + */ + +/* + * Do linear interpolation between two given (x, y) points + */ +static s16 +ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, + s16 y_left, s16 y_right) +{ + s16 ratio, result; + + /* Avoid divide by zero and skip interpolation + * if we have the same point */ + if ((x_left == x_right) || (y_left == y_right)) + return y_left; + + /* + * Since we use ints and not fps, we need to scale up in + * order to get a sane ratio value (or else we 'll eg. get + * always 1 instead of 1.25, 1.75 etc). We scale up by 100 + * to have some accuracy both for 0.5 and 0.25 steps. + */ + ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left)); + + /* Now scale down to be in range */ + result = y_left + (ratio * (target - x_left) / 100); + + return result; +} + +/* + * Find vertical boundary (min pwr) for the linear PCDAC curve. + * + * Since we have the top of the curve and we draw the line below + * until we reach 1 (1 pcdac step) we need to know which point + * (x value) that is so that we don't go below y axis and have negative + * pcdac values when creating the curve, or fill the table with zeroes. + */ +static s16 +ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, + const s16 *pwrL, const s16 *pwrR) +{ + s8 tmp; + s16 min_pwrL, min_pwrR; + s16 pwr_i; + + if (pwrL[0] == pwrL[1]) + min_pwrL = pwrL[0]; + else { + pwr_i = pwrL[0]; + do { + pwr_i--; + tmp = (s8) ath5k_get_interpolated_value(pwr_i, + pwrL[0], pwrL[1], + stepL[0], stepL[1]); + } while (tmp > 1); + + min_pwrL = pwr_i; + } + + if (pwrR[0] == pwrR[1]) + min_pwrR = pwrR[0]; + else { + pwr_i = pwrR[0]; + do { + pwr_i--; + tmp = (s8) ath5k_get_interpolated_value(pwr_i, + pwrR[0], pwrR[1], + stepR[0], stepR[1]); + } while (tmp > 1); + + min_pwrR = pwr_i; + } + + /* Keep the right boundary so that it works for both curves */ + return max(min_pwrL, min_pwrR); +} + +/* + * Interpolate (pwr,vpd) points to create a Power to PDADC or a + * Power to PCDAC curve. + * + * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC + * steps (offsets) on y axis. Power can go up to 31.5dB and max + * PCDAC/PDADC step for each curve is 64 but we can write more than + * one curves on hw so we can go up to 128 (which is the max step we + * can write on the final table). + * + * We write y values (PCDAC/PDADC steps) on hw. + */ +static void +ath5k_create_power_curve(s16 pmin, s16 pmax, + const s16 *pwr, const u8 *vpd, + u8 num_points, + u8 *vpd_table, u8 type) +{ + u8 idx[2] = { 0, 1 }; + s16 pwr_i = 2*pmin; + int i; + + if (num_points < 2) + return; + + /* We want the whole line, so adjust boundaries + * to cover the entire power range. Note that + * power values are already 0.25dB so no need + * to multiply pwr_i by 2 */ + if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { + pwr_i = pmin; + pmin = 0; + pmax = 63; + } + + /* Find surrounding turning points (TPs) + * and interpolate between them */ + for (i = 0; (i <= (u16) (pmax - pmin)) && + (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { + + /* We passed the right TP, move to the next set of TPs + * if we pass the last TP, extrapolate above using the last + * two TPs for ratio */ + if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { + idx[0]++; + idx[1]++; + } + + vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, + pwr[idx[0]], pwr[idx[1]], + vpd[idx[0]], vpd[idx[1]]); + + /* Increase by 0.5dB + * (0.25 dB units) */ + pwr_i += 2; + } +} + +/* + * Get the surrounding per-channel power calibration piers + * for a given frequency so that we can interpolate between + * them and come up with an apropriate dataset for our current + * channel. + */ +static void +ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, + struct net80211_channel *channel, + struct ath5k_chan_pcal_info **pcinfo_l, + struct ath5k_chan_pcal_info **pcinfo_r) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + struct ath5k_chan_pcal_info *pcinfo; + u8 idx_l, idx_r; + u8 mode, max, i; + u32 target = channel->center_freq; + + idx_l = 0; + idx_r = 0; + + if (!(channel->hw_value & CHANNEL_OFDM)) { + pcinfo = ee->ee_pwr_cal_b; + mode = AR5K_EEPROM_MODE_11B; + } else if (channel->hw_value & CHANNEL_2GHZ) { + pcinfo = ee->ee_pwr_cal_g; + mode = AR5K_EEPROM_MODE_11G; + } else { + pcinfo = ee->ee_pwr_cal_a; + mode = AR5K_EEPROM_MODE_11A; + } + max = ee->ee_n_piers[mode] - 1; + + /* Frequency is below our calibrated + * range. Use the lowest power curve + * we have */ + if (target < pcinfo[0].freq) { + idx_l = idx_r = 0; + goto done; + } + + /* Frequency is above our calibrated + * range. Use the highest power curve + * we have */ + if (target > pcinfo[max].freq) { + idx_l = idx_r = max; + goto done; + } + + /* Frequency is inside our calibrated + * channel range. Pick the surrounding + * calibration piers so that we can + * interpolate */ + for (i = 0; i <= max; i++) { + + /* Frequency matches one of our calibration + * piers, no need to interpolate, just use + * that calibration pier */ + if (pcinfo[i].freq == target) { + idx_l = idx_r = i; + goto done; + } + + /* We found a calibration pier that's above + * frequency, use this pier and the previous + * one to interpolate */ + if (target < pcinfo[i].freq) { + idx_r = i; + idx_l = idx_r - 1; + goto done; + } + } + +done: + *pcinfo_l = &pcinfo[idx_l]; + *pcinfo_r = &pcinfo[idx_r]; + + return; +} + +/* + * Get the surrounding per-rate power calibration data + * for a given frequency and interpolate between power + * values to set max target power supported by hw for + * each rate. + */ +static void +ath5k_get_rate_pcal_data(struct ath5k_hw *ah, + struct net80211_channel *channel, + struct ath5k_rate_pcal_info *rates) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + struct ath5k_rate_pcal_info *rpinfo; + u8 idx_l, idx_r; + u8 mode, max, i; + u32 target = channel->center_freq; + + idx_l = 0; + idx_r = 0; + + if (!(channel->hw_value & CHANNEL_OFDM)) { + rpinfo = ee->ee_rate_tpwr_b; + mode = AR5K_EEPROM_MODE_11B; + } else if (channel->hw_value & CHANNEL_2GHZ) { + rpinfo = ee->ee_rate_tpwr_g; + mode = AR5K_EEPROM_MODE_11G; + } else { + rpinfo = ee->ee_rate_tpwr_a; + mode = AR5K_EEPROM_MODE_11A; + } + max = ee->ee_rate_target_pwr_num[mode] - 1; + + /* Get the surrounding calibration + * piers - same as above */ + if (target < rpinfo[0].freq) { + idx_l = idx_r = 0; + goto done; + } + + if (target > rpinfo[max].freq) { + idx_l = idx_r = max; + goto done; + } + + for (i = 0; i <= max; i++) { + + if (rpinfo[i].freq == target) { + idx_l = idx_r = i; + goto done; + } + + if (target < rpinfo[i].freq) { + idx_r = i; + idx_l = idx_r - 1; + goto done; + } + } + +done: + /* Now interpolate power value, based on the frequency */ + rates->freq = target; + + rates->target_power_6to24 = + ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, + rpinfo[idx_r].freq, + rpinfo[idx_l].target_power_6to24, + rpinfo[idx_r].target_power_6to24); + + rates->target_power_36 = + ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, + rpinfo[idx_r].freq, + rpinfo[idx_l].target_power_36, + rpinfo[idx_r].target_power_36); + + rates->target_power_48 = + ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, + rpinfo[idx_r].freq, + rpinfo[idx_l].target_power_48, + rpinfo[idx_r].target_power_48); + + rates->target_power_54 = + ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, + rpinfo[idx_r].freq, + rpinfo[idx_l].target_power_54, + rpinfo[idx_r].target_power_54); +} + +/* + * Get the max edge power for this channel if + * we have such data from EEPROM's Conformance Test + * Limits (CTL), and limit max power if needed. + * + * FIXME: Only works for world regulatory domains + */ +static void +ath5k_get_max_ctl_power(struct ath5k_hw *ah, + struct net80211_channel *channel) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + struct ath5k_edge_power *rep = ee->ee_ctl_pwr; + u8 *ctl_val = ee->ee_ctl; + s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; + s16 edge_pwr = 0; + u8 rep_idx; + u8 i, ctl_mode; + u8 ctl_idx = 0xFF; + u32 target = channel->center_freq; + + /* Find out a CTL for our mode that's not mapped + * on a specific reg domain. + * + * TODO: Map our current reg domain to one of the 3 available + * reg domain ids so that we can support more CTLs. */ + switch (channel->hw_value & CHANNEL_MODES) { + case CHANNEL_A: + ctl_mode = AR5K_CTL_11A | AR5K_CTL_NO_REGDOMAIN; + break; + case CHANNEL_G: + ctl_mode = AR5K_CTL_11G | AR5K_CTL_NO_REGDOMAIN; + break; + case CHANNEL_B: + ctl_mode = AR5K_CTL_11B | AR5K_CTL_NO_REGDOMAIN; + break; + case CHANNEL_T: + ctl_mode = AR5K_CTL_TURBO | AR5K_CTL_NO_REGDOMAIN; + break; + case CHANNEL_TG: + ctl_mode = AR5K_CTL_TURBOG | AR5K_CTL_NO_REGDOMAIN; + break; + case CHANNEL_XR: + /* Fall through */ + default: + return; + } + + for (i = 0; i < ee->ee_ctls; i++) { + if (ctl_val[i] == ctl_mode) { + ctl_idx = i; + break; + } + } + + /* If we have a CTL dataset available grab it and find the + * edge power for our frequency */ + if (ctl_idx == 0xFF) + return; + + /* Edge powers are sorted by frequency from lower + * to higher. Each CTL corresponds to 8 edge power + * measurements. */ + rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; + + /* Don't do boundaries check because we + * might have more that one bands defined + * for this mode */ + + /* Get the edge power that's closer to our + * frequency */ + for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { + rep_idx += i; + if (target <= rep[rep_idx].freq) + edge_pwr = (s16) rep[rep_idx].edge; + } + + if (edge_pwr) { + ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr); + } +} + + +/* + * Power to PCDAC table functions + */ + +/* + * Fill Power to PCDAC table on RF5111 + * + * No further processing is needed for RF5111, the only thing we have to + * do is fill the values below and above calibration range since eeprom data + * may not cover the entire PCDAC table. + */ +static void +ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, + s16 *table_max) +{ + u8 *pcdac_out = ah->ah_txpower.txp_pd_table; + u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; + u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; + s16 min_pwr, max_pwr; + + /* Get table boundaries */ + min_pwr = table_min[0]; + pcdac_0 = pcdac_tmp[0]; + + max_pwr = table_max[0]; + pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; + + /* Extrapolate below minimum using pcdac_0 */ + pcdac_i = 0; + for (i = 0; i < min_pwr; i++) + pcdac_out[pcdac_i++] = pcdac_0; + + /* Copy values from pcdac_tmp */ + pwr_idx = min_pwr; + for (i = 0 ; pwr_idx <= max_pwr && + pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { + pcdac_out[pcdac_i++] = pcdac_tmp[i]; + pwr_idx++; + } + + /* Extrapolate above maximum */ + while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) + pcdac_out[pcdac_i++] = pcdac_n; + +} + +/* + * Combine available XPD Curves and fill Linear Power to PCDAC table + * on RF5112 + * + * RFX112 can have up to 2 curves (one for low txpower range and one for + * higher txpower range). We need to put them both on pcdac_out and place + * them in the correct location. In case we only have one curve available + * just fit it on pcdac_out (it's supposed to cover the entire range of + * available pwr levels since it's always the higher power curve). Extrapolate + * below and above final table if needed. + */ +static void +ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, + s16 *table_max, u8 pdcurves) +{ + u8 *pcdac_out = ah->ah_txpower.txp_pd_table; + u8 *pcdac_low_pwr; + u8 *pcdac_high_pwr; + u8 *pcdac_tmp; + u8 pwr; + s16 max_pwr_idx; + s16 min_pwr_idx; + s16 mid_pwr_idx = 0; + /* Edge flag turs on the 7nth bit on the PCDAC + * to delcare the higher power curve (force values + * to be greater than 64). If we only have one curve + * we don't need to set this, if we have 2 curves and + * fill the table backwards this can also be used to + * switch from higher power curve to lower power curve */ + u8 edge_flag; + int i; + + /* When we have only one curve available + * that's the higher power curve. If we have + * two curves the first is the high power curve + * and the next is the low power curve. */ + if (pdcurves > 1) { + pcdac_low_pwr = ah->ah_txpower.tmpL[1]; + pcdac_high_pwr = ah->ah_txpower.tmpL[0]; + mid_pwr_idx = table_max[1] - table_min[1] - 1; + max_pwr_idx = (table_max[0] - table_min[0]) / 2; + + /* If table size goes beyond 31.5dB, keep the + * upper 31.5dB range when setting tx power. + * Note: 126 = 31.5 dB in quarter dB steps */ + if (table_max[0] - table_min[1] > 126) + min_pwr_idx = table_max[0] - 126; + else + min_pwr_idx = table_min[1]; + + /* Since we fill table backwards + * start from high power curve */ + pcdac_tmp = pcdac_high_pwr; + + edge_flag = 0x40; + } else { + pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ + pcdac_high_pwr = ah->ah_txpower.tmpL[0]; + min_pwr_idx = table_min[0]; + max_pwr_idx = (table_max[0] - table_min[0]) / 2; + pcdac_tmp = pcdac_high_pwr; + edge_flag = 0; + } + + /* This is used when setting tx power*/ + ah->ah_txpower.txp_min_idx = min_pwr_idx/2; + + /* Fill Power to PCDAC table backwards */ + pwr = max_pwr_idx; + for (i = 63; i >= 0; i--) { + /* Entering lower power range, reset + * edge flag and set pcdac_tmp to lower + * power curve.*/ + if (edge_flag == 0x40 && + (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { + edge_flag = 0x00; + pcdac_tmp = pcdac_low_pwr; + pwr = mid_pwr_idx/2; + } + + /* Don't go below 1, extrapolate below if we have + * already swithced to the lower power curve -or + * we only have one curve and edge_flag is zero + * anyway */ + if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { + while (i >= 0) { + pcdac_out[i] = pcdac_out[i + 1]; + i--; + } + break; + } + + pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; + + /* Extrapolate above if pcdac is greater than + * 126 -this can happen because we OR pcdac_out + * value with edge_flag on high power curve */ + if (pcdac_out[i] > 126) + pcdac_out[i] = 126; + + /* Decrease by a 0.5dB step */ + pwr--; + } +} + +/* Write PCDAC values on hw */ +static void +ath5k_setup_pcdac_table(struct ath5k_hw *ah) +{ + u8 *pcdac_out = ah->ah_txpower.txp_pd_table; + int i; + + /* + * Write TX power values + */ + for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { + ath5k_hw_reg_write(ah, + (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) | + (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16), + AR5K_PHY_PCDAC_TXPOWER(i)); + } +} + + +/* + * Power to PDADC table functions + */ + +/* + * Set the gain boundaries and create final Power to PDADC table + * + * We can have up to 4 pd curves, we need to do a simmilar process + * as we do for RF5112. This time we don't have an edge_flag but we + * set the gain boundaries on a separate register. + */ +static void +ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, + s16 *pwr_min, s16 *pwr_max, u8 pdcurves) +{ + u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; + u8 *pdadc_out = ah->ah_txpower.txp_pd_table; + u8 *pdadc_tmp; + s16 pdadc_0; + u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; + u8 pd_gain_overlap; + + /* Note: Register value is initialized on initvals + * there is no feedback from hw. + * XXX: What about pd_gain_overlap from EEPROM ? */ + pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & + AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; + + /* Create final PDADC table */ + for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { + pdadc_tmp = ah->ah_txpower.tmpL[pdg]; + + if (pdg == pdcurves - 1) + /* 2 dB boundary stretch for last + * (higher power) curve */ + gain_boundaries[pdg] = pwr_max[pdg] + 4; + else + /* Set gain boundary in the middle + * between this curve and the next one */ + gain_boundaries[pdg] = + (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; + + /* Sanity check in case our 2 db stretch got out of + * range. */ + if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) + gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; + + /* For the first curve (lower power) + * start from 0 dB */ + if (pdg == 0) + pdadc_0 = 0; + else + /* For the other curves use the gain overlap */ + pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - + pd_gain_overlap; + + /* Force each power step to be at least 0.5 dB */ + if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) + pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; + else + pwr_step = 1; + + /* If pdadc_0 is negative, we need to extrapolate + * below this pdgain by a number of pwr_steps */ + while ((pdadc_0 < 0) && (pdadc_i < 128)) { + s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; + pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; + pdadc_0++; + } + + /* Set last pwr level, using gain boundaries */ + pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; + /* Limit it to be inside pwr range */ + table_size = pwr_max[pdg] - pwr_min[pdg]; + max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; + + /* Fill pdadc_out table */ + while (pdadc_0 < max_idx) + pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; + + /* Need to extrapolate above this pdgain? */ + if (pdadc_n <= max_idx) + continue; + + /* Force each power step to be at least 0.5 dB */ + if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) + pwr_step = pdadc_tmp[table_size - 1] - + pdadc_tmp[table_size - 2]; + else + pwr_step = 1; + + /* Extrapolate above */ + while ((pdadc_0 < (s16) pdadc_n) && + (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { + s16 tmp = pdadc_tmp[table_size - 1] + + (pdadc_0 - max_idx) * pwr_step; + pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; + pdadc_0++; + } + } + + while (pdg < AR5K_EEPROM_N_PD_GAINS) { + gain_boundaries[pdg] = gain_boundaries[pdg - 1]; + pdg++; + } + + while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { + pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; + pdadc_i++; + } + + /* Set gain boundaries */ + ath5k_hw_reg_write(ah, + AR5K_REG_SM(pd_gain_overlap, + AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | + AR5K_REG_SM(gain_boundaries[0], + AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | + AR5K_REG_SM(gain_boundaries[1], + AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | + AR5K_REG_SM(gain_boundaries[2], + AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | + AR5K_REG_SM(gain_boundaries[3], + AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), + AR5K_PHY_TPC_RG5); + + /* Used for setting rate power table */ + ah->ah_txpower.txp_min_idx = pwr_min[0]; + +} + +/* Write PDADC values on hw */ +static void +ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, + u8 pdcurves, u8 *pdg_to_idx) +{ + u8 *pdadc_out = ah->ah_txpower.txp_pd_table; + u32 reg; + u8 i; + + /* Select the right pdgain curves */ + + /* Clear current settings */ + reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); + reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | + AR5K_PHY_TPC_RG1_PDGAIN_2 | + AR5K_PHY_TPC_RG1_PDGAIN_3 | + AR5K_PHY_TPC_RG1_NUM_PD_GAIN); + + /* + * Use pd_gains curve from eeprom + * + * This overrides the default setting from initvals + * in case some vendors (e.g. Zcomax) don't use the default + * curves. If we don't honor their settings we 'll get a + * 5dB (1 * gain overlap ?) drop. + */ + reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); + + switch (pdcurves) { + case 3: + reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); + /* Fall through */ + case 2: + reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); + /* Fall through */ + case 1: + reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); + break; + } + ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); + + /* + * Write TX power values + */ + for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { + ath5k_hw_reg_write(ah, + ((pdadc_out[4*i + 0] & 0xff) << 0) | + ((pdadc_out[4*i + 1] & 0xff) << 8) | + ((pdadc_out[4*i + 2] & 0xff) << 16) | + ((pdadc_out[4*i + 3] & 0xff) << 24), + AR5K_PHY_PDADC_TXPOWER(i)); + } +} + + +/* + * Common code for PCDAC/PDADC tables + */ + +/* + * This is the main function that uses all of the above + * to set PCDAC/PDADC table on hw for the current channel. + * This table is used for tx power calibration on the basband, + * without it we get weird tx power levels and in some cases + * distorted spectral mask + */ +static int +ath5k_setup_channel_powertable(struct ath5k_hw *ah, + struct net80211_channel *channel, + u8 ee_mode, u8 type) +{ + struct ath5k_pdgain_info *pdg_L, *pdg_R; + struct ath5k_chan_pcal_info *pcinfo_L; + struct ath5k_chan_pcal_info *pcinfo_R; + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; + s16 table_min[AR5K_EEPROM_N_PD_GAINS]; + s16 table_max[AR5K_EEPROM_N_PD_GAINS]; + u8 *tmpL; + u8 *tmpR; + u32 target = channel->center_freq; + int pdg, i; + + /* Get surounding freq piers for this channel */ + ath5k_get_chan_pcal_surrounding_piers(ah, channel, + &pcinfo_L, + &pcinfo_R); + + /* Loop over pd gain curves on + * surounding freq piers by index */ + for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { + + /* Fill curves in reverse order + * from lower power (max gain) + * to higher power. Use curve -> idx + * backmaping we did on eeprom init */ + u8 idx = pdg_curve_to_idx[pdg]; + + /* Grab the needed curves by index */ + pdg_L = &pcinfo_L->pd_curves[idx]; + pdg_R = &pcinfo_R->pd_curves[idx]; + + /* Initialize the temp tables */ + tmpL = ah->ah_txpower.tmpL[pdg]; + tmpR = ah->ah_txpower.tmpR[pdg]; + + /* Set curve's x boundaries and create + * curves so that they cover the same + * range (if we don't do that one table + * will have values on some range and the + * other one won't have any so interpolation + * will fail) */ + table_min[pdg] = min(pdg_L->pd_pwr[0], + pdg_R->pd_pwr[0]) / 2; + + table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], + pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; + + /* Now create the curves on surrounding channels + * and interpolate if needed to get the final + * curve for this gain on this channel */ + switch (type) { + case AR5K_PWRTABLE_LINEAR_PCDAC: + /* Override min/max so that we don't loose + * accuracy (don't divide by 2) */ + table_min[pdg] = min(pdg_L->pd_pwr[0], + pdg_R->pd_pwr[0]); + + table_max[pdg] = + max(pdg_L->pd_pwr[pdg_L->pd_points - 1], + pdg_R->pd_pwr[pdg_R->pd_points - 1]); + + /* Override minimum so that we don't get + * out of bounds while extrapolating + * below. Don't do this when we have 2 + * curves and we are on the high power curve + * because table_min is ok in this case */ + if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { + + table_min[pdg] = + ath5k_get_linear_pcdac_min(pdg_L->pd_step, + pdg_R->pd_step, + pdg_L->pd_pwr, + pdg_R->pd_pwr); + + /* Don't go too low because we will + * miss the upper part of the curve. + * Note: 126 = 31.5dB (max power supported) + * in 0.25dB units */ + if (table_max[pdg] - table_min[pdg] > 126) + table_min[pdg] = table_max[pdg] - 126; + } + + /* Fall through */ + case AR5K_PWRTABLE_PWR_TO_PCDAC: + case AR5K_PWRTABLE_PWR_TO_PDADC: + + ath5k_create_power_curve(table_min[pdg], + table_max[pdg], + pdg_L->pd_pwr, + pdg_L->pd_step, + pdg_L->pd_points, tmpL, type); + + /* We are in a calibration + * pier, no need to interpolate + * between freq piers */ + if (pcinfo_L == pcinfo_R) + continue; + + ath5k_create_power_curve(table_min[pdg], + table_max[pdg], + pdg_R->pd_pwr, + pdg_R->pd_step, + pdg_R->pd_points, tmpR, type); + break; + default: + return -EINVAL; + } + + /* Interpolate between curves + * of surounding freq piers to + * get the final curve for this + * pd gain. Re-use tmpL for interpolation + * output */ + for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && + (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { + tmpL[i] = (u8) ath5k_get_interpolated_value(target, + (s16) pcinfo_L->freq, + (s16) pcinfo_R->freq, + (s16) tmpL[i], + (s16) tmpR[i]); + } + } + + /* Now we have a set of curves for this + * channel on tmpL (x range is table_max - table_min + * and y values are tmpL[pdg][]) sorted in the same + * order as EEPROM (because we've used the backmaping). + * So for RF5112 it's from higher power to lower power + * and for RF2413 it's from lower power to higher power. + * For RF5111 we only have one curve. */ + + /* Fill min and max power levels for this + * channel by interpolating the values on + * surounding channels to complete the dataset */ + ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, + (s16) pcinfo_L->freq, + (s16) pcinfo_R->freq, + pcinfo_L->min_pwr, pcinfo_R->min_pwr); + + ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, + (s16) pcinfo_L->freq, + (s16) pcinfo_R->freq, + pcinfo_L->max_pwr, pcinfo_R->max_pwr); + + /* We are ready to go, fill PCDAC/PDADC + * table and write settings on hardware */ + switch (type) { + case AR5K_PWRTABLE_LINEAR_PCDAC: + /* For RF5112 we can have one or two curves + * and each curve covers a certain power lvl + * range so we need to do some more processing */ + ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, + ee->ee_pd_gains[ee_mode]); + + /* Set txp.offset so that we can + * match max power value with max + * table index */ + ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); + + /* Write settings on hw */ + ath5k_setup_pcdac_table(ah); + break; + case AR5K_PWRTABLE_PWR_TO_PCDAC: + /* We are done for RF5111 since it has only + * one curve, just fit the curve on the table */ + ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); + + /* No rate powertable adjustment for RF5111 */ + ah->ah_txpower.txp_min_idx = 0; + ah->ah_txpower.txp_offset = 0; + + /* Write settings on hw */ + ath5k_setup_pcdac_table(ah); + break; + case AR5K_PWRTABLE_PWR_TO_PDADC: + /* Set PDADC boundaries and fill + * final PDADC table */ + ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, + ee->ee_pd_gains[ee_mode]); + + /* Write settings on hw */ + ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx); + + /* Set txp.offset, note that table_min + * can be negative */ + ah->ah_txpower.txp_offset = table_min[0]; + break; + default: + return -EINVAL; + } + + return 0; +} + + +/* + * Per-rate tx power setting + * + * This is the code that sets the desired tx power (below + * maximum) on hw for each rate (we also have TPC that sets + * power per packet). We do that by providing an index on the + * PCDAC/PDADC table we set up. + */ + +/* + * Set rate power table + * + * For now we only limit txpower based on maximum tx power + * supported by hw (what's inside rate_info). We need to limit + * this even more, based on regulatory domain etc. + * + * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) + * and is indexed as follows: + * rates[0] - rates[7] -> OFDM rates + * rates[8] - rates[14] -> CCK rates + * rates[15] -> XR rates (they all have the same power) + */ +static void +ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, + struct ath5k_rate_pcal_info *rate_info, + u8 ee_mode) +{ + unsigned int i; + u16 *rates; + + /* max_pwr is power level we got from driver/user in 0.5dB + * units, switch to 0.25dB units so we can compare */ + max_pwr *= 2; + max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; + + /* apply rate limits */ + rates = ah->ah_txpower.txp_rates_power_table; + + /* OFDM rates 6 to 24Mb/s */ + for (i = 0; i < 5; i++) + rates[i] = min(max_pwr, rate_info->target_power_6to24); + + /* Rest OFDM rates */ + rates[5] = min(rates[0], rate_info->target_power_36); + rates[6] = min(rates[0], rate_info->target_power_48); + rates[7] = min(rates[0], rate_info->target_power_54); + + /* CCK rates */ + /* 1L */ + rates[8] = min(rates[0], rate_info->target_power_6to24); + /* 2L */ + rates[9] = min(rates[0], rate_info->target_power_36); + /* 2S */ + rates[10] = min(rates[0], rate_info->target_power_36); + /* 5L */ + rates[11] = min(rates[0], rate_info->target_power_48); + /* 5S */ + rates[12] = min(rates[0], rate_info->target_power_48); + /* 11L */ + rates[13] = min(rates[0], rate_info->target_power_54); + /* 11S */ + rates[14] = min(rates[0], rate_info->target_power_54); + + /* XR rates */ + rates[15] = min(rates[0], rate_info->target_power_6to24); + + /* CCK rates have different peak to average ratio + * so we have to tweak their power so that gainf + * correction works ok. For this we use OFDM to + * CCK delta from eeprom */ + if ((ee_mode == AR5K_EEPROM_MODE_11G) && + (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) + for (i = 8; i <= 15; i++) + rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; + + ah->ah_txpower.txp_min_pwr = rates[7]; + ah->ah_txpower.txp_max_pwr = rates[0]; + ah->ah_txpower.txp_ofdm = rates[7]; +} + + +/* + * Set transmition power + */ +int +ath5k_hw_txpower(struct ath5k_hw *ah, struct net80211_channel *channel, + u8 ee_mode, u8 txpower) +{ + struct ath5k_rate_pcal_info rate_info; + u8 type; + int ret; + + if (txpower > AR5K_TUNE_MAX_TXPOWER) { + DBG("ath5k: invalid tx power %d\n", txpower); + return -EINVAL; + } + if (txpower == 0) + txpower = AR5K_TUNE_DEFAULT_TXPOWER; + + /* Reset TX power values */ + memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); + ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; + ah->ah_txpower.txp_min_pwr = 0; + ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER; + + /* Initialize TX power table */ + switch (ah->ah_radio) { + case AR5K_RF5111: + type = AR5K_PWRTABLE_PWR_TO_PCDAC; + break; + case AR5K_RF5112: + type = AR5K_PWRTABLE_LINEAR_PCDAC; + break; + case AR5K_RF2413: + case AR5K_RF5413: + case AR5K_RF2316: + case AR5K_RF2317: + case AR5K_RF2425: + type = AR5K_PWRTABLE_PWR_TO_PDADC; + break; + default: + return -EINVAL; + } + + /* FIXME: Only on channel/mode change */ + ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type); + if (ret) + return ret; + + /* Limit max power if we have a CTL available */ + ath5k_get_max_ctl_power(ah, channel); + + /* FIXME: Tx power limit for this regdomain + * XXX: Mac80211/CRDA will do that anyway ? */ + + /* FIXME: Antenna reduction stuff */ + + /* FIXME: Limit power on turbo modes */ + + /* FIXME: TPC scale reduction */ + + /* Get surounding channels for per-rate power table + * calibration */ + ath5k_get_rate_pcal_data(ah, channel, &rate_info); + + /* Setup rate power table */ + ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); + + /* Write rate power table on hw */ + ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | + AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | + AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); + + ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | + AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | + AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); + + ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | + AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | + AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); + + ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | + AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | + AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); + + /* FIXME: TPC support */ + if (ah->ah_txpower.txp_tpc) { + ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | + AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); + + ath5k_hw_reg_write(ah, + AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | + AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | + AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), + AR5K_TPC); + } else { + ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | + AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); + } + + return 0; +} + +int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 mode, u8 txpower) +{ + struct net80211_channel *channel = ah->ah_current_channel; + + DBG2("ath5k: changing txpower to %d\n", txpower); + + return ath5k_hw_txpower(ah, channel, mode, txpower); +} + +#undef _ATH5K_PHY diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_qcu.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_qcu.c new file mode 100644 index 0000000..a674b85 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_qcu.c @@ -0,0 +1,394 @@ +/* + * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> + * + * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +FILE_LICENCE ( MIT ); + +/********************************************\ +Queue Control Unit, DFS Control Unit Functions +\********************************************/ + +#include "ath5k.h" +#include "reg.h" +#include "base.h" + +/* + * Set properties for a transmit queue + */ +int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, + const struct ath5k_txq_info *queue_info) +{ + if (ah->ah_txq.tqi_type == AR5K_TX_QUEUE_INACTIVE) + return -EIO; + + memcpy(&ah->ah_txq, queue_info, sizeof(struct ath5k_txq_info)); + + /*XXX: Is this supported on 5210 ?*/ + if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && + ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || + (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || + queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) + ah->ah_txq.tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; + + return 0; +} + +/* + * Initialize a transmit queue + */ +int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, + struct ath5k_txq_info *queue_info) +{ + unsigned int queue; + int ret; + + /* We only use one queue */ + queue = 0; + + /* + * Setup internal queue structure + */ + memset(&ah->ah_txq, 0, sizeof(struct ath5k_txq_info)); + ah->ah_txq.tqi_type = queue_type; + + if (queue_info != NULL) { + queue_info->tqi_type = queue_type; + ret = ath5k_hw_set_tx_queueprops(ah, queue_info); + if (ret) + return ret; + } + + /* + * We use ah_txq_status to hold a temp value for + * the Secondary interrupt mask registers on 5211+ + * check out ath5k_hw_reset_tx_queue + */ + AR5K_Q_ENABLE_BITS(ah->ah_txq_status, 0); + + return 0; +} + +/* + * Set a transmit queue inactive + */ +void ath5k_hw_release_tx_queue(struct ath5k_hw *ah) +{ + /* This queue will be skipped in further operations */ + ah->ah_txq.tqi_type = AR5K_TX_QUEUE_INACTIVE; + /*For SIMR setup*/ + AR5K_Q_DISABLE_BITS(ah->ah_txq_status, 0); +} + +/* + * Set DFS properties for a transmit queue on DCU + */ +int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah) +{ + u32 cw_min, cw_max, retry_lg, retry_sh; + struct ath5k_txq_info *tq = &ah->ah_txq; + const int queue = 0; + + tq = &ah->ah_txq; + + if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) + return 0; + + if (ah->ah_version == AR5K_AR5210) { + /* Only handle data queues, others will be ignored */ + if (tq->tqi_type != AR5K_TX_QUEUE_DATA) + return 0; + + /* Set Slot time */ + ath5k_hw_reg_write(ah, ah->ah_turbo ? + AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME, + AR5K_SLOT_TIME); + /* Set ACK_CTS timeout */ + ath5k_hw_reg_write(ah, ah->ah_turbo ? + AR5K_INIT_ACK_CTS_TIMEOUT_TURBO : + AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME); + /* Set Transmit Latency */ + ath5k_hw_reg_write(ah, ah->ah_turbo ? + AR5K_INIT_TRANSMIT_LATENCY_TURBO : + AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210); + + /* Set IFS0 */ + if (ah->ah_turbo) { + ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO + + (ah->ah_aifs + tq->tqi_aifs) * + AR5K_INIT_SLOT_TIME_TURBO) << + AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO, + AR5K_IFS0); + } else { + ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS + + (ah->ah_aifs + tq->tqi_aifs) * + AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) | + AR5K_INIT_SIFS, AR5K_IFS0); + } + + /* Set IFS1 */ + ath5k_hw_reg_write(ah, ah->ah_turbo ? + AR5K_INIT_PROTO_TIME_CNTRL_TURBO : + AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1); + /* Set AR5K_PHY_SETTLING */ + ath5k_hw_reg_write(ah, ah->ah_turbo ? + (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) + | 0x38 : + (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) + | 0x1C, + AR5K_PHY_SETTLING); + /* Set Frame Control Register */ + ath5k_hw_reg_write(ah, ah->ah_turbo ? + (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE | + AR5K_PHY_TURBO_SHORT | 0x2020) : + (AR5K_PHY_FRAME_CTL_INI | 0x1020), + AR5K_PHY_FRAME_CTL_5210); + } + + /* + * Calculate cwmin/max by channel mode + */ + cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN; + cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX; + ah->ah_aifs = AR5K_TUNE_AIFS; + /*XR is only supported on 5212*/ + if (IS_CHAN_XR(ah->ah_current_channel) && + ah->ah_version == AR5K_AR5212) { + cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR; + cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR; + ah->ah_aifs = AR5K_TUNE_AIFS_XR; + /*B mode is not supported on 5210*/ + } else if (IS_CHAN_B(ah->ah_current_channel) && + ah->ah_version != AR5K_AR5210) { + cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B; + cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B; + ah->ah_aifs = AR5K_TUNE_AIFS_11B; + } + + cw_min = 1; + while (cw_min < ah->ah_cw_min) + cw_min = (cw_min << 1) | 1; + + cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) : + ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); + cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) : + ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); + + /* + * Calculate and set retry limits + */ + if (ah->ah_software_retry) { + /* XXX Need to test this */ + retry_lg = ah->ah_limit_tx_retries; + retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ? + AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg; + } else { + retry_lg = AR5K_INIT_LG_RETRY; + retry_sh = AR5K_INIT_SH_RETRY; + } + + /*No QCU/DCU [5210]*/ + if (ah->ah_version == AR5K_AR5210) { + ath5k_hw_reg_write(ah, + (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S) + | AR5K_REG_SM(AR5K_INIT_SLG_RETRY, + AR5K_NODCU_RETRY_LMT_SLG_RETRY) + | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, + AR5K_NODCU_RETRY_LMT_SSH_RETRY) + | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY) + | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY), + AR5K_NODCU_RETRY_LMT); + } else { + /*QCU/DCU [5211+]*/ + ath5k_hw_reg_write(ah, + AR5K_REG_SM(AR5K_INIT_SLG_RETRY, + AR5K_DCU_RETRY_LMT_SLG_RETRY) | + AR5K_REG_SM(AR5K_INIT_SSH_RETRY, + AR5K_DCU_RETRY_LMT_SSH_RETRY) | + AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) | + AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY), + AR5K_QUEUE_DFS_RETRY_LIMIT(queue)); + + /*===Rest is also for QCU/DCU only [5211+]===*/ + + /* + * Set initial content window (cw_min/cw_max) + * and arbitrated interframe space (aifs)... + */ + ath5k_hw_reg_write(ah, + AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) | + AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) | + AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs, + AR5K_DCU_LCL_IFS_AIFS), + AR5K_QUEUE_DFS_LOCAL_IFS(queue)); + + /* + * Set misc registers + */ + /* Enable DCU early termination for this queue */ + AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_DCU_EARLY); + + /* Enable DCU to wait for next fragment from QCU */ + AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), + AR5K_DCU_MISC_FRAG_WAIT); + + /* On Maui and Spirit use the global seqnum on DCU */ + if (ah->ah_mac_version < AR5K_SREV_AR5211) + AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), + AR5K_DCU_MISC_SEQNUM_CTL); + + if (tq->tqi_cbr_period) { + ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period, + AR5K_QCU_CBRCFG_INTVAL) | + AR5K_REG_SM(tq->tqi_cbr_overflow_limit, + AR5K_QCU_CBRCFG_ORN_THRES), + AR5K_QUEUE_CBRCFG(queue)); + AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_FRSHED_CBR); + if (tq->tqi_cbr_overflow_limit) + AR5K_REG_ENABLE_BITS(ah, + AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_CBR_THRES_ENABLE); + } + + if (tq->tqi_ready_time && + (tq->tqi_type != AR5K_TX_QUEUE_ID_CAB)) + ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time, + AR5K_QCU_RDYTIMECFG_INTVAL) | + AR5K_QCU_RDYTIMECFG_ENABLE, + AR5K_QUEUE_RDYTIMECFG(queue)); + + if (tq->tqi_burst_time) { + ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time, + AR5K_DCU_CHAN_TIME_DUR) | + AR5K_DCU_CHAN_TIME_ENABLE, + AR5K_QUEUE_DFS_CHANNEL_TIME(queue)); + + if (tq->tqi_flags + & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) + AR5K_REG_ENABLE_BITS(ah, + AR5K_QUEUE_MISC(queue), + AR5K_QCU_MISC_RDY_VEOL_POLICY); + } + + if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) + ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS, + AR5K_QUEUE_DFS_MISC(queue)); + + if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) + ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG, + AR5K_QUEUE_DFS_MISC(queue)); + + /* TODO: Handle frame compression */ + + /* + * Enable interrupts for this tx queue + * in the secondary interrupt mask registers + */ + if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE) + AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue); + + if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE) + AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue); + + if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE) + AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue); + + if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE) + AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue); + + if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE) + AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue); + + if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRORNINT_ENABLE) + AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue); + + if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRURNINT_ENABLE) + AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue); + + if (tq->tqi_flags & AR5K_TXQ_FLAG_QTRIGINT_ENABLE) + AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue); + + if (tq->tqi_flags & AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE) + AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue); + + /* Update secondary interrupt mask registers */ + + /* Filter out inactive queues */ + ah->ah_txq_imr_txok &= ah->ah_txq_status; + ah->ah_txq_imr_txerr &= ah->ah_txq_status; + ah->ah_txq_imr_txurn &= ah->ah_txq_status; + ah->ah_txq_imr_txdesc &= ah->ah_txq_status; + ah->ah_txq_imr_txeol &= ah->ah_txq_status; + ah->ah_txq_imr_cbrorn &= ah->ah_txq_status; + ah->ah_txq_imr_cbrurn &= ah->ah_txq_status; + ah->ah_txq_imr_qtrig &= ah->ah_txq_status; + ah->ah_txq_imr_nofrm &= ah->ah_txq_status; + + ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok, + AR5K_SIMR0_QCU_TXOK) | + AR5K_REG_SM(ah->ah_txq_imr_txdesc, + AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0); + ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr, + AR5K_SIMR1_QCU_TXERR) | + AR5K_REG_SM(ah->ah_txq_imr_txeol, + AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1); + /* Update simr2 but don't overwrite rest simr2 settings */ + AR5K_REG_DISABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN); + AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2, + AR5K_REG_SM(ah->ah_txq_imr_txurn, + AR5K_SIMR2_QCU_TXURN)); + ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn, + AR5K_SIMR3_QCBRORN) | + AR5K_REG_SM(ah->ah_txq_imr_cbrurn, + AR5K_SIMR3_QCBRURN), AR5K_SIMR3); + ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig, + AR5K_SIMR4_QTRIG), AR5K_SIMR4); + /* Set TXNOFRM_QCU for the queues with TXNOFRM enabled */ + ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm, + AR5K_TXNOFRM_QCU), AR5K_TXNOFRM); + /* No queue has TXNOFRM enabled, disable the interrupt + * by setting AR5K_TXNOFRM to zero */ + if (ah->ah_txq_imr_nofrm == 0) + ath5k_hw_reg_write(ah, 0, AR5K_TXNOFRM); + + /* Set QCU mask for this DCU to save power */ + AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue); + } + + return 0; +} + +/* + * Set slot time on DCU + */ +int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time) +{ + if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) + return -EINVAL; + + if (ah->ah_version == AR5K_AR5210) + ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time, + ah->ah_turbo), AR5K_SLOT_TIME); + else + ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT); + + return 0; +} + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_reset.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_reset.c new file mode 100644 index 0000000..dc80093 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/ath5k_reset.c @@ -0,0 +1,1176 @@ +/* + * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> + * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> + * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> + * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> + * + * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +FILE_LICENCE ( MIT ); + +#define _ATH5K_RESET + +/*****************************\ + Reset functions and helpers +\*****************************/ + +#include <gpxe/pci.h> /* To determine if a card is pci-e */ +#include <unistd.h> + +#include "ath5k.h" +#include "reg.h" +#include "base.h" + +/* Find last set bit; fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32 */ +static int fls(int x) +{ + int r = 32; + + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; +} + + +/** + * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 + * + * @ah: the &struct ath5k_hw + * @channel: the currently set channel upon reset + * + * Write the delta slope coefficient (used on pilot tracking ?) for OFDM + * operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset(). + * + * Since delta slope is floating point we split it on its exponent and + * mantissa and provide these values on hw. + * + * For more infos i think this patent is related + * http://www.freepatentsonline.com/7184495.html + */ +static int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, + struct net80211_channel *channel) +{ + /* Get exponent and mantissa and set it */ + u32 coef_scaled, coef_exp, coef_man, + ds_coef_exp, ds_coef_man, clock; + + if (!(ah->ah_version == AR5K_AR5212) || + !(channel->hw_value & CHANNEL_OFDM)) { + DBG("ath5k: attempt to set OFDM timings on non-OFDM channel\n"); + return -EFAULT; + } + + /* Get coefficient + * ALGO: coef = (5 * clock * carrier_freq) / 2) + * we scale coef by shifting clock value by 24 for + * better precision since we use integers */ + /* TODO: Half/quarter rate */ + clock = ath5k_hw_htoclock(1, channel->hw_value & CHANNEL_TURBO); + + coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq; + + /* Get exponent + * ALGO: coef_exp = 14 - highest set bit position */ + coef_exp = fls(coef_scaled) - 1; + + /* Doesn't make sense if it's zero*/ + if (!coef_scaled || !coef_exp) + return -EINVAL; + + /* Note: we've shifted coef_scaled by 24 */ + coef_exp = 14 - (coef_exp - 24); + + + /* Get mantissa (significant digits) + * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */ + coef_man = coef_scaled + + (1 << (24 - coef_exp - 1)); + + /* Calculate delta slope coefficient exponent + * and mantissa (remove scaling) and set them on hw */ + ds_coef_man = coef_man >> (24 - coef_exp); + ds_coef_exp = coef_exp - 16; + + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, + AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, + AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); + + return 0; +} + + +/* + * index into rates for control rates, we can set it up like this because + * this is only used for AR5212 and we know it supports G mode + */ +static const unsigned int control_rates[] = + { 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 }; + +/** + * ath5k_hw_write_rate_duration - fill rate code to duration table + * + * @ah: the &struct ath5k_hw + * @mode: one of enum ath5k_driver_mode + * + * Write the rate code to duration table upon hw reset. This is a helper for + * ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on + * the hardware, based on current mode, for each rate. The rates which are + * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have + * different rate code so we write their value twice (one for long preample + * and one for short). + * + * Note: Band doesn't matter here, if we set the values for OFDM it works + * on both a and g modes. So all we have to do is set values for all g rates + * that include all OFDM and CCK rates. If we operate in turbo or xr/half/ + * quarter rate mode, we need to use another set of bitrates (that's why we + * need the mode parameter) but we don't handle these proprietary modes yet. + */ +static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah, + unsigned int mode __unused) +{ + struct ath5k_softc *sc = ah->ah_sc; + u16 rate; + int i; + + /* Write rate duration table */ + for (i = 0; i < sc->hwinfo->nr_rates[NET80211_BAND_2GHZ]; i++) { + u32 reg; + u16 tx_time; + + rate = sc->hwinfo->rates[NET80211_BAND_2GHZ][i]; + + /* Set ACK timeout */ + reg = AR5K_RATE_DUR(ath5k_bitrate_to_hw_rix(rate)); + + /* An ACK frame consists of 10 bytes. If you add the FCS, + * it's 14 bytes. Note we use the control rate and not the + * actual rate for this rate. See mac80211 tx.c + * ieee80211_duration() for a brief description of + * what rate we should choose to TX ACKs. */ + tx_time = net80211_duration(sc->dev, 14, rate); + + ath5k_hw_reg_write(ah, tx_time, reg); + + if (rate != 20 && rate != 55 && rate != 110) + continue; + + /* + * We're not distinguishing short preamble here, + * This is true, all we'll get is a longer value here + * which is not necessarilly bad. + */ + ath5k_hw_reg_write(ah, tx_time, + reg + (AR5K_SET_SHORT_PREAMBLE << 2)); + } +} + +/* + * Reset chipset + */ +static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val) +{ + int ret; + u32 mask = val ? val : ~0U; + + /* Read-and-clear RX Descriptor Pointer*/ + ath5k_hw_reg_read(ah, AR5K_RXDP); + + /* + * Reset the device and wait until success + */ + ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL); + + /* Wait at least 128 PCI clocks */ + udelay(15); + + if (ah->ah_version == AR5K_AR5210) { + val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA + | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY; + mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA + | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY; + } else { + val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; + mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; + } + + ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, 0); + + /* + * Reset configuration register (for hw byte-swap). Note that this + * is only set for big endian. We do the necessary magic in + * AR5K_INIT_CFG. + */ + if ((val & AR5K_RESET_CTL_PCU) == 0) + ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG); + + return ret; +} + +/* + * Sleep control + */ +int ath5k_hw_wake(struct ath5k_hw *ah) +{ + unsigned int i; + u32 staid, data; + + staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1); + staid &= ~AR5K_STA_ID1_PWR_SV; + + /* Preserve sleep duration */ + data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL); + if (data & 0xffc00000) + data = 0; + else + data = data & 0xfffcffff; + + ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL); + udelay(15); + + for (i = 50; i > 0; i--) { + /* Check if the chip did wake up */ + if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) & + AR5K_PCICFG_SPWR_DN) == 0) + break; + + /* Wait a bit and retry */ + udelay(200); + ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL); + } + + /* Fail if the chip didn't wake up */ + if (i <= 0) + return -EIO; + + ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1); + + return 0; +} + +/* + * Bring up MAC + PHY Chips and program PLL + * TODO: Half/Quarter rate support + */ +int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, int initial __unused) +{ + struct pci_device *pdev = ah->ah_sc->pdev; + u32 turbo, mode, clock, bus_flags; + int ret; + + turbo = 0; + mode = 0; + clock = 0; + + /* Wakeup the device */ + ret = ath5k_hw_wake(ah); + if (ret) { + DBG("ath5k: failed to wake up the MAC chip\n"); + return ret; + } + + if (ah->ah_version != AR5K_AR5210) { + /* + * Get channel mode flags + */ + + if (ah->ah_radio >= AR5K_RF5112) { + mode = AR5K_PHY_MODE_RAD_RF5112; + clock = AR5K_PHY_PLL_RF5112; + } else { + mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/ + clock = AR5K_PHY_PLL_RF5111; /*Zero*/ + } + + if (flags & CHANNEL_2GHZ) { + mode |= AR5K_PHY_MODE_FREQ_2GHZ; + clock |= AR5K_PHY_PLL_44MHZ; + + if (flags & CHANNEL_CCK) { + mode |= AR5K_PHY_MODE_MOD_CCK; + } else if (flags & CHANNEL_OFDM) { + /* XXX Dynamic OFDM/CCK is not supported by the + * AR5211 so we set MOD_OFDM for plain g (no + * CCK headers) operation. We need to test + * this, 5211 might support ofdm-only g after + * all, there are also initial register values + * in the code for g mode (see initvals.c). */ + if (ah->ah_version == AR5K_AR5211) + mode |= AR5K_PHY_MODE_MOD_OFDM; + else + mode |= AR5K_PHY_MODE_MOD_DYN; + } else { + DBG("ath5k: invalid radio modulation mode\n"); + return -EINVAL; + } + } else if (flags & CHANNEL_5GHZ) { + mode |= AR5K_PHY_MODE_FREQ_5GHZ; + + if (ah->ah_radio == AR5K_RF5413) + clock = AR5K_PHY_PLL_40MHZ_5413; + else + clock |= AR5K_PHY_PLL_40MHZ; + + if (flags & CHANNEL_OFDM) + mode |= AR5K_PHY_MODE_MOD_OFDM; + else { + DBG("ath5k: invalid radio modulation mode\n"); + return -EINVAL; + } + } else { + DBG("ath5k: invalid radio frequency mode\n"); + return -EINVAL; + } + + if (flags & CHANNEL_TURBO) + turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT; + } else { /* Reset the device */ + + /* ...enable Atheros turbo mode if requested */ + if (flags & CHANNEL_TURBO) + ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE, + AR5K_PHY_TURBO); + } + + /* reseting PCI on PCI-E cards results card to hang + * and always return 0xffff... so we ingore that flag + * for PCI-E cards */ + if (pci_find_capability(pdev, PCI_CAP_ID_EXP)) + bus_flags = 0; + else + bus_flags = AR5K_RESET_CTL_PCI; + + /* Reset chipset */ + if (ah->ah_version == AR5K_AR5210) { + ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | + AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA | + AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI); + mdelay(2); + } else { + ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | + AR5K_RESET_CTL_BASEBAND | bus_flags); + } + if (ret) { + DBG("ath5k: failed to reset the MAC chip\n"); + return -EIO; + } + + /* ...wakeup again!*/ + ret = ath5k_hw_wake(ah); + if (ret) { + DBG("ath5k: failed to resume the MAC chip\n"); + return ret; + } + + /* ...final warm reset */ + if (ath5k_hw_nic_reset(ah, 0)) { + DBG("ath5k: failed to warm reset the MAC chip\n"); + return -EIO; + } + + if (ah->ah_version != AR5K_AR5210) { + + /* ...update PLL if needed */ + if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) { + ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL); + udelay(300); + } + + /* ...set the PHY operating mode */ + ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE); + ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO); + } + + return 0; +} + +static int ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, + struct net80211_channel *channel) +{ + u8 refclk_freq; + + if ((ah->ah_radio == AR5K_RF5112) || + (ah->ah_radio == AR5K_RF5413) || + (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) + refclk_freq = 40; + else + refclk_freq = 32; + + if ((channel->center_freq % refclk_freq != 0) && + ((channel->center_freq % refclk_freq < 10) || + (channel->center_freq % refclk_freq > 22))) + return 1; + else + return 0; +} + +/* TODO: Half/Quarter rate */ +static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah, + struct net80211_channel *channel) +{ + if (ah->ah_version == AR5K_AR5212 && + ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { + + /* Setup ADC control */ + ath5k_hw_reg_write(ah, + (AR5K_REG_SM(2, + AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) | + AR5K_REG_SM(2, + AR5K_PHY_ADC_CTL_INBUFGAIN_ON) | + AR5K_PHY_ADC_CTL_PWD_DAC_OFF | + AR5K_PHY_ADC_CTL_PWD_ADC_OFF), + AR5K_PHY_ADC_CTL); + + + + /* Disable barker RSSI threshold */ + AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL, + AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR); + + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL, + AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2); + + /* Set the mute mask */ + ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK); + } + + /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */ + if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B) + ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH); + + /* Enable DCU double buffering */ + if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B) + AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, + AR5K_TXCFG_DCU_DBL_BUF_DIS); + + /* Set DAC/ADC delays */ + if (ah->ah_version == AR5K_AR5212) { + u32 scal; + if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)) + scal = AR5K_PHY_SCAL_32MHZ_2417; + else if (ath5k_eeprom_is_hb63(ah)) + scal = AR5K_PHY_SCAL_32MHZ_HB63; + else + scal = AR5K_PHY_SCAL_32MHZ; + ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL); + } + + /* Set fast ADC */ + if ((ah->ah_radio == AR5K_RF5413) || + (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) { + u32 fast_adc = 1; + + if (channel->center_freq == 2462 || + channel->center_freq == 2467) + fast_adc = 0; + + /* Only update if needed */ + if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc) + ath5k_hw_reg_write(ah, fast_adc, + AR5K_PHY_FAST_ADC); + } + + /* Fix for first revision of the RF5112 RF chipset */ + if (ah->ah_radio == AR5K_RF5112 && + ah->ah_radio_5ghz_revision < + AR5K_SREV_RAD_5112A) { + u32 data; + ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD, + AR5K_PHY_CCKTXCTL); + if (channel->hw_value & CHANNEL_5GHZ) + data = 0xffb81020; + else + data = 0xffb80d20; + ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL); + } + + if (ah->ah_mac_srev < AR5K_SREV_AR5211) { + u32 usec_reg; + /* 5311 has different tx/rx latency masks + * from 5211, since we deal 5311 the same + * as 5211 when setting initvals, shift + * values here to their proper locations */ + usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211); + ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 | + AR5K_USEC_32 | + AR5K_USEC_TX_LATENCY_5211 | + AR5K_REG_SM(29, + AR5K_USEC_RX_LATENCY_5210)), + AR5K_USEC_5211); + /* Clear QCU/DCU clock gating register */ + ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT); + /* Set DAC/ADC delays */ + ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL); + /* Enable PCU FIFO corruption ECO */ + AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211, + AR5K_DIAG_SW_ECO_ENABLE); + } +} + +static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah, + struct net80211_channel *channel, u8 *ant, u8 ee_mode) +{ + struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; + s16 cck_ofdm_pwr_delta; + + /* Adjust power delta for channel 14 */ + if (channel->center_freq == 2484) + cck_ofdm_pwr_delta = + ((ee->ee_cck_ofdm_power_delta - + ee->ee_scaled_cck_delta) * 2) / 10; + else + cck_ofdm_pwr_delta = + (ee->ee_cck_ofdm_power_delta * 2) / 10; + + /* Set CCK to OFDM power delta on tx power + * adjustment register */ + if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { + if (channel->hw_value == CHANNEL_G) + ath5k_hw_reg_write(ah, + AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1), + AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) | + AR5K_REG_SM((cck_ofdm_pwr_delta * -1), + AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX), + AR5K_PHY_TX_PWR_ADJ); + else + ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ); + } else { + /* For older revs we scale power on sw during tx power + * setup */ + ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta; + ah->ah_txpower.txp_cck_ofdm_gainf_delta = + ee->ee_cck_ofdm_gain_delta; + } + + /* Set antenna idle switch table */ + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, + AR5K_PHY_ANT_CTL_SWTABLE_IDLE, + (ah->ah_antenna[ee_mode][0] | + AR5K_PHY_ANT_CTL_TXRX_EN)); + + /* Set antenna switch table */ + ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[0]], + AR5K_PHY_ANT_SWITCH_TABLE_0); + ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[1]], + AR5K_PHY_ANT_SWITCH_TABLE_1); + + /* Noise floor threshold */ + ath5k_hw_reg_write(ah, + AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]), + AR5K_PHY_NFTHRES); + + if ((channel->hw_value & CHANNEL_TURBO) && + (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) { + /* Switch settling time (Turbo) */ + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING, + AR5K_PHY_SETTLING_SWITCH, + ee->ee_switch_settling_turbo[ee_mode]); + + /* Tx/Rx attenuation (Turbo) */ + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN, + AR5K_PHY_GAIN_TXRX_ATTEN, + ee->ee_atn_tx_rx_turbo[ee_mode]); + + /* ADC/PGA desired size (Turbo) */ + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, + AR5K_PHY_DESIRED_SIZE_ADC, + ee->ee_adc_desired_size_turbo[ee_mode]); + + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, + AR5K_PHY_DESIRED_SIZE_PGA, + ee->ee_pga_desired_size_turbo[ee_mode]); + + /* Tx/Rx margin (Turbo) */ + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ, + AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, + ee->ee_margin_tx_rx_turbo[ee_mode]); + + } else { + /* Switch settling time */ + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING, + AR5K_PHY_SETTLING_SWITCH, + ee->ee_switch_settling[ee_mode]); + + /* Tx/Rx attenuation */ + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN, + AR5K_PHY_GAIN_TXRX_ATTEN, + ee->ee_atn_tx_rx[ee_mode]); + + /* ADC/PGA desired size */ + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, + AR5K_PHY_DESIRED_SIZE_ADC, + ee->ee_adc_desired_size[ee_mode]); + + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, + AR5K_PHY_DESIRED_SIZE_PGA, + ee->ee_pga_desired_size[ee_mode]); + + /* Tx/Rx margin */ + if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ, + AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, + ee->ee_margin_tx_rx[ee_mode]); + } + + /* XPA delays */ + ath5k_hw_reg_write(ah, + (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | + (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | + (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | + (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4); + + /* XLNA delay */ + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3, + AR5K_PHY_RF_CTL3_TXE2XLNA_ON, + ee->ee_tx_end2xlna_enable[ee_mode]); + + /* Thresh64 (ANI) */ + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF, + AR5K_PHY_NF_THRESH62, + ee->ee_thr_62[ee_mode]); + + + /* False detect backoff for channels + * that have spur noise. Write the new + * cyclic power RSSI threshold. */ + if (ath5k_hw_chan_has_spur_noise(ah, channel)) + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR, + AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, + AR5K_INIT_CYCRSSI_THR1 + + ee->ee_false_detect[ee_mode]); + else + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR, + AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, + AR5K_INIT_CYCRSSI_THR1); + + /* I/Q correction + * TODO: Per channel i/q infos ? */ + AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, + AR5K_PHY_IQ_CORR_ENABLE | + (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) | + ee->ee_q_cal[ee_mode]); + + /* Heavy clipping -disable for now */ + if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1) + ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE); + + return; +} + +/* + * Main reset function + */ +int ath5k_hw_reset(struct ath5k_hw *ah, + struct net80211_channel *channel, int change_channel) +{ + u32 s_seq[10], s_ant, s_led[3], staid1_flags, tsf_up, tsf_lo; + u32 phy_tst1; + u8 mode, freq, ee_mode, ant[2]; + int i, ret; + + s_ant = 0; + ee_mode = 0; + staid1_flags = 0; + tsf_up = 0; + tsf_lo = 0; + freq = 0; + mode = 0; + + /* + * Save some registers before a reset + */ + /*DCU/Antenna selection not available on 5210*/ + if (ah->ah_version != AR5K_AR5210) { + + switch (channel->hw_value & CHANNEL_MODES) { + case CHANNEL_A: + mode = AR5K_MODE_11A; + freq = AR5K_INI_RFGAIN_5GHZ; + ee_mode = AR5K_EEPROM_MODE_11A; + break; + case CHANNEL_G: + mode = AR5K_MODE_11G; + freq = AR5K_INI_RFGAIN_2GHZ; + ee_mode = AR5K_EEPROM_MODE_11G; + break; + case CHANNEL_B: + mode = AR5K_MODE_11B; + freq = AR5K_INI_RFGAIN_2GHZ; + ee_mode = AR5K_EEPROM_MODE_11B; + break; + case CHANNEL_T: + mode = AR5K_MODE_11A_TURBO; + freq = AR5K_INI_RFGAIN_5GHZ; + ee_mode = AR5K_EEPROM_MODE_11A; + break; + case CHANNEL_TG: + if (ah->ah_version == AR5K_AR5211) { + DBG("ath5k: TurboG not available on 5211\n"); + return -EINVAL; + } + mode = AR5K_MODE_11G_TURBO; + freq = AR5K_INI_RFGAIN_2GHZ; + ee_mode = AR5K_EEPROM_MODE_11G; + break; + case CHANNEL_XR: + if (ah->ah_version == AR5K_AR5211) { + DBG("ath5k: XR mode not available on 5211\n"); + return -EINVAL; + } + mode = AR5K_MODE_XR; + freq = AR5K_INI_RFGAIN_5GHZ; + ee_mode = AR5K_EEPROM_MODE_11A; + break; + default: + DBG("ath5k: invalid channel (%d MHz)\n", + channel->center_freq); + return -EINVAL; + } + + if (change_channel) { + /* + * Save frame sequence count + * For revs. after Oahu, only save + * seq num for DCU 0 (Global seq num) + */ + if (ah->ah_mac_srev < AR5K_SREV_AR5211) { + + for (i = 0; i < 10; i++) + s_seq[i] = ath5k_hw_reg_read(ah, + AR5K_QUEUE_DCU_SEQNUM(i)); + + } else { + s_seq[0] = ath5k_hw_reg_read(ah, + AR5K_QUEUE_DCU_SEQNUM(0)); + } + } + + /* Save default antenna */ + s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA); + + if (ah->ah_version == AR5K_AR5212) { + /* Since we are going to write rf buffer + * check if we have any pending gain_F + * optimization settings */ + if (change_channel && ah->ah_rf_banks != NULL) + ath5k_hw_gainf_calibrate(ah); + } + } + + /*GPIOs*/ + s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & + AR5K_PCICFG_LEDSTATE; + s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR); + s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO); + + /* AR5K_STA_ID1 flags, only preserve antenna + * settings and ack/cts rate mode */ + staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & + (AR5K_STA_ID1_DEFAULT_ANTENNA | + AR5K_STA_ID1_DESC_ANTENNA | + AR5K_STA_ID1_RTS_DEF_ANTENNA | + AR5K_STA_ID1_ACKCTS_6MB | + AR5K_STA_ID1_BASE_RATE_11B | + AR5K_STA_ID1_SELFGEN_DEF_ANT); + + /* Wakeup the device */ + ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, 0); + if (ret) + return ret; + + /* PHY access enable */ + if (ah->ah_mac_srev >= AR5K_SREV_AR5211) + ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); + else + ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40, + AR5K_PHY(0)); + + /* Write initial settings */ + ret = ath5k_hw_write_initvals(ah, mode, change_channel); + if (ret) + return ret; + + /* + * 5211/5212 Specific + */ + if (ah->ah_version != AR5K_AR5210) { + + /* + * Write initial RF gain settings + * This should work for both 5111/5112 + */ + ret = ath5k_hw_rfgain_init(ah, freq); + if (ret) + return ret; + + mdelay(1); + + /* + * Tweak initval settings for revised + * chipsets and add some more config + * bits + */ + ath5k_hw_tweak_initval_settings(ah, channel); + + /* + * Set TX power (FIXME) + */ + ret = ath5k_hw_txpower(ah, channel, ee_mode, + AR5K_TUNE_DEFAULT_TXPOWER); + if (ret) + return ret; + + /* Write rate duration table only on AR5212 */ + if (ah->ah_version == AR5K_AR5212) + ath5k_hw_write_rate_duration(ah, mode); + + /* + * Write RF buffer + */ + ret = ath5k_hw_rfregs_init(ah, channel, mode); + if (ret) + return ret; + + + /* Write OFDM timings on 5212*/ + if (ah->ah_version == AR5K_AR5212 && + channel->hw_value & CHANNEL_OFDM) { + ret = ath5k_hw_write_ofdm_timings(ah, channel); + if (ret) + return ret; + } + + /*Enable/disable 802.11b mode on 5111 + (enable 2111 frequency converter + CCK)*/ + if (ah->ah_radio == AR5K_RF5111) { + if (mode == AR5K_MODE_11B) + AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, + AR5K_TXCFG_B_MODE); + else + AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, + AR5K_TXCFG_B_MODE); + } + + /* + * In case a fixed antenna was set as default + * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE + * registers. + */ + if (s_ant != 0) { + if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */ + ant[0] = ant[1] = AR5K_ANT_FIXED_A; + else /* 2 - Aux */ + ant[0] = ant[1] = AR5K_ANT_FIXED_B; + } else { + ant[0] = AR5K_ANT_FIXED_A; + ant[1] = AR5K_ANT_FIXED_B; + } + + /* Commit values from EEPROM */ + ath5k_hw_commit_eeprom_settings(ah, channel, ant, ee_mode); + + } else { + /* + * For 5210 we do all initialization using + * initvals, so we don't have to modify + * any settings (5210 also only supports + * a/aturbo modes) + */ + mdelay(1); + /* Disable phy and wait */ + ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); + mdelay(1); + } + + /* + * Restore saved values + */ + + /*DCU/Antenna selection not available on 5210*/ + if (ah->ah_version != AR5K_AR5210) { + + if (change_channel) { + if (ah->ah_mac_srev < AR5K_SREV_AR5211) { + for (i = 0; i < 10; i++) + ath5k_hw_reg_write(ah, s_seq[i], + AR5K_QUEUE_DCU_SEQNUM(i)); + } else { + ath5k_hw_reg_write(ah, s_seq[0], + AR5K_QUEUE_DCU_SEQNUM(0)); + } + } + + ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA); + } + + /* Ledstate */ + AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]); + + /* Gpio settings */ + ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR); + ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO); + + /* Restore sta_id flags and preserve our mac address*/ + ath5k_hw_reg_write(ah, AR5K_LOW_ID(ah->ah_sta_id), + AR5K_STA_ID0); + ath5k_hw_reg_write(ah, staid1_flags | AR5K_HIGH_ID(ah->ah_sta_id), + AR5K_STA_ID1); + + + /* + * Configure PCU + */ + + /* Restore bssid and bssid mask */ + /* XXX: add ah->aid once mac80211 gives this to us */ + ath5k_hw_set_associd(ah, ah->ah_bssid, 0); + + /* Set PCU config */ + ath5k_hw_set_opmode(ah); + + /* Clear any pending interrupts + * PISR/SISR Not available on 5210 */ + if (ah->ah_version != AR5K_AR5210) + ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR); + + /* Set RSSI/BRSSI thresholds + * + * Note: If we decide to set this value + * dynamicaly, have in mind that when AR5K_RSSI_THR + * register is read it might return 0x40 if we haven't + * wrote anything to it plus BMISS RSSI threshold is zeroed. + * So doing a save/restore procedure here isn't the right + * choice. Instead store it on ath5k_hw */ + ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES | + AR5K_TUNE_BMISS_THRES << + AR5K_RSSI_THR_BMISS_S), + AR5K_RSSI_THR); + + /* MIC QoS support */ + if (ah->ah_mac_srev >= AR5K_SREV_AR2413) { + ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL); + ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL); + } + + /* QoS NOACK Policy */ + if (ah->ah_version == AR5K_AR5212) { + ath5k_hw_reg_write(ah, + AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) | + AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | + AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET), + AR5K_QOS_NOACK); + } + + + /* + * Configure PHY + */ + + /* Set channel on PHY */ + ret = ath5k_hw_channel(ah, channel); + if (ret) + return ret; + + /* + * Enable the PHY and wait until completion + * This includes BaseBand and Synthesizer + * activation. + */ + ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); + + /* + * On 5211+ read activation -> rx delay + * and use it. + * + * TODO: Half/quarter rate support + */ + if (ah->ah_version != AR5K_AR5210) { + u32 delay; + delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & + AR5K_PHY_RX_DELAY_M; + delay = (channel->hw_value & CHANNEL_CCK) ? + ((delay << 2) / 22) : (delay / 10); + + udelay(100 + (2 * delay)); + } else { + mdelay(1); + } + + /* + * Perform ADC test to see if baseband is ready + * Set tx hold and check adc test register + */ + phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); + ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); + for (i = 0; i <= 20; i++) { + if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) + break; + udelay(200); + } + ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); + + /* + * Start automatic gain control calibration + * + * During AGC calibration RX path is re-routed to + * a power detector so we don't receive anything. + * + * This method is used to calibrate some static offsets + * used together with on-the fly I/Q calibration (the + * one performed via ath5k_hw_phy_calibrate), that doesn't + * interrupt rx path. + * + * While rx path is re-routed to the power detector we also + * start a noise floor calibration, to measure the + * card's noise floor (the noise we measure when we are not + * transmiting or receiving anything). + * + * If we are in a noisy environment AGC calibration may time + * out and/or noise floor calibration might timeout. + */ + AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_CAL); + + /* At the same time start I/Q calibration for QAM constellation + * -no need for CCK- */ + ah->ah_calibration = 0; + if (!(mode == AR5K_MODE_11B)) { + ah->ah_calibration = 1; + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, + AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); + AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, + AR5K_PHY_IQ_RUN); + } + + /* Wait for gain calibration to finish (we check for I/Q calibration + * during ath5k_phy_calibrate) */ + if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, + AR5K_PHY_AGCCTL_CAL, 0, 0)) { + DBG("ath5k: gain calibration timeout (%d MHz)\n", + channel->center_freq); + } + + /* + * If we run NF calibration before AGC, it always times out. + * Binary HAL starts NF and AGC calibration at the same time + * and only waits for AGC to finish. Also if AGC or NF cal. + * times out, reset doesn't fail on binary HAL. I believe + * that's wrong because since rx path is routed to a detector, + * if cal. doesn't finish we won't have RX. Sam's HAL for AR5210/5211 + * enables noise floor calibration after offset calibration and if noise + * floor calibration fails, reset fails. I believe that's + * a better approach, we just need to find a polling interval + * that suits best, even if reset continues we need to make + * sure that rx path is ready. + */ + ath5k_hw_noise_floor_calibration(ah, channel->center_freq); + + + /* + * Configure QCUs/DCUs + */ + + /* TODO: HW Compression support for data queues */ + /* TODO: Burst prefetch for data queues */ + + /* + * Reset queues and start beacon timers at the end of the reset routine + * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping + * Note: If we want we can assign multiple qcus on one dcu. + */ + ret = ath5k_hw_reset_tx_queue(ah); + if (ret) { + DBG("ath5k: failed to reset TX queue\n"); + return ret; + } + + /* + * Configure DMA/Interrupts + */ + + /* + * Set Rx/Tx DMA Configuration + * + * Set standard DMA size (128). Note that + * a DMA size of 512 causes rx overruns and tx errors + * on pci-e cards (tested on 5424 but since rx overruns + * also occur on 5416/5418 with madwifi we set 128 + * for all PCI-E cards to be safe). + * + * XXX: need to check 5210 for this + * TODO: Check out tx triger level, it's always 64 on dumps but I + * guess we can tweak it and see how it goes ;-) + */ + if (ah->ah_version != AR5K_AR5210) { + AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, + AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B); + AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, + AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B); + } + + /* Pre-enable interrupts on 5211/5212*/ + if (ah->ah_version != AR5K_AR5210) + ath5k_hw_set_imr(ah, ah->ah_imr); + + /* + * Setup RFKill interrupt if rfkill flag is set on eeprom. + * TODO: Use gpio pin and polarity infos from eeprom + * TODO: Handle this in ath5k_intr because it'll result + * a nasty interrupt storm. + */ +#if 0 + if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) { + ath5k_hw_set_gpio_input(ah, 0); + ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0); + if (ah->ah_gpio[0] == 0) + ath5k_hw_set_gpio_intr(ah, 0, 1); + else + ath5k_hw_set_gpio_intr(ah, 0, 0); + } +#endif + + /* + * Disable beacons and reset the register + */ + AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE | + AR5K_BEACON_RESET_TSF); + + return 0; +} + +#undef _ATH5K_RESET diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/base.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/base.h new file mode 100644 index 0000000..45dad07 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/base.h @@ -0,0 +1,140 @@ +/*- + * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net> + * Original from Linux kernel 2.6.30. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + */ + +/* + * Defintions for the Atheros Wireless LAN controller driver. + */ +#ifndef _DEV_ATH_ATHVAR_H +#define _DEV_ATH_ATHVAR_H + +FILE_LICENCE ( BSD3 ); + +#include "ath5k.h" +#include <gpxe/iobuf.h> + +#define ATH_RXBUF 16 /* number of RX buffers */ +#define ATH_TXBUF 16 /* number of TX buffers */ + +struct ath5k_buf { + struct list_head list; + unsigned int flags; /* rx descriptor flags */ + struct ath5k_desc *desc; /* virtual addr of desc */ + u32 daddr; /* physical addr of desc */ + struct io_buffer *iob; /* I/O buffer for buf */ + u32 iobaddr;/* physical addr of iob data */ +}; + +/* + * Data transmit queue state. One of these exists for each + * hardware transmit queue. Packets sent to us from above + * are assigned to queues based on their priority. Not all + * devices support a complete set of hardware transmit queues. + * For those devices the array sc_ac2q will map multiple + * priorities to fewer hardware queues (typically all to one + * hardware queue). + */ +struct ath5k_txq { + unsigned int qnum; /* hardware q number */ + u32 *link; /* link ptr in last TX desc */ + struct list_head q; /* transmit queue */ + int setup; +}; + +#if CHAN_DEBUG +#define ATH_CHAN_MAX (26+26+26+200+200) +#else +#define ATH_CHAN_MAX (14+14+14+252+20) +#endif + +/* Software Carrier, keeps track of the driver state + * associated with an instance of a device */ +struct ath5k_softc { + struct pci_device *pdev; /* for dma mapping */ + void *iobase; /* address of the device */ + struct net80211_device *dev; /* IEEE 802.11 common */ + struct ath5k_hw *ah; /* Atheros HW */ + struct net80211_hw_info *hwinfo; + int curband; + int irq_ena; /* interrupts enabled */ + + struct ath5k_buf *bufptr; /* allocated buffer ptr */ + struct ath5k_desc *desc; /* TX/RX descriptors */ + u32 desc_daddr; /* DMA (physical) address */ + size_t desc_len; /* size of TX/RX descriptors */ + u16 cachelsz; /* cache line size */ + + int status; +#define ATH_STAT_INVALID 0x01 /* disable hardware accesses */ +#define ATH_STAT_MRRETRY 0x02 /* multi-rate retry support */ +#define ATH_STAT_PROMISC 0x04 +#define ATH_STAT_LEDSOFT 0x08 /* enable LED gpio status */ +#define ATH_STAT_STARTED 0x10 /* opened & irqs enabled */ + + unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */ + unsigned int curmode; /* current phy mode */ + struct net80211_channel *curchan; /* current h/w channel */ + + enum ath5k_int imask; /* interrupt mask copy */ + + u8 bssidmask[ETH_ALEN]; + + unsigned int rxbufsize; /* rx size based on mtu */ + struct list_head rxbuf; /* receive buffer */ + u32 *rxlink; /* link ptr in last RX desc */ + + struct list_head txbuf; /* transmit buffer */ + unsigned int txbuf_len; /* buf count in txbuf list */ + struct ath5k_txq txq; /* tx queue */ + + int last_calib_ticks; + + int power_level; /* Requested tx power in dbm */ + int assoc; /* assocate state */ + + int hw_rate; /* Hardware tx rate code */ + int hw_rtscts_rate; /* Hardware rts/cts rate code */ +}; + +#define ath5k_hw_hasbssidmask(_ah) \ + (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0) +#define ath5k_hw_hasveol(_ah) \ + (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) + +#endif diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/desc.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/desc.h new file mode 100644 index 0000000..6e11b0d --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/desc.h @@ -0,0 +1,332 @@ +/* + * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* + * Internal RX/TX descriptor structures + * (rX: reserved fields possibily used by future versions of the ar5k chipset) + */ + +/* + * common hardware RX control descriptor + */ +struct ath5k_hw_rx_ctl { + u32 rx_control_0; /* RX control word 0 */ + u32 rx_control_1; /* RX control word 1 */ +} __attribute__ ((packed)); + +/* RX control word 0 field/sflags */ +#define AR5K_DESC_RX_CTL0 0x00000000 + +/* RX control word 1 fields/flags */ +#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff +#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 + +/* + * common hardware RX status descriptor + * 5210/11 and 5212 differ only in the flags defined below + */ +struct ath5k_hw_rx_status { + u32 rx_status_0; /* RX status word 0 */ + u32 rx_status_1; /* RX status word 1 */ +} __attribute__ ((packed)); + +/* 5210/5211 */ +/* RX status word 0 fields/flags */ +#define AR5K_5210_RX_DESC_STATUS0_DATA_LEN 0x00000fff +#define AR5K_5210_RX_DESC_STATUS0_MORE 0x00001000 +#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 +#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE_S 15 +#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 +#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19 +#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000 +#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27 + +/* RX status word 1 fields/flags */ +#define AR5K_5210_RX_DESC_STATUS1_DONE 0x00000001 +#define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 +#define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR 0x00000004 +#define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008 +#define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 +#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR 0x000000e0 +#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S 5 +#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 +#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX 0x00007e00 +#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S 9 +#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 +#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15 +#define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000 + +/* 5212 */ +/* RX status word 0 fields/flags */ +#define AR5K_5212_RX_DESC_STATUS0_DATA_LEN 0x00000fff +#define AR5K_5212_RX_DESC_STATUS0_MORE 0x00001000 +#define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000 +#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000 +#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE_S 15 +#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000 +#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20 +#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000 +#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28 + +/* RX status word 1 fields/flags */ +#define AR5K_5212_RX_DESC_STATUS1_DONE 0x00000001 +#define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 +#define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR 0x00000004 +#define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008 +#define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR 0x00000010 +#define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR 0x00000020 +#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 +#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00 +#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S 9 +#define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 +#define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16 +#define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000 + +/* + * common hardware RX error descriptor + */ +struct ath5k_hw_rx_error { + u32 rx_error_0; /* RX status word 0 */ + u32 rx_error_1; /* RX status word 1 */ +} __attribute__ ((packed)); + +/* RX error word 0 fields/flags */ +#define AR5K_RX_DESC_ERROR0 0x00000000 + +/* RX error word 1 fields/flags */ +#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00 +#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8 + +/* PHY Error codes */ +#define AR5K_DESC_RX_PHY_ERROR_NONE 0x00 +#define AR5K_DESC_RX_PHY_ERROR_TIMING 0x20 +#define AR5K_DESC_RX_PHY_ERROR_PARITY 0x40 +#define AR5K_DESC_RX_PHY_ERROR_RATE 0x60 +#define AR5K_DESC_RX_PHY_ERROR_LENGTH 0x80 +#define AR5K_DESC_RX_PHY_ERROR_64QAM 0xa0 +#define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0 +#define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 + +/* + * 5210/5211 hardware 2-word TX control descriptor + */ +struct ath5k_hw_2w_tx_ctl { + u32 tx_control_0; /* TX control word 0 */ + u32 tx_control_1; /* TX control word 1 */ +} __attribute__ ((packed)); + +/* TX control word 0 fields/flags */ +#define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff +#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/ +#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S 12 +#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 +#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18 +#define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 +#define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 +#define AR5K_2W_TX_DESC_CTL0_LONG_PACKET 0x00800000 /*[5210]*/ +#define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 /*[5211]*/ +#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 /*[5210]*/ +#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S 26 +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000 +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000 + +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT \ + (ah->ah_version == AR5K_AR5210 ? \ + AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \ + AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211) + +#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 +#define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 +#define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 + +/* TX control word 1 fields/flags */ +#define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff +#define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000 +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 0x0007e000 +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211 0x000fe000 + +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX \ + (ah->ah_version == AR5K_AR5210 ? \ + AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \ + AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211) + +#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 +#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 /*[5211]*/ +#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S 20 +#define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 /*[5211]*/ +#define AR5K_2W_TX_DESC_CTL1_RTS_DURATION 0xfff80000 /*[5210 ?]*/ + +/* Frame types */ +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0x00 +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 0x04 +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL 0x08 +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c +#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 0x10 + +/* + * 5212 hardware 4-word TX control descriptor + */ +struct ath5k_hw_4w_tx_ctl { + u32 tx_control_0; /* TX control word 0 */ + +#define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff +#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000 +#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16 +#define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000 +#define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000 +#define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000 +#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000 +#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 +#define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000 +#define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 +#define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000 + + u32 tx_control_1; /* TX control word 1 */ + +#define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff +#define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000 +#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 +#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 +#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000 +#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20 +#define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25 +#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27 +#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000 +#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29 + + u32 tx_control_2; /* TX control word 2 */ + +#define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff +#define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000 +#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28 + + u32 tx_control_3; /* TX control word 3 */ + +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000 +#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15 +#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 +#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20 +} __attribute__ ((packed)); + +/* + * Common TX status descriptor + */ +struct ath5k_hw_tx_status { + u32 tx_status_0; /* TX status word 0 */ + u32 tx_status_1; /* TX status word 1 */ +} __attribute__ ((packed)); + +/* TX status word 0 fields/flags */ +#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 +#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 +#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 +#define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008 +/*??? +#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0 +#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4 +*/ +#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0 +#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4 +/*??? +#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00 +#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8 +*/ +#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00 +#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8 +#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000 +#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12 +#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 +#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16 + +/* TX status word 1 fields/flags */ +#define AR5K_DESC_TX_STATUS1_DONE 0x00000001 +#define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe +#define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1 +#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 +#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13 +#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000 +#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21 +#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000 +#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000 + +/* + * 5210/5211 hardware TX descriptor + */ +struct ath5k_hw_5210_tx_desc { + struct ath5k_hw_2w_tx_ctl tx_ctl; + struct ath5k_hw_tx_status tx_stat; +} __attribute__ ((packed)); + +/* + * 5212 hardware TX descriptor + */ +struct ath5k_hw_5212_tx_desc { + struct ath5k_hw_4w_tx_ctl tx_ctl; + struct ath5k_hw_tx_status tx_stat; +} __attribute__ ((packed)); + +/* + * common hardware RX descriptor + */ +struct ath5k_hw_all_rx_desc { + struct ath5k_hw_rx_ctl rx_ctl; + union { + struct ath5k_hw_rx_status rx_stat; + struct ath5k_hw_rx_error rx_err; + } u; +} __attribute__ ((packed)); + +/* + * Atheros hardware descriptor + * This is read and written to by the hardware + */ +struct ath5k_desc { + u32 ds_link; /* physical address of the next descriptor */ + u32 ds_data; /* physical address of data buffer (skb) */ + + union { + struct ath5k_hw_5210_tx_desc ds_tx5210; + struct ath5k_hw_5212_tx_desc ds_tx5212; + struct ath5k_hw_all_rx_desc ds_rx; + } ud; +} __attribute__ ((packed)); + +#define AR5K_RXDESC_INTREQ 0x0020 + +#define AR5K_TXDESC_CLRDMASK 0x0001 +#define AR5K_TXDESC_NOACK 0x0002 /*[5211+]*/ +#define AR5K_TXDESC_RTSENA 0x0004 +#define AR5K_TXDESC_CTSENA 0x0008 +#define AR5K_TXDESC_INTREQ 0x0010 +#define AR5K_TXDESC_VEOL 0x0020 /*[5211+]*/ + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/eeprom.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/eeprom.h new file mode 100644 index 0000000..4d6250a --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/eeprom.h @@ -0,0 +1,441 @@ +/* + * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* + * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE) + */ +#define AR5K_EEPROM_MAGIC 0x003d /* EEPROM Magic number */ +#define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */ +#define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */ +#define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */ +#define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */ + +#define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */ +#define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */ +#define AR5K_EEPROM_CHECKSUM 0x00c0 /* EEPROM checksum */ +#define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */ +#define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE) +#define AR5K_EEPROM_INFO_CKSUM 0xffff +#define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n)) + +#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) /* EEPROM Version */ +#define AR5K_EEPROM_VERSION_3_0 0x3000 /* No idea what's going on before this version */ +#define AR5K_EEPROM_VERSION_3_1 0x3001 /* ob/db values for 2Ghz (ar5211_rfregs) */ +#define AR5K_EEPROM_VERSION_3_2 0x3002 /* different frequency representation (eeprom_bin2freq) */ +#define AR5K_EEPROM_VERSION_3_3 0x3003 /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */ +#define AR5K_EEPROM_VERSION_3_4 0x3004 /* has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) */ +#define AR5K_EEPROM_VERSION_4_0 0x4000 /* has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */ +#define AR5K_EEPROM_VERSION_4_1 0x4001 /* has ee_margin_tx_rx (eeprom_init) */ +#define AR5K_EEPROM_VERSION_4_2 0x4002 /* has ee_cck_ofdm_gain_delta (eeprom_init) */ +#define AR5K_EEPROM_VERSION_4_3 0x4003 /* power calibration changes */ +#define AR5K_EEPROM_VERSION_4_4 0x4004 +#define AR5K_EEPROM_VERSION_4_5 0x4005 +#define AR5K_EEPROM_VERSION_4_6 0x4006 /* has ee_scaled_cck_delta */ +#define AR5K_EEPROM_VERSION_4_7 0x3007 /* 4007 ? */ +#define AR5K_EEPROM_VERSION_4_9 0x4009 /* EAR futureproofing */ +#define AR5K_EEPROM_VERSION_5_0 0x5000 /* Has 2413 PDADC calibration etc */ +#define AR5K_EEPROM_VERSION_5_1 0x5001 /* Has capability values */ +#define AR5K_EEPROM_VERSION_5_3 0x5003 /* Has spur mitigation tables */ + +#define AR5K_EEPROM_MODE_11A 0 +#define AR5K_EEPROM_MODE_11B 1 +#define AR5K_EEPROM_MODE_11G 2 + +#define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) /* Header that contains the device caps */ +#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) +#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) +#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) +#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */ +#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */ +#define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) +#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */ +#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz */ + +#define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c +#define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2 +#define AR5K_EEPROM_RFKILL_POLARITY 0x00000002 +#define AR5K_EEPROM_RFKILL_POLARITY_S 1 + +/* Newer EEPROMs are using a different offset */ +#define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \ + (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0) + +#define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3) +#define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((s8)(((_v) >> 8) & 0xff)) +#define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((s8)((_v) & 0xff)) + +/* Misc values available since EEPROM 4.0 */ +#define AR5K_EEPROM_MISC0 AR5K_EEPROM_INFO(4) +#define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff) +#define AR5K_EEPROM_HDR_XR2_DIS(_v) (((_v) >> 12) & 0x1) +#define AR5K_EEPROM_HDR_XR5_DIS(_v) (((_v) >> 13) & 0x1) +#define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3) + +#define AR5K_EEPROM_MISC1 AR5K_EEPROM_INFO(5) +#define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff) +#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) +#define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) (((_v) >> 15) & 0x1) + +#define AR5K_EEPROM_MISC2 AR5K_EEPROM_INFO(6) +#define AR5K_EEPROM_EEP_FILE_VERSION(_v) (((_v) >> 8) & 0xff) +#define AR5K_EEPROM_EAR_FILE_VERSION(_v) ((_v) & 0xff) + +#define AR5K_EEPROM_MISC3 AR5K_EEPROM_INFO(7) +#define AR5K_EEPROM_ART_BUILD_NUM(_v) (((_v) >> 10) & 0x3f) +#define AR5K_EEPROM_EAR_FILE_ID(_v) ((_v) & 0xff) + +#define AR5K_EEPROM_MISC4 AR5K_EEPROM_INFO(8) +#define AR5K_EEPROM_CAL_DATA_START(_v) (((_v) >> 4) & 0xfff) +#define AR5K_EEPROM_MASK_R0(_v) (((_v) >> 2) & 0x3) +#define AR5K_EEPROM_MASK_R1(_v) ((_v) & 0x3) + +#define AR5K_EEPROM_MISC5 AR5K_EEPROM_INFO(9) +#define AR5K_EEPROM_COMP_DIS(_v) ((_v) & 0x1) +#define AR5K_EEPROM_AES_DIS(_v) (((_v) >> 1) & 0x1) +#define AR5K_EEPROM_FF_DIS(_v) (((_v) >> 2) & 0x1) +#define AR5K_EEPROM_BURST_DIS(_v) (((_v) >> 3) & 0x1) +#define AR5K_EEPROM_MAX_QCU(_v) (((_v) >> 4) & 0xf) +#define AR5K_EEPROM_HEAVY_CLIP_EN(_v) (((_v) >> 8) & 0x1) +#define AR5K_EEPROM_KEY_CACHE_SIZE(_v) (((_v) >> 12) & 0xf) + +#define AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10) +#define AR5K_EEPROM_TX_CHAIN_DIS ((_v) & 0x8) +#define AR5K_EEPROM_RX_CHAIN_DIS (((_v) >> 3) & 0x8) +#define AR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1) +#define AR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1) +#define AR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1) +#define AR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 9) & 0x1) +#define AR5K_EEPROM_JAP_11A_NEW_EN (((_v) >> 10) & 0x1) + +/* calibration settings */ +#define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) +#define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2) +#define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d) +#define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) /* Conformance test limits */ +#define AR5K_EEPROM_GROUPS_START(_v) AR5K_EEPROM_OFF(_v, 0x0100, 0x0150) /* Start of Groups */ +#define AR5K_EEPROM_GROUP1_OFFSET 0x0 +#define AR5K_EEPROM_GROUP2_OFFSET 0x5 +#define AR5K_EEPROM_GROUP3_OFFSET 0x37 +#define AR5K_EEPROM_GROUP4_OFFSET 0x46 +#define AR5K_EEPROM_GROUP5_OFFSET 0x55 +#define AR5K_EEPROM_GROUP6_OFFSET 0x65 +#define AR5K_EEPROM_GROUP7_OFFSET 0x69 +#define AR5K_EEPROM_GROUP8_OFFSET 0x6f + +#define AR5K_EEPROM_TARGET_PWR_OFF_11A(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \ + AR5K_EEPROM_GROUP5_OFFSET, 0x0000) +#define AR5K_EEPROM_TARGET_PWR_OFF_11B(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \ + AR5K_EEPROM_GROUP6_OFFSET, 0x0010) +#define AR5K_EEPROM_TARGET_PWR_OFF_11G(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \ + AR5K_EEPROM_GROUP7_OFFSET, 0x0014) + +/* [3.1 - 3.3] */ +#define AR5K_EEPROM_OBDB0_2GHZ 0x00ec +#define AR5K_EEPROM_OBDB1_2GHZ 0x00ed + +#define AR5K_EEPROM_PROTECT 0x003f /* EEPROM protect status */ +#define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 /* Read protection bit for offsets 0x0 - 0x1f */ +#define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 /* Write protection bit for offsets 0x0 - 0x1f */ +#define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 /* 0x20 - 0x3f */ +#define AR5K_EEPROM_PROTECT_WR_32_63 0x0008 +#define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 /* 0x40 - 0x7f */ +#define AR5K_EEPROM_PROTECT_WR_64_127 0x0020 +#define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 /* 0x80 - 0xbf (regdom) */ +#define AR5K_EEPROM_PROTECT_WR_128_191 0x0080 +#define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 /* 0xc0 - 0xcf */ +#define AR5K_EEPROM_PROTECT_WR_192_207 0x0200 +#define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 /* 0xd0 - 0xdf */ +#define AR5K_EEPROM_PROTECT_WR_208_223 0x0800 +#define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 /* 0xe0 - 0xef */ +#define AR5K_EEPROM_PROTECT_WR_224_239 0x2000 +#define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 /* 0xf0 - 0xff */ +#define AR5K_EEPROM_PROTECT_WR_240_255 0x8000 + +/* Some EEPROM defines */ +#define AR5K_EEPROM_EEP_SCALE 100 +#define AR5K_EEPROM_EEP_DELTA 10 +#define AR5K_EEPROM_N_MODES 3 +#define AR5K_EEPROM_N_5GHZ_CHAN 10 +#define AR5K_EEPROM_N_2GHZ_CHAN 3 +#define AR5K_EEPROM_N_2GHZ_CHAN_2413 4 +#define AR5K_EEPROM_N_2GHZ_CHAN_MAX 4 +#define AR5K_EEPROM_MAX_CHAN 10 +#define AR5K_EEPROM_N_PWR_POINTS_5111 11 +#define AR5K_EEPROM_N_PCDAC 11 +#define AR5K_EEPROM_N_PHASE_CAL 5 +#define AR5K_EEPROM_N_TEST_FREQ 8 +#define AR5K_EEPROM_N_EDGES 8 +#define AR5K_EEPROM_N_INTERCEPTS 11 +#define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff) +#define AR5K_EEPROM_PCDAC_M 0x3f +#define AR5K_EEPROM_PCDAC_START 1 +#define AR5K_EEPROM_PCDAC_STOP 63 +#define AR5K_EEPROM_PCDAC_STEP 1 +#define AR5K_EEPROM_NON_EDGE_M 0x40 +#define AR5K_EEPROM_CHANNEL_POWER 8 +#define AR5K_EEPROM_N_OBDB 4 +#define AR5K_EEPROM_OBDB_DIS 0xffff +#define AR5K_EEPROM_CHANNEL_DIS 0xff +#define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10) +#define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32) +#define AR5K_EEPROM_MAX_CTLS 32 +#define AR5K_EEPROM_N_PD_CURVES 4 +#define AR5K_EEPROM_N_XPD0_POINTS 4 +#define AR5K_EEPROM_N_XPD3_POINTS 3 +#define AR5K_EEPROM_N_PD_GAINS 4 +#define AR5K_EEPROM_N_PD_POINTS 5 +#define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35 +#define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55 +#define AR5K_EEPROM_POWER_M 0x3f +#define AR5K_EEPROM_POWER_MIN 0 +#define AR5K_EEPROM_POWER_MAX 3150 +#define AR5K_EEPROM_POWER_STEP 50 +#define AR5K_EEPROM_POWER_TABLE_SIZE 64 +#define AR5K_EEPROM_N_POWER_LOC_11B 4 +#define AR5K_EEPROM_N_POWER_LOC_11G 6 +#define AR5K_EEPROM_I_GAIN 10 +#define AR5K_EEPROM_CCK_OFDM_DELTA 15 +#define AR5K_EEPROM_N_IQ_CAL 2 + +#define AR5K_EEPROM_READ(_o, _v) do { \ + ret = ath5k_hw_eeprom_read(ah, (_o), &(_v)); \ + if (ret) \ + return ret; \ +} while (0) + +#define AR5K_EEPROM_READ_HDR(_o, _v) \ + AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v); \ + +enum ath5k_ant_setting { + AR5K_ANT_VARIABLE = 0, /* variable by programming */ + AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */ + AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */ + AR5K_ANT_MAX = 3, +}; + +enum ath5k_ctl_mode { + AR5K_CTL_11A = 0, + AR5K_CTL_11B = 1, + AR5K_CTL_11G = 2, + AR5K_CTL_TURBO = 3, + AR5K_CTL_TURBOG = 4, + AR5K_CTL_2GHT20 = 5, + AR5K_CTL_5GHT20 = 6, + AR5K_CTL_2GHT40 = 7, + AR5K_CTL_5GHT40 = 8, + AR5K_CTL_MODE_M = 15, +}; + +/* Default CTL ids for the 3 main reg domains. + * Atheros only uses these by default but vendors + * can have up to 32 different CTLs for different + * scenarios. Note that theese values are ORed with + * the mode id (above) so we can have up to 24 CTL + * datasets out of these 3 main regdomains. That leaves + * 8 ids that can be used by vendors and since 0x20 is + * missing from HAL sources i guess this is the set of + * custom CTLs vendors can use. */ +#define AR5K_CTL_FCC 0x10 +#define AR5K_CTL_CUSTOM 0x20 +#define AR5K_CTL_ETSI 0x30 +#define AR5K_CTL_MKK 0x40 + +/* Indicates a CTL with only mode set and + * no reg domain mapping, such CTLs are used + * for world roaming domains or simply when + * a reg domain is not set */ +#define AR5K_CTL_NO_REGDOMAIN 0xf0 + +/* Indicates an empty (invalid) CTL */ +#define AR5K_CTL_NO_CTL 0xff + +/* Per channel calibration data, used for power table setup */ +struct ath5k_chan_pcal_info_rf5111 { + /* Power levels in half dbm units + * for one power curve. */ + u8 pwr[AR5K_EEPROM_N_PWR_POINTS_5111]; + /* PCDAC table steps + * for the above values */ + u8 pcdac[AR5K_EEPROM_N_PWR_POINTS_5111]; + /* Starting PCDAC step */ + u8 pcdac_min; + /* Final PCDAC step */ + u8 pcdac_max; +}; + +struct ath5k_chan_pcal_info_rf5112 { + /* Power levels in quarter dBm units + * for lower (0) and higher (3) + * level curves in 0.25dB units */ + s8 pwr_x0[AR5K_EEPROM_N_XPD0_POINTS]; + s8 pwr_x3[AR5K_EEPROM_N_XPD3_POINTS]; + /* PCDAC table steps + * for the above values */ + u8 pcdac_x0[AR5K_EEPROM_N_XPD0_POINTS]; + u8 pcdac_x3[AR5K_EEPROM_N_XPD3_POINTS]; +}; + +struct ath5k_chan_pcal_info_rf2413 { + /* Starting pwr/pddac values */ + s8 pwr_i[AR5K_EEPROM_N_PD_GAINS]; + u8 pddac_i[AR5K_EEPROM_N_PD_GAINS]; + /* (pwr,pddac) points + * power levels in 0.5dB units */ + s8 pwr[AR5K_EEPROM_N_PD_GAINS] + [AR5K_EEPROM_N_PD_POINTS]; + u8 pddac[AR5K_EEPROM_N_PD_GAINS] + [AR5K_EEPROM_N_PD_POINTS]; +}; + +enum ath5k_powertable_type { + AR5K_PWRTABLE_PWR_TO_PCDAC = 0, + AR5K_PWRTABLE_LINEAR_PCDAC = 1, + AR5K_PWRTABLE_PWR_TO_PDADC = 2, +}; + +struct ath5k_pdgain_info { + u8 pd_points; + u8 *pd_step; + /* Power values are in + * 0.25dB units */ + s16 *pd_pwr; +}; + +struct ath5k_chan_pcal_info { + /* Frequency */ + u16 freq; + /* Tx power boundaries */ + s16 max_pwr; + s16 min_pwr; + union { + struct ath5k_chan_pcal_info_rf5111 rf5111_info; + struct ath5k_chan_pcal_info_rf5112 rf5112_info; + struct ath5k_chan_pcal_info_rf2413 rf2413_info; + }; + /* Raw values used by phy code + * Curves are stored in order from lower + * gain to higher gain (max txpower -> min txpower) */ + struct ath5k_pdgain_info *pd_curves; +}; + +/* Per rate calibration data for each mode, + * used for rate power table setup. + * Note: Values in 0.5dB units */ +struct ath5k_rate_pcal_info { + u16 freq; /* Frequency */ + /* Power level for 6-24Mbit/s rates or + * 1Mb rate */ + u16 target_power_6to24; + /* Power level for 36Mbit rate or + * 2Mb rate */ + u16 target_power_36; + /* Power level for 48Mbit rate or + * 5.5Mbit rate */ + u16 target_power_48; + /* Power level for 54Mbit rate or + * 11Mbit rate */ + u16 target_power_54; +}; + +/* Power edges for conformance test limits */ +struct ath5k_edge_power { + u16 freq; + u16 edge; /* in half dBm */ + int flag; +}; + +/* EEPROM calibration data */ +struct ath5k_eeprom_info { + + /* Header information */ + u16 ee_magic; + u16 ee_protect; + u16 ee_regdomain; + u16 ee_version; + u16 ee_header; + u16 ee_ant_gain; + u16 ee_misc0; + u16 ee_misc1; + u16 ee_misc2; + u16 ee_misc3; + u16 ee_misc4; + u16 ee_misc5; + u16 ee_misc6; + u16 ee_cck_ofdm_gain_delta; + u16 ee_cck_ofdm_power_delta; + u16 ee_scaled_cck_delta; + + /* RF Calibration settings (reset, rfregs) */ + u16 ee_i_cal[AR5K_EEPROM_N_MODES]; + u16 ee_q_cal[AR5K_EEPROM_N_MODES]; + u16 ee_fixed_bias[AR5K_EEPROM_N_MODES]; + u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES]; + u16 ee_xr_power[AR5K_EEPROM_N_MODES]; + u16 ee_switch_settling[AR5K_EEPROM_N_MODES]; + u16 ee_atn_tx_rx[AR5K_EEPROM_N_MODES]; + u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]; + u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; + u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; + u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]; + u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]; + u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]; + u16 ee_thr_62[AR5K_EEPROM_N_MODES]; + u16 ee_xlna_gain[AR5K_EEPROM_N_MODES]; + u16 ee_xpd[AR5K_EEPROM_N_MODES]; + u16 ee_x_gain[AR5K_EEPROM_N_MODES]; + u16 ee_i_gain[AR5K_EEPROM_N_MODES]; + u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; + u16 ee_switch_settling_turbo[AR5K_EEPROM_N_MODES]; + u16 ee_margin_tx_rx_turbo[AR5K_EEPROM_N_MODES]; + u16 ee_atn_tx_rx_turbo[AR5K_EEPROM_N_MODES]; + + /* Power calibration data */ + u16 ee_false_detect[AR5K_EEPROM_N_MODES]; + + /* Number of pd gain curves per mode */ + u8 ee_pd_gains[AR5K_EEPROM_N_MODES]; + /* Back mapping pdcurve number -> pdcurve index in pd->pd_curves */ + u8 ee_pdc_to_idx[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS]; + + u8 ee_n_piers[AR5K_EEPROM_N_MODES]; + struct ath5k_chan_pcal_info ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN]; + struct ath5k_chan_pcal_info ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX]; + struct ath5k_chan_pcal_info ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX]; + + /* Per rate target power levels */ + u8 ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES]; + struct ath5k_rate_pcal_info ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN]; + struct ath5k_rate_pcal_info ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX]; + struct ath5k_rate_pcal_info ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX]; + + /* Conformance test limits (Unused) */ + u8 ee_ctls; + u8 ee_ctl[AR5K_EEPROM_MAX_CTLS]; + struct ath5k_edge_power ee_ctl_pwr[AR5K_EEPROM_N_EDGES * AR5K_EEPROM_MAX_CTLS]; + + /* Noise Floor Calibration settings */ + s16 ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; + s8 ee_adc_desired_size[AR5K_EEPROM_N_MODES]; + s8 ee_pga_desired_size[AR5K_EEPROM_N_MODES]; + s8 ee_adc_desired_size_turbo[AR5K_EEPROM_N_MODES]; + s8 ee_pga_desired_size_turbo[AR5K_EEPROM_N_MODES]; + s8 ee_pd_gain_overlap; + + u32 ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; +}; + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/reg.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/reg.h new file mode 100644 index 0000000..7070d15 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/reg.h @@ -0,0 +1,2589 @@ +/* + * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> + * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* + * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k + * maintained by Reyk Floeter + * + * I tried to document those registers by looking at ar5k code, some + * 802.11 (802.11e mostly) papers and by reading various public available + * Atheros presentations and papers like these: + * + * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf + * http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf + * + * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf + * + * This file also contains register values found on a memory dump of + * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal + * released by Atheros and on various debug messages found on the net. + */ + + + +/*====MAC DMA REGISTERS====*/ + +/* + * AR5210-Specific TXDP registers + * 5210 has only 2 transmit queues so no DCU/QCU, just + * 2 transmit descriptor pointers... + */ +#define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */ +#define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */ + +/* + * Mac Control Register + */ +#define AR5K_CR 0x0008 /* Register Address */ +#define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */ +#define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */ +#define AR5K_CR_RXE 0x00000004 /* RX Enable */ +#define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */ +#define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */ +#define AR5K_CR_RXD 0x00000020 /* RX Disable */ +#define AR5K_CR_SWI 0x00000040 /* Software Interrupt */ + +/* + * RX Descriptor Pointer register + */ +#define AR5K_RXDP 0x000c + +/* + * Configuration and status register + */ +#define AR5K_CFG 0x0014 /* Register Address */ +#define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */ +#define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer */ +#define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */ +#define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */ +#define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */ +#define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */ +#define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */ +#define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */ +#define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */ +#define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */ +#define AR5K_CFG_TXCNT_S 11 +#define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */ +#define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */ +#define AR5K_CFG_PCI_THRES 0x00060000 /* PCI Master req q threshold [5211+] */ +#define AR5K_CFG_PCI_THRES_S 17 + +/* + * Interrupt enable register + */ +#define AR5K_IER 0x0024 /* Register Address */ +#define AR5K_IER_DISABLE 0x00000000 /* Disable card interrupts */ +#define AR5K_IER_ENABLE 0x00000001 /* Enable card interrupts */ + + +/* + * 0x0028 is Beacon Control Register on 5210 + * and first RTS duration register on 5211 + */ + +/* + * Beacon control register [5210] + */ +#define AR5K_BCR 0x0028 /* Register Address */ +#define AR5K_BCR_AP 0x00000000 /* AP mode */ +#define AR5K_BCR_ADHOC 0x00000001 /* Ad-Hoc mode */ +#define AR5K_BCR_BDMAE 0x00000002 /* DMA enable */ +#define AR5K_BCR_TQ1FV 0x00000004 /* Use Queue1 for CAB traffic */ +#define AR5K_BCR_TQ1V 0x00000008 /* Use Queue1 for Beacon traffic */ +#define AR5K_BCR_BCGET 0x00000010 + +/* + * First RTS duration register [5211] + */ +#define AR5K_RTSD0 0x0028 /* Register Address */ +#define AR5K_RTSD0_6 0x000000ff /* 6Mb RTS duration mask (?) */ +#define AR5K_RTSD0_6_S 0 /* 6Mb RTS duration shift (?) */ +#define AR5K_RTSD0_9 0x0000ff00 /* 9Mb*/ +#define AR5K_RTSD0_9_S 8 +#define AR5K_RTSD0_12 0x00ff0000 /* 12Mb*/ +#define AR5K_RTSD0_12_S 16 +#define AR5K_RTSD0_18 0xff000000 /* 16Mb*/ +#define AR5K_RTSD0_18_S 24 + + +/* + * 0x002c is Beacon Status Register on 5210 + * and second RTS duration register on 5211 + */ + +/* + * Beacon status register [5210] + * + * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR + * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning + * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR). + * So SNAPPEDBCRVALID sould also stand for "snapped BCR -values- valid", so i + * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what + * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR. + */ +#define AR5K_BSR 0x002c /* Register Address */ +#define AR5K_BSR_BDLYSW 0x00000001 /* SW Beacon delay (?) */ +#define AR5K_BSR_BDLYDMA 0x00000002 /* DMA Beacon delay (?) */ +#define AR5K_BSR_TXQ1F 0x00000004 /* Beacon queue (1) finished */ +#define AR5K_BSR_ATIMDLY 0x00000008 /* ATIM delay (?) */ +#define AR5K_BSR_SNPADHOC 0x00000100 /* Ad-hoc mode set (?) */ +#define AR5K_BSR_SNPBDMAE 0x00000200 /* Beacon DMA enabled (?) */ +#define AR5K_BSR_SNPTQ1FV 0x00000400 /* Queue1 is used for CAB traffic (?) */ +#define AR5K_BSR_SNPTQ1V 0x00000800 /* Queue1 is used for Beacon traffic (?) */ +#define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /* BCR snapshots are valid (?) */ +#define AR5K_BSR_SWBA_CNT 0x00ff0000 + +/* + * Second RTS duration register [5211] + */ +#define AR5K_RTSD1 0x002c /* Register Address */ +#define AR5K_RTSD1_24 0x000000ff /* 24Mb */ +#define AR5K_RTSD1_24_S 0 +#define AR5K_RTSD1_36 0x0000ff00 /* 36Mb */ +#define AR5K_RTSD1_36_S 8 +#define AR5K_RTSD1_48 0x00ff0000 /* 48Mb */ +#define AR5K_RTSD1_48_S 16 +#define AR5K_RTSD1_54 0xff000000 /* 54Mb */ +#define AR5K_RTSD1_54_S 24 + + +/* + * Transmit configuration register + */ +#define AR5K_TXCFG 0x0030 /* Register Address */ +#define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size (read) */ +#define AR5K_TXCFG_SDMAMR_S 0 +#define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */ +#define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */ +#define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Triger level mask */ +#define AR5K_TXCFG_TXFULL_S 4 +#define AR5K_TXCFG_TXFULL_0B 0x00000000 +#define AR5K_TXCFG_TXFULL_64B 0x00000010 +#define AR5K_TXCFG_TXFULL_128B 0x00000020 +#define AR5K_TXCFG_TXFULL_192B 0x00000030 +#define AR5K_TXCFG_TXFULL_256B 0x00000040 +#define AR5K_TXCFG_TXCONT_EN 0x00000080 +#define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */ +#define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400 /* Enable jumbo tx descriptors [5211+] */ +#define AR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800 /* Adhoc Beacon ATIM Policy */ +#define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000 /* Disable ATIM window defer [5211+] */ +#define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */ +#define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */ +#define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */ +#define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 /* Jumbo frame mode [5211+] */ +#define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000 /* Disable double buffering on DCU */ +#define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000 /* Disable DCU caching */ + +/* + * Receive configuration register + */ +#define AR5K_RXCFG 0x0034 /* Register Address */ +#define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size (write) */ +#define AR5K_RXCFG_SDMAMW_S 0 +#define AR5K_RXCFG_ZLFDMA 0x00000008 /* Enable Zero-length frame DMA */ +#define AR5K_RXCFG_DEF_ANTENNA 0x00000010 /* Default antenna (?) */ +#define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo rx descriptors [5211+] */ +#define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames [5211+] */ +#define AR5K_RXCFG_SLE_ENTRY 0x00000080 /* Sleep entry policy */ + +/* + * Receive jumbo descriptor last address register + * Only found in 5211 (?) + */ +#define AR5K_RXJLA 0x0038 + +/* + * MIB control register + */ +#define AR5K_MIBC 0x0040 /* Register Address */ +#define AR5K_MIBC_COW 0x00000001 /* Warn test indicator */ +#define AR5K_MIBC_FMC 0x00000002 /* Freeze MIB Counters */ +#define AR5K_MIBC_CMC 0x00000004 /* Clean MIB Counters */ +#define AR5K_MIBC_MCS 0x00000008 /* MIB counter strobe */ + +/* + * Timeout prescale register + */ +#define AR5K_TOPS 0x0044 +#define AR5K_TOPS_M 0x0000ffff + +/* + * Receive timeout register (no frame received) + */ +#define AR5K_RXNOFRM 0x0048 +#define AR5K_RXNOFRM_M 0x000003ff + +/* + * Transmit timeout register (no frame sent) + */ +#define AR5K_TXNOFRM 0x004c +#define AR5K_TXNOFRM_M 0x000003ff +#define AR5K_TXNOFRM_QCU 0x000ffc00 +#define AR5K_TXNOFRM_QCU_S 10 + +/* + * Receive frame gap timeout register + */ +#define AR5K_RPGTO 0x0050 +#define AR5K_RPGTO_M 0x000003ff + +/* + * Receive frame count limit register + */ +#define AR5K_RFCNT 0x0054 +#define AR5K_RFCNT_M 0x0000001f /* [5211+] (?) */ +#define AR5K_RFCNT_RFCL 0x0000000f /* [5210] */ + +/* + * Misc settings register + * (reserved0-3) + */ +#define AR5K_MISC 0x0058 /* Register Address */ +#define AR5K_MISC_DMA_OBS_M 0x000001e0 +#define AR5K_MISC_DMA_OBS_S 5 +#define AR5K_MISC_MISC_OBS_M 0x00000e00 +#define AR5K_MISC_MISC_OBS_S 9 +#define AR5K_MISC_MAC_OBS_LSB_M 0x00007000 +#define AR5K_MISC_MAC_OBS_LSB_S 12 +#define AR5K_MISC_MAC_OBS_MSB_M 0x00038000 +#define AR5K_MISC_MAC_OBS_MSB_S 15 +#define AR5K_MISC_LED_DECAY 0x001c0000 /* [5210] */ +#define AR5K_MISC_LED_BLINK 0x00e00000 /* [5210] */ + +/* + * QCU/DCU clock gating register (5311) + * (reserved4-5) + */ +#define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */ +#define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */ +#define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /* Mask for DCU clock */ + +/* + * Interrupt Status Registers + * + * For 5210 there is only one status register but for + * 5211/5212 we have one primary and 4 secondary registers. + * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212. + * Most of these bits are common for all chipsets. + */ +#define AR5K_ISR 0x001c /* Register Address [5210] */ +#define AR5K_PISR 0x0080 /* Register Address [5211+] */ +#define AR5K_ISR_RXOK 0x00000001 /* Frame successfuly recieved */ +#define AR5K_ISR_RXDESC 0x00000002 /* RX descriptor request */ +#define AR5K_ISR_RXERR 0x00000004 /* Receive error */ +#define AR5K_ISR_RXNOFRM 0x00000008 /* No frame received (receive timeout) */ +#define AR5K_ISR_RXEOL 0x00000010 /* Empty RX descriptor */ +#define AR5K_ISR_RXORN 0x00000020 /* Receive FIFO overrun */ +#define AR5K_ISR_TXOK 0x00000040 /* Frame successfuly transmited */ +#define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */ +#define AR5K_ISR_TXERR 0x00000100 /* Transmit error */ +#define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout) */ +#define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */ +#define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */ +#define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ +#define AR5K_ISR_SWI 0x00002000 /* Software interrupt */ +#define AR5K_ISR_RXPHY 0x00004000 /* PHY error */ +#define AR5K_ISR_RXKCM 0x00008000 /* RX Key cache miss */ +#define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ +#define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ +#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ +#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ +#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ +#define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ +#define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */ +#define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */ +#define AR5K_ISR_DPERR 0x00400000 /* Det par Error (?) [5210] */ +#define AR5K_ISR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */ +#define AR5K_ISR_TIM 0x00800000 /* [5211+] */ +#define AR5K_ISR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT, + CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */ +#define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill) */ +#define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */ +#define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */ +#define AR5K_ISR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */ + +/* + * Secondary status registers [5211+] (0 - 4) + * + * These give the status for each QCU, only QCUs 0-9 are + * represented. + */ +#define AR5K_SISR0 0x0084 /* Register Address [5211+] */ +#define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ +#define AR5K_SISR0_QCU_TXOK_S 0 +#define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ +#define AR5K_SISR0_QCU_TXDESC_S 16 + +#define AR5K_SISR1 0x0088 /* Register Address [5211+] */ +#define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ +#define AR5K_SISR1_QCU_TXERR_S 0 +#define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ +#define AR5K_SISR1_QCU_TXEOL_S 16 + +#define AR5K_SISR2 0x008c /* Register Address [5211+] */ +#define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ +#define AR5K_SISR2_QCU_TXURN_S 0 +#define AR5K_SISR2_MCABT 0x00100000 /* Master Cycle Abort */ +#define AR5K_SISR2_SSERR 0x00200000 /* Signaled System Error */ +#define AR5K_SISR2_DPERR 0x00400000 /* Bus parity error */ +#define AR5K_SISR2_TIM 0x01000000 /* [5212+] */ +#define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */ +#define AR5K_SISR2_DTIM_SYNC 0x04000000 /* DTIM sync lost [5212+] */ +#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ +#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ +#define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ +#define AR5K_SISR2_TSFOOR 0x80000000 /* TSF OOR (?) */ + +#define AR5K_SISR3 0x0090 /* Register Address [5211+] */ +#define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ +#define AR5K_SISR3_QCBRORN_S 0 +#define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ +#define AR5K_SISR3_QCBRURN_S 16 + +#define AR5K_SISR4 0x0094 /* Register Address [5211+] */ +#define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */ +#define AR5K_SISR4_QTRIG_S 0 + +/* + * Shadow read-and-clear interrupt status registers [5211+] + */ +#define AR5K_RAC_PISR 0x00c0 /* Read and clear PISR */ +#define AR5K_RAC_SISR0 0x00c4 /* Read and clear SISR0 */ +#define AR5K_RAC_SISR1 0x00c8 /* Read and clear SISR1 */ +#define AR5K_RAC_SISR2 0x00cc /* Read and clear SISR2 */ +#define AR5K_RAC_SISR3 0x00d0 /* Read and clear SISR3 */ +#define AR5K_RAC_SISR4 0x00d4 /* Read and clear SISR4 */ + +/* + * Interrupt Mask Registers + * + * As whith ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary + * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match. + */ +#define AR5K_IMR 0x0020 /* Register Address [5210] */ +#define AR5K_PIMR 0x00a0 /* Register Address [5211+] */ +#define AR5K_IMR_RXOK 0x00000001 /* Frame successfuly recieved*/ +#define AR5K_IMR_RXDESC 0x00000002 /* RX descriptor request*/ +#define AR5K_IMR_RXERR 0x00000004 /* Receive error*/ +#define AR5K_IMR_RXNOFRM 0x00000008 /* No frame received (receive timeout)*/ +#define AR5K_IMR_RXEOL 0x00000010 /* Empty RX descriptor*/ +#define AR5K_IMR_RXORN 0x00000020 /* Receive FIFO overrun*/ +#define AR5K_IMR_TXOK 0x00000040 /* Frame successfuly transmited*/ +#define AR5K_IMR_TXDESC 0x00000080 /* TX descriptor request*/ +#define AR5K_IMR_TXERR 0x00000100 /* Transmit error*/ +#define AR5K_IMR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout)*/ +#define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/ +#define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/ +#define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/ +#define AR5K_IMR_SWI 0x00002000 /* Software interrupt */ +#define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/ +#define AR5K_IMR_RXKCM 0x00008000 /* RX Key cache miss */ +#define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/ +#define AR5K_IMR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ +#define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ +#define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ +#define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ +#define AR5K_IMR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ +#define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/ +#define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */ +#define AR5K_IMR_DPERR 0x00400000 /* Det par Error (?) [5210] */ +#define AR5K_IMR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */ +#define AR5K_IMR_TIM 0x00800000 /* [5211+] */ +#define AR5K_IMR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT, + CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */ +#define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/ +#define AR5K_IMR_QCBRORN 0x02000000 /* QCU CBR overrun (?) [5211+] */ +#define AR5K_IMR_QCBRURN 0x04000000 /* QCU CBR underrun (?) [5211+] */ +#define AR5K_IMR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */ + +/* + * Secondary interrupt mask registers [5211+] (0 - 4) + */ +#define AR5K_SIMR0 0x00a4 /* Register Address [5211+] */ +#define AR5K_SIMR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ +#define AR5K_SIMR0_QCU_TXOK_S 0 +#define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ +#define AR5K_SIMR0_QCU_TXDESC_S 16 + +#define AR5K_SIMR1 0x00a8 /* Register Address [5211+] */ +#define AR5K_SIMR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ +#define AR5K_SIMR1_QCU_TXERR_S 0 +#define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ +#define AR5K_SIMR1_QCU_TXEOL_S 16 + +#define AR5K_SIMR2 0x00ac /* Register Address [5211+] */ +#define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ +#define AR5K_SIMR2_QCU_TXURN_S 0 +#define AR5K_SIMR2_MCABT 0x00100000 /* Master Cycle Abort */ +#define AR5K_SIMR2_SSERR 0x00200000 /* Signaled System Error */ +#define AR5K_SIMR2_DPERR 0x00400000 /* Bus parity error */ +#define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */ +#define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */ +#define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* DTIM Sync lost [5212+] */ +#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ +#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ +#define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */ +#define AR5K_SIMR2_TSFOOR 0x80000000 /* TSF OOR (?) */ + +#define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */ +#define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ +#define AR5K_SIMR3_QCBRORN_S 0 +#define AR5K_SIMR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ +#define AR5K_SIMR3_QCBRURN_S 16 + +#define AR5K_SIMR4 0x00b4 /* Register Address [5211+] */ +#define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */ +#define AR5K_SIMR4_QTRIG_S 0 + +/* + * DMA Debug registers 0-7 + * 0xe0 - 0xfc + */ + +/* + * Decompression mask registers [5212+] + */ +#define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (index) */ +#define AR5K_DCM_DATA 0x0404 /*Decompression mask data */ + +/* + * Wake On Wireless pattern control register [5212+] + */ +#define AR5K_WOW_PCFG 0x0410 /* Register Address */ +#define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001 /* Pattern match enable */ +#define AR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002 /* Long frame policy */ +#define AR5K_WOW_PCFG_WOBMISS 0x00000004 /* Wake on bea(con) miss (?) */ +#define AR5K_WOW_PCFG_PAT_0_EN 0x00000100 /* Enable pattern 0 */ +#define AR5K_WOW_PCFG_PAT_1_EN 0x00000200 /* Enable pattern 1 */ +#define AR5K_WOW_PCFG_PAT_2_EN 0x00000400 /* Enable pattern 2 */ +#define AR5K_WOW_PCFG_PAT_3_EN 0x00000800 /* Enable pattern 3 */ +#define AR5K_WOW_PCFG_PAT_4_EN 0x00001000 /* Enable pattern 4 */ +#define AR5K_WOW_PCFG_PAT_5_EN 0x00002000 /* Enable pattern 5 */ + +/* + * Wake On Wireless pattern index register (?) [5212+] + */ +#define AR5K_WOW_PAT_IDX 0x0414 + +/* + * Wake On Wireless pattern data register [5212+] + */ +#define AR5K_WOW_PAT_DATA 0x0418 /* Register Address */ +#define AR5K_WOW_PAT_DATA_0_3_V 0x00000001 /* Pattern 0, 3 value */ +#define AR5K_WOW_PAT_DATA_1_4_V 0x00000100 /* Pattern 1, 4 value */ +#define AR5K_WOW_PAT_DATA_2_5_V 0x00010000 /* Pattern 2, 5 value */ +#define AR5K_WOW_PAT_DATA_0_3_M 0x01000000 /* Pattern 0, 3 mask */ +#define AR5K_WOW_PAT_DATA_1_4_M 0x04000000 /* Pattern 1, 4 mask */ +#define AR5K_WOW_PAT_DATA_2_5_M 0x10000000 /* Pattern 2, 5 mask */ + +/* + * Decompression configuration registers [5212+] + */ +#define AR5K_DCCFG 0x0420 /* Register Address */ +#define AR5K_DCCFG_GLOBAL_EN 0x00000001 /* Enable decompression on all queues */ +#define AR5K_DCCFG_BYPASS_EN 0x00000002 /* Bypass decompression */ +#define AR5K_DCCFG_BCAST_EN 0x00000004 /* Enable decompression for bcast frames */ +#define AR5K_DCCFG_MCAST_EN 0x00000008 /* Enable decompression for mcast frames */ + +/* + * Compression configuration registers [5212+] + */ +#define AR5K_CCFG 0x0600 /* Register Address */ +#define AR5K_CCFG_WINDOW_SIZE 0x00000007 /* Compression window size */ +#define AR5K_CCFG_CPC_EN 0x00000008 /* Enable performance counters */ + +#define AR5K_CCFG_CCU 0x0604 /* Register Address */ +#define AR5K_CCFG_CCU_CUP_EN 0x00000001 /* CCU Catchup enable */ +#define AR5K_CCFG_CCU_CREDIT 0x00000002 /* CCU Credit (field) */ +#define AR5K_CCFG_CCU_CD_THRES 0x00000080 /* CCU Cyc(lic?) debt threshold (field) */ +#define AR5K_CCFG_CCU_CUP_LCNT 0x00010000 /* CCU Catchup lit(?) count */ +#define AR5K_CCFG_CCU_INIT 0x00100200 /* Initial value during reset */ + +/* + * Compression performance counter registers [5212+] + */ +#define AR5K_CPC0 0x0610 /* Compression performance counter 0 */ +#define AR5K_CPC1 0x0614 /* Compression performance counter 1*/ +#define AR5K_CPC2 0x0618 /* Compression performance counter 2 */ +#define AR5K_CPC3 0x061c /* Compression performance counter 3 */ +#define AR5K_CPCOVF 0x0620 /* Compression performance overflow */ + + +/* + * Queue control unit (QCU) registers [5211+] + * + * Card has 12 TX Queues but i see that only 0-9 are used (?) + * both in binary HAL (see ah.h) and ar5k. Each queue has it's own + * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate) + * configuration register (0x08c0 - 0x08ec), a ready time configuration + * register (0x0900 - 0x092c), a misc configuration register (0x09c0 - + * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some + * global registers, QCU transmit enable/disable and "one shot arm (?)" + * set/clear, which contain status for all queues (we shift by 1 for each + * queue). To access these registers easily we define some macros here + * that are used inside HAL. For more infos check out *_tx_queue functs. + */ + +/* + * Generic QCU Register access macros + */ +#define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r) +#define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q)) +#define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q)) + +/* + * QCU Transmit descriptor pointer registers + */ +#define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */ +#define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q) + +/* + * QCU Transmit enable register + */ +#define AR5K_QCU_TXE 0x0840 +#define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q) +#define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q) + +/* + * QCU Transmit disable register + */ +#define AR5K_QCU_TXD 0x0880 +#define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q) +#define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q) + +/* + * QCU Constant Bit Rate configuration registers + */ +#define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */ +#define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */ +#define AR5K_QCU_CBRCFG_INTVAL_S 0 +#define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */ +#define AR5K_QCU_CBRCFG_ORN_THRES_S 24 +#define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q) + +/* + * QCU Ready time configuration registers + */ +#define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */ +#define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */ +#define AR5K_QCU_RDYTIMECFG_INTVAL_S 0 +#define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */ +#define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q) + +/* + * QCU one shot arm set registers + */ +#define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */ +#define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff + +/* + * QCU one shot arm clear registers + */ +#define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */ +#define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff + +/* + * QCU misc registers + */ +#define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */ +#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */ +#define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */ +#define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */ +#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated */ +#define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* TIMT gated */ +#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated */ +#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */ +#define AR5K_QCU_MISC_CBREXP_DIS 0x00000020 /* Disable CBR expired counter (normal queue) */ +#define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 /* Disable CBR expired counter (beacon queue) */ +#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Enable Beacon use */ +#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR expired threshold enabled */ +#define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 /* TXE reset when RDYTIME expired or VEOL */ +#define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */ +#define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU early termination */ +#define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000 /* Enable frame compression */ +#define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q) + + +/* + * QCU status registers + */ +#define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */ +#define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */ +#define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter */ +#define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q) + +/* + * QCU ready time shutdown register + */ +#define AR5K_QCU_RDYTIMESHDN 0x0a40 +#define AR5K_QCU_RDYTIMESHDN_M 0x000003ff + +/* + * QCU compression buffer base registers [5212+] + */ +#define AR5K_QCU_CBB_SELECT 0x0b00 +#define AR5K_QCU_CBB_ADDR 0x0b04 +#define AR5K_QCU_CBB_ADDR_S 9 + +/* + * QCU compression buffer configuration register [5212+] + * (buffer size) + */ +#define AR5K_QCU_CBCFG 0x0b08 + + + +/* + * Distributed Coordination Function (DCF) control unit (DCU) + * registers [5211+] + * + * These registers control the various characteristics of each queue + * for 802.11e (WME) combatibility so they go together with + * QCU registers in pairs. For each queue we have a QCU mask register, + * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c), + * a retry limit register (0x1080 - 0x10ac), a channel time register + * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and + * a sequence number register (0x1140 - 0x116c). It seems that "global" + * registers here afect all queues (see use of DCU_GBL_IFS_SLOT in ar5k). + * We use the same macros here for easier register access. + * + */ + +/* + * DCU QCU mask registers + */ +#define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */ +#define AR5K_DCU_QCUMASK_M 0x000003ff +#define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q) + +/* + * DCU local Inter Frame Space settings register + */ +#define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */ +#define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff /* Minimum Contention Window */ +#define AR5K_DCU_LCL_IFS_CW_MIN_S 0 +#define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 /* Maximum Contention Window */ +#define AR5K_DCU_LCL_IFS_CW_MAX_S 10 +#define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */ +#define AR5K_DCU_LCL_IFS_AIFS_S 20 +#define AR5K_DCU_LCL_IFS_AIFS_MAX 0xfc /* Anything above that can cause DCU to hang */ +#define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q) + +/* + * DCU retry limit registers + */ +#define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */ +#define AR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ +#define AR5K_DCU_RETRY_LMT_SH_RETRY_S 0 +#define AR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry limit mask */ +#define AR5K_DCU_RETRY_LMT_LG_RETRY_S 4 +#define AR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask (?) */ +#define AR5K_DCU_RETRY_LMT_SSH_RETRY_S 8 +#define AR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask (?) */ +#define AR5K_DCU_RETRY_LMT_SLG_RETRY_S 14 +#define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q) + +/* + * DCU channel time registers + */ +#define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */ +#define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /* Channel time duration */ +#define AR5K_DCU_CHAN_TIME_DUR_S 0 +#define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /* Enable channel time */ +#define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q) + +/* + * DCU misc registers [5211+] + * + * Note: Arbiter lockout control controls the + * behaviour on low priority queues when we have multiple queues + * with pending frames. Intra-frame lockout means we wait until + * the queue's current frame transmits (with post frame backoff and bursting) + * before we transmit anything else and global lockout means we + * wait for the whole queue to finish before higher priority queues + * can transmit (this is used on beacon and CAB queues). + * No lockout means there is no special handling. + */ +#define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */ +#define AR5K_DCU_MISC_BACKOFF 0x0000003f /* Mask for backoff threshold */ +#define AR5K_DCU_MISC_ETS_RTS_POL 0x00000040 /* End of transmission series + station RTS/data failure count + reset policy (?) */ +#define AR5K_DCU_MISC_ETS_CW_POL 0x00000080 /* End of transmission series + CW reset policy */ +#define AR5K_DCU_MISC_FRAG_WAIT 0x00000100 /* Wait for next fragment */ +#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */ +#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */ +#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff */ +#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */ +#define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */ +#define AR5K_DCU_MISC_VIRTCOL_NORMAL 0 +#define AR5K_DCU_MISC_VIRTCOL_IGNORE 1 +#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Enable Beacon use */ +#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */ +#define AR5K_DCU_MISC_ARBLOCK_CTL_S 17 +#define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */ +#define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */ +#define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */ +#define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 /* Ignore Arbiter lockout */ +#define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment */ +#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff */ +#define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision cw policy */ +#define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 /* Blown IFS policy (?) */ +#define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */ +#define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q) + +/* + * DCU frame sequence number registers + */ +#define AR5K_DCU_SEQNUM_BASE 0x1140 +#define AR5K_DCU_SEQNUM_M 0x00000fff +#define AR5K_QUEUE_DCU_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q) + +/* + * DCU global IFS SIFS register + */ +#define AR5K_DCU_GBL_IFS_SIFS 0x1030 +#define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff + +/* + * DCU global IFS slot interval register + */ +#define AR5K_DCU_GBL_IFS_SLOT 0x1070 +#define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff + +/* + * DCU global IFS EIFS register + */ +#define AR5K_DCU_GBL_IFS_EIFS 0x10b0 +#define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff + +/* + * DCU global IFS misc register + * + * LFSR stands for Linear Feedback Shift Register + * and it's used for generating pseudo-random + * number sequences. + * + * (If i understand corectly, random numbers are + * used for idle sensing -multiplied with cwmin/max etc-) + */ +#define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */ +#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 /* LFSR Slice Select */ +#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode */ +#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */ +#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */ +#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S 10 +#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* DCU Arbiter delay mask */ +#define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000 /* SIFS cnt reset policy (?) */ +#define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000 /* AIFS cnt reset policy (?) */ +#define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000 /* Disable random LFSR slice */ + +/* + * DCU frame prefetch control register + */ +#define AR5K_DCU_FP 0x1230 /* Register Address */ +#define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 /* Enable non-burst prefetch on DCU (?) */ +#define AR5K_DCU_FP_NOBURST_EN 0x00000010 /* Enable non-burst prefetch (?) */ +#define AR5K_DCU_FP_BURST_DCU_EN 0x00000020 /* Enable burst prefetch on DCU (?) */ + +/* + * DCU transmit pause control/status register + */ +#define AR5K_DCU_TXP 0x1270 /* Register Address */ +#define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask */ +#define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status */ + +/* + * DCU transmit filter table 0 (32 entries) + * each entry contains a 32bit slice of the + * 128bit tx filter for each DCU (4 slices per DCU) + */ +#define AR5K_DCU_TX_FILTER_0_BASE 0x1038 +#define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64)) + +/* + * DCU transmit filter table 1 (16 entries) + */ +#define AR5K_DCU_TX_FILTER_1_BASE 0x103c +#define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64)) + +/* + * DCU clear transmit filter register + */ +#define AR5K_DCU_TX_FILTER_CLR 0x143c + +/* + * DCU set transmit filter register + */ +#define AR5K_DCU_TX_FILTER_SET 0x147c + +/* + * Reset control register + */ +#define AR5K_RESET_CTL 0x4000 /* Register Address */ +#define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */ +#define AR5K_RESET_CTL_DMA 0x00000002 /* DMA (Rx/Tx) reset [5210] */ +#define AR5K_RESET_CTL_BASEBAND 0x00000002 /* Baseband reset [5211+] */ +#define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */ +#define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */ +#define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */ + +/* + * Sleep control register + */ +#define AR5K_SLEEP_CTL 0x4004 /* Register Address */ +#define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /* Sleep duration mask */ +#define AR5K_SLEEP_CTL_SLDUR_S 0 +#define AR5K_SLEEP_CTL_SLE 0x00030000 /* Sleep enable mask */ +#define AR5K_SLEEP_CTL_SLE_S 16 +#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */ +#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */ +#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 /* Normal sleep policy */ +#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */ +#define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000 /* Sleep duration timing policy */ +#define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000 /* Sleep duration write policy */ +#define AR5K_SLEEP_CTL_SLE_POL 0x00100000 /* Sleep policy mode */ + +/* + * Interrupt pending register + */ +#define AR5K_INTPEND 0x4008 +#define AR5K_INTPEND_M 0x00000001 + +/* + * Sleep force register + */ +#define AR5K_SFR 0x400c +#define AR5K_SFR_EN 0x00000001 + +/* + * PCI configuration register + * TODO: Fix LED stuff + */ +#define AR5K_PCICFG 0x4010 /* Register Address */ +#define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */ +#define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep clock */ +#define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */ +#define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */ +#define AR5K_PCICFG_EESIZE_S 3 +#define AR5K_PCICFG_EESIZE_4K 0 /* 4K */ +#define AR5K_PCICFG_EESIZE_8K 1 /* 8K */ +#define AR5K_PCICFG_EESIZE_16K 2 /* 16K */ +#define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size [5211+] */ +#define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */ +#define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */ +#define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */ +#define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */ +#define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */ +#define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix */ +#define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep */ +#define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */ +#define AR5K_PCICFG_RETRY_FIX 0x00001000 /* Enable pci core retry fix */ +#define AR5K_PCICFG_SL_INPEN 0x00002000 /* Sleep even whith pending interrupts*/ +#define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */ +#define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */ +#define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */ +#define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */ +#define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */ +#define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */ +#define AR5K_PCICFG_LEDBLINK 0x00700000 /* Led blink rate */ +#define AR5K_PCICFG_LEDBLINK_S 20 +#define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slowest led blink rate [5211+] */ +#define AR5K_PCICFG_LEDSTATE \ + (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ + AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) +#define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 /* Sleep clock rate */ +#define AR5K_PCICFG_SLEEP_CLOCK_RATE_S 24 + +/* + * "General Purpose Input/Output" (GPIO) control register + * + * I'm not sure about this but after looking at the code + * for all chipsets here is what i got. + * + * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits) + * Mode 0 -> always input + * Mode 1 -> output when GPIODO for this GPIO is set to 0 + * Mode 2 -> output when GPIODO for this GPIO is set to 1 + * Mode 3 -> always output + * + * For more infos check out get_gpio/set_gpio and + * set_gpio_input/set_gpio_output functs. + * For more infos on gpio interrupt check out set_gpio_intr. + */ +#define AR5K_NUM_GPIO 6 + +#define AR5K_GPIOCR 0x4014 /* Register Address */ +#define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */ +#define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is low */ +#define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is high */ +#define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */ +#define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /* Mode 1 for pin n */ +#define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /* Mode 2 for pin n */ +#define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2)) /* Mode 3 for pin n */ +#define AR5K_GPIOCR_INT_SEL(n) ((n) << 12) /* Interrupt for GPIO pin n */ + +/* + * "General Purpose Input/Output" (GPIO) data output register + */ +#define AR5K_GPIODO 0x4018 + +/* + * "General Purpose Input/Output" (GPIO) data input register + */ +#define AR5K_GPIODI 0x401c +#define AR5K_GPIODI_M 0x0000002f + +/* + * Silicon revision register + */ +#define AR5K_SREV 0x4020 /* Register Address */ +#define AR5K_SREV_REV 0x0000000f /* Mask for revision */ +#define AR5K_SREV_REV_S 0 +#define AR5K_SREV_VER 0x000000ff /* Mask for version */ +#define AR5K_SREV_VER_S 4 + +/* + * TXE write posting register + */ +#define AR5K_TXEPOST 0x4028 + +/* + * QCU sleep mask + */ +#define AR5K_QCU_SLEEP_MASK 0x402c + +/* 0x4068 is compression buffer configuration + * register on 5414 and pm configuration register + * on 5424 and newer pci-e chips. */ + +/* + * Compression buffer configuration + * register (enable/disable) [5414] + */ +#define AR5K_5414_CBCFG 0x4068 +#define AR5K_5414_CBCFG_BUF_DIS 0x10 /* Disable buffer */ + +/* + * PCI-E Power managment configuration + * and status register [5424+] + */ +#define AR5K_PCIE_PM_CTL 0x4068 /* Register address */ +/* Only 5424 */ +#define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001 /* enable PCIe core enter L1 + when d2_sleep_en is asserted */ +#define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002 /* Clear L0 and L0S counters */ +#define AR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004 /* Start L0 nd L0S counters */ +#define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008 /* Enable reset when link goes + down */ +/* Wake On Wireless */ +#define AR5K_PCIE_PM_CTL_PME_EN 0x00000010 /* PME Enable */ +#define AR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020 /* Aux power detect */ +#define AR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040 /* Clear PME */ +#define AR5K_PCIE_PM_CTL_PSM_D0 0x00000080 +#define AR5K_PCIE_PM_CTL_PSM_D1 0x00000100 +#define AR5K_PCIE_PM_CTL_PSM_D2 0x00000200 +#define AR5K_PCIE_PM_CTL_PSM_D3 0x00000400 + +/* + * PCI-E Workaround enable register + */ +#define AR5K_PCIE_WAEN 0x407c + +/* + * PCI-E Serializer/Desirializer + * registers + */ +#define AR5K_PCIE_SERDES 0x4080 +#define AR5K_PCIE_SERDES_RESET 0x4084 + +/*====EEPROM REGISTERS====*/ + +/* + * EEPROM access registers + * + * Here we got a difference between 5210/5211-12 + * read data register for 5210 is at 0x6800 and + * status register is at 0x6c00. There is also + * no eeprom command register on 5210 and the + * offsets are different. + * + * To read eeprom data for a specific offset: + * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) + * read AR5K_EEPROM_BASE +(4 * offset) + * check the eeprom status register + * and read eeprom data register. + * + * 5211 - write offset to AR5K_EEPROM_BASE + * 5212 write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD + * check the eeprom status register + * and read eeprom data register. + * + * To write eeprom data for a specific offset: + * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) + * write data to AR5K_EEPROM_BASE +(4 * offset) + * check the eeprom status register + * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD + * 5212 write offset to AR5K_EEPROM_BASE + * write data to data register + * write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD + * check the eeprom status register + * + * For more infos check eeprom_* functs and the ar5k.c + * file posted in madwifi-devel mailing list. + * http://sourceforge.net/mailarchive/message.php?msg_id=8966525 + * + */ +#define AR5K_EEPROM_BASE 0x6000 + +/* + * EEPROM data register + */ +#define AR5K_EEPROM_DATA_5211 0x6004 +#define AR5K_EEPROM_DATA_5210 0x6800 +#define AR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \ + AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211) + +/* + * EEPROM command register + */ +#define AR5K_EEPROM_CMD 0x6008 /* Register Addres */ +#define AR5K_EEPROM_CMD_READ 0x00000001 /* EEPROM read */ +#define AR5K_EEPROM_CMD_WRITE 0x00000002 /* EEPROM write */ +#define AR5K_EEPROM_CMD_RESET 0x00000004 /* EEPROM reset */ + +/* + * EEPROM status register + */ +#define AR5K_EEPROM_STAT_5210 0x6c00 /* Register Address [5210] */ +#define AR5K_EEPROM_STAT_5211 0x600c /* Register Address [5211+] */ +#define AR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \ + AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211) +#define AR5K_EEPROM_STAT_RDERR 0x00000001 /* EEPROM read failed */ +#define AR5K_EEPROM_STAT_RDDONE 0x00000002 /* EEPROM read successful */ +#define AR5K_EEPROM_STAT_WRERR 0x00000004 /* EEPROM write failed */ +#define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */ + +/* + * EEPROM config register + */ +#define AR5K_EEPROM_CFG 0x6010 /* Register Addres */ +#define AR5K_EEPROM_CFG_SIZE 0x00000003 /* Size determination override */ +#define AR5K_EEPROM_CFG_SIZE_AUTO 0 +#define AR5K_EEPROM_CFG_SIZE_4KBIT 1 +#define AR5K_EEPROM_CFG_SIZE_8KBIT 2 +#define AR5K_EEPROM_CFG_SIZE_16KBIT 3 +#define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 /* Disable write wait */ +#define AR5K_EEPROM_CFG_CLK_RATE 0x00000018 /* Clock rate */ +#define AR5K_EEPROM_CFG_CLK_RATE_S 3 +#define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 0 +#define AR5K_EEPROM_CFG_CLK_RATE_312KHZ 1 +#define AR5K_EEPROM_CFG_CLK_RATE_625KHZ 2 +#define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 /* Protection key */ +#define AR5K_EEPROM_CFG_PROT_KEY_S 8 +#define AR5K_EEPROM_CFG_LIND_EN 0x01000000 /* Enable length indicator (?) */ + + +/* + * TODO: Wake On Wireless registers + * Range 0x7000 - 0x7ce0 + */ + +/* + * Protocol Control Unit (PCU) registers + */ +/* + * Used for checking initial register writes + * during channel reset (see reset func) + */ +#define AR5K_PCU_MIN 0x8000 +#define AR5K_PCU_MAX 0x8fff + +/* + * First station id register (Lower 32 bits of MAC address) + */ +#define AR5K_STA_ID0 0x8000 +#define AR5K_STA_ID0_ARRD_L32 0xffffffff + +/* + * Second station id register (Upper 16 bits of MAC address + PCU settings) + */ +#define AR5K_STA_ID1 0x8004 /* Register Address */ +#define AR5K_STA_ID1_ADDR_U16 0x0000ffff /* Upper 16 bits of MAC addres */ +#define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */ +#define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */ +#define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting */ +#define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */ +#define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */ +#define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */ +#define AR5K_STA_ID1_PCF_5210 0x00200000 /* Enable PCF on [5210]*/ +#define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \ + AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211) +#define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */ +#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */ +#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS */ +#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS */ +#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate for ACK/CTS [5211+] */ +#define AR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000 /* Use def. antenna for self generated frames */ +#define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 /* Enable MIC */ +#define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000 /* Look up key when key id != 0 */ +#define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 /* Preserve sequence number */ +#define AR5K_STA_ID1_CBCIV_ENDIAN 0x40000000 /* ??? */ +#define AR5K_STA_ID1_KEYSRCH_MCAST 0x80000000 /* Do key cache search for mcast frames */ + +/* + * First BSSID register (MAC address, lower 32bits) + */ +#define AR5K_BSS_ID0 0x8008 + +/* + * Second BSSID register (MAC address in upper 16 bits) + * + * AID: Association ID + */ +#define AR5K_BSS_ID1 0x800c +#define AR5K_BSS_ID1_AID 0xffff0000 +#define AR5K_BSS_ID1_AID_S 16 + +/* + * Backoff slot time register + */ +#define AR5K_SLOT_TIME 0x8010 + +/* + * ACK/CTS timeout register + */ +#define AR5K_TIME_OUT 0x8014 /* Register Address */ +#define AR5K_TIME_OUT_ACK 0x00001fff /* ACK timeout mask */ +#define AR5K_TIME_OUT_ACK_S 0 +#define AR5K_TIME_OUT_CTS 0x1fff0000 /* CTS timeout mask */ +#define AR5K_TIME_OUT_CTS_S 16 + +/* + * RSSI threshold register + */ +#define AR5K_RSSI_THR 0x8018 /* Register Address */ +#define AR5K_RSSI_THR_M 0x000000ff /* Mask for RSSI threshold [5211+] */ +#define AR5K_RSSI_THR_BMISS_5210 0x00000700 /* Mask for Beacon Missed threshold [5210] */ +#define AR5K_RSSI_THR_BMISS_5210_S 8 +#define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /* Mask for Beacon Missed threshold [5211+] */ +#define AR5K_RSSI_THR_BMISS_5211_S 8 +#define AR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \ + AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211) +#define AR5K_RSSI_THR_BMISS_S 8 + +/* + * 5210 has more PCU registers because there is no QCU/DCU + * so queue parameters are set here, this way a lot common + * registers have different address for 5210. To make things + * easier we define a macro based on ah->ah_version for common + * registers with different addresses and common flags. + */ + +/* + * Retry limit register + * + * Retry limit register for 5210 (no QCU/DCU so it's done in PCU) + */ +#define AR5K_NODCU_RETRY_LMT 0x801c /* Register Address */ +#define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ +#define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0 +#define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */ +#define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4 +#define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask */ +#define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8 +#define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask */ +#define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14 +#define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /* Minimum contention window mask */ +#define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20 + +/* + * Transmit latency register + */ +#define AR5K_USEC_5210 0x8020 /* Register Address [5210] */ +#define AR5K_USEC_5211 0x801c /* Register Address [5211+] */ +#define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \ + AR5K_USEC_5210 : AR5K_USEC_5211) +#define AR5K_USEC_1 0x0000007f /* clock cycles for 1us */ +#define AR5K_USEC_1_S 0 +#define AR5K_USEC_32 0x00003f80 /* clock cycles for 1us while on 32Mhz clock */ +#define AR5K_USEC_32_S 7 +#define AR5K_USEC_TX_LATENCY_5211 0x007fc000 +#define AR5K_USEC_TX_LATENCY_5211_S 14 +#define AR5K_USEC_RX_LATENCY_5211 0x1f800000 +#define AR5K_USEC_RX_LATENCY_5211_S 23 +#define AR5K_USEC_TX_LATENCY_5210 0x000fc000 /* also for 5311 */ +#define AR5K_USEC_TX_LATENCY_5210_S 14 +#define AR5K_USEC_RX_LATENCY_5210 0x03f00000 /* also for 5311 */ +#define AR5K_USEC_RX_LATENCY_5210_S 20 + +/* + * PCU beacon control register + */ +#define AR5K_BEACON_5210 0x8024 /*Register Address [5210] */ +#define AR5K_BEACON_5211 0x8020 /*Register Address [5211+] */ +#define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \ + AR5K_BEACON_5210 : AR5K_BEACON_5211) +#define AR5K_BEACON_PERIOD 0x0000ffff /* Mask for beacon period */ +#define AR5K_BEACON_PERIOD_S 0 +#define AR5K_BEACON_TIM 0x007f0000 /* Mask for TIM offset */ +#define AR5K_BEACON_TIM_S 16 +#define AR5K_BEACON_ENABLE 0x00800000 /* Enable beacons */ +#define AR5K_BEACON_RESET_TSF 0x01000000 /* Force TSF reset */ + +/* + * CFP period register + */ +#define AR5K_CFP_PERIOD_5210 0x8028 +#define AR5K_CFP_PERIOD_5211 0x8024 +#define AR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \ + AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211) + +/* + * Next beacon time register + */ +#define AR5K_TIMER0_5210 0x802c +#define AR5K_TIMER0_5211 0x8028 +#define AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \ + AR5K_TIMER0_5210 : AR5K_TIMER0_5211) + +/* + * Next DMA beacon alert register + */ +#define AR5K_TIMER1_5210 0x8030 +#define AR5K_TIMER1_5211 0x802c +#define AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \ + AR5K_TIMER1_5210 : AR5K_TIMER1_5211) + +/* + * Next software beacon alert register + */ +#define AR5K_TIMER2_5210 0x8034 +#define AR5K_TIMER2_5211 0x8030 +#define AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \ + AR5K_TIMER2_5210 : AR5K_TIMER2_5211) + +/* + * Next ATIM window time register + */ +#define AR5K_TIMER3_5210 0x8038 +#define AR5K_TIMER3_5211 0x8034 +#define AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \ + AR5K_TIMER3_5210 : AR5K_TIMER3_5211) + + +/* + * 5210 First inter frame spacing register (IFS) + */ +#define AR5K_IFS0 0x8040 +#define AR5K_IFS0_SIFS 0x000007ff +#define AR5K_IFS0_SIFS_S 0 +#define AR5K_IFS0_DIFS 0x007ff800 +#define AR5K_IFS0_DIFS_S 11 + +/* + * 5210 Second inter frame spacing register (IFS) + */ +#define AR5K_IFS1 0x8044 +#define AR5K_IFS1_PIFS 0x00000fff +#define AR5K_IFS1_PIFS_S 0 +#define AR5K_IFS1_EIFS 0x03fff000 +#define AR5K_IFS1_EIFS_S 12 +#define AR5K_IFS1_CS_EN 0x04000000 + + +/* + * CFP duration register + */ +#define AR5K_CFP_DUR_5210 0x8048 +#define AR5K_CFP_DUR_5211 0x8038 +#define AR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \ + AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211) + +/* + * Receive filter register + */ +#define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */ +#define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */ +#define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \ + AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) +#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ +#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ +#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ +#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ +#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ +#define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ +#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame [5212+] */ +#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests [5212+] */ +#define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors [5212+] */ +#define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */ +#define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /* [5211] */ +#define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /* [5211] */ +#define AR5K_RX_FILTER_PHYERR \ + ((ah->ah_version == AR5K_AR5211 ? \ + AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212)) +#define AR5K_RX_FILTER_RADARERR \ + ((ah->ah_version == AR5K_AR5211 ? \ + AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212)) + +/* + * Multicast filter register (lower 32 bits) + */ +#define AR5K_MCAST_FILTER0_5210 0x8050 +#define AR5K_MCAST_FILTER0_5211 0x8040 +#define AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \ + AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211) + +/* + * Multicast filter register (higher 16 bits) + */ +#define AR5K_MCAST_FILTER1_5210 0x8054 +#define AR5K_MCAST_FILTER1_5211 0x8044 +#define AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \ + AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211) + + +/* + * Transmit mask register (lower 32 bits) [5210] + */ +#define AR5K_TX_MASK0 0x8058 + +/* + * Transmit mask register (higher 16 bits) [5210] + */ +#define AR5K_TX_MASK1 0x805c + +/* + * Clear transmit mask [5210] + */ +#define AR5K_CLR_TMASK 0x8060 + +/* + * Trigger level register (before transmission) [5210] + */ +#define AR5K_TRIG_LVL 0x8064 + + +/* + * PCU control register + * + * Only DIS_RX is used in the code, the rest i guess are + * for tweaking/diagnostics. + */ +#define AR5K_DIAG_SW_5210 0x8068 /* Register Address [5210] */ +#define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */ +#define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) +#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 /* Disable ACKs if WEP key is invalid */ +#define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs */ +#define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs */ +#define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable encryption */ +#define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable decryption */ +#define AR5K_DIAG_SW_DIS_TX 0x00000020 /* Disable transmit [5210] */ +#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable recieve */ +#define AR5K_DIAG_SW_DIS_RX_5211 0x00000020 +#define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211) +#define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /* Loopback (i guess it goes with DIS_TX) [5210] */ +#define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 +#define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) +#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 /* Corrupted FCS */ +#define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 +#define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) +#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 /* Dump channel info */ +#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 +#define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) +#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 /* Enable fixed scrambler seed */ +#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 +#define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) +#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */ +#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */ +#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask */ +#define AR5K_DIAG_SW_SCRAM_SEED_S 10 +#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */ +#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 +#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 /* Accept frames of non-zero protocol number */ +#define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \ + AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) +#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 /* Observation point select (?) */ +#define AR5K_DIAG_SW_OBSPT_S 18 +#define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x0010000 /* Force RX Clear high */ +#define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x0020000 /* Ignore virtual carrier sense */ +#define AR5K_DIAG_SW_CHANEL_IDLE_HIGH 0x0040000 /* Force channel idle high */ +#define AR5K_DIAG_SW_PHEAR_ME 0x0080000 /* ??? */ + +/* + * TSF (clock) register (lower 32 bits) + */ +#define AR5K_TSF_L32_5210 0x806c +#define AR5K_TSF_L32_5211 0x804c +#define AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \ + AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211) + +/* + * TSF (clock) register (higher 32 bits) + */ +#define AR5K_TSF_U32_5210 0x8070 +#define AR5K_TSF_U32_5211 0x8050 +#define AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \ + AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211) + +/* + * Last beacon timestamp register (Read Only) + */ +#define AR5K_LAST_TSTP 0x8080 + +/* + * ADDAC test register [5211+] + */ +#define AR5K_ADDAC_TEST 0x8054 /* Register Address */ +#define AR5K_ADDAC_TEST_TXCONT 0x00000001 /* Test continuous tx */ +#define AR5K_ADDAC_TEST_TST_MODE 0x00000002 /* Test mode */ +#define AR5K_ADDAC_TEST_LOOP_EN 0x00000004 /* Enable loop */ +#define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008 /* Loop length (field) */ +#define AR5K_ADDAC_TEST_USE_U8 0x00004000 /* Use upper 8 bits */ +#define AR5K_ADDAC_TEST_MSB 0x00008000 /* State of MSB */ +#define AR5K_ADDAC_TEST_TRIG_SEL 0x00010000 /* Trigger select */ +#define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000 /* Trigger polarity */ +#define AR5K_ADDAC_TEST_RXCONT 0x00040000 /* Continuous capture */ +#define AR5K_ADDAC_TEST_CAPTURE 0x00080000 /* Begin capture */ +#define AR5K_ADDAC_TEST_TST_ARM 0x00100000 /* ARM rx buffer for capture */ + +/* + * Default antenna register [5211+] + */ +#define AR5K_DEFAULT_ANTENNA 0x8058 + +/* + * Frame control QoS mask register (?) [5211+] + * (FC_QOS_MASK) + */ +#define AR5K_FRAME_CTL_QOSM 0x805c + +/* + * Seq mask register (?) [5211+] + */ +#define AR5K_SEQ_MASK 0x8060 + +/* + * Retry count register [5210] + */ +#define AR5K_RETRY_CNT 0x8084 /* Register Address [5210] */ +#define AR5K_RETRY_CNT_SSH 0x0000003f /* Station short retry count (?) */ +#define AR5K_RETRY_CNT_SLG 0x00000fc0 /* Station long retry count (?) */ + +/* + * Back-off status register [5210] + */ +#define AR5K_BACKOFF 0x8088 /* Register Address [5210] */ +#define AR5K_BACKOFF_CW 0x000003ff /* Backoff Contention Window (?) */ +#define AR5K_BACKOFF_CNT 0x03ff0000 /* Backoff count (?) */ + + + +/* + * NAV register (current) + */ +#define AR5K_NAV_5210 0x808c +#define AR5K_NAV_5211 0x8084 +#define AR5K_NAV (ah->ah_version == AR5K_AR5210 ? \ + AR5K_NAV_5210 : AR5K_NAV_5211) + +/* + * RTS success register + */ +#define AR5K_RTS_OK_5210 0x8090 +#define AR5K_RTS_OK_5211 0x8088 +#define AR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \ + AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211) + +/* + * RTS failure register + */ +#define AR5K_RTS_FAIL_5210 0x8094 +#define AR5K_RTS_FAIL_5211 0x808c +#define AR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \ + AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211) + +/* + * ACK failure register + */ +#define AR5K_ACK_FAIL_5210 0x8098 +#define AR5K_ACK_FAIL_5211 0x8090 +#define AR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \ + AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211) + +/* + * FCS failure register + */ +#define AR5K_FCS_FAIL_5210 0x809c +#define AR5K_FCS_FAIL_5211 0x8094 +#define AR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \ + AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211) + +/* + * Beacon count register + */ +#define AR5K_BEACON_CNT_5210 0x80a0 +#define AR5K_BEACON_CNT_5211 0x8098 +#define AR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \ + AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211) + + +/*===5212 Specific PCU registers===*/ + +/* + * Transmit power control register + */ +#define AR5K_TPC 0x80e8 +#define AR5K_TPC_ACK 0x0000003f /* ack frames */ +#define AR5K_TPC_ACK_S 0 +#define AR5K_TPC_CTS 0x00003f00 /* cts frames */ +#define AR5K_TPC_CTS_S 8 +#define AR5K_TPC_CHIRP 0x003f0000 /* chirp frames */ +#define AR5K_TPC_CHIRP_S 16 +#define AR5K_TPC_DOPPLER 0x0f000000 /* doppler chirp span */ +#define AR5K_TPC_DOPPLER_S 24 + +/* + * XR (eXtended Range) mode register + */ +#define AR5K_XRMODE 0x80c0 /* Register Address */ +#define AR5K_XRMODE_POLL_TYPE_M 0x0000003f /* Mask for Poll type (?) */ +#define AR5K_XRMODE_POLL_TYPE_S 0 +#define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c /* Mask for Poll subtype (?) */ +#define AR5K_XRMODE_POLL_SUBTYPE_S 2 +#define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080 /* Wait for poll */ +#define AR5K_XRMODE_SIFS_DELAY 0x000fff00 /* Mask for SIFS delay */ +#define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000 /* Mask for frame hold (?) */ +#define AR5K_XRMODE_FRAME_HOLD_S 20 + +/* + * XR delay register + */ +#define AR5K_XRDELAY 0x80c4 /* Register Address */ +#define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff /* Mask for slot delay */ +#define AR5K_XRDELAY_SLOT_DELAY_S 0 +#define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 /* Mask for CHIRP data delay */ +#define AR5K_XRDELAY_CHIRP_DELAY_S 16 + +/* + * XR timeout register + */ +#define AR5K_XRTIMEOUT 0x80c8 /* Register Address */ +#define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff /* Mask for CHIRP timeout */ +#define AR5K_XRTIMEOUT_CHIRP_S 0 +#define AR5K_XRTIMEOUT_POLL_M 0xffff0000 /* Mask for Poll timeout */ +#define AR5K_XRTIMEOUT_POLL_S 16 + +/* + * XR chirp register + */ +#define AR5K_XRCHIRP 0x80cc /* Register Address */ +#define AR5K_XRCHIRP_SEND 0x00000001 /* Send CHIRP */ +#define AR5K_XRCHIRP_GAP 0xffff0000 /* Mask for CHIRP gap (?) */ + +/* + * XR stomp register + */ +#define AR5K_XRSTOMP 0x80d0 /* Register Address */ +#define AR5K_XRSTOMP_TX 0x00000001 /* Stomp Tx (?) */ +#define AR5K_XRSTOMP_RX 0x00000002 /* Stomp Rx (?) */ +#define AR5K_XRSTOMP_TX_RSSI 0x00000004 /* Stomp Tx RSSI (?) */ +#define AR5K_XRSTOMP_TX_BSSID 0x00000008 /* Stomp Tx BSSID (?) */ +#define AR5K_XRSTOMP_DATA 0x00000010 /* Stomp data (?)*/ +#define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00 /* Mask for XR RSSI threshold */ + +/* + * First enhanced sleep register + */ +#define AR5K_SLEEP0 0x80d4 /* Register Address */ +#define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff /* Mask for next DTIM (?) */ +#define AR5K_SLEEP0_NEXT_DTIM_S 0 +#define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 /* Assume DTIM */ +#define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 /* Enable enchanced sleep control */ +#define AR5K_SLEEP0_CABTO 0xff000000 /* Mask for CAB Time Out */ +#define AR5K_SLEEP0_CABTO_S 24 + +/* + * Second enhanced sleep register + */ +#define AR5K_SLEEP1 0x80d8 /* Register Address */ +#define AR5K_SLEEP1_NEXT_TIM 0x0007ffff /* Mask for next TIM (?) */ +#define AR5K_SLEEP1_NEXT_TIM_S 0 +#define AR5K_SLEEP1_BEACON_TO 0xff000000 /* Mask for Beacon Time Out */ +#define AR5K_SLEEP1_BEACON_TO_S 24 + +/* + * Third enhanced sleep register + */ +#define AR5K_SLEEP2 0x80dc /* Register Address */ +#define AR5K_SLEEP2_TIM_PER 0x0000ffff /* Mask for TIM period (?) */ +#define AR5K_SLEEP2_TIM_PER_S 0 +#define AR5K_SLEEP2_DTIM_PER 0xffff0000 /* Mask for DTIM period (?) */ +#define AR5K_SLEEP2_DTIM_PER_S 16 + +/* + * BSSID mask registers + */ +#define AR5K_BSS_IDM0 0x80e0 /* Upper bits */ +#define AR5K_BSS_IDM1 0x80e4 /* Lower bits */ + +/* + * TX power control (TPC) register + * + * XXX: PCDAC steps (0.5dbm) or DBM ? + * + */ +#define AR5K_TXPC 0x80e8 /* Register Address */ +#define AR5K_TXPC_ACK_M 0x0000003f /* ACK tx power */ +#define AR5K_TXPC_ACK_S 0 +#define AR5K_TXPC_CTS_M 0x00003f00 /* CTS tx power */ +#define AR5K_TXPC_CTS_S 8 +#define AR5K_TXPC_CHIRP_M 0x003f0000 /* CHIRP tx power */ +#define AR5K_TXPC_CHIRP_S 16 +#define AR5K_TXPC_DOPPLER 0x0f000000 /* Doppler chirp span (?) */ +#define AR5K_TXPC_DOPPLER_S 24 + +/* + * Profile count registers + */ +#define AR5K_PROFCNT_TX 0x80ec /* Tx count */ +#define AR5K_PROFCNT_RX 0x80f0 /* Rx count */ +#define AR5K_PROFCNT_RXCLR 0x80f4 /* Clear Rx count */ +#define AR5K_PROFCNT_CYCLE 0x80f8 /* Cycle count (?) */ + +/* + * Quiet period control registers + */ +#define AR5K_QUIET_CTL1 0x80fc /* Register Address */ +#define AR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff /* Next quiet period TSF (TU) */ +#define AR5K_QUIET_CTL1_NEXT_QT_TSF_S 0 +#define AR5K_QUIET_CTL1_QT_EN 0x00010000 /* Enable quiet period */ +#define AR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000 /* Send ACK/CTS during quiet period */ + +#define AR5K_QUIET_CTL2 0x8100 /* Register Address */ +#define AR5K_QUIET_CTL2_QT_PER 0x0000ffff /* Mask for quiet period periodicity */ +#define AR5K_QUIET_CTL2_QT_PER_S 0 +#define AR5K_QUIET_CTL2_QT_DUR 0xffff0000 /* Mask for quiet period duration */ +#define AR5K_QUIET_CTL2_QT_DUR_S 16 + +/* + * TSF parameter register + */ +#define AR5K_TSF_PARM 0x8104 /* Register Address */ +#define AR5K_TSF_PARM_INC 0x000000ff /* Mask for TSF increment */ +#define AR5K_TSF_PARM_INC_S 0 + +/* + * QoS NOACK policy + */ +#define AR5K_QOS_NOACK 0x8108 /* Register Address */ +#define AR5K_QOS_NOACK_2BIT_VALUES 0x0000000f /* ??? */ +#define AR5K_QOS_NOACK_2BIT_VALUES_S 0 +#define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070 /* ??? */ +#define AR5K_QOS_NOACK_BIT_OFFSET_S 4 +#define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180 /* ??? */ +#define AR5K_QOS_NOACK_BYTE_OFFSET_S 7 + +/* + * PHY error filter register + */ +#define AR5K_PHY_ERR_FIL 0x810c +#define AR5K_PHY_ERR_FIL_RADAR 0x00000020 /* Radar signal */ +#define AR5K_PHY_ERR_FIL_OFDM 0x00020000 /* OFDM false detect (ANI) */ +#define AR5K_PHY_ERR_FIL_CCK 0x02000000 /* CCK false detect (ANI) */ + +/* + * XR latency register + */ +#define AR5K_XRLAT_TX 0x8110 + +/* + * ACK SIFS register + */ +#define AR5K_ACKSIFS 0x8114 /* Register Address */ +#define AR5K_ACKSIFS_INC 0x00000000 /* ACK SIFS Increment (field) */ + +/* + * MIC QoS control register (?) + */ +#define AR5K_MIC_QOS_CTL 0x8118 /* Register Address */ +#define AR5K_MIC_QOS_CTL_OFF(_n) (1 << (_n * 2)) +#define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000 /* Enable MIC QoS */ + +/* + * MIC QoS select register (?) + */ +#define AR5K_MIC_QOS_SEL 0x811c +#define AR5K_MIC_QOS_SEL_OFF(_n) (1 << (_n * 4)) + +/* + * Misc mode control register (?) + */ +#define AR5K_MISC_MODE 0x8120 /* Register Address */ +#define AR5K_MISC_MODE_FBSSID_MATCH 0x00000001 /* Force BSSID match */ +#define AR5K_MISC_MODE_ACKSIFS_MEM 0x00000002 /* ACK SIFS memory (?) */ +#define AR5K_MISC_MODE_COMBINED_MIC 0x00000004 /* use rx/tx MIC key */ +/* more bits */ + +/* + * OFDM Filter counter + */ +#define AR5K_OFDM_FIL_CNT 0x8124 + +/* + * CCK Filter counter + */ +#define AR5K_CCK_FIL_CNT 0x8128 + +/* + * PHY Error Counters (?) + */ +#define AR5K_PHYERR_CNT1 0x812c +#define AR5K_PHYERR_CNT1_MASK 0x8130 + +#define AR5K_PHYERR_CNT2 0x8134 +#define AR5K_PHYERR_CNT2_MASK 0x8138 + +/* + * TSF Threshold register (?) + */ +#define AR5K_TSF_THRES 0x813c + +/* + * TODO: Wake On Wireless registers + * Range: 0x8147 - 0x818c + */ + +/* + * Rate -> ACK SIFS mapping table (32 entries) + */ +#define AR5K_RATE_ACKSIFS_BASE 0x8680 /* Register Address */ +#define AR5K_RATE_ACKSIFS(_n) (AR5K_RATE_ACKSIFS_BSE + ((_n) << 2)) +#define AR5K_RATE_ACKSIFS_NORMAL 0x00000001 /* Normal SIFS (field) */ +#define AR5K_RATE_ACKSIFS_TURBO 0x00000400 /* Turbo SIFS (field) */ + +/* + * Rate -> duration mapping table (32 entries) + */ +#define AR5K_RATE_DUR_BASE 0x8700 +#define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2)) + +/* + * Rate -> db mapping table + * (8 entries, each one has 4 8bit fields) + */ +#define AR5K_RATE2DB_BASE 0x87c0 +#define AR5K_RATE2DB(_n) (AR5K_RATE2DB_BASE + ((_n) << 2)) + +/* + * db -> Rate mapping table + * (8 entries, each one has 4 8bit fields) + */ +#define AR5K_DB2RATE_BASE 0x87e0 +#define AR5K_DB2RATE(_n) (AR5K_DB2RATE_BASE + ((_n) << 2)) + +/*===5212 end===*/ + +/* + * Key table (WEP) register + */ +#define AR5K_KEYTABLE_0_5210 0x9000 +#define AR5K_KEYTABLE_0_5211 0x8800 +#define AR5K_KEYTABLE_5210(_n) (AR5K_KEYTABLE_0_5210 + ((_n) << 5)) +#define AR5K_KEYTABLE_5211(_n) (AR5K_KEYTABLE_0_5211 + ((_n) << 5)) +#define AR5K_KEYTABLE(_n) (ah->ah_version == AR5K_AR5210 ? \ + AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n)) +#define AR5K_KEYTABLE_OFF(_n, x) (AR5K_KEYTABLE(_n) + (x << 2)) +#define AR5K_KEYTABLE_TYPE(_n) AR5K_KEYTABLE_OFF(_n, 5) +#define AR5K_KEYTABLE_TYPE_40 0x00000000 +#define AR5K_KEYTABLE_TYPE_104 0x00000001 +#define AR5K_KEYTABLE_TYPE_128 0x00000003 +#define AR5K_KEYTABLE_TYPE_TKIP 0x00000004 /* [5212+] */ +#define AR5K_KEYTABLE_TYPE_AES 0x00000005 /* [5211+] */ +#define AR5K_KEYTABLE_TYPE_CCM 0x00000006 /* [5212+] */ +#define AR5K_KEYTABLE_TYPE_NULL 0x00000007 /* [5211+] */ +#define AR5K_KEYTABLE_ANTENNA 0x00000008 /* [5212+] */ +#define AR5K_KEYTABLE_MAC0(_n) AR5K_KEYTABLE_OFF(_n, 6) +#define AR5K_KEYTABLE_MAC1(_n) AR5K_KEYTABLE_OFF(_n, 7) +#define AR5K_KEYTABLE_VALID 0x00008000 + +/* If key type is TKIP and MIC is enabled + * MIC key goes in offset entry + 64 */ +#define AR5K_KEYTABLE_MIC_OFFSET 64 + +/* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit + * WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit + * WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit + * + * Some vendors have introduced bigger WEP keys to address + * security vulnerabilities in WEP. This includes: + * + * WEP 232-bit = 232-bit entered key + 24 bit IV = 256-bit + * + * We can expand this if we find ar5k Atheros cards with a larger + * key table size. + */ +#define AR5K_KEYTABLE_SIZE_5210 64 +#define AR5K_KEYTABLE_SIZE_5211 128 +#define AR5K_KEYTABLE_SIZE (ah->ah_version == AR5K_AR5210 ? \ + AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211) + + +/*===PHY REGISTERS===*/ + +/* + * PHY registers start + */ +#define AR5K_PHY_BASE 0x9800 +#define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2)) + +/* + * TST_2 (Misc config parameters) + */ +#define AR5K_PHY_TST2 0x9800 /* Register Address */ +#define AR5K_PHY_TST2_TRIG_SEL 0x00000007 /* Trigger select (?)*/ +#define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) */ +#define AR5K_PHY_TST2_CBUS_MODE 0x00000060 /* Cardbus mode (?) */ +#define AR5K_PHY_TST2_CLK32 0x00000400 /* CLK_OUT is CLK32 (32Khz external) */ +#define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 /* Enable Chancor dump (?) */ +#define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 /* Even Chancor dump (?) */ +#define AR5K_PHY_TST2_RFSILENT_EN 0x00002000 /* Enable RFSILENT */ +#define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch ?) */ +#define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000 /* Enable mini OBS (?) */ +#define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000 /* 2GHz rx path is the 5GHz path inverted (?) */ +#define AR5K_PHY_TST2_SLOW_CLK160 0x00020000 /* Slow CLK160 (?) */ +#define AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000 /* AGC OBS Select 3 (?) */ +#define AR5K_PHY_TST2_BBB_OBS_SEL 0x00080000 /* BB OBS Select (field ?) */ +#define AR5K_PHY_TST2_ADC_OBS_SEL 0x00800000 /* ADC OBS Select (field ?) */ +#define AR5K_PHY_TST2_RX_CLR_SEL 0x08000000 /* RX Clear Select (?) */ +#define AR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000 /* Force AGC clear (?) */ +#define AR5K_PHY_SHIFT_2GHZ 0x00004007 /* Used to access 2GHz radios */ +#define AR5K_PHY_SHIFT_5GHZ 0x00000007 /* Used to access 5GHz radios (default) */ + +/* + * PHY frame control register [5110] /turbo mode register [5111+] + * + * There is another frame control register for [5111+] + * at address 0x9944 (see below) but the 2 first flags + * are common here between 5110 frame control register + * and [5111+] turbo mode register, so this also works as + * a "turbo mode register" for 5110. We treat this one as + * a frame control register for 5110 below. + */ +#define AR5K_PHY_TURBO 0x9804 /* Register Address */ +#define AR5K_PHY_TURBO_MODE 0x00000001 /* Enable turbo mode */ +#define AR5K_PHY_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode */ +#define AR5K_PHY_TURBO_MIMO 0x00000004 /* Set turbo for mimo mimo */ + +/* + * PHY agility command register + * (aka TST_1) + */ +#define AR5K_PHY_AGC 0x9808 /* Register Address */ +#define AR5K_PHY_TST1 0x9808 +#define AR5K_PHY_AGC_DISABLE 0x08000000 /* Disable AGC to A2 (?)*/ +#define AR5K_PHY_TST1_TXHOLD 0x00003800 /* Set tx hold (?) */ +#define AR5K_PHY_TST1_TXSRC_SRC 0x00000002 /* Used with bit 7 (?) */ +#define AR5K_PHY_TST1_TXSRC_SRC_S 1 +#define AR5K_PHY_TST1_TXSRC_ALT 0x00000080 /* Set input to tsdac (?) */ +#define AR5K_PHY_TST1_TXSRC_ALT_S 7 + + +/* + * PHY timing register 3 [5112+] + */ +#define AR5K_PHY_TIMING_3 0x9814 +#define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 +#define AR5K_PHY_TIMING_3_DSC_MAN_S 17 +#define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000 +#define AR5K_PHY_TIMING_3_DSC_EXP_S 13 + +/* + * PHY chip revision register + */ +#define AR5K_PHY_CHIP_ID 0x9818 + +/* + * PHY activation register + */ +#define AR5K_PHY_ACT 0x981c /* Register Address */ +#define AR5K_PHY_ACT_ENABLE 0x00000001 /* Activate PHY */ +#define AR5K_PHY_ACT_DISABLE 0x00000002 /* Deactivate PHY */ + +/* + * PHY RF control registers + */ +#define AR5K_PHY_RF_CTL2 0x9824 /* Register Address */ +#define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f /* TX frame to TX data start */ +#define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0 + +#define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */ +#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00 /* TX end to XLNA on */ +#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 8 + +#define AR5K_PHY_ADC_CTL 0x982c +#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003 +#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S 0 +#define AR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x00002000 +#define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF 0x00004000 +#define AR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x00008000 +#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x00030000 +#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S 16 + +#define AR5K_PHY_RF_CTL4 0x9834 /* Register Address */ +#define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 /* TX frame to XPA A on (field) */ +#define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100 /* TX frame to XPA B on (field) */ +#define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000 /* TX end to XPA A off (field) */ +#define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000 /* TX end to XPA B off (field) */ + +/* + * Pre-Amplifier control register + * (XPA -> external pre-amplifier) + */ +#define AR5K_PHY_PA_CTL 0x9838 /* Register Address */ +#define AR5K_PHY_PA_CTL_XPA_A_HI 0x00000001 /* XPA A high (?) */ +#define AR5K_PHY_PA_CTL_XPA_B_HI 0x00000002 /* XPA B high (?) */ +#define AR5K_PHY_PA_CTL_XPA_A_EN 0x00000004 /* Enable XPA A */ +#define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008 /* Enable XPA B */ + +/* + * PHY settling register + */ +#define AR5K_PHY_SETTLING 0x9844 /* Register Address */ +#define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */ +#define AR5K_PHY_SETTLING_AGC_S 0 +#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settlig time */ +#define AR5K_PHY_SETTLING_SWITCH_S 7 + +/* + * PHY Gain registers + */ +#define AR5K_PHY_GAIN 0x9848 /* Register Address */ +#define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* TX-RX Attenuation */ +#define AR5K_PHY_GAIN_TXRX_ATTEN_S 12 +#define AR5K_PHY_GAIN_TXRX_RF_MAX 0x007c0000 +#define AR5K_PHY_GAIN_TXRX_RF_MAX_S 18 + +#define AR5K_PHY_GAIN_OFFSET 0x984c /* Register Address */ +#define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */ + +/* + * Desired ADC/PGA size register + * (for more infos read ANI patent) + */ +#define AR5K_PHY_DESIRED_SIZE 0x9850 /* Register Address */ +#define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff /* ADC desired size */ +#define AR5K_PHY_DESIRED_SIZE_ADC_S 0 +#define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 /* PGA desired size */ +#define AR5K_PHY_DESIRED_SIZE_PGA_S 8 +#define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 /* Total desired size */ +#define AR5K_PHY_DESIRED_SIZE_TOT_S 20 + +/* + * PHY signal register + * (for more infos read ANI patent) + */ +#define AR5K_PHY_SIG 0x9858 /* Register Address */ +#define AR5K_PHY_SIG_FIRSTEP 0x0003f000 /* FIRSTEP */ +#define AR5K_PHY_SIG_FIRSTEP_S 12 +#define AR5K_PHY_SIG_FIRPWR 0x03fc0000 /* FIPWR */ +#define AR5K_PHY_SIG_FIRPWR_S 18 + +/* + * PHY coarse agility control register + * (for more infos read ANI patent) + */ +#define AR5K_PHY_AGCCOARSE 0x985c /* Register Address */ +#define AR5K_PHY_AGCCOARSE_LO 0x00007f80 /* AGC Coarse low */ +#define AR5K_PHY_AGCCOARSE_LO_S 7 +#define AR5K_PHY_AGCCOARSE_HI 0x003f8000 /* AGC Coarse high */ +#define AR5K_PHY_AGCCOARSE_HI_S 15 + +/* + * PHY agility control register + */ +#define AR5K_PHY_AGCCTL 0x9860 /* Register address */ +#define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */ +#define AR5K_PHY_AGCCTL_NF 0x00000002 /* Enable Noise Floor calibration */ +#define AR5K_PHY_AGCCTL_NF_EN 0x00008000 /* Enable nf calibration to happen (?) */ +#define AR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000 /* Don't update nf automaticaly */ + +/* + * PHY noise floor status register + */ +#define AR5K_PHY_NF 0x9864 /* Register address */ +#define AR5K_PHY_NF_M 0x000001ff /* Noise floor mask */ +#define AR5K_PHY_NF_ACTIVE 0x00000100 /* Noise floor calibration still active */ +#define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M) +#define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1) +#define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9)) +#define AR5K_PHY_NF_THRESH62 0x0007f000 /* Thresh62 -check ANI patent- (field) */ +#define AR5K_PHY_NF_THRESH62_S 12 +#define AR5K_PHY_NF_MINCCA_PWR 0x0ff80000 /* ??? */ +#define AR5K_PHY_NF_MINCCA_PWR_S 19 + +/* + * PHY ADC saturation register [5110] + */ +#define AR5K_PHY_ADCSAT 0x9868 +#define AR5K_PHY_ADCSAT_ICNT 0x0001f800 +#define AR5K_PHY_ADCSAT_ICNT_S 11 +#define AR5K_PHY_ADCSAT_THR 0x000007e0 +#define AR5K_PHY_ADCSAT_THR_S 5 + +/* + * PHY Weak ofdm signal detection threshold registers (ANI) [5212+] + */ + +/* High thresholds */ +#define AR5K_PHY_WEAK_OFDM_HIGH_THR 0x9868 +#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT 0x0000001f +#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S 0 +#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe0000 +#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S 17 +#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f000000 +#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 24 + +/* Low thresholds */ +#define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c +#define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001 +#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00 +#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 8 +#define AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc000 +#define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S 14 +#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe00000 +#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S 21 + + +/* + * PHY sleep registers [5112+] + */ +#define AR5K_PHY_SCR 0x9870 + +#define AR5K_PHY_SLMT 0x9874 +#define AR5K_PHY_SLMT_32MHZ 0x0000007f + +#define AR5K_PHY_SCAL 0x9878 +#define AR5K_PHY_SCAL_32MHZ 0x0000000e +#define AR5K_PHY_SCAL_32MHZ_2417 0x0000000a +#define AR5K_PHY_SCAL_32MHZ_HB63 0x00000032 + +/* + * PHY PLL (Phase Locked Loop) control register + */ +#define AR5K_PHY_PLL 0x987c +#define AR5K_PHY_PLL_20MHZ 0x00000013 /* For half rate (?) */ +/* 40MHz -> 5GHz band */ +#define AR5K_PHY_PLL_40MHZ_5211 0x00000018 +#define AR5K_PHY_PLL_40MHZ_5212 0x000000aa +#define AR5K_PHY_PLL_40MHZ_5413 0x00000004 +#define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \ + AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212) +/* 44MHz -> 2.4GHz band */ +#define AR5K_PHY_PLL_44MHZ_5211 0x00000019 +#define AR5K_PHY_PLL_44MHZ_5212 0x000000ab +#define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \ + AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) + +#define AR5K_PHY_PLL_RF5111 0x00000000 +#define AR5K_PHY_PLL_RF5112 0x00000040 +#define AR5K_PHY_PLL_HALF_RATE 0x00000100 +#define AR5K_PHY_PLL_QUARTER_RATE 0x00000200 + +/* + * RF Buffer register + * + * It's obvious from the code that 0x989c is the buffer register but + * for the other special registers that we write to after sending each + * packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers + * for now. It's interesting that they are also used for some other operations. + */ + +#define AR5K_RF_BUFFER 0x989c +#define AR5K_RF_BUFFER_CONTROL_0 0x98c0 /* Channel on 5110 */ +#define AR5K_RF_BUFFER_CONTROL_1 0x98c4 /* Bank 7 on 5112 */ +#define AR5K_RF_BUFFER_CONTROL_2 0x98cc /* Bank 7 on 5111 */ + +#define AR5K_RF_BUFFER_CONTROL_3 0x98d0 /* Bank 2 on 5112 */ + /* Channel set on 5111 */ + /* Used to read radio revision*/ + +#define AR5K_RF_BUFFER_CONTROL_4 0x98d4 /* RF Stage register on 5110 */ + /* Bank 0,1,2,6 on 5111 */ + /* Bank 1 on 5112 */ + /* Used during activation on 5111 */ + +#define AR5K_RF_BUFFER_CONTROL_5 0x98d8 /* Bank 3 on 5111 */ + /* Used during activation on 5111 */ + /* Channel on 5112 */ + /* Bank 6 on 5112 */ + +#define AR5K_RF_BUFFER_CONTROL_6 0x98dc /* Bank 3 on 5112 */ + +/* + * PHY RF stage register [5210] + */ +#define AR5K_PHY_RFSTG 0x98d4 +#define AR5K_PHY_RFSTG_DISABLE 0x00000021 + +/* + * BIN masks (?) + */ +#define AR5K_PHY_BIN_MASK_1 0x9900 +#define AR5K_PHY_BIN_MASK_2 0x9904 +#define AR5K_PHY_BIN_MASK_3 0x9908 + +#define AR5K_PHY_BIN_MASK_CTL 0x990c +#define AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff +#define AR5K_PHY_BIN_MASK_CTL_MASK_4_S 0 +#define AR5K_PHY_BIN_MASK_CTL_RATE 0xff000000 +#define AR5K_PHY_BIN_MASK_CTL_RATE_S 24 + +/* + * PHY Antenna control register + */ +#define AR5K_PHY_ANT_CTL 0x9910 /* Register Address */ +#define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 /* Enable TX/RX (?) */ +#define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004 /* Sectored Antenna */ +#define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008 /* Hitune5 (?) */ +#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0 /* Switch table idle (?) */ +#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4 + +/* + * PHY receiver delay register [5111+] + */ +#define AR5K_PHY_RX_DELAY 0x9914 /* Register Address */ +#define AR5K_PHY_RX_DELAY_M 0x00003fff /* Mask for RX activate to receive delay (/100ns) */ + +/* + * PHY max rx length register (?) [5111] + */ +#define AR5K_PHY_MAX_RX_LEN 0x991c + +/* + * PHY timing register 4 + * I(nphase)/Q(adrature) calibration register [5111+] + */ +#define AR5K_PHY_IQ 0x9920 /* Register Address */ +#define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */ +#define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */ +#define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 +#define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */ +#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 /* Mask for max number of samples in log scale */ +#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 +#define AR5K_PHY_IQ_RUN 0x00010000 /* Run i/q calibration */ +#define AR5K_PHY_IQ_USE_PT_DF 0x00020000 /* Use pilot track df (?) */ +#define AR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000 /* Early trigger threshold (?) (field) */ +#define AR5K_PHY_IQ_PILOT_MASK_EN 0x10000000 /* Enable pilot mask (?) */ +#define AR5K_PHY_IQ_CHAN_MASK_EN 0x20000000 /* Enable channel mask (?) */ +#define AR5K_PHY_IQ_SPUR_FILT_EN 0x40000000 /* Enable spur filter */ +#define AR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000 /* Enable spur rssi */ + +/* + * PHY timing register 5 + * OFDM Self-correlator Cyclic RSSI threshold params + * (Check out bb_cycpwr_thr1 on ANI patent) + */ +#define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */ +#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */ +#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */ +#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 1 +#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */ +#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */ +#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */ +#define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI 0x00800000 /* Long sc threshold hi rssi (?) */ + +/* + * PHY-only warm reset register + */ +#define AR5K_PHY_WARM_RESET 0x9928 + +/* + * PHY-only control register + */ +#define AR5K_PHY_CTL 0x992c /* Register Address */ +#define AR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001 /* RX drain rate (?) */ +#define AR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002 /* Late tx signal symbol (?) */ +#define AR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004 /* Generate scrambler */ +#define AR5K_PHY_CTL_TX_ANT_SEL 0x00000008 /* TX antenna select */ +#define AR5K_PHY_CTL_TX_ANT_STATIC 0x00000010 /* Static TX antenna */ +#define AR5K_PHY_CTL_RX_ANT_SEL 0x00000020 /* RX antenna select */ +#define AR5K_PHY_CTL_RX_ANT_STATIC 0x00000040 /* Static RX antenna */ +#define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 /* Enable low freq sleep */ + +/* + * PHY PAPD probe register [5111+] + */ +#define AR5K_PHY_PAPD_PROBE 0x9930 +#define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001 +#define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x00000002 +#define AR5K_PHY_PAPD_PROBE_COMP_GAIN 0x00000040 +#define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 +#define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9 +#define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000 +#define AR5K_PHY_PAPD_PROBE_PREDIST_EN 0x00010000 +#define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /* [5112+] */ +#define AR5K_PHY_PAPD_PROBE_TYPE_S 23 +#define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0 +#define AR5K_PHY_PAPD_PROBE_TYPE_XR 1 +#define AR5K_PHY_PAPD_PROBE_TYPE_CCK 2 +#define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000 +#define AR5K_PHY_PAPD_PROBE_GAINF_S 25 +#define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883 /* [5212+] */ +#define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882 /* [5212+] */ + +/* + * PHY TX rate power registers [5112+] + */ +#define AR5K_PHY_TXPOWER_RATE1 0x9934 +#define AR5K_PHY_TXPOWER_RATE2 0x9938 +#define AR5K_PHY_TXPOWER_RATE_MAX 0x993c +#define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040 +#define AR5K_PHY_TXPOWER_RATE3 0xa234 +#define AR5K_PHY_TXPOWER_RATE4 0xa238 + +/* + * PHY frame control register [5111+] + */ +#define AR5K_PHY_FRAME_CTL_5210 0x9804 +#define AR5K_PHY_FRAME_CTL_5211 0x9944 +#define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \ + AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211) +/*---[5111+]---*/ +#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 /* Mask for tx clip (?) */ +#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3 +#define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 /* Prepend chan info */ +#define AR5K_PHY_FRAME_CTL_EMU 0x80000000 +#define AR5K_PHY_FRAME_CTL_EMU_S 31 +/*---[5110/5111]---*/ +#define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 /* PHY timing error */ +#define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 /* Parity error */ +#define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 /* Illegal rate */ +#define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 /* Illegal length */ +#define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 +#define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* TX underrun */ +#define AR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ + AR5K_PHY_FRAME_CTL_TXURN_ERR | \ + AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ + AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \ + AR5K_PHY_FRAME_CTL_PARITY_ERR | \ + AR5K_PHY_FRAME_CTL_TIMING_ERR + +/* + * PHY Tx Power adjustment register [5212A+] + */ +#define AR5K_PHY_TX_PWR_ADJ 0x994c +#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA 0x00000fc0 +#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S 6 +#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX 0x00fc0000 +#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S 18 + +/* + * PHY radar detection register [5111+] + */ +#define AR5K_PHY_RADAR 0x9954 +#define AR5K_PHY_RADAR_ENABLE 0x00000001 +#define AR5K_PHY_RADAR_DISABLE 0x00000000 +#define AR5K_PHY_RADAR_INBANDTHR 0x0000003e /* Inband threshold + 5-bits, units unknown {0..31} + (? MHz ?) */ +#define AR5K_PHY_RADAR_INBANDTHR_S 1 + +#define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0 /* Pulse RSSI/SNR threshold + 6-bits, dBm range {0..63} + in dBm units. */ +#define AR5K_PHY_RADAR_PRSSI_THR_S 6 + +#define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000 /* Pulse height threshold + 6-bits, dBm range {0..63} + in dBm units. */ +#define AR5K_PHY_RADAR_PHEIGHT_THR_S 12 + +#define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000 /* Radar RSSI/SNR threshold. + 6-bits, dBm range {0..63} + in dBm units. */ +#define AR5K_PHY_RADAR_RSSI_THR_S 18 + +#define AR5K_PHY_RADAR_FIRPWR_THR 0x7f000000 /* Finite Impulse Response + filter power out threshold. + 7-bits, standard power range + {0..127} in 1/2 dBm units. */ +#define AR5K_PHY_RADAR_FIRPWR_THRS 24 + +/* + * PHY antenna switch table registers + */ +#define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960 +#define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 + +/* + * PHY Noise floor threshold + */ +#define AR5K_PHY_NFTHRES 0x9968 + +/* + * Sigma Delta register (?) [5213] + */ +#define AR5K_PHY_SIGMA_DELTA 0x996C +#define AR5K_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 +#define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S 0 +#define AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f8 +#define AR5K_PHY_SIGMA_DELTA_FILT2_S 3 +#define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00 +#define AR5K_PHY_SIGMA_DELTA_FILT1_S 8 +#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000 +#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13 + +/* + * RF restart register [5112+] (?) + */ +#define AR5K_PHY_RESTART 0x9970 /* restart */ +#define AR5K_PHY_RESTART_DIV_GC 0x001c0000 /* Fast diversity gc_limit (?) */ +#define AR5K_PHY_RESTART_DIV_GC_S 18 + +/* + * RF Bus access request register (for synth-oly channel switching) + */ +#define AR5K_PHY_RFBUS_REQ 0x997C +#define AR5K_PHY_RFBUS_REQ_REQUEST 0x00000001 + +/* + * Spur mitigation masks (?) + */ +#define AR5K_PHY_TIMING_7 0x9980 +#define AR5K_PHY_TIMING_8 0x9984 +#define AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff +#define AR5K_PHY_TIMING_8_PILOT_MASK_2_S 0 + +#define AR5K_PHY_BIN_MASK2_1 0x9988 +#define AR5K_PHY_BIN_MASK2_2 0x998c +#define AR5K_PHY_BIN_MASK2_3 0x9990 + +#define AR5K_PHY_BIN_MASK2_4 0x9994 +#define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff +#define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0 + +#define AR5K_PHY_TIMING_9 0x9998 +#define AR5K_PHY_TIMING_10 0x999c +#define AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff +#define AR5K_PHY_TIMING_10_PILOT_MASK_2_S 0 + +/* + * Spur mitigation control + */ +#define AR5K_PHY_TIMING_11 0x99a0 /* Register address */ +#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */ +#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0 +#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */ +#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S 20 +#define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */ +#define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */ + +/* + * Gain tables + */ +#define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */ +#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) +#define AR5K_RF_GAIN_BASE 0x9a00 /* RF Amplrifier Gain table base address */ +#define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2)) + +/* + * PHY timing IQ calibration result register [5111+] + */ +#define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 /* I (Inphase) power value */ +#define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 /* Q (Quadrature) power value */ +#define AR5K_PHY_IQRES_CAL_CORR 0x9c18 /* I/Q Correlation */ + +/* + * PHY current RSSI register [5111+] + */ +#define AR5K_PHY_CURRENT_RSSI 0x9c1c + +/* + * PHY RF Bus grant register + */ +#define AR5K_PHY_RFBUS_GRANT 0x9c20 +#define AR5K_PHY_RFBUS_GRANT_OK 0x00000001 + +/* + * PHY ADC test register + */ +#define AR5K_PHY_ADC_TEST 0x9c24 +#define AR5K_PHY_ADC_TEST_I 0x00000001 +#define AR5K_PHY_ADC_TEST_Q 0x00000200 + +/* + * PHY DAC test register + */ +#define AR5K_PHY_DAC_TEST 0x9c28 +#define AR5K_PHY_DAC_TEST_I 0x00000001 +#define AR5K_PHY_DAC_TEST_Q 0x00000200 + +/* + * PHY PTAT register (?) + */ +#define AR5K_PHY_PTAT 0x9c2c + +/* + * PHY Illegal TX rate register [5112+] + */ +#define AR5K_PHY_BAD_TX_RATE 0x9c30 + +/* + * PHY SPUR Power register [5112+] + */ +#define AR5K_PHY_SPUR_PWR 0x9c34 /* Register Address */ +#define AR5K_PHY_SPUR_PWR_I 0x00000001 /* SPUR Power estimate for I (field) */ +#define AR5K_PHY_SPUR_PWR_Q 0x00000100 /* SPUR Power estimate for Q (field) */ +#define AR5K_PHY_SPUR_PWR_FILT 0x00010000 /* Power with SPUR removed (field) */ + +/* + * PHY Channel status register [5112+] (?) + */ +#define AR5K_PHY_CHAN_STATUS 0x9c38 +#define AR5K_PHY_CHAN_STATUS_BT_ACT 0x00000001 +#define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002 +#define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004 +#define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008 + +/* + * Heavy clip enable register + */ +#define AR5K_PHY_HEAVY_CLIP_ENABLE 0x99e0 + +/* + * PHY clock sleep registers [5112+] + */ +#define AR5K_PHY_SCLOCK 0x99f0 +#define AR5K_PHY_SCLOCK_32MHZ 0x0000000c +#define AR5K_PHY_SDELAY 0x99f4 +#define AR5K_PHY_SDELAY_32MHZ 0x000000ff +#define AR5K_PHY_SPENDING 0x99f8 + + +/* + * PHY PAPD I (power?) table (?) + * (92! entries) + */ +#define AR5K_PHY_PAPD_I_BASE 0xa000 +#define AR5K_PHY_PAPD_I(_n) (AR5K_PHY_PAPD_I_BASE + ((_n) << 2)) + +/* + * PHY PCDAC TX power table + */ +#define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180 +#define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) + +/* + * PHY mode register [5111+] + */ +#define AR5K_PHY_MODE 0x0a200 /* Register Address */ +#define AR5K_PHY_MODE_MOD 0x00000001 /* PHY Modulation bit */ +#define AR5K_PHY_MODE_MOD_OFDM 0 +#define AR5K_PHY_MODE_MOD_CCK 1 +#define AR5K_PHY_MODE_FREQ 0x00000002 /* Freq mode bit */ +#define AR5K_PHY_MODE_FREQ_5GHZ 0 +#define AR5K_PHY_MODE_FREQ_2GHZ 2 +#define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* Enable Dynamic OFDM/CCK mode [5112+] */ +#define AR5K_PHY_MODE_RAD 0x00000008 /* [5212+] */ +#define AR5K_PHY_MODE_RAD_RF5111 0 +#define AR5K_PHY_MODE_RAD_RF5112 8 +#define AR5K_PHY_MODE_XR 0x00000010 /* Enable XR mode [5112+] */ +#define AR5K_PHY_MODE_HALF_RATE 0x00000020 /* Enable Half rate (test) */ +#define AR5K_PHY_MODE_QUARTER_RATE 0x00000040 /* Enable Quarter rat (test) */ + +/* + * PHY CCK transmit control register [5111+ (?)] + */ +#define AR5K_PHY_CCKTXCTL 0xa204 +#define AR5K_PHY_CCKTXCTL_WORLD 0x00000000 +#define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010 +#define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001 +#define AR5K_PHY_CCKTXCTK_DAC_SCALE 0x00000004 + +/* + * PHY CCK Cross-correlator Barker RSSI threshold register [5212+] + */ +#define AR5K_PHY_CCK_CROSSCORR 0xa208 +#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000000f +#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0 + +/* Same address is used for antenna diversity activation */ +#define AR5K_PHY_FAST_ANT_DIV 0xa208 +#define AR5K_PHY_FAST_ANT_DIV_EN 0x00002000 + +/* + * PHY 2GHz gain register [5111+] + */ +#define AR5K_PHY_GAIN_2GHZ 0xa20c +#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 +#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18 +#define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c + +#define AR5K_PHY_CCK_RX_CTL_4 0xa21c +#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT 0x01f80000 +#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S 19 + +#define AR5K_PHY_DAG_CCK_CTL 0xa228 +#define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR 0x00000200 +#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc00 +#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S 10 + +#define AR5K_PHY_FAST_ADC 0xa24c + +#define AR5K_PHY_BLUETOOTH 0xa254 + +/* + * Transmit Power Control register + * [2413+] + */ +#define AR5K_PHY_TPC_RG1 0xa258 +#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000 +#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 14 +#define AR5K_PHY_TPC_RG1_PDGAIN_1 0x00030000 +#define AR5K_PHY_TPC_RG1_PDGAIN_1_S 16 +#define AR5K_PHY_TPC_RG1_PDGAIN_2 0x000c0000 +#define AR5K_PHY_TPC_RG1_PDGAIN_2_S 18 +#define AR5K_PHY_TPC_RG1_PDGAIN_3 0x00300000 +#define AR5K_PHY_TPC_RG1_PDGAIN_3_S 20 + +#define AR5K_PHY_TPC_RG5 0xa26C +#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP 0x0000000F +#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S 0 +#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1 0x000003F0 +#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S 4 +#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2 0x0000FC00 +#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S 10 +#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3 0x003F0000 +#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16 +#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000 +#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22 + +/* + * PHY PDADC Tx power table + */ +#define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280 +#define AR5K_PHY_PDADC_TXPOWER(_n) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2)) diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/rfbuffer.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/rfbuffer.h new file mode 100644 index 0000000..e50baff --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/rfbuffer.h @@ -0,0 +1,1181 @@ +/* + * RF Buffer handling functions + * + * Copyright (c) 2009 Nick Kossifidis <mickflemm@gmail.com> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + + +/* + * There are some special registers on the RF chip + * that control various operation settings related mostly to + * the analog parts (channel, gain adjustment etc). + * + * We don't write on those registers directly but + * we send a data packet on the chip, using a special register, + * that holds all the settings we need. After we 've sent the + * data packet, we write on another special register to notify hw + * to apply the settings. This is done so that control registers + * can be dynamicaly programmed during operation and the settings + * are applied faster on the hw. + * + * We call each data packet an "RF Bank" and all the data we write + * (all RF Banks) "RF Buffer". This file holds initial RF Buffer + * data for the different RF chips, and various info to match RF + * Buffer offsets with specific RF registers so that we can access + * them. We tweak these settings on rfregs_init function. + * + * Also check out reg.h and U.S. Patent 6677779 B1 (about buffer + * registers and control registers): + * + * http://www.google.com/patents?id=qNURAAAAEBAJ + */ + + +/* + * Struct to hold default mode specific RF + * register values (RF Banks) + */ +struct ath5k_ini_rfbuffer { + u8 rfb_bank; /* RF Bank number */ + u16 rfb_ctrl_register; /* RF Buffer control register */ + u32 rfb_mode_data[5]; /* RF Buffer data for each mode */ +}; + +/* + * Struct to hold RF Buffer field + * infos used to access certain RF + * analog registers + */ +struct ath5k_rfb_field { + u8 len; /* Field length */ + u16 pos; /* Offset on the raw packet */ + u8 col; /* Column -used for shifting */ +}; + +/* + * RF analog register definition + */ +struct ath5k_rf_reg { + u8 bank; /* RF Buffer Bank number */ + u8 index; /* Register's index on rf_regs_idx */ + struct ath5k_rfb_field field; /* RF Buffer field for this register */ +}; + +/* Map RF registers to indexes + * We do this to handle common bits and make our + * life easier by using an index for each register + * instead of a full rfb_field */ +enum ath5k_rf_regs_idx { + /* BANK 6 */ + AR5K_RF_OB_2GHZ = 0, + AR5K_RF_OB_5GHZ, + AR5K_RF_DB_2GHZ, + AR5K_RF_DB_5GHZ, + AR5K_RF_FIXED_BIAS_A, + AR5K_RF_FIXED_BIAS_B, + AR5K_RF_PWD_XPD, + AR5K_RF_XPD_SEL, + AR5K_RF_XPD_GAIN, + AR5K_RF_PD_GAIN_LO, + AR5K_RF_PD_GAIN_HI, + AR5K_RF_HIGH_VC_CP, + AR5K_RF_MID_VC_CP, + AR5K_RF_LOW_VC_CP, + AR5K_RF_PUSH_UP, + AR5K_RF_PAD2GND, + AR5K_RF_XB2_LVL, + AR5K_RF_XB5_LVL, + AR5K_RF_PWD_ICLOBUF_2G, + AR5K_RF_PWD_84, + AR5K_RF_PWD_90, + AR5K_RF_PWD_130, + AR5K_RF_PWD_131, + AR5K_RF_PWD_132, + AR5K_RF_PWD_136, + AR5K_RF_PWD_137, + AR5K_RF_PWD_138, + AR5K_RF_PWD_166, + AR5K_RF_PWD_167, + AR5K_RF_DERBY_CHAN_SEL_MODE, + /* BANK 7 */ + AR5K_RF_GAIN_I, + AR5K_RF_PLO_SEL, + AR5K_RF_RFGAIN_SEL, + AR5K_RF_RFGAIN_STEP, + AR5K_RF_WAIT_S, + AR5K_RF_WAIT_I, + AR5K_RF_MAX_TIME, + AR5K_RF_MIXVGA_OVR, + AR5K_RF_MIXGAIN_OVR, + AR5K_RF_MIXGAIN_STEP, + AR5K_RF_PD_DELAY_A, + AR5K_RF_PD_DELAY_B, + AR5K_RF_PD_DELAY_XR, + AR5K_RF_PD_PERIOD_A, + AR5K_RF_PD_PERIOD_B, + AR5K_RF_PD_PERIOD_XR, +}; + + +/*******************\ +* RF5111 (Sombrero) * +\*******************/ + +/* BANK 6 len pos col */ +#define AR5K_RF5111_OB_2GHZ { 3, 119, 0 } +#define AR5K_RF5111_DB_2GHZ { 3, 122, 0 } + +#define AR5K_RF5111_OB_5GHZ { 3, 104, 0 } +#define AR5K_RF5111_DB_5GHZ { 3, 107, 0 } + +#define AR5K_RF5111_PWD_XPD { 1, 95, 0 } +#define AR5K_RF5111_XPD_GAIN { 4, 96, 0 } + +/* Access to PWD registers */ +#define AR5K_RF5111_PWD(_n) { 1, (135 - _n), 3 } + +/* BANK 7 len pos col */ +#define AR5K_RF5111_GAIN_I { 6, 29, 0 } +#define AR5K_RF5111_PLO_SEL { 1, 4, 0 } +#define AR5K_RF5111_RFGAIN_SEL { 1, 36, 0 } +#define AR5K_RF5111_RFGAIN_STEP { 6, 37, 0 } +/* Only on AR5212 BaseBand and up */ +#define AR5K_RF5111_WAIT_S { 5, 19, 0 } +#define AR5K_RF5111_WAIT_I { 5, 24, 0 } +#define AR5K_RF5111_MAX_TIME { 2, 49, 0 } + +static const struct ath5k_rf_reg rf_regs_5111[] = { + {6, AR5K_RF_OB_2GHZ, AR5K_RF5111_OB_2GHZ}, + {6, AR5K_RF_DB_2GHZ, AR5K_RF5111_DB_2GHZ}, + {6, AR5K_RF_OB_5GHZ, AR5K_RF5111_OB_5GHZ}, + {6, AR5K_RF_DB_5GHZ, AR5K_RF5111_DB_5GHZ}, + {6, AR5K_RF_PWD_XPD, AR5K_RF5111_PWD_XPD}, + {6, AR5K_RF_XPD_GAIN, AR5K_RF5111_XPD_GAIN}, + {6, AR5K_RF_PWD_84, AR5K_RF5111_PWD(84)}, + {6, AR5K_RF_PWD_90, AR5K_RF5111_PWD(90)}, + {7, AR5K_RF_GAIN_I, AR5K_RF5111_GAIN_I}, + {7, AR5K_RF_PLO_SEL, AR5K_RF5111_PLO_SEL}, + {7, AR5K_RF_RFGAIN_SEL, AR5K_RF5111_RFGAIN_SEL}, + {7, AR5K_RF_RFGAIN_STEP, AR5K_RF5111_RFGAIN_STEP}, + {7, AR5K_RF_WAIT_S, AR5K_RF5111_WAIT_S}, + {7, AR5K_RF_WAIT_I, AR5K_RF5111_WAIT_I}, + {7, AR5K_RF_MAX_TIME, AR5K_RF5111_MAX_TIME} +}; + +/* Default mode specific settings */ +static const struct ath5k_ini_rfbuffer rfb_5111[] = { + { 0, 0x989c, + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 0, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 0, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 0, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 0, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 0, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 0, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 0, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 0, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 0, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 0, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 0, 0x989c, + { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } }, + { 0, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 0, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 0, 0x989c, + { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } }, + { 0, 0x989c, + { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } }, + { 0, 0x98d4, + { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } }, + { 1, 0x98d4, + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, + { 2, 0x98d4, + { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } }, + { 3, 0x98d8, + { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, + { 6, 0x989c, + { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } }, + { 6, 0x989c, + { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } }, + { 6, 0x989c, + { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } }, + { 6, 0x989c, + { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } }, + { 6, 0x989c, + { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } }, + { 6, 0x98d4, + { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } }, + { 7, 0x989c, + { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } }, + { 7, 0x989c, + { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } }, + { 7, 0x989c, + { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, + { 7, 0x989c, + { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } }, + { 7, 0x989c, + { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } }, + { 7, 0x989c, + { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } }, + { 7, 0x989c, + { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } }, + { 7, 0x98cc, + { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, +}; + + + +/***********************\ +* RF5112/RF2112 (Derby) * +\***********************/ + +/* BANK 7 (Common) len pos col */ +#define AR5K_RF5112X_GAIN_I { 6, 14, 0 } +#define AR5K_RF5112X_MIXVGA_OVR { 1, 36, 0 } +#define AR5K_RF5112X_MIXGAIN_OVR { 2, 37, 0 } +#define AR5K_RF5112X_MIXGAIN_STEP { 4, 32, 0 } +#define AR5K_RF5112X_PD_DELAY_A { 4, 58, 0 } +#define AR5K_RF5112X_PD_DELAY_B { 4, 62, 0 } +#define AR5K_RF5112X_PD_DELAY_XR { 4, 66, 0 } +#define AR5K_RF5112X_PD_PERIOD_A { 4, 70, 0 } +#define AR5K_RF5112X_PD_PERIOD_B { 4, 74, 0 } +#define AR5K_RF5112X_PD_PERIOD_XR { 4, 78, 0 } + +/* RFX112 (Derby 1) */ + +/* BANK 6 len pos col */ +#define AR5K_RF5112_OB_2GHZ { 3, 269, 0 } +#define AR5K_RF5112_DB_2GHZ { 3, 272, 0 } + +#define AR5K_RF5112_OB_5GHZ { 3, 261, 0 } +#define AR5K_RF5112_DB_5GHZ { 3, 264, 0 } + +#define AR5K_RF5112_FIXED_BIAS_A { 1, 260, 0 } +#define AR5K_RF5112_FIXED_BIAS_B { 1, 259, 0 } + +#define AR5K_RF5112_XPD_SEL { 1, 284, 0 } +#define AR5K_RF5112_XPD_GAIN { 2, 252, 0 } + +/* Access to PWD registers */ +#define AR5K_RF5112_PWD(_n) { 1, (302 - _n), 3 } + +static const struct ath5k_rf_reg rf_regs_5112[] = { + {6, AR5K_RF_OB_2GHZ, AR5K_RF5112_OB_2GHZ}, + {6, AR5K_RF_DB_2GHZ, AR5K_RF5112_DB_2GHZ}, + {6, AR5K_RF_OB_5GHZ, AR5K_RF5112_OB_5GHZ}, + {6, AR5K_RF_DB_5GHZ, AR5K_RF5112_DB_5GHZ}, + {6, AR5K_RF_FIXED_BIAS_A, AR5K_RF5112_FIXED_BIAS_A}, + {6, AR5K_RF_FIXED_BIAS_B, AR5K_RF5112_FIXED_BIAS_B}, + {6, AR5K_RF_XPD_SEL, AR5K_RF5112_XPD_SEL}, + {6, AR5K_RF_XPD_GAIN, AR5K_RF5112_XPD_GAIN}, + {6, AR5K_RF_PWD_130, AR5K_RF5112_PWD(130)}, + {6, AR5K_RF_PWD_131, AR5K_RF5112_PWD(131)}, + {6, AR5K_RF_PWD_132, AR5K_RF5112_PWD(132)}, + {6, AR5K_RF_PWD_136, AR5K_RF5112_PWD(136)}, + {6, AR5K_RF_PWD_137, AR5K_RF5112_PWD(137)}, + {6, AR5K_RF_PWD_138, AR5K_RF5112_PWD(138)}, + {7, AR5K_RF_GAIN_I, AR5K_RF5112X_GAIN_I}, + {7, AR5K_RF_MIXVGA_OVR, AR5K_RF5112X_MIXVGA_OVR}, + {7, AR5K_RF_MIXGAIN_OVR, AR5K_RF5112X_MIXGAIN_OVR}, + {7, AR5K_RF_MIXGAIN_STEP, AR5K_RF5112X_MIXGAIN_STEP}, + {7, AR5K_RF_PD_DELAY_A, AR5K_RF5112X_PD_DELAY_A}, + {7, AR5K_RF_PD_DELAY_B, AR5K_RF5112X_PD_DELAY_B}, + {7, AR5K_RF_PD_DELAY_XR, AR5K_RF5112X_PD_DELAY_XR}, + {7, AR5K_RF_PD_PERIOD_A, AR5K_RF5112X_PD_PERIOD_A}, + {7, AR5K_RF_PD_PERIOD_B, AR5K_RF5112X_PD_PERIOD_B}, + {7, AR5K_RF_PD_PERIOD_XR, AR5K_RF5112X_PD_PERIOD_XR}, +}; + +/* Default mode specific settings */ +static const struct ath5k_ini_rfbuffer rfb_5112[] = { + { 1, 0x98d4, + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, + { 2, 0x98d0, + { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, + { 3, 0x98dc, + { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, + { 6, 0x989c, + { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } }, + { 6, 0x989c, + { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } }, + { 6, 0x989c, + { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } }, + { 6, 0x989c, + { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } }, + { 6, 0x989c, + { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, + { 6, 0x989c, + { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, + { 6, 0x989c, + { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, + { 6, 0x989c, + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, + { 6, 0x989c, + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, + { 6, 0x989c, + { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } }, + { 6, 0x989c, + { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } }, + { 6, 0x989c, + { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, + { 6, 0x989c, + { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } }, + { 6, 0x989c, + { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } }, + { 6, 0x989c, + { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } }, + { 6, 0x989c, + { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, + { 6, 0x989c, + { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } }, + { 6, 0x989c, + { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, + { 6, 0x989c, + { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, + { 6, 0x989c, + { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } }, + { 6, 0x989c, + { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } }, + { 6, 0x989c, + { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, + { 6, 0x989c, + { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } }, + { 6, 0x989c, + { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } }, + { 6, 0x989c, + { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } }, + { 6, 0x989c, + { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } }, + { 6, 0x989c, + { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } }, + { 6, 0x989c, + { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } }, + { 6, 0x989c, + { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } }, + { 6, 0x989c, + { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } }, + { 6, 0x989c, + { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } }, + { 6, 0x989c, + { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } }, + { 6, 0x98d0, + { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } }, + { 7, 0x989c, + { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, + { 7, 0x989c, + { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, + { 7, 0x989c, + { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } }, + { 7, 0x989c, + { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, + { 7, 0x989c, + { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } }, + { 7, 0x989c, + { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, + { 7, 0x989c, + { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, + { 7, 0x989c, + { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } }, + { 7, 0x989c, + { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } }, + { 7, 0x989c, + { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, + { 7, 0x989c, + { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, + { 7, 0x989c, + { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, + { 7, 0x98c4, + { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, +}; + +/* RFX112A (Derby 2) */ + +/* BANK 6 len pos col */ +#define AR5K_RF5112A_OB_2GHZ { 3, 287, 0 } +#define AR5K_RF5112A_DB_2GHZ { 3, 290, 0 } + +#define AR5K_RF5112A_OB_5GHZ { 3, 279, 0 } +#define AR5K_RF5112A_DB_5GHZ { 3, 282, 0 } + +#define AR5K_RF5112A_FIXED_BIAS_A { 1, 278, 0 } +#define AR5K_RF5112A_FIXED_BIAS_B { 1, 277, 0 } + +#define AR5K_RF5112A_XPD_SEL { 1, 302, 0 } +#define AR5K_RF5112A_PDGAINLO { 2, 270, 0 } +#define AR5K_RF5112A_PDGAINHI { 2, 257, 0 } + +/* Access to PWD registers */ +#define AR5K_RF5112A_PWD(_n) { 1, (306 - _n), 3 } + +/* Voltage regulators */ +#define AR5K_RF5112A_HIGH_VC_CP { 2, 90, 2 } +#define AR5K_RF5112A_MID_VC_CP { 2, 92, 2 } +#define AR5K_RF5112A_LOW_VC_CP { 2, 94, 2 } +#define AR5K_RF5112A_PUSH_UP { 1, 254, 2 } + +/* Power consumption */ +#define AR5K_RF5112A_PAD2GND { 1, 281, 1 } +#define AR5K_RF5112A_XB2_LVL { 2, 1, 3 } +#define AR5K_RF5112A_XB5_LVL { 2, 3, 3 } + +static const struct ath5k_rf_reg rf_regs_5112a[] = { + {6, AR5K_RF_OB_2GHZ, AR5K_RF5112A_OB_2GHZ}, + {6, AR5K_RF_DB_2GHZ, AR5K_RF5112A_DB_2GHZ}, + {6, AR5K_RF_OB_5GHZ, AR5K_RF5112A_OB_5GHZ}, + {6, AR5K_RF_DB_5GHZ, AR5K_RF5112A_DB_5GHZ}, + {6, AR5K_RF_FIXED_BIAS_A, AR5K_RF5112A_FIXED_BIAS_A}, + {6, AR5K_RF_FIXED_BIAS_B, AR5K_RF5112A_FIXED_BIAS_B}, + {6, AR5K_RF_XPD_SEL, AR5K_RF5112A_XPD_SEL}, + {6, AR5K_RF_PD_GAIN_LO, AR5K_RF5112A_PDGAINLO}, + {6, AR5K_RF_PD_GAIN_HI, AR5K_RF5112A_PDGAINHI}, + {6, AR5K_RF_PWD_130, AR5K_RF5112A_PWD(130)}, + {6, AR5K_RF_PWD_131, AR5K_RF5112A_PWD(131)}, + {6, AR5K_RF_PWD_132, AR5K_RF5112A_PWD(132)}, + {6, AR5K_RF_PWD_136, AR5K_RF5112A_PWD(136)}, + {6, AR5K_RF_PWD_137, AR5K_RF5112A_PWD(137)}, + {6, AR5K_RF_PWD_138, AR5K_RF5112A_PWD(138)}, + {6, AR5K_RF_PWD_166, AR5K_RF5112A_PWD(166)}, + {6, AR5K_RF_PWD_167, AR5K_RF5112A_PWD(167)}, + {6, AR5K_RF_HIGH_VC_CP, AR5K_RF5112A_HIGH_VC_CP}, + {6, AR5K_RF_MID_VC_CP, AR5K_RF5112A_MID_VC_CP}, + {6, AR5K_RF_LOW_VC_CP, AR5K_RF5112A_LOW_VC_CP}, + {6, AR5K_RF_PUSH_UP, AR5K_RF5112A_PUSH_UP}, + {6, AR5K_RF_PAD2GND, AR5K_RF5112A_PAD2GND}, + {6, AR5K_RF_XB2_LVL, AR5K_RF5112A_XB2_LVL}, + {6, AR5K_RF_XB5_LVL, AR5K_RF5112A_XB5_LVL}, + {7, AR5K_RF_GAIN_I, AR5K_RF5112X_GAIN_I}, + {7, AR5K_RF_MIXVGA_OVR, AR5K_RF5112X_MIXVGA_OVR}, + {7, AR5K_RF_MIXGAIN_OVR, AR5K_RF5112X_MIXGAIN_OVR}, + {7, AR5K_RF_MIXGAIN_STEP, AR5K_RF5112X_MIXGAIN_STEP}, + {7, AR5K_RF_PD_DELAY_A, AR5K_RF5112X_PD_DELAY_A}, + {7, AR5K_RF_PD_DELAY_B, AR5K_RF5112X_PD_DELAY_B}, + {7, AR5K_RF_PD_DELAY_XR, AR5K_RF5112X_PD_DELAY_XR}, + {7, AR5K_RF_PD_PERIOD_A, AR5K_RF5112X_PD_PERIOD_A}, + {7, AR5K_RF_PD_PERIOD_B, AR5K_RF5112X_PD_PERIOD_B}, + {7, AR5K_RF_PD_PERIOD_XR, AR5K_RF5112X_PD_PERIOD_XR}, +}; + +/* Default mode specific settings */ +static const struct ath5k_ini_rfbuffer rfb_5112a[] = { + { 1, 0x98d4, + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, + { 2, 0x98d0, + { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, + { 3, 0x98dc, + { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } }, + { 6, 0x989c, + { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } }, + { 6, 0x989c, + { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, + { 6, 0x989c, + { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } }, + { 6, 0x989c, + { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } }, + { 6, 0x989c, + { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } }, + { 6, 0x989c, + { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } }, + { 6, 0x989c, + { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } }, + { 6, 0x989c, + { 0x004c0000, 0x004c0000, 0x004c0000, 0x004c0000, 0x004c0000 } }, + { 6, 0x989c, + { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } }, + { 6, 0x989c, + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, + { 6, 0x989c, + { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } }, + { 6, 0x989c, + { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, + { 6, 0x989c, + { 0x02190000, 0x02190000, 0x02190000, 0x02190000, 0x02190000 } }, + { 6, 0x989c, + { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, + { 6, 0x989c, + { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } }, + { 6, 0x989c, + { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } }, + { 6, 0x989c, + { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } }, + { 6, 0x989c, + { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, + { 6, 0x989c, + { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, + { 6, 0x989c, + { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } }, + { 6, 0x989c, + { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } }, + { 6, 0x989c, + { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, + { 6, 0x989c, + { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } }, + { 6, 0x989c, + { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } }, + { 6, 0x989c, + { 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080 } }, + { 6, 0x989c, + { 0x00270019, 0x00270019, 0x00270019, 0x00270019, 0x00270019 } }, + { 6, 0x989c, + { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } }, + { 6, 0x989c, + { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } }, + { 6, 0x989c, + { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } }, + { 6, 0x989c, + { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } }, + { 6, 0x989c, + { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } }, + { 6, 0x98d8, + { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } }, + { 7, 0x989c, + { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, + { 7, 0x989c, + { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, + { 7, 0x989c, + { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } }, + { 7, 0x989c, + { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, + { 7, 0x989c, + { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } }, + { 7, 0x989c, + { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, + { 7, 0x989c, + { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, + { 7, 0x989c, + { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } }, + { 7, 0x989c, + { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } }, + { 7, 0x989c, + { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, + { 7, 0x989c, + { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, + { 7, 0x989c, + { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, + { 7, 0x98c4, + { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, +}; + + + +/******************\ +* RF2413 (Griffin) * +\******************/ + +/* BANK 6 len pos col */ +#define AR5K_RF2413_OB_2GHZ { 3, 168, 0 } +#define AR5K_RF2413_DB_2GHZ { 3, 165, 0 } + +static const struct ath5k_rf_reg rf_regs_2413[] = { + {6, AR5K_RF_OB_2GHZ, AR5K_RF2413_OB_2GHZ}, + {6, AR5K_RF_DB_2GHZ, AR5K_RF2413_DB_2GHZ}, +}; + +/* Default mode specific settings + * XXX: a/aTurbo ??? + */ +static const struct ath5k_ini_rfbuffer rfb_2413[] = { + { 1, 0x98d4, + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, + { 2, 0x98d0, + { 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 } }, + { 3, 0x98dc, + { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } }, + { 6, 0x989c, + { 0xf0000000, 0xf0000000, 0xf0000000, 0xf0000000, 0xf0000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x03000000, 0x03000000, 0x03000000, 0x03000000, 0x03000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x40400000, 0x40400000, 0x40400000, 0x40400000, 0x40400000 } }, + { 6, 0x989c, + { 0x65050000, 0x65050000, 0x65050000, 0x65050000, 0x65050000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00420000, 0x00420000, 0x00420000, 0x00420000, 0x00420000 } }, + { 6, 0x989c, + { 0x00b50000, 0x00b50000, 0x00b50000, 0x00b50000, 0x00b50000 } }, + { 6, 0x989c, + { 0x00030000, 0x00030000, 0x00030000, 0x00030000, 0x00030000 } }, + { 6, 0x989c, + { 0x00f70000, 0x00f70000, 0x00f70000, 0x00f70000, 0x00f70000 } }, + { 6, 0x989c, + { 0x009d0000, 0x009d0000, 0x009d0000, 0x009d0000, 0x009d0000 } }, + { 6, 0x989c, + { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } }, + { 6, 0x989c, + { 0x04220000, 0x04220000, 0x04220000, 0x04220000, 0x04220000 } }, + { 6, 0x989c, + { 0x00230018, 0x00230018, 0x00230018, 0x00230018, 0x00230018 } }, + { 6, 0x989c, + { 0x00280000, 0x00280000, 0x00280060, 0x00280060, 0x00280060 } }, + { 6, 0x989c, + { 0x005000c0, 0x005000c0, 0x005000c3, 0x005000c3, 0x005000c3 } }, + { 6, 0x989c, + { 0x0004007f, 0x0004007f, 0x0004007f, 0x0004007f, 0x0004007f } }, + { 6, 0x989c, + { 0x00000458, 0x00000458, 0x00000458, 0x00000458, 0x00000458 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x0000c000, 0x0000c000, 0x0000c000, 0x0000c000, 0x0000c000 } }, + { 6, 0x98d8, + { 0x00400230, 0x00400230, 0x00400230, 0x00400230, 0x00400230 } }, + { 7, 0x989c, + { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } }, + { 7, 0x989c, + { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } }, + { 7, 0x98cc, + { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } }, +}; + + + +/***************************\ +* RF2315/RF2316 (Cobra SoC) * +\***************************/ + +/* BANK 6 len pos col */ +#define AR5K_RF2316_OB_2GHZ { 3, 178, 0 } +#define AR5K_RF2316_DB_2GHZ { 3, 175, 0 } + +static const struct ath5k_rf_reg rf_regs_2316[] = { + {6, AR5K_RF_OB_2GHZ, AR5K_RF2316_OB_2GHZ}, + {6, AR5K_RF_DB_2GHZ, AR5K_RF2316_DB_2GHZ}, +}; + +/* Default mode specific settings */ +static const struct ath5k_ini_rfbuffer rfb_2316[] = { + { 1, 0x98d4, + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, + { 2, 0x98d0, + { 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 } }, + { 3, 0x98dc, + { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000 } }, + { 6, 0x989c, + { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } }, + { 6, 0x989c, + { 0x02000000, 0x02000000, 0x02000000, 0x02000000, 0x02000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0xf8000000, 0xf8000000, 0xf8000000, 0xf8000000, 0xf8000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x95150000, 0x95150000, 0x95150000, 0x95150000, 0x95150000 } }, + { 6, 0x989c, + { 0xc1000000, 0xc1000000, 0xc1000000, 0xc1000000, 0xc1000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00080000, 0x00080000, 0x00080000, 0x00080000, 0x00080000 } }, + { 6, 0x989c, + { 0x00d50000, 0x00d50000, 0x00d50000, 0x00d50000, 0x00d50000 } }, + { 6, 0x989c, + { 0x000e0000, 0x000e0000, 0x000e0000, 0x000e0000, 0x000e0000 } }, + { 6, 0x989c, + { 0x00dc0000, 0x00dc0000, 0x00dc0000, 0x00dc0000, 0x00dc0000 } }, + { 6, 0x989c, + { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } }, + { 6, 0x989c, + { 0x008a0000, 0x008a0000, 0x008a0000, 0x008a0000, 0x008a0000 } }, + { 6, 0x989c, + { 0x10880000, 0x10880000, 0x10880000, 0x10880000, 0x10880000 } }, + { 6, 0x989c, + { 0x008c0060, 0x008c0060, 0x008c0060, 0x008c0060, 0x008c0060 } }, + { 6, 0x989c, + { 0x00a00000, 0x00a00000, 0x00a00080, 0x00a00080, 0x00a00080 } }, + { 6, 0x989c, + { 0x00400000, 0x00400000, 0x0040000d, 0x0040000d, 0x0040000d } }, + { 6, 0x989c, + { 0x00110400, 0x00110400, 0x00110400, 0x00110400, 0x00110400 } }, + { 6, 0x989c, + { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, + { 6, 0x989c, + { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } }, + { 6, 0x989c, + { 0x00000b00, 0x00000b00, 0x00000b00, 0x00000b00, 0x00000b00 } }, + { 6, 0x989c, + { 0x00000be8, 0x00000be8, 0x00000be8, 0x00000be8, 0x00000be8 } }, + { 6, 0x98c0, + { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } }, + { 7, 0x989c, + { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } }, + { 7, 0x989c, + { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } }, + { 7, 0x98cc, + { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } }, +}; + + + +/******************************\ +* RF5413/RF5424 (Eagle/Condor) * +\******************************/ + +/* BANK 6 len pos col */ +#define AR5K_RF5413_OB_2GHZ { 3, 241, 0 } +#define AR5K_RF5413_DB_2GHZ { 3, 238, 0 } + +#define AR5K_RF5413_OB_5GHZ { 3, 247, 0 } +#define AR5K_RF5413_DB_5GHZ { 3, 244, 0 } + +#define AR5K_RF5413_PWD_ICLOBUF2G { 3, 131, 3 } +#define AR5K_RF5413_DERBY_CHAN_SEL_MODE { 1, 291, 2 } + +static const struct ath5k_rf_reg rf_regs_5413[] = { + {6, AR5K_RF_OB_2GHZ, AR5K_RF5413_OB_2GHZ}, + {6, AR5K_RF_DB_2GHZ, AR5K_RF5413_DB_2GHZ}, + {6, AR5K_RF_OB_5GHZ, AR5K_RF5413_OB_5GHZ}, + {6, AR5K_RF_DB_5GHZ, AR5K_RF5413_DB_5GHZ}, + {6, AR5K_RF_PWD_ICLOBUF_2G, AR5K_RF5413_PWD_ICLOBUF2G}, + {6, AR5K_RF_DERBY_CHAN_SEL_MODE, AR5K_RF5413_DERBY_CHAN_SEL_MODE}, +}; + +/* Default mode specific settings */ +static const struct ath5k_ini_rfbuffer rfb_5413[] = { + { 1, 0x98d4, + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, + { 2, 0x98d0, + { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, + { 3, 0x98dc, + { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } }, + { 6, 0x989c, + { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } }, + { 6, 0x989c, + { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } }, + { 6, 0x989c, + { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } }, + { 6, 0x989c, + { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } }, + { 6, 0x989c, + { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } }, + { 6, 0x989c, + { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } }, + { 6, 0x989c, + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, + { 6, 0x989c, + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, + { 6, 0x989c, + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, + { 6, 0x989c, + { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, + { 6, 0x989c, + { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } }, + { 6, 0x989c, + { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } }, + { 6, 0x989c, + { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } }, + { 6, 0x989c, + { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } }, + { 6, 0x989c, + { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } }, + { 6, 0x989c, + { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } }, + { 6, 0x989c, + { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } }, + { 6, 0x989c, + { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } }, + { 6, 0x989c, + { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } }, + { 6, 0x989c, + { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } }, + { 6, 0x989c, + { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } }, + { 6, 0x989c, + { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } }, + { 6, 0x989c, + { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } }, + { 6, 0x989c, + { 0x00510040, 0x00510040, 0x00510040, 0x00510040, 0x00510040 } }, + { 6, 0x989c, + { 0x005000da, 0x005000da, 0x005000da, 0x005000da, 0x005000da } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } }, + { 6, 0x989c, + { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00002c00 } }, + { 6, 0x98c8, + { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } }, + { 7, 0x989c, + { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } }, + { 7, 0x989c, + { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } }, + { 7, 0x98cc, + { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } }, +}; + + + +/***************************\ +* RF2425/RF2417 (Swan/Nala) * +* AR2317 (Spider SoC) * +\***************************/ + +/* BANK 6 len pos col */ +#define AR5K_RF2425_OB_2GHZ { 3, 193, 0 } +#define AR5K_RF2425_DB_2GHZ { 3, 190, 0 } + +static const struct ath5k_rf_reg rf_regs_2425[] = { + {6, AR5K_RF_OB_2GHZ, AR5K_RF2425_OB_2GHZ}, + {6, AR5K_RF_DB_2GHZ, AR5K_RF2425_DB_2GHZ}, +}; + +/* Default mode specific settings + * XXX: a/aTurbo ? + */ +static const struct ath5k_ini_rfbuffer rfb_2425[] = { + { 1, 0x98d4, + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, + { 2, 0x98d0, + { 0x02001408, 0x02001408, 0x02001408, 0x02001408, 0x02001408 } }, + { 3, 0x98dc, + { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } }, + { 6, 0x989c, + { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 } }, + { 6, 0x989c, + { 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 } }, + { 6, 0x989c, + { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } }, + { 6, 0x989c, + { 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 } }, + { 6, 0x989c, + { 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000 } }, + { 6, 0x989c, + { 0x00140000, 0x00140000, 0x00140000, 0x00140000, 0x00140000 } }, + { 6, 0x989c, + { 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 } }, + { 6, 0x989c, + { 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a } }, + { 6, 0x989c, + { 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 } }, + { 6, 0x989c, + { 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 } }, + { 6, 0x989c, + { 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 } }, + { 6, 0x989c, + { 0x00001688, 0x00001688, 0x00001688, 0x00001688, 0x00001688 } }, + { 6, 0x98c4, + { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } }, + { 7, 0x989c, + { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } }, + { 7, 0x989c, + { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } }, + { 7, 0x98cc, + { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } }, +}; + +/* + * TODO: Handle the few differences with swan during + * bank modification and get rid of this + */ +static const struct ath5k_ini_rfbuffer rfb_2317[] = { + { 1, 0x98d4, + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, + { 2, 0x98d0, + { 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 } }, + { 3, 0x98dc, + { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } }, + { 6, 0x989c, + { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 } }, + { 6, 0x989c, + { 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 } }, + { 6, 0x989c, + { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } }, + { 6, 0x989c, + { 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 } }, + { 6, 0x989c, + { 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000 } }, + { 6, 0x989c, + { 0x00140100, 0x00140100, 0x00140100, 0x00140100, 0x00140100 } }, + { 6, 0x989c, + { 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 } }, + { 6, 0x989c, + { 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a } }, + { 6, 0x989c, + { 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 } }, + { 6, 0x989c, + { 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 } }, + { 6, 0x989c, + { 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 } }, + { 6, 0x989c, + { 0x00009688, 0x00009688, 0x00009688, 0x00009688, 0x00009688 } }, + { 6, 0x98c4, + { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } }, + { 7, 0x989c, + { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } }, + { 7, 0x989c, + { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } }, + { 7, 0x98cc, + { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } }, +}; + +/* + * TODO: Handle the few differences with swan during + * bank modification and get rid of this + * XXX: a/aTurbo ? + */ +static const struct ath5k_ini_rfbuffer rfb_2417[] = { + { 1, 0x98d4, + /* mode a/XR mode aTurbo mode b mode g mode gTurbo */ + { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, + { 2, 0x98d0, + { 0x02001408, 0x02001408, 0x02001408, 0x02001408, 0x02001408 } }, + { 3, 0x98dc, + { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } }, + { 6, 0x989c, + { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 } }, + { 6, 0x989c, + { 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 } }, + { 6, 0x989c, + { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } }, + { 6, 0x989c, + { 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 } }, + { 6, 0x989c, + { 0x00e70000, 0x00e70000, 0x80e70000, 0x80e70000, 0x00e70000 } }, + { 6, 0x989c, + { 0x00140000, 0x00140000, 0x00140000, 0x00140000, 0x00140000 } }, + { 6, 0x989c, + { 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 } }, + { 6, 0x989c, + { 0x0007001a, 0x0007001a, 0x0207001a, 0x0207001a, 0x0007001a } }, + { 6, 0x989c, + { 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 } }, + { 6, 0x989c, + { 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 } }, + { 6, 0x989c, + { 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, + { 6, 0x989c, + { 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 } }, + { 6, 0x989c, + { 0x00001688, 0x00001688, 0x00001688, 0x00001688, 0x00001688 } }, + { 6, 0x98c4, + { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } }, + { 7, 0x989c, + { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } }, + { 7, 0x989c, + { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } }, + { 7, 0x98cc, + { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } }, +}; diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/rfgain.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/rfgain.h new file mode 100644 index 0000000..1354d8c --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ath5k/rfgain.h @@ -0,0 +1,516 @@ +/* + * RF Gain optimization + * + * Copyright (c) 2004-2009 Reyk Floeter <reyk@openbsd.org> + * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* + * Mode-specific RF Gain table (64bytes) for RF5111/5112 + * (RF5110 only comes with AR5210 and only supports a/turbo a mode so initial + * RF Gain values are included in AR5K_AR5210_INI) + */ +struct ath5k_ini_rfgain { + u16 rfg_register; /* RF Gain register address */ + u32 rfg_value[2]; /* [freq (see below)] */ +}; + +/* Initial RF Gain settings for RF5111 */ +static const struct ath5k_ini_rfgain rfgain_5111[] = { + /* 5Ghz 2Ghz */ + { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } }, + { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } }, + { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } }, + { AR5K_RF_GAIN(3), { 0x00000069, 0x00000150 } }, + { AR5K_RF_GAIN(4), { 0x00000199, 0x00000190 } }, + { AR5K_RF_GAIN(5), { 0x000001d9, 0x000001d0 } }, + { AR5K_RF_GAIN(6), { 0x00000019, 0x00000010 } }, + { AR5K_RF_GAIN(7), { 0x00000059, 0x00000044 } }, + { AR5K_RF_GAIN(8), { 0x00000099, 0x00000084 } }, + { AR5K_RF_GAIN(9), { 0x000001a5, 0x00000148 } }, + { AR5K_RF_GAIN(10), { 0x000001e5, 0x00000188 } }, + { AR5K_RF_GAIN(11), { 0x00000025, 0x000001c8 } }, + { AR5K_RF_GAIN(12), { 0x000001c8, 0x00000014 } }, + { AR5K_RF_GAIN(13), { 0x00000008, 0x00000042 } }, + { AR5K_RF_GAIN(14), { 0x00000048, 0x00000082 } }, + { AR5K_RF_GAIN(15), { 0x00000088, 0x00000178 } }, + { AR5K_RF_GAIN(16), { 0x00000198, 0x000001b8 } }, + { AR5K_RF_GAIN(17), { 0x000001d8, 0x000001f8 } }, + { AR5K_RF_GAIN(18), { 0x00000018, 0x00000012 } }, + { AR5K_RF_GAIN(19), { 0x00000058, 0x00000052 } }, + { AR5K_RF_GAIN(20), { 0x00000098, 0x00000092 } }, + { AR5K_RF_GAIN(21), { 0x000001a4, 0x0000017c } }, + { AR5K_RF_GAIN(22), { 0x000001e4, 0x000001bc } }, + { AR5K_RF_GAIN(23), { 0x00000024, 0x000001fc } }, + { AR5K_RF_GAIN(24), { 0x00000064, 0x0000000a } }, + { AR5K_RF_GAIN(25), { 0x000000a4, 0x0000004a } }, + { AR5K_RF_GAIN(26), { 0x000000e4, 0x0000008a } }, + { AR5K_RF_GAIN(27), { 0x0000010a, 0x0000015a } }, + { AR5K_RF_GAIN(28), { 0x0000014a, 0x0000019a } }, + { AR5K_RF_GAIN(29), { 0x0000018a, 0x000001da } }, + { AR5K_RF_GAIN(30), { 0x000001ca, 0x0000000e } }, + { AR5K_RF_GAIN(31), { 0x0000000a, 0x0000004e } }, + { AR5K_RF_GAIN(32), { 0x0000004a, 0x0000008e } }, + { AR5K_RF_GAIN(33), { 0x0000008a, 0x0000015e } }, + { AR5K_RF_GAIN(34), { 0x000001ba, 0x0000019e } }, + { AR5K_RF_GAIN(35), { 0x000001fa, 0x000001de } }, + { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000009 } }, + { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000049 } }, + { AR5K_RF_GAIN(38), { 0x00000186, 0x00000089 } }, + { AR5K_RF_GAIN(39), { 0x000001c6, 0x00000179 } }, + { AR5K_RF_GAIN(40), { 0x00000006, 0x000001b9 } }, + { AR5K_RF_GAIN(41), { 0x00000046, 0x000001f9 } }, + { AR5K_RF_GAIN(42), { 0x00000086, 0x00000039 } }, + { AR5K_RF_GAIN(43), { 0x000000c6, 0x00000079 } }, + { AR5K_RF_GAIN(44), { 0x000000c6, 0x000000b9 } }, + { AR5K_RF_GAIN(45), { 0x000000c6, 0x000001bd } }, + { AR5K_RF_GAIN(46), { 0x000000c6, 0x000001fd } }, + { AR5K_RF_GAIN(47), { 0x000000c6, 0x0000003d } }, + { AR5K_RF_GAIN(48), { 0x000000c6, 0x0000007d } }, + { AR5K_RF_GAIN(49), { 0x000000c6, 0x000000bd } }, + { AR5K_RF_GAIN(50), { 0x000000c6, 0x000000fd } }, + { AR5K_RF_GAIN(51), { 0x000000c6, 0x000000fd } }, + { AR5K_RF_GAIN(52), { 0x000000c6, 0x000000fd } }, + { AR5K_RF_GAIN(53), { 0x000000c6, 0x000000fd } }, + { AR5K_RF_GAIN(54), { 0x000000c6, 0x000000fd } }, + { AR5K_RF_GAIN(55), { 0x000000c6, 0x000000fd } }, + { AR5K_RF_GAIN(56), { 0x000000c6, 0x000000fd } }, + { AR5K_RF_GAIN(57), { 0x000000c6, 0x000000fd } }, + { AR5K_RF_GAIN(58), { 0x000000c6, 0x000000fd } }, + { AR5K_RF_GAIN(59), { 0x000000c6, 0x000000fd } }, + { AR5K_RF_GAIN(60), { 0x000000c6, 0x000000fd } }, + { AR5K_RF_GAIN(61), { 0x000000c6, 0x000000fd } }, + { AR5K_RF_GAIN(62), { 0x000000c6, 0x000000fd } }, + { AR5K_RF_GAIN(63), { 0x000000c6, 0x000000fd } }, +}; + +/* Initial RF Gain settings for RF5112 */ +static const struct ath5k_ini_rfgain rfgain_5112[] = { + /* 5Ghz 2Ghz */ + { AR5K_RF_GAIN(0), { 0x00000007, 0x00000007 } }, + { AR5K_RF_GAIN(1), { 0x00000047, 0x00000047 } }, + { AR5K_RF_GAIN(2), { 0x00000087, 0x00000087 } }, + { AR5K_RF_GAIN(3), { 0x000001a0, 0x000001a0 } }, + { AR5K_RF_GAIN(4), { 0x000001e0, 0x000001e0 } }, + { AR5K_RF_GAIN(5), { 0x00000020, 0x00000020 } }, + { AR5K_RF_GAIN(6), { 0x00000060, 0x00000060 } }, + { AR5K_RF_GAIN(7), { 0x000001a1, 0x000001a1 } }, + { AR5K_RF_GAIN(8), { 0x000001e1, 0x000001e1 } }, + { AR5K_RF_GAIN(9), { 0x00000021, 0x00000021 } }, + { AR5K_RF_GAIN(10), { 0x00000061, 0x00000061 } }, + { AR5K_RF_GAIN(11), { 0x00000162, 0x00000162 } }, + { AR5K_RF_GAIN(12), { 0x000001a2, 0x000001a2 } }, + { AR5K_RF_GAIN(13), { 0x000001e2, 0x000001e2 } }, + { AR5K_RF_GAIN(14), { 0x00000022, 0x00000022 } }, + { AR5K_RF_GAIN(15), { 0x00000062, 0x00000062 } }, + { AR5K_RF_GAIN(16), { 0x00000163, 0x00000163 } }, + { AR5K_RF_GAIN(17), { 0x000001a3, 0x000001a3 } }, + { AR5K_RF_GAIN(18), { 0x000001e3, 0x000001e3 } }, + { AR5K_RF_GAIN(19), { 0x00000023, 0x00000023 } }, + { AR5K_RF_GAIN(20), { 0x00000063, 0x00000063 } }, + { AR5K_RF_GAIN(21), { 0x00000184, 0x00000184 } }, + { AR5K_RF_GAIN(22), { 0x000001c4, 0x000001c4 } }, + { AR5K_RF_GAIN(23), { 0x00000004, 0x00000004 } }, + { AR5K_RF_GAIN(24), { 0x000001ea, 0x0000000b } }, + { AR5K_RF_GAIN(25), { 0x0000002a, 0x0000004b } }, + { AR5K_RF_GAIN(26), { 0x0000006a, 0x0000008b } }, + { AR5K_RF_GAIN(27), { 0x000000aa, 0x000001ac } }, + { AR5K_RF_GAIN(28), { 0x000001ab, 0x000001ec } }, + { AR5K_RF_GAIN(29), { 0x000001eb, 0x0000002c } }, + { AR5K_RF_GAIN(30), { 0x0000002b, 0x00000012 } }, + { AR5K_RF_GAIN(31), { 0x0000006b, 0x00000052 } }, + { AR5K_RF_GAIN(32), { 0x000000ab, 0x00000092 } }, + { AR5K_RF_GAIN(33), { 0x000001ac, 0x00000193 } }, + { AR5K_RF_GAIN(34), { 0x000001ec, 0x000001d3 } }, + { AR5K_RF_GAIN(35), { 0x0000002c, 0x00000013 } }, + { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000053 } }, + { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000093 } }, + { AR5K_RF_GAIN(38), { 0x000000ba, 0x00000194 } }, + { AR5K_RF_GAIN(39), { 0x000001bb, 0x000001d4 } }, + { AR5K_RF_GAIN(40), { 0x000001fb, 0x00000014 } }, + { AR5K_RF_GAIN(41), { 0x0000003b, 0x0000003a } }, + { AR5K_RF_GAIN(42), { 0x0000007b, 0x0000007a } }, + { AR5K_RF_GAIN(43), { 0x000000bb, 0x000000ba } }, + { AR5K_RF_GAIN(44), { 0x000001bc, 0x000001bb } }, + { AR5K_RF_GAIN(45), { 0x000001fc, 0x000001fb } }, + { AR5K_RF_GAIN(46), { 0x0000003c, 0x0000003b } }, + { AR5K_RF_GAIN(47), { 0x0000007c, 0x0000007b } }, + { AR5K_RF_GAIN(48), { 0x000000bc, 0x000000bb } }, + { AR5K_RF_GAIN(49), { 0x000000fc, 0x000001bc } }, + { AR5K_RF_GAIN(50), { 0x000000fc, 0x000001fc } }, + { AR5K_RF_GAIN(51), { 0x000000fc, 0x0000003c } }, + { AR5K_RF_GAIN(52), { 0x000000fc, 0x0000007c } }, + { AR5K_RF_GAIN(53), { 0x000000fc, 0x000000bc } }, + { AR5K_RF_GAIN(54), { 0x000000fc, 0x000000fc } }, + { AR5K_RF_GAIN(55), { 0x000000fc, 0x000000fc } }, + { AR5K_RF_GAIN(56), { 0x000000fc, 0x000000fc } }, + { AR5K_RF_GAIN(57), { 0x000000fc, 0x000000fc } }, + { AR5K_RF_GAIN(58), { 0x000000fc, 0x000000fc } }, + { AR5K_RF_GAIN(59), { 0x000000fc, 0x000000fc } }, + { AR5K_RF_GAIN(60), { 0x000000fc, 0x000000fc } }, + { AR5K_RF_GAIN(61), { 0x000000fc, 0x000000fc } }, + { AR5K_RF_GAIN(62), { 0x000000fc, 0x000000fc } }, + { AR5K_RF_GAIN(63), { 0x000000fc, 0x000000fc } }, +}; + +/* Initial RF Gain settings for RF2413 */ +static const struct ath5k_ini_rfgain rfgain_2413[] = { + { AR5K_RF_GAIN(0), { 0x00000000, 0x00000000 } }, + { AR5K_RF_GAIN(1), { 0x00000000, 0x00000040 } }, + { AR5K_RF_GAIN(2), { 0x00000000, 0x00000080 } }, + { AR5K_RF_GAIN(3), { 0x00000000, 0x00000181 } }, + { AR5K_RF_GAIN(4), { 0x00000000, 0x000001c1 } }, + { AR5K_RF_GAIN(5), { 0x00000000, 0x00000001 } }, + { AR5K_RF_GAIN(6), { 0x00000000, 0x00000041 } }, + { AR5K_RF_GAIN(7), { 0x00000000, 0x00000081 } }, + { AR5K_RF_GAIN(8), { 0x00000000, 0x00000168 } }, + { AR5K_RF_GAIN(9), { 0x00000000, 0x000001a8 } }, + { AR5K_RF_GAIN(10), { 0x00000000, 0x000001e8 } }, + { AR5K_RF_GAIN(11), { 0x00000000, 0x00000028 } }, + { AR5K_RF_GAIN(12), { 0x00000000, 0x00000068 } }, + { AR5K_RF_GAIN(13), { 0x00000000, 0x00000189 } }, + { AR5K_RF_GAIN(14), { 0x00000000, 0x000001c9 } }, + { AR5K_RF_GAIN(15), { 0x00000000, 0x00000009 } }, + { AR5K_RF_GAIN(16), { 0x00000000, 0x00000049 } }, + { AR5K_RF_GAIN(17), { 0x00000000, 0x00000089 } }, + { AR5K_RF_GAIN(18), { 0x00000000, 0x00000190 } }, + { AR5K_RF_GAIN(19), { 0x00000000, 0x000001d0 } }, + { AR5K_RF_GAIN(20), { 0x00000000, 0x00000010 } }, + { AR5K_RF_GAIN(21), { 0x00000000, 0x00000050 } }, + { AR5K_RF_GAIN(22), { 0x00000000, 0x00000090 } }, + { AR5K_RF_GAIN(23), { 0x00000000, 0x00000191 } }, + { AR5K_RF_GAIN(24), { 0x00000000, 0x000001d1 } }, + { AR5K_RF_GAIN(25), { 0x00000000, 0x00000011 } }, + { AR5K_RF_GAIN(26), { 0x00000000, 0x00000051 } }, + { AR5K_RF_GAIN(27), { 0x00000000, 0x00000091 } }, + { AR5K_RF_GAIN(28), { 0x00000000, 0x00000178 } }, + { AR5K_RF_GAIN(29), { 0x00000000, 0x000001b8 } }, + { AR5K_RF_GAIN(30), { 0x00000000, 0x000001f8 } }, + { AR5K_RF_GAIN(31), { 0x00000000, 0x00000038 } }, + { AR5K_RF_GAIN(32), { 0x00000000, 0x00000078 } }, + { AR5K_RF_GAIN(33), { 0x00000000, 0x00000199 } }, + { AR5K_RF_GAIN(34), { 0x00000000, 0x000001d9 } }, + { AR5K_RF_GAIN(35), { 0x00000000, 0x00000019 } }, + { AR5K_RF_GAIN(36), { 0x00000000, 0x00000059 } }, + { AR5K_RF_GAIN(37), { 0x00000000, 0x00000099 } }, + { AR5K_RF_GAIN(38), { 0x00000000, 0x000000d9 } }, + { AR5K_RF_GAIN(39), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(40), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(41), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(42), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(43), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(44), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(45), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(46), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(47), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(48), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(49), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(50), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(51), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(52), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(53), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(54), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(55), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(56), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(57), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(58), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(59), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(60), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(61), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(62), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(63), { 0x00000000, 0x000000f9 } }, +}; + +/* Initial RF Gain settings for AR2316 */ +static const struct ath5k_ini_rfgain rfgain_2316[] = { + { AR5K_RF_GAIN(0), { 0x00000000, 0x00000000 } }, + { AR5K_RF_GAIN(1), { 0x00000000, 0x00000040 } }, + { AR5K_RF_GAIN(2), { 0x00000000, 0x00000080 } }, + { AR5K_RF_GAIN(3), { 0x00000000, 0x000000c0 } }, + { AR5K_RF_GAIN(4), { 0x00000000, 0x000000e0 } }, + { AR5K_RF_GAIN(5), { 0x00000000, 0x000000e0 } }, + { AR5K_RF_GAIN(6), { 0x00000000, 0x00000128 } }, + { AR5K_RF_GAIN(7), { 0x00000000, 0x00000128 } }, + { AR5K_RF_GAIN(8), { 0x00000000, 0x00000128 } }, + { AR5K_RF_GAIN(9), { 0x00000000, 0x00000168 } }, + { AR5K_RF_GAIN(10), { 0x00000000, 0x000001a8 } }, + { AR5K_RF_GAIN(11), { 0x00000000, 0x000001e8 } }, + { AR5K_RF_GAIN(12), { 0x00000000, 0x00000028 } }, + { AR5K_RF_GAIN(13), { 0x00000000, 0x00000068 } }, + { AR5K_RF_GAIN(14), { 0x00000000, 0x000000a8 } }, + { AR5K_RF_GAIN(15), { 0x00000000, 0x000000e8 } }, + { AR5K_RF_GAIN(16), { 0x00000000, 0x000000e8 } }, + { AR5K_RF_GAIN(17), { 0x00000000, 0x00000130 } }, + { AR5K_RF_GAIN(18), { 0x00000000, 0x00000130 } }, + { AR5K_RF_GAIN(19), { 0x00000000, 0x00000170 } }, + { AR5K_RF_GAIN(20), { 0x00000000, 0x000001b0 } }, + { AR5K_RF_GAIN(21), { 0x00000000, 0x000001f0 } }, + { AR5K_RF_GAIN(22), { 0x00000000, 0x00000030 } }, + { AR5K_RF_GAIN(23), { 0x00000000, 0x00000070 } }, + { AR5K_RF_GAIN(24), { 0x00000000, 0x000000b0 } }, + { AR5K_RF_GAIN(25), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(26), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(27), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(28), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(29), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(30), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(31), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(32), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(33), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(34), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(35), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(36), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(37), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(38), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(39), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(40), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(41), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(42), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(43), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(44), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(45), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(46), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(47), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(48), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(49), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(50), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(51), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(52), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(53), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(54), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(55), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(56), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(57), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(58), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(59), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(60), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(61), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(62), { 0x00000000, 0x000000f0 } }, + { AR5K_RF_GAIN(63), { 0x00000000, 0x000000f0 } }, +}; + + +/* Initial RF Gain settings for RF5413 */ +static const struct ath5k_ini_rfgain rfgain_5413[] = { + /* 5Ghz 2Ghz */ + { AR5K_RF_GAIN(0), { 0x00000000, 0x00000000 } }, + { AR5K_RF_GAIN(1), { 0x00000040, 0x00000040 } }, + { AR5K_RF_GAIN(2), { 0x00000080, 0x00000080 } }, + { AR5K_RF_GAIN(3), { 0x000001a1, 0x00000161 } }, + { AR5K_RF_GAIN(4), { 0x000001e1, 0x000001a1 } }, + { AR5K_RF_GAIN(5), { 0x00000021, 0x000001e1 } }, + { AR5K_RF_GAIN(6), { 0x00000061, 0x00000021 } }, + { AR5K_RF_GAIN(7), { 0x00000188, 0x00000061 } }, + { AR5K_RF_GAIN(8), { 0x000001c8, 0x00000188 } }, + { AR5K_RF_GAIN(9), { 0x00000008, 0x000001c8 } }, + { AR5K_RF_GAIN(10), { 0x00000048, 0x00000008 } }, + { AR5K_RF_GAIN(11), { 0x00000088, 0x00000048 } }, + { AR5K_RF_GAIN(12), { 0x000001a9, 0x00000088 } }, + { AR5K_RF_GAIN(13), { 0x000001e9, 0x00000169 } }, + { AR5K_RF_GAIN(14), { 0x00000029, 0x000001a9 } }, + { AR5K_RF_GAIN(15), { 0x00000069, 0x000001e9 } }, + { AR5K_RF_GAIN(16), { 0x000001d0, 0x00000029 } }, + { AR5K_RF_GAIN(17), { 0x00000010, 0x00000069 } }, + { AR5K_RF_GAIN(18), { 0x00000050, 0x00000190 } }, + { AR5K_RF_GAIN(19), { 0x00000090, 0x000001d0 } }, + { AR5K_RF_GAIN(20), { 0x000001b1, 0x00000010 } }, + { AR5K_RF_GAIN(21), { 0x000001f1, 0x00000050 } }, + { AR5K_RF_GAIN(22), { 0x00000031, 0x00000090 } }, + { AR5K_RF_GAIN(23), { 0x00000071, 0x00000171 } }, + { AR5K_RF_GAIN(24), { 0x000001b8, 0x000001b1 } }, + { AR5K_RF_GAIN(25), { 0x000001f8, 0x000001f1 } }, + { AR5K_RF_GAIN(26), { 0x00000038, 0x00000031 } }, + { AR5K_RF_GAIN(27), { 0x00000078, 0x00000071 } }, + { AR5K_RF_GAIN(28), { 0x00000199, 0x00000198 } }, + { AR5K_RF_GAIN(29), { 0x000001d9, 0x000001d8 } }, + { AR5K_RF_GAIN(30), { 0x00000019, 0x00000018 } }, + { AR5K_RF_GAIN(31), { 0x00000059, 0x00000058 } }, + { AR5K_RF_GAIN(32), { 0x00000099, 0x00000098 } }, + { AR5K_RF_GAIN(33), { 0x000000d9, 0x00000179 } }, + { AR5K_RF_GAIN(34), { 0x000000f9, 0x000001b9 } }, + { AR5K_RF_GAIN(35), { 0x000000f9, 0x000001f9 } }, + { AR5K_RF_GAIN(36), { 0x000000f9, 0x00000039 } }, + { AR5K_RF_GAIN(37), { 0x000000f9, 0x00000079 } }, + { AR5K_RF_GAIN(38), { 0x000000f9, 0x000000b9 } }, + { AR5K_RF_GAIN(39), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(40), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(41), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(42), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(43), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(44), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(45), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(46), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(47), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(48), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(49), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(50), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(51), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(52), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(53), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(54), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(55), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(56), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(57), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(58), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(59), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(60), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(61), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(62), { 0x000000f9, 0x000000f9 } }, + { AR5K_RF_GAIN(63), { 0x000000f9, 0x000000f9 } }, +}; + + +/* Initial RF Gain settings for RF2425 */ +static const struct ath5k_ini_rfgain rfgain_2425[] = { + { AR5K_RF_GAIN(0), { 0x00000000, 0x00000000 } }, + { AR5K_RF_GAIN(1), { 0x00000000, 0x00000040 } }, + { AR5K_RF_GAIN(2), { 0x00000000, 0x00000080 } }, + { AR5K_RF_GAIN(3), { 0x00000000, 0x00000181 } }, + { AR5K_RF_GAIN(4), { 0x00000000, 0x000001c1 } }, + { AR5K_RF_GAIN(5), { 0x00000000, 0x00000001 } }, + { AR5K_RF_GAIN(6), { 0x00000000, 0x00000041 } }, + { AR5K_RF_GAIN(7), { 0x00000000, 0x00000081 } }, + { AR5K_RF_GAIN(8), { 0x00000000, 0x00000188 } }, + { AR5K_RF_GAIN(9), { 0x00000000, 0x000001c8 } }, + { AR5K_RF_GAIN(10), { 0x00000000, 0x00000008 } }, + { AR5K_RF_GAIN(11), { 0x00000000, 0x00000048 } }, + { AR5K_RF_GAIN(12), { 0x00000000, 0x00000088 } }, + { AR5K_RF_GAIN(13), { 0x00000000, 0x00000189 } }, + { AR5K_RF_GAIN(14), { 0x00000000, 0x000001c9 } }, + { AR5K_RF_GAIN(15), { 0x00000000, 0x00000009 } }, + { AR5K_RF_GAIN(16), { 0x00000000, 0x00000049 } }, + { AR5K_RF_GAIN(17), { 0x00000000, 0x00000089 } }, + { AR5K_RF_GAIN(18), { 0x00000000, 0x000001b0 } }, + { AR5K_RF_GAIN(19), { 0x00000000, 0x000001f0 } }, + { AR5K_RF_GAIN(20), { 0x00000000, 0x00000030 } }, + { AR5K_RF_GAIN(21), { 0x00000000, 0x00000070 } }, + { AR5K_RF_GAIN(22), { 0x00000000, 0x00000171 } }, + { AR5K_RF_GAIN(23), { 0x00000000, 0x000001b1 } }, + { AR5K_RF_GAIN(24), { 0x00000000, 0x000001f1 } }, + { AR5K_RF_GAIN(25), { 0x00000000, 0x00000031 } }, + { AR5K_RF_GAIN(26), { 0x00000000, 0x00000071 } }, + { AR5K_RF_GAIN(27), { 0x00000000, 0x000001b8 } }, + { AR5K_RF_GAIN(28), { 0x00000000, 0x000001f8 } }, + { AR5K_RF_GAIN(29), { 0x00000000, 0x00000038 } }, + { AR5K_RF_GAIN(30), { 0x00000000, 0x00000078 } }, + { AR5K_RF_GAIN(31), { 0x00000000, 0x000000b8 } }, + { AR5K_RF_GAIN(32), { 0x00000000, 0x000001b9 } }, + { AR5K_RF_GAIN(33), { 0x00000000, 0x000001f9 } }, + { AR5K_RF_GAIN(34), { 0x00000000, 0x00000039 } }, + { AR5K_RF_GAIN(35), { 0x00000000, 0x00000079 } }, + { AR5K_RF_GAIN(36), { 0x00000000, 0x000000b9 } }, + { AR5K_RF_GAIN(37), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(38), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(39), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(40), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(41), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(42), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(43), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(44), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(45), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(46), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(47), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(48), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(49), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(50), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(51), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(52), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(53), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(54), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(55), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(56), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(57), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(58), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(59), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(60), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(61), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(62), { 0x00000000, 0x000000f9 } }, + { AR5K_RF_GAIN(63), { 0x00000000, 0x000000f9 } }, +}; + +#define AR5K_GAIN_CRN_FIX_BITS_5111 4 +#define AR5K_GAIN_CRN_FIX_BITS_5112 7 +#define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112 +#define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15 +#define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20 +#define AR5K_GAIN_CCK_PROBE_CORR 5 +#define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15 +#define AR5K_GAIN_STEP_COUNT 10 + +/* Check if our current measurement is inside our + * current variable attenuation window */ +#define AR5K_GAIN_CHECK_ADJUST(_g) \ + ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high) + +struct ath5k_gain_opt_step { + s8 gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS]; + s8 gos_gain; +}; + +struct ath5k_gain_opt { + u8 go_default; + u8 go_steps_count; + const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT]; +}; + +/* + * Parameters on gos_param: + * 1) Tx clip PHY register + * 2) PWD 90 RF register + * 3) PWD 84 RF register + * 4) RFGainSel RF register + */ +static const struct ath5k_gain_opt rfgain_opt_5111 = { + 4, + 9, + { + { { 4, 1, 1, 1 }, 6 }, + { { 4, 0, 1, 1 }, 4 }, + { { 3, 1, 1, 1 }, 3 }, + { { 4, 0, 0, 1 }, 1 }, + { { 4, 1, 1, 0 }, 0 }, + { { 4, 0, 1, 0 }, -2 }, + { { 3, 1, 1, 0 }, -3 }, + { { 4, 0, 0, 0 }, -4 }, + { { 2, 1, 1, 0 }, -6 } + } +}; + +/* + * Parameters on gos_param: + * 1) Mixgain ovr RF register + * 2) PWD 138 RF register + * 3) PWD 137 RF register + * 4) PWD 136 RF register + * 5) PWD 132 RF register + * 6) PWD 131 RF register + * 7) PWD 130 RF register + */ +static const struct ath5k_gain_opt rfgain_opt_5112 = { + 1, + 8, + { + { { 3, 0, 0, 0, 0, 0, 0 }, 6 }, + { { 2, 0, 0, 0, 0, 0, 0 }, 0 }, + { { 1, 0, 0, 0, 0, 0, 0 }, -3 }, + { { 0, 0, 0, 0, 0, 0, 0 }, -6 }, + { { 0, 1, 1, 0, 0, 0, 0 }, -8 }, + { { 0, 1, 1, 0, 1, 1, 0 }, -10 }, + { { 0, 1, 0, 1, 1, 1, 0 }, -13 }, + { { 0, 1, 0, 1, 1, 0, 1 }, -16 }, + } +}; + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/atl1e.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/atl1e.c new file mode 100644 index 0000000..664eba0 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/atl1e.c @@ -0,0 +1,1757 @@ +/* + * Copyright(c) 2007 Atheros Corporation. All rights reserved. + * + * Derived from Intel e1000 driver + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. + * + * Modified for gPXE, October 2009 by Joshua Oreman <oremanj@rwcr.net>. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include "atl1e.h" + +/* User-tweakable parameters: */ +#define TX_DESC_COUNT 32 /* TX descriptors, minimum 32 */ +#define RX_MEM_SIZE 8192 /* RX area size, minimum 8kb */ +#define MAX_FRAME_SIZE 1500 /* Maximum MTU supported, minimum 1500 */ + +/* Arcane parameters: */ +#define PREAMBLE_LEN 7 +#define RX_JUMBO_THRESH ((MAX_FRAME_SIZE + ETH_HLEN + \ + VLAN_HLEN + ETH_FCS_LEN + 7) >> 3) +#define IMT_VAL 100 /* interrupt moderator timer, us */ +#define ICT_VAL 50000 /* interrupt clear timer, us */ +#define SMB_TIMER 200000 +#define RRD_THRESH 1 /* packets to queue before interrupt */ +#define TPD_BURST 5 +#define TPD_THRESH (TX_DESC_COUNT / 2) +#define RX_COUNT_DOWN 4 +#define TX_COUNT_DOWN (IMT_VAL * 4 / 3) +#define DMAR_DLY_CNT 15 +#define DMAW_DLY_CNT 4 + +#define PCI_DEVICE_ID_ATTANSIC_L1E 0x1026 + +/* + * atl1e_pci_tbl - PCI Device ID Table + * + * Wildcard entries (PCI_ANY_ID) should come last + * Last entry must be all 0s + * + * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, + * Class, Class Mask, private data (not used) } + */ +static struct pci_device_id atl1e_pci_tbl[] = { + PCI_ROM(0x1969, 0x1026, "atl1e_26", "Attansic L1E 0x1026", 0), + PCI_ROM(0x1969, 0x1066, "atl1e_66", "Attansic L1E 0x1066", 0), +}; + +static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter); + +static const u16 +atl1e_rx_page_vld_regs[AT_PAGE_NUM_PER_QUEUE] = +{ + REG_HOST_RXF0_PAGE0_VLD, REG_HOST_RXF0_PAGE1_VLD +}; + +static const u16 +atl1e_rx_page_lo_addr_regs[AT_PAGE_NUM_PER_QUEUE] = +{ + REG_HOST_RXF0_PAGE0_LO, REG_HOST_RXF0_PAGE1_LO +}; + +static const u16 +atl1e_rx_page_write_offset_regs[AT_PAGE_NUM_PER_QUEUE] = +{ + REG_HOST_RXF0_MB0_LO, REG_HOST_RXF0_MB1_LO +}; + +static const u16 atl1e_pay_load_size[] = { + 128, 256, 512, 1024, 2048, 4096, +}; + +/* + * atl1e_irq_enable - Enable default interrupt generation settings + * @adapter: board private structure + */ +static inline void atl1e_irq_enable(struct atl1e_adapter *adapter) +{ + AT_WRITE_REG(&adapter->hw, REG_ISR, 0); + AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); + AT_WRITE_FLUSH(&adapter->hw); +} + +/* + * atl1e_irq_disable - Mask off interrupt generation on the NIC + * @adapter: board private structure + */ +static inline void atl1e_irq_disable(struct atl1e_adapter *adapter) +{ + AT_WRITE_REG(&adapter->hw, REG_IMR, 0); + AT_WRITE_FLUSH(&adapter->hw); +} + +/* + * atl1e_irq_reset - reset interrupt confiure on the NIC + * @adapter: board private structure + */ +static inline void atl1e_irq_reset(struct atl1e_adapter *adapter) +{ + AT_WRITE_REG(&adapter->hw, REG_ISR, 0); + AT_WRITE_REG(&adapter->hw, REG_IMR, 0); + AT_WRITE_FLUSH(&adapter->hw); +} + +static void atl1e_reset(struct atl1e_adapter *adapter) +{ + atl1e_down(adapter); + atl1e_up(adapter); +} + +static int atl1e_check_link(struct atl1e_adapter *adapter) +{ + struct atl1e_hw *hw = &adapter->hw; + struct net_device *netdev = adapter->netdev; + int err = 0; + u16 speed, duplex, phy_data; + + /* MII_BMSR must read twise */ + atl1e_read_phy_reg(hw, MII_BMSR, &phy_data); + atl1e_read_phy_reg(hw, MII_BMSR, &phy_data); + + if ((phy_data & BMSR_LSTATUS) == 0) { + /* link down */ + if (netdev_link_ok(netdev)) { /* old link state: Up */ + u32 value; + /* disable rx */ + value = AT_READ_REG(hw, REG_MAC_CTRL); + value &= ~MAC_CTRL_RX_EN; + AT_WRITE_REG(hw, REG_MAC_CTRL, value); + adapter->link_speed = SPEED_0; + + DBG("atl1e: %s link is down\n", netdev->name); + netdev_link_down(netdev); + } + } else { + /* Link Up */ + err = atl1e_get_speed_and_duplex(hw, &speed, &duplex); + if (err) + return err; + + /* link result is our setting */ + if (adapter->link_speed != speed || + adapter->link_duplex != duplex) { + adapter->link_speed = speed; + adapter->link_duplex = duplex; + atl1e_setup_mac_ctrl(adapter); + + DBG("atl1e: %s link is up, %d Mbps, %s duplex\n", + netdev->name, adapter->link_speed, + adapter->link_duplex == FULL_DUPLEX ? + "full" : "half"); + netdev_link_up(netdev); + } + } + return 0; +} + +static int atl1e_mdio_read(struct net_device *netdev, int phy_id __unused, + int reg_num) +{ + struct atl1e_adapter *adapter = netdev_priv(netdev); + u16 result; + + atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result); + return result; +} + +static void atl1e_mdio_write(struct net_device *netdev, int phy_id __unused, + int reg_num, int val) +{ + struct atl1e_adapter *adapter = netdev_priv(netdev); + + atl1e_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val); +} + +static void atl1e_setup_pcicmd(struct pci_device *pdev) +{ + u16 cmd; + + pci_read_config_word(pdev, PCI_COMMAND, &cmd); + cmd |= (PCI_COMMAND_MEM | PCI_COMMAND_MASTER); + pci_write_config_word(pdev, PCI_COMMAND, cmd); + + /* + * some motherboards BIOS(PXE/EFI) driver may set PME + * while they transfer control to OS (Windows/Linux) + * so we should clear this bit before NIC work normally + */ + pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0); + mdelay(1); +} + +/* + * atl1e_sw_init - Initialize general software structures (struct atl1e_adapter) + * @adapter: board private structure to initialize + * + * atl1e_sw_init initializes the Adapter private data structure. + * Fields are initialized based on PCI device information and + * OS network device settings (MTU size). + */ +static int atl1e_sw_init(struct atl1e_adapter *adapter) +{ + struct atl1e_hw *hw = &adapter->hw; + struct pci_device *pdev = adapter->pdev; + u32 phy_status_data = 0; + u8 rev_id = 0; + + adapter->link_speed = SPEED_0; /* hardware init */ + adapter->link_duplex = FULL_DUPLEX; + + /* PCI config space info */ + pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); + + phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS); + /* nic type */ + if (rev_id >= 0xF0) { + hw->nic_type = athr_l2e_revB; + } else { + if (phy_status_data & PHY_STATUS_100M) + hw->nic_type = athr_l1e; + else + hw->nic_type = athr_l2e_revA; + } + + phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS); + + hw->emi_ca = !!(phy_status_data & PHY_STATUS_EMI_CA); + + hw->phy_configured = 0; + + /* need confirm */ + + hw->dmar_block = atl1e_dma_req_1024; + hw->dmaw_block = atl1e_dma_req_1024; + + netdev_link_down(adapter->netdev); + + return 0; +} + +/* + * atl1e_clean_tx_ring - free all Tx buffers for device close + * @adapter: board private structure + */ +static void atl1e_clean_tx_ring(struct atl1e_adapter *adapter) +{ + struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *) + &adapter->tx_ring; + struct atl1e_tx_buffer *tx_buffer = NULL; + u16 index, ring_count = tx_ring->count; + + if (tx_ring->desc == NULL || tx_ring->tx_buffer == NULL) + return; + + for (index = 0; index < ring_count; index++) { + tx_buffer = &tx_ring->tx_buffer[index]; + if (tx_buffer->iob) { + netdev_tx_complete(adapter->netdev, tx_buffer->iob); + tx_buffer->dma = 0; + tx_buffer->iob = NULL; + } + } + + /* Zero out Tx-buffers */ + memset(tx_ring->desc, 0, sizeof(struct atl1e_tpd_desc) * + ring_count); + memset(tx_ring->tx_buffer, 0, sizeof(struct atl1e_tx_buffer) * + ring_count); +} + +/* + * atl1e_clean_rx_ring - Free rx-reservation iobs + * @adapter: board private structure + */ +static void atl1e_clean_rx_ring(struct atl1e_adapter *adapter) +{ + struct atl1e_rx_ring *rx_ring = + (struct atl1e_rx_ring *)&adapter->rx_ring; + struct atl1e_rx_page_desc *rx_page_desc = &rx_ring->rx_page_desc; + u16 j; + + if (adapter->ring_vir_addr == NULL) + return; + + /* Zero out the descriptor ring */ + for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) { + if (rx_page_desc->rx_page[j].addr != NULL) { + memset(rx_page_desc->rx_page[j].addr, 0, + rx_ring->real_page_size); + } + } +} + +static void atl1e_cal_ring_size(struct atl1e_adapter *adapter, u32 *ring_size) +{ + *ring_size = ((u32)(adapter->tx_ring.count * + sizeof(struct atl1e_tpd_desc) + 7 + /* tx ring, qword align */ + + adapter->rx_ring.real_page_size * AT_PAGE_NUM_PER_QUEUE + + 31 + /* rx ring, 32 bytes align */ + + (1 + AT_PAGE_NUM_PER_QUEUE) * + sizeof(u32) + 3)); + /* tx, rx cmd, dword align */ +} + +static void atl1e_init_ring_resources(struct atl1e_adapter *adapter) +{ + struct atl1e_tx_ring *tx_ring = NULL; + struct atl1e_rx_ring *rx_ring = NULL; + + tx_ring = &adapter->tx_ring; + rx_ring = &adapter->rx_ring; + + rx_ring->real_page_size = adapter->rx_ring.page_size + + MAX_FRAME_SIZE + + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN; + rx_ring->real_page_size = (rx_ring->real_page_size + 31) & ~31; + atl1e_cal_ring_size(adapter, &adapter->ring_size); + + adapter->ring_vir_addr = NULL; + adapter->rx_ring.desc = NULL; + + return; +} + +/* + * Read / Write Ptr Initialize: + */ +static void atl1e_init_ring_ptrs(struct atl1e_adapter *adapter) +{ + struct atl1e_tx_ring *tx_ring = NULL; + struct atl1e_rx_ring *rx_ring = NULL; + struct atl1e_rx_page_desc *rx_page_desc = NULL; + int j; + + tx_ring = &adapter->tx_ring; + rx_ring = &adapter->rx_ring; + rx_page_desc = &rx_ring->rx_page_desc; + + tx_ring->next_to_use = 0; + tx_ring->next_to_clean = 0; + + rx_page_desc->rx_using = 0; + rx_page_desc->rx_nxseq = 0; + for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) { + *rx_page_desc->rx_page[j].write_offset_addr = 0; + rx_page_desc->rx_page[j].read_offset = 0; + } +} + +/* + * atl1e_free_ring_resources - Free Tx / RX descriptor Resources + * @adapter: board private structure + * + * Free all transmit software resources + */ +static void atl1e_free_ring_resources(struct atl1e_adapter *adapter) +{ + atl1e_clean_tx_ring(adapter); + atl1e_clean_rx_ring(adapter); + + if (adapter->ring_vir_addr) { + free_dma(adapter->ring_vir_addr, adapter->ring_size); + adapter->ring_vir_addr = NULL; + adapter->ring_dma = 0; + } + + if (adapter->tx_ring.tx_buffer) { + free(adapter->tx_ring.tx_buffer); + adapter->tx_ring.tx_buffer = NULL; + } +} + +/* + * atl1e_setup_mem_resources - allocate Tx / RX descriptor resources + * @adapter: board private structure + * + * Return 0 on success, negative on failure + */ +static int atl1e_setup_ring_resources(struct atl1e_adapter *adapter) +{ + struct atl1e_tx_ring *tx_ring; + struct atl1e_rx_ring *rx_ring; + struct atl1e_rx_page_desc *rx_page_desc; + int size, j; + u32 offset = 0; + int err = 0; + + if (adapter->ring_vir_addr != NULL) + return 0; /* alloced already */ + + tx_ring = &adapter->tx_ring; + rx_ring = &adapter->rx_ring; + + /* real ring DMA buffer */ + + size = adapter->ring_size; + adapter->ring_vir_addr = malloc_dma(adapter->ring_size, 32); + + if (adapter->ring_vir_addr == NULL) { + DBG("atl1e: out of memory allocating %d bytes for %s ring\n", + adapter->ring_size, adapter->netdev->name); + return -ENOMEM; + } + + adapter->ring_dma = virt_to_bus(adapter->ring_vir_addr); + memset(adapter->ring_vir_addr, 0, adapter->ring_size); + + rx_page_desc = &rx_ring->rx_page_desc; + + /* Init TPD Ring */ + tx_ring->dma = (adapter->ring_dma + 7) & ~7; + offset = tx_ring->dma - adapter->ring_dma; + tx_ring->desc = (struct atl1e_tpd_desc *) + (adapter->ring_vir_addr + offset); + size = sizeof(struct atl1e_tx_buffer) * (tx_ring->count); + tx_ring->tx_buffer = zalloc(size); + if (tx_ring->tx_buffer == NULL) { + DBG("atl1e: out of memory allocating %d bytes for %s txbuf\n", + size, adapter->netdev->name); + err = -ENOMEM; + goto failed; + } + + /* Init RXF-Pages */ + offset += (sizeof(struct atl1e_tpd_desc) * tx_ring->count); + offset = (offset + 31) & ~31; + + for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) { + rx_page_desc->rx_page[j].dma = + adapter->ring_dma + offset; + rx_page_desc->rx_page[j].addr = + adapter->ring_vir_addr + offset; + offset += rx_ring->real_page_size; + } + + /* Init CMB dma address */ + tx_ring->cmb_dma = adapter->ring_dma + offset; + tx_ring->cmb = (u32 *)(adapter->ring_vir_addr + offset); + offset += sizeof(u32); + + for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) { + rx_page_desc->rx_page[j].write_offset_dma = + adapter->ring_dma + offset; + rx_page_desc->rx_page[j].write_offset_addr = + adapter->ring_vir_addr + offset; + offset += sizeof(u32); + } + + if (offset > adapter->ring_size) { + DBG("atl1e: ring miscalculation! need %d > %d bytes\n", + offset, adapter->ring_size); + err = -EINVAL; + goto failed; + } + + return 0; +failed: + atl1e_free_ring_resources(adapter); + return err; +} + +static inline void atl1e_configure_des_ring(const struct atl1e_adapter *adapter) +{ + + struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw; + struct atl1e_rx_ring *rx_ring = + (struct atl1e_rx_ring *)&adapter->rx_ring; + struct atl1e_tx_ring *tx_ring = + (struct atl1e_tx_ring *)&adapter->tx_ring; + struct atl1e_rx_page_desc *rx_page_desc = NULL; + int j; + + AT_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, 0); + AT_WRITE_REG(hw, REG_TPD_BASE_ADDR_LO, tx_ring->dma); + AT_WRITE_REG(hw, REG_TPD_RING_SIZE, (u16)(tx_ring->count)); + AT_WRITE_REG(hw, REG_HOST_TX_CMB_LO, tx_ring->cmb_dma); + + rx_page_desc = &rx_ring->rx_page_desc; + + /* RXF Page Physical address / Page Length */ + AT_WRITE_REG(hw, REG_RXF0_BASE_ADDR_HI, 0); + + for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) { + u32 page_phy_addr; + u32 offset_phy_addr; + + page_phy_addr = rx_page_desc->rx_page[j].dma; + offset_phy_addr = rx_page_desc->rx_page[j].write_offset_dma; + + AT_WRITE_REG(hw, atl1e_rx_page_lo_addr_regs[j], page_phy_addr); + AT_WRITE_REG(hw, atl1e_rx_page_write_offset_regs[j], + offset_phy_addr); + AT_WRITE_REGB(hw, atl1e_rx_page_vld_regs[j], 1); + } + + /* Page Length */ + AT_WRITE_REG(hw, REG_HOST_RXFPAGE_SIZE, rx_ring->page_size); + /* Load all of base address above */ + AT_WRITE_REG(hw, REG_LOAD_PTR, 1); + + return; +} + +static inline void atl1e_configure_tx(struct atl1e_adapter *adapter) +{ + struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw; + u32 dev_ctrl_data = 0; + u32 max_pay_load = 0; + u32 jumbo_thresh = 0; + u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */ + + /* configure TXQ param */ + if (hw->nic_type != athr_l2e_revB) { + extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN; + jumbo_thresh = MAX_FRAME_SIZE + extra_size; + AT_WRITE_REG(hw, REG_TX_EARLY_TH, (jumbo_thresh + 7) >> 3); + } + + dev_ctrl_data = AT_READ_REG(hw, REG_DEVICE_CTRL); + + max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT)) & + DEVICE_CTRL_MAX_PAYLOAD_MASK; + if (max_pay_load < hw->dmaw_block) + hw->dmaw_block = max_pay_load; + + max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT)) & + DEVICE_CTRL_MAX_RREQ_SZ_MASK; + if (max_pay_load < hw->dmar_block) + hw->dmar_block = max_pay_load; + + if (hw->nic_type != athr_l2e_revB) + AT_WRITE_REGW(hw, REG_TXQ_CTRL + 2, + atl1e_pay_load_size[hw->dmar_block]); + /* enable TXQ */ + AT_WRITE_REGW(hw, REG_TXQ_CTRL, + ((TPD_BURST & TXQ_CTRL_NUM_TPD_BURST_MASK) + << TXQ_CTRL_NUM_TPD_BURST_SHIFT) + | TXQ_CTRL_ENH_MODE | TXQ_CTRL_EN); + return; +} + +static inline void atl1e_configure_rx(struct atl1e_adapter *adapter) +{ + struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw; + u32 rxf_len = 0; + u32 rxf_low = 0; + u32 rxf_high = 0; + u32 rxf_thresh_data = 0; + u32 rxq_ctrl_data = 0; + + if (hw->nic_type != athr_l2e_revB) { + AT_WRITE_REGW(hw, REG_RXQ_JMBOSZ_RRDTIM, + (u16)((RX_JUMBO_THRESH & RXQ_JMBOSZ_TH_MASK) << + RXQ_JMBOSZ_TH_SHIFT | + (1 & RXQ_JMBO_LKAH_MASK) << + RXQ_JMBO_LKAH_SHIFT)); + + rxf_len = AT_READ_REG(hw, REG_SRAM_RXF_LEN); + rxf_high = rxf_len * 4 / 5; + rxf_low = rxf_len / 5; + rxf_thresh_data = ((rxf_high & RXQ_RXF_PAUSE_TH_HI_MASK) + << RXQ_RXF_PAUSE_TH_HI_SHIFT) | + ((rxf_low & RXQ_RXF_PAUSE_TH_LO_MASK) + << RXQ_RXF_PAUSE_TH_LO_SHIFT); + + AT_WRITE_REG(hw, REG_RXQ_RXF_PAUSE_THRESH, rxf_thresh_data); + } + + /* RRS */ + AT_WRITE_REG(hw, REG_IDT_TABLE, 0); + AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, 0); + + rxq_ctrl_data |= RXQ_CTRL_PBA_ALIGN_32 | + RXQ_CTRL_CUT_THRU_EN | RXQ_CTRL_EN; + + AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data); + return; +} + +static inline void atl1e_configure_dma(struct atl1e_adapter *adapter) +{ + struct atl1e_hw *hw = &adapter->hw; + u32 dma_ctrl_data = 0; + + dma_ctrl_data = DMA_CTRL_RXCMB_EN; + dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK) + << DMA_CTRL_DMAR_BURST_LEN_SHIFT; + dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK) + << DMA_CTRL_DMAW_BURST_LEN_SHIFT; + dma_ctrl_data |= DMA_CTRL_DMAR_REQ_PRI | DMA_CTRL_DMAR_OUT_ORDER; + dma_ctrl_data |= (DMAR_DLY_CNT & DMA_CTRL_DMAR_DLY_CNT_MASK) + << DMA_CTRL_DMAR_DLY_CNT_SHIFT; + dma_ctrl_data |= (DMAW_DLY_CNT & DMA_CTRL_DMAW_DLY_CNT_MASK) + << DMA_CTRL_DMAW_DLY_CNT_SHIFT; + + AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data); + return; +} + +static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter) +{ + u32 value; + struct atl1e_hw *hw = &adapter->hw; + + /* Config MAC CTRL Register */ + value = MAC_CTRL_TX_EN | + MAC_CTRL_RX_EN ; + + if (FULL_DUPLEX == adapter->link_duplex) + value |= MAC_CTRL_DUPLX; + + value |= ((u32)((SPEED_1000 == adapter->link_speed) ? + MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) << + MAC_CTRL_SPEED_SHIFT); + value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); + + value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); + value |= ((PREAMBLE_LEN & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); + + value |= MAC_CTRL_BC_EN; + value |= MAC_CTRL_MC_ALL_EN; + + AT_WRITE_REG(hw, REG_MAC_CTRL, value); +} + +/* + * atl1e_configure - Configure Transmit&Receive Unit after Reset + * @adapter: board private structure + * + * Configure the Tx /Rx unit of the MAC after a reset. + */ +static int atl1e_configure(struct atl1e_adapter *adapter) +{ + struct atl1e_hw *hw = &adapter->hw; + u32 intr_status_data = 0; + + /* clear interrupt status */ + AT_WRITE_REG(hw, REG_ISR, ~0); + + /* 1. set MAC Address */ + atl1e_hw_set_mac_addr(hw); + + /* 2. Init the Multicast HASH table (clear) */ + AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); + AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); + + /* 3. Clear any WOL status */ + AT_WRITE_REG(hw, REG_WOL_CTRL, 0); + + /* 4. Descripter Ring BaseMem/Length/Read ptr/Write ptr + * TPD Ring/SMB/RXF0 Page CMBs, they use the same + * High 32bits memory */ + atl1e_configure_des_ring(adapter); + + /* 5. set Interrupt Moderator Timer */ + AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, IMT_VAL); + AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER2_INIT, IMT_VAL); + AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_LED_MODE | + MASTER_CTRL_ITIMER_EN | MASTER_CTRL_ITIMER2_EN); + + /* 6. rx/tx threshold to trig interrupt */ + AT_WRITE_REGW(hw, REG_TRIG_RRD_THRESH, RRD_THRESH); + AT_WRITE_REGW(hw, REG_TRIG_TPD_THRESH, TPD_THRESH); + AT_WRITE_REGW(hw, REG_TRIG_RXTIMER, RX_COUNT_DOWN); + AT_WRITE_REGW(hw, REG_TRIG_TXTIMER, TX_COUNT_DOWN); + + /* 7. set Interrupt Clear Timer */ + AT_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, ICT_VAL); + + /* 8. set MTU */ + AT_WRITE_REG(hw, REG_MTU, MAX_FRAME_SIZE + ETH_HLEN + + VLAN_HLEN + ETH_FCS_LEN); + + /* 9. config TXQ early tx threshold */ + atl1e_configure_tx(adapter); + + /* 10. config RXQ */ + atl1e_configure_rx(adapter); + + /* 11. config DMA Engine */ + atl1e_configure_dma(adapter); + + /* 12. smb timer to trig interrupt */ + AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, SMB_TIMER); + + intr_status_data = AT_READ_REG(hw, REG_ISR); + if ((intr_status_data & ISR_PHY_LINKDOWN) != 0) { + DBG("atl1e: configure failed, PCIE phy link down\n"); + return -1; + } + + AT_WRITE_REG(hw, REG_ISR, 0x7fffffff); + return 0; +} + +static inline void atl1e_clear_phy_int(struct atl1e_adapter *adapter) +{ + u16 phy_data; + + atl1e_read_phy_reg(&adapter->hw, MII_INT_STATUS, &phy_data); +} + +static int atl1e_clean_tx_irq(struct atl1e_adapter *adapter) +{ + struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *) + &adapter->tx_ring; + struct atl1e_tx_buffer *tx_buffer = NULL; + u16 hw_next_to_clean = AT_READ_REGW(&adapter->hw, REG_TPD_CONS_IDX); + u16 next_to_clean = tx_ring->next_to_clean; + + while (next_to_clean != hw_next_to_clean) { + tx_buffer = &tx_ring->tx_buffer[next_to_clean]; + + tx_buffer->dma = 0; + if (tx_buffer->iob) { + netdev_tx_complete(adapter->netdev, tx_buffer->iob); + tx_buffer->iob = NULL; + } + + if (++next_to_clean == tx_ring->count) + next_to_clean = 0; + } + + tx_ring->next_to_clean = next_to_clean; + + return 1; +} + +static struct atl1e_rx_page *atl1e_get_rx_page(struct atl1e_adapter *adapter) +{ + struct atl1e_rx_page_desc *rx_page_desc = + (struct atl1e_rx_page_desc *) &adapter->rx_ring.rx_page_desc; + u8 rx_using = rx_page_desc->rx_using; + + return (struct atl1e_rx_page *)&(rx_page_desc->rx_page[rx_using]); +} + +static void atl1e_clean_rx_irq(struct atl1e_adapter *adapter) +{ + struct net_device *netdev = adapter->netdev; + struct atl1e_rx_ring *rx_ring = (struct atl1e_rx_ring *) + &adapter->rx_ring; + struct atl1e_rx_page_desc *rx_page_desc = + (struct atl1e_rx_page_desc *) &rx_ring->rx_page_desc; + struct io_buffer *iob = NULL; + struct atl1e_rx_page *rx_page = atl1e_get_rx_page(adapter); + u32 packet_size, write_offset; + struct atl1e_recv_ret_status *prrs; + + write_offset = *(rx_page->write_offset_addr); + if (rx_page->read_offset >= write_offset) + return; + + do { + /* get new packet's rrs */ + prrs = (struct atl1e_recv_ret_status *) (rx_page->addr + + rx_page->read_offset); + /* check sequence number */ + if (prrs->seq_num != rx_page_desc->rx_nxseq) { + DBG("atl1e %s: RX sequence number error (%d != %d)\n", + netdev->name, prrs->seq_num, + rx_page_desc->rx_nxseq); + rx_page_desc->rx_nxseq++; + goto fatal_err; + } + + rx_page_desc->rx_nxseq++; + + /* error packet */ + if (prrs->pkt_flag & RRS_IS_ERR_FRAME) { + if (prrs->err_flag & (RRS_ERR_BAD_CRC | + RRS_ERR_DRIBBLE | RRS_ERR_CODE | + RRS_ERR_TRUNC)) { + /* hardware error, discard this + packet */ + netdev_rx_err(netdev, NULL, EIO); + goto skip_pkt; + } + } + + packet_size = ((prrs->word1 >> RRS_PKT_SIZE_SHIFT) & + RRS_PKT_SIZE_MASK) - ETH_FCS_LEN; + iob = alloc_iob(packet_size + NET_IP_ALIGN); + if (iob == NULL) { + DBG("atl1e %s: dropping packet under memory pressure\n", + netdev->name); + goto skip_pkt; + } + iob_reserve(iob, NET_IP_ALIGN); + memcpy(iob->data, (u8 *)(prrs + 1), packet_size); + iob_put(iob, packet_size); + + netdev_rx(netdev, iob); + +skip_pkt: + /* skip current packet whether it's ok or not. */ + rx_page->read_offset += + (((u32)((prrs->word1 >> RRS_PKT_SIZE_SHIFT) & + RRS_PKT_SIZE_MASK) + + sizeof(struct atl1e_recv_ret_status) + 31) & + 0xFFFFFFE0); + + if (rx_page->read_offset >= rx_ring->page_size) { + /* mark this page clean */ + u16 reg_addr; + u8 rx_using; + + rx_page->read_offset = + *(rx_page->write_offset_addr) = 0; + rx_using = rx_page_desc->rx_using; + reg_addr = + atl1e_rx_page_vld_regs[rx_using]; + AT_WRITE_REGB(&adapter->hw, reg_addr, 1); + rx_page_desc->rx_using ^= 1; + rx_page = atl1e_get_rx_page(adapter); + } + write_offset = *(rx_page->write_offset_addr); + } while (rx_page->read_offset < write_offset); + + return; + +fatal_err: + if (!netdev_link_ok(adapter->netdev)) + atl1e_reset(adapter); +} + +/* + * atl1e_poll - poll for completed transmissions and received packets + * @netdev: network device + */ +static void atl1e_poll(struct net_device *netdev) +{ + struct atl1e_adapter *adapter = netdev_priv(netdev); + struct atl1e_hw *hw = &adapter->hw; + int max_ints = 64; + u32 status; + + do { + status = AT_READ_REG(hw, REG_ISR); + if ((status & IMR_NORMAL_MASK) == 0) + break; + + /* link event */ + if (status & ISR_GPHY) + atl1e_clear_phy_int(adapter); + /* Ack ISR */ + AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); + + /* check if PCIE PHY Link down */ + if (status & ISR_PHY_LINKDOWN) { + DBG("atl1e: PCI-E PHY link down: %x\n", status); + if (netdev_link_ok(adapter->netdev)) { + /* reset MAC */ + atl1e_irq_reset(adapter); + atl1e_reset(adapter); + break; + } + } + + /* check if DMA read/write error */ + if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { + DBG("atl1e: PCI-E DMA RW error: %x\n", status); + atl1e_irq_reset(adapter); + atl1e_reset(adapter); + break; + } + + /* link event */ + if (status & (ISR_GPHY | ISR_MANUAL)) { + atl1e_check_link(adapter); + break; + } + + /* transmit event */ + if (status & ISR_TX_EVENT) + atl1e_clean_tx_irq(adapter); + + if (status & ISR_RX_EVENT) + atl1e_clean_rx_irq(adapter); + } while (--max_ints > 0); + + /* re-enable Interrupt*/ + AT_WRITE_REG(&adapter->hw, REG_ISR, 0); + + return; +} + +static inline u16 atl1e_tpd_avail(struct atl1e_adapter *adapter) +{ + struct atl1e_tx_ring *tx_ring = &adapter->tx_ring; + u16 next_to_use = 0; + u16 next_to_clean = 0; + + next_to_clean = tx_ring->next_to_clean; + next_to_use = tx_ring->next_to_use; + + return (u16)(next_to_clean > next_to_use) ? + (next_to_clean - next_to_use - 1) : + (tx_ring->count + next_to_clean - next_to_use - 1); +} + +/* + * get next usable tpd + * Note: should call atl1e_tdp_avail to make sure + * there is enough tpd to use + */ +static struct atl1e_tpd_desc *atl1e_get_tpd(struct atl1e_adapter *adapter) +{ + struct atl1e_tx_ring *tx_ring = &adapter->tx_ring; + u16 next_to_use = 0; + + next_to_use = tx_ring->next_to_use; + if (++tx_ring->next_to_use == tx_ring->count) + tx_ring->next_to_use = 0; + + memset(&tx_ring->desc[next_to_use], 0, sizeof(struct atl1e_tpd_desc)); + return (struct atl1e_tpd_desc *)&tx_ring->desc[next_to_use]; +} + +static struct atl1e_tx_buffer * +atl1e_get_tx_buffer(struct atl1e_adapter *adapter, struct atl1e_tpd_desc *tpd) +{ + struct atl1e_tx_ring *tx_ring = &adapter->tx_ring; + + return &tx_ring->tx_buffer[tpd - tx_ring->desc]; +} + +static void atl1e_tx_map(struct atl1e_adapter *adapter, + struct io_buffer *iob, struct atl1e_tpd_desc *tpd) +{ + struct atl1e_tx_buffer *tx_buffer = NULL; + u16 buf_len = iob_len(iob); + + tx_buffer = atl1e_get_tx_buffer(adapter, tpd); + tx_buffer->iob = iob; + tx_buffer->length = buf_len; + tx_buffer->dma = virt_to_bus(iob->data); + tpd->buffer_addr = cpu_to_le64(tx_buffer->dma); + tpd->word2 = ((tpd->word2 & ~TPD_BUFLEN_MASK) | + ((cpu_to_le32(buf_len) & TPD_BUFLEN_MASK) << + TPD_BUFLEN_SHIFT)); + tpd->word3 |= 1 << TPD_EOP_SHIFT; +} + +static void atl1e_tx_queue(struct atl1e_adapter *adapter, u16 count __unused, + struct atl1e_tpd_desc *tpd __unused) +{ + struct atl1e_tx_ring *tx_ring = &adapter->tx_ring; + wmb(); + AT_WRITE_REG(&adapter->hw, REG_MB_TPD_PROD_IDX, tx_ring->next_to_use); +} + +static int atl1e_xmit_frame(struct net_device *netdev, struct io_buffer *iob) +{ + struct atl1e_adapter *adapter = netdev_priv(netdev); + u16 tpd_req = 1; + struct atl1e_tpd_desc *tpd; + + if (!netdev_link_ok(netdev)) { + return -EINVAL; + } + + if (atl1e_tpd_avail(adapter) < tpd_req) { + return -EBUSY; + } + + tpd = atl1e_get_tpd(adapter); + + atl1e_tx_map(adapter, iob, tpd); + atl1e_tx_queue(adapter, tpd_req, tpd); + + return 0; +} + +int atl1e_up(struct atl1e_adapter *adapter) +{ + struct net_device *netdev = adapter->netdev; + int err = 0; + u32 val; + + /* hardware has been reset, we need to reload some things */ + err = atl1e_init_hw(&adapter->hw); + if (err) { + return -EIO; + } + atl1e_init_ring_ptrs(adapter); + + memcpy(adapter->hw.mac_addr, netdev->ll_addr, ETH_ALEN); + + if (atl1e_configure(adapter) != 0) { + return -EIO; + } + + atl1e_irq_disable(adapter); + + val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL); + AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, + val | MASTER_CTRL_MANUAL_INT); + + return err; +} + +void atl1e_irq(struct net_device *netdev, int enable) +{ + struct atl1e_adapter *adapter = netdev_priv(netdev); + + if (enable) + atl1e_irq_enable(adapter); + else + atl1e_irq_disable(adapter); +} + +void atl1e_down(struct atl1e_adapter *adapter) +{ + struct net_device *netdev = adapter->netdev; + + /* reset MAC to disable all RX/TX */ + atl1e_reset_hw(&adapter->hw); + mdelay(1); + + netdev_link_down(netdev); + adapter->link_speed = SPEED_0; + adapter->link_duplex = -1; + + atl1e_clean_tx_ring(adapter); + atl1e_clean_rx_ring(adapter); +} + +/* + * atl1e_open - Called when a network interface is made active + * @netdev: network interface device structure + * + * Returns 0 on success, negative value on failure + * + * The open entry point is called when a network interface is made + * active by the system (IFF_UP). At this point all resources needed + * for transmit and receive operations are allocated, the interrupt + * handler is registered with the OS, the watchdog timer is started, + * and the stack is notified that the interface is ready. + */ +static int atl1e_open(struct net_device *netdev) +{ + struct atl1e_adapter *adapter = netdev_priv(netdev); + int err; + + /* allocate rx/tx dma buffer & descriptors */ + atl1e_init_ring_resources(adapter); + err = atl1e_setup_ring_resources(adapter); + if (err) + return err; + + err = atl1e_up(adapter); + if (err) + goto err_up; + + return 0; + +err_up: + atl1e_free_ring_resources(adapter); + atl1e_reset_hw(&adapter->hw); + + return err; +} + +/* + * atl1e_close - Disables a network interface + * @netdev: network interface device structure + * + * Returns 0, this is not allowed to fail + * + * The close entry point is called when an interface is de-activated + * by the OS. The hardware is still under the drivers control, but + * needs to be disabled. A global MAC reset is issued to stop the + * hardware, and all transmit and receive resources are freed. + */ +static void atl1e_close(struct net_device *netdev) +{ + struct atl1e_adapter *adapter = netdev_priv(netdev); + + atl1e_down(adapter); + atl1e_free_ring_resources(adapter); +} + +static struct net_device_operations atl1e_netdev_ops = { + .open = atl1e_open, + .close = atl1e_close, + .transmit = atl1e_xmit_frame, + .poll = atl1e_poll, + .irq = atl1e_irq, +}; + +static void atl1e_init_netdev(struct net_device *netdev, struct pci_device *pdev) +{ + netdev_init(netdev, &atl1e_netdev_ops); + + netdev->dev = &pdev->dev; + pci_set_drvdata(pdev, netdev); +} + +/* + * atl1e_probe - Device Initialization Routine + * @pdev: PCI device information struct + * @ent: entry in atl1e_pci_tbl + * + * Returns 0 on success, negative on failure + * + * atl1e_probe initializes an adapter identified by a pci_device structure. + * The OS initialization, configuring of the adapter private structure, + * and a hardware reset occur. + */ +static int atl1e_probe(struct pci_device *pdev, + const struct pci_device_id *ent __unused) +{ + struct net_device *netdev; + struct atl1e_adapter *adapter = NULL; + static int cards_found; + + int err = 0; + + adjust_pci_device(pdev); + + netdev = alloc_etherdev(sizeof(struct atl1e_adapter)); + if (netdev == NULL) { + err = -ENOMEM; + DBG("atl1e: out of memory allocating net_device\n"); + goto err; + } + + atl1e_init_netdev(netdev, pdev); + + adapter = netdev_priv(netdev); + adapter->bd_number = cards_found; + adapter->netdev = netdev; + adapter->pdev = pdev; + adapter->hw.adapter = adapter; + if (!pdev->membase) { + err = -EIO; + DBG("atl1e: cannot map device registers\n"); + goto err_free_netdev; + } + adapter->hw.hw_addr = bus_to_virt(pdev->membase); + + /* init mii data */ + adapter->mii.dev = netdev; + adapter->mii.mdio_read = atl1e_mdio_read; + adapter->mii.mdio_write = atl1e_mdio_write; + adapter->mii.phy_id_mask = 0x1f; + adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK; + + /* get user settings */ + adapter->tx_ring.count = TX_DESC_COUNT; + adapter->rx_ring.page_size = RX_MEM_SIZE; + + atl1e_setup_pcicmd(pdev); + + /* setup the private structure */ + err = atl1e_sw_init(adapter); + if (err) { + DBG("atl1e: private data init failed\n"); + goto err_free_netdev; + } + + /* Init GPHY as early as possible due to power saving issue */ + atl1e_phy_init(&adapter->hw); + + /* reset the controller to + * put the device in a known good starting state */ + err = atl1e_reset_hw(&adapter->hw); + if (err) { + err = -EIO; + goto err_free_netdev; + } + + /* This may have been run by a zero-wait timer around + now... unclear. */ + atl1e_restart_autoneg(&adapter->hw); + + if (atl1e_read_mac_addr(&adapter->hw) != 0) { + DBG("atl1e: cannot read MAC address from EEPROM\n"); + err = -EIO; + goto err_free_netdev; + } + + memcpy(netdev->hw_addr, adapter->hw.perm_mac_addr, ETH_ALEN); + memcpy(netdev->ll_addr, adapter->hw.mac_addr, ETH_ALEN); + DBG("atl1e: Attansic L1E Ethernet controller on %s, " + "%02x:%02x:%02x:%02x:%02x:%02x\n", adapter->netdev->name, + adapter->hw.mac_addr[0], adapter->hw.mac_addr[1], + adapter->hw.mac_addr[2], adapter->hw.mac_addr[3], + adapter->hw.mac_addr[4], adapter->hw.mac_addr[5]); + + err = register_netdev(netdev); + if (err) { + DBG("atl1e: cannot register network device\n"); + goto err_free_netdev; + } + + netdev_link_down(netdev); + + cards_found++; + return 0; + +err_free_netdev: + netdev_nullify(netdev); + netdev_put(netdev); +err: + return err; +} + +/* + * atl1e_remove - Device Removal Routine + * @pdev: PCI device information struct + * + * atl1e_remove is called by the PCI subsystem to alert the driver + * that it should release a PCI device. The could be caused by a + * Hot-Plug event, or because the driver is going to be removed from + * memory. + */ +static void atl1e_remove(struct pci_device *pdev) +{ + struct net_device *netdev = pci_get_drvdata(pdev); + struct atl1e_adapter *adapter = netdev_priv(netdev); + + unregister_netdev(netdev); + atl1e_free_ring_resources(adapter); + atl1e_force_ps(&adapter->hw); + netdev_nullify(netdev); + netdev_put(netdev); +} + +struct pci_driver atl1e_driver __pci_driver = { + .ids = atl1e_pci_tbl, + .id_count = (sizeof(atl1e_pci_tbl) / sizeof(atl1e_pci_tbl[0])), + .probe = atl1e_probe, + .remove = atl1e_remove, +}; + +/********** Hardware-level functions: **********/ + +/* + * check_eeprom_exist + * return 0 if eeprom exist + */ +int atl1e_check_eeprom_exist(struct atl1e_hw *hw) +{ + u32 value; + + value = AT_READ_REG(hw, REG_SPI_FLASH_CTRL); + if (value & SPI_FLASH_CTRL_EN_VPD) { + value &= ~SPI_FLASH_CTRL_EN_VPD; + AT_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); + } + value = AT_READ_REGW(hw, REG_PCIE_CAP_LIST); + return ((value & 0xFF00) == 0x6C00) ? 0 : 1; +} + +void atl1e_hw_set_mac_addr(struct atl1e_hw *hw) +{ + u32 value; + /* + * 00-0B-6A-F6-00-DC + * 0: 6AF600DC 1: 000B + * low dword + */ + value = (((u32)hw->mac_addr[2]) << 24) | + (((u32)hw->mac_addr[3]) << 16) | + (((u32)hw->mac_addr[4]) << 8) | + (((u32)hw->mac_addr[5])) ; + AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); + /* hight dword */ + value = (((u32)hw->mac_addr[0]) << 8) | + (((u32)hw->mac_addr[1])) ; + AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); +} + +/* + * atl1e_get_permanent_address + * return 0 if get valid mac address, + */ +static int atl1e_get_permanent_address(struct atl1e_hw *hw) +{ + u32 addr[2]; + u32 i; + u32 twsi_ctrl_data; + u8 eth_addr[ETH_ALEN]; + + /* init */ + addr[0] = addr[1] = 0; + + if (!atl1e_check_eeprom_exist(hw)) { + /* eeprom exist */ + twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL); + twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART; + AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data); + for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) { + mdelay(10); + twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL); + if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0) + break; + } + if (i >= AT_TWSI_EEPROM_TIMEOUT) + return AT_ERR_TIMEOUT; + } + + /* maybe MAC-address is from BIOS */ + addr[0] = AT_READ_REG(hw, REG_MAC_STA_ADDR); + addr[1] = AT_READ_REG(hw, REG_MAC_STA_ADDR + 4); + *(u32 *) ð_addr[2] = swap32(addr[0]); + *(u16 *) ð_addr[0] = swap16(*(u16 *)&addr[1]); + + memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); + return 0; +} + +void atl1e_force_ps(struct atl1e_hw *hw) +{ + AT_WRITE_REGW(hw, REG_GPHY_CTRL, + GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET); +} + +/* + * Reads the adapter's MAC address from the EEPROM + * + * hw - Struct containing variables accessed by shared code + */ +int atl1e_read_mac_addr(struct atl1e_hw *hw) +{ + int err = 0; + + err = atl1e_get_permanent_address(hw); + if (err) + return AT_ERR_EEPROM; + memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr)); + return 0; +} + +/* + * Reads the value from a PHY register + * hw - Struct containing variables accessed by shared code + * reg_addr - address of the PHY register to read + */ +int atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data) +{ + u32 val; + int i; + + val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | + MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | + MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; + + AT_WRITE_REG(hw, REG_MDIO_CTRL, val); + + wmb(); + + for (i = 0; i < MDIO_WAIT_TIMES; i++) { + udelay(2); + val = AT_READ_REG(hw, REG_MDIO_CTRL); + if (!(val & (MDIO_START | MDIO_BUSY))) + break; + wmb(); + } + if (!(val & (MDIO_START | MDIO_BUSY))) { + *phy_data = (u16)val; + return 0; + } + + return AT_ERR_PHY; +} + +/* + * Writes a value to a PHY register + * hw - Struct containing variables accessed by shared code + * reg_addr - address of the PHY register to write + * data - data to write to the PHY + */ +int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data) +{ + int i; + u32 val; + + val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | + (reg_addr&MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | + MDIO_SUP_PREAMBLE | + MDIO_START | + MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; + + AT_WRITE_REG(hw, REG_MDIO_CTRL, val); + wmb(); + + for (i = 0; i < MDIO_WAIT_TIMES; i++) { + udelay(2); + val = AT_READ_REG(hw, REG_MDIO_CTRL); + if (!(val & (MDIO_START | MDIO_BUSY))) + break; + wmb(); + } + + if (!(val & (MDIO_START | MDIO_BUSY))) + return 0; + + return AT_ERR_PHY; +} + +/* + * atl1e_init_pcie - init PCIE module + */ +static void atl1e_init_pcie(struct atl1e_hw *hw) +{ + u32 value; + /* comment 2lines below to save more power when sususpend + value = LTSSM_TEST_MODE_DEF; + AT_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); + */ + + /* pcie flow control mode change */ + value = AT_READ_REG(hw, 0x1008); + value |= 0x8000; + AT_WRITE_REG(hw, 0x1008, value); +} +/* + * Configures PHY autoneg and flow control advertisement settings + * + * hw - Struct containing variables accessed by shared code + */ +static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw) +{ + s32 ret_val; + u16 mii_autoneg_adv_reg; + u16 mii_1000t_ctrl_reg; + + if (0 != hw->mii_autoneg_adv_reg) + return 0; + /* Read the MII Auto-Neg Advertisement Register (Address 4/9). */ + mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; + mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK; + + /* + * First we clear all the 10/100 mb speed bits in the Auto-Neg + * Advertisement Register (Address 4) and the 1000 mb speed bits in + * the 1000Base-T control Register (Address 9). + */ + mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; + mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK; + + /* Assume auto-detect media type */ + mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS | + MII_AR_10T_FD_CAPS | + MII_AR_100TX_HD_CAPS | + MII_AR_100TX_FD_CAPS); + if (hw->nic_type == athr_l1e) { + mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS; + } + + /* flow control fixed to enable all */ + mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); + + hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; + hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg; + + ret_val = atl1e_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); + if (ret_val) + return ret_val; + + if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) { + ret_val = atl1e_write_phy_reg(hw, MII_AT001_CR, + mii_1000t_ctrl_reg); + if (ret_val) + return ret_val; + } + + return 0; +} + + +/* + * Resets the PHY and make all config validate + * + * hw - Struct containing variables accessed by shared code + * + * Sets bit 15 and 12 of the MII control regiser (for F001 bug) + */ +int atl1e_phy_commit(struct atl1e_hw *hw) +{ + int ret_val; + u16 phy_data; + + phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; + + ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data); + if (ret_val) { + u32 val; + int i; + /************************************** + * pcie serdes link may be down ! + **************************************/ + for (i = 0; i < 25; i++) { + mdelay(1); + val = AT_READ_REG(hw, REG_MDIO_CTRL); + if (!(val & (MDIO_START | MDIO_BUSY))) + break; + } + + if (0 != (val & (MDIO_START | MDIO_BUSY))) { + DBG("atl1e: PCI-E link down for at least 25ms\n"); + return ret_val; + } + + DBG("atl1e: PCI-E link up after %d ms\n", i); + } + return 0; +} + +int atl1e_phy_init(struct atl1e_hw *hw) +{ + s32 ret_val; + u16 phy_val; + + if (hw->phy_configured) { + if (hw->re_autoneg) { + hw->re_autoneg = 0; + return atl1e_restart_autoneg(hw); + } + return 0; + } + + /* RESET GPHY Core */ + AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT); + mdelay(2); + AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT | + GPHY_CTRL_EXT_RESET); + mdelay(2); + + /* patches */ + /* p1. eable hibernation mode */ + ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0xB); + if (ret_val) + return ret_val; + ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0xBC00); + if (ret_val) + return ret_val; + /* p2. set Class A/B for all modes */ + ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0); + if (ret_val) + return ret_val; + phy_val = 0x02ef; + /* remove Class AB */ + /* phy_val = hw->emi_ca ? 0x02ef : 0x02df; */ + ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, phy_val); + if (ret_val) + return ret_val; + /* p3. 10B ??? */ + ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x12); + if (ret_val) + return ret_val; + ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x4C04); + if (ret_val) + return ret_val; + /* p4. 1000T power */ + ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x4); + if (ret_val) + return ret_val; + ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x8BBB); + if (ret_val) + return ret_val; + + ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x5); + if (ret_val) + return ret_val; + ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x2C46); + if (ret_val) + return ret_val; + + mdelay(1); + + /*Enable PHY LinkChange Interrupt */ + ret_val = atl1e_write_phy_reg(hw, MII_INT_CTRL, 0xC00); + if (ret_val) { + DBG("atl1e: Error enable PHY linkChange Interrupt\n"); + return ret_val; + } + /* setup AutoNeg parameters */ + ret_val = atl1e_phy_setup_autoneg_adv(hw); + if (ret_val) { + DBG("atl1e: Error Setting up Auto-Negotiation\n"); + return ret_val; + } + /* SW.Reset & En-Auto-Neg to restart Auto-Neg*/ + DBG("atl1e: Restarting Auto-Neg"); + ret_val = atl1e_phy_commit(hw); + if (ret_val) { + DBG("atl1e: Error Resetting the phy"); + return ret_val; + } + + hw->phy_configured = 1; + + return 0; +} + +/* + * Reset the transmit and receive units; mask and clear all interrupts. + * hw - Struct containing variables accessed by shared code + * return : 0 or idle status (if error) + */ +int atl1e_reset_hw(struct atl1e_hw *hw) +{ + struct atl1e_adapter *adapter = hw->adapter; + struct pci_device *pdev = adapter->pdev; + int timeout = 0; + u32 idle_status_data = 0; + u16 pci_cfg_cmd_word = 0; + + /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ + pci_read_config_word(pdev, PCI_COMMAND, &pci_cfg_cmd_word); + if ((pci_cfg_cmd_word & (PCI_COMMAND_IO | PCI_COMMAND_MEM | + PCI_COMMAND_MASTER)) + != (PCI_COMMAND_IO | PCI_COMMAND_MEM | + PCI_COMMAND_MASTER)) { + pci_cfg_cmd_word |= (PCI_COMMAND_IO | PCI_COMMAND_MEM | + PCI_COMMAND_MASTER); + pci_write_config_word(pdev, PCI_COMMAND, pci_cfg_cmd_word); + } + + /* + * Issue Soft Reset to the MAC. This will reset the chip's + * transmit, receive, DMA. It will not effect + * the current PCI configuration. The global reset bit is self- + * clearing, and should clear within a microsecond. + */ + AT_WRITE_REG(hw, REG_MASTER_CTRL, + MASTER_CTRL_LED_MODE | MASTER_CTRL_SOFT_RST); + wmb(); + mdelay(1); + + /* Wait at least 10ms for All module to be Idle */ + for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) { + idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS); + if (idle_status_data == 0) + break; + mdelay(1); + } + + if (timeout >= AT_HW_MAX_IDLE_DELAY) { + DBG("atl1e: MAC reset timeout\n"); + return AT_ERR_TIMEOUT; + } + + return 0; +} + + +/* + * Performs basic configuration of the adapter. + * + * hw - Struct containing variables accessed by shared code + * Assumes that the controller has previously been reset and is in a + * post-reset uninitialized state. Initializes multicast table, + * and Calls routines to setup link + * Leaves the transmit and receive units disabled and uninitialized. + */ +int atl1e_init_hw(struct atl1e_hw *hw) +{ + s32 ret_val = 0; + + atl1e_init_pcie(hw); + + /* Zero out the Multicast HASH table */ + /* clear the old settings from the multicast hash table */ + AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); + AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); + + ret_val = atl1e_phy_init(hw); + + return ret_val; +} + +/* + * Detects the current speed and duplex settings of the hardware. + * + * hw - Struct containing variables accessed by shared code + * speed - Speed of the connection + * duplex - Duplex setting of the connection + */ +int atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex) +{ + int err; + u16 phy_data; + + /* Read PHY Specific Status Register (17) */ + err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data); + if (err) + return err; + + if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED)) + return AT_ERR_PHY_RES; + + switch (phy_data & MII_AT001_PSSR_SPEED) { + case MII_AT001_PSSR_1000MBS: + *speed = SPEED_1000; + break; + case MII_AT001_PSSR_100MBS: + *speed = SPEED_100; + break; + case MII_AT001_PSSR_10MBS: + *speed = SPEED_10; + break; + default: + return AT_ERR_PHY_SPEED; + break; + } + + if (phy_data & MII_AT001_PSSR_DPLX) + *duplex = FULL_DUPLEX; + else + *duplex = HALF_DUPLEX; + + return 0; +} + +int atl1e_restart_autoneg(struct atl1e_hw *hw) +{ + int err = 0; + + err = atl1e_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); + if (err) + return err; + + if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) { + err = atl1e_write_phy_reg(hw, MII_AT001_CR, + hw->mii_1000t_ctrl_reg); + if (err) + return err; + } + + err = atl1e_write_phy_reg(hw, MII_BMCR, + MII_CR_RESET | MII_CR_AUTO_NEG_EN | + MII_CR_RESTART_AUTO_NEG); + return err; +} + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/b44.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/b44.c new file mode 100644 index 0000000..c48b314 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/b44.c @@ -0,0 +1,951 @@ +/* + * Copyright (c) 2008 Stefan Hajnoczi <stefanha@gmail.com> + * Copyright (c) 2008 Pantelis Koukousoulas <pktoss@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * This driver is a port of the b44 linux driver version 1.01 + * + * Copyright (c) 2002 David S. Miller <davem@redhat.com> + * Copyright (c) Pekka Pietikainen <pp@ee.oulu.fi> + * Copyright (C) 2006 Broadcom Corporation. + * + * Some ssb bits copied from version 2.0 of the b44 driver + * Copyright (c) Michael Buesch + * + * Copyright (c) a lot of people too. Please respect their work. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <errno.h> +#include <assert.h> +#include <stdio.h> +#include <unistd.h> +#include <byteswap.h> +#include <gpxe/io.h> +#include <mii.h> +#include <gpxe/iobuf.h> +#include <gpxe/malloc.h> +#include <gpxe/pci.h> +#include <gpxe/netdevice.h> +#include <gpxe/ethernet.h> +#include <gpxe/if_ether.h> +#include <gpxe/memmap.h> +#include "b44.h" + + +static inline int ring_next(int index) +{ + /* B44_RING_SIZE is a power of 2 :) */ + return (index + 1) & (B44_RING_SIZE - 1); +} + + +/* Memory-mapped I/O wrappers */ + +static inline u32 br32(const struct b44_private *bp, u32 reg) +{ + return readl(bp->regs + reg); +} + + +static inline void bw32(const struct b44_private *bp, u32 reg, u32 val) +{ + writel(val, bp->regs + reg); +} + + +static inline void bflush(const struct b44_private *bp, u32 reg, u32 timeout) +{ + readl(bp->regs + reg); + udelay(timeout); +} + + +#define VIRT_TO_B44(addr) ( virt_to_bus(addr) + SB_PCI_DMA ) + + +/** + * Return non-zero if the installed RAM is within + * the limit given and zero if it is outside. + * Hopefully will be removed soon. + */ +int phys_ram_within_limit(u64 limit) +{ + struct memory_map memmap; + struct memory_region *highest = NULL; + get_memmap(&memmap); + + highest = &memmap.regions[memmap.count - 1]; + + return (highest->end < limit); +} + + +/** + * Ring cells waiting to be processed are between 'tx_cur' and 'pending' + * indexes in the ring. + */ +static u32 pending_tx_index(struct b44_private *bp) +{ + u32 pending = br32(bp, B44_DMATX_STAT); + pending &= DMATX_STAT_CDMASK; + + pending /= sizeof(struct dma_desc); + return pending & (B44_RING_SIZE - 1); +} + + +/** + * Ring cells waiting to be processed are between 'rx_cur' and 'pending' + * indexes in the ring. + */ +static u32 pending_rx_index(struct b44_private *bp) +{ + u32 pending = br32(bp, B44_DMARX_STAT); + pending &= DMARX_STAT_CDMASK; + + pending /= sizeof(struct dma_desc); + return pending & (B44_RING_SIZE - 1); +} + + +/** + * Wait until the given bit is set/cleared. + */ +static int b44_wait_bit(struct b44_private *bp, unsigned long reg, u32 bit, + unsigned long timeout, const int clear) +{ + unsigned long i; + + for (i = 0; i < timeout; i++) { + u32 val = br32(bp, reg); + + if (clear && !(val & bit)) + break; + + if (!clear && (val & bit)) + break; + + udelay(10); + } + if (i == timeout) { + return -ENODEV; + } + return 0; +} + + +/* + * Sonics Silicon Backplane support. SSB is a mini-bus interconnecting + * so-called IP Cores. One of those cores implements the Fast Ethernet + * functionality and another one the PCI engine. + * + * You need to switch to the core you want to talk to before actually + * sending commands. + * + * See: http://bcm-v4.sipsolutions.net/Backplane for (reverse-engineered) + * specs. + */ + +static inline u32 ssb_get_core_rev(struct b44_private *bp) +{ + return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK); +} + + +static inline int ssb_is_core_up(struct b44_private *bp) +{ + return ((br32(bp, B44_SBTMSLOW) & (SSB_CORE_DOWN | SBTMSLOW_CLOCK)) + == SBTMSLOW_CLOCK); +} + + +static u32 ssb_pci_setup(struct b44_private *bp, u32 cores) +{ + u32 bar_orig, pci_rev, val; + + pci_read_config_dword(bp->pci, SSB_BAR0_WIN, &bar_orig); + pci_write_config_dword(bp->pci, SSB_BAR0_WIN, + BCM4400_PCI_CORE_ADDR); + pci_rev = ssb_get_core_rev(bp); + + val = br32(bp, B44_SBINTVEC); + val |= cores; + bw32(bp, B44_SBINTVEC, val); + + val = br32(bp, SSB_PCI_TRANS_2); + val |= SSB_PCI_PREF | SSB_PCI_BURST; + bw32(bp, SSB_PCI_TRANS_2, val); + + pci_write_config_dword(bp->pci, SSB_BAR0_WIN, bar_orig); + + return pci_rev; +} + + +static void ssb_core_disable(struct b44_private *bp) +{ + if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET) + return; + + bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK)); + b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0); + b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1); + + bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK | + SSB_CORE_DOWN)); + bflush(bp, B44_SBTMSLOW, 1); + + bw32(bp, B44_SBTMSLOW, SSB_CORE_DOWN); + bflush(bp, B44_SBTMSLOW, 1); +} + + +static void ssb_core_reset(struct b44_private *bp) +{ + u32 val; + const u32 mask = (SBTMSLOW_CLOCK | SBTMSLOW_FGC | SBTMSLOW_RESET); + + ssb_core_disable(bp); + + bw32(bp, B44_SBTMSLOW, mask); + bflush(bp, B44_SBTMSLOW, 1); + + /* Clear SERR if set, this is a hw bug workaround. */ + if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR) + bw32(bp, B44_SBTMSHIGH, 0); + + val = br32(bp, B44_SBIMSTATE); + if (val & (SBIMSTATE_BAD)) { + bw32(bp, B44_SBIMSTATE, val & ~SBIMSTATE_BAD); + } + + bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC)); + bflush(bp, B44_SBTMSLOW, 1); + + bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK)); + bflush(bp, B44_SBTMSLOW, 1); +} + + +/* + * Driver helper functions + */ + +/* + * Chip reset provides power to the b44 MAC & PCI cores, which + * is necessary for MAC register access. We only do a partial + * reset in case of transmit/receive errors (ISTAT_ERRORS) to + * avoid the chip being hung for an unnecessary long time in + * this case. + * + * Called-by: b44_close, b44_halt, b44_inithw(b44_open), b44_probe + */ +static void b44_chip_reset(struct b44_private *bp, int reset_kind) +{ + if (ssb_is_core_up(bp)) { + bw32(bp, B44_RCV_LAZY, 0); + + bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE); + + b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1); + + bw32(bp, B44_DMATX_CTRL, 0); + + bp->tx_dirty = bp->tx_cur = 0; + + if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) + b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE, + 100, 0); + + bw32(bp, B44_DMARX_CTRL, 0); + + bp->rx_cur = 0; + } else { + ssb_pci_setup(bp, SBINTVEC_ENET0); + } + + ssb_core_reset(bp); + + /* Don't enable PHY if we are only doing a partial reset. */ + if (reset_kind == B44_CHIP_RESET_PARTIAL) + return; + + /* Make PHY accessible. */ + bw32(bp, B44_MDIO_CTRL, + (MDIO_CTRL_PREAMBLE | (0x0d & MDIO_CTRL_MAXF_MASK))); + bflush(bp, B44_MDIO_CTRL, 1); + + /* Enable internal or external PHY */ + if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) { + bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL); + bflush(bp, B44_ENET_CTRL, 1); + } else { + u32 val = br32(bp, B44_DEVCTRL); + if (val & DEVCTRL_EPR) { + bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR)); + bflush(bp, B44_DEVCTRL, 100); + } + } +} + + +/** + * called by b44_poll in the error path + */ +static void b44_halt(struct b44_private *bp) +{ + /* disable ints */ + bw32(bp, B44_IMASK, 0); + bflush(bp, B44_IMASK, 1); + + DBG("b44: powering down PHY\n"); + bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN); + + /* + * Now reset the chip, but without enabling + * the MAC&PHY part of it. + * This has to be done _after_ we shut down the PHY + */ + b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL); +} + + + +/* + * Called at device open time to get the chip ready for + * packet processing. + * + * Called-by: b44_open + */ +static void b44_init_hw(struct b44_private *bp, int reset_kind) +{ + u32 val; +#define CTRL_MASK (DMARX_CTRL_ENABLE | (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)) + + b44_chip_reset(bp, B44_CHIP_RESET_FULL); + if (reset_kind == B44_FULL_RESET) { + b44_phy_reset(bp); + } + + /* Enable CRC32, set proper LED modes and power on PHY */ + bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL); + bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT)); + + /* This sets the MAC address too. */ + b44_set_rx_mode(bp->netdev); + + /* MTU + eth header + possible VLAN tag + struct rx_header */ + bw32(bp, B44_RXMAXLEN, B44_MAX_MTU + ETH_HLEN + 8 + RX_HEADER_LEN); + bw32(bp, B44_TXMAXLEN, B44_MAX_MTU + ETH_HLEN + 8 + RX_HEADER_LEN); + + bw32(bp, B44_TX_HIWMARK, TX_HIWMARK_DEFLT); + if (reset_kind == B44_PARTIAL_RESET) { + bw32(bp, B44_DMARX_CTRL, CTRL_MASK); + } else { + bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE); + bw32(bp, B44_DMATX_ADDR, VIRT_TO_B44(bp->tx)); + + bw32(bp, B44_DMARX_CTRL, CTRL_MASK); + bw32(bp, B44_DMARX_ADDR, VIRT_TO_B44(bp->rx)); + bw32(bp, B44_DMARX_PTR, B44_RX_RING_LEN_BYTES); + + bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ); + } + + val = br32(bp, B44_ENET_CTRL); + bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE)); +#undef CTRL_MASK +} + + +/*** Management of ring descriptors ***/ + + +static void b44_populate_rx_descriptor(struct b44_private *bp, u32 idx) +{ + struct rx_header *rh; + u32 ctrl, addr; + + rh = bp->rx_iobuf[idx]->data; + rh->len = 0; + rh->flags = 0; + ctrl = DESC_CTRL_LEN & (RX_PKT_BUF_SZ - RX_PKT_OFFSET); + if (idx == B44_RING_LAST) { + ctrl |= DESC_CTRL_EOT; + } + addr = VIRT_TO_B44(bp->rx_iobuf[idx]->data); + + bp->rx[idx].ctrl = cpu_to_le32(ctrl); + bp->rx[idx].addr = cpu_to_le32(addr); + bw32(bp, B44_DMARX_PTR, idx * sizeof(struct dma_desc)); +} + + +/* + * Refill RX ring descriptors with buffers. This is needed + * because during rx we are passing ownership of descriptor + * buffers to the network stack. + */ +static void b44_rx_refill(struct b44_private *bp, u32 pending) +{ + u32 i; + + // skip pending + for (i = pending + 1; i != bp->rx_cur; i = ring_next(i)) { + if (bp->rx_iobuf[i] != NULL) + continue; + + bp->rx_iobuf[i] = alloc_iob(RX_PKT_BUF_SZ); + if (!bp->rx_iobuf[i]) { + DBG("Refill rx ring failed!!\n"); + break; + } + + b44_populate_rx_descriptor(bp, i); + } +} + + +static void b44_free_rx_ring(struct b44_private *bp) +{ + u32 i; + + if (bp->rx) { + for (i = 0; i < B44_RING_SIZE; i++) { + free_iob(bp->rx_iobuf[i]); + bp->rx_iobuf[i] = NULL; + } + free_dma(bp->rx, B44_RX_RING_LEN_BYTES); + bp->rx = NULL; + } +} + + +static int b44_init_rx_ring(struct b44_private *bp) +{ + b44_free_rx_ring(bp); + + bp->rx = malloc_dma(B44_RX_RING_LEN_BYTES, B44_DMA_ALIGNMENT); + if (!bp->rx) + return -ENOMEM; + + memset(bp->rx_iobuf, 0, sizeof(bp->rx_iobuf)); + + bp->rx_iobuf[0] = alloc_iob(RX_PKT_BUF_SZ); + b44_populate_rx_descriptor(bp, 0); + b44_rx_refill(bp, 0); + + DBG("Init RX rings: rx=0x%08lx\n", VIRT_TO_B44(bp->rx)); + return 0; +} + + +static void b44_free_tx_ring(struct b44_private *bp) +{ + if (bp->tx) { + free_dma(bp->tx, B44_TX_RING_LEN_BYTES); + bp->tx = NULL; + } +} + + +static int b44_init_tx_ring(struct b44_private *bp) +{ + b44_free_tx_ring(bp); + + bp->tx = malloc_dma(B44_TX_RING_LEN_BYTES, B44_DMA_ALIGNMENT); + if (!bp->tx) + return -ENOMEM; + + memset(bp->tx, 0, B44_TX_RING_LEN_BYTES); + memset(bp->tx_iobuf, 0, sizeof(bp->tx_iobuf)); + + DBG("Init TX rings: tx=0x%08lx\n", VIRT_TO_B44(bp->tx)); + return 0; +} + + +/*** Interaction with the PHY ***/ + + +static int b44_phy_read(struct b44_private *bp, int reg, u32 * val) +{ + int err; + + u32 arg1 = (MDIO_OP_READ << MDIO_DATA_OP_SHIFT); + u32 arg2 = (bp->phy_addr << MDIO_DATA_PMD_SHIFT); + u32 arg3 = (reg << MDIO_DATA_RA_SHIFT); + u32 arg4 = (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT); + u32 argv = arg1 | arg2 | arg3 | arg4; + + bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII); + bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START | argv)); + err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0); + *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA; + + return err; +} + + +static int b44_phy_write(struct b44_private *bp, int reg, u32 val) +{ + u32 arg1 = (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT); + u32 arg2 = (bp->phy_addr << MDIO_DATA_PMD_SHIFT); + u32 arg3 = (reg << MDIO_DATA_RA_SHIFT); + u32 arg4 = (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT); + u32 arg5 = (val & MDIO_DATA_DATA); + u32 argv = arg1 | arg2 | arg3 | arg4 | arg5; + + + bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII); + bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START | argv)); + return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0); +} + + +static int b44_phy_reset(struct b44_private *bp) +{ + u32 val; + int err; + + err = b44_phy_write(bp, MII_BMCR, BMCR_RESET); + if (err) + return err; + + udelay(100); + err = b44_phy_read(bp, MII_BMCR, &val); + if (!err) { + if (val & BMCR_RESET) { + return -ENODEV; + } + } + + return 0; +} + + +/* + * The BCM44xx CAM (Content Addressable Memory) stores the MAC + * and PHY address. + */ +static void b44_cam_write(struct b44_private *bp, unsigned char *data, + int index) +{ + u32 val; + + val = ((u32) data[2]) << 24; + val |= ((u32) data[3]) << 16; + val |= ((u32) data[4]) << 8; + val |= ((u32) data[5]) << 0; + bw32(bp, B44_CAM_DATA_LO, val); + + + val = (CAM_DATA_HI_VALID | + (((u32) data[0]) << 8) | (((u32) data[1]) << 0)); + + bw32(bp, B44_CAM_DATA_HI, val); + + val = CAM_CTRL_WRITE | (index << CAM_CTRL_INDEX_SHIFT); + bw32(bp, B44_CAM_CTRL, val); + + b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1); +} + + +static void b44_set_mac_addr(struct b44_private *bp) +{ + u32 val; + bw32(bp, B44_CAM_CTRL, 0); + b44_cam_write(bp, bp->netdev->ll_addr, 0); + val = br32(bp, B44_CAM_CTRL); + bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE); +} + + +/* Read 128-bytes of EEPROM. */ +static void b44_read_eeprom(struct b44_private *bp, u8 * data) +{ + long i; + u16 *ptr = (u16 *) data; + + for (i = 0; i < 128; i += 2) + ptr[i / 2] = cpu_to_le16(readw(bp->regs + 4096 + i)); +} + + +static void b44_load_mac_and_phy_addr(struct b44_private *bp) +{ + u8 eeprom[128]; + + /* Load MAC address, note byteswapping */ + b44_read_eeprom(bp, &eeprom[0]); + bp->netdev->hw_addr[0] = eeprom[79]; + bp->netdev->hw_addr[1] = eeprom[78]; + bp->netdev->hw_addr[2] = eeprom[81]; + bp->netdev->hw_addr[3] = eeprom[80]; + bp->netdev->hw_addr[4] = eeprom[83]; + bp->netdev->hw_addr[5] = eeprom[82]; + + /* Load PHY address */ + bp->phy_addr = eeprom[90] & 0x1f; +} + + +static void b44_set_rx_mode(struct net_device *netdev) +{ + struct b44_private *bp = netdev_priv(netdev); + unsigned char zero[6] = { 0, 0, 0, 0, 0, 0 }; + u32 val; + int i; + + val = br32(bp, B44_RXCONFIG); + val &= ~RXCONFIG_PROMISC; + val |= RXCONFIG_ALLMULTI; + + b44_set_mac_addr(bp); + + for (i = 1; i < 64; i++) + b44_cam_write(bp, zero, i); + + bw32(bp, B44_RXCONFIG, val); + val = br32(bp, B44_CAM_CTRL); + bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE); +} + + +/*** Implementation of gPXE driver callbacks ***/ + +/** + * Probe device + * + * @v pci PCI device + * @v id Matching entry in ID table + * @ret rc Return status code + */ +static int b44_probe(struct pci_device *pci, const struct pci_device_id *id) +{ + struct net_device *netdev; + struct b44_private *bp; + int rc; + + /* + * Bail out if more than 1GB of physical RAM is installed. + * This limitation will be removed later when dma mapping + * is merged into mainline. + */ + if (!phys_ram_within_limit(B44_30BIT_DMA_MASK)) { + DBG("Sorry, this version of the driver does not\n" + "support systems with more than 1GB of RAM.\n"); + return -ENOMEM; + } + + /* Set up netdev */ + netdev = alloc_etherdev(sizeof(*bp)); + if (!netdev) + return -ENOMEM; + + netdev_init(netdev, &b44_operations); + pci_set_drvdata(pci, netdev); + netdev->dev = &pci->dev; + + /* Set up private data */ + bp = netdev_priv(netdev); + memset(bp, 0, sizeof(*bp)); + bp->netdev = netdev; + bp->pci = pci; + + /* Map device registers */ + bp->regs = ioremap(pci->membase, B44_REGS_SIZE); + if (!bp->regs) { + netdev_put(netdev); + return -ENOMEM; + } + + /* Enable PCI bus mastering */ + adjust_pci_device(pci); + + b44_load_mac_and_phy_addr(bp); + + /* Link management currently not implemented */ + netdev_link_up(netdev); + + rc = register_netdev(netdev); + if (rc != 0) { + iounmap(bp->regs); + netdev_put(netdev); + return rc; + } + + b44_chip_reset(bp, B44_CHIP_RESET_FULL); + + DBG("b44 %s (%04x:%04x) regs=%p MAC=%s\n", id->name, id->vendor, + id->device, bp->regs, eth_ntoa(netdev->ll_addr)); + + return 0; +} + + +/** + * Remove device + * + * @v pci PCI device + */ +static void b44_remove(struct pci_device *pci) +{ + struct net_device *netdev = pci_get_drvdata(pci); + struct b44_private *bp = netdev_priv(netdev); + + ssb_core_disable(bp); + unregister_netdev(netdev); + iounmap(bp->regs); + netdev_nullify(netdev); + netdev_put(netdev); +} + + +/** Enable or disable interrupts + * + * @v netdev Network device + * @v enable Interrupts should be enabled + */ +static void b44_irq(struct net_device *netdev, int enable) +{ + struct b44_private *bp = netdev_priv(netdev); + + /* Interrupt mask specifies which events generate interrupts */ + bw32(bp, B44_IMASK, enable ? IMASK_DEF : IMASK_DISABLE); +} + + +/** Open network device + * + * @v netdev Network device + * @ret rc Return status code + */ +static int b44_open(struct net_device *netdev) +{ + struct b44_private *bp = netdev_priv(netdev); + int rc; + + rc = b44_init_tx_ring(bp); + if (rc != 0) + return rc; + + rc = b44_init_rx_ring(bp); + if (rc != 0) + return rc; + + b44_init_hw(bp, B44_FULL_RESET); + + /* Disable interrupts */ + b44_irq(netdev, 0); + + return 0; +} + + +/** Close network device + * + * @v netdev Network device + */ +static void b44_close(struct net_device *netdev) +{ + struct b44_private *bp = netdev_priv(netdev); + + b44_chip_reset(bp, B44_FULL_RESET); + b44_free_tx_ring(bp); + b44_free_rx_ring(bp); +} + + +/** Transmit packet + * + * @v netdev Network device + * @v iobuf I/O buffer + * @ret rc Return status code + */ +static int b44_transmit(struct net_device *netdev, struct io_buffer *iobuf) +{ + struct b44_private *bp = netdev_priv(netdev); + u32 cur = bp->tx_cur; + u32 ctrl; + + /* Check for TX ring overflow */ + if (bp->tx[cur].ctrl) { + DBG("tx overflow\n"); + return -ENOBUFS; + } + + /* Will call netdev_tx_complete() on the iobuf later */ + bp->tx_iobuf[cur] = iobuf; + + /* Set up TX descriptor */ + ctrl = (iob_len(iobuf) & DESC_CTRL_LEN) | + DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF; + + if (cur == B44_RING_LAST) + ctrl |= DESC_CTRL_EOT; + + bp->tx[cur].ctrl = cpu_to_le32(ctrl); + bp->tx[cur].addr = cpu_to_le32(VIRT_TO_B44(iobuf->data)); + + /* Update next available descriptor index */ + cur = ring_next(cur); + bp->tx_cur = cur; + wmb(); + + /* Tell card that a new TX descriptor is ready */ + bw32(bp, B44_DMATX_PTR, cur * sizeof(struct dma_desc)); + return 0; +} + + +/** Recycles sent TX descriptors and notifies network stack + * + * @v bp Driver state + */ +static void b44_tx_complete(struct b44_private *bp) +{ + u32 cur, i; + + cur = pending_tx_index(bp); + + for (i = bp->tx_dirty; i != cur; i = ring_next(i)) { + /* Free finished frame */ + netdev_tx_complete(bp->netdev, bp->tx_iobuf[i]); + bp->tx_iobuf[i] = NULL; + + /* Clear TX descriptor */ + bp->tx[i].ctrl = 0; + bp->tx[i].addr = 0; + } + bp->tx_dirty = cur; +} + + +static void b44_process_rx_packets(struct b44_private *bp) +{ + struct io_buffer *iob; /* received data */ + struct rx_header *rh; + u32 pending, i; + u16 len; + + pending = pending_rx_index(bp); + + for (i = bp->rx_cur; i != pending; i = ring_next(i)) { + iob = bp->rx_iobuf[i]; + if (iob == NULL) + break; + + rh = iob->data; + len = le16_to_cpu(rh->len); + + /* + * Guard against incompletely written RX descriptors. + * Without this, things can get really slow! + */ + if (len == 0) + break; + + /* Discard CRC that is generated by the card */ + len -= 4; + + /* Check for invalid packets and errors */ + if (len > RX_PKT_BUF_SZ - RX_PKT_OFFSET || + (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) { + DBG("rx error len=%d flags=%04x\n", len, + cpu_to_le16(rh->flags)); + rh->len = 0; + rh->flags = 0; + netdev_rx_err(bp->netdev, iob, -EINVAL); + continue; + } + + /* Clear RX descriptor */ + rh->len = 0; + rh->flags = 0; + bp->rx_iobuf[i] = NULL; + + /* Hand off the IO buffer to the network stack */ + iob_reserve(iob, RX_PKT_OFFSET); + iob_put(iob, len); + netdev_rx(bp->netdev, iob); + } + bp->rx_cur = i; + b44_rx_refill(bp, pending_rx_index(bp)); +} + + +/** Poll for completed and received packets + * + * @v netdev Network device + */ +static void b44_poll(struct net_device *netdev) +{ + struct b44_private *bp = netdev_priv(netdev); + u32 istat; + + /* Interrupt status */ + istat = br32(bp, B44_ISTAT); + istat &= IMASK_DEF; /* only the events we care about */ + + if (!istat) + return; + if (istat & ISTAT_TX) + b44_tx_complete(bp); + if (istat & ISTAT_RX) + b44_process_rx_packets(bp); + if (istat & ISTAT_ERRORS) { + DBG("b44 error istat=0x%08x\n", istat); + + /* Reset B44 core partially to avoid long waits */ + b44_irq(bp->netdev, 0); + b44_halt(bp); + b44_init_tx_ring(bp); + b44_init_rx_ring(bp); + b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY); + } + + /* Acknowledge interrupt */ + bw32(bp, B44_ISTAT, 0); + bflush(bp, B44_ISTAT, 1); +} + + +static struct net_device_operations b44_operations = { + .open = b44_open, + .close = b44_close, + .transmit = b44_transmit, + .poll = b44_poll, + .irq = b44_irq, +}; + + +static struct pci_device_id b44_nics[] = { + PCI_ROM(0x14e4, 0x4401, "BCM4401", "BCM4401", 0), + PCI_ROM(0x14e4, 0x170c, "BCM4401-B0", "BCM4401-B0", 0), + PCI_ROM(0x14e4, 0x4402, "BCM4401-B1", "BCM4401-B1", 0), +}; + + +struct pci_driver b44_driver __pci_driver = { + .ids = b44_nics, + .id_count = sizeof b44_nics / sizeof b44_nics[0], + .probe = b44_probe, + .remove = b44_remove, +}; diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/b44.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/b44.h new file mode 100644 index 0000000..b5afcbd --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/b44.h @@ -0,0 +1,470 @@ +/* + * Copyright (c) 2008 Stefan Hajnoczi <stefanha@gmail.com> + * Copyright (c) 2008 Pantelis Koukousoulas <pktoss@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * This driver is a port of the b44 linux driver version 1.01 + * + * Copyright (c) 2002 David S. Miller <davem@redhat.com> + * Copyright (c) Pekka Pietikainen <pp@ee.oulu.fi> + * Copyright (C) 2006 Broadcom Corporation. + * + * Some ssb bits copied from version 2.0 of the b44 driver + * Copyright (c) Michael Buesch + * + * Copyright (c) a lot of people too. Please respect their work. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#ifndef _B44_H +#define _B44_H + +/* BCM44xx Register layout */ +#define B44_DEVCTRL 0x0000UL /* Device Control */ +#define DEVCTRL_MPM 0x00000040 /* MP PME Enable (B0 only) */ +#define DEVCTRL_PFE 0x00000080 /* Pattern Filtering Enable */ +#define DEVCTRL_IPP 0x00000400 /* Internal EPHY Present */ +#define DEVCTRL_EPR 0x00008000 /* EPHY Reset */ +#define DEVCTRL_PME 0x00001000 /* PHY Mode Enable */ +#define DEVCTRL_PMCE 0x00002000 /* PHY Mode Clocks Enable */ +#define DEVCTRL_PADDR 0x0007c000 /* PHY Address */ +#define DEVCTRL_PADDR_SHIFT 18 +#define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */ +#define B44_WKUP_LEN 0x0010UL /* Wakeup Length */ +#define WKUP_LEN_P0_MASK 0x0000007f /* Pattern 0 */ +#define WKUP_LEN_D0 0x00000080 +#define WKUP_LEN_P1_MASK 0x00007f00 /* Pattern 1 */ +#define WKUP_LEN_P1_SHIFT 8 +#define WKUP_LEN_D1 0x00008000 +#define WKUP_LEN_P2_MASK 0x007f0000 /* Pattern 2 */ +#define WKUP_LEN_P2_SHIFT 16 +#define WKUP_LEN_D2 0x00000000 +#define WKUP_LEN_P3_MASK 0x7f000000 /* Pattern 3 */ +#define WKUP_LEN_P3_SHIFT 24 +#define WKUP_LEN_D3 0x80000000 +#define WKUP_LEN_DISABLE 0x80808080 +#define WKUP_LEN_ENABLE_TWO 0x80800000 +#define WKUP_LEN_ENABLE_THREE 0x80000000 +#define B44_ISTAT 0x0020UL /* Interrupt Status */ +#define ISTAT_LS 0x00000020 /* Link Change (B0 only) */ +#define ISTAT_PME 0x00000040 /* Power Management Event */ +#define ISTAT_TO 0x00000080 /* General Purpose Timeout */ +#define ISTAT_DSCE 0x00000400 /* Descriptor Error */ +#define ISTAT_DATAE 0x00000800 /* Data Error */ +#define ISTAT_DPE 0x00001000 /* Descr. Protocol Error */ +#define ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */ +#define ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */ +#define ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */ +#define ISTAT_RX 0x00010000 /* RX Interrupt */ +#define ISTAT_TX 0x01000000 /* TX Interrupt */ +#define ISTAT_EMAC 0x04000000 /* EMAC Interrupt */ +#define ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */ +#define ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */ +#define ISTAT_ERRORS (ISTAT_DSCE|ISTAT_DATAE|ISTAT_DPE|\ + ISTAT_RDU|ISTAT_RFO|ISTAT_TFU) +#define B44_IMASK 0x0024UL /* Interrupt Mask */ +#define IMASK_DEF (ISTAT_ERRORS | ISTAT_RX | ISTAT_TX) +#define IMASK_DISABLE 0 +#define B44_GPTIMER 0x0028UL /* General Purpose Timer */ +#define B44_ADDR_LO 0x0088UL /* ENET Address Lo (B0 only) */ +#define B44_ADDR_HI 0x008CUL /* ENET Address Hi (B0 only) */ +#define B44_FILT_ADDR 0x0090UL /* ENET Filter Address */ +#define B44_FILT_DATA 0x0094UL /* ENET Filter Data */ +#define B44_TXBURST 0x00A0UL /* TX Max Burst Length */ +#define B44_RXBURST 0x00A4UL /* RX Max Burst Length */ +#define B44_MAC_CTRL 0x00A8UL /* MAC Control */ +#define MAC_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */ +#define MAC_CTRL_PHY_PDOWN 0x00000004 /* Onchip EPHY Powerdown */ +#define MAC_CTRL_PHY_EDET 0x00000008 /* Onchip EPHY Energy Detected*/ +#define MAC_CTRL_PHY_LEDCTRL 0x000000e0 /* Onchip EPHY LED Control */ +#define MAC_CTRL_PHY_LEDCTRL_SHIFT 5 +#define B44_MAC_FLOW 0x00ACUL /* MAC Flow Control */ +#define MAC_FLOW_RX_HI_WATER 0x000000ff /* Receive FIFO HI Water Mark */ +#define MAC_FLOW_PAUSE_ENAB 0x00008000 /* Enbl Pause Frm Generation */ +#define B44_RCV_LAZY 0x0100UL /* Lazy Interrupt Control */ +#define RCV_LAZY_TO_MASK 0x00ffffff /* Timeout */ +#define RCV_LAZY_FC_MASK 0xff000000 /* Frame Count */ +#define RCV_LAZY_FC_SHIFT 24 +#define B44_DMATX_CTRL 0x0200UL /* DMA TX Control */ +#define DMATX_CTRL_ENABLE 0x00000001 /* Enable */ +#define DMATX_CTRL_SUSPEND 0x00000002 /* Suepend Request */ +#define DMATX_CTRL_LPBACK 0x00000004 /* Loopback Enable */ +#define DMATX_CTRL_FAIRPRIOR 0x00000008 /* Fair Priority */ +#define DMATX_CTRL_FLUSH 0x00000010 /* Flush Request */ +#define B44_DMATX_ADDR 0x0204UL /* DMA TX Descriptor Ring Addr */ +#define B44_DMATX_PTR 0x0208UL /* DMA TX Last Posted Desc. */ +#define B44_DMATX_STAT 0x020CUL /* DMA TX Cur Actve Desc. + Sts */ +#define DMATX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ +#define DMATX_STAT_SMASK 0x0000f000 /* State Mask */ +#define DMATX_STAT_SDISABLED 0x00000000 /* State Disabled */ +#define DMATX_STAT_SACTIVE 0x00001000 /* State Active */ +#define DMATX_STAT_SIDLE 0x00002000 /* State Idle Wait */ +#define DMATX_STAT_SSTOPPED 0x00003000 /* State Stopped */ +#define DMATX_STAT_SSUSP 0x00004000 /* State Suspend Pending */ +#define DMATX_STAT_EMASK 0x000f0000 /* Error Mask */ +#define DMATX_STAT_ENONE 0x00000000 /* Error None */ +#define DMATX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ +#define DMATX_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */ +#define DMATX_STAT_EBEBR 0x00030000 /* Bus Error on Buffer Read */ +#define DMATX_STAT_EBEDA 0x00040000 /* Bus Error on Desc. Access */ +#define DMATX_STAT_FLUSHED 0x00100000 /* Flushed */ +#define B44_DMARX_CTRL 0x0210UL /* DMA RX Control */ +#define DMARX_CTRL_ENABLE 0x00000001 /* Enable */ +#define DMARX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */ +#define DMARX_CTRL_ROSHIFT 1 /* Receive Offset Shift */ +#define B44_DMARX_ADDR 0x0214UL /* DMA RX Descriptor Ring Addr */ +#define B44_DMARX_PTR 0x0218UL /* DMA RX Last Posted Desc */ +#define B44_DMARX_STAT 0x021CUL /* Cur Active Desc. + Status */ +#define DMARX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ +#define DMARX_STAT_SMASK 0x0000f000 /* State Mask */ +#define DMARX_STAT_SDISABLED 0x00000000 /* State Disbaled */ +#define DMARX_STAT_SACTIVE 0x00001000 /* State Active */ +#define DMARX_STAT_SIDLE 0x00002000 /* State Idle Wait */ +#define DMARX_STAT_SSTOPPED 0x00003000 /* State Stopped */ +#define DMARX_STAT_EMASK 0x000f0000 /* Error Mask */ +#define DMARX_STAT_ENONE 0x00000000 /* Error None */ +#define DMARX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ +#define DMARX_STAT_EDFO 0x00020000 /* Error Data FIFO Overflow */ +#define DMARX_STAT_EBEBW 0x00030000 /* Error on Buffer Write */ +#define DMARX_STAT_EBEDA 0x00040000 /* Bus Error on Desc. Access */ +#define B44_DMAFIFO_AD 0x0220UL /* DMA FIFO Diag Address */ +#define DMAFIFO_AD_OMASK 0x0000ffff /* Offset Mask */ +#define DMAFIFO_AD_SMASK 0x000f0000 /* Select Mask */ +#define DMAFIFO_AD_SXDD 0x00000000 /* Select Transmit DMA Data */ +#define DMAFIFO_AD_SXDP 0x00010000 /* Sel Transmit DMA Pointers */ +#define DMAFIFO_AD_SRDD 0x00040000 /* Select Receive DMA Data */ +#define DMAFIFO_AD_SRDP 0x00050000 /* Sel Receive DMA Pointers */ +#define DMAFIFO_AD_SXFD 0x00080000 /* Select Transmit FIFO Data */ +#define DMAFIFO_AD_SXFP 0x00090000 /* Sel Transmit FIFO Pointers */ +#define DMAFIFO_AD_SRFD 0x000c0000 /* Select Receive FIFO Data */ +#define DMAFIFO_AD_SRFP 0x000c0000 /* Sel Receive FIFO Pointers */ +#define B44_DMAFIFO_LO 0x0224UL /* DMA FIFO Diag Low Data */ +#define B44_DMAFIFO_HI 0x0228UL /* DMA FIFO Diag High Data */ +#define B44_RXCONFIG 0x0400UL /* EMAC RX Config */ +#define RXCONFIG_DBCAST 0x00000001 /* Disable Broadcast */ +#define RXCONFIG_ALLMULTI 0x00000002 /* Accept All Multicast */ +#define RXCONFIG_NORX_WHILE_TX 0x00000004 /* Rcv Disble While TX */ +#define RXCONFIG_PROMISC 0x00000008 /* Promiscuous Enable */ +#define RXCONFIG_LPBACK 0x00000010 /* Loopback Enable */ +#define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */ +#define RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept UFC Frame */ +#define RXCONFIG_RFILT 0x00000080 /* Reject Filter */ +#define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */ +#define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */ +#define B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */ +#define MDIO_CTRL_MAXF_MASK 0x0000007f /* MDC Frequency */ +#define MDIO_CTRL_PREAMBLE 0x00000080 /* MII Preamble Enable */ +#define B44_MDIO_DATA 0x0414UL /* EMAC MDIO Data */ +#define MDIO_DATA_DATA 0x0000ffff /* R/W Data */ +#define MDIO_DATA_TA_MASK 0x00030000 /* Turnaround Value */ +#define MDIO_DATA_TA_SHIFT 16 +#define MDIO_TA_VALID 2 +#define MDIO_DATA_RA_MASK 0x007c0000 /* Register Address */ +#define MDIO_DATA_RA_SHIFT 18 +#define MDIO_DATA_PMD_MASK 0x0f800000 /* Physical Media Device */ +#define MDIO_DATA_PMD_SHIFT 23 +#define MDIO_DATA_OP_MASK 0x30000000 /* Opcode */ +#define MDIO_DATA_OP_SHIFT 28 +#define MDIO_OP_WRITE 1 +#define MDIO_OP_READ 2 +#define MDIO_DATA_SB_MASK 0xc0000000 /* Start Bits */ +#define MDIO_DATA_SB_SHIFT 30 +#define MDIO_DATA_SB_START 0x40000000 /* Start Of Frame */ +#define B44_EMAC_IMASK 0x0418UL /* EMAC Interrupt Mask */ +#define B44_EMAC_ISTAT 0x041CUL /* EMAC Interrupt Status */ +#define EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */ +#define EMAC_INT_MIB 0x00000002 /* MIB Interrupt */ +#define EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */ +#define B44_CAM_DATA_LO 0x0420UL /* EMAC CAM Data Low */ +#define B44_CAM_DATA_HI 0x0424UL /* EMAC CAM Data High */ +#define CAM_DATA_HI_VALID 0x00010000 /* Valid Bit */ +#define B44_CAM_CTRL 0x0428UL /* EMAC CAM Control */ +#define CAM_CTRL_ENABLE 0x00000001 /* CAM Enable */ +#define CAM_CTRL_MSEL 0x00000002 /* Mask Select */ +#define CAM_CTRL_READ 0x00000004 /* Read */ +#define CAM_CTRL_WRITE 0x00000008 /* Read */ +#define CAM_CTRL_INDEX_MASK 0x003f0000 /* Index Mask */ +#define CAM_CTRL_INDEX_SHIFT 16 +#define CAM_CTRL_BUSY 0x80000000 /* CAM Busy */ +#define B44_ENET_CTRL 0x042CUL /* EMAC ENET Control */ +#define ENET_CTRL_ENABLE 0x00000001 /* EMAC Enable */ +#define ENET_CTRL_DISABLE 0x00000002 /* EMAC Disable */ +#define ENET_CTRL_SRST 0x00000004 /* EMAC Soft Reset */ +#define ENET_CTRL_EPSEL 0x00000008 /* External PHY Select */ +#define B44_TX_CTRL 0x0430UL /* EMAC TX Control */ +#define TX_CTRL_DUPLEX 0x00000001 /* Full Duplex */ +#define TX_CTRL_FMODE 0x00000002 /* Flow Mode */ +#define TX_CTRL_SBENAB 0x00000004 /* Single Backoff Enable */ +#define TX_CTRL_SMALL_SLOT 0x00000008 /* Small Slottime */ +#define B44_TX_HIWMARK 0x0434UL /* EMAC TX High Watermark */ +#define TX_HIWMARK_DEFLT 56 /* Default used in all drivers */ +#define B44_MIB_CTRL 0x0438UL /* EMAC MIB Control */ +#define MIB_CTRL_CLR_ON_READ 0x00000001 /* Autoclear on Read */ +#define B44_TX_GOOD_O 0x0500UL /* MIB TX Good Octets */ +#define B44_TX_GOOD_P 0x0504UL /* MIB TX Good Packets */ +#define B44_TX_O 0x0508UL /* MIB TX Octets */ +#define B44_TX_P 0x050CUL /* MIB TX Packets */ +#define B44_TX_BCAST 0x0510UL /* MIB TX Broadcast Packets */ +#define B44_TX_MCAST 0x0514UL /* MIB TX Multicast Packets */ +#define B44_TX_64 0x0518UL /* MIB TX <= 64 byte Packets */ +#define B44_TX_65_127 0x051CUL /* MIB TX 65 to 127 byte Pkts */ +#define B44_TX_128_255 0x0520UL /* MIB TX 128 to 255 byte Pkts */ +#define B44_TX_256_511 0x0524UL /* MIB TX 256 to 511 byte Pkts */ +#define B44_TX_512_1023 0x0528UL /* MIB TX 512 to 1023 byte Pkts */ +#define B44_TX_1024_MAX 0x052CUL /* MIB TX 1024 to max byte Pkts */ +#define B44_TX_JABBER 0x0530UL /* MIB TX Jabber Packets */ +#define B44_TX_OSIZE 0x0534UL /* MIB TX Oversize Packets */ +#define B44_TX_FRAG 0x0538UL /* MIB TX Fragment Packets */ +#define B44_TX_URUNS 0x053CUL /* MIB TX Underruns */ +#define B44_TX_TCOLS 0x0540UL /* MIB TX Total Collisions */ +#define B44_TX_SCOLS 0x0544UL /* MIB TX Single Collisions */ +#define B44_TX_MCOLS 0x0548UL /* MIB TX Multiple Collisions */ +#define B44_TX_ECOLS 0x054CUL /* MIB TX Excessive Collisions */ +#define B44_TX_LCOLS 0x0550UL /* MIB TX Late Collisions */ +#define B44_TX_DEFERED 0x0554UL /* MIB TX Defered Packets */ +#define B44_TX_CLOST 0x0558UL /* MIB TX Carrier Lost */ +#define B44_TX_PAUSE 0x055CUL /* MIB TX Pause Packets */ +#define B44_RX_GOOD_O 0x0580UL /* MIB RX Good Octets */ +#define B44_RX_GOOD_P 0x0584UL /* MIB RX Good Packets */ +#define B44_RX_O 0x0588UL /* MIB RX Octets */ +#define B44_RX_P 0x058CUL /* MIB RX Packets */ +#define B44_RX_BCAST 0x0590UL /* MIB RX Broadcast Packets */ +#define B44_RX_MCAST 0x0594UL /* MIB RX Multicast Packets */ +#define B44_RX_64 0x0598UL /* MIB RX <= 64 byte Packets */ +#define B44_RX_65_127 0x059CUL /* MIB RX 65 to 127 byte Pkts */ +#define B44_RX_128_255 0x05A0UL /* MIB RX 128 to 255 byte Pkts */ +#define B44_RX_256_511 0x05A4UL /* MIB RX 256 to 511 byte Pkts */ +#define B44_RX_512_1023 0x05A8UL /* MIB RX 512 to 1023 byte Pkts */ +#define B44_RX_1024_MAX 0x05ACUL /* MIB RX 1024 to max byte Pkts */ +#define B44_RX_JABBER 0x05B0UL /* MIB RX Jabber Packets */ +#define B44_RX_OSIZE 0x05B4UL /* MIB RX Oversize Packets */ +#define B44_RX_FRAG 0x05B8UL /* MIB RX Fragment Packets */ +#define B44_RX_MISS 0x05BCUL /* MIB RX Missed Packets */ +#define B44_RX_CRCA 0x05C0UL /* MIB RX CRC Align Errors */ +#define B44_RX_USIZE 0x05C4UL /* MIB RX Undersize Packets */ +#define B44_RX_CRC 0x05C8UL /* MIB RX CRC Errors */ +#define B44_RX_ALIGN 0x05CCUL /* MIB RX Align Errors */ +#define B44_RX_SYM 0x05D0UL /* MIB RX Symbol Errors */ +#define B44_RX_PAUSE 0x05D4UL /* MIB RX Pause Packets */ +#define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */ + +/* Sonics Silicon backplane register definitions */ +#define B44_SBIMSTATE 0x0F90UL /* SB Initiator Agent State */ +#define SBIMSTATE_PC 0x0000000f /* Pipe Count */ +#define SBIMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */ +#define SBIMSTATE_AP_BOTH 0x00000000 /* both timeslices and token */ +#define SBIMSTATE_AP_TS 0x00000010 /* Use timeslices only */ +#define SBIMSTATE_AP_TK 0x00000020 /* Use token only */ +#define SBIMSTATE_AP_RSV 0x00000030 /* Reserved */ +#define SBIMSTATE_IBE 0x00020000 /* In Band Error */ +#define SBIMSTATE_TO 0x00040000 /* Timeout */ +#define SBIMSTATE_BAD ( SBIMSTATE_IBE | SBIMSTATE_TO ) +#define B44_SBINTVEC 0x0F94UL /* SB Interrupt Mask */ +#define SBINTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ +#define SBINTVEC_ENET0 0x00000002 /* Enable ints for enet 0 */ +#define SBINTVEC_ILINE20 0x00000004 /* Enable ints for iline20 */ +#define SBINTVEC_CODEC 0x00000008 /* Enable ints for v90 codec */ +#define SBINTVEC_USB 0x00000010 /* Enable intts for usb */ +#define SBINTVEC_EXTIF 0x00000020 /* Enable ints for ext i/f */ +#define SBINTVEC_ENET1 0x00000040 /* Enable ints for enet 1 */ +#define B44_SBTMSLOW 0x0F98UL /* SB Target State Low */ +#define SBTMSLOW_RESET 0x00000001 /* Reset */ +#define SBTMSLOW_REJECT 0x00000002 /* Reject */ +#define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */ +#define SBTMSLOW_FGC 0x00020000 /* Force Gated Clocks On */ +#define SBTMSLOW_PE 0x40000000 /* Power Management Enable */ +#define SBTMSLOW_BE 0x80000000 /* BIST Enable */ +#define B44_SBTMSHIGH 0x0F9CUL /* SB Target State High */ +#define SBTMSHIGH_SERR 0x00000001 /* S-error */ +#define SBTMSHIGH_INT 0x00000002 /* Interrupt */ +#define SBTMSHIGH_BUSY 0x00000004 /* Busy */ +#define SBTMSHIGH_GCR 0x20000000 /* Gated Clock Request */ +#define SBTMSHIGH_BISTF 0x40000000 /* BIST Failed */ +#define SBTMSHIGH_BISTD 0x80000000 /* BIST Done */ +#define B44_SBIDHIGH 0x0FFCUL /* SB Identification High */ +#define SBIDHIGH_RC_MASK 0x0000000f /* Revision Code */ +#define SBIDHIGH_CC_MASK 0x0000fff0 /* Core Code */ +#define SBIDHIGH_CC_SHIFT 4 +#define SBIDHIGH_VC_MASK 0xffff0000 /* Vendor Code */ +#define SBIDHIGH_VC_SHIFT 16 + +/* SSB PCI config space registers. */ +#define SSB_PMCSR 0x44 +#define SSB_PE 0x100 +#define SSB_BAR0_WIN 0x80 +#define SSB_BAR1_WIN 0x84 +#define SSB_SPROM_CONTROL 0x88 +#define SSB_BAR1_CONTROL 0x8c + +/* SSB core and host control registers. */ +#define SSB_CONTROL 0x0000UL +#define SSB_ARBCONTROL 0x0010UL +#define SSB_ISTAT 0x0020UL +#define SSB_IMASK 0x0024UL +#define SSB_MBOX 0x0028UL +#define SSB_BCAST_ADDR 0x0050UL +#define SSB_BCAST_DATA 0x0054UL +#define SSB_PCI_TRANS_0 0x0100UL +#define SSB_PCI_TRANS_1 0x0104UL +#define SSB_PCI_TRANS_2 0x0108UL +#define SSB_SPROM 0x0800UL + +#define SSB_PCI_MEM 0x00000000 +#define SSB_PCI_IO 0x00000001 +#define SSB_PCI_CFG0 0x00000002 +#define SSB_PCI_CFG1 0x00000003 +#define SSB_PCI_PREF 0x00000004 +#define SSB_PCI_BURST 0x00000008 +#define SSB_PCI_MASK0 0xfc000000 +#define SSB_PCI_MASK1 0xfc000000 +#define SSB_PCI_MASK2 0xc0000000 + +/* 4400 PHY registers */ +#define B44_MII_AUXCTRL 24 /* Auxiliary Control */ +#define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */ +#define MII_AUXCTRL_SPEED 0x0002 /* 1=100Mbps, 0=10Mbps */ +#define MII_AUXCTRL_FORCED 0x0004 /* Forced 10/100 */ +#define B44_MII_ALEDCTRL 26 /* Activity LED */ +#define MII_ALEDCTRL_ALLMSK 0x7fff +#define B44_MII_TLEDCTRL 27 /* Traffic Meter LED */ +#define MII_TLEDCTRL_ENABLE 0x0040 + +/* RX/TX descriptor */ +struct dma_desc { + u32 ctrl; /* length of data and flags */ + u32 addr; /* address of data */ +}; + +/* There are only 12 bits in the DMA engine for descriptor offsetting + * so the table must be aligned on a boundary of this. + */ +#define B44_DMA_ALIGNMENT 4096 + +/* The DMA engine can only address the first gigabyte of address space + */ +#define B44_30BIT_DMA_MASK 0x3fffffff + +#define DESC_CTRL_LEN 0x00001fff +#define DESC_CTRL_CMASK 0x0ff00000 /* Core specific bits */ +#define DESC_CTRL_EOT 0x10000000 /* End of Table */ +#define DESC_CTRL_IOC 0x20000000 /* Interrupt On Completion */ +#define DESC_CTRL_EOF 0x40000000 /* End of Frame */ +#define DESC_CTRL_SOF 0x80000000 /* Start of Frame */ + +struct rx_header { + u16 len; + u16 flags; + u16 pad[12]; +}; +#define RX_HEADER_LEN 28 + +#define RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */ +#define RX_FLAG_CRCERR 0x00000002 /* CRC Error */ +#define RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */ +#define RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */ +#define RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */ +#define RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */ +#define RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */ +#define RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */ +#define RX_FLAG_LAST 0x00000800 /* Last buffer in frame */ +#define RX_FLAG_ERRORS (RX_FLAG_ODD | RX_FLAG_SERR |\ + RX_FLAG_CRCERR | RX_FLAG_OFIFO) + +/* Client Mode PCI memory access space (1 GB) */ +#define SB_PCI_DMA 0x40000000 + + /* Address of PCI core on BCM4400 cards */ +#define BCM4400_PCI_CORE_ADDR 0x18002000 + +/* Hardware minimum and maximum for a single frame's data payload */ +#define B44_MIN_MTU 60 +#define B44_MAX_MTU 1500 + +#define B44_RING_SIZE 8 +#define B44_RING_LAST ( B44_RING_SIZE - 1 ) + +#define B44_RX_RING_LEN_BYTES ( sizeof bp->rx[0] * B44_RING_SIZE ) +#define B44_TX_RING_LEN_BYTES ( sizeof bp->tx[0] * B44_RING_SIZE ) + +#define RX_PKT_OFFSET 30 +#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET + 64) + +#define B44_FULL_RESET 1 +#define B44_FULL_RESET_SKIP_PHY 2 +#define B44_PARTIAL_RESET 3 +#define B44_CHIP_RESET_FULL 4 +#define B44_CHIP_RESET_PARTIAL 5 + +#define SSB_CORE_DOWN ( SBTMSLOW_RESET | SBTMSLOW_REJECT ) + +#define B44_REGS_SIZE 8192 + +/** Driver private state */ +struct b44_private { + struct net_device *netdev; + struct pci_device *pci; + u8 *regs; /* memory-mapped registers */ + u8 phy_addr; + + struct dma_desc *tx; + struct io_buffer *tx_iobuf[B44_RING_SIZE]; + u32 tx_cur; /* next available descriptor */ + u32 tx_dirty; /* oldest pending descriptor */ + + struct dma_desc *rx; + struct io_buffer *rx_iobuf[B44_RING_SIZE]; + u32 rx_cur; /* next descriptor to read */ +}; + + +static void ssb_core_reset ( struct b44_private *bp ); +static void ssb_core_disable ( struct b44_private *bp ); +static u32 ssb_pci_setup ( struct b44_private *bp, u32 cores ); + +static void b44_chip_reset ( struct b44_private *bp, int reset_kind ); +static void b44_init_hw ( struct b44_private *bp, int reset_kind ); +static void b44_cam_write ( struct b44_private *bp, u8 *data, int index ); +static void b44_set_mac_addr ( struct b44_private *bp ); +static void b44_set_rx_mode ( struct net_device *netdev ); +static void b44_halt(struct b44_private *); + +static int b44_phy_reset ( struct b44_private *bp ); +static int b44_phy_write ( struct b44_private *bp, int reg, u32 val ); +static int b44_phy_read ( struct b44_private *bp, int reg, u32 *val ); + +static int b44_init_tx_ring ( struct b44_private *bp ); +static void b44_free_tx_ring ( struct b44_private *bp ); +static int b44_init_rx_ring ( struct b44_private *bp ); +static void b44_free_rx_ring ( struct b44_private *bp ); +static void b44_rx_refill ( struct b44_private *bp, u32 pending ); +static void b44_populate_rx_descriptor (struct b44_private *bp, u32 index); + +static int b44_probe ( struct pci_device *pci, + const struct pci_device_id *id ); +static void b44_remove ( struct pci_device *pci ); + +static int b44_open ( struct net_device *netdev ); +static void b44_close ( struct net_device *netdev ); +static void b44_irq ( struct net_device *netdev, int enable ); +static void b44_poll ( struct net_device *netdev ); +static void b44_process_rx_packets ( struct b44_private *bp ); +static int b44_transmit ( struct net_device *netdev, + struct io_buffer *iobuf ); + +static struct net_device_operations b44_operations; + +#endif /* _B44_H */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/bnx2.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/bnx2.c new file mode 100644 index 0000000..c385dd8 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/bnx2.c @@ -0,0 +1,2697 @@ +/* bnx2.c: Broadcom NX2 network driver. + * + * Copyright (c) 2004, 2005, 2006 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation. + * + * Written by: Michael Chan (mchan@broadcom.com) + * + * Etherboot port by Ryan Jackson (rjackson@lnxi.com), based on driver + * version 1.4.40 from linux 2.6.17 + */ + +FILE_LICENCE ( GPL_ANY ); + +#include "etherboot.h" +#include "nic.h" +#include <errno.h> +#include <gpxe/pci.h> +#include <gpxe/ethernet.h> +#include "string.h" +#include <mii.h> +#include "bnx2.h" +#include "bnx2_fw.h" + +#if 0 +/* Dummy defines for error handling */ +#define EBUSY 1 +#define ENODEV 2 +#define EINVAL 3 +#define ENOMEM 4 +#define EIO 5 +#endif + +/* The bnx2 seems to be picky about the alignment of the receive buffers + * and possibly the status block. + */ +static struct bss { + struct tx_bd tx_desc_ring[TX_DESC_CNT]; + struct rx_bd rx_desc_ring[RX_DESC_CNT]; + unsigned char rx_buf[RX_BUF_CNT][RX_BUF_SIZE]; + struct status_block status_blk; + struct statistics_block stats_blk; +} bnx2_bss; + +static struct bnx2 bnx2; + +static struct flash_spec flash_table[] = +{ + /* Slow EEPROM */ + {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, + 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, + SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, + "EEPROM - slow"}, + /* Expansion entry 0001 */ + {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 0001"}, + /* Saifun SA25F010 (non-buffered flash) */ + /* strap, cfg1, & write1 need updates */ + {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, + "Non-buffered flash (128kB)"}, + /* Saifun SA25F020 (non-buffered flash) */ + /* strap, cfg1, & write1 need updates */ + {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, + "Non-buffered flash (256kB)"}, + /* Expansion entry 0100 */ + {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 0100"}, + /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ + {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, + 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, + ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, + "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, + /* Entry 0110: ST M45PE20 (non-buffered flash)*/ + {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, + 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, + ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, + "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, + /* Saifun SA25F005 (non-buffered flash) */ + /* strap, cfg1, & write1 need updates */ + {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, + "Non-buffered flash (64kB)"}, + /* Fast EEPROM */ + {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, + 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, + SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, + "EEPROM - fast"}, + /* Expansion entry 1001 */ + {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1001"}, + /* Expansion entry 1010 */ + {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1010"}, + /* ATMEL AT45DB011B (buffered flash) */ + {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, + 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, + BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, + "Buffered flash (128kB)"}, + /* Expansion entry 1100 */ + {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1100"}, + /* Expansion entry 1101 */ + {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1101"}, + /* Ateml Expansion entry 1110 */ + {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, + 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, + BUFFERED_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1110 (Atmel)"}, + /* ATMEL AT45DB021B (buffered flash) */ + {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, + 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, + BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, + "Buffered flash (256kB)"}, +}; + +static u32 +bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset) +{ + REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); + return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW)); +} + +static void +bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) +{ + REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); + REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val); +} + +static void +bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) +{ + offset += cid_addr; + REG_WR(bp, BNX2_CTX_DATA_ADR, offset); + REG_WR(bp, BNX2_CTX_DATA, val); +} + +static int +bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) +{ + u32 val1; + int i, ret; + + if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { + val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); + val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); + REG_RD(bp, BNX2_EMAC_MDIO_MODE); + + udelay(40); + } + + val1 = (bp->phy_addr << 21) | (reg << 16) | + BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT | + BNX2_EMAC_MDIO_COMM_START_BUSY; + REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); + + for (i = 0; i < 50; i++) { + udelay(10); + + val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); + if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { + udelay(5); + + val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); + val1 &= BNX2_EMAC_MDIO_COMM_DATA; + + break; + } + } + + if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) { + *val = 0x0; + ret = -EBUSY; + } + else { + *val = val1; + ret = 0; + } + + if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { + val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); + val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); + REG_RD(bp, BNX2_EMAC_MDIO_MODE); + + udelay(40); + } + + return ret; +} + +static int +bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) +{ + u32 val1; + int i, ret; + + if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { + val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); + val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); + REG_RD(bp, BNX2_EMAC_MDIO_MODE); + + udelay(40); + } + + val1 = (bp->phy_addr << 21) | (reg << 16) | val | + BNX2_EMAC_MDIO_COMM_COMMAND_WRITE | + BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT; + REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); + + for (i = 0; i < 50; i++) { + udelay(10); + + val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); + if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { + udelay(5); + break; + } + } + + if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) + ret = -EBUSY; + else + ret = 0; + + if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { + val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); + val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); + REG_RD(bp, BNX2_EMAC_MDIO_MODE); + + udelay(40); + } + + return ret; +} + +static void +bnx2_disable_int(struct bnx2 *bp) +{ + REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, + BNX2_PCICFG_INT_ACK_CMD_MASK_INT); + REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD); + +} + +static int +bnx2_alloc_mem(struct bnx2 *bp) +{ + bp->tx_desc_ring = bnx2_bss.tx_desc_ring; + bp->tx_desc_mapping = virt_to_bus(bp->tx_desc_ring); + + bp->rx_desc_ring = bnx2_bss.rx_desc_ring; + memset(bp->rx_desc_ring, 0, sizeof(struct rx_bd) * RX_DESC_CNT); + bp->rx_desc_mapping = virt_to_bus(bp->rx_desc_ring); + + memset(&bnx2_bss.status_blk, 0, sizeof(struct status_block)); + bp->status_blk = &bnx2_bss.status_blk; + bp->status_blk_mapping = virt_to_bus(&bnx2_bss.status_blk); + + bp->stats_blk = &bnx2_bss.stats_blk; + memset(&bnx2_bss.stats_blk, 0, sizeof(struct statistics_block)); + bp->stats_blk_mapping = virt_to_bus(&bnx2_bss.stats_blk); + + return 0; +} + +static void +bnx2_report_fw_link(struct bnx2 *bp) +{ + u32 fw_link_status = 0; + + if (bp->link_up) { + u32 bmsr; + + switch (bp->line_speed) { + case SPEED_10: + if (bp->duplex == DUPLEX_HALF) + fw_link_status = BNX2_LINK_STATUS_10HALF; + else + fw_link_status = BNX2_LINK_STATUS_10FULL; + break; + case SPEED_100: + if (bp->duplex == DUPLEX_HALF) + fw_link_status = BNX2_LINK_STATUS_100HALF; + else + fw_link_status = BNX2_LINK_STATUS_100FULL; + break; + case SPEED_1000: + if (bp->duplex == DUPLEX_HALF) + fw_link_status = BNX2_LINK_STATUS_1000HALF; + else + fw_link_status = BNX2_LINK_STATUS_1000FULL; + break; + case SPEED_2500: + if (bp->duplex == DUPLEX_HALF) + fw_link_status = BNX2_LINK_STATUS_2500HALF; + else + fw_link_status = BNX2_LINK_STATUS_2500FULL; + break; + } + + fw_link_status |= BNX2_LINK_STATUS_LINK_UP; + + if (bp->autoneg) { + fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED; + + bnx2_read_phy(bp, MII_BMSR, &bmsr); + bnx2_read_phy(bp, MII_BMSR, &bmsr); + + if (!(bmsr & BMSR_ANEGCOMPLETE) || + bp->phy_flags & PHY_PARALLEL_DETECT_FLAG) + fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET; + else + fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE; + } + } + else + fw_link_status = BNX2_LINK_STATUS_LINK_DOWN; + + REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status); +} + +static void +bnx2_report_link(struct bnx2 *bp) +{ + if (bp->link_up) { + printf("NIC Link is Up, "); + + printf("%d Mbps ", bp->line_speed); + + if (bp->duplex == DUPLEX_FULL) + printf("full duplex"); + else + printf("half duplex"); + + if (bp->flow_ctrl) { + if (bp->flow_ctrl & FLOW_CTRL_RX) { + printf(", receive "); + if (bp->flow_ctrl & FLOW_CTRL_TX) + printf("& transmit "); + } + else { + printf(", transmit "); + } + printf("flow control ON"); + } + printf("\n"); + } + else { + printf("NIC Link is Down\n"); + } + + bnx2_report_fw_link(bp); +} + +static void +bnx2_resolve_flow_ctrl(struct bnx2 *bp) +{ + u32 local_adv, remote_adv; + + bp->flow_ctrl = 0; + if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != + (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { + + if (bp->duplex == DUPLEX_FULL) { + bp->flow_ctrl = bp->req_flow_ctrl; + } + return; + } + + if (bp->duplex != DUPLEX_FULL) { + return; + } + + if ((bp->phy_flags & PHY_SERDES_FLAG) && + (CHIP_NUM(bp) == CHIP_NUM_5708)) { + u32 val; + + bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); + if (val & BCM5708S_1000X_STAT1_TX_PAUSE) + bp->flow_ctrl |= FLOW_CTRL_TX; + if (val & BCM5708S_1000X_STAT1_RX_PAUSE) + bp->flow_ctrl |= FLOW_CTRL_RX; + return; + } + + bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); + bnx2_read_phy(bp, MII_LPA, &remote_adv); + + if (bp->phy_flags & PHY_SERDES_FLAG) { + u32 new_local_adv = 0; + u32 new_remote_adv = 0; + + if (local_adv & ADVERTISE_1000XPAUSE) + new_local_adv |= ADVERTISE_PAUSE_CAP; + if (local_adv & ADVERTISE_1000XPSE_ASYM) + new_local_adv |= ADVERTISE_PAUSE_ASYM; + if (remote_adv & ADVERTISE_1000XPAUSE) + new_remote_adv |= ADVERTISE_PAUSE_CAP; + if (remote_adv & ADVERTISE_1000XPSE_ASYM) + new_remote_adv |= ADVERTISE_PAUSE_ASYM; + + local_adv = new_local_adv; + remote_adv = new_remote_adv; + } + + /* See Table 28B-3 of 802.3ab-1999 spec. */ + if (local_adv & ADVERTISE_PAUSE_CAP) { + if(local_adv & ADVERTISE_PAUSE_ASYM) { + if (remote_adv & ADVERTISE_PAUSE_CAP) { + bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; + } + else if (remote_adv & ADVERTISE_PAUSE_ASYM) { + bp->flow_ctrl = FLOW_CTRL_RX; + } + } + else { + if (remote_adv & ADVERTISE_PAUSE_CAP) { + bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; + } + } + } + else if (local_adv & ADVERTISE_PAUSE_ASYM) { + if ((remote_adv & ADVERTISE_PAUSE_CAP) && + (remote_adv & ADVERTISE_PAUSE_ASYM)) { + + bp->flow_ctrl = FLOW_CTRL_TX; + } + } +} + +static int +bnx2_5708s_linkup(struct bnx2 *bp) +{ + u32 val; + + bp->link_up = 1; + bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); + switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) { + case BCM5708S_1000X_STAT1_SPEED_10: + bp->line_speed = SPEED_10; + break; + case BCM5708S_1000X_STAT1_SPEED_100: + bp->line_speed = SPEED_100; + break; + case BCM5708S_1000X_STAT1_SPEED_1G: + bp->line_speed = SPEED_1000; + break; + case BCM5708S_1000X_STAT1_SPEED_2G5: + bp->line_speed = SPEED_2500; + break; + } + if (val & BCM5708S_1000X_STAT1_FD) + bp->duplex = DUPLEX_FULL; + else + bp->duplex = DUPLEX_HALF; + + return 0; +} + +static int +bnx2_5706s_linkup(struct bnx2 *bp) +{ + u32 bmcr, local_adv, remote_adv, common; + + bp->link_up = 1; + bp->line_speed = SPEED_1000; + + bnx2_read_phy(bp, MII_BMCR, &bmcr); + if (bmcr & BMCR_FULLDPLX) { + bp->duplex = DUPLEX_FULL; + } + else { + bp->duplex = DUPLEX_HALF; + } + + if (!(bmcr & BMCR_ANENABLE)) { + return 0; + } + + bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); + bnx2_read_phy(bp, MII_LPA, &remote_adv); + + common = local_adv & remote_adv; + if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) { + + if (common & ADVERTISE_1000XFULL) { + bp->duplex = DUPLEX_FULL; + } + else { + bp->duplex = DUPLEX_HALF; + } + } + + return 0; +} + +static int +bnx2_copper_linkup(struct bnx2 *bp) +{ + u32 bmcr; + + bnx2_read_phy(bp, MII_BMCR, &bmcr); + if (bmcr & BMCR_ANENABLE) { + u32 local_adv, remote_adv, common; + + bnx2_read_phy(bp, MII_CTRL1000, &local_adv); + bnx2_read_phy(bp, MII_STAT1000, &remote_adv); + + common = local_adv & (remote_adv >> 2); + if (common & ADVERTISE_1000FULL) { + bp->line_speed = SPEED_1000; + bp->duplex = DUPLEX_FULL; + } + else if (common & ADVERTISE_1000HALF) { + bp->line_speed = SPEED_1000; + bp->duplex = DUPLEX_HALF; + } + else { + bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); + bnx2_read_phy(bp, MII_LPA, &remote_adv); + + common = local_adv & remote_adv; + if (common & ADVERTISE_100FULL) { + bp->line_speed = SPEED_100; + bp->duplex = DUPLEX_FULL; + } + else if (common & ADVERTISE_100HALF) { + bp->line_speed = SPEED_100; + bp->duplex = DUPLEX_HALF; + } + else if (common & ADVERTISE_10FULL) { + bp->line_speed = SPEED_10; + bp->duplex = DUPLEX_FULL; + } + else if (common & ADVERTISE_10HALF) { + bp->line_speed = SPEED_10; + bp->duplex = DUPLEX_HALF; + } + else { + bp->line_speed = 0; + bp->link_up = 0; + } + } + } + else { + if (bmcr & BMCR_SPEED100) { + bp->line_speed = SPEED_100; + } + else { + bp->line_speed = SPEED_10; + } + if (bmcr & BMCR_FULLDPLX) { + bp->duplex = DUPLEX_FULL; + } + else { + bp->duplex = DUPLEX_HALF; + } + } + + return 0; +} + +static int +bnx2_set_mac_link(struct bnx2 *bp) +{ + u32 val; + + REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620); + if (bp->link_up && (bp->line_speed == SPEED_1000) && + (bp->duplex == DUPLEX_HALF)) { + REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff); + } + + /* Configure the EMAC mode register. */ + val = REG_RD(bp, BNX2_EMAC_MODE); + + val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | + BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | + BNX2_EMAC_MODE_25G); + + if (bp->link_up) { + switch (bp->line_speed) { + case SPEED_10: + if (CHIP_NUM(bp) == CHIP_NUM_5708) { + val |= BNX2_EMAC_MODE_PORT_MII_10; + break; + } + /* fall through */ + case SPEED_100: + val |= BNX2_EMAC_MODE_PORT_MII; + break; + case SPEED_2500: + val |= BNX2_EMAC_MODE_25G; + /* fall through */ + case SPEED_1000: + val |= BNX2_EMAC_MODE_PORT_GMII; + break; + } + } + else { + val |= BNX2_EMAC_MODE_PORT_GMII; + } + + /* Set the MAC to operate in the appropriate duplex mode. */ + if (bp->duplex == DUPLEX_HALF) + val |= BNX2_EMAC_MODE_HALF_DUPLEX; + REG_WR(bp, BNX2_EMAC_MODE, val); + + /* Enable/disable rx PAUSE. */ + bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN; + + if (bp->flow_ctrl & FLOW_CTRL_RX) + bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN; + REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode); + + /* Enable/disable tx PAUSE. */ + val = REG_RD(bp, BNX2_EMAC_TX_MODE); + val &= ~BNX2_EMAC_TX_MODE_FLOW_EN; + + if (bp->flow_ctrl & FLOW_CTRL_TX) + val |= BNX2_EMAC_TX_MODE_FLOW_EN; + REG_WR(bp, BNX2_EMAC_TX_MODE, val); + + /* Acknowledge the interrupt. */ + REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); + + return 0; +} + +static int +bnx2_set_link(struct bnx2 *bp) +{ + u32 bmsr; + u8 link_up; + + if (bp->loopback == MAC_LOOPBACK) { + bp->link_up = 1; + return 0; + } + + link_up = bp->link_up; + + bnx2_read_phy(bp, MII_BMSR, &bmsr); + bnx2_read_phy(bp, MII_BMSR, &bmsr); + + if ((bp->phy_flags & PHY_SERDES_FLAG) && + (CHIP_NUM(bp) == CHIP_NUM_5706)) { + u32 val; + + val = REG_RD(bp, BNX2_EMAC_STATUS); + if (val & BNX2_EMAC_STATUS_LINK) + bmsr |= BMSR_LSTATUS; + else + bmsr &= ~BMSR_LSTATUS; + } + + if (bmsr & BMSR_LSTATUS) { + bp->link_up = 1; + + if (bp->phy_flags & PHY_SERDES_FLAG) { + if (CHIP_NUM(bp) == CHIP_NUM_5706) + bnx2_5706s_linkup(bp); + else if (CHIP_NUM(bp) == CHIP_NUM_5708) + bnx2_5708s_linkup(bp); + } + else { + bnx2_copper_linkup(bp); + } + bnx2_resolve_flow_ctrl(bp); + } + else { + if ((bp->phy_flags & PHY_SERDES_FLAG) && + (bp->autoneg & AUTONEG_SPEED)) { + + u32 bmcr; + + bnx2_read_phy(bp, MII_BMCR, &bmcr); + if (!(bmcr & BMCR_ANENABLE)) { + bnx2_write_phy(bp, MII_BMCR, bmcr | + BMCR_ANENABLE); + } + } + bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; + bp->link_up = 0; + } + + if (bp->link_up != link_up) { + bnx2_report_link(bp); + } + + bnx2_set_mac_link(bp); + + return 0; +} + +static int +bnx2_reset_phy(struct bnx2 *bp) +{ + int i; + u32 reg; + + bnx2_write_phy(bp, MII_BMCR, BMCR_RESET); + +#define PHY_RESET_MAX_WAIT 100 + for (i = 0; i < PHY_RESET_MAX_WAIT; i++) { + udelay(10); + + bnx2_read_phy(bp, MII_BMCR, ®); + if (!(reg & BMCR_RESET)) { + udelay(20); + break; + } + } + if (i == PHY_RESET_MAX_WAIT) { + return -EBUSY; + } + return 0; +} + +static u32 +bnx2_phy_get_pause_adv(struct bnx2 *bp) +{ + u32 adv = 0; + + if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) == + (FLOW_CTRL_RX | FLOW_CTRL_TX)) { + + if (bp->phy_flags & PHY_SERDES_FLAG) { + adv = ADVERTISE_1000XPAUSE; + } + else { + adv = ADVERTISE_PAUSE_CAP; + } + } + else if (bp->req_flow_ctrl & FLOW_CTRL_TX) { + if (bp->phy_flags & PHY_SERDES_FLAG) { + adv = ADVERTISE_1000XPSE_ASYM; + } + else { + adv = ADVERTISE_PAUSE_ASYM; + } + } + else if (bp->req_flow_ctrl & FLOW_CTRL_RX) { + if (bp->phy_flags & PHY_SERDES_FLAG) { + adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; + } + else { + adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; + } + } + return adv; +} + +static int +bnx2_setup_serdes_phy(struct bnx2 *bp) +{ + u32 adv, bmcr, up1; + u32 new_adv = 0; + + if (!(bp->autoneg & AUTONEG_SPEED)) { + u32 new_bmcr; + int force_link_down = 0; + + if (CHIP_NUM(bp) == CHIP_NUM_5708) { + bnx2_read_phy(bp, BCM5708S_UP1, &up1); + if (up1 & BCM5708S_UP1_2G5) { + up1 &= ~BCM5708S_UP1_2G5; + bnx2_write_phy(bp, BCM5708S_UP1, up1); + force_link_down = 1; + } + } + + bnx2_read_phy(bp, MII_ADVERTISE, &adv); + adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); + + bnx2_read_phy(bp, MII_BMCR, &bmcr); + new_bmcr = bmcr & ~BMCR_ANENABLE; + new_bmcr |= BMCR_SPEED1000; + if (bp->req_duplex == DUPLEX_FULL) { + adv |= ADVERTISE_1000XFULL; + new_bmcr |= BMCR_FULLDPLX; + } + else { + adv |= ADVERTISE_1000XHALF; + new_bmcr &= ~BMCR_FULLDPLX; + } + if ((new_bmcr != bmcr) || (force_link_down)) { + /* Force a link down visible on the other side */ + if (bp->link_up) { + bnx2_write_phy(bp, MII_ADVERTISE, adv & + ~(ADVERTISE_1000XFULL | + ADVERTISE_1000XHALF)); + bnx2_write_phy(bp, MII_BMCR, bmcr | + BMCR_ANRESTART | BMCR_ANENABLE); + + bp->link_up = 0; + bnx2_write_phy(bp, MII_BMCR, new_bmcr); + } + bnx2_write_phy(bp, MII_ADVERTISE, adv); + bnx2_write_phy(bp, MII_BMCR, new_bmcr); + } + return 0; + } + + if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) { + bnx2_read_phy(bp, BCM5708S_UP1, &up1); + up1 |= BCM5708S_UP1_2G5; + bnx2_write_phy(bp, BCM5708S_UP1, up1); + } + + if (bp->advertising & ADVERTISED_1000baseT_Full) + new_adv |= ADVERTISE_1000XFULL; + + new_adv |= bnx2_phy_get_pause_adv(bp); + + bnx2_read_phy(bp, MII_ADVERTISE, &adv); + bnx2_read_phy(bp, MII_BMCR, &bmcr); + + bp->serdes_an_pending = 0; + if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { + /* Force a link down visible on the other side */ + if (bp->link_up) { + int i; + + bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); + for (i = 0; i < 110; i++) { + udelay(100); + } + } + + bnx2_write_phy(bp, MII_ADVERTISE, new_adv); + bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | + BMCR_ANENABLE); +#if 0 + if (CHIP_NUM(bp) == CHIP_NUM_5706) { + /* Speed up link-up time when the link partner + * does not autonegotiate which is very common + * in blade servers. Some blade servers use + * IPMI for kerboard input and it's important + * to minimize link disruptions. Autoneg. involves + * exchanging base pages plus 3 next pages and + * normally completes in about 120 msec. + */ + bp->current_interval = SERDES_AN_TIMEOUT; + bp->serdes_an_pending = 1; + mod_timer(&bp->timer, jiffies + bp->current_interval); + } +#endif + } + + return 0; +} + +#define ETHTOOL_ALL_FIBRE_SPEED \ + (ADVERTISED_1000baseT_Full) + +#define ETHTOOL_ALL_COPPER_SPEED \ + (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ + ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ + ADVERTISED_1000baseT_Full) + +#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \ + ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA) + +#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL) + +static int +bnx2_setup_copper_phy(struct bnx2 *bp) +{ + u32 bmcr; + u32 new_bmcr; + + bnx2_read_phy(bp, MII_BMCR, &bmcr); + + if (bp->autoneg & AUTONEG_SPEED) { + u32 adv_reg, adv1000_reg; + u32 new_adv_reg = 0; + u32 new_adv1000_reg = 0; + + bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg); + adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP | + ADVERTISE_PAUSE_ASYM); + + bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg); + adv1000_reg &= PHY_ALL_1000_SPEED; + + if (bp->advertising & ADVERTISED_10baseT_Half) + new_adv_reg |= ADVERTISE_10HALF; + if (bp->advertising & ADVERTISED_10baseT_Full) + new_adv_reg |= ADVERTISE_10FULL; + if (bp->advertising & ADVERTISED_100baseT_Half) + new_adv_reg |= ADVERTISE_100HALF; + if (bp->advertising & ADVERTISED_100baseT_Full) + new_adv_reg |= ADVERTISE_100FULL; + if (bp->advertising & ADVERTISED_1000baseT_Full) + new_adv1000_reg |= ADVERTISE_1000FULL; + + new_adv_reg |= ADVERTISE_CSMA; + + new_adv_reg |= bnx2_phy_get_pause_adv(bp); + + if ((adv1000_reg != new_adv1000_reg) || + (adv_reg != new_adv_reg) || + ((bmcr & BMCR_ANENABLE) == 0)) { + + bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg); + bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg); + bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART | + BMCR_ANENABLE); + } + else if (bp->link_up) { + /* Flow ctrl may have changed from auto to forced */ + /* or vice-versa. */ + + bnx2_resolve_flow_ctrl(bp); + bnx2_set_mac_link(bp); + } + return 0; + } + + new_bmcr = 0; + if (bp->req_line_speed == SPEED_100) { + new_bmcr |= BMCR_SPEED100; + } + if (bp->req_duplex == DUPLEX_FULL) { + new_bmcr |= BMCR_FULLDPLX; + } + if (new_bmcr != bmcr) { + u32 bmsr; + int i = 0; + + bnx2_read_phy(bp, MII_BMSR, &bmsr); + bnx2_read_phy(bp, MII_BMSR, &bmsr); + + if (bmsr & BMSR_LSTATUS) { + /* Force link down */ + bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); + do { + udelay(100); + bnx2_read_phy(bp, MII_BMSR, &bmsr); + bnx2_read_phy(bp, MII_BMSR, &bmsr); + i++; + } while ((bmsr & BMSR_LSTATUS) && (i < 620)); + } + + bnx2_write_phy(bp, MII_BMCR, new_bmcr); + + /* Normally, the new speed is setup after the link has + * gone down and up again. In some cases, link will not go + * down so we need to set up the new speed here. + */ + if (bmsr & BMSR_LSTATUS) { + bp->line_speed = bp->req_line_speed; + bp->duplex = bp->req_duplex; + bnx2_resolve_flow_ctrl(bp); + bnx2_set_mac_link(bp); + } + } + return 0; +} + +static int +bnx2_setup_phy(struct bnx2 *bp) +{ + if (bp->loopback == MAC_LOOPBACK) + return 0; + + if (bp->phy_flags & PHY_SERDES_FLAG) { + return (bnx2_setup_serdes_phy(bp)); + } + else { + return (bnx2_setup_copper_phy(bp)); + } +} + +static int +bnx2_init_5708s_phy(struct bnx2 *bp) +{ + u32 val; + + bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3); + bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE); + bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); + + bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val); + val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN; + bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val); + + bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val); + val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN; + bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val); + + if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) { + bnx2_read_phy(bp, BCM5708S_UP1, &val); + val |= BCM5708S_UP1_2G5; + bnx2_write_phy(bp, BCM5708S_UP1, val); + } + + if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || + (CHIP_ID(bp) == CHIP_ID_5708_B0) || + (CHIP_ID(bp) == CHIP_ID_5708_B1)) { + /* increase tx signal amplitude */ + bnx2_write_phy(bp, BCM5708S_BLK_ADDR, + BCM5708S_BLK_ADDR_TX_MISC); + bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val); + val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM; + bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val); + bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); + } + + val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) & + BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK; + + if (val) { + u32 is_backplane; + + is_backplane = REG_RD_IND(bp, bp->shmem_base + + BNX2_SHARED_HW_CFG_CONFIG); + if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) { + bnx2_write_phy(bp, BCM5708S_BLK_ADDR, + BCM5708S_BLK_ADDR_TX_MISC); + bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val); + bnx2_write_phy(bp, BCM5708S_BLK_ADDR, + BCM5708S_BLK_ADDR_DIG); + } + } + return 0; +} + +static int +bnx2_init_5706s_phy(struct bnx2 *bp) +{ + u32 val; + + bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; + + if (CHIP_NUM(bp) == CHIP_NUM_5706) { + REG_WR(bp, BNX2_MISC_UNUSED0, 0x300); + } + + + bnx2_write_phy(bp, 0x18, 0x7); + bnx2_read_phy(bp, 0x18, &val); + bnx2_write_phy(bp, 0x18, val & ~0x4007); + + bnx2_write_phy(bp, 0x1c, 0x6c00); + bnx2_read_phy(bp, 0x1c, &val); + bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); + + return 0; +} + +static int +bnx2_init_copper_phy(struct bnx2 *bp) +{ + u32 val; + + bp->phy_flags |= PHY_CRC_FIX_FLAG; + + if (bp->phy_flags & PHY_CRC_FIX_FLAG) { + bnx2_write_phy(bp, 0x18, 0x0c00); + bnx2_write_phy(bp, 0x17, 0x000a); + bnx2_write_phy(bp, 0x15, 0x310b); + bnx2_write_phy(bp, 0x17, 0x201f); + bnx2_write_phy(bp, 0x15, 0x9506); + bnx2_write_phy(bp, 0x17, 0x401f); + bnx2_write_phy(bp, 0x15, 0x14e2); + bnx2_write_phy(bp, 0x18, 0x0400); + } + + bnx2_write_phy(bp, 0x18, 0x7); + bnx2_read_phy(bp, 0x18, &val); + bnx2_write_phy(bp, 0x18, val & ~0x4007); + + bnx2_read_phy(bp, 0x10, &val); + bnx2_write_phy(bp, 0x10, val & ~0x1); + + /* ethernet@wirespeed */ + bnx2_write_phy(bp, 0x18, 0x7007); + bnx2_read_phy(bp, 0x18, &val); + bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4)); + return 0; +} + +static int +bnx2_init_phy(struct bnx2 *bp) +{ + u32 val; + int rc = 0; + + bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG; + bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG; + + REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); + + bnx2_reset_phy(bp); + + bnx2_read_phy(bp, MII_PHYSID1, &val); + bp->phy_id = val << 16; + bnx2_read_phy(bp, MII_PHYSID2, &val); + bp->phy_id |= val & 0xffff; + + if (bp->phy_flags & PHY_SERDES_FLAG) { + if (CHIP_NUM(bp) == CHIP_NUM_5706) + rc = bnx2_init_5706s_phy(bp); + else if (CHIP_NUM(bp) == CHIP_NUM_5708) + rc = bnx2_init_5708s_phy(bp); + } + else { + rc = bnx2_init_copper_phy(bp); + } + + bnx2_setup_phy(bp); + + return rc; +} + +static int +bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent) +{ + int i; + u32 val; + + bp->fw_wr_seq++; + msg_data |= bp->fw_wr_seq; + + REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data); + + /* wait for an acknowledgement. */ + for (i = 0; i < (FW_ACK_TIME_OUT_MS / 50); i++) { + mdelay(50); + + val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB); + + if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ)) + break; + } + if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0) + return 0; + + /* If we timed out, inform the firmware that this is the case. */ + if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) { + if (!silent) + printf("fw sync timeout, reset code = %x\n", (unsigned int) msg_data); + + msg_data &= ~BNX2_DRV_MSG_CODE; + msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT; + + REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data); + + return -EBUSY; + } + + if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK) + return -EIO; + + return 0; +} + +static void +bnx2_init_context(struct bnx2 *bp) +{ + u32 vcid; + + vcid = 96; + while (vcid) { + u32 vcid_addr, pcid_addr, offset; + + vcid--; + + if (CHIP_ID(bp) == CHIP_ID_5706_A0) { + u32 new_vcid; + + vcid_addr = GET_PCID_ADDR(vcid); + if (vcid & 0x8) { + new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7); + } + else { + new_vcid = vcid; + } + pcid_addr = GET_PCID_ADDR(new_vcid); + } + else { + vcid_addr = GET_CID_ADDR(vcid); + pcid_addr = vcid_addr; + } + + REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00); + REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); + + /* Zero out the context. */ + for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) { + CTX_WR(bp, 0x00, offset, 0); + } + + REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); + REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); + } +} + +static int +bnx2_alloc_bad_rbuf(struct bnx2 *bp) +{ + u16 good_mbuf[512]; + u32 good_mbuf_cnt; + u32 val; + + REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, + BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE); + + good_mbuf_cnt = 0; + + /* Allocate a bunch of mbufs and save the good ones in an array. */ + val = REG_RD_IND(bp, BNX2_RBUF_STATUS1); + while (val & BNX2_RBUF_STATUS1_FREE_COUNT) { + REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ); + + val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC); + + val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE; + + /* The addresses with Bit 9 set are bad memory blocks. */ + if (!(val & (1 << 9))) { + good_mbuf[good_mbuf_cnt] = (u16) val; + good_mbuf_cnt++; + } + + val = REG_RD_IND(bp, BNX2_RBUF_STATUS1); + } + + /* Free the good ones back to the mbuf pool thus discarding + * all the bad ones. */ + while (good_mbuf_cnt) { + good_mbuf_cnt--; + + val = good_mbuf[good_mbuf_cnt]; + val = (val << 9) | val | 1; + + REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val); + } + return 0; +} + +static void +bnx2_set_mac_addr(struct bnx2 *bp) +{ + u32 val; + u8 *mac_addr = bp->nic->node_addr; + + val = (mac_addr[0] << 8) | mac_addr[1]; + + REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val); + + val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | + (mac_addr[4] << 8) | mac_addr[5]; + + REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val); +} + +static void +bnx2_set_rx_mode(struct nic *nic __unused) +{ + struct bnx2 *bp = &bnx2; + u32 rx_mode, sort_mode; + int i; + + rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS | + BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); + sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; + + if (!(bp->flags & ASF_ENABLE_FLAG)) { + rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; + } + + /* Accept all multicasts */ + for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { + REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), + 0xffffffff); + } + sort_mode |= BNX2_RPM_SORT_USER0_MC_EN; + + if (rx_mode != bp->rx_mode) { + bp->rx_mode = rx_mode; + REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode); + } + + REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0); + REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode); + REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA); +} + +static void +load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, u32 rv2p_proc) +{ + unsigned int i; + u32 val; + + + for (i = 0; i < rv2p_code_len; i += 8) { + REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code); + rv2p_code++; + REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code); + rv2p_code++; + + if (rv2p_proc == RV2P_PROC1) { + val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR; + REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val); + } + else { + val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR; + REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val); + } + } + + /* Reset the processor, un-stall is done later. */ + if (rv2p_proc == RV2P_PROC1) { + REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET); + } + else { + REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET); + } +} + +static void +load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) +{ + u32 offset; + u32 val; + + /* Halt the CPU. */ + val = REG_RD_IND(bp, cpu_reg->mode); + val |= cpu_reg->mode_value_halt; + REG_WR_IND(bp, cpu_reg->mode, val); + REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); + + /* Load the Text area. */ + offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); + if (fw->text) { + unsigned int j; + + for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { + REG_WR_IND(bp, offset, fw->text[j]); + } + } + + /* Load the Data area. */ + offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); + if (fw->data) { + unsigned int j; + + for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { + REG_WR_IND(bp, offset, fw->data[j]); + } + } + + /* Load the SBSS area. */ + offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); + if (fw->sbss) { + unsigned int j; + + for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { + REG_WR_IND(bp, offset, fw->sbss[j]); + } + } + + /* Load the BSS area. */ + offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); + if (fw->bss) { + unsigned int j; + + for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { + REG_WR_IND(bp, offset, fw->bss[j]); + } + } + + /* Load the Read-Only area. */ + offset = cpu_reg->spad_base + + (fw->rodata_addr - cpu_reg->mips_view_base); + if (fw->rodata) { + unsigned int j; + + for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { + REG_WR_IND(bp, offset, fw->rodata[j]); + } + } + + /* Clear the pre-fetch instruction. */ + REG_WR_IND(bp, cpu_reg->inst, 0); + REG_WR_IND(bp, cpu_reg->pc, fw->start_addr); + + /* Start the CPU. */ + val = REG_RD_IND(bp, cpu_reg->mode); + val &= ~cpu_reg->mode_value_halt; + REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); + REG_WR_IND(bp, cpu_reg->mode, val); +} + +static void +bnx2_init_cpus(struct bnx2 *bp) +{ + struct cpu_reg cpu_reg; + struct fw_info fw; + + /* Unfortunately, it looks like we need to load the firmware + * before the card will work properly. That means this driver + * will be huge by Etherboot standards (approx. 50K compressed). + */ + + /* Initialize the RV2P processor. */ + load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1); + load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2); + + /* Initialize the RX Processor. */ + cpu_reg.mode = BNX2_RXP_CPU_MODE; + cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA; + cpu_reg.state = BNX2_RXP_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE; + cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK; + cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION; + cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BNX2_RXP_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = bnx2_RXP_b06FwReleaseMajor; + fw.ver_minor = bnx2_RXP_b06FwReleaseMinor; + fw.ver_fix = bnx2_RXP_b06FwReleaseFix; + fw.start_addr = bnx2_RXP_b06FwStartAddr; + + fw.text_addr = bnx2_RXP_b06FwTextAddr; + fw.text_len = bnx2_RXP_b06FwTextLen; + fw.text_index = 0; + fw.text = bnx2_RXP_b06FwText; + + fw.data_addr = bnx2_RXP_b06FwDataAddr; + fw.data_len = bnx2_RXP_b06FwDataLen; + fw.data_index = 0; + fw.data = bnx2_RXP_b06FwData; + + fw.sbss_addr = bnx2_RXP_b06FwSbssAddr; + fw.sbss_len = bnx2_RXP_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bnx2_RXP_b06FwSbss; + + fw.bss_addr = bnx2_RXP_b06FwBssAddr; + fw.bss_len = bnx2_RXP_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bnx2_RXP_b06FwBss; + + fw.rodata_addr = bnx2_RXP_b06FwRodataAddr; + fw.rodata_len = bnx2_RXP_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bnx2_RXP_b06FwRodata; + + load_cpu_fw(bp, &cpu_reg, &fw); + + /* Initialize the TX Processor. */ + cpu_reg.mode = BNX2_TXP_CPU_MODE; + cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA; + cpu_reg.state = BNX2_TXP_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE; + cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK; + cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION; + cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BNX2_TXP_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = bnx2_TXP_b06FwReleaseMajor; + fw.ver_minor = bnx2_TXP_b06FwReleaseMinor; + fw.ver_fix = bnx2_TXP_b06FwReleaseFix; + fw.start_addr = bnx2_TXP_b06FwStartAddr; + + fw.text_addr = bnx2_TXP_b06FwTextAddr; + fw.text_len = bnx2_TXP_b06FwTextLen; + fw.text_index = 0; + fw.text = bnx2_TXP_b06FwText; + + fw.data_addr = bnx2_TXP_b06FwDataAddr; + fw.data_len = bnx2_TXP_b06FwDataLen; + fw.data_index = 0; + fw.data = bnx2_TXP_b06FwData; + + fw.sbss_addr = bnx2_TXP_b06FwSbssAddr; + fw.sbss_len = bnx2_TXP_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bnx2_TXP_b06FwSbss; + + fw.bss_addr = bnx2_TXP_b06FwBssAddr; + fw.bss_len = bnx2_TXP_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bnx2_TXP_b06FwBss; + + fw.rodata_addr = bnx2_TXP_b06FwRodataAddr; + fw.rodata_len = bnx2_TXP_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bnx2_TXP_b06FwRodata; + + load_cpu_fw(bp, &cpu_reg, &fw); + + /* Initialize the TX Patch-up Processor. */ + cpu_reg.mode = BNX2_TPAT_CPU_MODE; + cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA; + cpu_reg.state = BNX2_TPAT_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE; + cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK; + cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION; + cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BNX2_TPAT_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = bnx2_TPAT_b06FwReleaseMajor; + fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor; + fw.ver_fix = bnx2_TPAT_b06FwReleaseFix; + fw.start_addr = bnx2_TPAT_b06FwStartAddr; + + fw.text_addr = bnx2_TPAT_b06FwTextAddr; + fw.text_len = bnx2_TPAT_b06FwTextLen; + fw.text_index = 0; + fw.text = bnx2_TPAT_b06FwText; + + fw.data_addr = bnx2_TPAT_b06FwDataAddr; + fw.data_len = bnx2_TPAT_b06FwDataLen; + fw.data_index = 0; + fw.data = bnx2_TPAT_b06FwData; + + fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr; + fw.sbss_len = bnx2_TPAT_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bnx2_TPAT_b06FwSbss; + + fw.bss_addr = bnx2_TPAT_b06FwBssAddr; + fw.bss_len = bnx2_TPAT_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bnx2_TPAT_b06FwBss; + + fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr; + fw.rodata_len = bnx2_TPAT_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bnx2_TPAT_b06FwRodata; + + load_cpu_fw(bp, &cpu_reg, &fw); + + /* Initialize the Completion Processor. */ + cpu_reg.mode = BNX2_COM_CPU_MODE; + cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA; + cpu_reg.state = BNX2_COM_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE; + cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK; + cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION; + cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BNX2_COM_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = bnx2_COM_b06FwReleaseMajor; + fw.ver_minor = bnx2_COM_b06FwReleaseMinor; + fw.ver_fix = bnx2_COM_b06FwReleaseFix; + fw.start_addr = bnx2_COM_b06FwStartAddr; + + fw.text_addr = bnx2_COM_b06FwTextAddr; + fw.text_len = bnx2_COM_b06FwTextLen; + fw.text_index = 0; + fw.text = bnx2_COM_b06FwText; + + fw.data_addr = bnx2_COM_b06FwDataAddr; + fw.data_len = bnx2_COM_b06FwDataLen; + fw.data_index = 0; + fw.data = bnx2_COM_b06FwData; + + fw.sbss_addr = bnx2_COM_b06FwSbssAddr; + fw.sbss_len = bnx2_COM_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bnx2_COM_b06FwSbss; + + fw.bss_addr = bnx2_COM_b06FwBssAddr; + fw.bss_len = bnx2_COM_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bnx2_COM_b06FwBss; + + fw.rodata_addr = bnx2_COM_b06FwRodataAddr; + fw.rodata_len = bnx2_COM_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bnx2_COM_b06FwRodata; + + load_cpu_fw(bp, &cpu_reg, &fw); + +} + +static int +bnx2_set_power_state_0(struct bnx2 *bp) +{ + u16 pmcsr; + u32 val; + + pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr); + + pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, + (pmcsr & ~PCI_PM_CTRL_STATE_MASK) | + PCI_PM_CTRL_PME_STATUS); + + if (pmcsr & PCI_PM_CTRL_STATE_MASK) + /* delay required during transition out of D3hot */ + mdelay(20); + + val = REG_RD(bp, BNX2_EMAC_MODE); + val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD; + val &= ~BNX2_EMAC_MODE_MPKT; + REG_WR(bp, BNX2_EMAC_MODE, val); + + val = REG_RD(bp, BNX2_RPM_CONFIG); + val &= ~BNX2_RPM_CONFIG_ACPI_ENA; + REG_WR(bp, BNX2_RPM_CONFIG, val); + + return 0; +} + +static void +bnx2_enable_nvram_access(struct bnx2 *bp) +{ + u32 val; + + val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); + /* Enable both bits, even on read. */ + REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, + val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN); +} + +static void +bnx2_disable_nvram_access(struct bnx2 *bp) +{ + u32 val; + + val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); + /* Disable both bits, even after read. */ + REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, + val & ~(BNX2_NVM_ACCESS_ENABLE_EN | + BNX2_NVM_ACCESS_ENABLE_WR_EN)); +} + +static int +bnx2_init_nvram(struct bnx2 *bp) +{ + u32 val; + int j, entry_count, rc; + struct flash_spec *flash; + + /* Determine the selected interface. */ + val = REG_RD(bp, BNX2_NVM_CFG1); + + entry_count = sizeof(flash_table) / sizeof(struct flash_spec); + + rc = 0; + if (val & 0x40000000) { + /* Flash interface has been reconfigured */ + for (j = 0, flash = &flash_table[0]; j < entry_count; + j++, flash++) { + if ((val & FLASH_BACKUP_STRAP_MASK) == + (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { + bp->flash_info = flash; + break; + } + } + } + else { + u32 mask; + /* Not yet been reconfigured */ + + if (val & (1 << 23)) + mask = FLASH_BACKUP_STRAP_MASK; + else + mask = FLASH_STRAP_MASK; + + for (j = 0, flash = &flash_table[0]; j < entry_count; + j++, flash++) { + + if ((val & mask) == (flash->strapping & mask)) { + bp->flash_info = flash; + + /* Enable access to flash interface */ + bnx2_enable_nvram_access(bp); + + /* Reconfigure the flash interface */ + REG_WR(bp, BNX2_NVM_CFG1, flash->config1); + REG_WR(bp, BNX2_NVM_CFG2, flash->config2); + REG_WR(bp, BNX2_NVM_CFG3, flash->config3); + REG_WR(bp, BNX2_NVM_WRITE1, flash->write1); + + /* Disable access to flash interface */ + bnx2_disable_nvram_access(bp); + + break; + } + } + } /* if (val & 0x40000000) */ + + if (j == entry_count) { + bp->flash_info = NULL; + printf("Unknown flash/EEPROM type.\n"); + return -ENODEV; + } + + val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2); + val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK; + if (val) { + bp->flash_size = val; + } + else { + bp->flash_size = bp->flash_info->total_size; + } + + return rc; +} + +static int +bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) +{ + u32 val; + int i, rc = 0; + + /* Wait for the current PCI transaction to complete before + * issuing a reset. */ + REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS, + BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | + BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | + BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | + BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); + val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS); + udelay(5); + + + /* Wait for the firmware to tell us it is ok to issue a reset. */ + bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1); + + /* Deposit a driver reset signature so the firmware knows that + * this is a soft reset. */ + REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE, + BNX2_DRV_RESET_SIGNATURE_MAGIC); + + /* Do a dummy read to force the chip to complete all current transaction + * before we issue a reset. */ + val = REG_RD(bp, BNX2_MISC_ID); + + val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | + BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | + BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; + + /* Chip reset. */ + REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); + + if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || + (CHIP_ID(bp) == CHIP_ID_5706_A1)) + mdelay(15); + + /* Reset takes approximate 30 usec */ + for (i = 0; i < 10; i++) { + val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG); + if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | + BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { + break; + } + udelay(10); + } + + if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | + BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { + printf("Chip reset did not complete\n"); + return -EBUSY; + } + + /* Make sure byte swapping is properly configured. */ + val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0); + if (val != 0x01020304) { + printf("Chip not in correct endian mode\n"); + return -ENODEV; + } + + /* Wait for the firmware to finish its initialization. */ + rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0); + if (rc) { + return rc; + } + + if (CHIP_ID(bp) == CHIP_ID_5706_A0) { + /* Adjust the voltage regular to two steps lower. The default + * of this register is 0x0000000e. */ + REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); + + /* Remove bad rbuf memory from the free pool. */ + rc = bnx2_alloc_bad_rbuf(bp); + } + + return rc; +} + +static void +bnx2_disable(struct nic *nic __unused) +{ + struct bnx2* bp = &bnx2; + + if (bp->regview) { + bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_UNLOAD); + iounmap(bp->regview); + } +} + +static int +bnx2_init_chip(struct bnx2 *bp) +{ + u32 val; + int rc; + + /* Make sure the interrupt is not active. */ + REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT); + + val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP | + BNX2_DMA_CONFIG_DATA_WORD_SWAP | +#if __BYTE_ORDER == __BIG_ENDIAN + BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | +#endif + BNX2_DMA_CONFIG_CNTL_WORD_SWAP | + DMA_READ_CHANS << 12 | + DMA_WRITE_CHANS << 16; + + val |= (0x2 << 20) | (1 << 11); + + if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133)) + val |= (1 << 23); + + if ((CHIP_NUM(bp) == CHIP_NUM_5706) && + (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG)) + val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA; + + REG_WR(bp, BNX2_DMA_CONFIG, val); + + if (CHIP_ID(bp) == CHIP_ID_5706_A0) { + val = REG_RD(bp, BNX2_TDMA_CONFIG); + val |= BNX2_TDMA_CONFIG_ONE_DMA; + REG_WR(bp, BNX2_TDMA_CONFIG, val); + } + + if (bp->flags & PCIX_FLAG) { + u16 val16; + + pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, + &val16); + pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, + val16 & ~PCI_X_CMD_ERO); + } + + REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, + BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | + BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | + BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); + + /* Initialize context mapping and zero out the quick contexts. The + * context block must have already been enabled. */ + bnx2_init_context(bp); + + bnx2_init_nvram(bp); + bnx2_init_cpus(bp); + + bnx2_set_mac_addr(bp); + + val = REG_RD(bp, BNX2_MQ_CONFIG); + val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; + val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; + REG_WR(bp, BNX2_MQ_CONFIG, val); + + val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); + REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val); + REG_WR(bp, BNX2_MQ_KNL_WIND_END, val); + + val = (BCM_PAGE_BITS - 8) << 24; + REG_WR(bp, BNX2_RV2P_CONFIG, val); + + /* Configure page size. */ + val = REG_RD(bp, BNX2_TBDR_CONFIG); + val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE; + val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; + REG_WR(bp, BNX2_TBDR_CONFIG, val); + + val = bp->mac_addr[0] + + (bp->mac_addr[1] << 8) + + (bp->mac_addr[2] << 16) + + bp->mac_addr[3] + + (bp->mac_addr[4] << 8) + + (bp->mac_addr[5] << 16); + REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); + + /* Program the MTU. Also include 4 bytes for CRC32. */ + val = ETH_MAX_MTU + ETH_HLEN + 4; + if (val > (MAX_ETHERNET_PACKET_SIZE + 4)) + val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; + REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); + + bp->last_status_idx = 0; + bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE; + + /* Set up how to generate a link change interrupt. */ + REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); + + REG_WR(bp, BNX2_HC_STATUS_ADDR_L, + (u64) bp->status_blk_mapping & 0xffffffff); + REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32); + + REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L, + (u64) bp->stats_blk_mapping & 0xffffffff); + REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H, + (u64) bp->stats_blk_mapping >> 32); + + REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, + (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); + + REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP, + (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip); + + REG_WR(bp, BNX2_HC_COMP_PROD_TRIP, + (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip); + + REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks); + + REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks); + + REG_WR(bp, BNX2_HC_COM_TICKS, + (bp->com_ticks_int << 16) | bp->com_ticks); + + REG_WR(bp, BNX2_HC_CMD_TICKS, + (bp->cmd_ticks_int << 16) | bp->cmd_ticks); + + REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00); + REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ + + if (CHIP_ID(bp) == CHIP_ID_5706_A1) + REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS); + else { + REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE | + BNX2_HC_CONFIG_TX_TMR_MODE | + BNX2_HC_CONFIG_COLLECT_STATS); + } + + /* Clear internal stats counters. */ + REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW); + + REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); + + if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) & + BNX2_PORT_FEATURE_ASF_ENABLED) + bp->flags |= ASF_ENABLE_FLAG; + + /* Initialize the receive filter. */ + bnx2_set_rx_mode(bp->nic); + + rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET, + 0); + + REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff); + REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS); + + udelay(20); + + bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND); + + return rc; +} + +static void +bnx2_init_tx_ring(struct bnx2 *bp) +{ + struct tx_bd *txbd; + u32 val; + + txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT]; + + /* Etherboot lives below 4GB, so hi is always 0 */ + txbd->tx_bd_haddr_hi = 0; + txbd->tx_bd_haddr_lo = bp->tx_desc_mapping; + + bp->tx_prod = 0; + bp->tx_cons = 0; + bp->hw_tx_cons = 0; + bp->tx_prod_bseq = 0; + + val = BNX2_L2CTX_TYPE_TYPE_L2; + val |= BNX2_L2CTX_TYPE_SIZE_L2; + CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val); + + val = BNX2_L2CTX_CMD_TYPE_TYPE_L2; + val |= 8 << 16; + CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val); + + /* Etherboot lives below 4GB, so hi is always 0 */ + CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, 0); + + val = (u64) bp->tx_desc_mapping & 0xffffffff; + CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val); +} + +static void +bnx2_init_rx_ring(struct bnx2 *bp) +{ + struct rx_bd *rxbd; + unsigned int i; + u16 prod, ring_prod; + u32 val; + + bp->rx_buf_use_size = RX_BUF_USE_SIZE; + bp->rx_buf_size = RX_BUF_SIZE; + + ring_prod = prod = bp->rx_prod = 0; + bp->rx_cons = 0; + bp->hw_rx_cons = 0; + bp->rx_prod_bseq = 0; + + memset(bnx2_bss.rx_buf, 0, sizeof(bnx2_bss.rx_buf)); + + rxbd = &bp->rx_desc_ring[0]; + for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) { + rxbd->rx_bd_len = bp->rx_buf_use_size; + rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; + } + rxbd->rx_bd_haddr_hi = 0; + rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff; + + val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; + val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; + val |= 0x02 << 8; + CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val); + + /* Etherboot doesn't use memory above 4GB, so this is always 0 */ + CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, 0); + + val = bp->rx_desc_mapping & 0xffffffff; + CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val); + + for (i = 0; (int) i < bp->rx_ring_size; i++) { + rxbd = &bp->rx_desc_ring[RX_RING_IDX(ring_prod)]; + rxbd->rx_bd_haddr_hi = 0; + rxbd->rx_bd_haddr_lo = virt_to_bus(&bnx2_bss.rx_buf[ring_prod][0]); + bp->rx_prod_bseq += bp->rx_buf_use_size; + prod = NEXT_RX_BD(prod); + ring_prod = RX_RING_IDX(prod); + } + bp->rx_prod = prod; + + REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, bp->rx_prod); + + REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq); +} + +static int +bnx2_reset_nic(struct bnx2 *bp, u32 reset_code) +{ + int rc; + + rc = bnx2_reset_chip(bp, reset_code); + if (rc) { + return rc; + } + + bnx2_init_chip(bp); + bnx2_init_tx_ring(bp); + bnx2_init_rx_ring(bp); + return 0; +} + +static int +bnx2_init_nic(struct bnx2 *bp) +{ + int rc; + + if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0) + return rc; + + bnx2_init_phy(bp); + bnx2_set_link(bp); + return 0; +} + +static int +bnx2_init_board(struct pci_device *pdev, struct nic *nic) +{ + unsigned long bnx2reg_base, bnx2reg_len; + struct bnx2 *bp = &bnx2; + int rc; + u32 reg; + + bp->flags = 0; + bp->phy_flags = 0; + + /* enable device (incl. PCI PM wakeup), and bus-mastering */ + adjust_pci_device(pdev); + + nic->ioaddr = pdev->ioaddr & ~3; + nic->irqno = 0; + + rc = 0; + bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); + if (bp->pm_cap == 0) { + printf("Cannot find power management capability, aborting.\n"); + rc = -EIO; + goto err_out_disable; + } + + bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); + if (bp->pcix_cap == 0) { + printf("Cannot find PCIX capability, aborting.\n"); + rc = -EIO; + goto err_out_disable; + } + + bp->pdev = pdev; + bp->nic = nic; + + bnx2reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0); + bnx2reg_len = MB_GET_CID_ADDR(17); + + bp->regview = ioremap(bnx2reg_base, bnx2reg_len); + + if (!bp->regview) { + printf("Cannot map register space, aborting.\n"); + rc = -EIO; + goto err_out_disable; + } + + /* Configure byte swap and enable write to the reg_window registers. + * Rely on CPU to do target byte swapping on big endian systems + * The chip's target access swapping will not swap all accesses + */ + pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, + BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | + BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); + + bnx2_set_power_state_0(bp); + + bp->chip_id = REG_RD(bp, BNX2_MISC_ID); + + /* Get bus information. */ + reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS); + if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { + u32 clkreg; + + bp->flags |= PCIX_FLAG; + + clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); + + clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; + switch (clkreg) { + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: + bp->bus_speed_mhz = 133; + break; + + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: + bp->bus_speed_mhz = 100; + break; + + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: + bp->bus_speed_mhz = 66; + break; + + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: + bp->bus_speed_mhz = 50; + break; + + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: + bp->bus_speed_mhz = 33; + break; + } + } + else { + if (reg & BNX2_PCICFG_MISC_STATUS_M66EN) + bp->bus_speed_mhz = 66; + else + bp->bus_speed_mhz = 33; + } + + if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET) + bp->flags |= PCI_32BIT_FLAG; + + /* 5706A0 may falsely detect SERR and PERR. */ + if (CHIP_ID(bp) == CHIP_ID_5706_A0) { + reg = REG_RD(bp, PCI_COMMAND); + reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); + REG_WR(bp, PCI_COMMAND, reg); + } + else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) && + !(bp->flags & PCIX_FLAG)) { + + printf("5706 A1 can only be used in a PCIX bus, aborting.\n"); + goto err_out_disable; + } + + bnx2_init_nvram(bp); + + reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE); + + if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) == + BNX2_SHM_HDR_SIGNATURE_SIG) + bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0); + else + bp->shmem_base = HOST_VIEW_SHMEM_BASE; + + /* Get the permanent MAC address. First we need to make sure the + * firmware is actually running. + */ + reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE); + + if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != + BNX2_DEV_INFO_SIGNATURE_MAGIC) { + printf("Firmware not running, aborting.\n"); + rc = -ENODEV; + goto err_out_disable; + } + + bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV); + + reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER); + bp->mac_addr[0] = (u8) (reg >> 8); + bp->mac_addr[1] = (u8) reg; + + reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER); + bp->mac_addr[2] = (u8) (reg >> 24); + bp->mac_addr[3] = (u8) (reg >> 16); + bp->mac_addr[4] = (u8) (reg >> 8); + bp->mac_addr[5] = (u8) reg; + + bp->tx_ring_size = MAX_TX_DESC_CNT; + bp->rx_ring_size = RX_BUF_CNT; + bp->rx_max_ring_idx = MAX_RX_DESC_CNT; + + bp->rx_offset = RX_OFFSET; + + bp->tx_quick_cons_trip_int = 20; + bp->tx_quick_cons_trip = 20; + bp->tx_ticks_int = 80; + bp->tx_ticks = 80; + + bp->rx_quick_cons_trip_int = 6; + bp->rx_quick_cons_trip = 6; + bp->rx_ticks_int = 18; + bp->rx_ticks = 18; + + bp->stats_ticks = 1000000 & 0xffff00; + + bp->phy_addr = 1; + + /* No need for WOL support in Etherboot */ + bp->flags |= NO_WOL_FLAG; + + /* Disable WOL support if we are running on a SERDES chip. */ + if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) { + bp->phy_flags |= PHY_SERDES_FLAG; + if (CHIP_NUM(bp) == CHIP_NUM_5708) { + bp->phy_addr = 2; + reg = REG_RD_IND(bp, bp->shmem_base + + BNX2_SHARED_HW_CFG_CONFIG); + if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) + bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG; + } + } + + if (CHIP_ID(bp) == CHIP_ID_5706_A0) { + bp->tx_quick_cons_trip_int = + bp->tx_quick_cons_trip; + bp->tx_ticks_int = bp->tx_ticks; + bp->rx_quick_cons_trip_int = + bp->rx_quick_cons_trip; + bp->rx_ticks_int = bp->rx_ticks; + bp->comp_prod_trip_int = bp->comp_prod_trip; + bp->com_ticks_int = bp->com_ticks; + bp->cmd_ticks_int = bp->cmd_ticks; + } + + bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; + bp->req_line_speed = 0; + if (bp->phy_flags & PHY_SERDES_FLAG) { + bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; + + reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG); + reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK; + if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) { + bp->autoneg = 0; + bp->req_line_speed = bp->line_speed = SPEED_1000; + bp->req_duplex = DUPLEX_FULL; + } + } + else { + bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg; + } + + bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; + + /* Disable driver heartbeat checking */ + REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, + BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE); + REG_RD_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB); + + return 0; + +err_out_disable: + bnx2_disable(nic); + + return rc; +} + +static void +bnx2_transmit(struct nic *nic, const char *dst_addr, + unsigned int type, unsigned int size, const char *packet) +{ + /* Sometimes the nic will be behind by a frame. Using two transmit + * buffers prevents us from timing out in that case. + */ + static struct eth_frame { + uint8_t dst_addr[ETH_ALEN]; + uint8_t src_addr[ETH_ALEN]; + uint16_t type; + uint8_t data [ETH_FRAME_LEN - ETH_HLEN]; + } frame[2]; + static int frame_idx = 0; + + /* send the packet to destination */ + struct tx_bd *txbd; + struct bnx2 *bp = &bnx2; + u16 prod, ring_prod; + u16 hw_cons; + int i = 0; + + prod = bp->tx_prod; + ring_prod = TX_RING_IDX(prod); + hw_cons = bp->status_blk->status_tx_quick_consumer_index0; + if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) { + hw_cons++; + } + + while((hw_cons != prod) && (hw_cons != (PREV_TX_BD(prod)))) { + mdelay(10); /* give the nic a chance */ + //poll_interruptions(); + if (++i > 500) { /* timeout 5s for transmit */ + printf("transmit timed out\n"); + bnx2_disable(bp->nic); + bnx2_init_board(bp->pdev, bp->nic); + return; + } + } + if (i != 0) { + printf("#"); + } + + /* Copy the packet to the our local buffer */ + memcpy(&frame[frame_idx].dst_addr, dst_addr, ETH_ALEN); + memcpy(&frame[frame_idx].src_addr, nic->node_addr, ETH_ALEN); + frame[frame_idx].type = htons(type); + memset(&frame[frame_idx].data, 0, sizeof(frame[frame_idx].data)); + memcpy(&frame[frame_idx].data, packet, size); + + /* Setup the ring buffer entry to transmit */ + txbd = &bp->tx_desc_ring[ring_prod]; + txbd->tx_bd_haddr_hi = 0; /* Etherboot runs under 4GB */ + txbd->tx_bd_haddr_lo = virt_to_bus(&frame[frame_idx]); + txbd->tx_bd_mss_nbytes = (size + ETH_HLEN); + txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; + + /* Advance to the next entry */ + prod = NEXT_TX_BD(prod); + frame_idx ^= 1; + + bp->tx_prod_bseq += (size + ETH_HLEN); + + REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod); + REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq); + + wmb(); + + bp->tx_prod = prod; +} + +static int +bnx2_poll_link(struct bnx2 *bp) +{ + u32 new_link_state, old_link_state, emac_status; + + new_link_state = bp->status_blk->status_attn_bits & + STATUS_ATTN_BITS_LINK_STATE; + + old_link_state = bp->status_blk->status_attn_bits_ack & + STATUS_ATTN_BITS_LINK_STATE; + + if (!new_link_state && !old_link_state) { + /* For some reason the card doesn't always update the link + * status bits properly. Kick the stupid thing and try again. + */ + u32 bmsr; + + bnx2_read_phy(bp, MII_BMSR, &bmsr); + bnx2_read_phy(bp, MII_BMSR, &bmsr); + + if ((bp->phy_flags & PHY_SERDES_FLAG) && + (CHIP_NUM(bp) == CHIP_NUM_5706)) { + REG_RD(bp, BNX2_EMAC_STATUS); + } + + new_link_state = bp->status_blk->status_attn_bits & + STATUS_ATTN_BITS_LINK_STATE; + + old_link_state = bp->status_blk->status_attn_bits_ack & + STATUS_ATTN_BITS_LINK_STATE; + + /* Okay, for some reason the above doesn't work with some + * switches (like HP ProCurve). If the above doesn't work, + * check the MAC directly to see if we have a link. Perhaps we + * should always check the MAC instead probing the MII. + */ + if (!new_link_state && !old_link_state) { + emac_status = REG_RD(bp, BNX2_EMAC_STATUS); + if (emac_status & BNX2_EMAC_STATUS_LINK_CHANGE) { + /* Acknowledge the link change */ + REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); + } else if (emac_status & BNX2_EMAC_STATUS_LINK) { + new_link_state = !old_link_state; + } + } + + } + + if (new_link_state != old_link_state) { + if (new_link_state) { + REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, + STATUS_ATTN_BITS_LINK_STATE); + } + else { + REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, + STATUS_ATTN_BITS_LINK_STATE); + } + + bnx2_set_link(bp); + + /* This is needed to take care of transient status + * during link changes. + */ + + REG_WR(bp, BNX2_HC_COMMAND, + bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); + REG_RD(bp, BNX2_HC_COMMAND); + + } + + return bp->link_up; +} + +static int +bnx2_poll(struct nic* nic, int retrieve) +{ + struct bnx2 *bp = &bnx2; + struct rx_bd *cons_bd, *prod_bd; + u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod; + struct l2_fhdr *rx_hdr; + int result = 0; + unsigned int len; + unsigned char *data; + u32 status; + +#if 0 + if ((bp->status_blk->status_idx == bp->last_status_idx) && + (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) & + BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) { + + bp->last_status_idx = bp->status_blk->status_idx; + REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, + BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | + BNX2_PCICFG_INT_ACK_CMD_MASK_INT | + bp->last_status_idx); + return 0; + } +#endif + + if ((bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) && !retrieve) + return 1; + + if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) { + + hw_cons = bp->hw_rx_cons = bp->status_blk->status_rx_quick_consumer_index0; + if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) { + hw_cons++; + } + sw_cons = bp->rx_cons; + sw_prod = bp->rx_prod; + + rmb(); + if (sw_cons != hw_cons) { + + sw_ring_cons = RX_RING_IDX(sw_cons); + sw_ring_prod = RX_RING_IDX(sw_prod); + + data = bus_to_virt(bp->rx_desc_ring[sw_ring_cons].rx_bd_haddr_lo); + + rx_hdr = (struct l2_fhdr *)data; + len = rx_hdr->l2_fhdr_pkt_len - 4; + if ((len > (ETH_MAX_MTU + ETH_HLEN)) || + ((status = rx_hdr->l2_fhdr_status) & + (L2_FHDR_ERRORS_BAD_CRC | + L2_FHDR_ERRORS_PHY_DECODE | + L2_FHDR_ERRORS_ALIGNMENT | + L2_FHDR_ERRORS_TOO_SHORT | + L2_FHDR_ERRORS_GIANT_FRAME))) { + result = 0; + } + else + { + nic->packetlen = len; + memcpy(nic->packet, data + bp->rx_offset, len); + result = 1; + } + + /* Reuse the buffer */ + bp->rx_prod_bseq += bp->rx_buf_use_size; + if (sw_cons != sw_prod) { + cons_bd = &bp->rx_desc_ring[sw_ring_cons]; + prod_bd = &bp->rx_desc_ring[sw_ring_prod]; + prod_bd->rx_bd_haddr_hi = 0; /* Etherboot runs under 4GB */ + prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; + } + + sw_cons = NEXT_RX_BD(sw_cons); + sw_prod = NEXT_RX_BD(sw_prod); + + } + + bp->rx_cons = sw_cons; + bp->rx_prod = sw_prod; + + REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, bp->rx_prod); + + REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq); + + wmb(); + + } + + bnx2_poll_link(bp); + +#if 0 + bp->last_status_idx = bp->status_blk->status_idx; + rmb(); + + REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, + BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | + BNX2_PCICFG_INT_ACK_CMD_MASK_INT | + bp->last_status_idx); + + REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); +#endif + + return result; +} + +static void +bnx2_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE: break; + case ENABLE: break; + case FORCE: break; + } +} + +static struct nic_operations bnx2_operations = { + .connect = dummy_connect, + .poll = bnx2_poll, + .transmit = bnx2_transmit, + .irq = bnx2_irq, +}; + +static int +bnx2_probe(struct nic *nic, struct pci_device *pdev) +{ + struct bnx2 *bp = &bnx2; + int i, rc; + + if (pdev == 0) + return 0; + + memset(bp, 0, sizeof(*bp)); + + rc = bnx2_init_board(pdev, nic); + if (rc < 0) { + return 0; + } + + /* + nic->disable = bnx2_disable; + nic->transmit = bnx2_transmit; + nic->poll = bnx2_poll; + nic->irq = bnx2_irq; + */ + + nic->nic_op = &bnx2_operations; + + memcpy(nic->node_addr, bp->mac_addr, ETH_ALEN); + printf("Ethernet addr: %s\n", eth_ntoa( nic->node_addr ) ); + printf("Broadcom NetXtreme II (%c%d) PCI%s %s %dMHz\n", + (int) ((CHIP_ID(bp) & 0xf000) >> 12) + 'A', + (int) ((CHIP_ID(bp) & 0x0ff0) >> 4), + ((bp->flags & PCIX_FLAG) ? "-X" : ""), + ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"), + bp->bus_speed_mhz); + + bnx2_set_power_state_0(bp); + bnx2_disable_int(bp); + + bnx2_alloc_mem(bp); + + rc = bnx2_init_nic(bp); + if (rc) { + return 0; + } + + bnx2_poll_link(bp); + for(i = 0; !bp->link_up && (i < VALID_LINK_TIMEOUT*100); i++) { + mdelay(1); + bnx2_poll_link(bp); + } +#if 1 + if (!bp->link_up){ + printf("Valid link not established\n"); + goto err_out_disable; + } +#endif + + return 1; + +err_out_disable: + bnx2_disable(nic); + return 0; +} + +static struct pci_device_id bnx2_nics[] = { + PCI_ROM(0x14e4, 0x164a, "bnx2-5706", "Broadcom NetXtreme II BCM5706", 0), + PCI_ROM(0x14e4, 0x164c, "bnx2-5708", "Broadcom NetXtreme II BCM5708", 0), + PCI_ROM(0x14e4, 0x16aa, "bnx2-5706S", "Broadcom NetXtreme II BCM5706S", 0), + PCI_ROM(0x14e4, 0x16ac, "bnx2-5708S", "Broadcom NetXtreme II BCM5708S", 0), +}; + +PCI_DRIVER ( bnx2_driver, bnx2_nics, PCI_NO_CLASS ); + +DRIVER ( "BNX2", nic_driver, pci_driver, bnx2_driver, bnx2_probe, bnx2_disable ); + +/* +static struct pci_driver bnx2_driver __pci_driver = { + .type = NIC_DRIVER, + .name = "BNX2", + .probe = bnx2_probe, + .ids = bnx2_nics, + .id_count = sizeof(bnx2_nics)/sizeof(bnx2_nics[0]), + .class = 0, +}; +*/ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/bnx2.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/bnx2.h new file mode 100644 index 0000000..9267868 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/bnx2.h @@ -0,0 +1,4598 @@ +/* bnx2.h: Broadcom NX2 network driver. + * + * Copyright (c) 2004, 2005, 2006 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation. + * + * Written by: Michael Chan (mchan@broadcom.com) + */ + +FILE_LICENCE ( GPL_ANY ); + +#ifndef BNX2_H +#define BNX2_H + +#define L1_CACHE_BYTES 128 /* Rough approximaition of the cache line size */ +#define L1_CACHE_ALIGN(X) (((X) + L1_CACHE_BYTES-1)&~(L1_CACHE_BYTES -1)) + +typedef unsigned long dma_addr_t; + +/* From pci.h */ +typedef int pci_power_t; + +#define PCI_D0 ((pci_power_t) 0) +#define PCI_D1 ((pci_power_t) 1) +#define PCI_D2 ((pci_power_t) 2) +#define PCI_D3hot ((pci_power_t) 3) +#define PCI_D3cold ((pci_power_t) 4) +#define PCI_UNKNOWN ((pci_power_t) 5) +#define PCI_POWER_ERROR ((pci_power_t) -1) + +/* From pci_regs.h */ + +#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ +#define PCI_X_CMD 2 /* Modes & Features */ +#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ + +/* From mii.h */ + +/* Indicates what features are advertised by the interface. */ +#define ADVERTISED_10baseT_Half (1 << 0) +#define ADVERTISED_10baseT_Full (1 << 1) +#define ADVERTISED_100baseT_Half (1 << 2) +#define ADVERTISED_100baseT_Full (1 << 3) +#define ADVERTISED_1000baseT_Half (1 << 4) +#define ADVERTISED_1000baseT_Full (1 << 5) +#define ADVERTISED_Autoneg (1 << 6) +#define ADVERTISED_TP (1 << 7) +#define ADVERTISED_AUI (1 << 8) +#define ADVERTISED_MII (1 << 9) +#define ADVERTISED_FIBRE (1 << 10) +#define ADVERTISED_BNC (1 << 11) + +/* The following are all involved in forcing a particular link + * mode for the device for setting things. When getting the + * devices settings, these indicate the current mode and whether + * it was foced up into this mode or autonegotiated. + */ + +/* Duplex, half or full. */ +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 +#define DUPLEX_INVALID 0x02 + +/* Which connector port. */ +#define PORT_TP 0x00 +#define PORT_AUI 0x01 +#define PORT_MII 0x02 +#define PORT_FIBRE 0x03 +#define PORT_BNC 0x04 + +/* Which tranceiver to use. */ +#define XCVR_INTERNAL 0x00 +#define XCVR_EXTERNAL 0x01 +#define XCVR_DUMMY1 0x02 +#define XCVR_DUMMY2 0x03 +#define XCVR_DUMMY3 0x04 + +/* Enable or disable autonegotiation. If this is set to enable, + * the forced link modes above are completely ignored. + */ +#define AUTONEG_DISABLE 0x00 +#define AUTONEG_ENABLE 0x01 + +/* Wake-On-Lan options. */ +#define WAKE_PHY (1 << 0) +#define WAKE_UCAST (1 << 1) +#define WAKE_MCAST (1 << 2) +#define WAKE_BCAST (1 << 3) +#define WAKE_ARP (1 << 4) +#define WAKE_MAGIC (1 << 5) +#define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */ + +/* The following are all involved in forcing a particular link + * * mode for the device for setting things. When getting the + * * devices settings, these indicate the current mode and whether + * * it was foced up into this mode or autonegotiated. + * */ + +/* The forced speed, 10Mb, 100Mb, gigabit. */ +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_INVALID 0 /* XXX was 3 */ + + +/* Duplex, half or full. */ +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 +#define DUPLEX_INVALID 0x02 + +/* Which connector port. */ +#define PORT_TP 0x00 +#define PORT_AUI 0x01 +#define PORT_MII 0x02 +#define PORT_FIBRE 0x03 +#define PORT_BNC 0x04 + +/* Which tranceiver to use. */ +#define XCVR_INTERNAL 0x00 +#define XCVR_EXTERNAL 0x01 +#define XCVR_DUMMY1 0x02 +#define XCVR_DUMMY2 0x03 +#define XCVR_DUMMY3 0x04 + +/* Enable or disable autonegotiation. If this is set to enable, + * * the forced link modes above are completely ignored. + * */ +#define AUTONEG_DISABLE 0x00 +#define AUTONEG_ENABLE 0x01 + +/* Wake-On-Lan options. */ +#define WAKE_PHY (1 << 0) +#define WAKE_UCAST (1 << 1) +#define WAKE_MCAST (1 << 2) +#define WAKE_BCAST (1 << 3) +#define WAKE_ARP (1 << 4) +#define WAKE_MAGIC (1 << 5) +#define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */ + +/* Hardware data structures and register definitions automatically + * generated from RTL code. Do not modify. + */ + +/* + * tx_bd definition + */ +struct tx_bd { + u32 tx_bd_haddr_hi; + u32 tx_bd_haddr_lo; + u32 tx_bd_mss_nbytes; + u32 tx_bd_vlan_tag_flags; + #define TX_BD_FLAGS_CONN_FAULT (1<<0) + #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) + #define TX_BD_FLAGS_IP_CKSUM (1<<2) + #define TX_BD_FLAGS_VLAN_TAG (1<<3) + #define TX_BD_FLAGS_COAL_NOW (1<<4) + #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) + #define TX_BD_FLAGS_END (1<<6) + #define TX_BD_FLAGS_START (1<<7) + #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) + #define TX_BD_FLAGS_SW_FLAGS (1<<13) + #define TX_BD_FLAGS_SW_SNAP (1<<14) + #define TX_BD_FLAGS_SW_LSO (1<<15) + +}; + + +/* + * rx_bd definition + */ +struct rx_bd { + u32 rx_bd_haddr_hi; + u32 rx_bd_haddr_lo; + u32 rx_bd_len; + u32 rx_bd_flags; + #define RX_BD_FLAGS_NOPUSH (1<<0) + #define RX_BD_FLAGS_DUMMY (1<<1) + #define RX_BD_FLAGS_END (1<<2) + #define RX_BD_FLAGS_START (1<<3) + +}; + + +/* + * status_block definition + */ +struct status_block { + u32 status_attn_bits; + #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) + #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) + #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) + #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) + #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) + #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) + #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) + #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) + #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) + #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) + #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) + #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) + #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) + #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) + #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) + #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) + #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) + #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) + #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) + #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) + #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) + #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) + #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) + #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) + #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) + #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) + #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) + #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) + #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) + + u32 status_attn_bits_ack; +#if __BYTE_ORDER == __BIG_ENDIAN + u16 status_tx_quick_consumer_index0; + u16 status_tx_quick_consumer_index1; + u16 status_tx_quick_consumer_index2; + u16 status_tx_quick_consumer_index3; + u16 status_rx_quick_consumer_index0; + u16 status_rx_quick_consumer_index1; + u16 status_rx_quick_consumer_index2; + u16 status_rx_quick_consumer_index3; + u16 status_rx_quick_consumer_index4; + u16 status_rx_quick_consumer_index5; + u16 status_rx_quick_consumer_index6; + u16 status_rx_quick_consumer_index7; + u16 status_rx_quick_consumer_index8; + u16 status_rx_quick_consumer_index9; + u16 status_rx_quick_consumer_index10; + u16 status_rx_quick_consumer_index11; + u16 status_rx_quick_consumer_index12; + u16 status_rx_quick_consumer_index13; + u16 status_rx_quick_consumer_index14; + u16 status_rx_quick_consumer_index15; + u16 status_completion_producer_index; + u16 status_cmd_consumer_index; + u16 status_idx; + u16 status_unused; +#elif __BYTE_ORDER == __LITTLE_ENDIAN + u16 status_tx_quick_consumer_index1; + u16 status_tx_quick_consumer_index0; + u16 status_tx_quick_consumer_index3; + u16 status_tx_quick_consumer_index2; + u16 status_rx_quick_consumer_index1; + u16 status_rx_quick_consumer_index0; + u16 status_rx_quick_consumer_index3; + u16 status_rx_quick_consumer_index2; + u16 status_rx_quick_consumer_index5; + u16 status_rx_quick_consumer_index4; + u16 status_rx_quick_consumer_index7; + u16 status_rx_quick_consumer_index6; + u16 status_rx_quick_consumer_index9; + u16 status_rx_quick_consumer_index8; + u16 status_rx_quick_consumer_index11; + u16 status_rx_quick_consumer_index10; + u16 status_rx_quick_consumer_index13; + u16 status_rx_quick_consumer_index12; + u16 status_rx_quick_consumer_index15; + u16 status_rx_quick_consumer_index14; + u16 status_cmd_consumer_index; + u16 status_completion_producer_index; + u16 status_unused; + u16 status_idx; +#endif +}; + + +/* + * statistics_block definition + */ +struct statistics_block { + u32 stat_IfHCInOctets_hi; + u32 stat_IfHCInOctets_lo; + u32 stat_IfHCInBadOctets_hi; + u32 stat_IfHCInBadOctets_lo; + u32 stat_IfHCOutOctets_hi; + u32 stat_IfHCOutOctets_lo; + u32 stat_IfHCOutBadOctets_hi; + u32 stat_IfHCOutBadOctets_lo; + u32 stat_IfHCInUcastPkts_hi; + u32 stat_IfHCInUcastPkts_lo; + u32 stat_IfHCInMulticastPkts_hi; + u32 stat_IfHCInMulticastPkts_lo; + u32 stat_IfHCInBroadcastPkts_hi; + u32 stat_IfHCInBroadcastPkts_lo; + u32 stat_IfHCOutUcastPkts_hi; + u32 stat_IfHCOutUcastPkts_lo; + u32 stat_IfHCOutMulticastPkts_hi; + u32 stat_IfHCOutMulticastPkts_lo; + u32 stat_IfHCOutBroadcastPkts_hi; + u32 stat_IfHCOutBroadcastPkts_lo; + u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; + u32 stat_Dot3StatsCarrierSenseErrors; + u32 stat_Dot3StatsFCSErrors; + u32 stat_Dot3StatsAlignmentErrors; + u32 stat_Dot3StatsSingleCollisionFrames; + u32 stat_Dot3StatsMultipleCollisionFrames; + u32 stat_Dot3StatsDeferredTransmissions; + u32 stat_Dot3StatsExcessiveCollisions; + u32 stat_Dot3StatsLateCollisions; + u32 stat_EtherStatsCollisions; + u32 stat_EtherStatsFragments; + u32 stat_EtherStatsJabbers; + u32 stat_EtherStatsUndersizePkts; + u32 stat_EtherStatsOverrsizePkts; + u32 stat_EtherStatsPktsRx64Octets; + u32 stat_EtherStatsPktsRx65Octetsto127Octets; + u32 stat_EtherStatsPktsRx128Octetsto255Octets; + u32 stat_EtherStatsPktsRx256Octetsto511Octets; + u32 stat_EtherStatsPktsRx512Octetsto1023Octets; + u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; + u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; + u32 stat_EtherStatsPktsTx64Octets; + u32 stat_EtherStatsPktsTx65Octetsto127Octets; + u32 stat_EtherStatsPktsTx128Octetsto255Octets; + u32 stat_EtherStatsPktsTx256Octetsto511Octets; + u32 stat_EtherStatsPktsTx512Octetsto1023Octets; + u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; + u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; + u32 stat_XonPauseFramesReceived; + u32 stat_XoffPauseFramesReceived; + u32 stat_OutXonSent; + u32 stat_OutXoffSent; + u32 stat_FlowControlDone; + u32 stat_MacControlFramesReceived; + u32 stat_XoffStateEntered; + u32 stat_IfInFramesL2FilterDiscards; + u32 stat_IfInRuleCheckerDiscards; + u32 stat_IfInFTQDiscards; + u32 stat_IfInMBUFDiscards; + u32 stat_IfInRuleCheckerP4Hit; + u32 stat_CatchupInRuleCheckerDiscards; + u32 stat_CatchupInFTQDiscards; + u32 stat_CatchupInMBUFDiscards; + u32 stat_CatchupInRuleCheckerP4Hit; + u32 stat_GenStat00; + u32 stat_GenStat01; + u32 stat_GenStat02; + u32 stat_GenStat03; + u32 stat_GenStat04; + u32 stat_GenStat05; + u32 stat_GenStat06; + u32 stat_GenStat07; + u32 stat_GenStat08; + u32 stat_GenStat09; + u32 stat_GenStat10; + u32 stat_GenStat11; + u32 stat_GenStat12; + u32 stat_GenStat13; + u32 stat_GenStat14; + u32 stat_GenStat15; +}; + + +/* + * l2_fhdr definition + */ +struct l2_fhdr { + u32 l2_fhdr_status; + #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) + #define L2_FHDR_STATUS_RULE_P2 (1<<3) + #define L2_FHDR_STATUS_RULE_P3 (1<<4) + #define L2_FHDR_STATUS_RULE_P4 (1<<5) + #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) + #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) + #define L2_FHDR_STATUS_RSS_HASH (1<<8) + #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) + #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) + #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) + + #define L2_FHDR_ERRORS_BAD_CRC (1<<17) + #define L2_FHDR_ERRORS_PHY_DECODE (1<<18) + #define L2_FHDR_ERRORS_ALIGNMENT (1<<19) + #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) + #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) + #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) + #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) + + u32 l2_fhdr_hash; +#if __BYTE_ORDER == __BIG_ENDIAN + u16 l2_fhdr_pkt_len; + u16 l2_fhdr_vlan_tag; + u16 l2_fhdr_ip_xsum; + u16 l2_fhdr_tcp_udp_xsum; +#elif __BYTE_ORDER == __LITTLE_ENDIAN + u16 l2_fhdr_vlan_tag; + u16 l2_fhdr_pkt_len; + u16 l2_fhdr_tcp_udp_xsum; + u16 l2_fhdr_ip_xsum; +#endif +}; + + +/* + * l2_context definition + */ +#define BNX2_L2CTX_TYPE 0x00000000 +#define BNX2_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) +#define BNX2_L2CTX_TYPE_TYPE (0xf<<28) +#define BNX2_L2CTX_TYPE_TYPE_EMPTY (0<<28) +#define BNX2_L2CTX_TYPE_TYPE_L2 (1<<28) + +#define BNX2_L2CTX_TX_HOST_BIDX 0x00000088 +#define BNX2_L2CTX_EST_NBD 0x00000088 +#define BNX2_L2CTX_CMD_TYPE 0x00000088 +#define BNX2_L2CTX_CMD_TYPE_TYPE (0xf<<24) +#define BNX2_L2CTX_CMD_TYPE_TYPE_L2 (0<<24) +#define BNX2_L2CTX_CMD_TYPE_TYPE_TCP (1<<24) + +#define BNX2_L2CTX_TX_HOST_BSEQ 0x00000090 +#define BNX2_L2CTX_TSCH_BSEQ 0x00000094 +#define BNX2_L2CTX_TBDR_BSEQ 0x00000098 +#define BNX2_L2CTX_TBDR_BOFF 0x0000009c +#define BNX2_L2CTX_TBDR_BIDX 0x0000009c +#define BNX2_L2CTX_TBDR_BHADDR_HI 0x000000a0 +#define BNX2_L2CTX_TBDR_BHADDR_LO 0x000000a4 +#define BNX2_L2CTX_TXP_BOFF 0x000000a8 +#define BNX2_L2CTX_TXP_BIDX 0x000000a8 +#define BNX2_L2CTX_TXP_BSEQ 0x000000ac + + +/* + * l2_bd_chain_context definition + */ +#define BNX2_L2CTX_BD_PRE_READ 0x00000000 +#define BNX2_L2CTX_CTX_SIZE 0x00000000 +#define BNX2_L2CTX_CTX_TYPE 0x00000000 +#define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) +#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) +#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) +#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) + +#define BNX2_L2CTX_HOST_BDIDX 0x00000004 +#define BNX2_L2CTX_HOST_BSEQ 0x00000008 +#define BNX2_L2CTX_NX_BSEQ 0x0000000c +#define BNX2_L2CTX_NX_BDHADDR_HI 0x00000010 +#define BNX2_L2CTX_NX_BDHADDR_LO 0x00000014 +#define BNX2_L2CTX_NX_BDIDX 0x00000018 + + +/* + * pci_config_l definition + * offset: 0000 + */ +#define BNX2_PCICFG_MISC_CONFIG 0x00000068 +#define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) +#define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) +#define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) +#define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) +#define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) +#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) +#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) +#define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) +#define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) +#define BNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) + +#define BNX2_PCICFG_MISC_STATUS 0x0000006c +#define BNX2_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0) +#define BNX2_PCICFG_MISC_STATUS_32BIT_DET (1L<<1) +#define BNX2_PCICFG_MISC_STATUS_M66EN (1L<<2) +#define BNX2_PCICFG_MISC_STATUS_PCIX_DET (1L<<3) +#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4) +#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4) +#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) +#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) +#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) + +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) +#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) + +#define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078 +#define BNX2_PCICFG_REG_WINDOW 0x00000080 +#define BNX2_PCICFG_INT_ACK_CMD 0x00000084 +#define BNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) +#define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) +#define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) +#define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) + +#define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088 +#define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c +#define BNX2_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 +#define BNX2_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 + + +/* + * pci_reg definition + * offset: 0x400 + */ +#define BNX2_PCI_GRC_WINDOW_ADDR 0x00000400 +#define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8) + +#define BNX2_PCI_CONFIG_1 0x00000404 +#define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) +#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) +#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) +#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8) +#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8) +#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8) +#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8) +#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8) +#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8) +#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11) +#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11) +#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11) +#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11) +#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11) +#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11) +#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) +#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) +#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) + +#define BNX2_PCI_CONFIG_2 0x00000408 +#define BNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) +#define BNX2_PCI_CONFIG_2_BAR1_64ENA (1L<<4) +#define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) +#define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) +#define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8) +#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8) +#define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16) +#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21) +#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21) +#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21) +#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21) +#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21) +#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) +#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) +#define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) + +#define BNX2_PCI_CONFIG_3 0x0000040c +#define BNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) +#define BNX2_PCI_CONFIG_3_FORCE_PME (1L<<24) +#define BNX2_PCI_CONFIG_3_PME_STATUS (1L<<25) +#define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26) +#define BNX2_PCI_CONFIG_3_PM_STATE (0x3L<<27) +#define BNX2_PCI_CONFIG_3_VAUX_PRESET (1L<<30) +#define BNX2_PCI_CONFIG_3_PCI_POWER (1L<<31) + +#define BNX2_PCI_PM_DATA_A 0x00000410 +#define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0) +#define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8) +#define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16) +#define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24) + +#define BNX2_PCI_PM_DATA_B 0x00000414 +#define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0) +#define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8) +#define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16) +#define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24) + +#define BNX2_PCI_SWAP_DIAG0 0x00000418 +#define BNX2_PCI_SWAP_DIAG1 0x0000041c +#define BNX2_PCI_EXP_ROM_ADDR 0x00000420 +#define BNX2_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) +#define BNX2_PCI_EXP_ROM_ADDR_REQ (1L<<31) + +#define BNX2_PCI_EXP_ROM_DATA 0x00000424 +#define BNX2_PCI_VPD_INTF 0x00000428 +#define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0) + +#define BNX2_PCI_VPD_ADDR_FLAG 0x0000042c +#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) +#define BNX2_PCI_VPD_ADDR_FLAG_WR (1<<15) + +#define BNX2_PCI_VPD_DATA 0x00000430 +#define BNX2_PCI_ID_VAL1 0x00000434 +#define BNX2_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0) +#define BNX2_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16) + +#define BNX2_PCI_ID_VAL2 0x00000438 +#define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0) +#define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16) + +#define BNX2_PCI_ID_VAL3 0x0000043c +#define BNX2_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0) +#define BNX2_PCI_ID_VAL3_REVISION_ID (0xffL<<24) + +#define BNX2_PCI_ID_VAL4 0x00000440 +#define BNX2_PCI_ID_VAL4_CAP_ENA (0xfL<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_0 (0L<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_1 (1L<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_2 (2L<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_3 (3L<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_4 (4L<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_5 (5L<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_6 (6L<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_7 (7L<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_8 (8L<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_9 (9L<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_10 (10L<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_11 (11L<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_12 (12L<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) +#define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) +#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) +#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) +#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) +#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) +#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) +#define BNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) +#define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) +#define BNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15) +#define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) +#define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) +#define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) +#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) +#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) + +#define BNX2_PCI_ID_VAL5 0x00000444 +#define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0) +#define BNX2_PCI_ID_VAL5_D2_SUPPORT (1L<<1) +#define BNX2_PCI_ID_VAL5_PME_IN_D0 (1L<<2) +#define BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3) +#define BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4) +#define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) + +#define BNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448 +#define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) +#define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9) +#define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16) +#define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24) + +#define BNX2_PCI_ID_VAL6 0x0000044c +#define BNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0) +#define BNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8) +#define BNX2_PCI_ID_VAL6_BIST (0xffL<<16) + +#define BNX2_PCI_MSI_DATA 0x00000450 +#define BNX2_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) + +#define BNX2_PCI_MSI_ADDR_H 0x00000454 +#define BNX2_PCI_MSI_ADDR_L 0x00000458 + + +/* + * misc_reg definition + * offset: 0x800 + */ +#define BNX2_MISC_COMMAND 0x00000800 +#define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0) +#define BNX2_MISC_COMMAND_DISABLE_ALL (1L<<1) +#define BNX2_MISC_COMMAND_CORE_RESET (1L<<4) +#define BNX2_MISC_COMMAND_HARD_RESET (1L<<5) +#define BNX2_MISC_COMMAND_PAR_ERROR (1L<<8) +#define BNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) + +#define BNX2_MISC_CFG 0x00000804 +#define BNX2_MISC_CFG_PCI_GRC_TMOUT (1L<<0) +#define BNX2_MISC_CFG_NVM_WR_EN (0x3L<<1) +#define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) +#define BNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1) +#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1) +#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) +#define BNX2_MISC_CFG_BIST_EN (1L<<3) +#define BNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) +#define BNX2_MISC_CFG_BYPASS_BSCAN (1L<<5) +#define BNX2_MISC_CFG_BYPASS_EJTAG (1L<<6) +#define BNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) +#define BNX2_MISC_CFG_LEDMODE (0x3L<<8) +#define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8) +#define BNX2_MISC_CFG_LEDMODE_GPHY1 (1L<<8) +#define BNX2_MISC_CFG_LEDMODE_GPHY2 (2L<<8) + +#define BNX2_MISC_ID 0x00000808 +#define BNX2_MISC_ID_BOND_ID (0xfL<<0) +#define BNX2_MISC_ID_CHIP_METAL (0xffL<<4) +#define BNX2_MISC_ID_CHIP_REV (0xfL<<12) +#define BNX2_MISC_ID_CHIP_NUM (0xffffL<<16) + +#define BNX2_MISC_ENABLE_STATUS_BITS 0x0000080c +#define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0) +#define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1) +#define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2) +#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3) +#define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4) +#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5) +#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) +#define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7) +#define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8) +#define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9) +#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10) +#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) +#define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12) +#define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13) +#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14) +#define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15) +#define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16) +#define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17) +#define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18) +#define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19) +#define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) +#define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21) +#define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22) +#define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23) +#define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) +#define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) +#define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) +#define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) + +#define BNX2_MISC_ENABLE_SET_BITS 0x00000810 +#define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) +#define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1) +#define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2) +#define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3) +#define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4) +#define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5) +#define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) +#define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7) +#define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8) +#define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9) +#define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10) +#define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) +#define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12) +#define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13) +#define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14) +#define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15) +#define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16) +#define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17) +#define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18) +#define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19) +#define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) +#define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21) +#define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22) +#define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23) +#define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) +#define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) +#define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) +#define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) + +#define BNX2_MISC_ENABLE_CLR_BITS 0x00000814 +#define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) +#define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1) +#define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2) +#define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3) +#define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4) +#define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5) +#define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) +#define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7) +#define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8) +#define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9) +#define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10) +#define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) +#define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12) +#define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13) +#define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14) +#define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15) +#define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16) +#define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17) +#define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18) +#define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19) +#define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) +#define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21) +#define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22) +#define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23) +#define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) +#define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) +#define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) +#define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) + +#define BNX2_MISC_CLOCK_CONTROL_BITS 0x00000818 +#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) +#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) +#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) +#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) +#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) +#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) +#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) +#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) +#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) +#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) +#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) +#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) +#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) +#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) +#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) +#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) +#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) +#define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) +#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) +#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) +#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) +#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) +#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) +#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) +#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) +#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) +#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) +#define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) +#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) + +#define BNX2_MISC_GPIO 0x0000081c +#define BNX2_MISC_GPIO_VALUE (0xffL<<0) +#define BNX2_MISC_GPIO_SET (0xffL<<8) +#define BNX2_MISC_GPIO_CLR (0xffL<<16) +#define BNX2_MISC_GPIO_FLOAT (0xffL<<24) + +#define BNX2_MISC_GPIO_INT 0x00000820 +#define BNX2_MISC_GPIO_INT_INT_STATE (0xfL<<0) +#define BNX2_MISC_GPIO_INT_OLD_VALUE (0xfL<<8) +#define BNX2_MISC_GPIO_INT_OLD_SET (0xfL<<16) +#define BNX2_MISC_GPIO_INT_OLD_CLR (0xfL<<24) + +#define BNX2_MISC_CONFIG_LFSR 0x00000824 +#define BNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0) + +#define BNX2_MISC_LFSR_MASK_BITS 0x00000828 +#define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0) +#define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1) +#define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2) +#define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3) +#define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4) +#define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5) +#define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) +#define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7) +#define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8) +#define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9) +#define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10) +#define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) +#define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12) +#define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13) +#define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14) +#define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15) +#define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16) +#define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17) +#define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18) +#define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19) +#define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) +#define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21) +#define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22) +#define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23) +#define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) +#define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) +#define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) +#define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) + +#define BNX2_MISC_ARB_REQ0 0x0000082c +#define BNX2_MISC_ARB_REQ1 0x00000830 +#define BNX2_MISC_ARB_REQ2 0x00000834 +#define BNX2_MISC_ARB_REQ3 0x00000838 +#define BNX2_MISC_ARB_REQ4 0x0000083c +#define BNX2_MISC_ARB_FREE0 0x00000840 +#define BNX2_MISC_ARB_FREE1 0x00000844 +#define BNX2_MISC_ARB_FREE2 0x00000848 +#define BNX2_MISC_ARB_FREE3 0x0000084c +#define BNX2_MISC_ARB_FREE4 0x00000850 +#define BNX2_MISC_ARB_REQ_STATUS0 0x00000854 +#define BNX2_MISC_ARB_REQ_STATUS1 0x00000858 +#define BNX2_MISC_ARB_REQ_STATUS2 0x0000085c +#define BNX2_MISC_ARB_REQ_STATUS3 0x00000860 +#define BNX2_MISC_ARB_REQ_STATUS4 0x00000864 +#define BNX2_MISC_ARB_GNT0 0x00000868 +#define BNX2_MISC_ARB_GNT0_0 (0x7L<<0) +#define BNX2_MISC_ARB_GNT0_1 (0x7L<<4) +#define BNX2_MISC_ARB_GNT0_2 (0x7L<<8) +#define BNX2_MISC_ARB_GNT0_3 (0x7L<<12) +#define BNX2_MISC_ARB_GNT0_4 (0x7L<<16) +#define BNX2_MISC_ARB_GNT0_5 (0x7L<<20) +#define BNX2_MISC_ARB_GNT0_6 (0x7L<<24) +#define BNX2_MISC_ARB_GNT0_7 (0x7L<<28) + +#define BNX2_MISC_ARB_GNT1 0x0000086c +#define BNX2_MISC_ARB_GNT1_8 (0x7L<<0) +#define BNX2_MISC_ARB_GNT1_9 (0x7L<<4) +#define BNX2_MISC_ARB_GNT1_10 (0x7L<<8) +#define BNX2_MISC_ARB_GNT1_11 (0x7L<<12) +#define BNX2_MISC_ARB_GNT1_12 (0x7L<<16) +#define BNX2_MISC_ARB_GNT1_13 (0x7L<<20) +#define BNX2_MISC_ARB_GNT1_14 (0x7L<<24) +#define BNX2_MISC_ARB_GNT1_15 (0x7L<<28) + +#define BNX2_MISC_ARB_GNT2 0x00000870 +#define BNX2_MISC_ARB_GNT2_16 (0x7L<<0) +#define BNX2_MISC_ARB_GNT2_17 (0x7L<<4) +#define BNX2_MISC_ARB_GNT2_18 (0x7L<<8) +#define BNX2_MISC_ARB_GNT2_19 (0x7L<<12) +#define BNX2_MISC_ARB_GNT2_20 (0x7L<<16) +#define BNX2_MISC_ARB_GNT2_21 (0x7L<<20) +#define BNX2_MISC_ARB_GNT2_22 (0x7L<<24) +#define BNX2_MISC_ARB_GNT2_23 (0x7L<<28) + +#define BNX2_MISC_ARB_GNT3 0x00000874 +#define BNX2_MISC_ARB_GNT3_24 (0x7L<<0) +#define BNX2_MISC_ARB_GNT3_25 (0x7L<<4) +#define BNX2_MISC_ARB_GNT3_26 (0x7L<<8) +#define BNX2_MISC_ARB_GNT3_27 (0x7L<<12) +#define BNX2_MISC_ARB_GNT3_28 (0x7L<<16) +#define BNX2_MISC_ARB_GNT3_29 (0x7L<<20) +#define BNX2_MISC_ARB_GNT3_30 (0x7L<<24) +#define BNX2_MISC_ARB_GNT3_31 (0x7L<<28) + +#define BNX2_MISC_PRBS_CONTROL 0x00000878 +#define BNX2_MISC_PRBS_CONTROL_EN (1L<<0) +#define BNX2_MISC_PRBS_CONTROL_RSTB (1L<<1) +#define BNX2_MISC_PRBS_CONTROL_INV (1L<<2) +#define BNX2_MISC_PRBS_CONTROL_ERR_CLR (1L<<3) +#define BNX2_MISC_PRBS_CONTROL_ORDER (0x3L<<4) +#define BNX2_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4) +#define BNX2_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4) +#define BNX2_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4) +#define BNX2_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4) + +#define BNX2_MISC_PRBS_STATUS 0x0000087c +#define BNX2_MISC_PRBS_STATUS_LOCK (1L<<0) +#define BNX2_MISC_PRBS_STATUS_STKY (1L<<1) +#define BNX2_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2) +#define BNX2_MISC_PRBS_STATUS_STATE (0xfL<<16) + +#define BNX2_MISC_SM_ASF_CONTROL 0x00000880 +#define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) +#define BNX2_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1) +#define BNX2_MISC_SM_ASF_CONTROL_WG_TO (1L<<2) +#define BNX2_MISC_SM_ASF_CONTROL_HB_TO (1L<<3) +#define BNX2_MISC_SM_ASF_CONTROL_PA_TO (1L<<4) +#define BNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) +#define BNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) +#define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) +#define BNX2_MISC_SM_ASF_CONTROL_RES (0xfL<<8) +#define BNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) +#define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) +#define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) +#define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) +#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16) +#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24) +#define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) +#define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) + +#define BNX2_MISC_SMB_IN 0x00000884 +#define BNX2_MISC_SMB_IN_DAT_IN (0xffL<<0) +#define BNX2_MISC_SMB_IN_RDY (1L<<8) +#define BNX2_MISC_SMB_IN_DONE (1L<<9) +#define BNX2_MISC_SMB_IN_FIRSTBYTE (1L<<10) +#define BNX2_MISC_SMB_IN_STATUS (0x7L<<11) +#define BNX2_MISC_SMB_IN_STATUS_OK (0x0L<<11) +#define BNX2_MISC_SMB_IN_STATUS_PEC (0x1L<<11) +#define BNX2_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11) +#define BNX2_MISC_SMB_IN_STATUS_STOP (0x3L<<11) +#define BNX2_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11) + +#define BNX2_MISC_SMB_OUT 0x00000888 +#define BNX2_MISC_SMB_OUT_DAT_OUT (0xffL<<0) +#define BNX2_MISC_SMB_OUT_RDY (1L<<8) +#define BNX2_MISC_SMB_OUT_START (1L<<9) +#define BNX2_MISC_SMB_OUT_LAST (1L<<10) +#define BNX2_MISC_SMB_OUT_ACC_TYPE (1L<<11) +#define BNX2_MISC_SMB_OUT_ENB_PEC (1L<<12) +#define BNX2_MISC_SMB_OUT_GET_RX_LEN (1L<<13) +#define BNX2_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14) +#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) +#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) +#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) +#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) +#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) +#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) +#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) +#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) +#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) +#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20) +#define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) +#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) +#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) +#define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27) +#define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28) + +#define BNX2_MISC_SMB_WATCHDOG 0x0000088c +#define BNX2_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0) + +#define BNX2_MISC_SMB_HEARTBEAT 0x00000890 +#define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0) + +#define BNX2_MISC_SMB_POLL_ASF 0x00000894 +#define BNX2_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0) + +#define BNX2_MISC_SMB_POLL_LEGACY 0x00000898 +#define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0) + +#define BNX2_MISC_SMB_RETRAN 0x0000089c +#define BNX2_MISC_SMB_RETRAN_RETRAN (0xffL<<0) + +#define BNX2_MISC_SMB_TIMESTAMP 0x000008a0 +#define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0) + +#define BNX2_MISC_PERR_ENA0 0x000008a4 +#define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0) +#define BNX2_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1) +#define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2) +#define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3) +#define BNX2_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4) +#define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5) +#define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6) +#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7) +#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8) +#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9) +#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10) +#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11) +#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12) +#define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13) +#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14) +#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15) +#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16) +#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17) +#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18) +#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19) +#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20) +#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21) +#define BNX2_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22) +#define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23) +#define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24) +#define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25) +#define BNX2_MISC_PERR_ENA0_RBDC_MISC (1L<<26) +#define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27) +#define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28) +#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) +#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) +#define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) + +#define BNX2_MISC_PERR_ENA1 0x000008a8 +#define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) +#define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1) +#define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2) +#define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3) +#define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4) +#define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5) +#define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6) +#define BNX2_MISC_PERR_ENA1_TBDC_MISC (1L<<7) +#define BNX2_MISC_PERR_ENA1_TDMA_MISC (1L<<8) +#define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9) +#define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10) +#define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11) +#define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12) +#define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13) +#define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14) +#define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15) +#define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16) +#define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17) +#define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18) +#define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19) +#define BNX2_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20) +#define BNX2_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21) +#define BNX2_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22) +#define BNX2_MISC_PERR_ENA1_CSQ_MISC (1L<<23) +#define BNX2_MISC_PERR_ENA1_CPQ_MISC (1L<<24) +#define BNX2_MISC_PERR_ENA1_MCPQ_MISC (1L<<25) +#define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26) +#define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27) +#define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) +#define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) +#define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) +#define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) + +#define BNX2_MISC_PERR_ENA2 0x000008ac +#define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0) +#define BNX2_MISC_PERR_ENA2_COMXQ_MISC (1L<<1) +#define BNX2_MISC_PERR_ENA2_COMTQ_MISC (1L<<2) +#define BNX2_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3) +#define BNX2_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4) +#define BNX2_MISC_PERR_ENA2_TXPQ_MISC (1L<<5) +#define BNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) +#define BNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) +#define BNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8) + +#define BNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0 +#define BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) +#define BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) + +#define BNX2_MISC_VREG_CONTROL 0x000008b4 +#define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0) +#define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4) + +#define BNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8 +#define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) + +#define BNX2_MISC_UNUSED0 0x000008bc + + +/* + * nvm_reg definition + * offset: 0x6400 + */ +#define BNX2_NVM_COMMAND 0x00006400 +#define BNX2_NVM_COMMAND_RST (1L<<0) +#define BNX2_NVM_COMMAND_DONE (1L<<3) +#define BNX2_NVM_COMMAND_DOIT (1L<<4) +#define BNX2_NVM_COMMAND_WR (1L<<5) +#define BNX2_NVM_COMMAND_ERASE (1L<<6) +#define BNX2_NVM_COMMAND_FIRST (1L<<7) +#define BNX2_NVM_COMMAND_LAST (1L<<8) +#define BNX2_NVM_COMMAND_WREN (1L<<16) +#define BNX2_NVM_COMMAND_WRDI (1L<<17) +#define BNX2_NVM_COMMAND_EWSR (1L<<18) +#define BNX2_NVM_COMMAND_WRSR (1L<<19) + +#define BNX2_NVM_STATUS 0x00006404 +#define BNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0) +#define BNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4) +#define BNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) + +#define BNX2_NVM_WRITE 0x00006408 +#define BNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) +#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0) +#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0) +#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0) +#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0) +#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) +#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) +#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) + +#define BNX2_NVM_ADDR 0x0000640c +#define BNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) +#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0) +#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0) +#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0) +#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0) +#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) +#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) +#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) + +#define BNX2_NVM_READ 0x00006410 +#define BNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) +#define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0) +#define BNX2_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0) +#define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0) +#define BNX2_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0) +#define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) +#define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0) +#define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0) + +#define BNX2_NVM_CFG1 0x00006414 +#define BNX2_NVM_CFG1_FLASH_MODE (1L<<0) +#define BNX2_NVM_CFG1_BUFFER_MODE (1L<<1) +#define BNX2_NVM_CFG1_PASS_MODE (1L<<2) +#define BNX2_NVM_CFG1_BITBANG_MODE (1L<<3) +#define BNX2_NVM_CFG1_STATUS_BIT (0x7L<<4) +#define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4) +#define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) +#define BNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) +#define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) +#define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24) +#define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25) +#define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31) + +#define BNX2_NVM_CFG2 0x00006418 +#define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0) +#define BNX2_NVM_CFG2_DUMMY (0xffL<<8) +#define BNX2_NVM_CFG2_STATUS_CMD (0xffL<<16) + +#define BNX2_NVM_CFG3 0x0000641c +#define BNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) +#define BNX2_NVM_CFG3_WRITE_CMD (0xffL<<8) +#define BNX2_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16) +#define BNX2_NVM_CFG3_READ_CMD (0xffL<<24) + +#define BNX2_NVM_SW_ARB 0x00006420 +#define BNX2_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0) +#define BNX2_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) +#define BNX2_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2) +#define BNX2_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3) +#define BNX2_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4) +#define BNX2_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) +#define BNX2_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6) +#define BNX2_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7) +#define BNX2_NVM_SW_ARB_ARB_ARB0 (1L<<8) +#define BNX2_NVM_SW_ARB_ARB_ARB1 (1L<<9) +#define BNX2_NVM_SW_ARB_ARB_ARB2 (1L<<10) +#define BNX2_NVM_SW_ARB_ARB_ARB3 (1L<<11) +#define BNX2_NVM_SW_ARB_REQ0 (1L<<12) +#define BNX2_NVM_SW_ARB_REQ1 (1L<<13) +#define BNX2_NVM_SW_ARB_REQ2 (1L<<14) +#define BNX2_NVM_SW_ARB_REQ3 (1L<<15) + +#define BNX2_NVM_ACCESS_ENABLE 0x00006424 +#define BNX2_NVM_ACCESS_ENABLE_EN (1L<<0) +#define BNX2_NVM_ACCESS_ENABLE_WR_EN (1L<<1) + +#define BNX2_NVM_WRITE1 0x00006428 +#define BNX2_NVM_WRITE1_WREN_CMD (0xffL<<0) +#define BNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8) +#define BNX2_NVM_WRITE1_SR_DATA (0xffL<<16) + + + +/* + * dma_reg definition + * offset: 0xc00 + */ +#define BNX2_DMA_COMMAND 0x00000c00 +#define BNX2_DMA_COMMAND_ENABLE (1L<<0) + +#define BNX2_DMA_STATUS 0x00000c04 +#define BNX2_DMA_STATUS_PAR_ERROR_STATE (1L<<0) +#define BNX2_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16) +#define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17) +#define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18) +#define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19) +#define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20) +#define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21) +#define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22) +#define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) +#define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) +#define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) + +#define BNX2_DMA_CONFIG 0x00000c08 +#define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) +#define BNX2_DMA_CONFIG_DATA_WORD_SWAP (1L<<1) +#define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4) +#define BNX2_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5) +#define BNX2_DMA_CONFIG_ONE_DMA (1L<<6) +#define BNX2_DMA_CONFIG_CNTL_TWO_DMA (1L<<7) +#define BNX2_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8) +#define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10) +#define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11) +#define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12) +#define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16) +#define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20) +#define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23) +#define BNX2_DMA_CONFIG_BIG_SIZE (0xfL<<24) +#define BNX2_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24) +#define BNX2_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24) +#define BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) +#define BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) +#define BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) + +#define BNX2_DMA_BLACKOUT 0x00000c0c +#define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) +#define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) +#define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) + +#define BNX2_DMA_RCHAN_STAT 0x00000c30 +#define BNX2_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) +#define BNX2_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) +#define BNX2_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) +#define BNX2_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) +#define BNX2_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) +#define BNX2_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) +#define BNX2_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) +#define BNX2_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) +#define BNX2_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) +#define BNX2_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) +#define BNX2_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) +#define BNX2_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) +#define BNX2_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) +#define BNX2_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) +#define BNX2_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) +#define BNX2_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) + +#define BNX2_DMA_WCHAN_STAT 0x00000c34 +#define BNX2_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) +#define BNX2_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) +#define BNX2_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) +#define BNX2_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) +#define BNX2_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) +#define BNX2_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) +#define BNX2_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) +#define BNX2_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) +#define BNX2_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) +#define BNX2_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) +#define BNX2_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) +#define BNX2_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) +#define BNX2_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) +#define BNX2_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) +#define BNX2_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) +#define BNX2_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) + +#define BNX2_DMA_RCHAN_ASSIGNMENT 0x00000c38 +#define BNX2_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) +#define BNX2_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) +#define BNX2_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) +#define BNX2_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) +#define BNX2_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) +#define BNX2_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) +#define BNX2_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) +#define BNX2_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) + +#define BNX2_DMA_WCHAN_ASSIGNMENT 0x00000c3c +#define BNX2_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) +#define BNX2_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) +#define BNX2_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) +#define BNX2_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) +#define BNX2_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) +#define BNX2_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) +#define BNX2_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) +#define BNX2_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) + +#define BNX2_DMA_RCHAN_STAT_00 0x00000c40 +#define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) + +#define BNX2_DMA_RCHAN_STAT_01 0x00000c44 +#define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) + +#define BNX2_DMA_RCHAN_STAT_02 0x00000c48 +#define BNX2_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) +#define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) +#define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) +#define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) + +#define BNX2_DMA_RCHAN_STAT_10 0x00000c4c +#define BNX2_DMA_RCHAN_STAT_11 0x00000c50 +#define BNX2_DMA_RCHAN_STAT_12 0x00000c54 +#define BNX2_DMA_RCHAN_STAT_20 0x00000c58 +#define BNX2_DMA_RCHAN_STAT_21 0x00000c5c +#define BNX2_DMA_RCHAN_STAT_22 0x00000c60 +#define BNX2_DMA_RCHAN_STAT_30 0x00000c64 +#define BNX2_DMA_RCHAN_STAT_31 0x00000c68 +#define BNX2_DMA_RCHAN_STAT_32 0x00000c6c +#define BNX2_DMA_RCHAN_STAT_40 0x00000c70 +#define BNX2_DMA_RCHAN_STAT_41 0x00000c74 +#define BNX2_DMA_RCHAN_STAT_42 0x00000c78 +#define BNX2_DMA_RCHAN_STAT_50 0x00000c7c +#define BNX2_DMA_RCHAN_STAT_51 0x00000c80 +#define BNX2_DMA_RCHAN_STAT_52 0x00000c84 +#define BNX2_DMA_RCHAN_STAT_60 0x00000c88 +#define BNX2_DMA_RCHAN_STAT_61 0x00000c8c +#define BNX2_DMA_RCHAN_STAT_62 0x00000c90 +#define BNX2_DMA_RCHAN_STAT_70 0x00000c94 +#define BNX2_DMA_RCHAN_STAT_71 0x00000c98 +#define BNX2_DMA_RCHAN_STAT_72 0x00000c9c +#define BNX2_DMA_WCHAN_STAT_00 0x00000ca0 +#define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) + +#define BNX2_DMA_WCHAN_STAT_01 0x00000ca4 +#define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) + +#define BNX2_DMA_WCHAN_STAT_02 0x00000ca8 +#define BNX2_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0) +#define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16) +#define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17) +#define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18) + +#define BNX2_DMA_WCHAN_STAT_10 0x00000cac +#define BNX2_DMA_WCHAN_STAT_11 0x00000cb0 +#define BNX2_DMA_WCHAN_STAT_12 0x00000cb4 +#define BNX2_DMA_WCHAN_STAT_20 0x00000cb8 +#define BNX2_DMA_WCHAN_STAT_21 0x00000cbc +#define BNX2_DMA_WCHAN_STAT_22 0x00000cc0 +#define BNX2_DMA_WCHAN_STAT_30 0x00000cc4 +#define BNX2_DMA_WCHAN_STAT_31 0x00000cc8 +#define BNX2_DMA_WCHAN_STAT_32 0x00000ccc +#define BNX2_DMA_WCHAN_STAT_40 0x00000cd0 +#define BNX2_DMA_WCHAN_STAT_41 0x00000cd4 +#define BNX2_DMA_WCHAN_STAT_42 0x00000cd8 +#define BNX2_DMA_WCHAN_STAT_50 0x00000cdc +#define BNX2_DMA_WCHAN_STAT_51 0x00000ce0 +#define BNX2_DMA_WCHAN_STAT_52 0x00000ce4 +#define BNX2_DMA_WCHAN_STAT_60 0x00000ce8 +#define BNX2_DMA_WCHAN_STAT_61 0x00000cec +#define BNX2_DMA_WCHAN_STAT_62 0x00000cf0 +#define BNX2_DMA_WCHAN_STAT_70 0x00000cf4 +#define BNX2_DMA_WCHAN_STAT_71 0x00000cf8 +#define BNX2_DMA_WCHAN_STAT_72 0x00000cfc +#define BNX2_DMA_ARB_STAT_00 0x00000d00 +#define BNX2_DMA_ARB_STAT_00_MASTER (0xffffL<<0) +#define BNX2_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16) +#define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24) + +#define BNX2_DMA_ARB_STAT_01 0x00000d04 +#define BNX2_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0) +#define BNX2_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4) +#define BNX2_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8) +#define BNX2_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12) +#define BNX2_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16) +#define BNX2_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20) +#define BNX2_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24) +#define BNX2_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28) + +#define BNX2_DMA_FUSE_CTRL0_CMD 0x00000f00 +#define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0) +#define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1) +#define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2) +#define BNX2_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3) +#define BNX2_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8) + +#define BNX2_DMA_FUSE_CTRL0_DATA 0x00000f04 +#define BNX2_DMA_FUSE_CTRL1_CMD 0x00000f08 +#define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0) +#define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1) +#define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2) +#define BNX2_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3) +#define BNX2_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8) + +#define BNX2_DMA_FUSE_CTRL1_DATA 0x00000f0c +#define BNX2_DMA_FUSE_CTRL2_CMD 0x00000f10 +#define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0) +#define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1) +#define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2) +#define BNX2_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3) +#define BNX2_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8) + +#define BNX2_DMA_FUSE_CTRL2_DATA 0x00000f14 + + +/* + * context_reg definition + * offset: 0x1000 + */ +#define BNX2_CTX_COMMAND 0x00001000 +#define BNX2_CTX_COMMAND_ENABLED (1L<<0) + +#define BNX2_CTX_STATUS 0x00001004 +#define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0) +#define BNX2_CTX_STATUS_READ_STAT (1L<<16) +#define BNX2_CTX_STATUS_WRITE_STAT (1L<<17) +#define BNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18) +#define BNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19) + +#define BNX2_CTX_VIRT_ADDR 0x00001008 +#define BNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) + +#define BNX2_CTX_PAGE_TBL 0x0000100c +#define BNX2_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6) + +#define BNX2_CTX_DATA_ADR 0x00001010 +#define BNX2_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2) + +#define BNX2_CTX_DATA 0x00001014 +#define BNX2_CTX_LOCK 0x00001018 +#define BNX2_CTX_LOCK_TYPE (0x7L<<0) +#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) +#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) +#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) +#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) +#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) +#define BNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7) +#define BNX2_CTX_LOCK_GRANTED (1L<<26) +#define BNX2_CTX_LOCK_MODE (0x7L<<27) +#define BNX2_CTX_LOCK_MODE_UNLOCK (0x0L<<27) +#define BNX2_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) +#define BNX2_CTX_LOCK_MODE_SURE (0x2L<<27) +#define BNX2_CTX_LOCK_STATUS (1L<<30) +#define BNX2_CTX_LOCK_REQ (1L<<31) + +#define BNX2_CTX_ACCESS_STATUS 0x00001040 +#define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) +#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) +#define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) +#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) +#define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) + +#define BNX2_CTX_DBG_LOCK_STATUS 0x00001044 +#define BNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) +#define BNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) + +#define BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080 +#define BNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) +#define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) +#define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) + +#define BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084 +#define BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088 +#define BNX2_CTX_CHNL_LOCK_STATUS_3 0x0000108c +#define BNX2_CTX_CHNL_LOCK_STATUS_4 0x00001090 +#define BNX2_CTX_CHNL_LOCK_STATUS_5 0x00001094 +#define BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098 +#define BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c +#define BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0 + + +/* + * emac_reg definition + * offset: 0x1400 + */ +#define BNX2_EMAC_MODE 0x00001400 +#define BNX2_EMAC_MODE_RESET (1L<<0) +#define BNX2_EMAC_MODE_HALF_DUPLEX (1L<<1) +#define BNX2_EMAC_MODE_PORT (0x3L<<2) +#define BNX2_EMAC_MODE_PORT_NONE (0L<<2) +#define BNX2_EMAC_MODE_PORT_MII (1L<<2) +#define BNX2_EMAC_MODE_PORT_GMII (2L<<2) +#define BNX2_EMAC_MODE_PORT_MII_10 (3L<<2) +#define BNX2_EMAC_MODE_MAC_LOOP (1L<<4) +#define BNX2_EMAC_MODE_25G (1L<<5) +#define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) +#define BNX2_EMAC_MODE_TX_BURST (1L<<8) +#define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) +#define BNX2_EMAC_MODE_EXT_LINK_POL (1L<<10) +#define BNX2_EMAC_MODE_FORCE_LINK (1L<<11) +#define BNX2_EMAC_MODE_MPKT (1L<<18) +#define BNX2_EMAC_MODE_MPKT_RCVD (1L<<19) +#define BNX2_EMAC_MODE_ACPI_RCVD (1L<<20) + +#define BNX2_EMAC_STATUS 0x00001404 +#define BNX2_EMAC_STATUS_LINK (1L<<11) +#define BNX2_EMAC_STATUS_LINK_CHANGE (1L<<12) +#define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22) +#define BNX2_EMAC_STATUS_MI_INT (1L<<23) +#define BNX2_EMAC_STATUS_AP_ERROR (1L<<24) +#define BNX2_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) + +#define BNX2_EMAC_ATTENTION_ENA 0x00001408 +#define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11) +#define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) +#define BNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23) +#define BNX2_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) + +#define BNX2_EMAC_LED 0x0000140c +#define BNX2_EMAC_LED_OVERRIDE (1L<<0) +#define BNX2_EMAC_LED_1000MB_OVERRIDE (1L<<1) +#define BNX2_EMAC_LED_100MB_OVERRIDE (1L<<2) +#define BNX2_EMAC_LED_10MB_OVERRIDE (1L<<3) +#define BNX2_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) +#define BNX2_EMAC_LED_BLNK_TRAFFIC (1L<<5) +#define BNX2_EMAC_LED_TRAFFIC (1L<<6) +#define BNX2_EMAC_LED_1000MB (1L<<7) +#define BNX2_EMAC_LED_100MB (1L<<8) +#define BNX2_EMAC_LED_10MB (1L<<9) +#define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10) +#define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19) +#define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31) + +#define BNX2_EMAC_MAC_MATCH0 0x00001410 +#define BNX2_EMAC_MAC_MATCH1 0x00001414 +#define BNX2_EMAC_MAC_MATCH2 0x00001418 +#define BNX2_EMAC_MAC_MATCH3 0x0000141c +#define BNX2_EMAC_MAC_MATCH4 0x00001420 +#define BNX2_EMAC_MAC_MATCH5 0x00001424 +#define BNX2_EMAC_MAC_MATCH6 0x00001428 +#define BNX2_EMAC_MAC_MATCH7 0x0000142c +#define BNX2_EMAC_MAC_MATCH8 0x00001430 +#define BNX2_EMAC_MAC_MATCH9 0x00001434 +#define BNX2_EMAC_MAC_MATCH10 0x00001438 +#define BNX2_EMAC_MAC_MATCH11 0x0000143c +#define BNX2_EMAC_MAC_MATCH12 0x00001440 +#define BNX2_EMAC_MAC_MATCH13 0x00001444 +#define BNX2_EMAC_MAC_MATCH14 0x00001448 +#define BNX2_EMAC_MAC_MATCH15 0x0000144c +#define BNX2_EMAC_MAC_MATCH16 0x00001450 +#define BNX2_EMAC_MAC_MATCH17 0x00001454 +#define BNX2_EMAC_MAC_MATCH18 0x00001458 +#define BNX2_EMAC_MAC_MATCH19 0x0000145c +#define BNX2_EMAC_MAC_MATCH20 0x00001460 +#define BNX2_EMAC_MAC_MATCH21 0x00001464 +#define BNX2_EMAC_MAC_MATCH22 0x00001468 +#define BNX2_EMAC_MAC_MATCH23 0x0000146c +#define BNX2_EMAC_MAC_MATCH24 0x00001470 +#define BNX2_EMAC_MAC_MATCH25 0x00001474 +#define BNX2_EMAC_MAC_MATCH26 0x00001478 +#define BNX2_EMAC_MAC_MATCH27 0x0000147c +#define BNX2_EMAC_MAC_MATCH28 0x00001480 +#define BNX2_EMAC_MAC_MATCH29 0x00001484 +#define BNX2_EMAC_MAC_MATCH30 0x00001488 +#define BNX2_EMAC_MAC_MATCH31 0x0000148c +#define BNX2_EMAC_BACKOFF_SEED 0x00001498 +#define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0) + +#define BNX2_EMAC_RX_MTU_SIZE 0x0000149c +#define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) +#define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) + +#define BNX2_EMAC_SERDES_CNTL 0x000014a4 +#define BNX2_EMAC_SERDES_CNTL_RXR (0x7L<<0) +#define BNX2_EMAC_SERDES_CNTL_RXG (0x3L<<3) +#define BNX2_EMAC_SERDES_CNTL_RXCKSEL (1L<<6) +#define BNX2_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7) +#define BNX2_EMAC_SERDES_CNTL_BGMAX (1L<<10) +#define BNX2_EMAC_SERDES_CNTL_BGMIN (1L<<11) +#define BNX2_EMAC_SERDES_CNTL_TXMODE (1L<<12) +#define BNX2_EMAC_SERDES_CNTL_TXEDGE (1L<<13) +#define BNX2_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14) +#define BNX2_EMAC_SERDES_CNTL_PLLTEST (1L<<15) +#define BNX2_EMAC_SERDES_CNTL_CDET_EN (1L<<16) +#define BNX2_EMAC_SERDES_CNTL_TBI_LBK (1L<<17) +#define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18) +#define BNX2_EMAC_SERDES_CNTL_REV_PHASE (1L<<19) +#define BNX2_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20) +#define BNX2_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22) + +#define BNX2_EMAC_SERDES_STATUS 0x000014a8 +#define BNX2_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0) +#define BNX2_EMAC_SERDES_STATUS_COMMA_DET (1L<<8) + +#define BNX2_EMAC_MDIO_COMM 0x000014ac +#define BNX2_EMAC_MDIO_COMM_DATA (0xffffL<<0) +#define BNX2_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) +#define BNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) +#define BNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26) +#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) +#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) +#define BNX2_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) +#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) +#define BNX2_EMAC_MDIO_COMM_FAIL (1L<<28) +#define BNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29) +#define BNX2_EMAC_MDIO_COMM_DISEXT (1L<<30) + +#define BNX2_EMAC_MDIO_STATUS 0x000014b0 +#define BNX2_EMAC_MDIO_STATUS_LINK (1L<<0) +#define BNX2_EMAC_MDIO_STATUS_10MB (1L<<1) + +#define BNX2_EMAC_MDIO_MODE 0x000014b4 +#define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1) +#define BNX2_EMAC_MDIO_MODE_AUTO_POLL (1L<<4) +#define BNX2_EMAC_MDIO_MODE_BIT_BANG (1L<<8) +#define BNX2_EMAC_MDIO_MODE_MDIO (1L<<9) +#define BNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10) +#define BNX2_EMAC_MDIO_MODE_MDC (1L<<11) +#define BNX2_EMAC_MDIO_MODE_MDINT (1L<<12) +#define BNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) + +#define BNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8 +#define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) + +#define BNX2_EMAC_TX_MODE 0x000014bc +#define BNX2_EMAC_TX_MODE_RESET (1L<<0) +#define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) +#define BNX2_EMAC_TX_MODE_FLOW_EN (1L<<4) +#define BNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) +#define BNX2_EMAC_TX_MODE_LONG_PAUSE (1L<<6) +#define BNX2_EMAC_TX_MODE_LINK_AWARE (1L<<7) + +#define BNX2_EMAC_TX_STATUS 0x000014c0 +#define BNX2_EMAC_TX_STATUS_XOFFED (1L<<0) +#define BNX2_EMAC_TX_STATUS_XOFF_SENT (1L<<1) +#define BNX2_EMAC_TX_STATUS_XON_SENT (1L<<2) +#define BNX2_EMAC_TX_STATUS_LINK_UP (1L<<3) +#define BNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4) + +#define BNX2_EMAC_TX_LENGTHS 0x000014c4 +#define BNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0) +#define BNX2_EMAC_TX_LENGTHS_IPG (0xfL<<8) +#define BNX2_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12) + +#define BNX2_EMAC_RX_MODE 0x000014c8 +#define BNX2_EMAC_RX_MODE_RESET (1L<<0) +#define BNX2_EMAC_RX_MODE_FLOW_EN (1L<<2) +#define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) +#define BNX2_EMAC_RX_MODE_KEEP_PAUSE (1L<<4) +#define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5) +#define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6) +#define BNX2_EMAC_RX_MODE_LLC_CHK (1L<<7) +#define BNX2_EMAC_RX_MODE_PROMISCUOUS (1L<<8) +#define BNX2_EMAC_RX_MODE_NO_CRC_CHK (1L<<9) +#define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) +#define BNX2_EMAC_RX_MODE_FILT_BROADCAST (1L<<11) +#define BNX2_EMAC_RX_MODE_SORT_MODE (1L<<12) + +#define BNX2_EMAC_RX_STATUS 0x000014cc +#define BNX2_EMAC_RX_STATUS_FFED (1L<<0) +#define BNX2_EMAC_RX_STATUS_FF_RECEIVED (1L<<1) +#define BNX2_EMAC_RX_STATUS_N_RECEIVED (1L<<2) + +#define BNX2_EMAC_MULTICAST_HASH0 0x000014d0 +#define BNX2_EMAC_MULTICAST_HASH1 0x000014d4 +#define BNX2_EMAC_MULTICAST_HASH2 0x000014d8 +#define BNX2_EMAC_MULTICAST_HASH3 0x000014dc +#define BNX2_EMAC_MULTICAST_HASH4 0x000014e0 +#define BNX2_EMAC_MULTICAST_HASH5 0x000014e4 +#define BNX2_EMAC_MULTICAST_HASH6 0x000014e8 +#define BNX2_EMAC_MULTICAST_HASH7 0x000014ec +#define BNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 +#define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 +#define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 +#define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c +#define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510 +#define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514 +#define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518 +#define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c +#define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520 +#define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524 +#define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528 +#define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c +#define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530 +#define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534 +#define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538 +#define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c +#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540 +#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544 +#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548 +#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c +#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 +#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 +#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 +#define BNX2_EMAC_RXMAC_DEBUG0 0x0000155c +#define BNX2_EMAC_RXMAC_DEBUG1 0x00001560 +#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) +#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1) +#define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2) +#define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3) +#define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4) +#define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5) +#define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6) +#define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7) +#define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23) + +#define BNX2_EMAC_RXMAC_DEBUG2 0x00001564 +#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) +#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0) +#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0) +#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0) +#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0) +#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0) +#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0) +#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0) +#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0) +#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3) +#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3) +#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3) +#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3) +#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3) +#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3) +#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3) +#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3) +#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3) +#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3) +#define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7) +#define BNX2_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15) +#define BNX2_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16) +#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18) +#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18) +#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18) +#define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19) +#define BNX2_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23) + +#define BNX2_EMAC_RXMAC_DEBUG3 0x00001568 +#define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0) +#define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16) + +#define BNX2_EMAC_RXMAC_DEBUG4 0x0000156c +#define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16) +#define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22) +#define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) +#define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) +#define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) +#define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) +#define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) +#define BNX2_EMAC_RXMAC_DEBUG4_START (1L<<28) + +#define BNX2_EMAC_RXMAC_DEBUG5 0x00001570 +#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0) +#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0) +#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0) +#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0) +#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0) +#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0) +#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0) +#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0) +#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4) +#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4) +#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4) +#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4) +#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4) +#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4) +#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4) +#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4) +#define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7) +#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8) +#define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11) +#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12) +#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13) +#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14) +#define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15) +#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16) +#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) +#define BNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) + +#define BNX2_EMAC_RX_STAT_AC0 0x00001580 +#define BNX2_EMAC_RX_STAT_AC1 0x00001584 +#define BNX2_EMAC_RX_STAT_AC2 0x00001588 +#define BNX2_EMAC_RX_STAT_AC3 0x0000158c +#define BNX2_EMAC_RX_STAT_AC4 0x00001590 +#define BNX2_EMAC_RX_STAT_AC5 0x00001594 +#define BNX2_EMAC_RX_STAT_AC6 0x00001598 +#define BNX2_EMAC_RX_STAT_AC7 0x0000159c +#define BNX2_EMAC_RX_STAT_AC8 0x000015a0 +#define BNX2_EMAC_RX_STAT_AC9 0x000015a4 +#define BNX2_EMAC_RX_STAT_AC10 0x000015a8 +#define BNX2_EMAC_RX_STAT_AC11 0x000015ac +#define BNX2_EMAC_RX_STAT_AC12 0x000015b0 +#define BNX2_EMAC_RX_STAT_AC13 0x000015b4 +#define BNX2_EMAC_RX_STAT_AC14 0x000015b8 +#define BNX2_EMAC_RX_STAT_AC15 0x000015bc +#define BNX2_EMAC_RX_STAT_AC16 0x000015c0 +#define BNX2_EMAC_RX_STAT_AC17 0x000015c4 +#define BNX2_EMAC_RX_STAT_AC18 0x000015c8 +#define BNX2_EMAC_RX_STAT_AC19 0x000015cc +#define BNX2_EMAC_RX_STAT_AC20 0x000015d0 +#define BNX2_EMAC_RX_STAT_AC21 0x000015d4 +#define BNX2_EMAC_RX_STAT_AC22 0x000015d8 +#define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc +#define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 +#define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 +#define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 +#define BNX2_EMAC_TX_STAT_OUTXONSENT 0x0000160c +#define BNX2_EMAC_TX_STAT_OUTXOFFSENT 0x00001610 +#define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614 +#define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618 +#define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c +#define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620 +#define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624 +#define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628 +#define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c +#define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630 +#define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634 +#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638 +#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c +#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640 +#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 +#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 +#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c +#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650 +#define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 +#define BNX2_EMAC_TXMAC_DEBUG0 0x00001658 +#define BNX2_EMAC_TXMAC_DEBUG1 0x0000165c +#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0) +#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0) +#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0) +#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0) +#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0) +#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0) +#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0) +#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0) +#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0) +#define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4) +#define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5) +#define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6) +#define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10) +#define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11) +#define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12) +#define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13) +#define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14) +#define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15) +#define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19) + +#define BNX2_EMAC_TXMAC_DEBUG2 0x00001660 +#define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0) +#define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10) +#define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26) +#define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31) + +#define BNX2_EMAC_TXMAC_DEBUG3 0x00001664 +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0) +#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4) +#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4) +#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4) +#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4) +#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4) +#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4) +#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4) +#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4) +#define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7) +#define BNX2_EMAC_TXMAC_DEBUG3_XOFF (1L<<8) +#define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9) +#define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13) + +#define BNX2_EMAC_TXMAC_DEBUG4 0x00001668 +#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0) +#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16) +#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) +#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) +#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) +#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) +#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) +#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16) +#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16) +#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16) +#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16) +#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16) +#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) +#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) +#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) +#define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) +#define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) +#define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) +#define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23) +#define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24) +#define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25) +#define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26) +#define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27) +#define BNX2_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28) +#define BNX2_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29) +#define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30) +#define BNX2_EMAC_TXMAC_DEBUG4_GO (1L<<31) + +#define BNX2_EMAC_TX_STAT_AC0 0x00001680 +#define BNX2_EMAC_TX_STAT_AC1 0x00001684 +#define BNX2_EMAC_TX_STAT_AC2 0x00001688 +#define BNX2_EMAC_TX_STAT_AC3 0x0000168c +#define BNX2_EMAC_TX_STAT_AC4 0x00001690 +#define BNX2_EMAC_TX_STAT_AC5 0x00001694 +#define BNX2_EMAC_TX_STAT_AC6 0x00001698 +#define BNX2_EMAC_TX_STAT_AC7 0x0000169c +#define BNX2_EMAC_TX_STAT_AC8 0x000016a0 +#define BNX2_EMAC_TX_STAT_AC9 0x000016a4 +#define BNX2_EMAC_TX_STAT_AC10 0x000016a8 +#define BNX2_EMAC_TX_STAT_AC11 0x000016ac +#define BNX2_EMAC_TX_STAT_AC12 0x000016b0 +#define BNX2_EMAC_TX_STAT_AC13 0x000016b4 +#define BNX2_EMAC_TX_STAT_AC14 0x000016b8 +#define BNX2_EMAC_TX_STAT_AC15 0x000016bc +#define BNX2_EMAC_TX_STAT_AC16 0x000016c0 +#define BNX2_EMAC_TX_STAT_AC17 0x000016c4 +#define BNX2_EMAC_TX_STAT_AC18 0x000016c8 +#define BNX2_EMAC_TX_STAT_AC19 0x000016cc +#define BNX2_EMAC_TX_STAT_AC20 0x000016d0 +#define BNX2_EMAC_TX_STAT_AC21 0x000016d4 +#define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 + + +/* + * rpm_reg definition + * offset: 0x1800 + */ +#define BNX2_RPM_COMMAND 0x00001800 +#define BNX2_RPM_COMMAND_ENABLED (1L<<0) +#define BNX2_RPM_COMMAND_OVERRUN_ABORT (1L<<4) + +#define BNX2_RPM_STATUS 0x00001804 +#define BNX2_RPM_STATUS_MBUF_WAIT (1L<<0) +#define BNX2_RPM_STATUS_FREE_WAIT (1L<<1) + +#define BNX2_RPM_CONFIG 0x00001808 +#define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0) +#define BNX2_RPM_CONFIG_ACPI_ENA (1L<<1) +#define BNX2_RPM_CONFIG_ACPI_KEEP (1L<<2) +#define BNX2_RPM_CONFIG_MP_KEEP (1L<<3) +#define BNX2_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) +#define BNX2_RPM_CONFIG_IGNORE_VLAN (1L<<31) + +#define BNX2_RPM_VLAN_MATCH0 0x00001810 +#define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0) + +#define BNX2_RPM_VLAN_MATCH1 0x00001814 +#define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0) + +#define BNX2_RPM_VLAN_MATCH2 0x00001818 +#define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0) + +#define BNX2_RPM_VLAN_MATCH3 0x0000181c +#define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0) + +#define BNX2_RPM_SORT_USER0 0x00001820 +#define BNX2_RPM_SORT_USER0_PM_EN (0xffffL<<0) +#define BNX2_RPM_SORT_USER0_BC_EN (1L<<16) +#define BNX2_RPM_SORT_USER0_MC_EN (1L<<17) +#define BNX2_RPM_SORT_USER0_MC_HSH_EN (1L<<18) +#define BNX2_RPM_SORT_USER0_PROM_EN (1L<<19) +#define BNX2_RPM_SORT_USER0_VLAN_EN (0xfL<<20) +#define BNX2_RPM_SORT_USER0_PROM_VLAN (1L<<24) +#define BNX2_RPM_SORT_USER0_ENA (1L<<31) + +#define BNX2_RPM_SORT_USER1 0x00001824 +#define BNX2_RPM_SORT_USER1_PM_EN (0xffffL<<0) +#define BNX2_RPM_SORT_USER1_BC_EN (1L<<16) +#define BNX2_RPM_SORT_USER1_MC_EN (1L<<17) +#define BNX2_RPM_SORT_USER1_MC_HSH_EN (1L<<18) +#define BNX2_RPM_SORT_USER1_PROM_EN (1L<<19) +#define BNX2_RPM_SORT_USER1_VLAN_EN (0xfL<<20) +#define BNX2_RPM_SORT_USER1_PROM_VLAN (1L<<24) +#define BNX2_RPM_SORT_USER1_ENA (1L<<31) + +#define BNX2_RPM_SORT_USER2 0x00001828 +#define BNX2_RPM_SORT_USER2_PM_EN (0xffffL<<0) +#define BNX2_RPM_SORT_USER2_BC_EN (1L<<16) +#define BNX2_RPM_SORT_USER2_MC_EN (1L<<17) +#define BNX2_RPM_SORT_USER2_MC_HSH_EN (1L<<18) +#define BNX2_RPM_SORT_USER2_PROM_EN (1L<<19) +#define BNX2_RPM_SORT_USER2_VLAN_EN (0xfL<<20) +#define BNX2_RPM_SORT_USER2_PROM_VLAN (1L<<24) +#define BNX2_RPM_SORT_USER2_ENA (1L<<31) + +#define BNX2_RPM_SORT_USER3 0x0000182c +#define BNX2_RPM_SORT_USER3_PM_EN (0xffffL<<0) +#define BNX2_RPM_SORT_USER3_BC_EN (1L<<16) +#define BNX2_RPM_SORT_USER3_MC_EN (1L<<17) +#define BNX2_RPM_SORT_USER3_MC_HSH_EN (1L<<18) +#define BNX2_RPM_SORT_USER3_PROM_EN (1L<<19) +#define BNX2_RPM_SORT_USER3_VLAN_EN (0xfL<<20) +#define BNX2_RPM_SORT_USER3_PROM_VLAN (1L<<24) +#define BNX2_RPM_SORT_USER3_ENA (1L<<31) + +#define BNX2_RPM_STAT_L2_FILTER_DISCARDS 0x00001840 +#define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844 +#define BNX2_RPM_STAT_IFINFTQDISCARDS 0x00001848 +#define BNX2_RPM_STAT_IFINMBUFDISCARD 0x0000184c +#define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850 +#define BNX2_RPM_STAT_AC0 0x00001880 +#define BNX2_RPM_STAT_AC1 0x00001884 +#define BNX2_RPM_STAT_AC2 0x00001888 +#define BNX2_RPM_STAT_AC3 0x0000188c +#define BNX2_RPM_STAT_AC4 0x00001890 +#define BNX2_RPM_RC_CNTL_0 0x00001900 +#define BNX2_RPM_RC_CNTL_0_OFFSET (0xffL<<0) +#define BNX2_RPM_RC_CNTL_0_CLASS (0x7L<<8) +#define BNX2_RPM_RC_CNTL_0_PRIORITY (1L<<11) +#define BNX2_RPM_RC_CNTL_0_P4 (1L<<12) +#define BNX2_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13) +#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13) +#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13) +#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13) +#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13) +#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13) +#define BNX2_RPM_RC_CNTL_0_COMP (0x3L<<16) +#define BNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16) +#define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16) +#define BNX2_RPM_RC_CNTL_0_COMP_GREATER (2L<<16) +#define BNX2_RPM_RC_CNTL_0_COMP_LESS (3L<<16) +#define BNX2_RPM_RC_CNTL_0_SBIT (1L<<19) +#define BNX2_RPM_RC_CNTL_0_CMDSEL (0xfL<<20) +#define BNX2_RPM_RC_CNTL_0_MAP (1L<<24) +#define BNX2_RPM_RC_CNTL_0_DISCARD (1L<<25) +#define BNX2_RPM_RC_CNTL_0_MASK (1L<<26) +#define BNX2_RPM_RC_CNTL_0_P1 (1L<<27) +#define BNX2_RPM_RC_CNTL_0_P2 (1L<<28) +#define BNX2_RPM_RC_CNTL_0_P3 (1L<<29) +#define BNX2_RPM_RC_CNTL_0_NBIT (1L<<30) + +#define BNX2_RPM_RC_VALUE_MASK_0 0x00001904 +#define BNX2_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0) +#define BNX2_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16) + +#define BNX2_RPM_RC_CNTL_1 0x00001908 +#define BNX2_RPM_RC_CNTL_1_A (0x3ffffL<<0) +#define BNX2_RPM_RC_CNTL_1_B (0xfffL<<19) + +#define BNX2_RPM_RC_VALUE_MASK_1 0x0000190c +#define BNX2_RPM_RC_CNTL_2 0x00001910 +#define BNX2_RPM_RC_CNTL_2_A (0x3ffffL<<0) +#define BNX2_RPM_RC_CNTL_2_B (0xfffL<<19) + +#define BNX2_RPM_RC_VALUE_MASK_2 0x00001914 +#define BNX2_RPM_RC_CNTL_3 0x00001918 +#define BNX2_RPM_RC_CNTL_3_A (0x3ffffL<<0) +#define BNX2_RPM_RC_CNTL_3_B (0xfffL<<19) + +#define BNX2_RPM_RC_VALUE_MASK_3 0x0000191c +#define BNX2_RPM_RC_CNTL_4 0x00001920 +#define BNX2_RPM_RC_CNTL_4_A (0x3ffffL<<0) +#define BNX2_RPM_RC_CNTL_4_B (0xfffL<<19) + +#define BNX2_RPM_RC_VALUE_MASK_4 0x00001924 +#define BNX2_RPM_RC_CNTL_5 0x00001928 +#define BNX2_RPM_RC_CNTL_5_A (0x3ffffL<<0) +#define BNX2_RPM_RC_CNTL_5_B (0xfffL<<19) + +#define BNX2_RPM_RC_VALUE_MASK_5 0x0000192c +#define BNX2_RPM_RC_CNTL_6 0x00001930 +#define BNX2_RPM_RC_CNTL_6_A (0x3ffffL<<0) +#define BNX2_RPM_RC_CNTL_6_B (0xfffL<<19) + +#define BNX2_RPM_RC_VALUE_MASK_6 0x00001934 +#define BNX2_RPM_RC_CNTL_7 0x00001938 +#define BNX2_RPM_RC_CNTL_7_A (0x3ffffL<<0) +#define BNX2_RPM_RC_CNTL_7_B (0xfffL<<19) + +#define BNX2_RPM_RC_VALUE_MASK_7 0x0000193c +#define BNX2_RPM_RC_CNTL_8 0x00001940 +#define BNX2_RPM_RC_CNTL_8_A (0x3ffffL<<0) +#define BNX2_RPM_RC_CNTL_8_B (0xfffL<<19) + +#define BNX2_RPM_RC_VALUE_MASK_8 0x00001944 +#define BNX2_RPM_RC_CNTL_9 0x00001948 +#define BNX2_RPM_RC_CNTL_9_A (0x3ffffL<<0) +#define BNX2_RPM_RC_CNTL_9_B (0xfffL<<19) + +#define BNX2_RPM_RC_VALUE_MASK_9 0x0000194c +#define BNX2_RPM_RC_CNTL_10 0x00001950 +#define BNX2_RPM_RC_CNTL_10_A (0x3ffffL<<0) +#define BNX2_RPM_RC_CNTL_10_B (0xfffL<<19) + +#define BNX2_RPM_RC_VALUE_MASK_10 0x00001954 +#define BNX2_RPM_RC_CNTL_11 0x00001958 +#define BNX2_RPM_RC_CNTL_11_A (0x3ffffL<<0) +#define BNX2_RPM_RC_CNTL_11_B (0xfffL<<19) + +#define BNX2_RPM_RC_VALUE_MASK_11 0x0000195c +#define BNX2_RPM_RC_CNTL_12 0x00001960 +#define BNX2_RPM_RC_CNTL_12_A (0x3ffffL<<0) +#define BNX2_RPM_RC_CNTL_12_B (0xfffL<<19) + +#define BNX2_RPM_RC_VALUE_MASK_12 0x00001964 +#define BNX2_RPM_RC_CNTL_13 0x00001968 +#define BNX2_RPM_RC_CNTL_13_A (0x3ffffL<<0) +#define BNX2_RPM_RC_CNTL_13_B (0xfffL<<19) + +#define BNX2_RPM_RC_VALUE_MASK_13 0x0000196c +#define BNX2_RPM_RC_CNTL_14 0x00001970 +#define BNX2_RPM_RC_CNTL_14_A (0x3ffffL<<0) +#define BNX2_RPM_RC_CNTL_14_B (0xfffL<<19) + +#define BNX2_RPM_RC_VALUE_MASK_14 0x00001974 +#define BNX2_RPM_RC_CNTL_15 0x00001978 +#define BNX2_RPM_RC_CNTL_15_A (0x3ffffL<<0) +#define BNX2_RPM_RC_CNTL_15_B (0xfffL<<19) + +#define BNX2_RPM_RC_VALUE_MASK_15 0x0000197c +#define BNX2_RPM_RC_CONFIG 0x00001980 +#define BNX2_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0) +#define BNX2_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24) + +#define BNX2_RPM_DEBUG0 0x00001984 +#define BNX2_RPM_DEBUG0_FM_BCNT (0xffffL<<0) +#define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16) +#define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17) +#define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18) +#define BNX2_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19) +#define BNX2_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20) +#define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21) +#define BNX2_RPM_DEBUG0_LLC_SNAP (1L<<22) +#define BNX2_RPM_DEBUG0_FM_STARTED (1L<<23) +#define BNX2_RPM_DEBUG0_DONE (1L<<24) +#define BNX2_RPM_DEBUG0_WAIT_4_DONE (1L<<25) +#define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26) +#define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27) +#define BNX2_RPM_DEBUG0_IGNORE_VLAN (1L<<28) +#define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31) + +#define BNX2_RPM_DEBUG1 0x00001988 +#define BNX2_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0) +#define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0) +#define BNX2_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16) +#define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28) +#define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29) +#define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30) +#define BNX2_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31) + +#define BNX2_RPM_DEBUG2 0x0000198c +#define BNX2_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0) +#define BNX2_RPM_DEBUG2_IP_BCNT (0xffL<<16) +#define BNX2_RPM_DEBUG2_THIS_CMD_M4 (1L<<24) +#define BNX2_RPM_DEBUG2_THIS_CMD_M3 (1L<<25) +#define BNX2_RPM_DEBUG2_THIS_CMD_M2 (1L<<26) +#define BNX2_RPM_DEBUG2_THIS_CMD_M1 (1L<<27) +#define BNX2_RPM_DEBUG2_IPIPE_EMPTY (1L<<28) +#define BNX2_RPM_DEBUG2_FM_DISCARD (1L<<29) +#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30) +#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31) + +#define BNX2_RPM_DEBUG3 0x00001990 +#define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0) +#define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9) +#define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10) +#define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11) +#define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12) +#define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13) +#define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14) +#define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15) +#define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16) +#define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21) +#define BNX2_RPM_DEBUG3_DROP_NXT_VLD (1L<<22) +#define BNX2_RPM_DEBUG3_DROP_NXT (1L<<23) +#define BNX2_RPM_DEBUG3_FTQ_FSM (0x3L<<24) +#define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24) +#define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24) +#define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24) +#define BNX2_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26) +#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26) +#define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26) +#define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26) +#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26) +#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26) +#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26) +#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26) +#define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26) +#define BNX2_RPM_DEBUG3_MBFREE_FSM (1L<<29) +#define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29) +#define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29) +#define BNX2_RPM_DEBUG3_MBALLOC_FSM (1L<<30) +#define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30) +#define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30) +#define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31) + +#define BNX2_RPM_DEBUG4 0x00001994 +#define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0) +#define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25) +#define BNX2_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28) +#define BNX2_RPM_DEBUG4_DFIFO_EMPTY (1L<<31) + +#define BNX2_RPM_DEBUG5 0x00001998 +#define BNX2_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0) +#define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5) +#define BNX2_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10) +#define BNX2_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15) +#define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20) +#define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21) +#define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22) +#define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23) +#define BNX2_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24) +#define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25) +#define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26) +#define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27) +#define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28) +#define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29) +#define BNX2_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30) +#define BNX2_RPM_DEBUG5_HOLDREG_RD (1L<<31) + +#define BNX2_RPM_DEBUG6 0x0000199c +#define BNX2_RPM_DEBUG6_ACPI_VEC (0xffffL<<0) +#define BNX2_RPM_DEBUG6_VEC (0xffffL<<16) + +#define BNX2_RPM_DEBUG7 0x000019a0 +#define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0) + +#define BNX2_RPM_DEBUG8 0x000019a4 +#define BNX2_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0) +#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0) +#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0) +#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0) +#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0) +#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0) +#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0) +#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0) +#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0) +#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0) +#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0) +#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0) +#define BNX2_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4) +#define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5) +#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6) +#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7) +#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8) +#define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9) +#define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10) +#define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11) +#define BNX2_RPM_DEBUG8_EOF_DET (1L<<12) +#define BNX2_RPM_DEBUG8_SOF_DET (1L<<13) +#define BNX2_RPM_DEBUG8_WAIT_4_SOF (1L<<14) +#define BNX2_RPM_DEBUG8_ALL_DONE (1L<<15) +#define BNX2_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16) +#define BNX2_RPM_DEBUG8_BYTE_CTR (0xffL<<24) + +#define BNX2_RPM_DEBUG9 0x000019a8 +#define BNX2_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0) +#define BNX2_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3) +#define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4) +#define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28) +#define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29) +#define BNX2_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) +#define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) + +#define BNX2_RPM_ACPI_DBG_BUF_W00 0x000019c0 +#define BNX2_RPM_ACPI_DBG_BUF_W01 0x000019c4 +#define BNX2_RPM_ACPI_DBG_BUF_W02 0x000019c8 +#define BNX2_RPM_ACPI_DBG_BUF_W03 0x000019cc +#define BNX2_RPM_ACPI_DBG_BUF_W10 0x000019d0 +#define BNX2_RPM_ACPI_DBG_BUF_W11 0x000019d4 +#define BNX2_RPM_ACPI_DBG_BUF_W12 0x000019d8 +#define BNX2_RPM_ACPI_DBG_BUF_W13 0x000019dc +#define BNX2_RPM_ACPI_DBG_BUF_W20 0x000019e0 +#define BNX2_RPM_ACPI_DBG_BUF_W21 0x000019e4 +#define BNX2_RPM_ACPI_DBG_BUF_W22 0x000019e8 +#define BNX2_RPM_ACPI_DBG_BUF_W23 0x000019ec +#define BNX2_RPM_ACPI_DBG_BUF_W30 0x000019f0 +#define BNX2_RPM_ACPI_DBG_BUF_W31 0x000019f4 +#define BNX2_RPM_ACPI_DBG_BUF_W32 0x000019f8 +#define BNX2_RPM_ACPI_DBG_BUF_W33 0x000019fc + + +/* + * rbuf_reg definition + * offset: 0x200000 + */ +#define BNX2_RBUF_COMMAND 0x00200000 +#define BNX2_RBUF_COMMAND_ENABLED (1L<<0) +#define BNX2_RBUF_COMMAND_FREE_INIT (1L<<1) +#define BNX2_RBUF_COMMAND_RAM_INIT (1L<<2) +#define BNX2_RBUF_COMMAND_OVER_FREE (1L<<4) +#define BNX2_RBUF_COMMAND_ALLOC_REQ (1L<<5) + +#define BNX2_RBUF_STATUS1 0x00200004 +#define BNX2_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0) + +#define BNX2_RBUF_STATUS2 0x00200008 +#define BNX2_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0) +#define BNX2_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16) + +#define BNX2_RBUF_CONFIG 0x0020000c +#define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) +#define BNX2_RBUF_CONFIG_XON_TRIP (0x3ffL<<16) + +#define BNX2_RBUF_FW_BUF_ALLOC 0x00200010 +#define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) + +#define BNX2_RBUF_FW_BUF_FREE 0x00200014 +#define BNX2_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0) +#define BNX2_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7) +#define BNX2_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16) + +#define BNX2_RBUF_FW_BUF_SEL 0x00200018 +#define BNX2_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0) +#define BNX2_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7) +#define BNX2_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16) + +#define BNX2_RBUF_CONFIG2 0x0020001c +#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) +#define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16) + +#define BNX2_RBUF_CONFIG3 0x00200020 +#define BNX2_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0) +#define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16) + +#define BNX2_RBUF_PKT_DATA 0x00208000 +#define BNX2_RBUF_CLIST_DATA 0x00210000 +#define BNX2_RBUF_BUF_DATA 0x00220000 + + +/* + * rv2p_reg definition + * offset: 0x2800 + */ +#define BNX2_RV2P_COMMAND 0x00002800 +#define BNX2_RV2P_COMMAND_ENABLED (1L<<0) +#define BNX2_RV2P_COMMAND_PROC1_INTRPT (1L<<1) +#define BNX2_RV2P_COMMAND_PROC2_INTRPT (1L<<2) +#define BNX2_RV2P_COMMAND_ABORT0 (1L<<4) +#define BNX2_RV2P_COMMAND_ABORT1 (1L<<5) +#define BNX2_RV2P_COMMAND_ABORT2 (1L<<6) +#define BNX2_RV2P_COMMAND_ABORT3 (1L<<7) +#define BNX2_RV2P_COMMAND_ABORT4 (1L<<8) +#define BNX2_RV2P_COMMAND_ABORT5 (1L<<9) +#define BNX2_RV2P_COMMAND_PROC1_RESET (1L<<16) +#define BNX2_RV2P_COMMAND_PROC2_RESET (1L<<17) +#define BNX2_RV2P_COMMAND_CTXIF_RESET (1L<<18) + +#define BNX2_RV2P_STATUS 0x00002804 +#define BNX2_RV2P_STATUS_ALWAYS_0 (1L<<0) +#define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8) +#define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9) +#define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10) +#define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11) +#define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12) +#define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13) + +#define BNX2_RV2P_CONFIG 0x00002808 +#define BNX2_RV2P_CONFIG_STALL_PROC1 (1L<<0) +#define BNX2_RV2P_CONFIG_STALL_PROC2 (1L<<1) +#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8) +#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9) +#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10) +#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11) +#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12) +#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13) +#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16) +#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17) +#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18) +#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19) +#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20) +#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21) +#define BNX2_RV2P_CONFIG_PAGE_SIZE (0xfL<<24) +#define BNX2_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24) +#define BNX2_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24) +#define BNX2_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24) +#define BNX2_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24) +#define BNX2_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24) +#define BNX2_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24) +#define BNX2_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24) +#define BNX2_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24) +#define BNX2_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24) +#define BNX2_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24) +#define BNX2_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24) +#define BNX2_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24) +#define BNX2_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24) + +#define BNX2_RV2P_GEN_BFR_ADDR_0 0x00002810 +#define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16) + +#define BNX2_RV2P_GEN_BFR_ADDR_1 0x00002814 +#define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16) + +#define BNX2_RV2P_GEN_BFR_ADDR_2 0x00002818 +#define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16) + +#define BNX2_RV2P_GEN_BFR_ADDR_3 0x0000281c +#define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16) + +#define BNX2_RV2P_INSTR_HIGH 0x00002830 +#define BNX2_RV2P_INSTR_HIGH_HIGH (0x1fL<<0) + +#define BNX2_RV2P_INSTR_LOW 0x00002834 +#define BNX2_RV2P_PROC1_ADDR_CMD 0x00002838 +#define BNX2_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) +#define BNX2_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) + +#define BNX2_RV2P_PROC2_ADDR_CMD 0x0000283c +#define BNX2_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0) +#define BNX2_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31) + +#define BNX2_RV2P_PROC1_GRC_DEBUG 0x00002840 +#define BNX2_RV2P_PROC2_GRC_DEBUG 0x00002844 +#define BNX2_RV2P_GRC_PROC_DEBUG 0x00002848 +#define BNX2_RV2P_DEBUG_VECT_PEEK 0x0000284c +#define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX2_RV2P_PFTQ_DATA 0x00002b40 +#define BNX2_RV2P_PFTQ_CMD 0x00002b78 +#define BNX2_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX2_RV2P_PFTQ_CMD_WR_TOP (1L<<10) +#define BNX2_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX2_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX2_RV2P_PFTQ_CMD_SFT_RESET (1L<<25) +#define BNX2_RV2P_PFTQ_CMD_RD_DATA (1L<<26) +#define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX2_RV2P_PFTQ_CMD_ADD_DATA (1L<<28) +#define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX2_RV2P_PFTQ_CMD_POP (1L<<30) +#define BNX2_RV2P_PFTQ_CMD_BUSY (1L<<31) + +#define BNX2_RV2P_PFTQ_CTL 0x00002b7c +#define BNX2_RV2P_PFTQ_CTL_INTERVENE (1L<<0) +#define BNX2_RV2P_PFTQ_CTL_OVERFLOW (1L<<1) +#define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX2_RV2P_TFTQ_DATA 0x00002b80 +#define BNX2_RV2P_TFTQ_CMD 0x00002bb8 +#define BNX2_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX2_RV2P_TFTQ_CMD_WR_TOP (1L<<10) +#define BNX2_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX2_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX2_RV2P_TFTQ_CMD_SFT_RESET (1L<<25) +#define BNX2_RV2P_TFTQ_CMD_RD_DATA (1L<<26) +#define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX2_RV2P_TFTQ_CMD_ADD_DATA (1L<<28) +#define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX2_RV2P_TFTQ_CMD_POP (1L<<30) +#define BNX2_RV2P_TFTQ_CMD_BUSY (1L<<31) + +#define BNX2_RV2P_TFTQ_CTL 0x00002bbc +#define BNX2_RV2P_TFTQ_CTL_INTERVENE (1L<<0) +#define BNX2_RV2P_TFTQ_CTL_OVERFLOW (1L<<1) +#define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX2_RV2P_MFTQ_DATA 0x00002bc0 +#define BNX2_RV2P_MFTQ_CMD 0x00002bf8 +#define BNX2_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX2_RV2P_MFTQ_CMD_WR_TOP (1L<<10) +#define BNX2_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX2_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX2_RV2P_MFTQ_CMD_SFT_RESET (1L<<25) +#define BNX2_RV2P_MFTQ_CMD_RD_DATA (1L<<26) +#define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX2_RV2P_MFTQ_CMD_ADD_DATA (1L<<28) +#define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX2_RV2P_MFTQ_CMD_POP (1L<<30) +#define BNX2_RV2P_MFTQ_CMD_BUSY (1L<<31) + +#define BNX2_RV2P_MFTQ_CTL 0x00002bfc +#define BNX2_RV2P_MFTQ_CTL_INTERVENE (1L<<0) +#define BNX2_RV2P_MFTQ_CTL_OVERFLOW (1L<<1) +#define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22) + + + +/* + * mq_reg definition + * offset: 0x3c00 + */ +#define BNX2_MQ_COMMAND 0x00003c00 +#define BNX2_MQ_COMMAND_ENABLED (1L<<0) +#define BNX2_MQ_COMMAND_OVERFLOW (1L<<4) +#define BNX2_MQ_COMMAND_WR_ERROR (1L<<5) +#define BNX2_MQ_COMMAND_RD_ERROR (1L<<6) + +#define BNX2_MQ_STATUS 0x00003c04 +#define BNX2_MQ_STATUS_CTX_ACCESS_STAT (1L<<16) +#define BNX2_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17) +#define BNX2_MQ_STATUS_PCI_STALL_STAT (1L<<18) + +#define BNX2_MQ_CONFIG 0x00003c08 +#define BNX2_MQ_CONFIG_TX_HIGH_PRI (1L<<0) +#define BNX2_MQ_CONFIG_HALT_DIS (1L<<1) +#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4) +#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4) +#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4) +#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4) +#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4) +#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4) +#define BNX2_MQ_CONFIG_MAX_DEPTH (0x7fL<<8) +#define BNX2_MQ_CONFIG_CUR_DEPTH (0x7fL<<20) + +#define BNX2_MQ_ENQUEUE1 0x00003c0c +#define BNX2_MQ_ENQUEUE1_OFFSET (0x3fL<<2) +#define BNX2_MQ_ENQUEUE1_CID (0x3fffL<<8) +#define BNX2_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24) +#define BNX2_MQ_ENQUEUE1_KNL_MODE (1L<<28) + +#define BNX2_MQ_ENQUEUE2 0x00003c10 +#define BNX2_MQ_BAD_WR_ADDR 0x00003c14 +#define BNX2_MQ_BAD_RD_ADDR 0x00003c18 +#define BNX2_MQ_KNL_BYP_WIND_START 0x00003c1c +#define BNX2_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12) + +#define BNX2_MQ_KNL_WIND_END 0x00003c20 +#define BNX2_MQ_KNL_WIND_END_VALUE (0xffffffL<<8) + +#define BNX2_MQ_KNL_WRITE_MASK1 0x00003c24 +#define BNX2_MQ_KNL_TX_MASK1 0x00003c28 +#define BNX2_MQ_KNL_CMD_MASK1 0x00003c2c +#define BNX2_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30 +#define BNX2_MQ_KNL_RX_V2P_MASK1 0x00003c34 +#define BNX2_MQ_KNL_WRITE_MASK2 0x00003c38 +#define BNX2_MQ_KNL_TX_MASK2 0x00003c3c +#define BNX2_MQ_KNL_CMD_MASK2 0x00003c40 +#define BNX2_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44 +#define BNX2_MQ_KNL_RX_V2P_MASK2 0x00003c48 +#define BNX2_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c +#define BNX2_MQ_KNL_BYP_TX_MASK1 0x00003c50 +#define BNX2_MQ_KNL_BYP_CMD_MASK1 0x00003c54 +#define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58 +#define BNX2_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c +#define BNX2_MQ_KNL_BYP_WRITE_MASK2 0x00003c60 +#define BNX2_MQ_KNL_BYP_TX_MASK2 0x00003c64 +#define BNX2_MQ_KNL_BYP_CMD_MASK2 0x00003c68 +#define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c +#define BNX2_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70 +#define BNX2_MQ_MEM_WR_ADDR 0x00003c74 +#define BNX2_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0) + +#define BNX2_MQ_MEM_WR_DATA0 0x00003c78 +#define BNX2_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0) + +#define BNX2_MQ_MEM_WR_DATA1 0x00003c7c +#define BNX2_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0) + +#define BNX2_MQ_MEM_WR_DATA2 0x00003c80 +#define BNX2_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0) + +#define BNX2_MQ_MEM_RD_ADDR 0x00003c84 +#define BNX2_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0) + +#define BNX2_MQ_MEM_RD_DATA0 0x00003c88 +#define BNX2_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0) + +#define BNX2_MQ_MEM_RD_DATA1 0x00003c8c +#define BNX2_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0) + +#define BNX2_MQ_MEM_RD_DATA2 0x00003c90 +#define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) + + + +/* + * tbdr_reg definition + * offset: 0x5000 + */ +#define BNX2_TBDR_COMMAND 0x00005000 +#define BNX2_TBDR_COMMAND_ENABLE (1L<<0) +#define BNX2_TBDR_COMMAND_SOFT_RST (1L<<1) +#define BNX2_TBDR_COMMAND_MSTR_ABORT (1L<<4) + +#define BNX2_TBDR_STATUS 0x00005004 +#define BNX2_TBDR_STATUS_DMA_WAIT (1L<<0) +#define BNX2_TBDR_STATUS_FTQ_WAIT (1L<<1) +#define BNX2_TBDR_STATUS_FIFO_OVERFLOW (1L<<2) +#define BNX2_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3) +#define BNX2_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4) +#define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5) +#define BNX2_TBDR_STATUS_BURST_CNT (1L<<6) + +#define BNX2_TBDR_CONFIG 0x00005008 +#define BNX2_TBDR_CONFIG_MAX_BDS (0xffL<<0) +#define BNX2_TBDR_CONFIG_SWAP_MODE (1L<<8) +#define BNX2_TBDR_CONFIG_PRIORITY (1L<<9) +#define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10) +#define BNX2_TBDR_CONFIG_PAGE_SIZE (0xfL<<24) +#define BNX2_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24) +#define BNX2_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24) +#define BNX2_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24) +#define BNX2_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24) +#define BNX2_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24) +#define BNX2_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24) +#define BNX2_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24) +#define BNX2_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24) +#define BNX2_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24) +#define BNX2_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24) +#define BNX2_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24) +#define BNX2_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24) +#define BNX2_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24) + +#define BNX2_TBDR_DEBUG_VECT_PEEK 0x0000500c +#define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX2_TBDR_FTQ_DATA 0x000053c0 +#define BNX2_TBDR_FTQ_CMD 0x000053f8 +#define BNX2_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX2_TBDR_FTQ_CMD_WR_TOP (1L<<10) +#define BNX2_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX2_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX2_TBDR_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX2_TBDR_FTQ_CMD_RD_DATA (1L<<26) +#define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX2_TBDR_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX2_TBDR_FTQ_CMD_POP (1L<<30) +#define BNX2_TBDR_FTQ_CMD_BUSY (1L<<31) + +#define BNX2_TBDR_FTQ_CTL 0x000053fc +#define BNX2_TBDR_FTQ_CTL_INTERVENE (1L<<0) +#define BNX2_TBDR_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX2_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX2_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + + + +/* + * tdma_reg definition + * offset: 0x5c00 + */ +#define BNX2_TDMA_COMMAND 0x00005c00 +#define BNX2_TDMA_COMMAND_ENABLED (1L<<0) +#define BNX2_TDMA_COMMAND_MASTER_ABORT (1L<<4) +#define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7) + +#define BNX2_TDMA_STATUS 0x00005c04 +#define BNX2_TDMA_STATUS_DMA_WAIT (1L<<0) +#define BNX2_TDMA_STATUS_PAYLOAD_WAIT (1L<<1) +#define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2) +#define BNX2_TDMA_STATUS_LOCK_WAIT (1L<<3) +#define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16) +#define BNX2_TDMA_STATUS_BURST_CNT (1L<<17) + +#define BNX2_TDMA_CONFIG 0x00005c08 +#define BNX2_TDMA_CONFIG_ONE_DMA (1L<<0) +#define BNX2_TDMA_CONFIG_ONE_RECORD (1L<<1) +#define BNX2_TDMA_CONFIG_LIMIT_SZ (0xfL<<4) +#define BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4) +#define BNX2_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4) +#define BNX2_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4) +#define BNX2_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4) +#define BNX2_TDMA_CONFIG_LINE_SZ (0xfL<<8) +#define BNX2_TDMA_CONFIG_LINE_SZ_64 (0L<<8) +#define BNX2_TDMA_CONFIG_LINE_SZ_128 (4L<<8) +#define BNX2_TDMA_CONFIG_LINE_SZ_256 (6L<<8) +#define BNX2_TDMA_CONFIG_LINE_SZ_512 (8L<<8) +#define BNX2_TDMA_CONFIG_ALIGN_ENA (1L<<15) +#define BNX2_TDMA_CONFIG_CHK_L2_BD (1L<<16) +#define BNX2_TDMA_CONFIG_FIFO_CMP (0xfL<<20) + +#define BNX2_TDMA_PAYLOAD_PROD 0x00005c0c +#define BNX2_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3) + +#define BNX2_TDMA_DBG_WATCHDOG 0x00005c10 +#define BNX2_TDMA_DBG_TRIGGER 0x00005c14 +#define BNX2_TDMA_DMAD_FSM 0x00005c80 +#define BNX2_TDMA_DMAD_FSM_BD_INVLD (1L<<0) +#define BNX2_TDMA_DMAD_FSM_PUSH (0xfL<<4) +#define BNX2_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8) +#define BNX2_TDMA_DMAD_FSM_ARB_CTX (1L<<12) +#define BNX2_TDMA_DMAD_FSM_DR_INTF (1L<<16) +#define BNX2_TDMA_DMAD_FSM_DMAD (0x7L<<20) +#define BNX2_TDMA_DMAD_FSM_BD (0xfL<<24) + +#define BNX2_TDMA_DMAD_STATUS 0x00005c84 +#define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0) +#define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4) +#define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8) +#define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12) + +#define BNX2_TDMA_DR_INTF_FSM 0x00005c88 +#define BNX2_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0) +#define BNX2_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4) +#define BNX2_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8) +#define BNX2_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12) +#define BNX2_TDMA_DR_INTF_FSM_DMAD (0x7L<<16) + +#define BNX2_TDMA_DR_INTF_STATUS 0x00005c8c +#define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0) +#define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4) +#define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8) +#define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12) +#define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16) + +#define BNX2_TDMA_FTQ_DATA 0x00005fc0 +#define BNX2_TDMA_FTQ_CMD 0x00005ff8 +#define BNX2_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX2_TDMA_FTQ_CMD_WR_TOP (1L<<10) +#define BNX2_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX2_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX2_TDMA_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX2_TDMA_FTQ_CMD_RD_DATA (1L<<26) +#define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX2_TDMA_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX2_TDMA_FTQ_CMD_POP (1L<<30) +#define BNX2_TDMA_FTQ_CMD_BUSY (1L<<31) + +#define BNX2_TDMA_FTQ_CTL 0x00005ffc +#define BNX2_TDMA_FTQ_CTL_INTERVENE (1L<<0) +#define BNX2_TDMA_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX2_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX2_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + + + +/* + * hc_reg definition + * offset: 0x6800 + */ +#define BNX2_HC_COMMAND 0x00006800 +#define BNX2_HC_COMMAND_ENABLE (1L<<0) +#define BNX2_HC_COMMAND_SKIP_ABORT (1L<<4) +#define BNX2_HC_COMMAND_COAL_NOW (1L<<16) +#define BNX2_HC_COMMAND_COAL_NOW_WO_INT (1L<<17) +#define BNX2_HC_COMMAND_STATS_NOW (1L<<18) +#define BNX2_HC_COMMAND_FORCE_INT (0x3L<<19) +#define BNX2_HC_COMMAND_FORCE_INT_NULL (0L<<19) +#define BNX2_HC_COMMAND_FORCE_INT_HIGH (1L<<19) +#define BNX2_HC_COMMAND_FORCE_INT_LOW (2L<<19) +#define BNX2_HC_COMMAND_FORCE_INT_FREE (3L<<19) +#define BNX2_HC_COMMAND_CLR_STAT_NOW (1L<<21) + +#define BNX2_HC_STATUS 0x00006804 +#define BNX2_HC_STATUS_MASTER_ABORT (1L<<0) +#define BNX2_HC_STATUS_PARITY_ERROR_STATE (1L<<1) +#define BNX2_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16) +#define BNX2_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17) +#define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18) +#define BNX2_HC_STATUS_NUM_INT_GEN_STAT (1L<<19) +#define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20) +#define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23) +#define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24) +#define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25) + +#define BNX2_HC_CONFIG 0x00006808 +#define BNX2_HC_CONFIG_COLLECT_STATS (1L<<0) +#define BNX2_HC_CONFIG_RX_TMR_MODE (1L<<1) +#define BNX2_HC_CONFIG_TX_TMR_MODE (1L<<2) +#define BNX2_HC_CONFIG_COM_TMR_MODE (1L<<3) +#define BNX2_HC_CONFIG_CMD_TMR_MODE (1L<<4) +#define BNX2_HC_CONFIG_STATISTIC_PRIORITY (1L<<5) +#define BNX2_HC_CONFIG_STATUS_PRIORITY (1L<<6) +#define BNX2_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8) + +#define BNX2_HC_ATTN_BITS_ENABLE 0x0000680c +#define BNX2_HC_STATUS_ADDR_L 0x00006810 +#define BNX2_HC_STATUS_ADDR_H 0x00006814 +#define BNX2_HC_STATISTICS_ADDR_L 0x00006818 +#define BNX2_HC_STATISTICS_ADDR_H 0x0000681c +#define BNX2_HC_TX_QUICK_CONS_TRIP 0x00006820 +#define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0) +#define BNX2_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16) + +#define BNX2_HC_COMP_PROD_TRIP 0x00006824 +#define BNX2_HC_COMP_PROD_TRIP_VALUE (0xffL<<0) +#define BNX2_HC_COMP_PROD_TRIP_INT (0xffL<<16) + +#define BNX2_HC_RX_QUICK_CONS_TRIP 0x00006828 +#define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0) +#define BNX2_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16) + +#define BNX2_HC_RX_TICKS 0x0000682c +#define BNX2_HC_RX_TICKS_VALUE (0x3ffL<<0) +#define BNX2_HC_RX_TICKS_INT (0x3ffL<<16) + +#define BNX2_HC_TX_TICKS 0x00006830 +#define BNX2_HC_TX_TICKS_VALUE (0x3ffL<<0) +#define BNX2_HC_TX_TICKS_INT (0x3ffL<<16) + +#define BNX2_HC_COM_TICKS 0x00006834 +#define BNX2_HC_COM_TICKS_VALUE (0x3ffL<<0) +#define BNX2_HC_COM_TICKS_INT (0x3ffL<<16) + +#define BNX2_HC_CMD_TICKS 0x00006838 +#define BNX2_HC_CMD_TICKS_VALUE (0x3ffL<<0) +#define BNX2_HC_CMD_TICKS_INT (0x3ffL<<16) + +#define BNX2_HC_PERIODIC_TICKS 0x0000683c +#define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0) + +#define BNX2_HC_STAT_COLLECT_TICKS 0x00006840 +#define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4) + +#define BNX2_HC_STATS_TICKS 0x00006844 +#define BNX2_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8) + +#define BNX2_HC_STAT_MEM_DATA 0x0000684c +#define BNX2_HC_STAT_GEN_SEL_0 0x00006850 +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16) +#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24) + +#define BNX2_HC_STAT_GEN_SEL_1 0x00006854 +#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0) +#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8) +#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16) +#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24) + +#define BNX2_HC_STAT_GEN_SEL_2 0x00006858 +#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0) +#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8) +#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16) +#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24) + +#define BNX2_HC_STAT_GEN_SEL_3 0x0000685c +#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0) +#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8) +#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16) +#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24) + +#define BNX2_HC_STAT_GEN_STAT0 0x00006888 +#define BNX2_HC_STAT_GEN_STAT1 0x0000688c +#define BNX2_HC_STAT_GEN_STAT2 0x00006890 +#define BNX2_HC_STAT_GEN_STAT3 0x00006894 +#define BNX2_HC_STAT_GEN_STAT4 0x00006898 +#define BNX2_HC_STAT_GEN_STAT5 0x0000689c +#define BNX2_HC_STAT_GEN_STAT6 0x000068a0 +#define BNX2_HC_STAT_GEN_STAT7 0x000068a4 +#define BNX2_HC_STAT_GEN_STAT8 0x000068a8 +#define BNX2_HC_STAT_GEN_STAT9 0x000068ac +#define BNX2_HC_STAT_GEN_STAT10 0x000068b0 +#define BNX2_HC_STAT_GEN_STAT11 0x000068b4 +#define BNX2_HC_STAT_GEN_STAT12 0x000068b8 +#define BNX2_HC_STAT_GEN_STAT13 0x000068bc +#define BNX2_HC_STAT_GEN_STAT14 0x000068c0 +#define BNX2_HC_STAT_GEN_STAT15 0x000068c4 +#define BNX2_HC_STAT_GEN_STAT_AC0 0x000068c8 +#define BNX2_HC_STAT_GEN_STAT_AC1 0x000068cc +#define BNX2_HC_STAT_GEN_STAT_AC2 0x000068d0 +#define BNX2_HC_STAT_GEN_STAT_AC3 0x000068d4 +#define BNX2_HC_STAT_GEN_STAT_AC4 0x000068d8 +#define BNX2_HC_STAT_GEN_STAT_AC5 0x000068dc +#define BNX2_HC_STAT_GEN_STAT_AC6 0x000068e0 +#define BNX2_HC_STAT_GEN_STAT_AC7 0x000068e4 +#define BNX2_HC_STAT_GEN_STAT_AC8 0x000068e8 +#define BNX2_HC_STAT_GEN_STAT_AC9 0x000068ec +#define BNX2_HC_STAT_GEN_STAT_AC10 0x000068f0 +#define BNX2_HC_STAT_GEN_STAT_AC11 0x000068f4 +#define BNX2_HC_STAT_GEN_STAT_AC12 0x000068f8 +#define BNX2_HC_STAT_GEN_STAT_AC13 0x000068fc +#define BNX2_HC_STAT_GEN_STAT_AC14 0x00006900 +#define BNX2_HC_STAT_GEN_STAT_AC15 0x00006904 +#define BNX2_HC_VIS 0x00006908 +#define BNX2_HC_VIS_STAT_BUILD_STATE (0xfL<<0) +#define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0) +#define BNX2_HC_VIS_STAT_BUILD_STATE_START (1L<<0) +#define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0) +#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0) +#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0) +#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0) +#define BNX2_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0) +#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0) +#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0) +#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0) +#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0) +#define BNX2_HC_VIS_DMA_STAT_STATE (0xfL<<8) +#define BNX2_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8) +#define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8) +#define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8) +#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8) +#define BNX2_HC_VIS_DMA_STAT_STATE_COMP (4L<<8) +#define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8) +#define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8) +#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8) +#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8) +#define BNX2_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8) +#define BNX2_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8) +#define BNX2_HC_VIS_DMA_MSI_STATE (0x7L<<12) +#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15) +#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15) +#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15) +#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15) + +#define BNX2_HC_VIS_1 0x0000690c +#define BNX2_HC_VIS_1_HW_INTACK_STATE (1L<<4) +#define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4) +#define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4) +#define BNX2_HC_VIS_1_SW_INTACK_STATE (1L<<5) +#define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5) +#define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5) +#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6) +#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6) +#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6) +#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7) +#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7) +#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7) +#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17) +#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17) +#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17) +#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17) +#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17) +#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17) +#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17) +#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17) +#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17) +#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21) +#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21) +#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21) +#define BNX2_HC_VIS_1_INT_GEN_STATE (1L<<23) +#define BNX2_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23) +#define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23) +#define BNX2_HC_VIS_1_STAT_CHAN_ID (0x7L<<24) +#define BNX2_HC_VIS_1_INT_B (1L<<27) + +#define BNX2_HC_DEBUG_VECT_PEEK 0x00006910 +#define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX2_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX2_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + + + +/* + * txp_reg definition + * offset: 0x40000 + */ +#define BNX2_TXP_CPU_MODE 0x00045000 +#define BNX2_TXP_CPU_MODE_LOCAL_RST (1L<<0) +#define BNX2_TXP_CPU_MODE_STEP_ENA (1L<<1) +#define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BNX2_TXP_CPU_MODE_MSG_BIT1 (1L<<6) +#define BNX2_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BNX2_TXP_CPU_MODE_SOFT_HALT (1L<<10) +#define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BNX2_TXP_CPU_STATE 0x00045004 +#define BNX2_TXP_CPU_STATE_BREAKPOINT (1L<<0) +#define BNX2_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BNX2_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BNX2_TXP_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BNX2_TXP_CPU_STATE_SOFT_HALTED (1L<<10) +#define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BNX2_TXP_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BNX2_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BNX2_TXP_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BNX2_TXP_CPU_EVENT_MASK 0x00045008 +#define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BNX2_TXP_CPU_PROGRAM_COUNTER 0x0004501c +#define BNX2_TXP_CPU_INSTRUCTION 0x00045020 +#define BNX2_TXP_CPU_DATA_ACCESS 0x00045024 +#define BNX2_TXP_CPU_INTERRUPT_ENABLE 0x00045028 +#define BNX2_TXP_CPU_INTERRUPT_VECTOR 0x0004502c +#define BNX2_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030 +#define BNX2_TXP_CPU_HW_BREAKPOINT 0x00045034 +#define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BNX2_TXP_CPU_DEBUG_VECT_PEEK 0x00045038 +#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX2_TXP_CPU_LAST_BRANCH_ADDR 0x00045048 +#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BNX2_TXP_CPU_REG_FILE 0x00045200 +#define BNX2_TXP_FTQ_DATA 0x000453c0 +#define BNX2_TXP_FTQ_CMD 0x000453f8 +#define BNX2_TXP_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX2_TXP_FTQ_CMD_WR_TOP (1L<<10) +#define BNX2_TXP_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX2_TXP_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX2_TXP_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX2_TXP_FTQ_CMD_RD_DATA (1L<<26) +#define BNX2_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX2_TXP_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX2_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX2_TXP_FTQ_CMD_POP (1L<<30) +#define BNX2_TXP_FTQ_CMD_BUSY (1L<<31) + +#define BNX2_TXP_FTQ_CTL 0x000453fc +#define BNX2_TXP_FTQ_CTL_INTERVENE (1L<<0) +#define BNX2_TXP_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX2_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX2_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX2_TXP_SCRATCH 0x00060000 + + +/* + * tpat_reg definition + * offset: 0x80000 + */ +#define BNX2_TPAT_CPU_MODE 0x00085000 +#define BNX2_TPAT_CPU_MODE_LOCAL_RST (1L<<0) +#define BNX2_TPAT_CPU_MODE_STEP_ENA (1L<<1) +#define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BNX2_TPAT_CPU_MODE_MSG_BIT1 (1L<<6) +#define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BNX2_TPAT_CPU_MODE_SOFT_HALT (1L<<10) +#define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BNX2_TPAT_CPU_STATE 0x00085004 +#define BNX2_TPAT_CPU_STATE_BREAKPOINT (1L<<0) +#define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BNX2_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BNX2_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BNX2_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) +#define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BNX2_TPAT_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BNX2_TPAT_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BNX2_TPAT_CPU_EVENT_MASK 0x00085008 +#define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BNX2_TPAT_CPU_PROGRAM_COUNTER 0x0008501c +#define BNX2_TPAT_CPU_INSTRUCTION 0x00085020 +#define BNX2_TPAT_CPU_DATA_ACCESS 0x00085024 +#define BNX2_TPAT_CPU_INTERRUPT_ENABLE 0x00085028 +#define BNX2_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c +#define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030 +#define BNX2_TPAT_CPU_HW_BREAKPOINT 0x00085034 +#define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038 +#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048 +#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BNX2_TPAT_CPU_REG_FILE 0x00085200 +#define BNX2_TPAT_FTQ_DATA 0x000853c0 +#define BNX2_TPAT_FTQ_CMD 0x000853f8 +#define BNX2_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX2_TPAT_FTQ_CMD_WR_TOP (1L<<10) +#define BNX2_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX2_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX2_TPAT_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX2_TPAT_FTQ_CMD_RD_DATA (1L<<26) +#define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX2_TPAT_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX2_TPAT_FTQ_CMD_POP (1L<<30) +#define BNX2_TPAT_FTQ_CMD_BUSY (1L<<31) + +#define BNX2_TPAT_FTQ_CTL 0x000853fc +#define BNX2_TPAT_FTQ_CTL_INTERVENE (1L<<0) +#define BNX2_TPAT_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX2_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX2_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX2_TPAT_SCRATCH 0x000a0000 + + +/* + * rxp_reg definition + * offset: 0xc0000 + */ +#define BNX2_RXP_CPU_MODE 0x000c5000 +#define BNX2_RXP_CPU_MODE_LOCAL_RST (1L<<0) +#define BNX2_RXP_CPU_MODE_STEP_ENA (1L<<1) +#define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BNX2_RXP_CPU_MODE_MSG_BIT1 (1L<<6) +#define BNX2_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BNX2_RXP_CPU_MODE_SOFT_HALT (1L<<10) +#define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BNX2_RXP_CPU_STATE 0x000c5004 +#define BNX2_RXP_CPU_STATE_BREAKPOINT (1L<<0) +#define BNX2_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BNX2_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BNX2_RXP_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BNX2_RXP_CPU_STATE_SOFT_HALTED (1L<<10) +#define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BNX2_RXP_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BNX2_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BNX2_RXP_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BNX2_RXP_CPU_EVENT_MASK 0x000c5008 +#define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BNX2_RXP_CPU_PROGRAM_COUNTER 0x000c501c +#define BNX2_RXP_CPU_INSTRUCTION 0x000c5020 +#define BNX2_RXP_CPU_DATA_ACCESS 0x000c5024 +#define BNX2_RXP_CPU_INTERRUPT_ENABLE 0x000c5028 +#define BNX2_RXP_CPU_INTERRUPT_VECTOR 0x000c502c +#define BNX2_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030 +#define BNX2_RXP_CPU_HW_BREAKPOINT 0x000c5034 +#define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BNX2_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038 +#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX2_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048 +#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BNX2_RXP_CPU_REG_FILE 0x000c5200 +#define BNX2_RXP_CFTQ_DATA 0x000c5380 +#define BNX2_RXP_CFTQ_CMD 0x000c53b8 +#define BNX2_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX2_RXP_CFTQ_CMD_WR_TOP (1L<<10) +#define BNX2_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX2_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX2_RXP_CFTQ_CMD_SFT_RESET (1L<<25) +#define BNX2_RXP_CFTQ_CMD_RD_DATA (1L<<26) +#define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX2_RXP_CFTQ_CMD_ADD_DATA (1L<<28) +#define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX2_RXP_CFTQ_CMD_POP (1L<<30) +#define BNX2_RXP_CFTQ_CMD_BUSY (1L<<31) + +#define BNX2_RXP_CFTQ_CTL 0x000c53bc +#define BNX2_RXP_CFTQ_CTL_INTERVENE (1L<<0) +#define BNX2_RXP_CFTQ_CTL_OVERFLOW (1L<<1) +#define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX2_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX2_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX2_RXP_FTQ_DATA 0x000c53c0 +#define BNX2_RXP_FTQ_CMD 0x000c53f8 +#define BNX2_RXP_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX2_RXP_FTQ_CMD_WR_TOP (1L<<10) +#define BNX2_RXP_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX2_RXP_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX2_RXP_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX2_RXP_FTQ_CMD_RD_DATA (1L<<26) +#define BNX2_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX2_RXP_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX2_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX2_RXP_FTQ_CMD_POP (1L<<30) +#define BNX2_RXP_FTQ_CMD_BUSY (1L<<31) + +#define BNX2_RXP_FTQ_CTL 0x000c53fc +#define BNX2_RXP_FTQ_CTL_INTERVENE (1L<<0) +#define BNX2_RXP_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX2_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX2_RXP_SCRATCH 0x000e0000 + + +/* + * com_reg definition + * offset: 0x100000 + */ +#define BNX2_COM_CPU_MODE 0x00105000 +#define BNX2_COM_CPU_MODE_LOCAL_RST (1L<<0) +#define BNX2_COM_CPU_MODE_STEP_ENA (1L<<1) +#define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BNX2_COM_CPU_MODE_MSG_BIT1 (1L<<6) +#define BNX2_COM_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BNX2_COM_CPU_MODE_SOFT_HALT (1L<<10) +#define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BNX2_COM_CPU_STATE 0x00105004 +#define BNX2_COM_CPU_STATE_BREAKPOINT (1L<<0) +#define BNX2_COM_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BNX2_COM_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BNX2_COM_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BNX2_COM_CPU_STATE_SOFT_HALTED (1L<<10) +#define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BNX2_COM_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BNX2_COM_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BNX2_COM_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BNX2_COM_CPU_EVENT_MASK 0x00105008 +#define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BNX2_COM_CPU_PROGRAM_COUNTER 0x0010501c +#define BNX2_COM_CPU_INSTRUCTION 0x00105020 +#define BNX2_COM_CPU_DATA_ACCESS 0x00105024 +#define BNX2_COM_CPU_INTERRUPT_ENABLE 0x00105028 +#define BNX2_COM_CPU_INTERRUPT_VECTOR 0x0010502c +#define BNX2_COM_CPU_INTERRUPT_SAVED_PC 0x00105030 +#define BNX2_COM_CPU_HW_BREAKPOINT 0x00105034 +#define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BNX2_COM_CPU_DEBUG_VECT_PEEK 0x00105038 +#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX2_COM_CPU_LAST_BRANCH_ADDR 0x00105048 +#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BNX2_COM_CPU_REG_FILE 0x00105200 +#define BNX2_COM_COMXQ_FTQ_DATA 0x00105340 +#define BNX2_COM_COMXQ_FTQ_CMD 0x00105378 +#define BNX2_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10) +#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26) +#define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX2_COM_COMXQ_FTQ_CMD_POP (1L<<30) +#define BNX2_COM_COMXQ_FTQ_CMD_BUSY (1L<<31) + +#define BNX2_COM_COMXQ_FTQ_CTL 0x0010537c +#define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0) +#define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX2_COM_COMTQ_FTQ_DATA 0x00105380 +#define BNX2_COM_COMTQ_FTQ_CMD 0x001053b8 +#define BNX2_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10) +#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26) +#define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX2_COM_COMTQ_FTQ_CMD_POP (1L<<30) +#define BNX2_COM_COMTQ_FTQ_CMD_BUSY (1L<<31) + +#define BNX2_COM_COMTQ_FTQ_CTL 0x001053bc +#define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0) +#define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX2_COM_COMQ_FTQ_DATA 0x001053c0 +#define BNX2_COM_COMQ_FTQ_CMD 0x001053f8 +#define BNX2_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10) +#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX2_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26) +#define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX2_COM_COMQ_FTQ_CMD_POP (1L<<30) +#define BNX2_COM_COMQ_FTQ_CMD_BUSY (1L<<31) + +#define BNX2_COM_COMQ_FTQ_CTL 0x001053fc +#define BNX2_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0) +#define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX2_COM_SCRATCH 0x00120000 + + +/* + * cp_reg definition + * offset: 0x180000 + */ +#define BNX2_CP_CPU_MODE 0x00185000 +#define BNX2_CP_CPU_MODE_LOCAL_RST (1L<<0) +#define BNX2_CP_CPU_MODE_STEP_ENA (1L<<1) +#define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BNX2_CP_CPU_MODE_MSG_BIT1 (1L<<6) +#define BNX2_CP_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BNX2_CP_CPU_MODE_SOFT_HALT (1L<<10) +#define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BNX2_CP_CPU_STATE 0x00185004 +#define BNX2_CP_CPU_STATE_BREAKPOINT (1L<<0) +#define BNX2_CP_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BNX2_CP_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BNX2_CP_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BNX2_CP_CPU_STATE_SOFT_HALTED (1L<<10) +#define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BNX2_CP_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BNX2_CP_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BNX2_CP_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BNX2_CP_CPU_EVENT_MASK 0x00185008 +#define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BNX2_CP_CPU_PROGRAM_COUNTER 0x0018501c +#define BNX2_CP_CPU_INSTRUCTION 0x00185020 +#define BNX2_CP_CPU_DATA_ACCESS 0x00185024 +#define BNX2_CP_CPU_INTERRUPT_ENABLE 0x00185028 +#define BNX2_CP_CPU_INTERRUPT_VECTOR 0x0018502c +#define BNX2_CP_CPU_INTERRUPT_SAVED_PC 0x00185030 +#define BNX2_CP_CPU_HW_BREAKPOINT 0x00185034 +#define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BNX2_CP_CPU_DEBUG_VECT_PEEK 0x00185038 +#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX2_CP_CPU_LAST_BRANCH_ADDR 0x00185048 +#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BNX2_CP_CPU_REG_FILE 0x00185200 +#define BNX2_CP_CPQ_FTQ_DATA 0x001853c0 +#define BNX2_CP_CPQ_FTQ_CMD 0x001853f8 +#define BNX2_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10) +#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX2_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26) +#define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX2_CP_CPQ_FTQ_CMD_POP (1L<<30) +#define BNX2_CP_CPQ_FTQ_CMD_BUSY (1L<<31) + +#define BNX2_CP_CPQ_FTQ_CTL 0x001853fc +#define BNX2_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0) +#define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX2_CP_SCRATCH 0x001a0000 + + +/* + * mcp_reg definition + * offset: 0x140000 + */ +#define BNX2_MCP_CPU_MODE 0x00145000 +#define BNX2_MCP_CPU_MODE_LOCAL_RST (1L<<0) +#define BNX2_MCP_CPU_MODE_STEP_ENA (1L<<1) +#define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BNX2_MCP_CPU_MODE_MSG_BIT1 (1L<<6) +#define BNX2_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BNX2_MCP_CPU_MODE_SOFT_HALT (1L<<10) +#define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BNX2_MCP_CPU_STATE 0x00145004 +#define BNX2_MCP_CPU_STATE_BREAKPOINT (1L<<0) +#define BNX2_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BNX2_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BNX2_MCP_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BNX2_MCP_CPU_STATE_SOFT_HALTED (1L<<10) +#define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BNX2_MCP_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BNX2_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BNX2_MCP_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BNX2_MCP_CPU_EVENT_MASK 0x00145008 +#define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BNX2_MCP_CPU_PROGRAM_COUNTER 0x0014501c +#define BNX2_MCP_CPU_INSTRUCTION 0x00145020 +#define BNX2_MCP_CPU_DATA_ACCESS 0x00145024 +#define BNX2_MCP_CPU_INTERRUPT_ENABLE 0x00145028 +#define BNX2_MCP_CPU_INTERRUPT_VECTOR 0x0014502c +#define BNX2_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030 +#define BNX2_MCP_CPU_HW_BREAKPOINT 0x00145034 +#define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BNX2_MCP_CPU_DEBUG_VECT_PEEK 0x00145038 +#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX2_MCP_CPU_LAST_BRANCH_ADDR 0x00145048 +#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BNX2_MCP_CPU_REG_FILE 0x00145200 +#define BNX2_MCP_MCPQ_FTQ_DATA 0x001453c0 +#define BNX2_MCP_MCPQ_FTQ_CMD 0x001453f8 +#define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10) +#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26) +#define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX2_MCP_MCPQ_FTQ_CMD_POP (1L<<30) +#define BNX2_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31) + +#define BNX2_MCP_MCPQ_FTQ_CTL 0x001453fc +#define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0) +#define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX2_MCP_ROM 0x00150000 +#define BNX2_MCP_SCRATCH 0x00160000 + +#define BNX2_SHM_HDR_SIGNATURE BNX2_MCP_SCRATCH +#define BNX2_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000 +#define BNX2_SHM_HDR_SIGNATURE_SIG 0x53530000 +#define BNX2_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff +#define BNX2_SHM_HDR_SIGNATURE_VER_ONE 0x00000001 + +#define BNX2_SHM_HDR_ADDR_0 BNX2_MCP_SCRATCH + 4 +#define BNX2_SHM_HDR_ADDR_1 BNX2_MCP_SCRATCH + 8 + + +#define NUM_MC_HASH_REGISTERS 8 + + +/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */ +#define PHY_BCM5706_PHY_ID 0x00206160 + +#define PHY_ID(id) ((id) & 0xfffffff0) +#define PHY_REV_ID(id) ((id) & 0xf) + +/* 5708 Serdes PHY registers */ + +#define BCM5708S_UP1 0xb + +#define BCM5708S_UP1_2G5 0x1 + +#define BCM5708S_BLK_ADDR 0x1f + +#define BCM5708S_BLK_ADDR_DIG 0x0000 +#define BCM5708S_BLK_ADDR_DIG3 0x0002 +#define BCM5708S_BLK_ADDR_TX_MISC 0x0005 + +/* Digital Block */ +#define BCM5708S_1000X_CTL1 0x10 + +#define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001 +#define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010 + +#define BCM5708S_1000X_CTL2 0x11 + +#define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001 + +#define BCM5708S_1000X_STAT1 0x14 + +#define BCM5708S_1000X_STAT1_SGMII 0x0001 +#define BCM5708S_1000X_STAT1_LINK 0x0002 +#define BCM5708S_1000X_STAT1_FD 0x0004 +#define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018 +#define BCM5708S_1000X_STAT1_SPEED_10 0x0000 +#define BCM5708S_1000X_STAT1_SPEED_100 0x0008 +#define BCM5708S_1000X_STAT1_SPEED_1G 0x0010 +#define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018 +#define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020 +#define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040 + +/* Digital3 Block */ +#define BCM5708S_DIG_3_0 0x10 + +#define BCM5708S_DIG_3_0_USE_IEEE 0x0001 + +/* Tx/Misc Block */ +#define BCM5708S_TX_ACTL1 0x15 + +#define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30 + +#define BCM5708S_TX_ACTL3 0x17 + +#define MIN_ETHERNET_PACKET_SIZE 60 +#define MAX_ETHERNET_PACKET_SIZE 1514 +#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014 + +#define RX_COPY_THRESH 92 + +#define DMA_READ_CHANS 5 +#define DMA_WRITE_CHANS 3 + +#define BCM_PAGE_BITS 12 +#define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS) + +#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd)) +#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) + +#define MAX_RX_RINGS 4 +#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd)) +#define MAX_RX_DESC_CNT (RX_DESC_CNT - 1) +#define MAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS) + +#define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) == \ + (MAX_TX_DESC_CNT - 1)) ? \ + (x) + 2 : (x) + 1 + +#define PREV_TX_BD(x) ((((x)-1) & (MAX_TX_DESC_CNT)) == \ + (MAX_TX_DESC_CNT)) ? \ + (x) - 2 : (x) - 1 + +#define TX_RING_IDX(x) ((x) & MAX_TX_DESC_CNT) + +#define NEXT_RX_BD(x) (((x) & (MAX_RX_DESC_CNT - 1)) == \ + (MAX_RX_DESC_CNT - 1)) ? \ + (x) + 2 : (x) + 1 + +#define RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx) + +//#define RX_RING(x) (((x) & ~MAX_RX_DESC_CNT) >> 8) +#define RX_IDX(x) ((x) & MAX_RX_DESC_CNT) + +/* Context size. */ +#define CTX_SHIFT 7 +#define CTX_SIZE (1 << CTX_SHIFT) +#define CTX_MASK (CTX_SIZE - 1) +#define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) +#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) + +#define PHY_CTX_SHIFT 6 +#define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) +#define PHY_CTX_MASK (PHY_CTX_SIZE - 1) +#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) +#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) + +#define MB_KERNEL_CTX_SHIFT 8 +#define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) +#define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) +#define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) + +#define MAX_CID_CNT 0x4000 +#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) +#define INVALID_CID_ADDR 0xffffffff + +#define TX_CID 16 +#define RX_CID 0 + +#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) +#define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID) + +#if 0 +struct sw_bd { + struct sk_buff *skb; + DECLARE_PCI_UNMAP_ADDR(mapping) +}; +#endif + +/* Buffered flash (Atmel: AT45DB011B) specific information */ +#define SEEPROM_PAGE_BITS 2 +#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) +#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) +#define SEEPROM_PAGE_SIZE 4 +#define SEEPROM_TOTAL_SIZE 65536 + +#define BUFFERED_FLASH_PAGE_BITS 9 +#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) +#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) +#define BUFFERED_FLASH_PAGE_SIZE 264 +#define BUFFERED_FLASH_TOTAL_SIZE 0x21000 + +#define SAIFUN_FLASH_PAGE_BITS 8 +#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) +#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) +#define SAIFUN_FLASH_PAGE_SIZE 256 +#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 + +#define ST_MICRO_FLASH_PAGE_BITS 8 +#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) +#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) +#define ST_MICRO_FLASH_PAGE_SIZE 256 +#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 + +#define NVRAM_TIMEOUT_COUNT 30000 + + +#define FLASH_STRAP_MASK (BNX2_NVM_CFG1_FLASH_MODE | \ + BNX2_NVM_CFG1_BUFFER_MODE | \ + BNX2_NVM_CFG1_PROTECT_MODE | \ + BNX2_NVM_CFG1_FLASH_SIZE) + +#define FLASH_BACKUP_STRAP_MASK (0xf << 26) + +struct flash_spec { + u32 strapping; + u32 config1; + u32 config2; + u32 config3; + u32 write1; + u32 buffered; + u32 page_bits; + u32 page_size; + u32 addr_mask; + u32 total_size; + char *name; +}; + +struct bnx2 { + /* Fields used in the tx and intr/napi performance paths are grouped */ + /* together in the beginning of the structure. */ + void /*__iomem*/ *regview; + + struct nic *nic; + struct pci_device *pdev; + + /* atomic_t intr_sem; */ + + struct status_block *status_blk; + u32 last_status_idx; + + u32 flags; +#define PCIX_FLAG 1 +#define PCI_32BIT_FLAG 2 +#define ONE_TDMA_FLAG 4 /* no longer used */ +#define NO_WOL_FLAG 8 +#define USING_DAC_FLAG 0x10 +#define USING_MSI_FLAG 0x20 +#define ASF_ENABLE_FLAG 0x40 + + /* Put tx producer and consumer fields in separate cache lines. */ + u32 tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES))); + u16 tx_prod; + + struct tx_bd *tx_desc_ring; + struct sw_bd *tx_buf_ring; + int tx_ring_size; + + u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES))); + u16 hw_tx_cons; + +#ifdef BCM_VLAN + struct vlan_group *vlgrp; +#endif + + u32 rx_offset; + u32 rx_buf_use_size; /* useable size */ + u32 rx_buf_size; /* with alignment */ + u32 rx_max_ring_idx; + + u32 rx_prod_bseq; + u16 rx_prod; + u16 rx_cons; + u16 hw_rx_cons; + + u32 rx_csum; + +#if 0 + struct rx_bd *rx_desc_ring[MAX_RX_RINGS]; +#endif + struct rx_bd *rx_desc_ring; + + /* End of fields used in the performance code paths. */ + + char *name; + +#if 0 + int timer_interval; + int current_interval; + struct timer_list timer; + struct work_struct reset_task; + int in_reset_task; + + /* Used to synchronize phy accesses. */ + spinlock_t phy_lock; +#endif + + u32 phy_flags; +#define PHY_SERDES_FLAG 1 +#define PHY_CRC_FIX_FLAG 2 +#define PHY_PARALLEL_DETECT_FLAG 4 +#define PHY_2_5G_CAPABLE_FLAG 8 +#define PHY_INT_MODE_MASK_FLAG 0x300 +#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 +#define PHY_INT_MODE_LINK_READY_FLAG 0x200 + + u32 chip_id; + /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ +#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000) +#define CHIP_NUM_5706 0x57060000 +#define CHIP_NUM_5708 0x57080000 + +#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000) +#define CHIP_REV_Ax 0x00000000 +#define CHIP_REV_Bx 0x00001000 +#define CHIP_REV_Cx 0x00002000 + +#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0) +#define CHIP_BONDING(bp) (((bp)->chip_id) & 0x0000000f) + +#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0) +#define CHIP_ID_5706_A0 0x57060000 +#define CHIP_ID_5706_A1 0x57060010 +#define CHIP_ID_5706_A2 0x57060020 +#define CHIP_ID_5708_A0 0x57080000 +#define CHIP_ID_5708_B0 0x57081000 +#define CHIP_ID_5708_B1 0x57081010 + +#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf) + +/* A serdes chip will have the first bit of the bond id set. */ +#define CHIP_BOND_ID_SERDES_BIT 0x01 + + u32 phy_addr; + u32 phy_id; + + u16 bus_speed_mhz; + u8 wol; + + u8 pad; + + u16 fw_wr_seq; + u16 fw_drv_pulse_wr_seq; + + dma_addr_t tx_desc_mapping; + + + int rx_max_ring; + int rx_ring_size; +#if 0 + dma_addr_t rx_desc_mapping[MAX_RX_RINGS]; +#endif + dma_addr_t rx_desc_mapping; + + u16 tx_quick_cons_trip; + u16 tx_quick_cons_trip_int; + u16 rx_quick_cons_trip; + u16 rx_quick_cons_trip_int; + u16 comp_prod_trip; + u16 comp_prod_trip_int; + u16 tx_ticks; + u16 tx_ticks_int; + u16 com_ticks; + u16 com_ticks_int; + u16 cmd_ticks; + u16 cmd_ticks_int; + u16 rx_ticks; + u16 rx_ticks_int; + + u32 stats_ticks; + + dma_addr_t status_blk_mapping; + + struct statistics_block *stats_blk; + dma_addr_t stats_blk_mapping; + + u32 hc_cmd; + u32 rx_mode; + + u16 req_line_speed; + u8 req_duplex; + + u8 link_up; + + u16 line_speed; + u8 duplex; + u8 flow_ctrl; /* actual flow ctrl settings */ + /* may be different from */ + /* req_flow_ctrl if autoneg */ +#define FLOW_CTRL_TX 1 +#define FLOW_CTRL_RX 2 + + u32 advertising; + + u8 req_flow_ctrl; /* flow ctrl advertisement */ + /* settings or forced */ + /* settings */ + u8 autoneg; +#define AUTONEG_SPEED 1 +#define AUTONEG_FLOW_CTRL 2 + + u8 loopback; +#define MAC_LOOPBACK 1 +#define PHY_LOOPBACK 2 + + u8 serdes_an_pending; +#define SERDES_AN_TIMEOUT (HZ / 3) + + u8 mac_addr[8]; + + u32 shmem_base; + + u32 fw_ver; + + int pm_cap; + int pcix_cap; + + /* struct net_device_stats net_stats; */ + + struct flash_spec *flash_info; + u32 flash_size; + + int status_stats_size; +}; + +static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset); +static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val); + +#define REG_RD(bp, offset) \ + readl(bp->regview + offset) + +#define REG_WR(bp, offset, val) \ + writel(val, bp->regview + offset) + +#define REG_WR16(bp, offset, val) \ + writew(val, bp->regview + offset) + +#define REG_RD_IND(bp, offset) \ + bnx2_reg_rd_ind(bp, offset) + +#define REG_WR_IND(bp, offset, val) \ + bnx2_reg_wr_ind(bp, offset, val) + +/* Indirect context access. Unlike the MBQ_WR, these macros will not + * trigger a chip event. */ +static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val); + +#define CTX_WR(bp, cid_addr, offset, val) \ + bnx2_ctx_wr(bp, cid_addr, offset, val) + +struct cpu_reg { + u32 mode; + u32 mode_value_halt; + u32 mode_value_sstep; + + u32 state; + u32 state_value_clear; + + u32 gpr0; + u32 evmask; + u32 pc; + u32 inst; + u32 bp; + + u32 spad_base; + + u32 mips_view_base; +}; + +struct fw_info { + u32 ver_major; + u32 ver_minor; + u32 ver_fix; + + u32 start_addr; + + /* Text section. */ + u32 text_addr; + u32 text_len; + u32 text_index; + u32 *text; + + /* Data section. */ + u32 data_addr; + u32 data_len; + u32 data_index; + u32 *data; + + /* SBSS section. */ + u32 sbss_addr; + u32 sbss_len; + u32 sbss_index; + u32 *sbss; + + /* BSS section. */ + u32 bss_addr; + u32 bss_len; + u32 bss_index; + u32 *bss; + + /* Read-only section. */ + u32 rodata_addr; + u32 rodata_len; + u32 rodata_index; + u32 *rodata; +}; + +#define RV2P_PROC1 0 +#define RV2P_PROC2 1 + + +/* This value (in milliseconds) determines the frequency of the driver + * issuing the PULSE message code. The firmware monitors this periodic + * pulse to determine when to switch to an OS-absent mode. */ +#define DRV_PULSE_PERIOD_MS 250 + +/* This value (in milliseconds) determines how long the driver should + * wait for an acknowledgement from the firmware before timing out. Once + * the firmware has timed out, the driver will assume there is no firmware + * running and there won't be any firmware-driver synchronization during a + * driver reset. */ +#define FW_ACK_TIME_OUT_MS 100 + + +#define BNX2_DRV_RESET_SIGNATURE 0x00000000 +#define BNX2_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ +//#define DRV_RESET_SIGNATURE_MAGIC 0x47495352 /* RSIG */ + +#define BNX2_DRV_MB 0x00000004 +#define BNX2_DRV_MSG_CODE 0xff000000 +#define BNX2_DRV_MSG_CODE_RESET 0x01000000 +#define BNX2_DRV_MSG_CODE_UNLOAD 0x02000000 +#define BNX2_DRV_MSG_CODE_SHUTDOWN 0x03000000 +#define BNX2_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 +#define BNX2_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 +#define BNX2_DRV_MSG_CODE_PULSE 0x06000000 +#define BNX2_DRV_MSG_CODE_DIAG 0x07000000 +#define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 + +#define BNX2_DRV_MSG_DATA 0x00ff0000 +#define BNX2_DRV_MSG_DATA_WAIT0 0x00010000 +#define BNX2_DRV_MSG_DATA_WAIT1 0x00020000 +#define BNX2_DRV_MSG_DATA_WAIT2 0x00030000 +#define BNX2_DRV_MSG_DATA_WAIT3 0x00040000 + +#define BNX2_DRV_MSG_SEQ 0x0000ffff + +#define BNX2_FW_MB 0x00000008 +#define BNX2_FW_MSG_ACK 0x0000ffff +#define BNX2_FW_MSG_STATUS_MASK 0x00ff0000 +#define BNX2_FW_MSG_STATUS_OK 0x00000000 +#define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000 + +#define BNX2_LINK_STATUS 0x0000000c +#define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff +#define BNX2_LINK_STATUS_LINK_UP 0x1 +#define BNX2_LINK_STATUS_LINK_DOWN 0x0 +#define BNX2_LINK_STATUS_SPEED_MASK 0x1e +#define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1) +#define BNX2_LINK_STATUS_10HALF (1<<1) +#define BNX2_LINK_STATUS_10FULL (2<<1) +#define BNX2_LINK_STATUS_100HALF (3<<1) +#define BNX2_LINK_STATUS_100BASE_T4 (4<<1) +#define BNX2_LINK_STATUS_100FULL (5<<1) +#define BNX2_LINK_STATUS_1000HALF (6<<1) +#define BNX2_LINK_STATUS_1000FULL (7<<1) +#define BNX2_LINK_STATUS_2500HALF (8<<1) +#define BNX2_LINK_STATUS_2500FULL (9<<1) +#define BNX2_LINK_STATUS_AN_ENABLED (1<<5) +#define BNX2_LINK_STATUS_AN_COMPLETE (1<<6) +#define BNX2_LINK_STATUS_PARALLEL_DET (1<<7) +#define BNX2_LINK_STATUS_RESERVED (1<<8) +#define BNX2_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) +#define BNX2_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) +#define BNX2_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) +#define BNX2_LINK_STATUS_PARTNER_AD_100FULL (1<<12) +#define BNX2_LINK_STATUS_PARTNER_AD_100HALF (1<<13) +#define BNX2_LINK_STATUS_PARTNER_AD_10FULL (1<<14) +#define BNX2_LINK_STATUS_PARTNER_AD_10HALF (1<<15) +#define BNX2_LINK_STATUS_TX_FC_ENABLED (1<<16) +#define BNX2_LINK_STATUS_RX_FC_ENABLED (1<<17) +#define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) +#define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) +#define BNX2_LINK_STATUS_SERDES_LINK (1<<20) +#define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) +#define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) + +#define BNX2_DRV_PULSE_MB 0x00000010 +#define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff + +/* Indicate to the firmware not to go into the + * OS absent when it is not getting driver pulse. + * This is used for debugging. */ +#define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 + +#define BNX2_DEV_INFO_SIGNATURE 0x00000020 +#define BNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900 +#define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 +#define BNX2_DEV_INFO_FEATURE_CFG_VALID 0x01 +#define BNX2_DEV_INFO_SECONDARY_PORT 0x80 +#define BNX2_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 + +#define BNX2_SHARED_HW_CFG_PART_NUM 0x00000024 + +#define BNX2_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 +#define BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 +#define BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 +#define BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 +#define BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff + +#define BNX2_SHARED_HW_CFG POWER_CONSUMED 0x00000038 +#define BNX2_SHARED_HW_CFG_CONFIG 0x0000003c +#define BNX2_SHARED_HW_CFG_DESIGN_NIC 0 +#define BNX2_SHARED_HW_CFG_DESIGN_LOM 0x1 +#define BNX2_SHARED_HW_CFG_PHY_COPPER 0 +#define BNX2_SHARED_HW_CFG_PHY_FIBER 0x2 +#define BNX2_SHARED_HW_CFG_PHY_2_5G 0x20 +#define BNX2_SHARED_HW_CFG_PHY_BACKPLANE 0x40 +#define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 +#define BNX2_SHARED_HW_CFG_LED_MODE_MASK 0x300 +#define BNX2_SHARED_HW_CFG_LED_MODE_MAC 0 +#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 +#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 + +#define BNX2_SHARED_HW_CFG_CONFIG2 0x00000040 +#define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 + +#define BNX2_DEV_INFO_BC_REV 0x0000004c + +#define BNX2_PORT_HW_CFG_MAC_UPPER 0x00000050 +#define BNX2_PORT_HW_CFG_UPPERMAC_MASK 0xffff + +#define BNX2_PORT_HW_CFG_MAC_LOWER 0x00000054 +#define BNX2_PORT_HW_CFG_CONFIG 0x00000058 +#define BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff +#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 +#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 +#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 +#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000 + +#define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 +#define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c +#define BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 +#define BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 +#define BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 +#define BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c + +#define BNX2_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 + +#define BNX2_DEV_INFO_FORMAT_REV 0x000000c4 +#define BNX2_DEV_INFO_FORMAT_REV_MASK 0xff000000 +#define BNX2_DEV_INFO_FORMAT_REV_ID ('A' << 24) + +#define BNX2_SHARED_FEATURE 0x000000c8 +#define BNX2_SHARED_FEATURE_MASK 0xffffffff + +#define BNX2_PORT_FEATURE 0x000000d8 +#define BNX2_PORT2_FEATURE 0x00000014c +#define BNX2_PORT_FEATURE_WOL_ENABLED 0x01000000 +#define BNX2_PORT_FEATURE_MBA_ENABLED 0x02000000 +#define BNX2_PORT_FEATURE_ASF_ENABLED 0x04000000 +#define BNX2_PORT_FEATURE_IMD_ENABLED 0x08000000 +#define BNX2_PORT_FEATURE_BAR1_SIZE_MASK 0xf +#define BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 +#define BNX2_PORT_FEATURE_BAR1_SIZE_64K 0x1 +#define BNX2_PORT_FEATURE_BAR1_SIZE_128K 0x2 +#define BNX2_PORT_FEATURE_BAR1_SIZE_256K 0x3 +#define BNX2_PORT_FEATURE_BAR1_SIZE_512K 0x4 +#define BNX2_PORT_FEATURE_BAR1_SIZE_1M 0x5 +#define BNX2_PORT_FEATURE_BAR1_SIZE_2M 0x6 +#define BNX2_PORT_FEATURE_BAR1_SIZE_4M 0x7 +#define BNX2_PORT_FEATURE_BAR1_SIZE_8M 0x8 +#define BNX2_PORT_FEATURE_BAR1_SIZE_16M 0x9 +#define BNX2_PORT_FEATURE_BAR1_SIZE_32M 0xa +#define BNX2_PORT_FEATURE_BAR1_SIZE_64M 0xb +#define BNX2_PORT_FEATURE_BAR1_SIZE_128M 0xc +#define BNX2_PORT_FEATURE_BAR1_SIZE_256M 0xd +#define BNX2_PORT_FEATURE_BAR1_SIZE_512M 0xe +#define BNX2_PORT_FEATURE_BAR1_SIZE_1G 0xf + +#define BNX2_PORT_FEATURE_WOL 0xdc +#define BNX2_PORT2_FEATURE_WOL 0x150 +#define BNX2_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 +#define BNX2_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 +#define BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 +#define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 +#define BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 +#define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 +#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf +#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 +#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 +#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 +#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 +#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 +#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 +#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 +#define BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 +#define BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 +#define BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 + +#define BNX2_PORT_FEATURE_MBA 0xe0 +#define BNX2_PORT2_FEATURE_MBA 0x154 +#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 +#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 +#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 +#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 +#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 +#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 +#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c +#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 +#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 +#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 +#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc +#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 +#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 +#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 +#define BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 +#define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 +#define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 +#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 +#define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 +#define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 +#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 +#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 +#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 +#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 +#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 +#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 + +#define BNX2_PORT_FEATURE_IMD 0xe4 +#define BNX2_PORT2_FEATURE_IMD 0x158 +#define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 +#define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 + +#define BNX2_PORT_FEATURE_VLAN 0xe8 +#define BNX2_PORT2_FEATURE_VLAN 0x15c +#define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff +#define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 + +#define BNX2_BC_STATE_RESET_TYPE 0x000001c0 +#define BNX2_BC_STATE_RESET_TYPE_SIG 0x00005254 +#define BNX2_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff +#define BNX2_BC_STATE_RESET_TYPE_NONE (BNX2_BC_STATE_RESET_TYPE_SIG | \ + 0x00010000) +#define BNX2_BC_STATE_RESET_TYPE_PCI (BNX2_BC_STATE_RESET_TYPE_SIG | \ + 0x00020000) +#define BNX2_BC_STATE_RESET_TYPE_VAUX (BNX2_BC_STATE_RESET_TYPE_SIG | \ + 0x00030000) +#define BNX2_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE +#define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \ + DRV_MSG_CODE_RESET) +#define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \ + DRV_MSG_CODE_UNLOAD) +#define BNX2_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX2_BC_STATE_RESET_TYPE_SIG | \ + DRV_MSG_CODE_SHUTDOWN) +#define BNX2_BC_STATE_RESET_TYPE_DRV_WOL (BNX2_BC_STATE_RESET_TYPE_SIG | \ + DRV_MSG_CODE_WOL) +#define BNX2_BC_STATE_RESET_TYPE_DRV_DIAG (BNX2_BC_STATE_RESET_TYPE_SIG | \ + DRV_MSG_CODE_DIAG) +#define BNX2_BC_STATE_RESET_TYPE_VALUE(msg) (BNX2_BC_STATE_RESET_TYPE_SIG | \ + (msg)) + +#define BNX2_BC_STATE 0x000001c4 +#define BNX2_BC_STATE_ERR_MASK 0x0000ff00 +#define BNX2_BC_STATE_SIGN 0x42530000 +#define BNX2_BC_STATE_SIGN_MASK 0xffff0000 +#define BNX2_BC_STATE_BC1_START (BNX2_BC_STATE_SIGN | 0x1) +#define BNX2_BC_STATE_GET_NVM_CFG1 (BNX2_BC_STATE_SIGN | 0x2) +#define BNX2_BC_STATE_PROG_BAR (BNX2_BC_STATE_SIGN | 0x3) +#define BNX2_BC_STATE_INIT_VID (BNX2_BC_STATE_SIGN | 0x4) +#define BNX2_BC_STATE_GET_NVM_CFG2 (BNX2_BC_STATE_SIGN | 0x5) +#define BNX2_BC_STATE_APPLY_WKARND (BNX2_BC_STATE_SIGN | 0x6) +#define BNX2_BC_STATE_LOAD_BC2 (BNX2_BC_STATE_SIGN | 0x7) +#define BNX2_BC_STATE_GOING_BC2 (BNX2_BC_STATE_SIGN | 0x8) +#define BNX2_BC_STATE_GOING_DIAG (BNX2_BC_STATE_SIGN | 0x9) +#define BNX2_BC_STATE_RT_FINAL_INIT (BNX2_BC_STATE_SIGN | 0x81) +#define BNX2_BC_STATE_RT_WKARND (BNX2_BC_STATE_SIGN | 0x82) +#define BNX2_BC_STATE_RT_DRV_PULSE (BNX2_BC_STATE_SIGN | 0x83) +#define BNX2_BC_STATE_RT_FIOEVTS (BNX2_BC_STATE_SIGN | 0x84) +#define BNX2_BC_STATE_RT_DRV_CMD (BNX2_BC_STATE_SIGN | 0x85) +#define BNX2_BC_STATE_RT_LOW_POWER (BNX2_BC_STATE_SIGN | 0x86) +#define BNX2_BC_STATE_RT_SET_WOL (BNX2_BC_STATE_SIGN | 0x87) +#define BNX2_BC_STATE_RT_OTHER_FW (BNX2_BC_STATE_SIGN | 0x88) +#define BNX2_BC_STATE_RT_GOING_D3 (BNX2_BC_STATE_SIGN | 0x89) +#define BNX2_BC_STATE_ERR_BAD_VERSION (BNX2_BC_STATE_SIGN | 0x0100) +#define BNX2_BC_STATE_ERR_BAD_BC2_CRC (BNX2_BC_STATE_SIGN | 0x0200) +#define BNX2_BC_STATE_ERR_BC1_LOOP (BNX2_BC_STATE_SIGN | 0x0300) +#define BNX2_BC_STATE_ERR_UNKNOWN_CMD (BNX2_BC_STATE_SIGN | 0x0400) +#define BNX2_BC_STATE_ERR_DRV_DEAD (BNX2_BC_STATE_SIGN | 0x0500) +#define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600) +#define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700) + +#define BNX2_BC_STATE_DEBUG_CMD 0x1dc +#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 +#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 +#define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff +#define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff + +#define HOST_VIEW_SHMEM_BASE 0x167c00 + +/* Enable or disable autonegotiation. If this is set to enable, + * the forced link modes above are completely ignored. + */ +#define AUTONEG_DISABLE 0x00 +#define AUTONEG_ENABLE 0x01 + +#define RX_OFFSET (sizeof(struct l2_fhdr) + 2) + +#define RX_BUF_CNT 20 + +/* 8 for CRC and VLAN */ +#define RX_BUF_USE_SIZE (ETH_MAX_MTU + ETH_HLEN + RX_OFFSET + 8) + +/* 8 for alignment */ +//#define RX_BUF_SIZE (RX_BUF_USE_SIZE + 8) +#define RX_BUF_SIZE (L1_CACHE_ALIGN(RX_BUF_USE_SIZE + 8)) + + +#endif diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/davicom.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/davicom.c new file mode 100644 index 0000000..07c5e1b --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/davicom.c @@ -0,0 +1,727 @@ +#ifdef ALLMULTI +#error multicast support is not yet implemented +#endif +/* + DAVICOM DM9009/DM9102/DM9102A Etherboot Driver V1.00 + + This driver was ported from Marty Connor's Tulip Etherboot driver. + Thanks Marty Connor (mdc@etherboot.org) + + This davicom etherboot driver supports DM9009/DM9102/DM9102A/ + DM9102A+DM9801/DM9102A+DM9802 NICs. + + This software may be used and distributed according to the terms + of the GNU Public License, incorporated herein by reference. + +*/ + +FILE_LICENCE ( GPL_ANY ); + +/*********************************************************************/ +/* Revision History */ +/*********************************************************************/ + +/* + 19 OCT 2000 Sten 1.00 + Different half and full duplex mode + Do the different programming for DM9801/DM9802 + + 12 OCT 2000 Sten 0.90 + This driver was ported from tulip driver and it + has the following difference. + Changed symbol tulip/TULIP to davicom/DAVICOM + Deleted some code that did not use in this driver. + Used chain-strcture to replace ring structure + for both TX/RX descriptor. + Allocated two tx descriptor. + According current media mode to set operating + register(CR6) +*/ + + +/*********************************************************************/ +/* Declarations */ +/*********************************************************************/ + +#include "etherboot.h" +#include "nic.h" +#include <gpxe/pci.h> +#include <gpxe/ethernet.h> + +#undef DAVICOM_DEBUG +#undef DAVICOM_DEBUG_WHERE + +#define TX_TIME_OUT 2*TICKS_PER_SEC + +/* Register offsets for davicom device */ +enum davicom_offsets { + CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, + CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58, + CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0 +}; + +/* EEPROM Address width definitions */ +#define EEPROM_ADDRLEN 6 +#define EEPROM_SIZE 32 /* 1 << EEPROM_ADDRLEN */ +/* Used to be 128, but we only need to read enough to get the MAC + address at bytes 20..25 */ + +/* Data Read from the EEPROM */ +static unsigned char ee_data[EEPROM_SIZE]; + +/* The EEPROM commands include the alway-set leading bit. */ +#define EE_WRITE_CMD (5 << addr_len) +#define EE_READ_CMD (6 << addr_len) +#define EE_ERASE_CMD (7 << addr_len) + +/* EEPROM_Ctrl bits. */ +#define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */ +#define EE_CS 0x01 /* EEPROM chip select. */ +#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ +#define EE_WRITE_0 0x01 +#define EE_WRITE_1 0x05 +#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ +#define EE_ENB (0x4800 | EE_CS) + +/* Sten 10/11 for phyxcer */ +#define PHY_DATA_0 0x0 +#define PHY_DATA_1 0x20000 +#define MDCLKH 0x10000 + +/* Delay between EEPROM clock transitions. Even at 33Mhz current PCI + implementations don't overrun the EEPROM clock. We add a bus + turn-around to insure that this remains true. */ +#define eeprom_delay() inl(ee_addr) + +/* helpful macro if on a big_endian machine for changing byte order. + not strictly needed on Intel + Already defined in Etherboot includes +#define le16_to_cpu(val) (val) +*/ + +/* transmit and receive descriptor format */ +struct txdesc { + volatile unsigned long status; /* owner, status */ + unsigned long buf1sz:11, /* size of buffer 1 */ + buf2sz:11, /* size of buffer 2 */ + control:10; /* control bits */ + const unsigned char *buf1addr; /* buffer 1 address */ + const unsigned char *buf2addr; /* buffer 2 address */ +}; + +struct rxdesc { + volatile unsigned long status; /* owner, status */ + unsigned long buf1sz:11, /* size of buffer 1 */ + buf2sz:11, /* size of buffer 2 */ + control:10; /* control bits */ + unsigned char *buf1addr; /* buffer 1 address */ + unsigned char *buf2addr; /* buffer 2 address */ +}; + +/* Size of transmit and receive buffers */ +#define BUFLEN 1536 + +/*********************************************************************/ +/* Global Storage */ +/*********************************************************************/ + +static struct nic_operations davicom_operations; + +/* PCI Bus parameters */ +static unsigned short vendor, dev_id; +static unsigned long ioaddr; + +/* Note: transmit and receive buffers must be longword aligned and + longword divisable */ + +/* transmit descriptor and buffer */ +#define NTXD 2 +#define NRXD 4 +struct { + struct txdesc txd[NTXD] __attribute__ ((aligned(4))); + unsigned char txb[BUFLEN] __attribute__ ((aligned(4))); + struct rxdesc rxd[NRXD] __attribute__ ((aligned(4))); + unsigned char rxb[NRXD * BUFLEN] __attribute__ ((aligned(4))); +} davicom_bufs __shared; +#define txd davicom_bufs.txd +#define txb davicom_bufs.txb +#define rxd davicom_bufs.rxd +#define rxb davicom_bufs.rxb +static int rxd_tail; +static int TxPtr; + + +/*********************************************************************/ +/* Function Prototypes */ +/*********************************************************************/ +static void whereami(const char *str); +static int read_eeprom(unsigned long ioaddr, int location, int addr_len); +static int davicom_probe(struct nic *nic,struct pci_device *pci); +static void davicom_init_chain(struct nic *nic); /* Sten 10/9 */ +static void davicom_reset(struct nic *nic); +static void davicom_transmit(struct nic *nic, const char *d, unsigned int t, + unsigned int s, const char *p); +static int davicom_poll(struct nic *nic, int retrieve); +static void davicom_disable(struct nic *nic); +#ifdef DAVICOM_DEBUG +static void davicom_more(void); +#endif /* DAVICOM_DEBUG */ +static void davicom_wait(unsigned int nticks); +static int phy_read(int); +static void phy_write(int, u16); +static void phy_write_1bit(u32, u32); +static int phy_read_1bit(u32); +static void davicom_media_chk(struct nic *); + + +/*********************************************************************/ +/* Utility Routines */ +/*********************************************************************/ +static inline void whereami(const char *str) +{ + printf("%s\n", str); + /* sleep(2); */ +} + +#ifdef DAVICOM_DEBUG +static void davicom_more() +{ + printf("\n\n-- more --"); + while (!iskey()) + /* wait */; + getchar(); + printf("\n\n"); +} +#endif /* DAVICOM_DEBUG */ + +static void davicom_wait(unsigned int nticks) +{ + unsigned int to = currticks() + nticks; + while (currticks() < to) + /* wait */ ; +} + + +/*********************************************************************/ +/* For DAVICOM phyxcer register by MII interface */ +/*********************************************************************/ +/* + Read a word data from phy register +*/ +static int phy_read(int location) +{ + int i, phy_addr=1; + u16 phy_data; + u32 io_dcr9; + + whereami("phy_read\n"); + + io_dcr9 = ioaddr + CSR9; + + /* Send 33 synchronization clock to Phy controller */ + for (i=0; i<34; i++) + phy_write_1bit(io_dcr9, PHY_DATA_1); + + /* Send start command(01) to Phy */ + phy_write_1bit(io_dcr9, PHY_DATA_0); + phy_write_1bit(io_dcr9, PHY_DATA_1); + + /* Send read command(10) to Phy */ + phy_write_1bit(io_dcr9, PHY_DATA_1); + phy_write_1bit(io_dcr9, PHY_DATA_0); + + /* Send Phy addres */ + for (i=0x10; i>0; i=i>>1) + phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0); + + /* Send register addres */ + for (i=0x10; i>0; i=i>>1) + phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0); + + /* Skip transition state */ + phy_read_1bit(io_dcr9); + + /* read 16bit data */ + for (phy_data=0, i=0; i<16; i++) { + phy_data<<=1; + phy_data|=phy_read_1bit(io_dcr9); + } + + return phy_data; +} + +/* + Write a word to Phy register +*/ +static void phy_write(int location, u16 phy_data) +{ + u16 i, phy_addr=1; + u32 io_dcr9; + + whereami("phy_write\n"); + + io_dcr9 = ioaddr + CSR9; + + /* Send 33 synchronization clock to Phy controller */ + for (i=0; i<34; i++) + phy_write_1bit(io_dcr9, PHY_DATA_1); + + /* Send start command(01) to Phy */ + phy_write_1bit(io_dcr9, PHY_DATA_0); + phy_write_1bit(io_dcr9, PHY_DATA_1); + + /* Send write command(01) to Phy */ + phy_write_1bit(io_dcr9, PHY_DATA_0); + phy_write_1bit(io_dcr9, PHY_DATA_1); + + /* Send Phy addres */ + for (i=0x10; i>0; i=i>>1) + phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0); + + /* Send register addres */ + for (i=0x10; i>0; i=i>>1) + phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0); + + /* written trasnition */ + phy_write_1bit(io_dcr9, PHY_DATA_1); + phy_write_1bit(io_dcr9, PHY_DATA_0); + + /* Write a word data to PHY controller */ + for (i=0x8000; i>0; i>>=1) + phy_write_1bit(io_dcr9, phy_data&i ? PHY_DATA_1: PHY_DATA_0); +} + +/* + Write one bit data to Phy Controller +*/ +static void phy_write_1bit(u32 ee_addr, u32 phy_data) +{ + whereami("phy_write_1bit\n"); + outl(phy_data, ee_addr); /* MII Clock Low */ + eeprom_delay(); + outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */ + eeprom_delay(); + outl(phy_data, ee_addr); /* MII Clock Low */ + eeprom_delay(); +} + +/* + Read one bit phy data from PHY controller +*/ +static int phy_read_1bit(u32 ee_addr) +{ + int phy_data; + + whereami("phy_read_1bit\n"); + + outl(0x50000, ee_addr); + eeprom_delay(); + + phy_data=(inl(ee_addr)>>19) & 0x1; + + outl(0x40000, ee_addr); + eeprom_delay(); + + return phy_data; +} + +/* + DM9801/DM9802 present check and program +*/ +static void HPNA_process(void) +{ + + if ( (phy_read(3) & 0xfff0) == 0xb900 ) { + if ( phy_read(31) == 0x4404 ) { + /* DM9801 present */ + if (phy_read(3) == 0xb901) + phy_write(16, 0x5); /* DM9801 E4 */ + else + phy_write(16, 0x1005); /* DM9801 E3 and others */ + phy_write(25, ((phy_read(24) + 3) & 0xff) | 0xf000); + } else { + /* DM9802 present */ + phy_write(16, 0x5); + phy_write(25, (phy_read(25) & 0xff00) + 2); + } + } +} + +/* + Sense media mode and set CR6 +*/ +static void davicom_media_chk(struct nic * nic __unused) +{ + unsigned long to, csr6; + + csr6 = 0x00200000; /* SF */ + outl(csr6, ioaddr + CSR6); + +#define PCI_DEVICE_ID_DM9009 0x9009 + if (vendor == PCI_VENDOR_ID_DAVICOM && dev_id == PCI_DEVICE_ID_DM9009) { + /* Set to 10BaseT mode for DM9009 */ + phy_write(0, 0); + } else { + /* For DM9102/DM9102A */ + to = currticks() + 2 * TICKS_PER_SEC; + while ( ((phy_read(1) & 0x24)!=0x24) && (currticks() < to)) + /* wait */ ; + + if ( (phy_read(1) & 0x24) == 0x24 ) { + if (phy_read(17) & 0xa000) + csr6 |= 0x00000200; /* Full Duplex mode */ + } else + csr6 |= 0x00040000; /* Select DM9801/DM9802 when Ethernet link failed */ + } + + /* set the chip's operating mode */ + outl(csr6, ioaddr + CSR6); + + /* DM9801/DM9802 present check & program */ + if (csr6 & 0x40000) + HPNA_process(); +} + + +/*********************************************************************/ +/* EEPROM Reading Code */ +/*********************************************************************/ +/* EEPROM routines adapted from the Linux Tulip Code */ +/* Reading a serial EEPROM is a "bit" grungy, but we work our way + through:->. +*/ +static int read_eeprom(unsigned long ioaddr, int location, int addr_len) +{ + int i; + unsigned short retval = 0; + long ee_addr = ioaddr + CSR9; + int read_cmd = location | EE_READ_CMD; + + whereami("read_eeprom\n"); + + outl(EE_ENB & ~EE_CS, ee_addr); + outl(EE_ENB, ee_addr); + + /* Shift the read command bits out. */ + for (i = 4 + addr_len; i >= 0; i--) { + short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + outl(EE_ENB | dataval, ee_addr); + eeprom_delay(); + outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); + eeprom_delay(); + } + outl(EE_ENB, ee_addr); + + for (i = 16; i > 0; i--) { + outl(EE_ENB | EE_SHIFT_CLK, ee_addr); + eeprom_delay(); + retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0); + outl(EE_ENB, ee_addr); + eeprom_delay(); + } + + /* Terminate the EEPROM access. */ + outl(EE_ENB & ~EE_CS, ee_addr); + return retval; +} + +/*********************************************************************/ +/* davicom_init_chain - setup the tx and rx descriptors */ +/* Sten 10/9 */ +/*********************************************************************/ +static void davicom_init_chain(struct nic *nic) +{ + int i; + + /* setup the transmit descriptor */ + /* Sten: Set 2 TX descriptor but use one TX buffer because + it transmit a packet and wait complete every time. */ + for (i=0; i<NTXD; i++) { + txd[i].buf1addr = (void *)virt_to_bus(&txb[0]); /* Used same TX buffer */ + txd[i].buf2addr = (void *)virt_to_bus(&txd[i+1]); /* Point to Next TX desc */ + txd[i].buf1sz = 0; + txd[i].buf2sz = 0; + txd[i].control = 0x184; /* Begin/End/Chain */ + txd[i].status = 0x00000000; /* give ownership to Host */ + } + + /* construct perfect filter frame with mac address as first match + and broadcast address for all others */ + for (i=0; i<192; i++) txb[i] = 0xFF; + txb[0] = nic->node_addr[0]; + txb[1] = nic->node_addr[1]; + txb[4] = nic->node_addr[2]; + txb[5] = nic->node_addr[3]; + txb[8] = nic->node_addr[4]; + txb[9] = nic->node_addr[5]; + + /* setup receive descriptor */ + for (i=0; i<NRXD; i++) { + rxd[i].buf1addr = (void *)virt_to_bus(&rxb[i * BUFLEN]); + rxd[i].buf2addr = (void *)virt_to_bus(&rxd[i+1]); /* Point to Next RX desc */ + rxd[i].buf1sz = BUFLEN; + rxd[i].buf2sz = 0; /* not used */ + rxd[i].control = 0x4; /* Chain Structure */ + rxd[i].status = 0x80000000; /* give ownership to device */ + } + + /* Chain the last descriptor to first */ + txd[NTXD - 1].buf2addr = (void *)virt_to_bus(&txd[0]); + rxd[NRXD - 1].buf2addr = (void *)virt_to_bus(&rxd[0]); + TxPtr = 0; + rxd_tail = 0; +} + + +/*********************************************************************/ +/* davicom_reset - Reset adapter */ +/*********************************************************************/ +static void davicom_reset(struct nic *nic) +{ + unsigned long to; + + whereami("davicom_reset\n"); + + /* Stop Tx and RX */ + outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); + + /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ + outl(0x00000001, ioaddr + CSR0); + + davicom_wait(TICKS_PER_SEC); + + /* TX/RX descriptor burst */ + outl(0x0C00000, ioaddr + CSR0); /* Sten 10/9 */ + + /* set up transmit and receive descriptors */ + davicom_init_chain(nic); /* Sten 10/9 */ + + /* Point to receive descriptor */ + outl(virt_to_bus(&rxd[0]), ioaddr + CSR3); + outl(virt_to_bus(&txd[0]), ioaddr + CSR4); /* Sten 10/9 */ + + /* According phyxcer media mode to set CR6, + DM9102/A phyxcer can auto-detect media mode */ + davicom_media_chk(nic); + + /* Prepare Setup Frame Sten 10/9 */ + txd[TxPtr].buf1sz = 192; + txd[TxPtr].control = 0x024; /* SF/CE */ + txd[TxPtr].status = 0x80000000; /* Give ownership to device */ + + /* Start Tx */ + outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6); + /* immediate transmit demand */ + outl(0, ioaddr + CSR1); + + to = currticks() + TX_TIME_OUT; + while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) /* Sten 10/9 */ + /* wait */ ; + + if (currticks() >= to) { + printf ("TX Setup Timeout!\n"); + } + /* Point to next TX descriptor */ + TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */ + +#ifdef DAVICOM_DEBUG + printf("txd.status = %X\n", txd.status); + printf("ticks = %d\n", currticks() - (to - TX_TIME_OUT)); + davicom_more(); +#endif + + /* enable RX */ + outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6); + /* immediate poll demand */ + outl(0, ioaddr + CSR2); +} + + +/*********************************************************************/ +/* eth_transmit - Transmit a frame */ +/*********************************************************************/ +static void davicom_transmit(struct nic *nic, const char *d, unsigned int t, + unsigned int s, const char *p) +{ + unsigned long to; + + whereami("davicom_transmit\n"); + + /* Stop Tx */ + /* outl(inl(ioaddr + CSR6) & ~0x00002000, ioaddr + CSR6); */ + + /* setup ethernet header */ + memcpy(&txb[0], d, ETH_ALEN); /* DA 6byte */ + memcpy(&txb[ETH_ALEN], nic->node_addr, ETH_ALEN); /* SA 6byte*/ + txb[ETH_ALEN*2] = (t >> 8) & 0xFF; /* Frame type: 2byte */ + txb[ETH_ALEN*2+1] = t & 0xFF; + memcpy(&txb[ETH_HLEN], p, s); /* Frame data */ + + /* setup the transmit descriptor */ + txd[TxPtr].buf1sz = ETH_HLEN+s; + txd[TxPtr].control = 0x00000184; /* LS+FS+CE */ + txd[TxPtr].status = 0x80000000; /* give ownership to device */ + + /* immediate transmit demand */ + outl(0, ioaddr + CSR1); + + to = currticks() + TX_TIME_OUT; + while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) + /* wait */ ; + + if (currticks() >= to) { + printf ("TX Timeout!\n"); + } + + /* Point to next TX descriptor */ + TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */ + +} + +/*********************************************************************/ +/* eth_poll - Wait for a frame */ +/*********************************************************************/ +static int davicom_poll(struct nic *nic, int retrieve) +{ + whereami("davicom_poll\n"); + + if (rxd[rxd_tail].status & 0x80000000) + return 0; + + if ( ! retrieve ) return 1; + + whereami("davicom_poll got one\n"); + + nic->packetlen = (rxd[rxd_tail].status & 0x3FFF0000) >> 16; + + if( rxd[rxd_tail].status & 0x00008000){ + rxd[rxd_tail].status = 0x80000000; + rxd_tail++; + if (rxd_tail == NRXD) rxd_tail = 0; + return 0; + } + + /* copy packet to working buffer */ + /* XXX - this copy could be avoided with a little more work + but for now we are content with it because the optimised + memcpy is quite fast */ + + memcpy(nic->packet, rxb + rxd_tail * BUFLEN, nic->packetlen); + + /* return the descriptor and buffer to receive ring */ + rxd[rxd_tail].status = 0x80000000; + rxd_tail++; + if (rxd_tail == NRXD) rxd_tail = 0; + + return 1; +} + +/*********************************************************************/ +/* eth_disable - Disable the interface */ +/*********************************************************************/ +static void davicom_disable ( struct nic *nic ) { + + whereami("davicom_disable\n"); + + davicom_reset(nic); + + /* disable interrupts */ + outl(0x00000000, ioaddr + CSR7); + + /* Stop the chip's Tx and Rx processes. */ + outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); + + /* Clear the missed-packet counter. */ + inl(ioaddr + CSR8); +} + + +/*********************************************************************/ +/* eth_irq - enable, disable and force interrupts */ +/*********************************************************************/ +static void davicom_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + + +/*********************************************************************/ +/* eth_probe - Look for an adapter */ +/*********************************************************************/ +static int davicom_probe ( struct nic *nic, struct pci_device *pci ) { + + unsigned int i; + + whereami("davicom_probe\n"); + + if (pci->ioaddr == 0) + return 0; + + vendor = pci->vendor; + dev_id = pci->device; + ioaddr = pci->ioaddr; + + nic->ioaddr = pci->ioaddr; + nic->irqno = 0; + + /* wakeup chip */ + pci_write_config_dword(pci, 0x40, 0x00000000); + + /* Stop the chip's Tx and Rx processes. */ + outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); + + /* Clear the missed-packet counter. */ + inl(ioaddr + CSR8); + + /* Get MAC Address */ + /* read EEPROM data */ + for (i = 0; i < sizeof(ee_data)/2; i++) + ((unsigned short *)ee_data)[i] = + le16_to_cpu(read_eeprom(ioaddr, i, EEPROM_ADDRLEN)); + + /* extract MAC address from EEPROM buffer */ + for (i=0; i<ETH_ALEN; i++) + nic->node_addr[i] = ee_data[20+i]; + + DBG ( "Davicom %s at IOADDR %4.4lx\n", eth_ntoa ( nic->node_addr ), ioaddr ); + + /* initialize device */ + davicom_reset(nic); + nic->nic_op = &davicom_operations; + return 1; +} + +static struct nic_operations davicom_operations = { + .connect = dummy_connect, + .poll = davicom_poll, + .transmit = davicom_transmit, + .irq = davicom_irq, + +}; + +static struct pci_device_id davicom_nics[] = { +PCI_ROM(0x1282, 0x9100, "davicom9100", "Davicom 9100", 0), +PCI_ROM(0x1282, 0x9102, "davicom9102", "Davicom 9102", 0), +PCI_ROM(0x1282, 0x9009, "davicom9009", "Davicom 9009", 0), +PCI_ROM(0x1282, 0x9132, "davicom9132", "Davicom 9132", 0), /* Needs probably some fixing */ +}; + +PCI_DRIVER ( davicom_driver, davicom_nics, PCI_NO_CLASS ); + +DRIVER ( "DAVICOM", nic_driver, pci_driver, davicom_driver, + davicom_probe, davicom_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/depca.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/depca.c new file mode 100644 index 0000000..ea85cbe --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/depca.c @@ -0,0 +1,805 @@ +/* #warning "depca.c: FIXME: fix relocation" */ + +FILE_LICENCE ( GPL_ANY ); + +#if 0 +/* Not fixed for relocation yet. Probably won't work relocated above 16MB */ +#ifdef ALLMULTI +#error multicast support is not yet implemented +#endif +/* Etherboot: depca.h merged, comments from Linux driver retained */ +/* depca.c: A DIGITAL DEPCA & EtherWORKS ethernet driver for linux. + + Written 1994, 1995 by David C. Davies. + + + Copyright 1994 David C. Davies + and + United States Government + (as represented by the Director, National Security Agency). + + Copyright 1995 Digital Equipment Corporation. + + + This software may be used and distributed according to the terms of + the GNU Public License, incorporated herein by reference. + + This driver is written for the Digital Equipment Corporation series + of DEPCA and EtherWORKS ethernet cards: + + DEPCA (the original) + DE100 + DE101 + DE200 Turbo + DE201 Turbo + DE202 Turbo (TP BNC) + DE210 + DE422 (EISA) + + The driver has been tested on DE100, DE200 and DE202 cards in a + relatively busy network. The DE422 has been tested a little. + + This driver will NOT work for the DE203, DE204 and DE205 series of + cards, since they have a new custom ASIC in place of the AMD LANCE + chip. See the 'ewrk3.c' driver in the Linux source tree for running + those cards. + + I have benchmarked the driver with a DE100 at 595kB/s to (542kB/s from) + a DECstation 5000/200. + + The author may be reached at davies@maniac.ultranet.com + + ========================================================================= + + The driver was originally based on the 'lance.c' driver from Donald + Becker which is included with the standard driver distribution for + linux. V0.4 is a complete re-write with only the kernel interface + remaining from the original code. + + 1) Lance.c code in /linux/drivers/net/ + 2) "Ethernet/IEEE 802.3 Family. 1992 World Network Data Book/Handbook", + AMD, 1992 [(800) 222-9323]. + 3) "Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)", + AMD, Pub. #17881, May 1993. + 4) "Am79C960 PCnet-ISA(tm), Single-Chip Ethernet Controller for ISA", + AMD, Pub. #16907, May 1992 + 5) "DEC EtherWORKS LC Ethernet Controller Owners Manual", + Digital Equipment corporation, 1990, Pub. #EK-DE100-OM.003 + 6) "DEC EtherWORKS Turbo Ethernet Controller Owners Manual", + Digital Equipment corporation, 1990, Pub. #EK-DE200-OM.003 + 7) "DEPCA Hardware Reference Manual", Pub. #EK-DEPCA-PR + Digital Equipment Corporation, 1989 + 8) "DEC EtherWORKS Turbo_(TP BNC) Ethernet Controller Owners Manual", + Digital Equipment corporation, 1991, Pub. #EK-DE202-OM.001 + + + Peter Bauer's depca.c (V0.5) was referred to when debugging V0.1 of this + driver. + + The original DEPCA card requires that the ethernet ROM address counter + be enabled to count and has an 8 bit NICSR. The ROM counter enabling is + only done when a 0x08 is read as the first address octet (to minimise + the chances of writing over some other hardware's I/O register). The + NICSR accesses have been changed to byte accesses for all the cards + supported by this driver, since there is only one useful bit in the MSB + (remote boot timeout) and it is not used. Also, there is a maximum of + only 48kB network RAM for this card. My thanks to Torbjorn Lindh for + help debugging all this (and holding my feet to the fire until I got it + right). + + The DE200 series boards have on-board 64kB RAM for use as a shared + memory network buffer. Only the DE100 cards make use of a 2kB buffer + mode which has not been implemented in this driver (only the 32kB and + 64kB modes are supported [16kB/48kB for the original DEPCA]). + + At the most only 2 DEPCA cards can be supported on the ISA bus because + there is only provision for two I/O base addresses on each card (0x300 + and 0x200). The I/O address is detected by searching for a byte sequence + in the Ethernet station address PROM at the expected I/O address for the + Ethernet PROM. The shared memory base address is 'autoprobed' by + looking for the self test PROM and detecting the card name. When a + second DEPCA is detected, information is placed in the base_addr + variable of the next device structure (which is created if necessary), + thus enabling ethif_probe initialization for the device. More than 2 + EISA cards can be supported, but care will be needed assigning the + shared memory to ensure that each slot has the correct IRQ, I/O address + and shared memory address assigned. + + ************************************************************************ + + NOTE: If you are using two ISA DEPCAs, it is important that you assign + the base memory addresses correctly. The driver autoprobes I/O 0x300 + then 0x200. The base memory address for the first device must be less + than that of the second so that the auto probe will correctly assign the + I/O and memory addresses on the same card. I can't think of a way to do + this unambiguously at the moment, since there is nothing on the cards to + tie I/O and memory information together. + + I am unable to test 2 cards together for now, so this code is + unchecked. All reports, good or bad, are welcome. + + ************************************************************************ + + The board IRQ setting must be at an unused IRQ which is auto-probed + using Donald Becker's autoprobe routines. DEPCA and DE100 board IRQs are + {2,3,4,5,7}, whereas the DE200 is at {5,9,10,11,15}. Note that IRQ2 is + really IRQ9 in machines with 16 IRQ lines. + + No 16MB memory limitation should exist with this driver as DMA is not + used and the common memory area is in low memory on the network card (my + current system has 20MB and I've not had problems yet). + + The ability to load this driver as a loadable module has been added. To + utilise this ability, you have to do <8 things: + + 0) have a copy of the loadable modules code installed on your system. + 1) copy depca.c from the /linux/drivers/net directory to your favourite + temporary directory. + 2) if you wish, edit the source code near line 1530 to reflect the I/O + address and IRQ you're using (see also 5). + 3) compile depca.c, but include -DMODULE in the command line to ensure + that the correct bits are compiled (see end of source code). + 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a + kernel with the depca configuration turned off and reboot. + 5) insmod depca.o [irq=7] [io=0x200] [mem=0xd0000] [adapter_name=DE100] + [Alan Cox: Changed the code to allow command line irq/io assignments] + [Dave Davies: Changed the code to allow command line mem/name + assignments] + 6) run the net startup bits for your eth?? interface manually + (usually /etc/rc.inet[12] at boot time). + 7) enjoy! + + Note that autoprobing is not allowed in loadable modules - the system is + already up and running and you're messing with interrupts. + + To unload a module, turn off the associated interface + 'ifconfig eth?? down' then 'rmmod depca'. + + To assign a base memory address for the shared memory when running as a + loadable module, see 5 above. To include the adapter name (if you have + no PROM but know the card name) also see 5 above. Note that this last + option will not work with kernel built-in depca's. + + The shared memory assignment for a loadable module makes sense to avoid + the 'memory autoprobe' picking the wrong shared memory (for the case of + 2 depca's in a PC). + + ************************************************************************ + Support for MCA EtherWORKS cards added 11-3-98. + Verified to work with up to 2 DE212 cards in a system (although not + fully stress-tested). + + Currently known bugs/limitations: + + Note: with the MCA stuff as a module, it trusts the MCA configuration, + not the command line for IRQ and memory address. You can + specify them if you want, but it will throw your values out. + You still have to pass the IO address it was configured as + though. + + ************************************************************************ + TO DO: + ------ + + + Revision History + ---------------- + + Version Date Description + + 0.1 25-jan-94 Initial writing. + 0.2 27-jan-94 Added LANCE TX hardware buffer chaining. + 0.3 1-feb-94 Added multiple DEPCA support. + 0.31 4-feb-94 Added DE202 recognition. + 0.32 19-feb-94 Tidy up. Improve multi-DEPCA support. + 0.33 25-feb-94 Fix DEPCA ethernet ROM counter enable. + Add jabber packet fix from murf@perftech.com + and becker@super.org + 0.34 7-mar-94 Fix DEPCA max network memory RAM & NICSR access. + 0.35 8-mar-94 Added DE201 recognition. Tidied up. + 0.351 30-apr-94 Added EISA support. Added DE422 recognition. + 0.36 16-may-94 DE422 fix released. + 0.37 22-jul-94 Added MODULE support + 0.38 15-aug-94 Added DBR ROM switch in depca_close(). + Multi DEPCA bug fix. + 0.38axp 15-sep-94 Special version for Alpha AXP Linux V1.0. + 0.381 12-dec-94 Added DE101 recognition, fix multicast bug. + 0.382 9-feb-95 Fix recognition bug reported by <bkm@star.rl.ac.uk>. + 0.383 22-feb-95 Fix for conflict with VESA SCSI reported by + <stromain@alf.dec.com> + 0.384 17-mar-95 Fix a ring full bug reported by <bkm@star.rl.ac.uk> + 0.385 3-apr-95 Fix a recognition bug reported by + <ryan.niemi@lastfrontier.com> + 0.386 21-apr-95 Fix the last fix...sorry, must be galloping senility + 0.40 25-May-95 Rewrite for portability & updated. + ALPHA support from <jestabro@amt.tay1.dec.com> + 0.41 26-Jun-95 Added verify_area() calls in depca_ioctl() from + suggestion by <heiko@colossus.escape.de> + 0.42 27-Dec-95 Add 'mem' shared memory assignment for loadable + modules. + Add 'adapter_name' for loadable modules when no PROM. + Both above from a suggestion by + <pchen@woodruffs121.residence.gatech.edu>. + Add new multicasting code. + 0.421 22-Apr-96 Fix alloc_device() bug <jari@markkus2.fimr.fi> + 0.422 29-Apr-96 Fix depca_hw_init() bug <jari@markkus2.fimr.fi> + 0.423 7-Jun-96 Fix module load bug <kmg@barco.be> + 0.43 16-Aug-96 Update alloc_device() to conform to de4x5.c + 0.44 1-Sep-97 Fix *_probe() to test check_region() first - bug + reported by <mmogilvi@elbert.uccs.edu> + 0.45 3-Nov-98 Added support for MCA EtherWORKS (DE210/DE212) cards + by <tymm@computer.org> + 0.451 5-Nov-98 Fixed mca stuff cuz I'm a dummy. <tymm@computer.org> + 0.5 14-Nov-98 Re-spin for 2.1.x kernels. + 0.51 27-Jun-99 Correct received packet length for CRC from + report by <worm@dkik.dk> + + ========================================================================= +*/ + +#include "etherboot.h" +#include "nic.h" +#include <gpxe/isa.h> +#include "console.h" +#include <gpxe/ethernet.h> + +/* +** I/O addresses. Note that the 2k buffer option is not supported in +** this driver. +*/ +#define DEPCA_NICSR 0x00 /* Network interface CSR */ +#define DEPCA_RBI 0x02 /* RAM buffer index (2k buffer mode) */ +#define DEPCA_DATA 0x04 /* LANCE registers' data port */ +#define DEPCA_ADDR 0x06 /* LANCE registers' address port */ +#define DEPCA_HBASE 0x08 /* EISA high memory base address reg. */ +#define DEPCA_PROM 0x0c /* Ethernet address ROM data port */ +#define DEPCA_CNFG 0x0c /* EISA Configuration port */ +#define DEPCA_RBSA 0x0e /* RAM buffer starting address (2k buff.) */ + +/* +** These are LANCE registers addressable through nic->ioaddr + DEPCA_ADDR +*/ +#define CSR0 0 +#define CSR1 1 +#define CSR2 2 +#define CSR3 3 + +/* +** NETWORK INTERFACE CSR (NI_CSR) bit definitions +*/ + +#define TO 0x0100 /* Time Out for remote boot */ +#define SHE 0x0080 /* SHadow memory Enable */ +#define BS 0x0040 /* Bank Select */ +#define BUF 0x0020 /* BUFfer size (1->32k, 0->64k) */ +#define RBE 0x0010 /* Remote Boot Enable (1->net boot) */ +#define AAC 0x0008 /* Address ROM Address Counter (1->enable) */ +#define _128KB 0x0008 /* 128kB Network RAM (1->enable) */ +#define IM 0x0004 /* Interrupt Mask (1->mask) */ +#define IEN 0x0002 /* Interrupt tristate ENable (1->enable) */ +#define LED 0x0001 /* LED control */ + +/* +** Control and Status Register 0 (CSR0) bit definitions +*/ + +#define ERR 0x8000 /* Error summary */ +#define BABL 0x4000 /* Babble transmitter timeout error */ +#define CERR 0x2000 /* Collision Error */ +#define MISS 0x1000 /* Missed packet */ +#define MERR 0x0800 /* Memory Error */ +#define RINT 0x0400 /* Receiver Interrupt */ +#define TINT 0x0200 /* Transmit Interrupt */ +#define IDON 0x0100 /* Initialization Done */ +#define INTR 0x0080 /* Interrupt Flag */ +#define INEA 0x0040 /* Interrupt Enable */ +#define RXON 0x0020 /* Receiver on */ +#define TXON 0x0010 /* Transmitter on */ +#define TDMD 0x0008 /* Transmit Demand */ +#define STOP 0x0004 /* Stop */ +#define STRT 0x0002 /* Start */ +#define INIT 0x0001 /* Initialize */ +#define INTM 0xff00 /* Interrupt Mask */ +#define INTE 0xfff0 /* Interrupt Enable */ + +/* +** CONTROL AND STATUS REGISTER 3 (CSR3) +*/ + +#define BSWP 0x0004 /* Byte SWaP */ +#define ACON 0x0002 /* ALE control */ +#define BCON 0x0001 /* Byte CONtrol */ + +/* +** Initialization Block Mode Register +*/ + +#define PROM 0x8000 /* Promiscuous Mode */ +#define EMBA 0x0080 /* Enable Modified Back-off Algorithm */ +#define INTL 0x0040 /* Internal Loopback */ +#define DRTY 0x0020 /* Disable Retry */ +#define COLL 0x0010 /* Force Collision */ +#define DTCR 0x0008 /* Disable Transmit CRC */ +#define LOOP 0x0004 /* Loopback */ +#define DTX 0x0002 /* Disable the Transmitter */ +#define DRX 0x0001 /* Disable the Receiver */ + +/* +** Receive Message Descriptor 1 (RMD1) bit definitions. +*/ + +#define R_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */ +#define R_ERR 0x4000 /* Error Summary */ +#define R_FRAM 0x2000 /* Framing Error */ +#define R_OFLO 0x1000 /* Overflow Error */ +#define R_CRC 0x0800 /* CRC Error */ +#define R_BUFF 0x0400 /* Buffer Error */ +#define R_STP 0x0200 /* Start of Packet */ +#define R_ENP 0x0100 /* End of Packet */ + +/* +** Transmit Message Descriptor 1 (TMD1) bit definitions. +*/ + +#define T_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */ +#define T_ERR 0x4000 /* Error Summary */ +#define T_ADD_FCS 0x2000 /* More the 1 retry needed to Xmit */ +#define T_MORE 0x1000 /* >1 retry to transmit packet */ +#define T_ONE 0x0800 /* 1 try needed to transmit the packet */ +#define T_DEF 0x0400 /* Deferred */ +#define T_STP 0x02000000 /* Start of Packet */ +#define T_ENP 0x01000000 /* End of Packet */ +#define T_FLAGS 0xff000000 /* TX Flags Field */ + +/* +** Transmit Message Descriptor 3 (TMD3) bit definitions. +*/ + +#define TMD3_BUFF 0x8000 /* BUFFer error */ +#define TMD3_UFLO 0x4000 /* UnderFLOw error */ +#define TMD3_RES 0x2000 /* REServed */ +#define TMD3_LCOL 0x1000 /* Late COLlision */ +#define TMD3_LCAR 0x0800 /* Loss of CARrier */ +#define TMD3_RTRY 0x0400 /* ReTRY error */ + +/* +** Ethernet PROM defines +*/ +#define PROBE_LENGTH 32 + +/* +** Set the number of Tx and Rx buffers. Ensure that the memory requested +** here is <= to the amount of shared memory set up by the board switches. +** The number of descriptors MUST BE A POWER OF 2. +** +** total_memory = NUM_RX_DESC*(8+RX_BUFF_SZ) + NUM_TX_DESC*(8+TX_BUFF_SZ) +*/ +#define NUM_RX_DESC 2 /* Number of RX descriptors */ +#define NUM_TX_DESC 2 /* Number of TX descriptors */ +#define RX_BUFF_SZ 1536 /* Buffer size for each Rx buffer */ +#define TX_BUFF_SZ 1536 /* Buffer size for each Tx buffer */ + +/* +** ISA Bus defines +*/ +#ifndef DEPCA_MODEL +#define DEPCA_MODEL DEPCA +#endif + +static enum { + DEPCA, DE100, DE101, DE200, DE201, DE202, DE210, DE212, DE422, unknown +} adapter = DEPCA_MODEL; + +/* +** Name <-> Adapter mapping +*/ + +static char *adapter_name[] = { + "DEPCA", + "DE100","DE101", + "DE200","DE201","DE202", + "DE210","DE212", + "DE422", + "" +}; + +#ifndef DEPCA_RAM_BASE +#define DEPCA_RAM_BASE 0xd0000 +#endif + +/* +** Memory Alignment. Each descriptor is 4 longwords long. To force a +** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and +** DESC_ALIGN. ALIGN aligns the start address of the private memory area +** and hence the RX descriptor ring's first entry. +*/ +#define ALIGN4 ((u32)4 - 1) /* 1 longword align */ +#define ALIGN8 ((u32)8 - 1) /* 2 longword (quadword) align */ +#define ALIGN ALIGN8 /* Keep the LANCE happy... */ + +/* +** The DEPCA Rx and Tx ring descriptors. +*/ +struct depca_rx_desc { + volatile s32 base; + s16 buf_length; /* This length is negative 2's complement! */ + s16 msg_length; /* This length is "normal". */ +}; + +struct depca_tx_desc { + volatile s32 base; + s16 length; /* This length is negative 2's complement! */ + s16 misc; /* Errors and TDR info */ +}; + +#define LA_MASK 0x0000ffff /* LANCE address mask for mapping network RAM + to LANCE memory address space */ + +/* +** The Lance initialization block, described in databook, in common memory. +*/ +struct depca_init { + u16 mode; /* Mode register */ + u8 phys_addr[ETH_ALEN]; /* Physical ethernet address */ + u8 mcast_table[8]; /* Multicast Hash Table. */ + u32 rx_ring; /* Rx ring base pointer & ring length */ + u32 tx_ring; /* Tx ring base pointer & ring length */ +}; + +struct depca_private { + struct depca_rx_desc *rx_ring; + struct depca_tx_desc *tx_ring; + struct depca_init init_block; /* Shadow init block */ + char *rx_memcpy[NUM_RX_DESC]; + char *tx_memcpy[NUM_TX_DESC]; + u32 bus_offset; /* ISA bus address offset */ + u32 sh_mem; /* address of shared mem */ + u32 dma_buffs; /* Rx & Tx buffer start */ + int rx_cur, tx_cur; /* Next free ring entry */ + int txRingMask, rxRingMask; + s32 rx_rlen, tx_rlen; + /* log2([rt]xRingMask+1) for the descriptors */ +}; + +static Address mem_start = DEPCA_RAM_BASE; +static Address mem_len, offset; +static struct depca_private lp; + +/* +** Miscellaneous defines... +*/ +#define STOP_DEPCA(ioaddr) \ + outw(CSR0, ioaddr + DEPCA_ADDR);\ + outw(STOP, ioaddr + DEPCA_DATA) + +/* Initialize the lance Rx and Tx descriptor rings. */ +static void depca_init_ring(struct nic *nic) +{ + int i; + u32 p; + + lp.rx_cur = lp.tx_cur = 0; + /* Initialize the base addresses and length of each buffer in the ring */ + for (i = 0; i <= lp.rxRingMask; i++) { + writel((p = lp.dma_buffs + i * RX_BUFF_SZ) | R_OWN, &lp.rx_ring[i].base); + writew(-RX_BUFF_SZ, &lp.rx_ring[i].buf_length); + lp.rx_memcpy[i] = (char *) (p + lp.bus_offset); + } + for (i = 0; i <= lp.txRingMask; i++) { + writel((p = lp.dma_buffs + (i + lp.txRingMask + 1) * TX_BUFF_SZ) & 0x00ffffff, &lp.tx_ring[i].base); + lp.tx_memcpy[i] = (char *) (p + lp.bus_offset); + } + + /* Set up the initialization block */ + lp.init_block.rx_ring = ((u32) ((u32) lp.rx_ring) & LA_MASK) | lp.rx_rlen; + lp.init_block.tx_ring = ((u32) ((u32) lp.tx_ring) & LA_MASK) | lp.tx_rlen; + for (i = 0; i < ETH_ALEN; i++) + lp.init_block.phys_addr[i] = nic->node_addr[i]; + lp.init_block.mode = 0x0000; /* Enable the Tx and Rx */ + memset(lp.init_block.mcast_table, 0, sizeof(lp.init_block.mcast_table)); +} + +static inline void LoadCSRs(struct nic *nic) +{ + outw(CSR1, nic->ioaddr + DEPCA_ADDR); /* initialisation block address LSW */ + outw((u16) (lp.sh_mem & LA_MASK), nic->ioaddr + DEPCA_DATA); + outw(CSR2, nic->ioaddr + DEPCA_ADDR); /* initialisation block address MSW */ + outw((u16) ((lp.sh_mem & LA_MASK) >> 16), nic->ioaddr + DEPCA_DATA); + outw(CSR3, nic->ioaddr + DEPCA_ADDR); /* ALE control */ + outw(ACON, nic->ioaddr + DEPCA_DATA); + outw(CSR0, nic->ioaddr + DEPCA_ADDR); /* Point back to CSR0 */ +} + +static inline int InitRestartDepca(struct nic *nic) +{ + int i; + + /* Copy the shadow init_block to shared memory */ + memcpy_toio((char *)lp.sh_mem, &lp.init_block, sizeof(struct depca_init)); + outw(CSR0, nic->ioaddr + DEPCA_ADDR); /* point back to CSR0 */ + outw(INIT, nic->ioaddr + DEPCA_DATA); /* initialise DEPCA */ + + for (i = 0; i < 100 && !(inw(nic->ioaddr + DEPCA_DATA) & IDON); i++) + ; + if (i < 100) { + /* clear IDON by writing a 1, and start LANCE */ + outw(IDON | STRT, nic->ioaddr + DEPCA_DATA); + } else { + printf("DEPCA not initialised\n"); + return (1); + } + return (0); +} + +/************************************************************************** +RESET - Reset adapter +***************************************************************************/ +static void depca_reset(struct nic *nic) +{ + s16 nicsr; + int i, j; + + STOP_DEPCA(nic->ioaddr); + nicsr = inb(nic->ioaddr + DEPCA_NICSR); + nicsr = ((nicsr & ~SHE & ~RBE & ~IEN) | IM); + outb(nicsr, nic->ioaddr + DEPCA_NICSR); + if (inw(nic->ioaddr + DEPCA_DATA) != STOP) + { + printf("depca: Cannot stop NIC\n"); + return; + } + + /* Initialisation block */ + lp.sh_mem = mem_start; + mem_start += sizeof(struct depca_init); + /* Tx & Rx descriptors (aligned to a quadword boundary) */ + mem_start = (mem_start + ALIGN) & ~ALIGN; + lp.rx_ring = (struct depca_rx_desc *) mem_start; + mem_start += (sizeof(struct depca_rx_desc) * NUM_RX_DESC); + lp.tx_ring = (struct depca_tx_desc *) mem_start; + mem_start += (sizeof(struct depca_tx_desc) * NUM_TX_DESC); + + lp.bus_offset = mem_start & 0x00ff0000; + /* LANCE re-mapped start address */ + lp.dma_buffs = mem_start & LA_MASK; + + /* Finish initialising the ring information. */ + lp.rxRingMask = NUM_RX_DESC - 1; + lp.txRingMask = NUM_TX_DESC - 1; + + /* Calculate Tx/Rx RLEN size for the descriptors. */ + for (i = 0, j = lp.rxRingMask; j > 0; i++) { + j >>= 1; + } + lp.rx_rlen = (s32) (i << 29); + for (i = 0, j = lp.txRingMask; j > 0; i++) { + j >>= 1; + } + lp.tx_rlen = (s32) (i << 29); + + /* Load the initialisation block */ + depca_init_ring(nic); + LoadCSRs(nic); + InitRestartDepca(nic); +} + +/************************************************************************** +POLL - Wait for a frame +***************************************************************************/ +static int depca_poll(struct nic *nic, int retrieve) +{ + int entry; + u32 status; + + entry = lp.rx_cur; + if ((status = readl(&lp.rx_ring[entry].base) & R_OWN)) + return (0); + + if ( ! retrieve ) return 1; + + memcpy(nic->packet, lp.rx_memcpy[entry], nic->packetlen = lp.rx_ring[entry].msg_length); + lp.rx_ring[entry].base |= R_OWN; + lp.rx_cur = (++lp.rx_cur) & lp.rxRingMask; + return (1); +} + +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static void depca_transmit( + struct nic *nic, + const char *d, /* Destination */ + unsigned int t, /* Type */ + unsigned int s, /* size */ + const char *p) /* Packet */ +{ + int entry, len; + char *mem; + + /* send the packet to destination */ + /* + ** Caution: the right order is important here... dont + ** setup the ownership rights until all the other + ** information is in place + */ + mem = lp.tx_memcpy[entry = lp.tx_cur]; + memcpy_toio(mem, d, ETH_ALEN); + memcpy_toio(mem + ETH_ALEN, nic->node_addr, ETH_ALEN); + mem[ETH_ALEN * 2] = t >> 8; + mem[ETH_ALEN * 2 + 1] = t; + memcpy_toio(mem + ETH_HLEN, p, s); + s += ETH_HLEN; + len = (s < ETH_ZLEN ? ETH_ZLEN : s); + /* clean out flags */ + writel(readl(&lp.tx_ring[entry].base) & ~T_FLAGS, &lp.tx_ring[entry].base); + /* clears other error flags */ + writew(0x0000, &lp.tx_ring[entry].misc); + /* packet length in buffer */ + writew(-len, &lp.tx_ring[entry].length); + /* start and end of packet, ownership */ + writel(readl(&lp.tx_ring[entry].base) | (T_STP|T_ENP|T_OWN), &lp.tx_ring[entry].base); + /* update current pointers */ + lp.tx_cur = (++lp.tx_cur) & lp.txRingMask; +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void depca_disable ( struct nic *nic ) { + depca_reset(nic); + + STOP_DEPCA(nic->ioaddr); +} + +/************************************************************************** +IRQ - Interrupt Control +***************************************************************************/ +static void depca_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + +/* +** Look for a special sequence in the Ethernet station address PROM that +** is common across all DEPCA products. Note that the original DEPCA needs +** its ROM address counter to be initialized and enabled. Only enable +** if the first address octet is a 0x08 - this minimises the chances of +** messing around with some other hardware, but it assumes that this DEPCA +** card initialized itself correctly. +** +** Search the Ethernet address ROM for the signature. Since the ROM address +** counter can start at an arbitrary point, the search must include the entire +** probe sequence length plus the (length_of_the_signature - 1). +** Stop the search IMMEDIATELY after the signature is found so that the +** PROM address counter is correctly positioned at the start of the +** ethernet address for later read out. +*/ + + +/* + * Ugly, ugly, ugly. I can't quite make out where the split should be + * between probe1 and probe()... + * + */ +static u8 nicsr; + + +static int depca_probe1 ( isa_probe_addr_t ioaddr ) { + u8 data; + /* This is only correct for little endian machines, but then + Etherboot doesn't work on anything but a PC */ + u8 sig[] = { 0xFF, 0x00, 0x55, 0xAA, 0xFF, 0x00, 0x55, 0xAA }; + int i, j; + + data = inb(ioaddr + DEPCA_PROM); /* clear counter on DEPCA */ + data = inb(ioaddr + DEPCA_PROM); /* read data */ + if (data == 0x8) { + nicsr = inb(ioaddr + DEPCA_NICSR); + nicsr |= AAC; + outb(nicsr, ioaddr + DEPCA_NICSR); + } + for (i = 0, j = 0; j < (int)sizeof(sig) && i < PROBE_LENGTH+((int)sizeof(sig))-1; ++i) { + data = inb(ioaddr + DEPCA_PROM); + if (data == sig[j]) /* track signature */ + ++j; + else + j = (data == sig[0]) ? 1 : 0; + } + if (j != sizeof(sig)) + return (0); + /* put the card in its initial state */ + STOP_DEPCA(ioaddr); + nicsr = ((inb(ioaddr + DEPCA_NICSR) & ~SHE & ~RBE & ~IEN) | IM); + outb(nicsr, ioaddr + DEPCA_NICSR); + if (inw(ioaddr + DEPCA_DATA) != STOP) + return (0); + memcpy((char *)mem_start, sig, sizeof(sig)); + if (memcmp((char *)mem_start, sig, sizeof(sig)) != 0) + return (0); + + return 1; +} + +static struct nic_operations depca_operations = { + .connect = dummy_connect, + .poll = depca_poll, + .transmit = depca_transmit, + .irq = depca_irq, + +}; + +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +***************************************************************************/ +static int depca_probe ( struct nic *nic, struct isa_device *isa ) { + + int i, j; + long sum, chksum; + + nic->irqno = 0; + nic->ioaddr = isa->ioaddr; + + for (i = 0, j = 0, sum = 0; j < 3; j++) { + sum <<= 1; + if (sum > 0xFFFF) + sum -= 0xFFFF; + sum += (u8)(nic->node_addr[i++] = inb(nic->ioaddr + DEPCA_PROM)); + sum += (u16)((nic->node_addr[i++] = inb(nic->ioaddr + DEPCA_PROM)) << 8); + if (sum > 0xFFFF) + sum -= 0xFFFF; + } + if (sum == 0xFFFF) + sum = 0; + chksum = (u8)inb(nic->ioaddr + DEPCA_PROM); + chksum |= (u16)(inb(nic->ioaddr + DEPCA_PROM) << 8); + mem_len = (adapter == DEPCA) ? (48 << 10) : (64 << 10); + offset = 0; + if (nicsr & BUF) { + offset = 0x8000; + nicsr &= ~BS; + mem_len -= (32 << 10); + } + if (adapter != DEPCA) /* enable shadow RAM */ + outb(nicsr |= SHE, nic->ioaddr + DEPCA_NICSR); + DBG ( "%s base %4.4x, memory [%4.4lx-%4.4lx] addr %s", + adapter_name[adapter], nic->ioaddr, mem_start, + mem_start + mem_len, eth_ntoa ( nic->node_addr ) ); + if (sum != chksum) + printf(" (bad checksum)"); + putchar('\n'); + + depca_reset(nic); + + /* point to NIC specific routines */ + nic->nic_op = &depca_operations; + return 1; +} + +static isa_probe_addr_t depca_probe_addrs[] = { + 0x300, 0x200, +}; + +ISA_DRIVER ( depca_driver, depca_probe_addrs, depca_probe1, + GENERIC_ISAPNP_VENDOR, 0x80f7 ); + +DRIVER ( "depce", nic_driver, isa_driver, depca_driver, + depca_probe, depca_disable ); + +ISA_ROM ( "depca", "Digital DE100 and DE200" ); + +#endif + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/dmfe.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/dmfe.c new file mode 100644 index 0000000..8d79158 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/dmfe.c @@ -0,0 +1,1226 @@ +/************************************************************************** +* +* dmfe.c -- Etherboot device driver for the Davicom +* DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast ethernet card +* +* Written 2003-2003 by Timothy Legge <tlegge@rogers.com> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +* +* Portions of this code based on: +* +* dmfe.c: A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 +* NIC fast ethernet driver for Linux. +* Copyright (C) 1997 Sten Wang +* (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. +* +* +* REVISION HISTORY: +* ================ +* v1.0 10-02-2004 timlegge Boots ltsp needs cleanup +* +* Indent Options: indent -kr -i8 +* +* +***************************************************************************/ + +FILE_LICENCE ( GPL2_OR_LATER ); + +/* to get some global routines like printf */ +#include "etherboot.h" +/* to get the interface to the body of the program */ +#include "nic.h" +/* to get the PCI support functions, if this is a PCI NIC */ +#include <gpxe/pci.h> +#include <gpxe/ethernet.h> + +/* #define EDEBUG 1 */ +#ifdef EDEBUG +#define dprintf(x) printf x +#else +#define dprintf(x) +#endif + +/* Condensed operations for readability. */ +#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) +#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) + +/* Board/System/Debug information/definition ---------------- */ +#define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */ +#define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */ +#define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */ +#define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */ + +#define DM9102_IO_SIZE 0x80 +#define DM9102A_IO_SIZE 0x100 +#define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */ +#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */ +#define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */ +#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */ +#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */ +#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT) +#define TX_BUF_ALLOC 0x600 +#define RX_ALLOC_SIZE 0x620 +#define DM910X_RESET 1 +#define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */ +#define CR6_DEFAULT 0x00080000 /* HD */ +#define CR7_DEFAULT 0x180c1 +#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */ +#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */ +#define MAX_PACKET_SIZE 1514 +#define DMFE_MAX_MULTICAST 14 +#define RX_COPY_SIZE 100 +#define MAX_CHECK_PACKET 0x8000 +#define DM9801_NOISE_FLOOR 8 +#define DM9802_NOISE_FLOOR 5 + +#define DMFE_10MHF 0 +#define DMFE_100MHF 1 +#define DMFE_10MFD 4 +#define DMFE_100MFD 5 +#define DMFE_AUTO 8 +#define DMFE_1M_HPNA 0x10 + +#define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */ +#define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */ +#define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */ +#define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */ +#define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */ +#define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */ + +#define DMFE_TIMER_WUT (jiffies + HZ * 1) /* timer wakeup time : 1 second */ +#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */ +#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */ + +#define DMFE_DBUG(dbug_now, msg, value) if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value)) + +#define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half"); + + +/* CR9 definition: SROM/MII */ +#define CR9_SROM_READ 0x4800 +#define CR9_SRCS 0x1 +#define CR9_SRCLK 0x2 +#define CR9_CRDOUT 0x8 +#define SROM_DATA_0 0x0 +#define SROM_DATA_1 0x4 +#define PHY_DATA_1 0x20000 +#define PHY_DATA_0 0x00000 +#define MDCLKH 0x10000 + +#define PHY_POWER_DOWN 0x800 + +#define SROM_V41_CODE 0x14 + +#define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5); + +#define __CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE +#define CHK_IO_SIZE(pci_dev, dev_rev) __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev) + +/* Sten Check */ +#define DEVICE net_device + +/* Structure/enum declaration ------------------------------- */ +struct tx_desc { + u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */ + void * tx_buf_ptr; /* Data for us */ + struct tx_desc * next_tx_desc; +} __attribute__ ((aligned(32))); + +struct rx_desc { + u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */ + void * rx_skb_ptr; /* Data for us */ + struct rx_desc * next_rx_desc; +} __attribute__ ((aligned(32))); + +static struct dmfe_private { + u32 chip_id; /* Chip vendor/Device ID */ + u32 chip_revision; /* Chip revision */ + u32 cr0_data; +// u32 cr5_data; + u32 cr6_data; + u32 cr7_data; + u32 cr15_data; + + u16 HPNA_command; /* For HPNA register 16 */ + u16 HPNA_timer; /* For HPNA remote device check */ + u16 NIC_capability; /* NIC media capability */ + u16 PHY_reg4; /* Saved Phyxcer register 4 value */ + + u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */ + u8 chip_type; /* Keep DM9102A chip type */ + u8 media_mode; /* user specify media mode */ + u8 op_mode; /* real work media mode */ + u8 phy_addr; + u8 dm910x_chk_mode; /* Operating mode check */ + + /* NIC SROM data */ + unsigned char srom[128]; + /* Etherboot Only */ + u8 cur_tx; + u8 cur_rx; +} dfx; + +static struct dmfe_private *db; + +enum dmfe_offsets { + DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20, + DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48, + DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = + 0x70, + DCR15 = 0x78 +}; + +enum dmfe_CR6_bits { + CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80, + CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000, + CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000 +}; + +/* Global variable declaration ----------------------------- */ +static struct nic_operations dmfe_operations; + +static unsigned char dmfe_media_mode = DMFE_AUTO; +static u32 dmfe_cr6_user_set; + +/* For module input parameter */ +static u8 chkmode = 1; +static u8 HPNA_mode; /* Default: Low Power/High Speed */ +static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */ +static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */ +static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */ +static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control + 4: TX pause packet */ + + +/********************************************** +* Descriptor Ring and Buffer defination +***********************************************/ +struct { + struct tx_desc txd[TX_DESC_CNT] __attribute__ ((aligned(32))); + unsigned char txb[TX_BUF_ALLOC * TX_DESC_CNT] + __attribute__ ((aligned(32))); + struct rx_desc rxd[RX_DESC_CNT] __attribute__ ((aligned(32))); + unsigned char rxb[RX_ALLOC_SIZE * RX_DESC_CNT] + __attribute__ ((aligned(32))); +} dmfe_bufs __shared; +#define txd dmfe_bufs.txd +#define txb dmfe_bufs.txb +#define rxd dmfe_bufs.rxd +#define rxb dmfe_bufs.rxb + +/* NIC specific static variables go here */ +static long int BASE; + +static u16 read_srom_word(long ioaddr, int offset); +static void dmfe_init_dm910x(struct nic *nic); +static void dmfe_descriptor_init(struct nic *, unsigned long ioaddr); +static void update_cr6(u32, unsigned long); +static void send_filter_frame(struct nic *nic); +static void dm9132_id_table(struct nic *nic); + +static u16 phy_read(unsigned long, u8, u8, u32); +static void phy_write(unsigned long, u8, u8, u16, u32); +static void phy_write_1bit(unsigned long, u32); +static u16 phy_read_1bit(unsigned long); +static void dmfe_set_phyxcer(struct nic *nic); + +static void dmfe_parse_srom(struct nic *nic); +static void dmfe_program_DM9801(struct nic *nic, int); +static void dmfe_program_DM9802(struct nic *nic); + +static void dmfe_reset(struct nic *nic) +{ + /* system variable init */ + db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set; + + db->NIC_capability = 0xf; /* All capability */ + db->PHY_reg4 = 0x1e0; + + /* CR6 operation mode decision */ + if (!chkmode || (db->chip_id == PCI_DM9132_ID) || + (db->chip_revision >= 0x02000030)) { + db->cr6_data |= DMFE_TXTH_256; + db->cr0_data = CR0_DEFAULT; + db->dm910x_chk_mode = 4; /* Enter the normal mode */ + } else { + db->cr6_data |= CR6_SFT; /* Store & Forward mode */ + db->cr0_data = 0; + db->dm910x_chk_mode = 1; /* Enter the check mode */ + } + /* Initilize DM910X board */ + dmfe_init_dm910x(nic); + + return; +} + +/* Initilize DM910X board + * Reset DM910X board + * Initilize TX/Rx descriptor chain structure + * Send the set-up frame + * Enable Tx/Rx machine + */ + +static void dmfe_init_dm910x(struct nic *nic) +{ + unsigned long ioaddr = BASE; + + /* Reset DM910x MAC controller */ + outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */ + udelay(100); + outl(db->cr0_data, ioaddr + DCR0); + udelay(5); + + /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */ + db->phy_addr = 1; + + /* Parser SROM and media mode */ + dmfe_parse_srom(nic); + db->media_mode = dmfe_media_mode; + + /* RESET Phyxcer Chip by GPR port bit 7 */ + outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */ + if (db->chip_id == PCI_DM9009_ID) { + outl(0x80, ioaddr + DCR12); /* Issue RESET signal */ + mdelay(300); /* Delay 300 ms */ + } + outl(0x0, ioaddr + DCR12); /* Clear RESET signal */ + + /* Process Phyxcer Media Mode */ + if (!(db->media_mode & 0x10)) /* Force 1M mode */ + dmfe_set_phyxcer(nic); + + /* Media Mode Process */ + if (!(db->media_mode & DMFE_AUTO)) + db->op_mode = db->media_mode; /* Force Mode */ + + /* Initiliaze Transmit/Receive decriptor and CR3/4 */ + dmfe_descriptor_init(nic, ioaddr); + + /* tx descriptor start pointer */ + outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */ + + /* rx descriptor start pointer */ + outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */ + + /* Init CR6 to program DM910x operation */ + update_cr6(db->cr6_data, ioaddr); + + /* Send setup frame */ + if (db->chip_id == PCI_DM9132_ID) { + dm9132_id_table(nic); /* DM9132 */ + } else { + send_filter_frame(nic); /* DM9102/DM9102A */ + } + + /* Init CR7, interrupt active bit */ + db->cr7_data = CR7_DEFAULT; + outl(db->cr7_data, ioaddr + DCR7); + /* Init CR15, Tx jabber and Rx watchdog timer */ + outl(db->cr15_data, ioaddr + DCR15); + /* Enable DM910X Tx/Rx function */ + db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000; + update_cr6(db->cr6_data, ioaddr); +} +#ifdef EDEBUG +void hex_dump(const char *data, const unsigned int len); +#endif +/************************************************************************** +POLL - Wait for a frame +***************************************************************************/ +static int dmfe_poll(struct nic *nic, int retrieve) +{ + u32 rdes0; + int entry = db->cur_rx % RX_DESC_CNT; + int rxlen; + rdes0 = le32_to_cpu(rxd[entry].rdes0); + if (rdes0 & 0x80000000) + return 0; + + if (!retrieve) + return 1; + + if ((rdes0 & 0x300) != 0x300) { + /* A packet without First/Last flag */ + printf("strange Packet\n"); + rxd[entry].rdes0 = cpu_to_le32(0x80000000); + return 0; + } else { + /* A packet with First/Last flag */ + rxlen = ((rdes0 >> 16) & 0x3fff) - 4; + /* error summary bit check */ + if (rdes0 & 0x8000) { + printf("Error\n"); + return 0; + } + if (!(rdes0 & 0x8000) || + ((db->cr6_data & CR6_PM) && (rxlen > 6))) { + if (db->dm910x_chk_mode & 1) + printf("Silly check mode\n"); + + nic->packetlen = rxlen; + memcpy(nic->packet, rxb + (entry * RX_ALLOC_SIZE), + nic->packetlen); + } + } + rxd[entry].rdes0 = cpu_to_le32(0x80000000); + db->cur_rx++; + return 1; +} + +static void dmfe_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static void dmfe_transmit(struct nic *nic, + const char *dest, /* Destination */ + unsigned int type, /* Type */ + unsigned int size, /* size */ + const char *packet) /* Packet */ +{ + u16 nstype; + u8 *ptxb; + + ptxb = &txb[db->cur_tx]; + + /* Stop Tx */ + outl(0, BASE + DCR7); + memcpy(ptxb, dest, ETH_ALEN); + memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN); + nstype = htons((u16) type); + memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2); + memcpy(ptxb + ETH_HLEN, packet, size); + + size += ETH_HLEN; + while (size < ETH_ZLEN) + ptxb[size++] = '\0'; + + /* setup the transmit descriptor */ + txd[db->cur_tx].tdes1 = cpu_to_le32(0xe1000000 | size); + txd[db->cur_tx].tdes0 = cpu_to_le32(0x80000000); /* give ownership to device */ + + /* immediate transmit demand */ + outl(0x1, BASE + DCR1); + outl(db->cr7_data, BASE + DCR7); + + /* Point to next TX descriptor */ + db->cur_tx++; + db->cur_tx = db->cur_tx % TX_DESC_CNT; +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void dmfe_disable ( struct nic *nic __unused ) { + /* Reset & stop DM910X board */ + outl(DM910X_RESET, BASE + DCR0); + udelay(5); + phy_write(BASE, db->phy_addr, 0, 0x8000, db->chip_id); + +} + +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +***************************************************************************/ + +#define board_found 1 +#define valid_link 0 +static int dmfe_probe ( struct nic *nic, struct pci_device *pci ) { + + uint32_t dev_rev, pci_pmr; + int i; + + if (pci->ioaddr == 0) + return 0; + + BASE = pci->ioaddr; + printf("dmfe.c: Vendor=0x%hX Device=0x%hX\n", + pci->vendor, pci->device); + + /* Read Chip revision */ + pci_read_config_dword(pci, PCI_REVISION_ID, &dev_rev); + dprintf(("Revision %lX\n", dev_rev)); + + /* point to private storage */ + db = &dfx; + + db->chip_id = ((u32) pci->device << 16) | pci->vendor; + BASE = pci_bar_start(pci, PCI_BASE_ADDRESS_0); + db->chip_revision = dev_rev; + + pci_read_config_dword(pci, 0x50, &pci_pmr); + pci_pmr &= 0x70000; + if ((pci_pmr == 0x10000) && (dev_rev == 0x02000031)) + db->chip_type = 1; /* DM9102A E3 */ + else + db->chip_type = 0; + + dprintf(("Chip type : %d\n", db->chip_type)); + + /* read 64 word srom data */ + for (i = 0; i < 64; i++) + ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(BASE, i)); + + /* Set Node address */ + for (i = 0; i < 6; i++) + nic->node_addr[i] = db->srom[20 + i]; + + /* Print out some hardware info */ + DBG ( "%s: at ioaddr %4.4lx\n", eth_ntoa ( nic->node_addr ), BASE ); + + /* Set the card as PCI Bus Master */ + adjust_pci_device(pci); + + dmfe_reset(nic); + + nic->irqno = 0; + nic->ioaddr = pci->ioaddr; + + /* point to NIC specific routines */ + nic->nic_op = &dmfe_operations; + + return 1; +} + +/* + * Initialize transmit/Receive descriptor + * Using Chain structure, and allocate Tx/Rx buffer + */ + +static void dmfe_descriptor_init(struct nic *nic __unused, unsigned long ioaddr) +{ + int i; + db->cur_tx = 0; + db->cur_rx = 0; + + /* tx descriptor start pointer */ + outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */ + + /* rx descriptor start pointer */ + outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */ + + /* Init Transmit chain */ + for (i = 0; i < TX_DESC_CNT; i++) { + txd[i].tx_buf_ptr = &txb[i]; + txd[i].tdes0 = cpu_to_le32(0); + txd[i].tdes1 = cpu_to_le32(0x81000000); /* IC, chain */ + txd[i].tdes2 = cpu_to_le32(virt_to_bus(&txb[i])); + txd[i].tdes3 = cpu_to_le32(virt_to_bus(&txd[i + 1])); + txd[i].next_tx_desc = &txd[i + 1]; + } + /* Mark the last entry as wrapping the ring */ + txd[i - 1].tdes3 = virt_to_le32desc(&txd[0]); + txd[i - 1].next_tx_desc = &txd[0]; + + /* receive descriptor chain */ + for (i = 0; i < RX_DESC_CNT; i++) { + rxd[i].rx_skb_ptr = &rxb[i * RX_ALLOC_SIZE]; + rxd[i].rdes0 = cpu_to_le32(0x80000000); + rxd[i].rdes1 = cpu_to_le32(0x01000600); + rxd[i].rdes2 = + cpu_to_le32(virt_to_bus(&rxb[i * RX_ALLOC_SIZE])); + rxd[i].rdes3 = cpu_to_le32(virt_to_bus(&rxd[i + 1])); + rxd[i].next_rx_desc = &rxd[i + 1]; + } + /* Mark the last entry as wrapping the ring */ + rxd[i - 1].rdes3 = cpu_to_le32(virt_to_bus(&rxd[0])); + rxd[i - 1].next_rx_desc = &rxd[0]; + +} + +/* + * Update CR6 value + * Firstly stop DM910X , then written value and start + */ + +static void update_cr6(u32 cr6_data, unsigned long ioaddr) +{ + u32 cr6_tmp; + + cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */ + outl(cr6_tmp, ioaddr + DCR6); + udelay(5); + outl(cr6_data, ioaddr + DCR6); + udelay(5); +} + + +/* + * Send a setup frame for DM9132 + * This setup frame initilize DM910X addres filter mode +*/ + +static void dm9132_id_table(struct nic *nic __unused) +{ +#ifdef LINUX + u16 *addrptr; + u8 dmi_addr[8]; + unsigned long ioaddr = BASE + 0xc0; /* ID Table */ + u32 hash_val; + u16 i, hash_table[4]; +#endif + dprintf(("dm9132_id_table\n")); + + printf("FIXME: This function is broken. If you have this card contact " + "Timothy Legge at the etherboot-user list\n"); + +#ifdef LINUX + //DMFE_DBUG(0, "dm9132_id_table()", 0); + + /* Node address */ + addrptr = (u16 *) nic->node_addr; + outw(addrptr[0], ioaddr); + ioaddr += 4; + outw(addrptr[1], ioaddr); + ioaddr += 4; + outw(addrptr[2], ioaddr); + ioaddr += 4; + + /* Clear Hash Table */ + for (i = 0; i < 4; i++) + hash_table[i] = 0x0; + + /* broadcast address */ + hash_table[3] = 0x8000; + + /* the multicast address in Hash Table : 64 bits */ + for (mcptr = mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { + hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f; + hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); + } + + /* Write the hash table to MAC MD table */ + for (i = 0; i < 4; i++, ioaddr += 4) + outw(hash_table[i], ioaddr); +#endif +} + + +/* + * Send a setup frame for DM9102/DM9102A + * This setup frame initilize DM910X addres filter mode + */ + +static void send_filter_frame(struct nic *nic) +{ + + u8 *ptxb; + int i; + + dprintf(("send_filter_frame\n")); + /* point to the current txb incase multiple tx_rings are used */ + ptxb = &txb[db->cur_tx]; + + /* construct perfect filter frame with mac address as first match + and broadcast address for all others */ + for (i = 0; i < 192; i++) + ptxb[i] = 0xFF; + ptxb[0] = nic->node_addr[0]; + ptxb[1] = nic->node_addr[1]; + ptxb[4] = nic->node_addr[2]; + ptxb[5] = nic->node_addr[3]; + ptxb[8] = nic->node_addr[4]; + ptxb[9] = nic->node_addr[5]; + + /* prepare the setup frame */ + txd[db->cur_tx].tdes1 = cpu_to_le32(0x890000c0); + txd[db->cur_tx].tdes0 = cpu_to_le32(0x80000000); + update_cr6(db->cr6_data | 0x2000, BASE); + outl(0x1, BASE + DCR1); /* Issue Tx polling */ + update_cr6(db->cr6_data, BASE); + db->cur_tx++; +} + +/* + * Read one word data from the serial ROM + */ + +static u16 read_srom_word(long ioaddr, int offset) +{ + int i; + u16 srom_data = 0; + long cr9_ioaddr = ioaddr + DCR9; + + outl(CR9_SROM_READ, cr9_ioaddr); + outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); + + /* Send the Read Command 110b */ + SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); + SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); + SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr); + + /* Send the offset */ + for (i = 5; i >= 0; i--) { + srom_data = + (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0; + SROM_CLK_WRITE(srom_data, cr9_ioaddr); + } + + outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); + + for (i = 16; i > 0; i--) { + outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr); + udelay(5); + srom_data = + (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 + : 0); + outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); + udelay(5); + } + + outl(CR9_SROM_READ, cr9_ioaddr); + return srom_data; +} + + +/* + * Auto sense the media mode + */ + +#if 0 /* not used */ +static u8 dmfe_sense_speed(struct nic *nic __unused) +{ + u8 ErrFlag = 0; + u16 phy_mode; + + /* CR6 bit18=0, select 10/100M */ + update_cr6((db->cr6_data & ~0x40000), BASE); + + phy_mode = phy_read(BASE, db->phy_addr, 1, db->chip_id); + phy_mode = phy_read(BASE, db->phy_addr, 1, db->chip_id); + + if ((phy_mode & 0x24) == 0x24) { + if (db->chip_id == PCI_DM9132_ID) /* DM9132 */ + phy_mode = + phy_read(BASE, db->phy_addr, 7, + db->chip_id) & 0xf000; + else /* DM9102/DM9102A */ + phy_mode = + phy_read(BASE, db->phy_addr, 17, + db->chip_id) & 0xf000; + /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */ + switch (phy_mode) { + case 0x1000: + db->op_mode = DMFE_10MHF; + break; + case 0x2000: + db->op_mode = DMFE_10MFD; + break; + case 0x4000: + db->op_mode = DMFE_100MHF; + break; + case 0x8000: + db->op_mode = DMFE_100MFD; + break; + default: + db->op_mode = DMFE_10MHF; + ErrFlag = 1; + break; + } + } else { + db->op_mode = DMFE_10MHF; + //DMFE_DBUG(0, "Link Failed :", phy_mode); + ErrFlag = 1; + } + + return ErrFlag; +} +#endif + +/* + * Set 10/100 phyxcer capability + * AUTO mode : phyxcer register4 is NIC capability + * Force mode: phyxcer register4 is the force media + */ + +static void dmfe_set_phyxcer(struct nic *nic __unused) +{ + u16 phy_reg; + + /* Select 10/100M phyxcer */ + db->cr6_data &= ~0x40000; + update_cr6(db->cr6_data, BASE); + + /* DM9009 Chip: Phyxcer reg18 bit12=0 */ + if (db->chip_id == PCI_DM9009_ID) { + phy_reg = + phy_read(BASE, db->phy_addr, 18, + db->chip_id) & ~0x1000; + phy_write(BASE, db->phy_addr, 18, phy_reg, db->chip_id); + } + + /* Phyxcer capability setting */ + phy_reg = phy_read(BASE, db->phy_addr, 4, db->chip_id) & ~0x01e0; + + if (db->media_mode & DMFE_AUTO) { + /* AUTO Mode */ + phy_reg |= db->PHY_reg4; + } else { + /* Force Mode */ + switch (db->media_mode) { + case DMFE_10MHF: + phy_reg |= 0x20; + break; + case DMFE_10MFD: + phy_reg |= 0x40; + break; + case DMFE_100MHF: + phy_reg |= 0x80; + break; + case DMFE_100MFD: + phy_reg |= 0x100; + break; + } + if (db->chip_id == PCI_DM9009_ID) + phy_reg &= 0x61; + } + + /* Write new capability to Phyxcer Reg4 */ + if (!(phy_reg & 0x01e0)) { + phy_reg |= db->PHY_reg4; + db->media_mode |= DMFE_AUTO; + } + phy_write(BASE, db->phy_addr, 4, phy_reg, db->chip_id); + + /* Restart Auto-Negotiation */ + if (db->chip_type && (db->chip_id == PCI_DM9102_ID)) + phy_write(BASE, db->phy_addr, 0, 0x1800, db->chip_id); + if (!db->chip_type) + phy_write(BASE, db->phy_addr, 0, 0x1200, db->chip_id); +} + + +/* + * Process op-mode + * AUTO mode : PHY controller in Auto-negotiation Mode + * Force mode: PHY controller in force mode with HUB + * N-way force capability with SWITCH + */ + +#if 0 /* not used */ +static void dmfe_process_mode(struct nic *nic __unused) +{ + u16 phy_reg; + + /* Full Duplex Mode Check */ + if (db->op_mode & 0x4) + db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */ + else + db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */ + + /* Transciver Selection */ + if (db->op_mode & 0x10) /* 1M HomePNA */ + db->cr6_data |= 0x40000; /* External MII select */ + else + db->cr6_data &= ~0x40000; /* Internal 10/100 transciver */ + + update_cr6(db->cr6_data, BASE); + + /* 10/100M phyxcer force mode need */ + if (!(db->media_mode & 0x18)) { + /* Forece Mode */ + phy_reg = phy_read(BASE, db->phy_addr, 6, db->chip_id); + if (!(phy_reg & 0x1)) { + /* parter without N-Way capability */ + phy_reg = 0x0; + switch (db->op_mode) { + case DMFE_10MHF: + phy_reg = 0x0; + break; + case DMFE_10MFD: + phy_reg = 0x100; + break; + case DMFE_100MHF: + phy_reg = 0x2000; + break; + case DMFE_100MFD: + phy_reg = 0x2100; + break; + } + phy_write(BASE, db->phy_addr, 0, phy_reg, + db->chip_id); + if (db->chip_type + && (db->chip_id == PCI_DM9102_ID)) + mdelay(20); + phy_write(BASE, db->phy_addr, 0, phy_reg, + db->chip_id); + } + } +} +#endif + +/* + * Write a word to Phy register + */ + +static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, + u16 phy_data, u32 chip_id) +{ + u16 i; + unsigned long ioaddr; + + if (chip_id == PCI_DM9132_ID) { + ioaddr = iobase + 0x80 + offset * 4; + outw(phy_data, ioaddr); + } else { + /* DM9102/DM9102A Chip */ + ioaddr = iobase + DCR9; + + /* Send 33 synchronization clock to Phy controller */ + for (i = 0; i < 35; i++) + phy_write_1bit(ioaddr, PHY_DATA_1); + + /* Send start command(01) to Phy */ + phy_write_1bit(ioaddr, PHY_DATA_0); + phy_write_1bit(ioaddr, PHY_DATA_1); + + /* Send write command(01) to Phy */ + phy_write_1bit(ioaddr, PHY_DATA_0); + phy_write_1bit(ioaddr, PHY_DATA_1); + + /* Send Phy addres */ + for (i = 0x10; i > 0; i = i >> 1) + phy_write_1bit(ioaddr, + phy_addr & i ? PHY_DATA_1 : + PHY_DATA_0); + + /* Send register addres */ + for (i = 0x10; i > 0; i = i >> 1) + phy_write_1bit(ioaddr, + offset & i ? PHY_DATA_1 : + PHY_DATA_0); + + /* written trasnition */ + phy_write_1bit(ioaddr, PHY_DATA_1); + phy_write_1bit(ioaddr, PHY_DATA_0); + + /* Write a word data to PHY controller */ + for (i = 0x8000; i > 0; i >>= 1) + phy_write_1bit(ioaddr, + phy_data & i ? PHY_DATA_1 : + PHY_DATA_0); + } +} + + +/* + * Read a word data from phy register + */ + +static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, + u32 chip_id) +{ + int i; + u16 phy_data; + unsigned long ioaddr; + + if (chip_id == PCI_DM9132_ID) { + /* DM9132 Chip */ + ioaddr = iobase + 0x80 + offset * 4; + phy_data = inw(ioaddr); + } else { + /* DM9102/DM9102A Chip */ + ioaddr = iobase + DCR9; + + /* Send 33 synchronization clock to Phy controller */ + for (i = 0; i < 35; i++) + phy_write_1bit(ioaddr, PHY_DATA_1); + + /* Send start command(01) to Phy */ + phy_write_1bit(ioaddr, PHY_DATA_0); + phy_write_1bit(ioaddr, PHY_DATA_1); + + /* Send read command(10) to Phy */ + phy_write_1bit(ioaddr, PHY_DATA_1); + phy_write_1bit(ioaddr, PHY_DATA_0); + + /* Send Phy addres */ + for (i = 0x10; i > 0; i = i >> 1) + phy_write_1bit(ioaddr, + phy_addr & i ? PHY_DATA_1 : + PHY_DATA_0); + + /* Send register addres */ + for (i = 0x10; i > 0; i = i >> 1) + phy_write_1bit(ioaddr, + offset & i ? PHY_DATA_1 : + PHY_DATA_0); + + /* Skip transition state */ + phy_read_1bit(ioaddr); + + /* read 16bit data */ + for (phy_data = 0, i = 0; i < 16; i++) { + phy_data <<= 1; + phy_data |= phy_read_1bit(ioaddr); + } + } + + return phy_data; +} + + +/* + * Write one bit data to Phy Controller + */ + +static void phy_write_1bit(unsigned long ioaddr, u32 phy_data) +{ + outl(phy_data, ioaddr); /* MII Clock Low */ + udelay(1); + outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ + udelay(1); + outl(phy_data, ioaddr); /* MII Clock Low */ + udelay(1); +} + + +/* + * Read one bit phy data from PHY controller + */ + +static u16 phy_read_1bit(unsigned long ioaddr) +{ + u16 phy_data; + + outl(0x50000, ioaddr); + udelay(1); + phy_data = (inl(ioaddr) >> 19) & 0x1; + outl(0x40000, ioaddr); + udelay(1); + + return phy_data; +} + + +/* + * Parser SROM and media mode + */ + +static void dmfe_parse_srom(struct nic *nic) +{ + unsigned char *srom = db->srom; + int dmfe_mode, tmp_reg; + + /* Init CR15 */ + db->cr15_data = CR15_DEFAULT; + + /* Check SROM Version */ + if (((int) srom[18] & 0xff) == SROM_V41_CODE) { + /* SROM V4.01 */ + /* Get NIC support media mode */ + db->NIC_capability = *(u16 *) (srom + 34); + db->PHY_reg4 = 0; + for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) { + switch (db->NIC_capability & tmp_reg) { + case 0x1: + db->PHY_reg4 |= 0x0020; + break; + case 0x2: + db->PHY_reg4 |= 0x0040; + break; + case 0x4: + db->PHY_reg4 |= 0x0080; + break; + case 0x8: + db->PHY_reg4 |= 0x0100; + break; + } + } + + /* Media Mode Force or not check */ + dmfe_mode = *((int *) srom + 34) & *((int *) srom + 36); + switch (dmfe_mode) { + case 0x4: + dmfe_media_mode = DMFE_100MHF; + break; /* 100MHF */ + case 0x2: + dmfe_media_mode = DMFE_10MFD; + break; /* 10MFD */ + case 0x8: + dmfe_media_mode = DMFE_100MFD; + break; /* 100MFD */ + case 0x100: + case 0x200: + dmfe_media_mode = DMFE_1M_HPNA; + break; /* HomePNA */ + } + + /* Special Function setting */ + /* VLAN function */ + if ((SF_mode & 0x1) || (srom[43] & 0x80)) + db->cr15_data |= 0x40; + + /* Flow Control */ + if ((SF_mode & 0x2) || (srom[40] & 0x1)) + db->cr15_data |= 0x400; + + /* TX pause packet */ + if ((SF_mode & 0x4) || (srom[40] & 0xe)) + db->cr15_data |= 0x9800; + } + + /* Parse HPNA parameter */ + db->HPNA_command = 1; + + /* Accept remote command or not */ + if (HPNA_rx_cmd == 0) + db->HPNA_command |= 0x8000; + + /* Issue remote command & operation mode */ + if (HPNA_tx_cmd == 1) + switch (HPNA_mode) { /* Issue Remote Command */ + case 0: + db->HPNA_command |= 0x0904; + break; + case 1: + db->HPNA_command |= 0x0a00; + break; + case 2: + db->HPNA_command |= 0x0506; + break; + case 3: + db->HPNA_command |= 0x0602; + break; + } else + switch (HPNA_mode) { /* Don't Issue */ + case 0: + db->HPNA_command |= 0x0004; + break; + case 1: + db->HPNA_command |= 0x0000; + break; + case 2: + db->HPNA_command |= 0x0006; + break; + case 3: + db->HPNA_command |= 0x0002; + break; + } + + /* Check DM9801 or DM9802 present or not */ + db->HPNA_present = 0; + update_cr6(db->cr6_data | 0x40000, BASE); + tmp_reg = phy_read(BASE, db->phy_addr, 3, db->chip_id); + if ((tmp_reg & 0xfff0) == 0xb900) { + /* DM9801 or DM9802 present */ + db->HPNA_timer = 8; + if (phy_read(BASE, db->phy_addr, 31, db->chip_id) == + 0x4404) { + /* DM9801 HomeRun */ + db->HPNA_present = 1; + dmfe_program_DM9801(nic, tmp_reg); + } else { + /* DM9802 LongRun */ + db->HPNA_present = 2; + dmfe_program_DM9802(nic); + } + } + +} + +/* + * Init HomeRun DM9801 + */ + +static void dmfe_program_DM9801(struct nic *nic __unused, int HPNA_rev) +{ + u32 reg17, reg25; + + if (!HPNA_NoiseFloor) + HPNA_NoiseFloor = DM9801_NOISE_FLOOR; + switch (HPNA_rev) { + case 0xb900: /* DM9801 E3 */ + db->HPNA_command |= 0x1000; + reg25 = phy_read(BASE, db->phy_addr, 24, db->chip_id); + reg25 = ((reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000; + reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id); + break; + case 0xb901: /* DM9801 E4 */ + reg25 = phy_read(BASE, db->phy_addr, 25, db->chip_id); + reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor; + reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id); + reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3; + break; + case 0xb902: /* DM9801 E5 */ + case 0xb903: /* DM9801 E6 */ + default: + db->HPNA_command |= 0x1000; + reg25 = phy_read(BASE, db->phy_addr, 25, db->chip_id); + reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5; + reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id); + reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor; + break; + } + phy_write(BASE, db->phy_addr, 16, db->HPNA_command, db->chip_id); + phy_write(BASE, db->phy_addr, 17, reg17, db->chip_id); + phy_write(BASE, db->phy_addr, 25, reg25, db->chip_id); +} + + +/* + * Init HomeRun DM9802 + */ + +static void dmfe_program_DM9802(struct nic *nic __unused) +{ + u32 phy_reg; + + if (!HPNA_NoiseFloor) + HPNA_NoiseFloor = DM9802_NOISE_FLOOR; + phy_write(BASE, db->phy_addr, 16, db->HPNA_command, db->chip_id); + phy_reg = phy_read(BASE, db->phy_addr, 25, db->chip_id); + phy_reg = (phy_reg & 0xff00) + HPNA_NoiseFloor; + phy_write(BASE, db->phy_addr, 25, phy_reg, db->chip_id); +} + +static struct nic_operations dmfe_operations = { + .connect = dummy_connect, + .poll = dmfe_poll, + .transmit = dmfe_transmit, + .irq = dmfe_irq, + +}; + +static struct pci_device_id dmfe_nics[] = { + PCI_ROM(0x1282, 0x9100, "dmfe9100", "Davicom 9100", 0), + PCI_ROM(0x1282, 0x9102, "dmfe9102", "Davicom 9102", 0), + PCI_ROM(0x1282, 0x9009, "dmfe9009", "Davicom 9009", 0), + PCI_ROM(0x1282, 0x9132, "dmfe9132", "Davicom 9132", 0), /* Needs probably some fixing */ +}; + +PCI_DRIVER ( dmfe_driver, dmfe_nics, PCI_NO_CLASS ); + +DRIVER ( "DMFE/PCI", nic_driver, pci_driver, dmfe_driver, + dmfe_probe, dmfe_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/eepro.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/eepro.c new file mode 100644 index 0000000..a248692 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/eepro.c @@ -0,0 +1,637 @@ +#ifdef ALLMULTI +#error multicast support is not yet implemented +#endif +/************************************************************************** +Etherboot - BOOTP/TFTP Bootstrap Program +Intel EEPRO/10 NIC driver for Etherboot +Adapted from Linux eepro.c from kernel 2.2.17 + +This board accepts a 32 pin EEPROM (29C256), however a test with a +27C010 shows that this EPROM also works in the socket, but it's not clear +how repeatably. The two top address pins appear to be held low, thus +the bottom 32kB of the 27C010 is visible in the CPU's address space. +To be sure you could put 4 copies of the code in the 27C010, then +it doesn't matter whether the extra lines are held low or high, just +hopefully not floating as CMOS chips don't like floating inputs. + +Be careful with seating the EPROM as the socket on my board actually +has 34 pins, the top row of 2 are not used. +***************************************************************************/ + +/* + + timlegge 2005-05-18 remove the relocation changes cards that + write directly to the hardware don't need it +*/ + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2, or (at + * your option) any later version. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include "etherboot.h" +#include <errno.h> +#include "nic.h" +#include <gpxe/isa.h> +#include <gpxe/ethernet.h> + +/* Different 82595 chips */ +#define LAN595 0 +#define LAN595TX 1 +#define LAN595FX 2 +#define LAN595FX_10ISA 3 + +#define SLOW_DOWN inb(0x80); + +/* The station (ethernet) address prefix, used for IDing the board. */ +#define SA_ADDR0 0x00 /* Etherexpress Pro/10 */ +#define SA_ADDR1 0xaa +#define SA_ADDR2 0x00 + +#define GetBit(x,y) ((x & (1<<y))>>y) + +/* EEPROM Word 0: */ +#define ee_PnP 0 /* Plug 'n Play enable bit */ +#define ee_Word1 1 /* Word 1? */ +#define ee_BusWidth 2 /* 8/16 bit */ +#define ee_FlashAddr 3 /* Flash Address */ +#define ee_FlashMask 0x7 /* Mask */ +#define ee_AutoIO 6 /* */ +#define ee_reserved0 7 /* =0! */ +#define ee_Flash 8 /* Flash there? */ +#define ee_AutoNeg 9 /* Auto Negotiation enabled? */ +#define ee_IO0 10 /* IO Address LSB */ +#define ee_IO0Mask 0x /*...*/ +#define ee_IO1 15 /* IO MSB */ + +/* EEPROM Word 1: */ +#define ee_IntSel 0 /* Interrupt */ +#define ee_IntMask 0x7 +#define ee_LI 3 /* Link Integrity 0= enabled */ +#define ee_PC 4 /* Polarity Correction 0= enabled */ +#define ee_TPE_AUI 5 /* PortSelection 1=TPE */ +#define ee_Jabber 6 /* Jabber prevention 0= enabled */ +#define ee_AutoPort 7 /* Auto Port Selection 1= Disabled */ +#define ee_SMOUT 8 /* SMout Pin Control 0= Input */ +#define ee_PROM 9 /* Flash EPROM / PROM 0=Flash */ +#define ee_reserved1 10 /* .. 12 =0! */ +#define ee_AltReady 13 /* Alternate Ready, 0=normal */ +#define ee_reserved2 14 /* =0! */ +#define ee_Duplex 15 + +/* Word2,3,4: */ +#define ee_IA5 0 /*bit start for individual Addr Byte 5 */ +#define ee_IA4 8 /*bit start for individual Addr Byte 5 */ +#define ee_IA3 0 /*bit start for individual Addr Byte 5 */ +#define ee_IA2 8 /*bit start for individual Addr Byte 5 */ +#define ee_IA1 0 /*bit start for individual Addr Byte 5 */ +#define ee_IA0 8 /*bit start for individual Addr Byte 5 */ + +/* Word 5: */ +#define ee_BNC_TPE 0 /* 0=TPE */ +#define ee_BootType 1 /* 00=None, 01=IPX, 10=ODI, 11=NDIS */ +#define ee_BootTypeMask 0x3 +#define ee_NumConn 3 /* Number of Connections 0= One or Two */ +#define ee_FlashSock 4 /* Presence of Flash Socket 0= Present */ +#define ee_PortTPE 5 +#define ee_PortBNC 6 +#define ee_PortAUI 7 +#define ee_PowerMgt 10 /* 0= disabled */ +#define ee_CP 13 /* Concurrent Processing */ +#define ee_CPMask 0x7 + +/* Word 6: */ +#define ee_Stepping 0 /* Stepping info */ +#define ee_StepMask 0x0F +#define ee_BoardID 4 /* Manucaturer Board ID, reserved */ +#define ee_BoardMask 0x0FFF + +/* Word 7: */ +#define ee_INT_TO_IRQ 0 /* int to IRQ Mapping = 0x1EB8 for Pro/10+ */ +#define ee_FX_INT2IRQ 0x1EB8 /* the _only_ mapping allowed for FX chips */ + +/*..*/ +#define ee_SIZE 0x40 /* total EEprom Size */ +#define ee_Checksum 0xBABA /* initial and final value for adding checksum */ + + +/* Card identification via EEprom: */ +#define ee_addr_vendor 0x10 /* Word offset for EISA Vendor ID */ +#define ee_addr_id 0x11 /* Word offset for Card ID */ +#define ee_addr_SN 0x12 /* Serial Number */ +#define ee_addr_CRC_8 0x14 /* CRC over last thee Bytes */ + + +#define ee_vendor_intel0 0x25 /* Vendor ID Intel */ +#define ee_vendor_intel1 0xD4 +#define ee_id_eepro10p0 0x10 /* ID for eepro/10+ */ +#define ee_id_eepro10p1 0x31 + +/* now this section could be used by both boards: the oldies and the ee10: + * ee10 uses tx buffer before of rx buffer and the oldies the inverse. + * (aris) + */ +#define RAM_SIZE 0x8000 + +#define RCV_HEADER 8 +#define RCV_DEFAULT_RAM 0x6000 +#define RCV_RAM rcv_ram + +static unsigned rcv_ram = RCV_DEFAULT_RAM; + +#define XMT_HEADER 8 +#define XMT_RAM (RAM_SIZE - RCV_RAM) + +#define XMT_START ((rcv_start + RCV_RAM) % RAM_SIZE) + +#define RCV_LOWER_LIMIT (rcv_start >> 8) +#define RCV_UPPER_LIMIT (((rcv_start + RCV_RAM) - 2) >> 8) +#define XMT_LOWER_LIMIT (XMT_START >> 8) +#define XMT_UPPER_LIMIT (((XMT_START + XMT_RAM) - 2) >> 8) + +#define RCV_START_PRO 0x00 +#define RCV_START_10 XMT_RAM + /* by default the old driver */ +static unsigned rcv_start = RCV_START_PRO; + +#define RCV_DONE 0x0008 +#define RX_OK 0x2000 +#define RX_ERROR 0x0d81 + +#define TX_DONE_BIT 0x0080 +#define CHAIN_BIT 0x8000 +#define XMT_STATUS 0x02 +#define XMT_CHAIN 0x04 +#define XMT_COUNT 0x06 + +#define BANK0_SELECT 0x00 +#define BANK1_SELECT 0x40 +#define BANK2_SELECT 0x80 + +/* Bank 0 registers */ +#define COMMAND_REG 0x00 /* Register 0 */ +#define MC_SETUP 0x03 +#define XMT_CMD 0x04 +#define DIAGNOSE_CMD 0x07 +#define RCV_ENABLE_CMD 0x08 +#define RCV_DISABLE_CMD 0x0a +#define STOP_RCV_CMD 0x0b +#define RESET_CMD 0x0e +#define POWER_DOWN_CMD 0x18 +#define RESUME_XMT_CMD 0x1c +#define SEL_RESET_CMD 0x1e +#define STATUS_REG 0x01 /* Register 1 */ +#define RX_INT 0x02 +#define TX_INT 0x04 +#define EXEC_STATUS 0x30 +#define ID_REG 0x02 /* Register 2 */ +#define R_ROBIN_BITS 0xc0 /* round robin counter */ +#define ID_REG_MASK 0x2c +#define ID_REG_SIG 0x24 +#define AUTO_ENABLE 0x10 +#define INT_MASK_REG 0x03 /* Register 3 */ +#define RX_STOP_MASK 0x01 +#define RX_MASK 0x02 +#define TX_MASK 0x04 +#define EXEC_MASK 0x08 +#define ALL_MASK 0x0f +#define IO_32_BIT 0x10 +#define RCV_BAR 0x04 /* The following are word (16-bit) registers */ +#define RCV_STOP 0x06 + +#define XMT_BAR_PRO 0x0a +#define XMT_BAR_10 0x0b +static unsigned xmt_bar = XMT_BAR_PRO; + +#define HOST_ADDRESS_REG 0x0c +#define IO_PORT 0x0e +#define IO_PORT_32_BIT 0x0c + +/* Bank 1 registers */ +#define REG1 0x01 +#define WORD_WIDTH 0x02 +#define INT_ENABLE 0x80 +#define INT_NO_REG 0x02 +#define RCV_LOWER_LIMIT_REG 0x08 +#define RCV_UPPER_LIMIT_REG 0x09 + +#define XMT_LOWER_LIMIT_REG_PRO 0x0a +#define XMT_UPPER_LIMIT_REG_PRO 0x0b +#define XMT_LOWER_LIMIT_REG_10 0x0b +#define XMT_UPPER_LIMIT_REG_10 0x0a +static unsigned xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_PRO; +static unsigned xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_PRO; + +/* Bank 2 registers */ +#define XMT_Chain_Int 0x20 /* Interrupt at the end of the transmit chain */ +#define XMT_Chain_ErrStop 0x40 /* Interrupt at the end of the chain even if there are errors */ +#define RCV_Discard_BadFrame 0x80 /* Throw bad frames away, and continue to receive others */ +#define REG2 0x02 +#define PRMSC_Mode 0x01 +#define Multi_IA 0x20 +#define REG3 0x03 +#define TPE_BIT 0x04 +#define BNC_BIT 0x20 +#define REG13 0x0d +#define FDX 0x00 +#define A_N_ENABLE 0x02 + +#define I_ADD_REG0 0x04 +#define I_ADD_REG1 0x05 +#define I_ADD_REG2 0x06 +#define I_ADD_REG3 0x07 +#define I_ADD_REG4 0x08 +#define I_ADD_REG5 0x09 + +#define EEPROM_REG_PRO 0x0a +#define EEPROM_REG_10 0x0b +static unsigned eeprom_reg = EEPROM_REG_PRO; + +#define EESK 0x01 +#define EECS 0x02 +#define EEDI 0x04 +#define EEDO 0x08 + +/* The horrible routine to read a word from the serial EEPROM. */ +/* IMPORTANT - the 82595 will be set to Bank 0 after the eeprom is read */ + +/* The delay between EEPROM clock transitions. */ +#define eeprom_delay() { udelay(40); } +#define EE_READ_CMD (6 << 6) + +/* do a full reset; data sheet asks for 250us delay */ +#define eepro_full_reset(ioaddr) outb(RESET_CMD, ioaddr); udelay(255); + +/* do a nice reset */ +#define eepro_sel_reset(ioaddr) \ + do { \ + outb ( SEL_RESET_CMD, ioaddr ); \ + (void) SLOW_DOWN; \ + (void) SLOW_DOWN; \ + } while (0) + +/* clear all interrupts */ +#define eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG) + +/* enable rx */ +#define eepro_en_rx(ioaddr) outb(RCV_ENABLE_CMD, ioaddr) + +/* disable rx */ +#define eepro_dis_rx(ioaddr) outb(RCV_DISABLE_CMD, ioaddr) + +/* switch bank */ +#define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr) +#define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr) +#define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr) + +static unsigned int rx_start, tx_start; +static int tx_last; +static unsigned int tx_end; +static int eepro = 0; +static unsigned int mem_start, mem_end = RCV_DEFAULT_RAM / 1024; + +/************************************************************************** +RESET - Reset adapter +***************************************************************************/ +static void eepro_reset(struct nic *nic) +{ + int temp_reg, i; + + /* put the card in its initial state */ + eepro_sw2bank2(nic->ioaddr); /* be careful, bank2 now */ + temp_reg = inb(nic->ioaddr + eeprom_reg); + DBG("Stepping %d\n", temp_reg >> 5); + if (temp_reg & 0x10) /* check the TurnOff Enable bit */ + outb(temp_reg & 0xEF, nic->ioaddr + eeprom_reg); + for (i = 0; i < ETH_ALEN; i++) /* fill the MAC address */ + outb(nic->node_addr[i], nic->ioaddr + I_ADD_REG0 + i); + temp_reg = inb(nic->ioaddr + REG1); + /* setup Transmit Chaining and discard bad RCV frames */ + outb(temp_reg | XMT_Chain_Int | XMT_Chain_ErrStop + | RCV_Discard_BadFrame, nic->ioaddr + REG1); + temp_reg = inb(nic->ioaddr + REG2); /* match broadcast */ + outb(temp_reg | 0x14, nic->ioaddr + REG2); + temp_reg = inb(nic->ioaddr + REG3); + outb(temp_reg & 0x3F, nic->ioaddr + REG3); /* clear test mode */ + /* set the receiving mode */ + eepro_sw2bank1(nic->ioaddr); /* be careful, bank1 now */ + /* initialise the RCV and XMT upper and lower limits */ + outb(RCV_LOWER_LIMIT, nic->ioaddr + RCV_LOWER_LIMIT_REG); + outb(RCV_UPPER_LIMIT, nic->ioaddr + RCV_UPPER_LIMIT_REG); + outb(XMT_LOWER_LIMIT, nic->ioaddr + xmt_lower_limit_reg); + outb(XMT_UPPER_LIMIT, nic->ioaddr + xmt_upper_limit_reg); + eepro_sw2bank0(nic->ioaddr); /* Switch back to bank 0 */ + eepro_clear_int(nic->ioaddr); + /* Initialise RCV */ + outw(rx_start = (RCV_LOWER_LIMIT << 8), nic->ioaddr + RCV_BAR); + outw(((RCV_UPPER_LIMIT << 8) | 0xFE), nic->ioaddr + RCV_STOP); + /* Make sure 1st poll won't find a valid packet header */ + outw((RCV_LOWER_LIMIT << 8), nic->ioaddr + HOST_ADDRESS_REG); + outw(0, nic->ioaddr + IO_PORT); + /* Intialise XMT */ + outw((XMT_LOWER_LIMIT << 8), nic->ioaddr + xmt_bar); + eepro_sel_reset(nic->ioaddr); + tx_start = tx_end = (unsigned int) (XMT_LOWER_LIMIT << 8); + tx_last = 0; + eepro_en_rx(nic->ioaddr); +} + +/************************************************************************** +POLL - Wait for a frame +***************************************************************************/ +static int eepro_poll(struct nic *nic, int retrieve) +{ + unsigned int rcv_car = rx_start; + unsigned int rcv_event, rcv_status, rcv_next_frame, rcv_size; + + /* return true if there's an ethernet packet ready to read */ + /* nic->packet should contain data on return */ + /* nic->packetlen should contain length of data */ +#if 0 + if ((inb(nic->ioaddr + STATUS_REG) & 0x40) == 0) + return (0); + outb(0x40, nic->ioaddr + STATUS_REG); +#endif + outw(rcv_car, nic->ioaddr + HOST_ADDRESS_REG); + rcv_event = inw(nic->ioaddr + IO_PORT); + if (rcv_event != RCV_DONE) + return (0); + + /* FIXME: I'm guessing this might not work with this card, since + it looks like once a rcv_event is started it must be completed. + maybe there's another way. */ + if ( ! retrieve ) return 1; + + rcv_status = inw(nic->ioaddr + IO_PORT); + rcv_next_frame = inw(nic->ioaddr + IO_PORT); + rcv_size = inw(nic->ioaddr + IO_PORT); +#if 0 + printf("%hX %hX %d %hhX\n", rcv_status, rcv_next_frame, rcv_size, + inb(nic->ioaddr + STATUS_REG)); +#endif + if ((rcv_status & (RX_OK|RX_ERROR)) != RX_OK) { + printf("Receive error %hX\n", rcv_status); + return (0); + } + rcv_size &= 0x3FFF; + insw(nic->ioaddr + IO_PORT, nic->packet, ((rcv_size + 3) >> 1)); +#if 0 +{ + int i; + for (i = 0; i < 48; i++) { + printf("%hhX", nic->packet[i]); + putchar(i % 16 == 15 ? '\n' : ' '); + } +} +#endif + nic->packetlen = rcv_size; + rcv_car = (rx_start + RCV_HEADER + rcv_size); + rx_start = rcv_next_frame; +/* + hex_dump(rcv_car, nic->packetlen); +*/ + + if (rcv_car == 0) + rcv_car = ((RCV_UPPER_LIMIT << 8) | 0xff); + outw(rcv_car - 1, nic->ioaddr + RCV_STOP); + return (1); +} + +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static void eepro_transmit( + struct nic *nic, + const char *d, /* Destination */ + unsigned int t, /* Type */ + unsigned int s, /* size */ + const char *p) /* Packet */ +{ + unsigned int status, tx_available, last, end, length; + unsigned short type; + int boguscount = 20; + + length = s + ETH_HLEN; + if (tx_end > tx_start) + tx_available = XMT_RAM - (tx_end - tx_start); + else if (tx_end < tx_start) + tx_available = tx_start - tx_end; + else + tx_available = XMT_RAM; + last = tx_end; + end = last + (((length + 3) >> 1) << 1) + XMT_HEADER; + if (end >= (XMT_UPPER_LIMIT << 8)) { + last = (XMT_LOWER_LIMIT << 8); + end = last + (((length + 3) >> 1) << 1) + XMT_HEADER; + } + outw(last, nic->ioaddr + HOST_ADDRESS_REG); + outw(XMT_CMD, nic->ioaddr + IO_PORT); + outw(0, nic->ioaddr + IO_PORT); + outw(end, nic->ioaddr + IO_PORT); + outw(length, nic->ioaddr + IO_PORT); + outsw(nic->ioaddr + IO_PORT, d, ETH_ALEN / 2); + outsw(nic->ioaddr + IO_PORT, nic->node_addr, ETH_ALEN / 2); + type = htons(t); + outsw(nic->ioaddr + IO_PORT, &type, sizeof(type) / 2); + outsw(nic->ioaddr + IO_PORT, p, (s + 3) >> 1); + /* A dummy read to flush the DRAM write pipeline */ + status = inw(nic->ioaddr + IO_PORT); + outw(last, nic->ioaddr + xmt_bar); + outb(XMT_CMD, nic->ioaddr); + tx_start = last; + tx_last = last; + tx_end = end; +#if 0 + printf("%d %d\n", tx_start, tx_end); +#endif + while (boguscount > 0) { + if (((status = inw(nic->ioaddr + IO_PORT)) & TX_DONE_BIT) == 0) { + udelay(40); + boguscount--; + continue; + } + if ((status & 0x2000) == 0) { + DBG("Transmit status %hX\n", status); + } + } +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void eepro_disable ( struct nic *nic, struct isa_device *isa __unused ) { + eepro_sw2bank0(nic->ioaddr); /* Switch to bank 0 */ + /* Flush the Tx and disable Rx */ + outb(STOP_RCV_CMD, nic->ioaddr); + tx_start = tx_end = (XMT_LOWER_LIMIT << 8); + tx_last = 0; + /* Reset the 82595 */ + eepro_full_reset(nic->ioaddr); +} + +/************************************************************************** +DISABLE - Enable, Disable, or Force interrupts +***************************************************************************/ +static void eepro_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + +static int read_eeprom(uint16_t ioaddr, int location) +{ + int i; + unsigned short retval = 0; + int ee_addr = ioaddr + eeprom_reg; + int read_cmd = location | EE_READ_CMD; + int ctrl_val = EECS; + + if (eepro == LAN595FX_10ISA) { + eepro_sw2bank1(ioaddr); + outb(0x00, ioaddr + STATUS_REG); + } + eepro_sw2bank2(ioaddr); + outb(ctrl_val, ee_addr); + /* shift the read command bits out */ + for (i = 8; i >= 0; i--) { + short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val; + outb(outval, ee_addr); + outb(outval | EESK, ee_addr); /* EEPROM clock tick */ + eeprom_delay(); + outb(outval, ee_addr); /* finish EEPROM clock tick */ + eeprom_delay(); + } + outb(ctrl_val, ee_addr); + for (i = 16; i > 0; i--) { + outb(ctrl_val | EESK, ee_addr); + eeprom_delay(); + retval = (retval << 1) | ((inb(ee_addr) & EEDO) ? 1 : 0); + outb(ctrl_val, ee_addr); + eeprom_delay(); + } + /* terminate the EEPROM access */ + ctrl_val &= ~EECS; + outb(ctrl_val | EESK, ee_addr); + eeprom_delay(); + outb(ctrl_val, ee_addr); + eeprom_delay(); + eepro_sw2bank0(ioaddr); + return (retval); +} + +static int eepro_probe1 ( isa_probe_addr_t ioaddr ) { + int id, counter; + + id = inb(ioaddr + ID_REG); + if ((id & ID_REG_MASK) != ID_REG_SIG) + return (0); + counter = id & R_ROBIN_BITS; + if (((id = inb(ioaddr + ID_REG)) & R_ROBIN_BITS) != (counter + 0x40)) + return (0); + /* yes the 82595 has been found */ + return (1); +} + +static struct nic_operations eepro_operations = { + .connect = dummy_connect, + .poll = eepro_poll, + .transmit = eepro_transmit, + .irq = eepro_irq, + +}; + +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +***************************************************************************/ +static int eepro_probe ( struct nic *nic, struct isa_device *isa ) { + + int i, l_eepro = 0; + union { + unsigned char caddr[ETH_ALEN]; + unsigned short saddr[ETH_ALEN/2]; + } station_addr; + const char *name; + + nic->irqno = 0; + nic->ioaddr = isa->ioaddr; + + station_addr.saddr[2] = read_eeprom(nic->ioaddr,2); + if ( ( station_addr.saddr[2] == 0x0000 ) || + ( station_addr.saddr[2] == 0xFFFF ) ) { + l_eepro = 3; + eepro = LAN595FX_10ISA; + eeprom_reg= EEPROM_REG_10; + rcv_start = RCV_START_10; + xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_10; + xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_10; + station_addr.saddr[2] = read_eeprom(nic->ioaddr,2); + } + station_addr.saddr[1] = read_eeprom(nic->ioaddr,3); + station_addr.saddr[0] = read_eeprom(nic->ioaddr,4); + if (l_eepro) + name = "Intel EtherExpress 10 ISA"; + else if (read_eeprom(nic->ioaddr,7) == ee_FX_INT2IRQ) { + name = "Intel EtherExpress Pro/10+ ISA"; + l_eepro = 2; + } else if (station_addr.saddr[0] == SA_ADDR1) { + name = "Intel EtherExpress Pro/10 ISA"; + l_eepro = 1; + } else { + l_eepro = 0; + name = "Intel 82595-based LAN card"; + } + station_addr.saddr[0] = swap16(station_addr.saddr[0]); + station_addr.saddr[1] = swap16(station_addr.saddr[1]); + station_addr.saddr[2] = swap16(station_addr.saddr[2]); + for (i = 0; i < ETH_ALEN; i++) { + nic->node_addr[i] = station_addr.caddr[i]; + } + + DBG ( "%s ioaddr %#hX, addr %s", name, nic->ioaddr, eth_ntoa ( nic->node_addr ) ); + + mem_start = RCV_LOWER_LIMIT << 8; + if ((mem_end & 0x3F) < 3 || (mem_end & 0x3F) > 29) + mem_end = RCV_UPPER_LIMIT << 8; + else { + mem_end = mem_end * 1024 + (RCV_LOWER_LIMIT << 8); + rcv_ram = mem_end - (RCV_LOWER_LIMIT << 8); + } + printf(", Rx mem %dK, if %s\n", (mem_end - mem_start) >> 10, + GetBit(read_eeprom(nic->ioaddr,5), ee_BNC_TPE) ? "BNC" : "TP"); + + eepro_reset(nic); + + /* point to NIC specific routines */ + nic->nic_op = &eepro_operations; + return 1; +} + +static isa_probe_addr_t eepro_probe_addrs[] = { + 0x300, 0x210, 0x240, 0x280, 0x2C0, 0x200, 0x320, 0x340, 0x360, +}; + +ISA_DRIVER ( eepro_driver, eepro_probe_addrs, eepro_probe1, + GENERIC_ISAPNP_VENDOR, 0x828a ); + +DRIVER ( "eepro", nic_driver, isa_driver, eepro_driver, + eepro_probe, eepro_disable ); + +ISA_ROM ( "eepro", "Intel Etherexpress Pro/10" ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/eepro100.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/eepro100.c new file mode 100644 index 0000000..85d7571 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/eepro100.c @@ -0,0 +1,853 @@ +/* + * eepro100.c -- This file implements the eepro100 driver for etherboot. + * + * + * Copyright (C) AW Computer Systems. + * written by R.E.Wolff -- R.E.Wolff@BitWizard.nl + * + * + * AW Computer Systems is contributing to the free software community + * by paying for this driver and then putting the result under GPL. + * + * If you need a Linux device driver, please contact BitWizard for a + * quote. + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2, or (at + * your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * date version by what + * Written: May 29 1997 V0.10 REW Initial revision. + * changes: May 31 1997 V0.90 REW Works! + * Jun 1 1997 V0.91 REW Cleanup + * Jun 2 1997 V0.92 REW Add some code documentation + * Jul 25 1997 V1.00 REW Tested by AW to work in a PROM + * Cleanup for publication + * Dez 11 2004 V1.10 Kiszka Add RX ring buffer support + * + * This is the etherboot intel etherexpress Pro/100B driver. + * + * It was written from scratch, with Donald Beckers eepro100.c kernel + * driver as a guideline. Mostly the 82557 related definitions and the + * lower level routines have been cut-and-pasted into this source. + * + * The driver was finished before Intel got the NDA out of the closet. + * I still don't have the docs. + * + * + * Datasheet is now published and available from + * ftp://download.intel.com/design/network/manuals/8255X_OpenSDM.pdf + * - Michael Brown + * */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +/* Philosophy of this driver. + * + * Probing: + * + * Using the pci.c functions of the Etherboot code, the 82557 chip is detected. + * It is verified that the BIOS initialized everything properly and if + * something is missing it is done now. + * + * + * Initialization: + * + * + * The chip is then initialized to "know" its ethernet address, and to + * start recieving packets. The Linux driver has a whole transmit and + * recieve ring of buffers. This is neat if you need high performance: + * you can write the buffers asynchronously to the chip reading the + * buffers and transmitting them over the network. Performance is NOT + * an issue here. We can boot a 400k kernel in about two + * seconds. (Theory: 0.4 seconds). Booting a system is going to take + * about half a minute anyway, so getting 10 times closer to the + * theoretical limit is going to make a difference of a few percent. */ +/* Not totally true: busy networks can cause packet drops due to RX + * buffer overflows. Fixed in V1.10 of this driver. [Kiszka] */ +/* + * + * Transmitting and recieving. + * + * We have only one transmit descriptor. It has two buffer descriptors: + * one for the header, and the other for the data. + * We have multiple receive buffers (currently: 4). The chip is told to + * receive packets and suspend itself once it ran on the last free buffer. + * The recieve (poll) routine simply looks at the current recieve buffer, + * picks the packet if any, and releases this buffer again (classic ring + * buffer concept). This helps to avoid packet drops on busy networks. + * + * Caveats: + * + * The Etherboot framework moves the code to the 48k segment from + * 0x94000 to 0xa0000. There is just a little room between the end of + * this driver and the 0xa0000 address. If you compile in too many + * features, this will overflow. + * The number under "hex" in the output of size that scrolls by while + * compiling should be less than 8000. Maybe even the stack is up there, + * so that you need even more headroom. + */ + +/* The etherboot authors seem to dislike the argument ordering in + * outb macros that Linux uses. I disklike the confusion that this + * has caused even more.... This file uses the Linux argument ordering. */ +/* Sorry not us. It's inherited code from FreeBSD. [The authors] */ + +#include "etherboot.h" +#include "nic.h" +#include <gpxe/ethernet.h> +#include <gpxe/pci.h> + +static int ioaddr; + +enum speedo_offsets { + SCBStatus = 0, SCBCmd = 2, /* Rx/Command Unit command and status. */ + SCBPointer = 4, /* General purpose pointer. */ + SCBPort = 8, /* Misc. commands and operands. */ + SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */ + SCBCtrlMDI = 16, /* MDI interface control. */ + SCBEarlyRx = 20, /* Early receive byte count. */ +}; + +enum SCBCmdBits { + SCBMaskCmdDone=0x8000, SCBMaskRxDone=0x4000, SCBMaskCmdIdle=0x2000, + SCBMaskRxSuspend=0x1000, SCBMaskEarlyRx=0x0800, SCBMaskFlowCtl=0x0400, + SCBTriggerIntr=0x0200, SCBMaskAll=0x0100, + /* The rest are Rx and Tx commands. */ + CUStart=0x0010, CUResume=0x0020, CUStatsAddr=0x0040, CUShowStats=0x0050, + CUCmdBase=0x0060, /* CU Base address (set to zero) . */ + CUDumpStats=0x0070, /* Dump then reset stats counters. */ + RxStart=0x0001, RxResume=0x0002, RxAbort=0x0004, RxAddrLoad=0x0006, + RxResumeNoResources=0x0007, +}; + +static int do_eeprom_cmd(int cmd, int cmd_len); +void hd(void *where, int n); + +/***********************************************************************/ +/* I82557 related defines */ +/***********************************************************************/ + +/* Serial EEPROM section. + A "bit" grungy, but we work our way through bit-by-bit :->. */ +/* EEPROM_Ctrl bits. */ +#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ +#define EE_CS 0x02 /* EEPROM chip select. */ +#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ +#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ +#define EE_WRITE_0 0x4802 +#define EE_WRITE_1 0x4806 +#define EE_ENB (0x4800 | EE_CS) + +/* The EEPROM commands include the alway-set leading bit. */ +#define EE_READ_CMD 6 + +/* The SCB accepts the following controls for the Tx and Rx units: */ +#define CU_START 0x0010 +#define CU_RESUME 0x0020 +#define CU_STATSADDR 0x0040 +#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */ +#define CU_CMD_BASE 0x0060 /* Base address to add to add CU commands. */ +#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */ + +#define RX_START 0x0001 +#define RX_RESUME 0x0002 +#define RX_ABORT 0x0004 +#define RX_ADDR_LOAD 0x0006 +#define RX_RESUMENR 0x0007 +#define INT_MASK 0x0100 +#define DRVR_INT 0x0200 /* Driver generated interrupt. */ + +enum phy_chips { NonSuchPhy=0, I82553AB, I82553C, I82503, DP83840, S80C240, + S80C24, PhyUndefined, DP83840A=10, }; + +/* Commands that can be put in a command list entry. */ +enum commands { + CmdNOp = 0, + CmdIASetup = 1, + CmdConfigure = 2, + CmdMulticastList = 3, + CmdTx = 4, + CmdTDR = 5, + CmdDump = 6, + CmdDiagnose = 7, + + /* And some extra flags: */ + CmdSuspend = 0x4000, /* Suspend after completion. */ + CmdIntr = 0x2000, /* Interrupt after completion. */ + CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ +}; + +/* How to wait for the command unit to accept a command. + Typically this takes 0 ticks. */ +static inline void wait_for_cmd_done(int cmd_ioaddr) +{ + int wait = 0; + int delayed_cmd; + + do + if (inb(cmd_ioaddr) == 0) return; + while(++wait <= 100); + delayed_cmd = inb(cmd_ioaddr); + do + if (inb(cmd_ioaddr) == 0) break; + while(++wait <= 10000); + printf("Command %2.2x was not immediately accepted, %d ticks!\n", + delayed_cmd, wait); +} + +/* Elements of the dump_statistics block. This block must be lword aligned. */ +static struct speedo_stats { + u32 tx_good_frames; + u32 tx_coll16_errs; + u32 tx_late_colls; + u32 tx_underruns; + u32 tx_lost_carrier; + u32 tx_deferred; + u32 tx_one_colls; + u32 tx_multi_colls; + u32 tx_total_colls; + u32 rx_good_frames; + u32 rx_crc_errs; + u32 rx_align_errs; + u32 rx_resource_errs; + u32 rx_overrun_errs; + u32 rx_colls_errs; + u32 rx_runt_errs; + u32 done_marker; +} lstats; + +/* A speedo3 TX buffer descriptor with two buffers... */ +static struct TxFD { + volatile s16 status; + s16 command; + u32 link; /* void * */ + u32 tx_desc_addr; /* (almost) Always points to the tx_buf_addr element. */ + s32 count; /* # of TBD (=2), Tx start thresh., etc. */ + /* This constitutes two "TBD" entries: hdr and data */ + u32 tx_buf_addr0; /* void *, header of frame to be transmitted. */ + s32 tx_buf_size0; /* Length of Tx hdr. */ + u32 tx_buf_addr1; /* void *, data to be transmitted. */ + s32 tx_buf_size1; /* Length of Tx data. */ +} txfd; + +struct RxFD { /* Receive frame descriptor. */ + volatile s16 status; + s16 command; + u32 link; /* struct RxFD * */ + u32 rx_buf_addr; /* void * */ + u16 count; + u16 size; + char packet[1518]; +}; + +static struct nic_operations eepro100_operations; + +#define RXFD_COUNT 4 +struct { + struct RxFD rxfds[RXFD_COUNT]; +} eepro100_bufs __shared; +#define rxfds eepro100_bufs.rxfds +static unsigned int rxfd = 0; + +static int congenb = 0; /* Enable congestion control in the DP83840. */ +static int txfifo = 8; /* Tx FIFO threshold in 4 byte units, 0-15 */ +static int rxfifo = 8; /* Rx FIFO threshold, default 32 bytes. */ +static int txdmacount = 0; /* Tx DMA burst length, 0-127, default 0. */ +static int rxdmacount = 0; /* Rx DMA length, 0 means no preemption. */ + +/* I don't understand a byte in this structure. It was copied from the + * Linux kernel initialization for the eepro100. -- REW */ +static struct ConfCmd { + s16 status; + s16 command; + u32 link; + unsigned char data[22]; +} confcmd = { + 0, 0, 0, /* filled in later */ + {22, 0x08, 0, 0, 0, 0x80, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */ + 0, 0x2E, 0, 0x60, 0, + 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */ + 0x3f, 0x05, } +}; + +/***********************************************************************/ +/* Locally used functions */ +/***********************************************************************/ + +/* Support function: mdio_write + * + * This probably writes to the "physical media interface chip". + * -- REW + */ + +static int mdio_write(int phy_id, int location, int value) +{ + int val, boguscnt = 64*4; /* <64 usec. to complete, typ 27 ticks */ + + outl(0x04000000 | (location<<16) | (phy_id<<21) | value, + ioaddr + SCBCtrlMDI); + do { + udelay(16); + + val = inl(ioaddr + SCBCtrlMDI); + if (--boguscnt < 0) { + printf(" mdio_write() timed out with val = %X.\n", val); + break; + } + } while (! (val & 0x10000000)); + return val & 0xffff; +} + +/* Support function: mdio_read + * + * This probably reads a register in the "physical media interface chip". + * -- REW + */ +static int mdio_read(int phy_id, int location) +{ + int val, boguscnt = 64*4; /* <64 usec. to complete, typ 27 ticks */ + outl(0x08000000 | (location<<16) | (phy_id<<21), ioaddr + SCBCtrlMDI); + do { + udelay(16); + + val = inl(ioaddr + SCBCtrlMDI); + + if (--boguscnt < 0) { + printf( " mdio_read() timed out with val = %X.\n", val); + break; + } + } while (! (val & 0x10000000)); + return val & 0xffff; +} + +/* The fixes for the code were kindly provided by Dragan Stancevic + <visitor@valinux.com> to strictly follow Intel specifications of EEPROM + access timing. + The publicly available sheet 64486302 (sec. 3.1) specifies 1us access + interval for serial EEPROM. However, it looks like that there is an + additional requirement dictating larger udelay's in the code below. + 2000/05/24 SAW */ +static int do_eeprom_cmd(int cmd, int cmd_len) +{ + unsigned retval = 0; + long ee_addr = ioaddr + SCBeeprom; + + outw(EE_ENB, ee_addr); udelay(2); + outw(EE_ENB | EE_SHIFT_CLK, ee_addr); udelay(2); + + /* Shift the command bits out. */ + do { + short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; + outw(dataval, ee_addr); udelay(2); + outw(dataval | EE_SHIFT_CLK, ee_addr); udelay(2); + retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0); + } while (--cmd_len >= 0); + outw(EE_ENB, ee_addr); udelay(2); + + /* Terminate the EEPROM access. */ + outw(EE_ENB & ~EE_CS, ee_addr); + return retval; +} + +#if 0 +static inline void whereami (const char *str) +{ + printf ("%s\n", str); + sleep (2); +} +#else +#define whereami(s) +#endif + +static void eepro100_irq(struct nic *nic __unused, irq_action_t action) +{ + uint16_t enabled_mask = ( SCBMaskCmdDone | SCBMaskCmdIdle | + SCBMaskEarlyRx | SCBMaskFlowCtl ); + + switch ( action ) { + case DISABLE : + outw(SCBMaskAll, ioaddr + SCBCmd); + break; + case ENABLE : + outw(enabled_mask, ioaddr + SCBCmd); + break; + case FORCE : + outw(enabled_mask | SCBTriggerIntr, ioaddr + SCBCmd); + break; + } +} + +/* function: eepro100_transmit + * This transmits a packet. + * + * Arguments: char d[6]: destination ethernet address. + * unsigned short t: ethernet protocol type. + * unsigned short s: size of the data-part of the packet. + * char *p: the data for the packet. + * returns: void. + */ + +static void eepro100_transmit(struct nic *nic, const char *d, unsigned int t, unsigned int s, const char *p) +{ + struct eth_hdr { + unsigned char dst_addr[ETH_ALEN]; + unsigned char src_addr[ETH_ALEN]; + unsigned short type; + } hdr; + unsigned short status; + int s1, s2; + unsigned long ct; + + status = inw(ioaddr + SCBStatus); + /* Acknowledge all of the current interrupt sources ASAP. */ + outw(status & 0xfc00, ioaddr + SCBStatus); + +#ifdef DEBUG + printf ("transmitting type %hX packet (%d bytes). status = %hX, cmd=%hX\n", + t, s, status, inw (ioaddr + SCBCmd)); +#endif + + memcpy (&hdr.dst_addr, d, ETH_ALEN); + memcpy (&hdr.src_addr, nic->node_addr, ETH_ALEN); + + hdr.type = htons (t); + + txfd.status = 0; + txfd.command = CmdSuspend | CmdTx | CmdTxFlex; + txfd.link = virt_to_bus (&txfd); + txfd.count = 0x02208000; + txfd.tx_desc_addr = virt_to_bus(&txfd.tx_buf_addr0); + + txfd.tx_buf_addr0 = virt_to_bus (&hdr); + txfd.tx_buf_size0 = sizeof (hdr); + + txfd.tx_buf_addr1 = virt_to_bus (p); + txfd.tx_buf_size1 = s; + +#ifdef DEBUG + printf ("txfd: \n"); + hd (&txfd, sizeof (txfd)); +#endif + + outl(virt_to_bus(&txfd), ioaddr + SCBPointer); + outb(CU_START, ioaddr + SCBCmd); + wait_for_cmd_done(ioaddr + SCBCmd); + + s1 = inw (ioaddr + SCBStatus); + + ct = currticks(); + /* timeout 10 ms for transmit */ + while (!txfd.status && ct + 10*1000) + /* Wait */; + s2 = inw (ioaddr + SCBStatus); + +#ifdef DEBUG + printf ("s1 = %hX, s2 = %hX.\n", s1, s2); +#endif +} + +/* + * Sometimes the receiver stops making progress. This routine knows how to + * get it going again, without losing packets or being otherwise nasty like + * a chip reset would be. Previously the driver had a whole sequence + * of if RxSuspended, if it's no buffers do one thing, if it's no resources, + * do another, etc. But those things don't really matter. Separate logic + * in the ISR provides for allocating buffers--the other half of operation + * is just making sure the receiver is active. speedo_rx_soft_reset does that. + * This problem with the old, more involved algorithm is shown up under + * ping floods on the order of 60K packets/second on a 100Mbps fdx network. + */ +static void +speedo_rx_soft_reset(void) +{ + int i; + + +#ifdef DEBUG + printf("reset\n"); +#endif + wait_for_cmd_done(ioaddr + SCBCmd); + /* + * Put the hardware into a known state. + */ + outb(RX_ABORT, ioaddr + SCBCmd); + + for (i = 0; i < RXFD_COUNT; i++) { + rxfds[i].status = 0; + rxfds[i].rx_buf_addr = 0xffffffff; + rxfds[i].count = 0; + rxfds[i].size = 1528; + } + + wait_for_cmd_done(ioaddr + SCBCmd); + + outl(virt_to_bus(&rxfds[rxfd]), ioaddr + SCBPointer); + outb(RX_START, ioaddr + SCBCmd); +} + +/* function: eepro100_poll / eth_poll + * This receives a packet from the network. + * + * Arguments: none + * + * returns: 1 if a packet was received. + * 0 if no packet was received. + * side effects: + * returns the packet in the array nic->packet. + * returns the length of the packet in nic->packetlen. + */ + +static int eepro100_poll(struct nic *nic, int retrieve) +{ + if (rxfds[rxfd].status) { + if (!retrieve) + return 1; +#ifdef DEBUG + printf("Got a packet: Len = %d, rxfd = %d.\n", + rxfds[rxfd].count & 0x3fff, rxfd); +#endif + /* First save the data from the rxfd */ + nic->packetlen = rxfds[rxfd].count & 0x3fff; + memcpy(nic->packet, rxfds[rxfd].packet, nic->packetlen); + + rxfds[rxfd].status = 0; + rxfds[rxfd].command = 0xc000; + rxfds[rxfd].rx_buf_addr = 0xFFFFFFFF; + rxfds[rxfd].count = 0; + rxfds[rxfd].size = 1528; + rxfds[(rxfd-1) % RXFD_COUNT].command = 0x0000; + rxfd = (rxfd+1) % RXFD_COUNT; + +#ifdef DEBUG + hd (nic->packet, 0x30); +#endif + + /* Acknowledge all conceivable interrupts */ + outw(0xff00, ioaddr + SCBStatus); + + return 1; + } + + /* + * The chip may have suspended reception for various reasons. + * Check for that, and re-prime it should this be the case. + */ + switch ((inw(ioaddr + SCBStatus) >> 2) & 0xf) { + case 0: /* Idle */ + break; + case 1: /* Suspended */ + case 2: /* No resources (RxFDs) */ + case 9: /* Suspended with no more RBDs */ + case 10: /* No resources due to no RBDs */ + case 12: /* Ready with no RBDs */ + speedo_rx_soft_reset(); + break; + default: + /* reserved values */ + break; + } + return 0; +} + +/* function: eepro100_disable + * resets the card. This is used to allow Etherboot or Linux + * to probe the card again from a "virginal" state.... + * Arguments: none + * + * returns: void. + */ +static void eepro100_disable ( struct nic *nic __unused ) { +/* from eepro100_reset */ + outl(0, ioaddr + SCBPort); +/* from eepro100_disable */ + /* See if this PartialReset solves the problem with interfering with + kernel operation after Etherboot hands over. - Ken 20001102 */ + outl(2, ioaddr + SCBPort); + + /* The following is from the Intel e100 driver. + * This hopefully solves the problem with hanging hard DOS images. */ + + /* wait for the reset to take effect */ + udelay(20); + + /* Mask off our interrupt line -- it is unmasked after reset */ + { + u16 intr_status; + /* Disable interrupts on our PCI board by setting the mask bit */ + outw(INT_MASK, ioaddr + SCBCmd); + intr_status = inw(ioaddr + SCBStatus); + /* ack and clear intrs */ + outw(intr_status, ioaddr + SCBStatus); + inw(ioaddr + SCBStatus); + } +} + +/* exported function: eepro100_probe / eth_probe + * initializes a card + * + * side effects: + * leaves the ioaddress of the 82557 chip in the variable ioaddr. + * leaves the 82557 initialized, and ready to recieve packets. + */ + +static int eepro100_probe ( struct nic *nic, struct pci_device *pci ) { + + unsigned short sum = 0; + int i; + int read_cmd, ee_size; + int options; + int rx_mode; + unsigned long ct; + + /* we cache only the first few words of the EEPROM data + be careful not to access beyond this array */ + unsigned short eeprom[16]; + + if (pci->ioaddr == 0) + return 0; + + adjust_pci_device(pci); + + nic->ioaddr = pci->ioaddr; + nic->irqno = pci->irq; + + ioaddr = nic->ioaddr; + + if ((do_eeprom_cmd(EE_READ_CMD << 24, 27) & 0xffe0000) + == 0xffe0000) { + ee_size = 0x100; + read_cmd = EE_READ_CMD << 24; + } else { + ee_size = 0x40; + read_cmd = EE_READ_CMD << 22; + } + + for (i = 0, sum = 0; i < ee_size; i++) { + unsigned short value = do_eeprom_cmd(read_cmd | (i << 16), 27); + if (i < (int)(sizeof(eeprom)/sizeof(eeprom[0]))) + eeprom[i] = value; + sum += value; + } + + for (i=0;i<ETH_ALEN;i++) { + nic->node_addr[i] = (eeprom[i/2] >> (8*(i&1))) & 0xff; + } + + DBG ( "Ethernet addr: %s\n", eth_ntoa ( nic->node_addr ) ); + + if (sum != 0xBABA) + printf("eepro100: Invalid EEPROM checksum %#hX, " + "check settings before activating this device!\n", sum); + outl(0, ioaddr + SCBPort); + udelay (10000); + whereami ("Got eeprom."); + + /* Base = 0, disable all interrupts */ + outl(0, ioaddr + SCBPointer); + outw(INT_MASK | RX_ADDR_LOAD, ioaddr + SCBCmd); + wait_for_cmd_done(ioaddr + SCBCmd); + whereami ("set rx base addr."); + + outl(virt_to_bus(&lstats), ioaddr + SCBPointer); + outb(CU_STATSADDR, ioaddr + SCBCmd); + wait_for_cmd_done(ioaddr + SCBCmd); + whereami ("set stats addr."); + + /* INIT RX stuff. */ + for (i = 0; i < RXFD_COUNT; i++) { + rxfds[i].status = 0x0000; + rxfds[i].command = 0x0000; + rxfds[i].rx_buf_addr = 0xFFFFFFFF; + rxfds[i].count = 0; + rxfds[i].size = 1528; + rxfds[i].link = virt_to_bus(&rxfds[i+1]); + } + + rxfds[RXFD_COUNT-1].status = 0x0000; + rxfds[RXFD_COUNT-1].command = 0xC000; + rxfds[RXFD_COUNT-1].link = virt_to_bus(&rxfds[0]); + + outl(virt_to_bus(&rxfds[0]), ioaddr + SCBPointer); + outb(RX_START, ioaddr + SCBCmd); + wait_for_cmd_done(ioaddr + SCBCmd); + + whereami ("started RX process."); + + /* INIT TX stuff. */ + + /* Base = 0 */ + outl(0, ioaddr + SCBPointer); + outb(CU_CMD_BASE, ioaddr + SCBCmd); + wait_for_cmd_done(ioaddr + SCBCmd); + + whereami ("set TX base addr."); + + txfd.command = (CmdIASetup); + txfd.status = 0x0000; + txfd.link = virt_to_bus (&confcmd); + + { + char *t = (char *)&txfd.tx_desc_addr; + + for (i=0;i<ETH_ALEN;i++) + t[i] = nic->node_addr[i]; + } + +#ifdef DEBUG + printf ("Setup_eaddr:\n"); + hd (&txfd, 0x20); +#endif + /* options = 0x40; */ /* 10mbps half duplex... */ + options = 0x00; /* Autosense */ + +#ifdef PROMISC + rx_mode = 3; +#elif ALLMULTI + rx_mode = 1; +#else + rx_mode = 0; +#endif + + if ( ((eeprom[6]>>8) & 0x3f) == DP83840 + || ((eeprom[6]>>8) & 0x3f) == DP83840A) { + int mdi_reg23 = mdio_read(eeprom[6] & 0x1f, 23) | 0x0422; + if (congenb) + mdi_reg23 |= 0x0100; + printf(" DP83840 specific setup, setting register 23 to %hX.\n", + mdi_reg23); + mdio_write(eeprom[6] & 0x1f, 23, mdi_reg23); + } + whereami ("Done DP8340 special setup."); + if (options != 0) { + mdio_write(eeprom[6] & 0x1f, 0, + ((options & 0x20) ? 0x2000 : 0) | /* 100mbps? */ + ((options & 0x10) ? 0x0100 : 0)); /* Full duplex? */ + whereami ("set mdio_register."); + } + + confcmd.command = CmdSuspend | CmdConfigure; + confcmd.status = 0x0000; + confcmd.link = virt_to_bus (&txfd); + confcmd.data[1] = (txfifo << 4) | rxfifo; + confcmd.data[4] = rxdmacount; + confcmd.data[5] = txdmacount + 0x80; + confcmd.data[15] = (rx_mode & 2) ? 0x49: 0x48; + confcmd.data[19] = (options & 0x10) ? 0xC0 : 0x80; + confcmd.data[21] = (rx_mode & 1) ? 0x0D: 0x05; + + outl(virt_to_bus(&txfd), ioaddr + SCBPointer); + outb(CU_START, ioaddr + SCBCmd); + wait_for_cmd_done(ioaddr + SCBCmd); + + whereami ("started TX thingy (config, iasetup)."); + + ct = currticks(); + while (!txfd.status && ct + 10*1000 < currticks()) + /* Wait */; + + /* Read the status register once to disgard stale data */ + mdio_read(eeprom[6] & 0x1f, 1); + /* Check to see if the network cable is plugged in. + * This allows for faster failure if there is nothing + * we can do. + */ + if (!(mdio_read(eeprom[6] & 0x1f, 1) & (1 << 2))) { + printf("Valid link not established\n"); + eepro100_disable(nic); + return 0; + } + nic->nic_op = &eepro100_operations; + return 1; +} + +/*********************************************************************/ + +#ifdef DEBUG + +/* Hexdump a number of bytes from memory... */ +void hd (void *where, int n) +{ + int i; + + while (n > 0) { + printf ("%X ", where); + for (i=0;i < ( (n>16)?16:n);i++) + printf (" %hhX", ((char *)where)[i]); + printf ("\n"); + n -= 16; + where += 16; + } +} +#endif + +static struct nic_operations eepro100_operations = { + .connect = dummy_connect, + .poll = eepro100_poll, + .transmit = eepro100_transmit, + .irq = eepro100_irq, + +}; + +static struct pci_device_id eepro100_nics[] = { +PCI_ROM(0x8086, 0x1029, "id1029", "Intel EtherExpressPro100 ID1029", 0), +PCI_ROM(0x8086, 0x1030, "id1030", "Intel EtherExpressPro100 ID1030", 0), +PCI_ROM(0x8086, 0x1031, "82801cam", "Intel 82801CAM (ICH3) Chipset Ethernet Controller", 0), +PCI_ROM(0x8086, 0x1032, "eepro100-1032", "Intel PRO/100 VE Network Connection", 0), +PCI_ROM(0x8086, 0x1033, "eepro100-1033", "Intel PRO/100 VM Network Connection", 0), +PCI_ROM(0x8086, 0x1034, "eepro100-1034", "Intel PRO/100 VM Network Connection", 0), +PCI_ROM(0x8086, 0x1035, "eepro100-1035", "Intel 82801CAM (ICH3) Chipset Ethernet Controller", 0), +PCI_ROM(0x8086, 0x1036, "eepro100-1036", "Intel 82801CAM (ICH3) Chipset Ethernet Controller", 0), +PCI_ROM(0x8086, 0x1037, "eepro100-1037", "Intel 82801CAM (ICH3) Chipset Ethernet Controller", 0), +PCI_ROM(0x8086, 0x1038, "id1038", "Intel PRO/100 VM Network Connection", 0), +PCI_ROM(0x8086, 0x1039, "82562et", "Intel PRO100 VE 82562ET", 0), +PCI_ROM(0x8086, 0x103a, "id103a", "Intel Corporation 82559 InBusiness 10/100", 0), +PCI_ROM(0x8086, 0x103b, "82562etb", "Intel PRO100 VE 82562ETB", 0), +PCI_ROM(0x8086, 0x103c, "eepro100-103c", "Intel PRO/100 VM Network Connection", 0), +PCI_ROM(0x8086, 0x103d, "eepro100-103d", "Intel PRO/100 VE Network Connection", 0), +PCI_ROM(0x8086, 0x103e, "eepro100-103e", "Intel PRO/100 VM Network Connection", 0), +PCI_ROM(0x8086, 0x1051, "prove", "Intel PRO/100 VE Network Connection", 0), +PCI_ROM(0x8086, 0x1059, "82551qm", "Intel PRO/100 M Mobile Connection", 0), +PCI_ROM(0x8086, 0x1209, "82559er", "Intel EtherExpressPro100 82559ER", 0), +PCI_ROM(0x8086, 0x1227, "82865", "Intel 82865 EtherExpress PRO/100A", 0), +PCI_ROM(0x8086, 0x1228, "82556", "Intel 82556 EtherExpress PRO/100 Smart", 0), +PCI_ROM(0x8086, 0x1229, "eepro100", "Intel EtherExpressPro100", 0), +PCI_ROM(0x8086, 0x2449, "82562em", "Intel EtherExpressPro100 82562EM", 0), +PCI_ROM(0x8086, 0x2459, "82562-1", "Intel 82562 based Fast Ethernet Connection", 0), +PCI_ROM(0x8086, 0x245d, "82562-2", "Intel 82562 based Fast Ethernet Connection", 0), +PCI_ROM(0x8086, 0x1050, "82562ez", "Intel 82562EZ Network Connection", 0), +PCI_ROM(0x8086, 0x1051, "eepro100-1051", "Intel 82801EB/ER (ICH5/ICH5R) Chipset Ethernet Controller", 0), +PCI_ROM(0x8086, 0x1065, "82562-3", "Intel 82562 based Fast Ethernet Connection", 0), +PCI_ROM(0x8086, 0x5200, "eepro100-5200", "Intel EtherExpress PRO/100 Intelligent Server", 0), +PCI_ROM(0x8086, 0x5201, "eepro100-5201", "Intel EtherExpress PRO/100 Intelligent Server", 0), +}; + +/* Cards with device ids 0x1030 to 0x103F, 0x2449, 0x2459 or 0x245D might need + * a workaround for hardware bug on 10 mbit half duplex (see linux driver eepro100.c) + * 2003/03/17 gbaum */ + + +PCI_DRIVER ( eepro100_driver, eepro100_nics, PCI_NO_CLASS ); + +DRIVER ( "EEPRO100", nic_driver, pci_driver, eepro100_driver, + eepro100_probe, eepro100_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/epic100.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/epic100.c new file mode 100644 index 0000000..aaa85f8 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/epic100.c @@ -0,0 +1,539 @@ + +/* epic100.c: A SMC 83c170 EPIC/100 fast ethernet driver for Etherboot */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +/* 05/06/2003 timlegge Fixed relocation and implemented Multicast */ +#define LINUX_OUT_MACROS + +#include "etherboot.h" +#include <gpxe/pci.h> +#include <gpxe/ethernet.h> +#include "nic.h" +#include "console.h" +#include "epic100.h" + +/* Condensed operations for readability */ +#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) +#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) + +#define TX_RING_SIZE 2 /* use at least 2 buffers for TX */ +#define RX_RING_SIZE 2 + +#define PKT_BUF_SZ 1536 /* Size of each temporary Tx/Rx buffer.*/ + +/* +#define DEBUG_RX +#define DEBUG_TX +#define DEBUG_EEPROM +*/ + +#define EPIC_DEBUG 0 /* debug level */ + +/* The EPIC100 Rx and Tx buffer descriptors. */ +struct epic_rx_desc { + unsigned long status; + unsigned long bufaddr; + unsigned long buflength; + unsigned long next; +}; +/* description of the tx descriptors control bits commonly used */ +#define TD_STDFLAGS TD_LASTDESC + +struct epic_tx_desc { + unsigned long status; + unsigned long bufaddr; + unsigned long buflength; + unsigned long next; +}; + +#define delay(nanosec) do { int _i = 3; while (--_i > 0) \ + { __SLOW_DOWN_IO; }} while (0) + +static void epic100_open(void); +static void epic100_init_ring(void); +static void epic100_disable(struct nic *nic); +static int epic100_poll(struct nic *nic, int retrieve); +static void epic100_transmit(struct nic *nic, const char *destaddr, + unsigned int type, unsigned int len, const char *data); +#ifdef DEBUG_EEPROM +static int read_eeprom(int location); +#endif +static int mii_read(int phy_id, int location); +static void epic100_irq(struct nic *nic, irq_action_t action); + +static struct nic_operations epic100_operations; + +static int ioaddr; + +static int command; +static int intstat; +static int intmask; +static int genctl ; +static int eectl ; +static int test ; +static int mmctl ; +static int mmdata ; +static int lan0 ; +static int mc0 ; +static int rxcon ; +static int txcon ; +static int prcdar ; +static int ptcdar ; +static int eththr ; + +static unsigned int cur_rx, cur_tx; /* The next free ring entry */ +#ifdef DEBUG_EEPROM +static unsigned short eeprom[64]; +#endif +static signed char phys[4]; /* MII device addresses. */ +struct { + struct epic_rx_desc rx_ring[RX_RING_SIZE] + __attribute__ ((aligned(4))); + struct epic_tx_desc tx_ring[TX_RING_SIZE] + __attribute__ ((aligned(4))); + unsigned char rx_packet[PKT_BUF_SZ * RX_RING_SIZE]; + unsigned char tx_packet[PKT_BUF_SZ * TX_RING_SIZE]; +} epic100_bufs __shared; +#define rx_ring epic100_bufs.rx_ring +#define tx_ring epic100_bufs.tx_ring +#define rx_packet epic100_bufs.rx_packet +#define tx_packet epic100_bufs.tx_packet + +/***********************************************************************/ +/* Externally visible functions */ +/***********************************************************************/ + + +static int +epic100_probe ( struct nic *nic, struct pci_device *pci ) { + + int i; + unsigned short* ap; + unsigned int phy, phy_idx; + + if (pci->ioaddr == 0) + return 0; + + /* Ideally we would detect all network cards in slot order. That would + be best done a central PCI probe dispatch, which wouldn't work + well with the current structure. So instead we detect just the + Epic cards in slot order. */ + + ioaddr = pci->ioaddr; + + nic->irqno = 0; + nic->ioaddr = pci->ioaddr & ~3; + + /* compute all used static epic100 registers address */ + command = ioaddr + COMMAND; /* Control Register */ + intstat = ioaddr + INTSTAT; /* Interrupt Status */ + intmask = ioaddr + INTMASK; /* Interrupt Mask */ + genctl = ioaddr + GENCTL; /* General Control */ + eectl = ioaddr + EECTL; /* EEPROM Control */ + test = ioaddr + TEST; /* Test register (clocks) */ + mmctl = ioaddr + MMCTL; /* MII Management Interface Control */ + mmdata = ioaddr + MMDATA; /* MII Management Interface Data */ + lan0 = ioaddr + LAN0; /* MAC address. (0x40-0x48) */ + mc0 = ioaddr + MC0; /* Multicast Control */ + rxcon = ioaddr + RXCON; /* Receive Control */ + txcon = ioaddr + TXCON; /* Transmit Control */ + prcdar = ioaddr + PRCDAR; /* PCI Receive Current Descr Address */ + ptcdar = ioaddr + PTCDAR; /* PCI Transmit Current Descr Address */ + eththr = ioaddr + ETHTHR; /* Early Transmit Threshold */ + + /* Reset the chip & bring it out of low-power mode. */ + outl(GC_SOFT_RESET, genctl); + + /* Disable ALL interrupts by setting the interrupt mask. */ + outl(INTR_DISABLE, intmask); + + /* + * set the internal clocks: + * Application Note 7.15 says: + * In order to set the CLOCK TEST bit in the TEST register, + * perform the following: + * + * Write 0x0008 to the test register at least sixteen + * consecutive times. + * + * The CLOCK TEST bit is Write-Only. Writing it several times + * consecutively insures a successful write to the bit... + */ + + for (i = 0; i < 16; i++) { + outl(0x00000008, test); + } + +#ifdef DEBUG_EEPROM +{ + unsigned short sum = 0; + unsigned short value; + for (i = 0; i < 64; i++) { + value = read_eeprom(i); + eeprom[i] = value; + sum += value; + } +} + +#if (EPIC_DEBUG > 1) + printf("EEPROM contents\n"); + for (i = 0; i < 64; i++) { + printf(" %hhX%s", eeprom[i], i % 16 == 15 ? "\n" : ""); + } +#endif +#endif + + /* This could also be read from the EEPROM. */ + ap = (unsigned short*)nic->node_addr; + for (i = 0; i < 3; i++) + *ap++ = inw(lan0 + i*4); + + DBG ( " I/O %4.4x %s ", ioaddr, eth_ntoa ( nic->node_addr ) ); + + /* Find the connected MII xcvrs. */ + for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(phys); phy++) { + int mii_status = mii_read(phy, 0); + + if (mii_status != 0xffff && mii_status != 0x0000) { + phys[phy_idx++] = phy; +#if (EPIC_DEBUG > 1) + printf("MII transceiver found at address %d.\n", phy); +#endif + } + } + if (phy_idx == 0) { +#if (EPIC_DEBUG > 1) + printf("***WARNING***: No MII transceiver found!\n"); +#endif + /* Use the known PHY address of the EPII. */ + phys[0] = 3; + } + + epic100_open(); + nic->nic_op = &epic100_operations; + + return 1; +} + +static void set_rx_mode(void) +{ + unsigned char mc_filter[8]; + int i; + memset(mc_filter, 0xff, sizeof(mc_filter)); + outl(0x0C, rxcon); + for(i = 0; i < 4; i++) + outw(((unsigned short *)mc_filter)[i], mc0 + i*4); + return; +} + + static void +epic100_open(void) +{ + int mii_reg5; + int full_duplex = 0; + unsigned long tmp; + + epic100_init_ring(); + + /* Pull the chip out of low-power mode, and set for PCI read multiple. */ + outl(GC_RX_FIFO_THR_64 | GC_MRC_READ_MULT | GC_ONE_COPY, genctl); + + outl(TX_FIFO_THRESH, eththr); + + tmp = TC_EARLY_TX_ENABLE | TX_SLOT_TIME; + + mii_reg5 = mii_read(phys[0], 5); + if (mii_reg5 != 0xffff && (mii_reg5 & 0x0100)) { + full_duplex = 1; + printf(" full-duplex mode"); + tmp |= TC_LM_FULL_DPX; + } else + tmp |= TC_LM_NORMAL; + + outl(tmp, txcon); + + /* Give adress of RX and TX ring to the chip */ + outl(virt_to_le32desc(&rx_ring), prcdar); + outl(virt_to_le32desc(&tx_ring), ptcdar); + + /* Start the chip's Rx process: receive unicast and broadcast */ + set_rx_mode(); + outl(CR_START_RX | CR_QUEUE_RX, command); + + putchar('\n'); +} + +/* Initialize the Rx and Tx rings. */ + static void +epic100_init_ring(void) +{ + int i; + + cur_rx = cur_tx = 0; + + for (i = 0; i < RX_RING_SIZE; i++) { + rx_ring[i].status = cpu_to_le32(RRING_OWN); /* Owned by Epic chip */ + rx_ring[i].buflength = cpu_to_le32(PKT_BUF_SZ); + rx_ring[i].bufaddr = virt_to_bus(&rx_packet[i * PKT_BUF_SZ]); + rx_ring[i].next = virt_to_le32desc(&rx_ring[i + 1]) ; + } + /* Mark the last entry as wrapping the ring. */ + rx_ring[i-1].next = virt_to_le32desc(&rx_ring[0]); + + /* + *The Tx buffer descriptor is filled in as needed, + * but we do need to clear the ownership bit. + */ + + for (i = 0; i < TX_RING_SIZE; i++) { + tx_ring[i].status = 0x0000; /* Owned by CPU */ + tx_ring[i].buflength = 0x0000 | cpu_to_le32(TD_STDFLAGS << 16); + tx_ring[i].bufaddr = virt_to_bus(&tx_packet[i * PKT_BUF_SZ]); + tx_ring[i].next = virt_to_le32desc(&tx_ring[i + 1]); + } + tx_ring[i-1].next = virt_to_le32desc(&tx_ring[0]); +} + +/* function: epic100_transmit + * This transmits a packet. + * + * Arguments: char d[6]: destination ethernet address. + * unsigned short t: ethernet protocol type. + * unsigned short s: size of the data-part of the packet. + * char *p: the data for the packet. + * returns: void. + */ + static void +epic100_transmit(struct nic *nic, const char *destaddr, unsigned int type, + unsigned int len, const char *data) +{ + unsigned short nstype; + unsigned char *txp; + int entry; + unsigned long ct; + + /* Calculate the next Tx descriptor entry. */ + entry = cur_tx % TX_RING_SIZE; + + if ((tx_ring[entry].status & TRING_OWN) == TRING_OWN) { + printf("eth_transmit: Unable to transmit. status=%4.4lx. Resetting...\n", + tx_ring[entry].status); + + epic100_open(); + return; + } + + txp = tx_packet + (entry * PKT_BUF_SZ); + + memcpy(txp, destaddr, ETH_ALEN); + memcpy(txp + ETH_ALEN, nic->node_addr, ETH_ALEN); + nstype = htons(type); + memcpy(txp + 12, (char*)&nstype, 2); + memcpy(txp + ETH_HLEN, data, len); + + len += ETH_HLEN; + len &= 0x0FFF; + while(len < ETH_ZLEN) + txp[len++] = '\0'; + /* + * Caution: the write order is important here, + * set the base address with the "ownership" + * bits last. + */ + + tx_ring[entry].buflength |= cpu_to_le32(len); + tx_ring[entry].status = cpu_to_le32(len << 16) | + cpu_to_le32(TRING_OWN); /* Pass ownership to the chip. */ + + cur_tx++; + + /* Trigger an immediate transmit demand. */ + outl(CR_QUEUE_TX, command); + + ct = currticks(); + /* timeout 10 ms for transmit */ + while ((le32_to_cpu(tx_ring[entry].status) & (TRING_OWN)) && + ct + 10*1000 < currticks()) + /* Wait */; + + if ((le32_to_cpu(tx_ring[entry].status) & TRING_OWN) != 0) + printf("Oops, transmitter timeout, status=%4.4lX\n", + tx_ring[entry].status); +} + +/* function: epic100_poll / eth_poll + * This receives a packet from the network. + * + * Arguments: none + * + * returns: 1 if a packet was received. + * 0 if no pacet was received. + * side effects: + * returns the packet in the array nic->packet. + * returns the length of the packet in nic->packetlen. + */ + + static int +epic100_poll(struct nic *nic, int retrieve) +{ + int entry; + int retcode; + int status; + entry = cur_rx % RX_RING_SIZE; + + if ((rx_ring[entry].status & cpu_to_le32(RRING_OWN)) == RRING_OWN) + return (0); + + if ( ! retrieve ) return 1; + + status = le32_to_cpu(rx_ring[entry].status); + /* We own the next entry, it's a new packet. Send it up. */ + +#if (EPIC_DEBUG > 4) + printf("epic_poll: entry %d status %hX\n", entry, status); +#endif + + cur_rx++; + if (status & 0x2000) { + printf("epic_poll: Giant packet\n"); + retcode = 0; + } else if (status & 0x0006) { + /* Rx Frame errors are counted in hardware. */ + printf("epic_poll: Frame received with errors\n"); + retcode = 0; + } else { + /* Omit the four octet CRC from the length. */ + nic->packetlen = le32_to_cpu((rx_ring[entry].buflength))- 4; + memcpy(nic->packet, &rx_packet[entry * PKT_BUF_SZ], nic->packetlen); + retcode = 1; + } + + /* Clear all error sources. */ + outl(status & INTR_CLEARERRS, intstat); + + /* Give the descriptor back to the chip */ + rx_ring[entry].status = RRING_OWN; + + /* Restart Receiver */ + outl(CR_START_RX | CR_QUEUE_RX, command); + + return retcode; +} + + +static void epic100_disable ( struct nic *nic __unused ) { + /* Soft reset the chip. */ + outl(GC_SOFT_RESET, genctl); +} + +static void epic100_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + +#ifdef DEBUG_EEPROM +/* Serial EEPROM section. */ + +/* EEPROM_Ctrl bits. */ +#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ +#define EE_CS 0x02 /* EEPROM chip select. */ +#define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */ +#define EE_WRITE_0 0x01 +#define EE_WRITE_1 0x09 +#define EE_DATA_READ 0x10 /* EEPROM chip data out. */ +#define EE_ENB (0x0001 | EE_CS) + +/* The EEPROM commands include the alway-set leading bit. */ +#define EE_WRITE_CMD (5 << 6) +#define EE_READ_CMD (6 << 6) +#define EE_ERASE_CMD (7 << 6) + +#define eeprom_delay(n) delay(n) + + static int +read_eeprom(int location) +{ + int i; + int retval = 0; + int read_cmd = location | EE_READ_CMD; + + outl(EE_ENB & ~EE_CS, eectl); + outl(EE_ENB, eectl); + + /* Shift the read command bits out. */ + for (i = 10; i >= 0; i--) { + short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + outl(EE_ENB | dataval, eectl); + eeprom_delay(100); + outl(EE_ENB | dataval | EE_SHIFT_CLK, eectl); + eeprom_delay(150); + outl(EE_ENB | dataval, eectl); /* Finish EEPROM a clock tick. */ + eeprom_delay(250); + } + outl(EE_ENB, eectl); + + for (i = 16; i > 0; i--) { + outl(EE_ENB | EE_SHIFT_CLK, eectl); + eeprom_delay(100); + retval = (retval << 1) | ((inl(eectl) & EE_DATA_READ) ? 1 : 0); + outl(EE_ENB, eectl); + eeprom_delay(100); + } + + /* Terminate the EEPROM access. */ + outl(EE_ENB & ~EE_CS, eectl); + return retval; +} +#endif + + +#define MII_READOP 1 +#define MII_WRITEOP 2 + + static int +mii_read(int phy_id, int location) +{ + int i; + + outl((phy_id << 9) | (location << 4) | MII_READOP, mmctl); + /* Typical operation takes < 50 ticks. */ + + for (i = 4000; i > 0; i--) + if ((inl(mmctl) & MII_READOP) == 0) + break; + return inw(mmdata); +} + +static struct nic_operations epic100_operations = { + .connect = dummy_connect, + .poll = epic100_poll, + .transmit = epic100_transmit, + .irq = epic100_irq, + +}; + +static struct pci_device_id epic100_nics[] = { +PCI_ROM(0x10b8, 0x0005, "epic100", "SMC EtherPowerII", 0), /* SMC 83c170 EPIC/100 */ +PCI_ROM(0x10b8, 0x0006, "smc-83c175", "SMC EPIC/C 83c175", 0), +}; + +PCI_DRIVER ( epic100_driver, epic100_nics, PCI_NO_CLASS ); + +DRIVER ( "EPIC100", nic_driver, pci_driver, epic100_driver, + epic100_probe, epic100_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/epic100.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/epic100.h new file mode 100644 index 0000000..f290b10 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/epic100.h @@ -0,0 +1,190 @@ +#ifndef _EPIC100_H_ +# define _EPIC100_H_ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#ifndef PCI_VENDOR_SMC +# define PCI_VENDOR_SMC 0x10B8 +#endif + +#ifndef PCI_DEVICE_SMC_EPIC100 +# define PCI_DEVICE_SMC_EPIC100 0x0005 +#endif + +#define PCI_DEVICE_ID_NONE 0xFFFF + +/* Offsets to registers (using SMC names). */ +enum epic100_registers { + COMMAND= 0, /* Control Register */ + INTSTAT= 4, /* Interrupt Status */ + INTMASK= 8, /* Interrupt Mask */ + GENCTL = 0x0C, /* General Control */ + NVCTL = 0x10, /* Non Volatile Control */ + EECTL = 0x14, /* EEPROM Control */ + TEST = 0x1C, /* Test register: marked as reserved (see in source code) */ + CRCCNT = 0x20, /* CRC Error Counter */ + ALICNT = 0x24, /* Frame Alignment Error Counter */ + MPCNT = 0x28, /* Missed Packet Counter */ + MMCTL = 0x30, /* MII Management Interface Control */ + MMDATA = 0x34, /* MII Management Interface Data */ + MIICFG = 0x38, /* MII Configuration */ + IPG = 0x3C, /* InterPacket Gap */ + LAN0 = 0x40, /* MAC address. (0x40-0x48) */ + IDCHK = 0x4C, /* BoardID/ Checksum */ + MC0 = 0x50, /* Multicast filter table. (0x50-0x5c) */ + RXCON = 0x60, /* Receive Control */ + TXCON = 0x70, /* Transmit Control */ + TXSTAT = 0x74, /* Transmit Status */ + PRCDAR = 0x84, /* PCI Receive Current Descriptor Address */ + PRSTAT = 0xA4, /* PCI Receive DMA Status */ + PRCPTHR= 0xB0, /* PCI Receive Copy Threshold */ + PTCDAR = 0xC4, /* PCI Transmit Current Descriptor Address */ + ETHTHR = 0xDC /* Early Transmit Threshold */ +}; + +/* Command register (CR_) bits */ +#define CR_STOP_RX (0x00000001) +#define CR_START_RX (0x00000002) +#define CR_QUEUE_TX (0x00000004) +#define CR_QUEUE_RX (0x00000008) +#define CR_NEXTFRAME (0x00000010) +#define CR_STOP_TX_DMA (0x00000020) +#define CR_STOP_RX_DMA (0x00000040) +#define CR_TX_UGO (0x00000080) + +/* Interrupt register bits. NI means No Interrupt generated */ + +#define INTR_RX_THR_STA (0x00400000) /* rx copy threshold status NI */ +#define INTR_RX_BUFF_EMPTY (0x00200000) /* rx buffers empty. NI */ +#define INTR_TX_IN_PROG (0x00100000) /* tx copy in progess. NI */ +#define INTR_RX_IN_PROG (0x00080000) /* rx copy in progress. NI */ +#define INTR_TXIDLE (0x00040000) /* tx idle. NI */ +#define INTR_RXIDLE (0x00020000) /* rx idle. NI */ +#define INTR_INTR_ACTIVE (0x00010000) /* Interrupt active. NI */ +#define INTR_RX_STATUS_OK (0x00008000) /* rx status valid. NI */ +#define INTR_PCI_TGT_ABT (0x00004000) /* PCI Target abort */ +#define INTR_PCI_MASTER_ABT (0x00002000) /* PCI Master abort */ +#define INTR_PCI_PARITY_ERR (0x00001000) /* PCI adress parity error */ +#define INTR_PCI_DATA_ERR (0x00000800) /* PCI data parity error */ +#define INTR_RX_THR_CROSSED (0x00000400) /* rx copy threshold crossed */ +#define INTR_CNTFULL (0x00000200) /* Counter overflow */ +#define INTR_TXUNDERRUN (0x00000100) /* tx underrun. */ +#define INTR_TXEMPTY (0x00000080) /* tx queue empty */ +#define INTR_TX_CH_COMPLETE (0x00000040) /* tx chain complete */ +#define INTR_TXDONE (0x00000020) /* tx complete (w or w/o err) */ +#define INTR_RXERROR (0x00000010) /* rx error (CRC) */ +#define INTR_RXOVERFLOW (0x00000008) /* rx buffer overflow */ +#define INTR_RX_QUEUE_EMPTY (0x00000004) /* rx queue empty. */ +#define INTR_RXHEADER (0x00000002) /* header copy complete */ +#define INTR_RXDONE (0x00000001) /* Receive copy complete */ + +#define INTR_CLEARINTR (0x00007FFF) +#define INTR_VALIDBITS (0x007FFFFF) +#define INTR_DISABLE (0x00000000) +#define INTR_CLEARERRS (0x00007F18) +#define INTR_ABNINTR (INTR_CNTFULL | INTR_TXUNDERRUN | INTR_RXOVERFLOW) + +/* General Control (GC_) bits */ + +#define GC_SOFT_RESET (0x00000001) +#define GC_INTR_ENABLE (0x00000002) +#define GC_SOFT_INTR (0x00000004) +#define GC_POWER_DOWN (0x00000008) +#define GC_ONE_COPY (0x00000010) +#define GC_BIG_ENDIAN (0x00000020) +#define GC_RX_PREEMPT_TX (0x00000040) +#define GC_TX_PREEMPT_RX (0x00000080) + +/* + * Receive FIFO Threshold values + * Control the level at which the PCI burst state machine + * begins to empty the receive FIFO. Possible values: 0-3 + * + * 0 => 32, 1 => 64, 2 => 96 3 => 128 bytes. + */ +#define GC_RX_FIFO_THR_32 (0x00000000) +#define GC_RX_FIFO_THR_64 (0x00000100) +#define GC_RX_FIFO_THR_96 (0x00000200) +#define GC_RX_FIFO_THR_128 (0x00000300) + +/* Memory Read Control (MRC_) values */ +#define GC_MRC_MEM_READ (0x00000000) +#define GC_MRC_READ_MULT (0x00000400) +#define GC_MRC_READ_LINE (0x00000800) + +#define GC_SOFTBIT0 (0x00001000) +#define GC_SOFTBIT1 (0x00002000) +#define GC_RESET_PHY (0x00004000) + +/* Definitions of the Receive Control (RC_) register bits */ + +#define RC_SAVE_ERRORED_PKT (0x00000001) +#define RC_SAVE_RUNT_FRAMES (0x00000002) +#define RC_RCV_BROADCAST (0x00000004) +#define RC_RCV_MULTICAST (0x00000008) +#define RC_RCV_INVERSE_PKT (0x00000010) +#define RC_PROMISCUOUS_MODE (0x00000020) +#define RC_MONITOR_MODE (0x00000040) +#define RC_EARLY_RCV_ENABLE (0x00000080) + +/* description of the rx descriptors control bits */ +#define RD_FRAGLIST (0x0001) /* Desc points to a fragment list */ +#define RD_LLFORM (0x0002) /* Frag list format */ +#define RD_HDR_CPY (0x0004) /* Desc used for header copy */ + +/* Definition of the Transmit CONTROL (TC) register bits */ + +#define TC_EARLY_TX_ENABLE (0x00000001) + +/* Loopback Mode (LM_) Select valuesbits */ +#define TC_LM_NORMAL (0x00000000) +#define TC_LM_INTERNAL (0x00000002) +#define TC_LM_EXTERNAL (0x00000004) +#define TC_LM_FULL_DPX (0x00000006) + +#define TX_SLOT_TIME (0x00000078) + +/* Bytes transferred to chip before transmission starts. */ +#define TX_FIFO_THRESH 128 /* Rounded down to 4 byte units. */ + +/* description of rx descriptors status bits */ +#define RRING_PKT_INTACT (0x0001) +#define RRING_ALIGN_ERR (0x0002) +#define RRING_CRC_ERR (0x0004) +#define RRING_MISSED_PKT (0x0008) +#define RRING_MULTICAST (0x0010) +#define RRING_BROADCAST (0x0020) +#define RRING_RECEIVER_DISABLE (0x0040) +#define RRING_STATUS_VALID (0x1000) +#define RRING_FRAGLIST_ERR (0x2000) +#define RRING_HDR_COPIED (0x4000) +#define RRING_OWN (0x8000) + +/* error summary */ +#define RRING_ERROR (RRING_ALIGN_ERR|RRING_CRC_ERR) + +/* description of tx descriptors status bits */ +#define TRING_PKT_INTACT (0x0001) /* pkt transmitted. */ +#define TRING_PKT_NONDEFER (0x0002) /* pkt xmitted w/o deferring */ +#define TRING_COLL (0x0004) /* pkt xmitted w collisions */ +#define TRING_CARR (0x0008) /* carrier sense lost */ +#define TRING_UNDERRUN (0x0010) /* DMA underrun */ +#define TRING_HB_COLL (0x0020) /* Collision detect Heartbeat */ +#define TRING_WIN_COLL (0x0040) /* out of window collision */ +#define TRING_DEFERRED (0x0080) /* Deferring */ +#define TRING_COLL_COUNT (0x0F00) /* collision counter (mask) */ +#define TRING_COLL_EXCESS (0x1000) /* tx aborted: excessive colls */ +#define TRING_OWN (0x8000) /* desc ownership bit */ + +/* error summary */ +#define TRING_ABORT (TRING_COLL_EXCESS|TRING_WIN_COLL|TRING_UNDERRUN) +#define TRING_ERROR (TRING_DEFERRED|TRING_WIN_COLL|TRING_UNDERRUN|TRING_CARR/*|TRING_COLL*/ ) + +/* description of the tx descriptors control bits */ +#define TD_FRAGLIST (0x0001) /* Desc points to a fragment list */ +#define TD_LLFORM (0x0002) /* Frag list format */ +#define TD_IAF (0x0004) /* Generate Interrupt after tx */ +#define TD_NOCRC (0x0008) /* No CRC generated */ +#define TD_LASTDESC (0x0010) /* Last desc for this frame */ + +#endif /* _EPIC100_H_ */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/etherfabric.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/etherfabric.c new file mode 100644 index 0000000..c4296b9 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/etherfabric.c @@ -0,0 +1,4236 @@ +/************************************************************************** + * + * Etherboot driver for Level 5 Etherfabric network cards + * + * Written by Michael Brown <mbrown@fensystems.co.uk> + * + * Copyright Fen Systems Ltd. 2005 + * Copyright Level 5 Networks Inc. 2005 + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL), incorporated herein by + * reference. Drivers based on or derived from this code fall under + * the GPL and must retain the authorship, copyright and license + * notice. + * + ************************************************************************** + */ + +FILE_LICENCE ( GPL_ANY ); + +#include <stdint.h> +#include <stdlib.h> +#include <unistd.h> +#include <errno.h> +#include <assert.h> +#include <byteswap.h> +#include <console.h> +#include <gpxe/io.h> +#include <gpxe/pci.h> +#include <gpxe/malloc.h> +#include <gpxe/ethernet.h> +#include <gpxe/iobuf.h> +#include <gpxe/netdevice.h> +#include <gpxe/timer.h> +#include <mii.h> +#include "etherfabric.h" +#include "etherfabric_nic.h" + +/************************************************************************** + * + * Constants and macros + * + ************************************************************************** + */ + +#define EFAB_REGDUMP(...) +#define EFAB_TRACE(...) DBGP(__VA_ARGS__) + +// printf() is not allowed within drivers. Use DBG() instead. +#define EFAB_LOG(...) DBG(__VA_ARGS__) +#define EFAB_ERR(...) DBG(__VA_ARGS__) + +#define FALCON_USE_IO_BAR 0 + +#define HZ 100 +#define EFAB_BYTE 1 + +/************************************************************************** + * + * Hardware data structures and sizing + * + ************************************************************************** + */ +extern int __invalid_queue_size; +#define FQS(_prefix, _x) \ + ( ( (_x) == 512 ) ? _prefix ## _SIZE_512 : \ + ( ( (_x) == 1024 ) ? _prefix ## _SIZE_1K : \ + ( ( (_x) == 2048 ) ? _prefix ## _SIZE_2K : \ + ( ( (_x) == 4096) ? _prefix ## _SIZE_4K : \ + __invalid_queue_size ) ) ) ) + + +#define EFAB_MAX_FRAME_LEN(mtu) \ + ( ( ( ( mtu ) + 4/* FCS */ ) + 7 ) & ~7 ) + +/************************************************************************** + * + * GMII routines + * + ************************************************************************** + */ + +static void falcon_mdio_write (struct efab_nic *efab, int device, + int location, int value ); +static int falcon_mdio_read ( struct efab_nic *efab, int device, int location ); + +/* GMII registers */ +#define GMII_PSSR 0x11 /* PHY-specific status register */ + +/* Pseudo extensions to the link partner ability register */ +#define LPA_EF_1000FULL 0x00020000 +#define LPA_EF_1000HALF 0x00010000 +#define LPA_EF_10000FULL 0x00040000 +#define LPA_EF_10000HALF 0x00080000 + +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) +#define LPA_EF_1000 ( LPA_EF_1000FULL | LPA_EF_1000HALF ) +#define LPA_EF_10000 ( LPA_EF_10000FULL | LPA_EF_10000HALF ) +#define LPA_EF_DUPLEX ( LPA_10FULL | LPA_100FULL | LPA_EF_1000FULL | \ + LPA_EF_10000FULL ) + +/* Mask of bits not associated with speed or duplexity. */ +#define LPA_OTHER ~( LPA_10FULL | LPA_10HALF | LPA_100FULL | \ + LPA_100HALF | LPA_EF_1000FULL | LPA_EF_1000HALF ) + +/* PHY-specific status register */ +#define PSSR_LSTATUS 0x0400 /* Bit 10 - link status */ + +/** + * Retrieve GMII autonegotiation advertised abilities + * + */ +static unsigned int +gmii_autoneg_advertised ( struct efab_nic *efab ) +{ + unsigned int mii_advertise; + unsigned int gmii_advertise; + + /* Extended bits are in bits 8 and 9 of MII_CTRL1000 */ + mii_advertise = falcon_mdio_read ( efab, 0, MII_ADVERTISE ); + gmii_advertise = ( ( falcon_mdio_read ( efab, 0, MII_CTRL1000 ) >> 8 ) + & 0x03 ); + return ( ( gmii_advertise << 16 ) | mii_advertise ); +} + +/** + * Retrieve GMII autonegotiation link partner abilities + * + */ +static unsigned int +gmii_autoneg_lpa ( struct efab_nic *efab ) +{ + unsigned int mii_lpa; + unsigned int gmii_lpa; + + /* Extended bits are in bits 10 and 11 of MII_STAT1000 */ + mii_lpa = falcon_mdio_read ( efab, 0, MII_LPA ); + gmii_lpa = ( falcon_mdio_read ( efab, 0, MII_STAT1000 ) >> 10 ) & 0x03; + return ( ( gmii_lpa << 16 ) | mii_lpa ); +} + +/** + * Calculate GMII autonegotiated link technology + * + */ +static unsigned int +gmii_nway_result ( unsigned int negotiated ) +{ + unsigned int other_bits; + + /* Mask out the speed and duplexity bits */ + other_bits = negotiated & LPA_OTHER; + + if ( negotiated & LPA_EF_1000FULL ) + return ( other_bits | LPA_EF_1000FULL ); + else if ( negotiated & LPA_EF_1000HALF ) + return ( other_bits | LPA_EF_1000HALF ); + else if ( negotiated & LPA_100FULL ) + return ( other_bits | LPA_100FULL ); + else if ( negotiated & LPA_100BASE4 ) + return ( other_bits | LPA_100BASE4 ); + else if ( negotiated & LPA_100HALF ) + return ( other_bits | LPA_100HALF ); + else if ( negotiated & LPA_10FULL ) + return ( other_bits | LPA_10FULL ); + else return ( other_bits | LPA_10HALF ); +} + +/** + * Check GMII PHY link status + * + */ +static int +gmii_link_ok ( struct efab_nic *efab ) +{ + int status; + int phy_status; + + /* BMSR is latching - it returns "link down" if the link has + * been down at any point since the last read. To get a + * real-time status, we therefore read the register twice and + * use the result of the second read. + */ + (void) falcon_mdio_read ( efab, 0, MII_BMSR ); + status = falcon_mdio_read ( efab, 0, MII_BMSR ); + + /* Read the PHY-specific Status Register. This is + * non-latching, so we need do only a single read. + */ + phy_status = falcon_mdio_read ( efab, 0, GMII_PSSR ); + + return ( ( status & BMSR_LSTATUS ) && ( phy_status & PSSR_LSTATUS ) ); +} + +/************************************************************************** + * + * MDIO routines + * + ************************************************************************** + */ + +/* Numbering of the MDIO Manageable Devices (MMDs) */ +/* Physical Medium Attachment/ Physical Medium Dependent sublayer */ +#define MDIO_MMD_PMAPMD (1) +/* WAN Interface Sublayer */ +#define MDIO_MMD_WIS (2) +/* Physical Coding Sublayer */ +#define MDIO_MMD_PCS (3) +/* PHY Extender Sublayer */ +#define MDIO_MMD_PHYXS (4) +/* Extender Sublayer */ +#define MDIO_MMD_DTEXS (5) +/* Transmission convergence */ +#define MDIO_MMD_TC (6) +/* Auto negotiation */ +#define MDIO_MMD_AN (7) + +/* Generic register locations */ +#define MDIO_MMDREG_CTRL1 (0) +#define MDIO_MMDREG_STAT1 (1) +#define MDIO_MMDREG_DEVS0 (5) +#define MDIO_MMDREG_STAT2 (8) + +/* Bits in MMDREG_CTRL1 */ +/* Reset */ +#define MDIO_MMDREG_CTRL1_RESET_LBN (15) +#define MDIO_MMDREG_CTRL1_RESET_WIDTH (1) + +/* Bits in MMDREG_STAT1 */ +#define MDIO_MMDREG_STAT1_FAULT_LBN (7) +#define MDIO_MMDREG_STAT1_FAULT_WIDTH (1) + +/* Link state */ +#define MDIO_MMDREG_STAT1_LINK_LBN (2) +#define MDIO_MMDREG_STAT1_LINK_WIDTH (1) + +/* Bits in MMDREG_DEVS0. */ +#define DEV_PRESENT_BIT(_b) (1 << _b) + +#define MDIO_MMDREG_DEVS0_DTEXS DEV_PRESENT_BIT(MDIO_MMD_DTEXS) +#define MDIO_MMDREG_DEVS0_PHYXS DEV_PRESENT_BIT(MDIO_MMD_PHYXS) +#define MDIO_MMDREG_DEVS0_PCS DEV_PRESENT_BIT(MDIO_MMD_PCS) +#define MDIO_MMDREG_DEVS0_WIS DEV_PRESENT_BIT(MDIO_MMD_WIS) +#define MDIO_MMDREG_DEVS0_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD) + +#define MDIO_MMDREG_DEVS0_AN DEV_PRESENT_BIT(MDIO_MMD_AN) + +/* Bits in MMDREG_STAT2 */ +#define MDIO_MMDREG_STAT2_PRESENT_VAL (2) +#define MDIO_MMDREG_STAT2_PRESENT_LBN (14) +#define MDIO_MMDREG_STAT2_PRESENT_WIDTH (2) + +/* PHY XGXS lane state */ +#define MDIO_PHYXS_LANE_STATE (0x18) +#define MDIO_PHYXS_LANE_ALIGNED_LBN (12) +#define MDIO_PHYXS_LANE_SYNC0_LBN (0) +#define MDIO_PHYXS_LANE_SYNC1_LBN (1) +#define MDIO_PHYXS_LANE_SYNC2_LBN (2) +#define MDIO_PHYXS_LANE_SYNC3_LBN (3) + +/* This ought to be ridiculous overkill. We expect it to fail rarely */ +#define MDIO45_RESET_TRIES 100 +#define MDIO45_RESET_SPINTIME 10 + +static int +mdio_clause45_wait_reset_mmds ( struct efab_nic* efab ) +{ + int tries = MDIO45_RESET_TRIES; + int in_reset; + + while(tries) { + int mask = efab->phy_op->mmds; + int mmd = 0; + in_reset = 0; + while(mask) { + if (mask & 1) { + int stat = falcon_mdio_read ( efab, mmd, + MDIO_MMDREG_CTRL1 ); + if (stat < 0) { + EFAB_ERR("Failed to read status of MMD %d\n", + mmd ); + in_reset = 1; + break; + } + if (stat & (1 << MDIO_MMDREG_CTRL1_RESET_LBN)) + in_reset |= (1 << mmd); + } + mask = mask >> 1; + mmd++; + } + if (!in_reset) + break; + tries--; + mdelay ( MDIO45_RESET_SPINTIME ); + } + if (in_reset != 0) { + EFAB_ERR("Not all MMDs came out of reset in time. MMDs " + "still in reset: %x\n", in_reset); + return -ETIMEDOUT; + } + return 0; +} + +static int +mdio_clause45_reset_mmd ( struct efab_nic *efab, int mmd ) +{ + int tries = MDIO45_RESET_TRIES; + int ctrl; + + falcon_mdio_write ( efab, mmd, MDIO_MMDREG_CTRL1, + ( 1 << MDIO_MMDREG_CTRL1_RESET_LBN ) ); + + /* Wait for the reset bit to clear. */ + do { + mdelay ( MDIO45_RESET_SPINTIME ); + + ctrl = falcon_mdio_read ( efab, mmd, MDIO_MMDREG_CTRL1 ); + if ( ~ctrl & ( 1 << MDIO_MMDREG_CTRL1_RESET_LBN ) ) + return 0; + } while ( --tries ); + + EFAB_ERR ( "Failed to reset mmd %d\n", mmd ); + + return -ETIMEDOUT; +} + +static int +mdio_clause45_links_ok(struct efab_nic *efab ) +{ + int status, good; + int ok = 1; + int mmd = 0; + int mmd_mask = efab->phy_op->mmds; + + while (mmd_mask) { + if (mmd_mask & 1) { + /* Double reads because link state is latched, and a + * read moves the current state into the register */ + status = falcon_mdio_read ( efab, mmd, + MDIO_MMDREG_STAT1 ); + status = falcon_mdio_read ( efab, mmd, + MDIO_MMDREG_STAT1 ); + + good = status & (1 << MDIO_MMDREG_STAT1_LINK_LBN); + ok = ok && good; + } + mmd_mask = (mmd_mask >> 1); + mmd++; + } + return ok; +} + +static int +mdio_clause45_check_mmds ( struct efab_nic *efab ) +{ + int mmd = 0; + int devices = falcon_mdio_read ( efab, MDIO_MMD_PHYXS, + MDIO_MMDREG_DEVS0 ); + int mmd_mask = efab->phy_op->mmds; + + /* Check all the expected MMDs are present */ + if ( devices < 0 ) { + EFAB_ERR ( "Failed to read devices present\n" ); + return -EIO; + } + if ( ( devices & mmd_mask ) != mmd_mask ) { + EFAB_ERR ( "required MMDs not present: got %x, wanted %x\n", + devices, mmd_mask ); + return -EIO; + } + + /* Check all required MMDs are responding and happy. */ + while ( mmd_mask ) { + if ( mmd_mask & 1 ) { + efab_dword_t reg; + int status; + reg.opaque = falcon_mdio_read ( efab, mmd, + MDIO_MMDREG_STAT2 ); + status = EFAB_DWORD_FIELD ( reg, + MDIO_MMDREG_STAT2_PRESENT ); + if ( status != MDIO_MMDREG_STAT2_PRESENT_VAL ) { + + + return -EIO; + } + } + mmd_mask >>= 1; + mmd++; + } + + return 0; +} + +/* I/O BAR address register */ +#define FCN_IOM_IND_ADR_REG 0x0 + +/* I/O BAR data register */ +#define FCN_IOM_IND_DAT_REG 0x4 + +/* Address region register */ +#define FCN_ADR_REGION_REG_KER 0x00 +#define FCN_ADR_REGION0_LBN 0 +#define FCN_ADR_REGION0_WIDTH 18 +#define FCN_ADR_REGION1_LBN 32 +#define FCN_ADR_REGION1_WIDTH 18 +#define FCN_ADR_REGION2_LBN 64 +#define FCN_ADR_REGION2_WIDTH 18 +#define FCN_ADR_REGION3_LBN 96 +#define FCN_ADR_REGION3_WIDTH 18 + +/* Interrupt enable register */ +#define FCN_INT_EN_REG_KER 0x0010 +#define FCN_MEM_PERR_INT_EN_KER_LBN 5 +#define FCN_MEM_PERR_INT_EN_KER_WIDTH 1 +#define FCN_KER_INT_CHAR_LBN 4 +#define FCN_KER_INT_CHAR_WIDTH 1 +#define FCN_KER_INT_KER_LBN 3 +#define FCN_KER_INT_KER_WIDTH 1 +#define FCN_ILL_ADR_ERR_INT_EN_KER_LBN 2 +#define FCN_ILL_ADR_ERR_INT_EN_KER_WIDTH 1 +#define FCN_SRM_PERR_INT_EN_KER_LBN 1 +#define FCN_SRM_PERR_INT_EN_KER_WIDTH 1 +#define FCN_DRV_INT_EN_KER_LBN 0 +#define FCN_DRV_INT_EN_KER_WIDTH 1 + +/* Interrupt status register */ +#define FCN_INT_ADR_REG_KER 0x0030 +#define FCN_INT_ADR_KER_LBN 0 +#define FCN_INT_ADR_KER_WIDTH EFAB_DMA_TYPE_WIDTH ( 64 ) + +/* Interrupt status register (B0 only) */ +#define INT_ISR0_B0 0x90 +#define INT_ISR1_B0 0xA0 + +/* Interrupt acknowledge register (A0/A1 only) */ +#define FCN_INT_ACK_KER_REG_A1 0x0050 +#define INT_ACK_DUMMY_DATA_LBN 0 +#define INT_ACK_DUMMY_DATA_WIDTH 32 + +/* Interrupt acknowledge work-around register (A0/A1 only )*/ +#define WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 0x0070 + +/* Hardware initialisation register */ +#define FCN_HW_INIT_REG_KER 0x00c0 +#define FCN_BCSR_TARGET_MASK_LBN 101 +#define FCN_BCSR_TARGET_MASK_WIDTH 4 + +/* SPI host command register */ +#define FCN_EE_SPI_HCMD_REG 0x0100 +#define FCN_EE_SPI_HCMD_CMD_EN_LBN 31 +#define FCN_EE_SPI_HCMD_CMD_EN_WIDTH 1 +#define FCN_EE_WR_TIMER_ACTIVE_LBN 28 +#define FCN_EE_WR_TIMER_ACTIVE_WIDTH 1 +#define FCN_EE_SPI_HCMD_SF_SEL_LBN 24 +#define FCN_EE_SPI_HCMD_SF_SEL_WIDTH 1 +#define FCN_EE_SPI_EEPROM 0 +#define FCN_EE_SPI_FLASH 1 +#define FCN_EE_SPI_HCMD_DABCNT_LBN 16 +#define FCN_EE_SPI_HCMD_DABCNT_WIDTH 5 +#define FCN_EE_SPI_HCMD_READ_LBN 15 +#define FCN_EE_SPI_HCMD_READ_WIDTH 1 +#define FCN_EE_SPI_READ 1 +#define FCN_EE_SPI_WRITE 0 +#define FCN_EE_SPI_HCMD_DUBCNT_LBN 12 +#define FCN_EE_SPI_HCMD_DUBCNT_WIDTH 2 +#define FCN_EE_SPI_HCMD_ADBCNT_LBN 8 +#define FCN_EE_SPI_HCMD_ADBCNT_WIDTH 2 +#define FCN_EE_SPI_HCMD_ENC_LBN 0 +#define FCN_EE_SPI_HCMD_ENC_WIDTH 8 + +/* SPI host address register */ +#define FCN_EE_SPI_HADR_REG 0x0110 +#define FCN_EE_SPI_HADR_DUBYTE_LBN 24 +#define FCN_EE_SPI_HADR_DUBYTE_WIDTH 8 +#define FCN_EE_SPI_HADR_ADR_LBN 0 +#define FCN_EE_SPI_HADR_ADR_WIDTH 24 + +/* SPI host data register */ +#define FCN_EE_SPI_HDATA_REG 0x0120 +#define FCN_EE_SPI_HDATA3_LBN 96 +#define FCN_EE_SPI_HDATA3_WIDTH 32 +#define FCN_EE_SPI_HDATA2_LBN 64 +#define FCN_EE_SPI_HDATA2_WIDTH 32 +#define FCN_EE_SPI_HDATA1_LBN 32 +#define FCN_EE_SPI_HDATA1_WIDTH 32 +#define FCN_EE_SPI_HDATA0_LBN 0 +#define FCN_EE_SPI_HDATA0_WIDTH 32 + +/* VPD Config 0 Register register */ +#define FCN_EE_VPD_CFG_REG 0x0140 +#define FCN_EE_VPD_EN_LBN 0 +#define FCN_EE_VPD_EN_WIDTH 1 +#define FCN_EE_VPD_EN_AD9_MODE_LBN 1 +#define FCN_EE_VPD_EN_AD9_MODE_WIDTH 1 +#define FCN_EE_EE_CLOCK_DIV_LBN 112 +#define FCN_EE_EE_CLOCK_DIV_WIDTH 7 +#define FCN_EE_SF_CLOCK_DIV_LBN 120 +#define FCN_EE_SF_CLOCK_DIV_WIDTH 7 + + +/* NIC status register */ +#define FCN_NIC_STAT_REG 0x0200 +#define FCN_ONCHIP_SRAM_LBN 16 +#define FCN_ONCHIP_SRAM_WIDTH 1 +#define FCN_SF_PRST_LBN 9 +#define FCN_SF_PRST_WIDTH 1 +#define FCN_EE_PRST_LBN 8 +#define FCN_EE_PRST_WIDTH 1 +#define FCN_EE_STRAP_LBN 7 +#define FCN_EE_STRAP_WIDTH 1 +#define FCN_PCI_PCIX_MODE_LBN 4 +#define FCN_PCI_PCIX_MODE_WIDTH 3 +#define FCN_PCI_PCIX_MODE_PCI33_DECODE 0 +#define FCN_PCI_PCIX_MODE_PCI66_DECODE 1 +#define FCN_PCI_PCIX_MODE_PCIX66_DECODE 5 +#define FCN_PCI_PCIX_MODE_PCIX100_DECODE 6 +#define FCN_PCI_PCIX_MODE_PCIX133_DECODE 7 +#define FCN_STRAP_ISCSI_EN_LBN 3 +#define FCN_STRAP_ISCSI_EN_WIDTH 1 +#define FCN_STRAP_PINS_LBN 0 +#define FCN_STRAP_PINS_WIDTH 3 +#define FCN_STRAP_10G_LBN 2 +#define FCN_STRAP_10G_WIDTH 1 +#define FCN_STRAP_DUAL_PORT_LBN 1 +#define FCN_STRAP_DUAL_PORT_WIDTH 1 +#define FCN_STRAP_PCIE_LBN 0 +#define FCN_STRAP_PCIE_WIDTH 1 + +/* Falcon revisions */ +#define FALCON_REV_A0 0 +#define FALCON_REV_A1 1 +#define FALCON_REV_B0 2 + +/* GPIO control register */ +#define FCN_GPIO_CTL_REG_KER 0x0210 +#define FCN_GPIO_CTL_REG_KER 0x0210 + +#define FCN_GPIO3_OEN_LBN 27 +#define FCN_GPIO3_OEN_WIDTH 1 +#define FCN_GPIO2_OEN_LBN 26 +#define FCN_GPIO2_OEN_WIDTH 1 +#define FCN_GPIO1_OEN_LBN 25 +#define FCN_GPIO1_OEN_WIDTH 1 +#define FCN_GPIO0_OEN_LBN 24 +#define FCN_GPIO0_OEN_WIDTH 1 + +#define FCN_GPIO3_OUT_LBN 19 +#define FCN_GPIO3_OUT_WIDTH 1 +#define FCN_GPIO2_OUT_LBN 18 +#define FCN_GPIO2_OUT_WIDTH 1 +#define FCN_GPIO1_OUT_LBN 17 +#define FCN_GPIO1_OUT_WIDTH 1 +#define FCN_GPIO0_OUT_LBN 16 +#define FCN_GPIO0_OUT_WIDTH 1 + +#define FCN_GPIO3_IN_LBN 11 +#define FCN_GPIO3_IN_WIDTH 1 +#define FCN_GPIO2_IN_LBN 10 +#define FCN_GPIO2_IN_WIDTH 1 +#define FCN_GPIO1_IN_LBN 9 +#define FCN_GPIO1_IN_WIDTH 1 +#define FCN_GPIO0_IN_LBN 8 +#define FCN_GPIO0_IN_WIDTH 1 + +#define FCN_FLASH_PRESENT_LBN 7 +#define FCN_FLASH_PRESENT_WIDTH 1 +#define FCN_EEPROM_PRESENT_LBN 6 +#define FCN_EEPROM_PRESENT_WIDTH 1 +#define FCN_BOOTED_USING_NVDEVICE_LBN 3 +#define FCN_BOOTED_USING_NVDEVICE_WIDTH 1 + +/* Defines for extra non-volatile storage */ +#define FCN_NV_MAGIC_NUMBER 0xFA1C + +/* Global control register */ +#define FCN_GLB_CTL_REG_KER 0x0220 +#define FCN_EXT_PHY_RST_CTL_LBN 63 +#define FCN_EXT_PHY_RST_CTL_WIDTH 1 +#define FCN_PCIE_SD_RST_CTL_LBN 61 +#define FCN_PCIE_SD_RST_CTL_WIDTH 1 +#define FCN_PCIE_STCK_RST_CTL_LBN 59 +#define FCN_PCIE_STCK_RST_CTL_WIDTH 1 +#define FCN_PCIE_NSTCK_RST_CTL_LBN 58 +#define FCN_PCIE_NSTCK_RST_CTL_WIDTH 1 +#define FCN_PCIE_CORE_RST_CTL_LBN 57 +#define FCN_PCIE_CORE_RST_CTL_WIDTH 1 +#define FCN_EE_RST_CTL_LBN 49 +#define FCN_EE_RST_CTL_WIDTH 1 +#define FCN_RST_EXT_PHY_LBN 31 +#define FCN_RST_EXT_PHY_WIDTH 1 +#define FCN_EXT_PHY_RST_DUR_LBN 1 +#define FCN_EXT_PHY_RST_DUR_WIDTH 3 +#define FCN_SWRST_LBN 0 +#define FCN_SWRST_WIDTH 1 +#define INCLUDE_IN_RESET 0 +#define EXCLUDE_FROM_RESET 1 + +/* FPGA build version */ +#define FCN_ALTERA_BUILD_REG_KER 0x0300 +#define FCN_VER_MAJOR_LBN 24 +#define FCN_VER_MAJOR_WIDTH 8 +#define FCN_VER_MINOR_LBN 16 +#define FCN_VER_MINOR_WIDTH 8 +#define FCN_VER_BUILD_LBN 0 +#define FCN_VER_BUILD_WIDTH 16 +#define FCN_VER_ALL_LBN 0 +#define FCN_VER_ALL_WIDTH 32 + +/* Spare EEPROM bits register (flash 0x390) */ +#define FCN_SPARE_REG_KER 0x310 +#define FCN_MEM_PERR_EN_TX_DATA_LBN 72 +#define FCN_MEM_PERR_EN_TX_DATA_WIDTH 2 + +/* Timer table for kernel access */ +#define FCN_TIMER_CMD_REG_KER 0x420 +#define FCN_TIMER_MODE_LBN 12 +#define FCN_TIMER_MODE_WIDTH 2 +#define FCN_TIMER_MODE_DIS 0 +#define FCN_TIMER_MODE_INT_HLDOFF 1 +#define FCN_TIMER_VAL_LBN 0 +#define FCN_TIMER_VAL_WIDTH 12 + +/* Receive configuration register */ +#define FCN_RX_CFG_REG_KER 0x800 +#define FCN_RX_XOFF_EN_LBN 0 +#define FCN_RX_XOFF_EN_WIDTH 1 + +/* SRAM receive descriptor cache configuration register */ +#define FCN_SRM_RX_DC_CFG_REG_KER 0x610 +#define FCN_SRM_RX_DC_BASE_ADR_LBN 0 +#define FCN_SRM_RX_DC_BASE_ADR_WIDTH 21 + +/* SRAM transmit descriptor cache configuration register */ +#define FCN_SRM_TX_DC_CFG_REG_KER 0x620 +#define FCN_SRM_TX_DC_BASE_ADR_LBN 0 +#define FCN_SRM_TX_DC_BASE_ADR_WIDTH 21 + +/* SRAM configuration register */ +#define FCN_SRM_CFG_REG_KER 0x630 +#define FCN_SRAM_OOB_ADR_INTEN_LBN 5 +#define FCN_SRAM_OOB_ADR_INTEN_WIDTH 1 +#define FCN_SRAM_OOB_BUF_INTEN_LBN 4 +#define FCN_SRAM_OOB_BUF_INTEN_WIDTH 1 +#define FCN_SRAM_OOB_BT_INIT_EN_LBN 3 +#define FCN_SRAM_OOB_BT_INIT_EN_WIDTH 1 +#define FCN_SRM_NUM_BANK_LBN 2 +#define FCN_SRM_NUM_BANK_WIDTH 1 +#define FCN_SRM_BANK_SIZE_LBN 0 +#define FCN_SRM_BANK_SIZE_WIDTH 2 +#define FCN_SRM_NUM_BANKS_AND_BANK_SIZE_LBN 0 +#define FCN_SRM_NUM_BANKS_AND_BANK_SIZE_WIDTH 3 + +#define FCN_RX_CFG_REG_KER 0x800 +#define FCN_RX_INGR_EN_B0_LBN 47 +#define FCN_RX_INGR_EN_B0_WIDTH 1 +#define FCN_RX_USR_BUF_SIZE_B0_LBN 19 +#define FCN_RX_USR_BUF_SIZE_B0_WIDTH 9 +#define FCN_RX_XON_MAC_TH_B0_LBN 10 +#define FCN_RX_XON_MAC_TH_B0_WIDTH 9 +#define FCN_RX_XOFF_MAC_TH_B0_LBN 1 +#define FCN_RX_XOFF_MAC_TH_B0_WIDTH 9 +#define FCN_RX_XOFF_MAC_EN_B0_LBN 0 +#define FCN_RX_XOFF_MAC_EN_B0_WIDTH 1 +#define FCN_RX_USR_BUF_SIZE_A1_LBN 11 +#define FCN_RX_USR_BUF_SIZE_A1_WIDTH 9 +#define FCN_RX_XON_MAC_TH_A1_LBN 6 +#define FCN_RX_XON_MAC_TH_A1_WIDTH 5 +#define FCN_RX_XOFF_MAC_TH_A1_LBN 1 +#define FCN_RX_XOFF_MAC_TH_A1_WIDTH 5 +#define FCN_RX_XOFF_MAC_EN_A1_LBN 0 +#define FCN_RX_XOFF_MAC_EN_A1_WIDTH 1 + +#define FCN_RX_USR_BUF_SIZE_A1_LBN 11 +#define FCN_RX_USR_BUF_SIZE_A1_WIDTH 9 +#define FCN_RX_XOFF_MAC_EN_A1_LBN 0 +#define FCN_RX_XOFF_MAC_EN_A1_WIDTH 1 + +/* Receive filter control register */ +#define FCN_RX_FILTER_CTL_REG_KER 0x810 +#define FCN_UDP_FULL_SRCH_LIMIT_LBN 32 +#define FCN_UDP_FULL_SRCH_LIMIT_WIDTH 8 +#define FCN_NUM_KER_LBN 24 +#define FCN_NUM_KER_WIDTH 2 +#define FCN_UDP_WILD_SRCH_LIMIT_LBN 16 +#define FCN_UDP_WILD_SRCH_LIMIT_WIDTH 8 +#define FCN_TCP_WILD_SRCH_LIMIT_LBN 8 +#define FCN_TCP_WILD_SRCH_LIMIT_WIDTH 8 +#define FCN_TCP_FULL_SRCH_LIMIT_LBN 0 +#define FCN_TCP_FULL_SRCH_LIMIT_WIDTH 8 + +/* RX queue flush register */ +#define FCN_RX_FLUSH_DESCQ_REG_KER 0x0820 +#define FCN_RX_FLUSH_DESCQ_CMD_LBN 24 +#define FCN_RX_FLUSH_DESCQ_CMD_WIDTH 1 +#define FCN_RX_FLUSH_DESCQ_LBN 0 +#define FCN_RX_FLUSH_DESCQ_WIDTH 12 + +/* Receive descriptor update register */ +#define FCN_RX_DESC_UPD_REG_KER 0x0830 +#define FCN_RX_DESC_WPTR_LBN 96 +#define FCN_RX_DESC_WPTR_WIDTH 12 +#define FCN_RX_DESC_UPD_REG_KER_DWORD ( FCN_RX_DESC_UPD_REG_KER + 12 ) +#define FCN_RX_DESC_WPTR_DWORD_LBN 0 +#define FCN_RX_DESC_WPTR_DWORD_WIDTH 12 + +/* Receive descriptor cache configuration register */ +#define FCN_RX_DC_CFG_REG_KER 0x840 +#define FCN_RX_DC_SIZE_LBN 0 +#define FCN_RX_DC_SIZE_WIDTH 2 + +#define FCN_RX_SELF_RST_REG_KER 0x890 +#define FCN_RX_ISCSI_DIS_LBN 17 +#define FCN_RX_ISCSI_DIS_WIDTH 1 +#define FCN_RX_NODESC_WAIT_DIS_LBN 9 +#define FCN_RX_NODESC_WAIT_DIS_WIDTH 1 +#define FCN_RX_RECOVERY_EN_LBN 8 +#define FCN_RX_RECOVERY_EN_WIDTH 1 + +/* TX queue flush register */ +#define FCN_TX_FLUSH_DESCQ_REG_KER 0x0a00 +#define FCN_TX_FLUSH_DESCQ_CMD_LBN 12 +#define FCN_TX_FLUSH_DESCQ_CMD_WIDTH 1 +#define FCN_TX_FLUSH_DESCQ_LBN 0 +#define FCN_TX_FLUSH_DESCQ_WIDTH 12 + +/* Transmit configuration register 2 */ +#define FCN_TX_CFG2_REG_KER 0xa80 +#define FCN_TX_DIS_NON_IP_EV_LBN 17 +#define FCN_TX_DIS_NON_IP_EV_WIDTH 1 + +/* Transmit descriptor update register */ +#define FCN_TX_DESC_UPD_REG_KER 0x0a10 +#define FCN_TX_DESC_WPTR_LBN 96 +#define FCN_TX_DESC_WPTR_WIDTH 12 +#define FCN_TX_DESC_UPD_REG_KER_DWORD ( FCN_TX_DESC_UPD_REG_KER + 12 ) +#define FCN_TX_DESC_WPTR_DWORD_LBN 0 +#define FCN_TX_DESC_WPTR_DWORD_WIDTH 12 + +/* Transmit descriptor cache configuration register */ +#define FCN_TX_DC_CFG_REG_KER 0xa20 +#define FCN_TX_DC_SIZE_LBN 0 +#define FCN_TX_DC_SIZE_WIDTH 2 + +/* PHY management transmit data register */ +#define FCN_MD_TXD_REG_KER 0xc00 +#define FCN_MD_TXD_LBN 0 +#define FCN_MD_TXD_WIDTH 16 + +/* PHY management receive data register */ +#define FCN_MD_RXD_REG_KER 0xc10 +#define FCN_MD_RXD_LBN 0 +#define FCN_MD_RXD_WIDTH 16 + +/* PHY management configuration & status register */ +#define FCN_MD_CS_REG_KER 0xc20 +#define FCN_MD_GC_LBN 4 +#define FCN_MD_GC_WIDTH 1 +#define FCN_MD_RIC_LBN 2 +#define FCN_MD_RIC_WIDTH 1 +#define FCN_MD_RDC_LBN 1 +#define FCN_MD_RDC_WIDTH 1 +#define FCN_MD_WRC_LBN 0 +#define FCN_MD_WRC_WIDTH 1 + +/* PHY management PHY address register */ +#define FCN_MD_PHY_ADR_REG_KER 0xc30 +#define FCN_MD_PHY_ADR_LBN 0 +#define FCN_MD_PHY_ADR_WIDTH 16 + +/* PHY management ID register */ +#define FCN_MD_ID_REG_KER 0xc40 +#define FCN_MD_PRT_ADR_LBN 11 +#define FCN_MD_PRT_ADR_WIDTH 5 +#define FCN_MD_DEV_ADR_LBN 6 +#define FCN_MD_DEV_ADR_WIDTH 5 + +/* PHY management status & mask register */ +#define FCN_MD_STAT_REG_KER 0xc50 +#define FCN_MD_PINT_LBN 4 +#define FCN_MD_PINT_WIDTH 1 +#define FCN_MD_DONE_LBN 3 +#define FCN_MD_DONE_WIDTH 1 +#define FCN_MD_BSERR_LBN 2 +#define FCN_MD_BSERR_WIDTH 1 +#define FCN_MD_LNFL_LBN 1 +#define FCN_MD_LNFL_WIDTH 1 +#define FCN_MD_BSY_LBN 0 +#define FCN_MD_BSY_WIDTH 1 + +/* Port 0 and 1 MAC control registers */ +#define FCN_MAC0_CTRL_REG_KER 0xc80 +#define FCN_MAC1_CTRL_REG_KER 0xc90 +#define FCN_MAC_XOFF_VAL_LBN 16 +#define FCN_MAC_XOFF_VAL_WIDTH 16 +#define FCN_MAC_BCAD_ACPT_LBN 4 +#define FCN_MAC_BCAD_ACPT_WIDTH 1 +#define FCN_MAC_UC_PROM_LBN 3 +#define FCN_MAC_UC_PROM_WIDTH 1 +#define FCN_MAC_LINK_STATUS_LBN 2 +#define FCN_MAC_LINK_STATUS_WIDTH 1 +#define FCN_MAC_SPEED_LBN 0 +#define FCN_MAC_SPEED_WIDTH 2 + +/* 10Gig Xaui XGXS Default Values */ +#define XX_TXDRV_DEQ_DEFAULT 0xe /* deq=.6 */ +#define XX_TXDRV_DTX_DEFAULT 0x5 /* 1.25 */ +#define XX_SD_CTL_DRV_DEFAULT 0 /* 20mA */ + +/* GMAC registers */ +#define FALCON_GMAC_REGBANK 0xe00 +#define FALCON_GMAC_REGBANK_SIZE 0x200 +#define FALCON_GMAC_REG_SIZE 0x10 + +/* XGMAC registers */ +#define FALCON_XMAC_REGBANK 0x1200 +#define FALCON_XMAC_REGBANK_SIZE 0x200 +#define FALCON_XMAC_REG_SIZE 0x10 + +/* XGMAC address register low */ +#define FCN_XM_ADR_LO_REG_MAC 0x00 +#define FCN_XM_ADR_3_LBN 24 +#define FCN_XM_ADR_3_WIDTH 8 +#define FCN_XM_ADR_2_LBN 16 +#define FCN_XM_ADR_2_WIDTH 8 +#define FCN_XM_ADR_1_LBN 8 +#define FCN_XM_ADR_1_WIDTH 8 +#define FCN_XM_ADR_0_LBN 0 +#define FCN_XM_ADR_0_WIDTH 8 + +/* XGMAC address register high */ +#define FCN_XM_ADR_HI_REG_MAC 0x01 +#define FCN_XM_ADR_5_LBN 8 +#define FCN_XM_ADR_5_WIDTH 8 +#define FCN_XM_ADR_4_LBN 0 +#define FCN_XM_ADR_4_WIDTH 8 + +/* XGMAC global configuration - port 0*/ +#define FCN_XM_GLB_CFG_REG_MAC 0x02 +#define FCN_XM_RX_STAT_EN_LBN 11 +#define FCN_XM_RX_STAT_EN_WIDTH 1 +#define FCN_XM_TX_STAT_EN_LBN 10 +#define FCN_XM_TX_STAT_EN_WIDTH 1 +#define FCN_XM_RX_JUMBO_MODE_LBN 6 +#define FCN_XM_RX_JUMBO_MODE_WIDTH 1 +#define FCN_XM_CORE_RST_LBN 0 +#define FCN_XM_CORE_RST_WIDTH 1 + +/* XGMAC transmit configuration - port 0 */ +#define FCN_XM_TX_CFG_REG_MAC 0x03 +#define FCN_XM_IPG_LBN 16 +#define FCN_XM_IPG_WIDTH 4 +#define FCN_XM_FCNTL_LBN 10 +#define FCN_XM_FCNTL_WIDTH 1 +#define FCN_XM_TXCRC_LBN 8 +#define FCN_XM_TXCRC_WIDTH 1 +#define FCN_XM_AUTO_PAD_LBN 5 +#define FCN_XM_AUTO_PAD_WIDTH 1 +#define FCN_XM_TX_PRMBL_LBN 2 +#define FCN_XM_TX_PRMBL_WIDTH 1 +#define FCN_XM_TXEN_LBN 1 +#define FCN_XM_TXEN_WIDTH 1 + +/* XGMAC receive configuration - port 0 */ +#define FCN_XM_RX_CFG_REG_MAC 0x04 +#define FCN_XM_PASS_CRC_ERR_LBN 25 +#define FCN_XM_PASS_CRC_ERR_WIDTH 1 +#define FCN_XM_AUTO_DEPAD_LBN 8 +#define FCN_XM_AUTO_DEPAD_WIDTH 1 +#define FCN_XM_RXEN_LBN 1 +#define FCN_XM_RXEN_WIDTH 1 + +/* XGMAC management interrupt mask register */ +#define FCN_XM_MGT_INT_MSK_REG_MAC_B0 0x5 +#define FCN_XM_MSK_PRMBLE_ERR_LBN 2 +#define FCN_XM_MSK_PRMBLE_ERR_WIDTH 1 +#define FCN_XM_MSK_RMTFLT_LBN 1 +#define FCN_XM_MSK_RMTFLT_WIDTH 1 +#define FCN_XM_MSK_LCLFLT_LBN 0 +#define FCN_XM_MSK_LCLFLT_WIDTH 1 + +/* XGMAC flow control register */ +#define FCN_XM_FC_REG_MAC 0x7 +#define FCN_XM_PAUSE_TIME_LBN 16 +#define FCN_XM_PAUSE_TIME_WIDTH 16 +#define FCN_XM_DIS_FCNTL_LBN 0 +#define FCN_XM_DIS_FCNTL_WIDTH 1 + +/* XGMAC transmit parameter register */ +#define FCN_XM_TX_PARAM_REG_MAC 0x0d +#define FCN_XM_TX_JUMBO_MODE_LBN 31 +#define FCN_XM_TX_JUMBO_MODE_WIDTH 1 +#define FCN_XM_MAX_TX_FRM_SIZE_LBN 16 +#define FCN_XM_MAX_TX_FRM_SIZE_WIDTH 14 +#define FCN_XM_ACPT_ALL_MCAST_LBN 11 +#define FCN_XM_ACPT_ALL_MCAST_WIDTH 1 + +/* XGMAC receive parameter register */ +#define FCN_XM_RX_PARAM_REG_MAC 0x0e +#define FCN_XM_MAX_RX_FRM_SIZE_LBN 0 +#define FCN_XM_MAX_RX_FRM_SIZE_WIDTH 14 + +/* XGMAC management interrupt status register */ +#define FCN_XM_MGT_INT_REG_MAC_B0 0x0f +#define FCN_XM_PRMBLE_ERR 2 +#define FCN_XM_PRMBLE_WIDTH 1 +#define FCN_XM_RMTFLT_LBN 1 +#define FCN_XM_RMTFLT_WIDTH 1 +#define FCN_XM_LCLFLT_LBN 0 +#define FCN_XM_LCLFLT_WIDTH 1 + +/* XAUI XGXS core status register */ +#define FCN_XX_ALIGN_DONE_LBN 20 +#define FCN_XX_ALIGN_DONE_WIDTH 1 +#define FCN_XX_CORE_STAT_REG_MAC 0x16 +#define FCN_XX_SYNC_STAT_LBN 16 +#define FCN_XX_SYNC_STAT_WIDTH 4 +#define FCN_XX_SYNC_STAT_DECODE_SYNCED 0xf +#define FCN_XX_COMMA_DET_LBN 12 +#define FCN_XX_COMMA_DET_WIDTH 4 +#define FCN_XX_COMMA_DET_RESET 0xf +#define FCN_XX_CHARERR_LBN 4 +#define FCN_XX_CHARERR_WIDTH 4 +#define FCN_XX_CHARERR_RESET 0xf +#define FCN_XX_DISPERR_LBN 0 +#define FCN_XX_DISPERR_WIDTH 4 +#define FCN_XX_DISPERR_RESET 0xf + +/* XGXS/XAUI powerdown/reset register */ +#define FCN_XX_PWR_RST_REG_MAC 0x10 +#define FCN_XX_PWRDND_EN_LBN 15 +#define FCN_XX_PWRDND_EN_WIDTH 1 +#define FCN_XX_PWRDNC_EN_LBN 14 +#define FCN_XX_PWRDNC_EN_WIDTH 1 +#define FCN_XX_PWRDNB_EN_LBN 13 +#define FCN_XX_PWRDNB_EN_WIDTH 1 +#define FCN_XX_PWRDNA_EN_LBN 12 +#define FCN_XX_PWRDNA_EN_WIDTH 1 +#define FCN_XX_RSTPLLCD_EN_LBN 9 +#define FCN_XX_RSTPLLCD_EN_WIDTH 1 +#define FCN_XX_RSTPLLAB_EN_LBN 8 +#define FCN_XX_RSTPLLAB_EN_WIDTH 1 +#define FCN_XX_RESETD_EN_LBN 7 +#define FCN_XX_RESETD_EN_WIDTH 1 +#define FCN_XX_RESETC_EN_LBN 6 +#define FCN_XX_RESETC_EN_WIDTH 1 +#define FCN_XX_RESETB_EN_LBN 5 +#define FCN_XX_RESETB_EN_WIDTH 1 +#define FCN_XX_RESETA_EN_LBN 4 +#define FCN_XX_RESETA_EN_WIDTH 1 +#define FCN_XX_RSTXGXSRX_EN_LBN 2 +#define FCN_XX_RSTXGXSRX_EN_WIDTH 1 +#define FCN_XX_RSTXGXSTX_EN_LBN 1 +#define FCN_XX_RSTXGXSTX_EN_WIDTH 1 +#define FCN_XX_RST_XX_EN_LBN 0 +#define FCN_XX_RST_XX_EN_WIDTH 1 + + +/* XGXS/XAUI powerdown/reset control register */ +#define FCN_XX_SD_CTL_REG_MAC 0x11 +#define FCN_XX_TERMADJ1_LBN 17 +#define FCN_XX_TERMADJ1_WIDTH 1 +#define FCN_XX_TERMADJ0_LBN 16 +#define FCN_XX_TERMADJ0_WIDTH 1 +#define FCN_XX_HIDRVD_LBN 15 +#define FCN_XX_HIDRVD_WIDTH 1 +#define FCN_XX_LODRVD_LBN 14 +#define FCN_XX_LODRVD_WIDTH 1 +#define FCN_XX_HIDRVC_LBN 13 +#define FCN_XX_HIDRVC_WIDTH 1 +#define FCN_XX_LODRVC_LBN 12 +#define FCN_XX_LODRVC_WIDTH 1 +#define FCN_XX_HIDRVB_LBN 11 +#define FCN_XX_HIDRVB_WIDTH 1 +#define FCN_XX_LODRVB_LBN 10 +#define FCN_XX_LODRVB_WIDTH 1 +#define FCN_XX_HIDRVA_LBN 9 +#define FCN_XX_HIDRVA_WIDTH 1 +#define FCN_XX_LODRVA_LBN 8 +#define FCN_XX_LODRVA_WIDTH 1 +#define FCN_XX_LPBKD_LBN 3 +#define FCN_XX_LPBKD_WIDTH 1 +#define FCN_XX_LPBKC_LBN 2 +#define FCN_XX_LPBKC_WIDTH 1 +#define FCN_XX_LPBKB_LBN 1 +#define FCN_XX_LPBKB_WIDTH 1 +#define FCN_XX_LPBKA_LBN 0 +#define FCN_XX_LPBKA_WIDTH 1 + +#define FCN_XX_TXDRV_CTL_REG_MAC 0x12 +#define FCN_XX_DEQD_LBN 28 +#define FCN_XX_DEQD_WIDTH 4 +#define FCN_XX_DEQC_LBN 24 +#define FCN_XX_DEQC_WIDTH 4 +#define FCN_XX_DEQB_LBN 20 +#define FCN_XX_DEQB_WIDTH 4 +#define FCN_XX_DEQA_LBN 16 +#define FCN_XX_DEQA_WIDTH 4 +#define FCN_XX_DTXD_LBN 12 +#define FCN_XX_DTXD_WIDTH 4 +#define FCN_XX_DTXC_LBN 8 +#define FCN_XX_DTXC_WIDTH 4 +#define FCN_XX_DTXB_LBN 4 +#define FCN_XX_DTXB_WIDTH 4 +#define FCN_XX_DTXA_LBN 0 +#define FCN_XX_DTXA_WIDTH 4 + +/* Receive filter table */ +#define FCN_RX_FILTER_TBL0 0xF00000 + +/* Receive descriptor pointer table */ +#define FCN_RX_DESC_PTR_TBL_KER_A1 0x11800 +#define FCN_RX_DESC_PTR_TBL_KER_B0 0xF40000 +#define FCN_RX_ISCSI_DDIG_EN_LBN 88 +#define FCN_RX_ISCSI_DDIG_EN_WIDTH 1 +#define FCN_RX_ISCSI_HDIG_EN_LBN 87 +#define FCN_RX_ISCSI_HDIG_EN_WIDTH 1 +#define FCN_RX_DESCQ_BUF_BASE_ID_LBN 36 +#define FCN_RX_DESCQ_BUF_BASE_ID_WIDTH 20 +#define FCN_RX_DESCQ_EVQ_ID_LBN 24 +#define FCN_RX_DESCQ_EVQ_ID_WIDTH 12 +#define FCN_RX_DESCQ_OWNER_ID_LBN 10 +#define FCN_RX_DESCQ_OWNER_ID_WIDTH 14 +#define FCN_RX_DESCQ_SIZE_LBN 3 +#define FCN_RX_DESCQ_SIZE_WIDTH 2 +#define FCN_RX_DESCQ_SIZE_4K 3 +#define FCN_RX_DESCQ_SIZE_2K 2 +#define FCN_RX_DESCQ_SIZE_1K 1 +#define FCN_RX_DESCQ_SIZE_512 0 +#define FCN_RX_DESCQ_TYPE_LBN 2 +#define FCN_RX_DESCQ_TYPE_WIDTH 1 +#define FCN_RX_DESCQ_JUMBO_LBN 1 +#define FCN_RX_DESCQ_JUMBO_WIDTH 1 +#define FCN_RX_DESCQ_EN_LBN 0 +#define FCN_RX_DESCQ_EN_WIDTH 1 + +/* Transmit descriptor pointer table */ +#define FCN_TX_DESC_PTR_TBL_KER_A1 0x11900 +#define FCN_TX_DESC_PTR_TBL_KER_B0 0xF50000 +#define FCN_TX_NON_IP_DROP_DIS_B0_LBN 91 +#define FCN_TX_NON_IP_DROP_DIS_B0_WIDTH 1 +#define FCN_TX_DESCQ_EN_LBN 88 +#define FCN_TX_DESCQ_EN_WIDTH 1 +#define FCN_TX_ISCSI_DDIG_EN_LBN 87 +#define FCN_TX_ISCSI_DDIG_EN_WIDTH 1 +#define FCN_TX_ISCSI_HDIG_EN_LBN 86 +#define FCN_TX_ISCSI_HDIG_EN_WIDTH 1 +#define FCN_TX_DESCQ_BUF_BASE_ID_LBN 36 +#define FCN_TX_DESCQ_BUF_BASE_ID_WIDTH 20 +#define FCN_TX_DESCQ_EVQ_ID_LBN 24 +#define FCN_TX_DESCQ_EVQ_ID_WIDTH 12 +#define FCN_TX_DESCQ_OWNER_ID_LBN 10 +#define FCN_TX_DESCQ_OWNER_ID_WIDTH 14 +#define FCN_TX_DESCQ_SIZE_LBN 3 +#define FCN_TX_DESCQ_SIZE_WIDTH 2 +#define FCN_TX_DESCQ_SIZE_4K 3 +#define FCN_TX_DESCQ_SIZE_2K 2 +#define FCN_TX_DESCQ_SIZE_1K 1 +#define FCN_TX_DESCQ_SIZE_512 0 +#define FCN_TX_DESCQ_TYPE_LBN 1 +#define FCN_TX_DESCQ_TYPE_WIDTH 2 +#define FCN_TX_DESCQ_FLUSH_LBN 0 +#define FCN_TX_DESCQ_FLUSH_WIDTH 1 + +/* Event queue pointer */ +#define FCN_EVQ_PTR_TBL_KER_A1 0x11a00 +#define FCN_EVQ_PTR_TBL_KER_B0 0xf60000 +#define FCN_EVQ_EN_LBN 23 +#define FCN_EVQ_EN_WIDTH 1 +#define FCN_EVQ_SIZE_LBN 20 +#define FCN_EVQ_SIZE_WIDTH 3 +#define FCN_EVQ_SIZE_32K 6 +#define FCN_EVQ_SIZE_16K 5 +#define FCN_EVQ_SIZE_8K 4 +#define FCN_EVQ_SIZE_4K 3 +#define FCN_EVQ_SIZE_2K 2 +#define FCN_EVQ_SIZE_1K 1 +#define FCN_EVQ_SIZE_512 0 +#define FCN_EVQ_BUF_BASE_ID_LBN 0 +#define FCN_EVQ_BUF_BASE_ID_WIDTH 20 + +/* RSS indirection table */ +#define FCN_RX_RSS_INDIR_TBL_B0 0xFB0000 + +/* Event queue read pointer */ +#define FCN_EVQ_RPTR_REG_KER_A1 0x11b00 +#define FCN_EVQ_RPTR_REG_KER_B0 0xfa0000 +#define FCN_EVQ_RPTR_LBN 0 +#define FCN_EVQ_RPTR_WIDTH 14 +#define FCN_EVQ_RPTR_REG_KER_DWORD_A1 ( FCN_EVQ_RPTR_REG_KER_A1 + 0 ) +#define FCN_EVQ_RPTR_REG_KER_DWORD_B0 ( FCN_EVQ_RPTR_REG_KER_B0 + 0 ) +#define FCN_EVQ_RPTR_DWORD_LBN 0 +#define FCN_EVQ_RPTR_DWORD_WIDTH 14 + +/* Special buffer descriptors */ +#define FCN_BUF_FULL_TBL_KER_A1 0x18000 +#define FCN_BUF_FULL_TBL_KER_B0 0x800000 +#define FCN_IP_DAT_BUF_SIZE_LBN 50 +#define FCN_IP_DAT_BUF_SIZE_WIDTH 1 +#define FCN_IP_DAT_BUF_SIZE_8K 1 +#define FCN_IP_DAT_BUF_SIZE_4K 0 +#define FCN_BUF_ADR_FBUF_LBN 14 +#define FCN_BUF_ADR_FBUF_WIDTH 34 +#define FCN_BUF_OWNER_ID_FBUF_LBN 0 +#define FCN_BUF_OWNER_ID_FBUF_WIDTH 14 + +/** Offset of a GMAC register within Falcon */ +#define FALCON_GMAC_REG( efab, mac_reg ) \ + ( FALCON_GMAC_REGBANK + \ + ( (mac_reg) * FALCON_GMAC_REG_SIZE ) ) + +/** Offset of an XMAC register within Falcon */ +#define FALCON_XMAC_REG( efab_port, mac_reg ) \ + ( FALCON_XMAC_REGBANK + \ + ( (mac_reg) * FALCON_XMAC_REG_SIZE ) ) + +#define FCN_MAC_DATA_LBN 0 +#define FCN_MAC_DATA_WIDTH 32 + +/* Transmit descriptor */ +#define FCN_TX_KER_PORT_LBN 63 +#define FCN_TX_KER_PORT_WIDTH 1 +#define FCN_TX_KER_BYTE_CNT_LBN 48 +#define FCN_TX_KER_BYTE_CNT_WIDTH 14 +#define FCN_TX_KER_BUF_ADR_LBN 0 +#define FCN_TX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 ) + + +/* Receive descriptor */ +#define FCN_RX_KER_BUF_SIZE_LBN 48 +#define FCN_RX_KER_BUF_SIZE_WIDTH 14 +#define FCN_RX_KER_BUF_ADR_LBN 0 +#define FCN_RX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 ) + +/* Event queue entries */ +#define FCN_EV_CODE_LBN 60 +#define FCN_EV_CODE_WIDTH 4 +#define FCN_RX_IP_EV_DECODE 0 +#define FCN_TX_IP_EV_DECODE 2 +#define FCN_DRIVER_EV_DECODE 5 + +/* Receive events */ +#define FCN_RX_EV_PKT_OK_LBN 56 +#define FCN_RX_EV_PKT_OK_WIDTH 1 +#define FCN_RX_PORT_LBN 30 +#define FCN_RX_PORT_WIDTH 1 +#define FCN_RX_EV_BYTE_CNT_LBN 16 +#define FCN_RX_EV_BYTE_CNT_WIDTH 14 +#define FCN_RX_EV_DESC_PTR_LBN 0 +#define FCN_RX_EV_DESC_PTR_WIDTH 12 + +/* Transmit events */ +#define FCN_TX_EV_DESC_PTR_LBN 0 +#define FCN_TX_EV_DESC_PTR_WIDTH 12 + +/******************************************************************************* + * + * + * Low-level hardware access + * + * + *******************************************************************************/ + +#define FCN_REVISION_REG(efab, reg) \ + ( ( efab->pci_revision == FALCON_REV_B0 ) ? reg ## _B0 : reg ## _A1 ) + +#define EFAB_SET_OWORD_FIELD_VER(efab, reg, field, val) \ + if ( efab->pci_revision == FALCON_REV_B0 ) \ + EFAB_SET_OWORD_FIELD ( reg, field ## _B0, val ); \ + else \ + EFAB_SET_OWORD_FIELD ( reg, field ## _A1, val ); + +#if FALCON_USE_IO_BAR + +/* Write dword via the I/O BAR */ +static inline void _falcon_writel ( struct efab_nic *efab, uint32_t value, + unsigned int reg ) { + outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG ); + outl ( value, efab->iobase + FCN_IOM_IND_DAT_REG ); +} + +/* Read dword via the I/O BAR */ +static inline uint32_t _falcon_readl ( struct efab_nic *efab, + unsigned int reg ) { + outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG ); + return inl ( efab->iobase + FCN_IOM_IND_DAT_REG ); +} + +#else /* FALCON_USE_IO_BAR */ + +#define _falcon_writel( efab, value, reg ) \ + writel ( (value), (efab)->membase + (reg) ) +#define _falcon_readl( efab, reg ) readl ( (efab)->membase + (reg) ) + +#endif /* FALCON_USE_IO_BAR */ + +/** + * Write to a Falcon register + * + */ +static inline void +falcon_write ( struct efab_nic *efab, efab_oword_t *value, unsigned int reg ) +{ + + EFAB_REGDUMP ( "Writing register %x with " EFAB_OWORD_FMT "\n", + reg, EFAB_OWORD_VAL ( *value ) ); + + _falcon_writel ( efab, value->u32[0], reg + 0 ); + _falcon_writel ( efab, value->u32[1], reg + 4 ); + _falcon_writel ( efab, value->u32[2], reg + 8 ); + wmb(); + _falcon_writel ( efab, value->u32[3], reg + 12 ); + wmb(); +} + +/** + * Write to Falcon SRAM + * + */ +static inline void +falcon_write_sram ( struct efab_nic *efab, efab_qword_t *value, + unsigned int index ) +{ + unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) + + ( index * sizeof ( *value ) ) ); + + EFAB_REGDUMP ( "Writing SRAM register %x with " EFAB_QWORD_FMT "\n", + reg, EFAB_QWORD_VAL ( *value ) ); + + _falcon_writel ( efab, value->u32[0], reg + 0 ); + _falcon_writel ( efab, value->u32[1], reg + 4 ); + wmb(); +} + +/** + * Write dword to Falcon register that allows partial writes + * + */ +static inline void +falcon_writel ( struct efab_nic *efab, efab_dword_t *value, unsigned int reg ) +{ + EFAB_REGDUMP ( "Writing partial register %x with " EFAB_DWORD_FMT "\n", + reg, EFAB_DWORD_VAL ( *value ) ); + _falcon_writel ( efab, value->u32[0], reg ); +} + +/** + * Read from a Falcon register + * + */ +static inline void +falcon_read ( struct efab_nic *efab, efab_oword_t *value, unsigned int reg ) +{ + value->u32[0] = _falcon_readl ( efab, reg + 0 ); + wmb(); + value->u32[1] = _falcon_readl ( efab, reg + 4 ); + value->u32[2] = _falcon_readl ( efab, reg + 8 ); + value->u32[3] = _falcon_readl ( efab, reg + 12 ); + + EFAB_REGDUMP ( "Read from register %x, got " EFAB_OWORD_FMT "\n", + reg, EFAB_OWORD_VAL ( *value ) ); +} + +/** + * Read from Falcon SRAM + * + */ +static inline void +falcon_read_sram ( struct efab_nic *efab, efab_qword_t *value, + unsigned int index ) +{ + unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) + + ( index * sizeof ( *value ) ) ); + + value->u32[0] = _falcon_readl ( efab, reg + 0 ); + value->u32[1] = _falcon_readl ( efab, reg + 4 ); + EFAB_REGDUMP ( "Read from SRAM register %x, got " EFAB_QWORD_FMT "\n", + reg, EFAB_QWORD_VAL ( *value ) ); +} + +/** + * Read dword from a portion of a Falcon register + * + */ +static inline void +falcon_readl ( struct efab_nic *efab, efab_dword_t *value, unsigned int reg ) +{ + value->u32[0] = _falcon_readl ( efab, reg ); + EFAB_REGDUMP ( "Read from register %x, got " EFAB_DWORD_FMT "\n", + reg, EFAB_DWORD_VAL ( *value ) ); +} + +#define FCN_DUMP_REG( efab, _reg ) do { \ + efab_oword_t reg; \ + falcon_read ( efab, ®, _reg ); \ + EFAB_LOG ( #_reg " = " EFAB_OWORD_FMT "\n", \ + EFAB_OWORD_VAL ( reg ) ); \ + } while ( 0 ); + +#define FCN_DUMP_MAC_REG( efab, _mac_reg ) do { \ + efab_dword_t reg; \ + efab->mac_op->mac_readl ( efab, ®, _mac_reg ); \ + EFAB_LOG ( #_mac_reg " = " EFAB_DWORD_FMT "\n", \ + EFAB_DWORD_VAL ( reg ) ); \ + } while ( 0 ); + +/** + * See if an event is present + * + * @v event Falcon event structure + * @ret True An event is pending + * @ret False No event is pending + * + * We check both the high and low dword of the event for all ones. We + * wrote all ones when we cleared the event, and no valid event can + * have all ones in either its high or low dwords. This approach is + * robust against reordering. + * + * Note that using a single 64-bit comparison is incorrect; even + * though the CPU read will be atomic, the DMA write may not be. + */ +static inline int +falcon_event_present ( falcon_event_t* event ) +{ + return ( ! ( EFAB_DWORD_IS_ALL_ONES ( event->dword[0] ) | + EFAB_DWORD_IS_ALL_ONES ( event->dword[1] ) ) ); +} + +static void +falcon_eventq_read_ack ( struct efab_nic *efab, struct efab_ev_queue *ev_queue ) +{ + efab_dword_t reg; + + EFAB_POPULATE_DWORD_1 ( reg, FCN_EVQ_RPTR_DWORD, ev_queue->read_ptr ); + falcon_writel ( efab, ®, + FCN_REVISION_REG ( efab, FCN_EVQ_RPTR_REG_KER_DWORD ) ); +} + +#if 0 +/** + * Dump register contents (for debugging) + * + * Marked as static inline so that it will not be compiled in if not + * used. + */ +static inline void +falcon_dump_regs ( struct efab_nic *efab ) +{ + FCN_DUMP_REG ( efab, FCN_INT_EN_REG_KER ); + FCN_DUMP_REG ( efab, FCN_INT_ADR_REG_KER ); + FCN_DUMP_REG ( efab, FCN_GLB_CTL_REG_KER ); + FCN_DUMP_REG ( efab, FCN_TIMER_CMD_REG_KER ); + FCN_DUMP_REG ( efab, FCN_SRM_RX_DC_CFG_REG_KER ); + FCN_DUMP_REG ( efab, FCN_SRM_TX_DC_CFG_REG_KER ); + FCN_DUMP_REG ( efab, FCN_RX_FILTER_CTL_REG_KER ); + FCN_DUMP_REG ( efab, FCN_RX_DC_CFG_REG_KER ); + FCN_DUMP_REG ( efab, FCN_TX_DC_CFG_REG_KER ); + FCN_DUMP_REG ( efab, FCN_MAC0_CTRL_REG_KER ); + FCN_DUMP_REG ( efab, FCN_MAC1_CTRL_REG_KER ); + FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) ); + FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) ); + FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) ); + FCN_DUMP_MAC_REG ( efab, GM_CFG1_REG_MAC ); + FCN_DUMP_MAC_REG ( efab, GM_CFG2_REG_MAC ); + FCN_DUMP_MAC_REG ( efab, GM_MAX_FLEN_REG_MAC ); + FCN_DUMP_MAC_REG ( efab, GM_MII_MGMT_CFG_REG_MAC ); + FCN_DUMP_MAC_REG ( efab, GM_ADR1_REG_MAC ); + FCN_DUMP_MAC_REG ( efab, GM_ADR2_REG_MAC ); + FCN_DUMP_MAC_REG ( efab, GMF_CFG0_REG_MAC ); + FCN_DUMP_MAC_REG ( efab, GMF_CFG1_REG_MAC ); + FCN_DUMP_MAC_REG ( efab, GMF_CFG2_REG_MAC ); + FCN_DUMP_MAC_REG ( efab, GMF_CFG3_REG_MAC ); + FCN_DUMP_MAC_REG ( efab, GMF_CFG4_REG_MAC ); + FCN_DUMP_MAC_REG ( efab, GMF_CFG5_REG_MAC ); +} +#endif + +static void +falcon_interrupts ( struct efab_nic *efab, int enabled, int force ) +{ + efab_oword_t int_en_reg_ker; + + EFAB_POPULATE_OWORD_2 ( int_en_reg_ker, + FCN_KER_INT_KER, force, + FCN_DRV_INT_EN_KER, enabled ); + falcon_write ( efab, &int_en_reg_ker, FCN_INT_EN_REG_KER ); +} + +/******************************************************************************* + * + * + * SPI access + * + * + *******************************************************************************/ + + +/** Maximum length for a single SPI transaction */ +#define FALCON_SPI_MAX_LEN 16 + +static int +falcon_spi_wait ( struct efab_nic *efab ) +{ + efab_oword_t reg; + int count; + + count = 0; + do { + udelay ( 100 ); + falcon_read ( efab, ®, FCN_EE_SPI_HCMD_REG ); + if ( EFAB_OWORD_FIELD ( reg, FCN_EE_SPI_HCMD_CMD_EN ) == 0 ) + return 0; + } while ( ++count < 1000 ); + + EFAB_ERR ( "Timed out waiting for SPI\n" ); + return -ETIMEDOUT; +} + +static int +falcon_spi_rw ( struct spi_bus* bus, struct spi_device *device, + unsigned int command, int address, + const void* data_out, void *data_in, size_t len ) +{ + struct efab_nic *efab = container_of ( bus, struct efab_nic, spi_bus ); + int address_len, rc, device_id, read_cmd; + efab_oword_t reg; + + /* falcon_init_spi_device() should have reduced the block size + * down so this constraint holds */ + assert ( len <= FALCON_SPI_MAX_LEN ); + + /* Is this the FLASH or EEPROM device? */ + if ( device == &efab->spi_flash ) + device_id = FCN_EE_SPI_FLASH; + else if ( device == &efab->spi_eeprom ) + device_id = FCN_EE_SPI_EEPROM; + else { + EFAB_ERR ( "Unknown device %p\n", device ); + return -EINVAL; + } + + EFAB_TRACE ( "Executing spi command %d on device %d at %d for %zd bytes\n", + command, device_id, address, len ); + + /* The bus must be idle */ + rc = falcon_spi_wait ( efab ); + if ( rc ) + goto fail1; + + /* Copy data out */ + if ( data_out ) { + memcpy ( ®, data_out, len ); + falcon_write ( efab, ®, FCN_EE_SPI_HDATA_REG ); + } + + /* Program address register */ + if ( address >= 0 ) { + EFAB_POPULATE_OWORD_1 ( reg, FCN_EE_SPI_HADR_ADR, address ); + falcon_write ( efab, ®, FCN_EE_SPI_HADR_REG ); + } + + /* Issue command */ + address_len = ( address >= 0 ) ? device->address_len / 8 : 0; + read_cmd = ( data_in ? FCN_EE_SPI_READ : FCN_EE_SPI_WRITE ); + EFAB_POPULATE_OWORD_7 ( reg, + FCN_EE_SPI_HCMD_CMD_EN, 1, + FCN_EE_SPI_HCMD_SF_SEL, device_id, + FCN_EE_SPI_HCMD_DABCNT, len, + FCN_EE_SPI_HCMD_READ, read_cmd, + FCN_EE_SPI_HCMD_DUBCNT, 0, + FCN_EE_SPI_HCMD_ADBCNT, address_len, + FCN_EE_SPI_HCMD_ENC, command ); + falcon_write ( efab, ®, FCN_EE_SPI_HCMD_REG ); + + /* Wait for the command to complete */ + rc = falcon_spi_wait ( efab ); + if ( rc ) + goto fail2; + + /* Copy data in */ + if ( data_in ) { + falcon_read ( efab, ®, FCN_EE_SPI_HDATA_REG ); + memcpy ( data_in, ®, len ); + } + + return 0; + +fail2: +fail1: + EFAB_ERR ( "Failed SPI command %d to device %d address 0x%x len 0x%zx\n", + command, device_id, address, len ); + + return rc; +} + +/** Portion of EEPROM available for non-volatile options */ +static struct nvo_fragment falcon_nvo_fragments[] = { + { 0x100, 0xf0 }, + { 0, 0 } +}; + +/******************************************************************************* + * + * + * Falcon bit-bashed I2C interface + * + * + *******************************************************************************/ + +static void +falcon_i2c_bit_write ( struct bit_basher *basher, unsigned int bit_id, + unsigned long data ) +{ + struct efab_nic *efab = container_of ( basher, struct efab_nic, + i2c_bb.basher ); + efab_oword_t reg; + + falcon_read ( efab, ®, FCN_GPIO_CTL_REG_KER ); + switch ( bit_id ) { + case I2C_BIT_SCL: + EFAB_SET_OWORD_FIELD ( reg, FCN_GPIO0_OEN, ( data ? 0 : 1 ) ); + break; + case I2C_BIT_SDA: + EFAB_SET_OWORD_FIELD ( reg, FCN_GPIO3_OEN, ( data ? 0 : 1 ) ); + break; + default: + EFAB_ERR ( "%s bit=%d\n", __func__, bit_id ); + break; + } + + falcon_write ( efab, ®, FCN_GPIO_CTL_REG_KER ); +} + +static int +falcon_i2c_bit_read ( struct bit_basher *basher, unsigned int bit_id ) +{ + struct efab_nic *efab = container_of ( basher, struct efab_nic, + i2c_bb.basher ); + efab_oword_t reg; + + falcon_read ( efab, ®, FCN_GPIO_CTL_REG_KER ); + switch ( bit_id ) { + case I2C_BIT_SCL: + return EFAB_OWORD_FIELD ( reg, FCN_GPIO0_IN ); + break; + case I2C_BIT_SDA: + return EFAB_OWORD_FIELD ( reg, FCN_GPIO3_IN ); + break; + default: + EFAB_ERR ( "%s bit=%d\n", __func__, bit_id ); + break; + } + + return -1; +} + +static struct bit_basher_operations falcon_i2c_bit_ops = { + .read = falcon_i2c_bit_read, + .write = falcon_i2c_bit_write, +}; + + +/******************************************************************************* + * + * + * MDIO access + * + * + *******************************************************************************/ + +static int +falcon_gmii_wait ( struct efab_nic *efab ) +{ + efab_dword_t md_stat; + int count; + + /* wait upto 10ms */ + for (count = 0; count < 1000; count++) { + falcon_readl ( efab, &md_stat, FCN_MD_STAT_REG_KER ); + if ( EFAB_DWORD_FIELD ( md_stat, FCN_MD_BSY ) == 0 ) { + if ( EFAB_DWORD_FIELD ( md_stat, FCN_MD_LNFL ) != 0 || + EFAB_DWORD_FIELD ( md_stat, FCN_MD_BSERR ) != 0 ) { + EFAB_ERR ( "Error from GMII access " + EFAB_DWORD_FMT"\n", + EFAB_DWORD_VAL ( md_stat )); + return -EIO; + } + return 0; + } + udelay(10); + } + + EFAB_ERR ( "Timed out waiting for GMII\n" ); + return -ETIMEDOUT; +} + +static void +falcon_mdio_write ( struct efab_nic *efab, int device, + int location, int value ) +{ + efab_oword_t reg; + + EFAB_TRACE ( "Writing GMII %d register %02x with %04x\n", + device, location, value ); + + /* Check MII not currently being accessed */ + if ( falcon_gmii_wait ( efab ) ) + return; + + /* Write the address/ID register */ + EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, location ); + falcon_write ( efab, ®, FCN_MD_PHY_ADR_REG_KER ); + + if ( efab->phy_10g ) { + /* clause45 */ + EFAB_POPULATE_OWORD_2 ( reg, + FCN_MD_PRT_ADR, efab->phy_addr, + FCN_MD_DEV_ADR, device ); + } + else { + /* clause22 */ + assert ( device == 0 ); + + EFAB_POPULATE_OWORD_2 ( reg, + FCN_MD_PRT_ADR, efab->phy_addr, + FCN_MD_DEV_ADR, location ); + } + falcon_write ( efab, ®, FCN_MD_ID_REG_KER ); + + + /* Write data */ + EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_TXD, value ); + falcon_write ( efab, ®, FCN_MD_TXD_REG_KER ); + + EFAB_POPULATE_OWORD_2 ( reg, + FCN_MD_WRC, 1, + FCN_MD_GC, ( efab->phy_10g ? 0 : 1 ) ); + falcon_write ( efab, ®, FCN_MD_CS_REG_KER ); + + /* Wait for data to be written */ + if ( falcon_gmii_wait ( efab ) ) { + /* Abort the write operation */ + EFAB_POPULATE_OWORD_2 ( reg, + FCN_MD_WRC, 0, + FCN_MD_GC, 1); + falcon_write ( efab, ®, FCN_MD_CS_REG_KER ); + udelay(10); + } +} + +static int +falcon_mdio_read ( struct efab_nic *efab, int device, int location ) +{ + efab_oword_t reg; + int value; + + /* Check MII not currently being accessed */ + if ( falcon_gmii_wait ( efab ) ) + return -1; + + if ( efab->phy_10g ) { + /* clause45 */ + EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, location ); + falcon_write ( efab, ®, FCN_MD_PHY_ADR_REG_KER ); + + EFAB_POPULATE_OWORD_2 ( reg, + FCN_MD_PRT_ADR, efab->phy_addr, + FCN_MD_DEV_ADR, device ); + falcon_write ( efab, ®, FCN_MD_ID_REG_KER); + + /* request data to be read */ + EFAB_POPULATE_OWORD_2 ( reg, + FCN_MD_RDC, 1, + FCN_MD_GC, 0 ); + } + else { + /* clause22 */ + assert ( device == 0 ); + + EFAB_POPULATE_OWORD_2 ( reg, + FCN_MD_PRT_ADR, efab->phy_addr, + FCN_MD_DEV_ADR, location ); + falcon_write ( efab, ®, FCN_MD_ID_REG_KER ); + + /* Request data to be read */ + EFAB_POPULATE_OWORD_2 ( reg, + FCN_MD_RIC, 1, + FCN_MD_GC, 1 ); + } + + falcon_write ( efab, ®, FCN_MD_CS_REG_KER ); + + /* Wait for data to become available */ + if ( falcon_gmii_wait ( efab ) ) { + /* Abort the read operation */ + EFAB_POPULATE_OWORD_2 ( reg, + FCN_MD_RIC, 0, + FCN_MD_GC, 1 ); + falcon_write ( efab, ®, FCN_MD_CS_REG_KER ); + udelay ( 10 ); + value = -1; + } + else { + /* Read the data */ + falcon_read ( efab, ®, FCN_MD_RXD_REG_KER ); + value = EFAB_OWORD_FIELD ( reg, FCN_MD_RXD ); + } + + EFAB_TRACE ( "Read from GMII %d register %02x, got %04x\n", + device, location, value ); + + return value; +} + +/******************************************************************************* + * + * + * MAC wrapper + * + * + *******************************************************************************/ + +static void +falcon_reconfigure_mac_wrapper ( struct efab_nic *efab ) +{ + efab_oword_t reg; + int link_speed; + + if ( efab->link_options & LPA_EF_10000 ) { + link_speed = 0x3; + } else if ( efab->link_options & LPA_EF_1000 ) { + link_speed = 0x2; + } else if ( efab->link_options & LPA_100 ) { + link_speed = 0x1; + } else { + link_speed = 0x0; + } + EFAB_POPULATE_OWORD_5 ( reg, + FCN_MAC_XOFF_VAL, 0xffff /* datasheet */, + FCN_MAC_BCAD_ACPT, 1, + FCN_MAC_UC_PROM, 0, + FCN_MAC_LINK_STATUS, 1, + FCN_MAC_SPEED, link_speed ); + + falcon_write ( efab, ®, FCN_MAC0_CTRL_REG_KER ); +} + +/******************************************************************************* + * + * + * GMAC handling + * + * + *******************************************************************************/ + +/* GMAC configuration register 1 */ +#define GM_CFG1_REG_MAC 0x00 +#define GM_SW_RST_LBN 31 +#define GM_SW_RST_WIDTH 1 +#define GM_RX_FC_EN_LBN 5 +#define GM_RX_FC_EN_WIDTH 1 +#define GM_TX_FC_EN_LBN 4 +#define GM_TX_FC_EN_WIDTH 1 +#define GM_RX_EN_LBN 2 +#define GM_RX_EN_WIDTH 1 +#define GM_TX_EN_LBN 0 +#define GM_TX_EN_WIDTH 1 + +/* GMAC configuration register 2 */ +#define GM_CFG2_REG_MAC 0x01 +#define GM_PAMBL_LEN_LBN 12 +#define GM_PAMBL_LEN_WIDTH 4 +#define GM_IF_MODE_LBN 8 +#define GM_IF_MODE_WIDTH 2 +#define GM_PAD_CRC_EN_LBN 2 +#define GM_PAD_CRC_EN_WIDTH 1 +#define GM_FD_LBN 0 +#define GM_FD_WIDTH 1 + +/* GMAC maximum frame length register */ +#define GM_MAX_FLEN_REG_MAC 0x04 +#define GM_MAX_FLEN_LBN 0 +#define GM_MAX_FLEN_WIDTH 16 + +/* GMAC MII management configuration register */ +#define GM_MII_MGMT_CFG_REG_MAC 0x08 +#define GM_MGMT_CLK_SEL_LBN 0 +#define GM_MGMT_CLK_SEL_WIDTH 3 + +/* GMAC MII management command register */ +#define GM_MII_MGMT_CMD_REG_MAC 0x09 +#define GM_MGMT_SCAN_CYC_LBN 1 +#define GM_MGMT_SCAN_CYC_WIDTH 1 +#define GM_MGMT_RD_CYC_LBN 0 +#define GM_MGMT_RD_CYC_WIDTH 1 + +/* GMAC MII management address register */ +#define GM_MII_MGMT_ADR_REG_MAC 0x0a +#define GM_MGMT_PHY_ADDR_LBN 8 +#define GM_MGMT_PHY_ADDR_WIDTH 5 +#define GM_MGMT_REG_ADDR_LBN 0 +#define GM_MGMT_REG_ADDR_WIDTH 5 + +/* GMAC MII management control register */ +#define GM_MII_MGMT_CTL_REG_MAC 0x0b +#define GM_MGMT_CTL_LBN 0 +#define GM_MGMT_CTL_WIDTH 16 + +/* GMAC MII management status register */ +#define GM_MII_MGMT_STAT_REG_MAC 0x0c +#define GM_MGMT_STAT_LBN 0 +#define GM_MGMT_STAT_WIDTH 16 + +/* GMAC MII management indicators register */ +#define GM_MII_MGMT_IND_REG_MAC 0x0d +#define GM_MGMT_BUSY_LBN 0 +#define GM_MGMT_BUSY_WIDTH 1 + +/* GMAC station address register 1 */ +#define GM_ADR1_REG_MAC 0x10 +#define GM_HWADDR_5_LBN 24 +#define GM_HWADDR_5_WIDTH 8 +#define GM_HWADDR_4_LBN 16 +#define GM_HWADDR_4_WIDTH 8 +#define GM_HWADDR_3_LBN 8 +#define GM_HWADDR_3_WIDTH 8 +#define GM_HWADDR_2_LBN 0 +#define GM_HWADDR_2_WIDTH 8 + +/* GMAC station address register 2 */ +#define GM_ADR2_REG_MAC 0x11 +#define GM_HWADDR_1_LBN 24 +#define GM_HWADDR_1_WIDTH 8 +#define GM_HWADDR_0_LBN 16 +#define GM_HWADDR_0_WIDTH 8 + +/* GMAC FIFO configuration register 0 */ +#define GMF_CFG0_REG_MAC 0x12 +#define GMF_FTFENREQ_LBN 12 +#define GMF_FTFENREQ_WIDTH 1 +#define GMF_STFENREQ_LBN 11 +#define GMF_STFENREQ_WIDTH 1 +#define GMF_FRFENREQ_LBN 10 +#define GMF_FRFENREQ_WIDTH 1 +#define GMF_SRFENREQ_LBN 9 +#define GMF_SRFENREQ_WIDTH 1 +#define GMF_WTMENREQ_LBN 8 +#define GMF_WTMENREQ_WIDTH 1 + +/* GMAC FIFO configuration register 1 */ +#define GMF_CFG1_REG_MAC 0x13 +#define GMF_CFGFRTH_LBN 16 +#define GMF_CFGFRTH_WIDTH 5 +#define GMF_CFGXOFFRTX_LBN 0 +#define GMF_CFGXOFFRTX_WIDTH 16 + +/* GMAC FIFO configuration register 2 */ +#define GMF_CFG2_REG_MAC 0x14 +#define GMF_CFGHWM_LBN 16 +#define GMF_CFGHWM_WIDTH 6 +#define GMF_CFGLWM_LBN 0 +#define GMF_CFGLWM_WIDTH 6 + +/* GMAC FIFO configuration register 3 */ +#define GMF_CFG3_REG_MAC 0x15 +#define GMF_CFGHWMFT_LBN 16 +#define GMF_CFGHWMFT_WIDTH 6 +#define GMF_CFGFTTH_LBN 0 +#define GMF_CFGFTTH_WIDTH 6 + +/* GMAC FIFO configuration register 4 */ +#define GMF_CFG4_REG_MAC 0x16 +#define GMF_HSTFLTRFRM_PAUSE_LBN 12 +#define GMF_HSTFLTRFRM_PAUSE_WIDTH 12 + +/* GMAC FIFO configuration register 5 */ +#define GMF_CFG5_REG_MAC 0x17 +#define GMF_CFGHDPLX_LBN 22 +#define GMF_CFGHDPLX_WIDTH 1 +#define GMF_CFGBYTMODE_LBN 19 +#define GMF_CFGBYTMODE_WIDTH 1 +#define GMF_HSTDRPLT64_LBN 18 +#define GMF_HSTDRPLT64_WIDTH 1 +#define GMF_HSTFLTRFRMDC_PAUSE_LBN 12 +#define GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1 + +static void +falcon_gmac_writel ( struct efab_nic *efab, efab_dword_t *value, + unsigned int mac_reg ) +{ + efab_oword_t temp; + + EFAB_POPULATE_OWORD_1 ( temp, FCN_MAC_DATA, + EFAB_DWORD_FIELD ( *value, FCN_MAC_DATA ) ); + falcon_write ( efab, &temp, FALCON_GMAC_REG ( efab, mac_reg ) ); +} + +static void +falcon_gmac_readl ( struct efab_nic *efab, efab_dword_t *value, + unsigned int mac_reg ) +{ + efab_oword_t temp; + + falcon_read ( efab, &temp, FALCON_GMAC_REG ( efab, mac_reg ) ); + EFAB_POPULATE_DWORD_1 ( *value, FCN_MAC_DATA, + EFAB_OWORD_FIELD ( temp, FCN_MAC_DATA ) ); +} + +static void +mentormac_reset ( struct efab_nic *efab ) +{ + efab_dword_t reg; + + /* Take into reset */ + EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 1 ); + falcon_gmac_writel ( efab, ®, GM_CFG1_REG_MAC ); + udelay ( 1000 ); + + /* Take out of reset */ + EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 0 ); + falcon_gmac_writel ( efab, ®, GM_CFG1_REG_MAC ); + udelay ( 1000 ); + + /* Configure GMII interface so PHY is accessible. Note that + * GMII interface is connected only to port 0, and that on + * Falcon this is a no-op. + */ + EFAB_POPULATE_DWORD_1 ( reg, GM_MGMT_CLK_SEL, 0x4 ); + falcon_gmac_writel ( efab, ®, GM_MII_MGMT_CFG_REG_MAC ); + udelay ( 10 ); +} + +static void +mentormac_init ( struct efab_nic *efab ) +{ + int pause, if_mode, full_duplex, bytemode, half_duplex; + efab_dword_t reg; + + /* Configuration register 1 */ + pause = ( efab->link_options & LPA_PAUSE_CAP ) ? 1 : 0; + if ( ! ( efab->link_options & LPA_EF_DUPLEX ) ) { + /* Half-duplex operation requires TX flow control */ + pause = 1; + } + EFAB_POPULATE_DWORD_4 ( reg, + GM_TX_EN, 1, + GM_TX_FC_EN, pause, + GM_RX_EN, 1, + GM_RX_FC_EN, 1 ); + falcon_gmac_writel ( efab, ®, GM_CFG1_REG_MAC ); + udelay ( 10 ); + + /* Configuration register 2 */ + if_mode = ( efab->link_options & LPA_EF_1000 ) ? 2 : 1; + full_duplex = ( efab->link_options & LPA_EF_DUPLEX ) ? 1 : 0; + EFAB_POPULATE_DWORD_4 ( reg, + GM_IF_MODE, if_mode, + GM_PAD_CRC_EN, 1, + GM_FD, full_duplex, + GM_PAMBL_LEN, 0x7 /* ? */ ); + falcon_gmac_writel ( efab, ®, GM_CFG2_REG_MAC ); + udelay ( 10 ); + + /* Max frame len register */ + EFAB_POPULATE_DWORD_1 ( reg, GM_MAX_FLEN, + EFAB_MAX_FRAME_LEN ( ETH_FRAME_LEN ) ); + falcon_gmac_writel ( efab, ®, GM_MAX_FLEN_REG_MAC ); + udelay ( 10 ); + + /* FIFO configuration register 0 */ + EFAB_POPULATE_DWORD_5 ( reg, + GMF_FTFENREQ, 1, + GMF_STFENREQ, 1, + GMF_FRFENREQ, 1, + GMF_SRFENREQ, 1, + GMF_WTMENREQ, 1 ); + falcon_gmac_writel ( efab, ®, GMF_CFG0_REG_MAC ); + udelay ( 10 ); + + /* FIFO configuration register 1 */ + EFAB_POPULATE_DWORD_2 ( reg, + GMF_CFGFRTH, 0x12, + GMF_CFGXOFFRTX, 0xffff ); + falcon_gmac_writel ( efab, ®, GMF_CFG1_REG_MAC ); + udelay ( 10 ); + + /* FIFO configuration register 2 */ + EFAB_POPULATE_DWORD_2 ( reg, + GMF_CFGHWM, 0x3f, + GMF_CFGLWM, 0xa ); + falcon_gmac_writel ( efab, ®, GMF_CFG2_REG_MAC ); + udelay ( 10 ); + + /* FIFO configuration register 3 */ + EFAB_POPULATE_DWORD_2 ( reg, + GMF_CFGHWMFT, 0x1c, + GMF_CFGFTTH, 0x08 ); + falcon_gmac_writel ( efab, ®, GMF_CFG3_REG_MAC ); + udelay ( 10 ); + + /* FIFO configuration register 4 */ + EFAB_POPULATE_DWORD_1 ( reg, GMF_HSTFLTRFRM_PAUSE, 1 ); + falcon_gmac_writel ( efab, ®, GMF_CFG4_REG_MAC ); + udelay ( 10 ); + + /* FIFO configuration register 5 */ + bytemode = ( efab->link_options & LPA_EF_1000 ) ? 1 : 0; + half_duplex = ( efab->link_options & LPA_EF_DUPLEX ) ? 0 : 1; + falcon_gmac_readl ( efab, ®, GMF_CFG5_REG_MAC ); + EFAB_SET_DWORD_FIELD ( reg, GMF_CFGBYTMODE, bytemode ); + EFAB_SET_DWORD_FIELD ( reg, GMF_CFGHDPLX, half_duplex ); + EFAB_SET_DWORD_FIELD ( reg, GMF_HSTDRPLT64, half_duplex ); + EFAB_SET_DWORD_FIELD ( reg, GMF_HSTFLTRFRMDC_PAUSE, 0 ); + falcon_gmac_writel ( efab, ®, GMF_CFG5_REG_MAC ); + udelay ( 10 ); + + /* MAC address */ + EFAB_POPULATE_DWORD_4 ( reg, + GM_HWADDR_5, efab->mac_addr[5], + GM_HWADDR_4, efab->mac_addr[4], + GM_HWADDR_3, efab->mac_addr[3], + GM_HWADDR_2, efab->mac_addr[2] ); + falcon_gmac_writel ( efab, ®, GM_ADR1_REG_MAC ); + udelay ( 10 ); + EFAB_POPULATE_DWORD_2 ( reg, + GM_HWADDR_1, efab->mac_addr[1], + GM_HWADDR_0, efab->mac_addr[0] ); + falcon_gmac_writel ( efab, ®, GM_ADR2_REG_MAC ); + udelay ( 10 ); +} + +static int +falcon_init_gmac ( struct efab_nic *efab ) +{ + /* Reset the MAC */ + mentormac_reset ( efab ); + + /* Initialise PHY */ + efab->phy_op->init ( efab ); + + /* check the link is up */ + if ( !efab->link_up ) + return -EAGAIN; + + /* Initialise MAC */ + mentormac_init ( efab ); + + /* reconfigure the MAC wrapper */ + falcon_reconfigure_mac_wrapper ( efab ); + + return 0; +} + +static struct efab_mac_operations falcon_gmac_operations = { + .init = falcon_init_gmac, +}; + + +/******************************************************************************* + * + * + * XMAC handling + * + * + *******************************************************************************/ + +/** + * Write dword to a Falcon XMAC register + * + */ +static void +falcon_xmac_writel ( struct efab_nic *efab, efab_dword_t *value, + unsigned int mac_reg ) +{ + efab_oword_t temp; + + EFAB_POPULATE_OWORD_1 ( temp, FCN_MAC_DATA, + EFAB_DWORD_FIELD ( *value, FCN_MAC_DATA ) ); + falcon_write ( efab, &temp, + FALCON_XMAC_REG ( efab, mac_reg ) ); +} + +/** + * Read dword from a Falcon XMAC register + * + */ +static void +falcon_xmac_readl ( struct efab_nic *efab, efab_dword_t *value, + unsigned int mac_reg ) +{ + efab_oword_t temp; + + falcon_read ( efab, &temp, + FALCON_XMAC_REG ( efab, mac_reg ) ); + EFAB_POPULATE_DWORD_1 ( *value, FCN_MAC_DATA, + EFAB_OWORD_FIELD ( temp, FCN_MAC_DATA ) ); +} + +/** + * Configure Falcon XAUI output + */ +static void +falcon_setup_xaui ( struct efab_nic *efab ) +{ + efab_dword_t sdctl, txdrv; + + falcon_xmac_readl ( efab, &sdctl, FCN_XX_SD_CTL_REG_MAC ); + EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT ); + EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVD, XX_SD_CTL_DRV_DEFAULT ); + EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT ); + EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVC, XX_SD_CTL_DRV_DEFAULT ); + EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT ); + EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVB, XX_SD_CTL_DRV_DEFAULT ); + EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT ); + EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVA, XX_SD_CTL_DRV_DEFAULT ); + falcon_xmac_writel ( efab, &sdctl, FCN_XX_SD_CTL_REG_MAC ); + + EFAB_POPULATE_DWORD_8 ( txdrv, + FCN_XX_DEQD, XX_TXDRV_DEQ_DEFAULT, + FCN_XX_DEQC, XX_TXDRV_DEQ_DEFAULT, + FCN_XX_DEQB, XX_TXDRV_DEQ_DEFAULT, + FCN_XX_DEQA, XX_TXDRV_DEQ_DEFAULT, + FCN_XX_DTXD, XX_TXDRV_DTX_DEFAULT, + FCN_XX_DTXC, XX_TXDRV_DTX_DEFAULT, + FCN_XX_DTXB, XX_TXDRV_DTX_DEFAULT, + FCN_XX_DTXA, XX_TXDRV_DTX_DEFAULT); + falcon_xmac_writel ( efab, &txdrv, FCN_XX_TXDRV_CTL_REG_MAC); +} + +static int +falcon_xgmii_status ( struct efab_nic *efab ) +{ + efab_dword_t reg; + + if ( efab->pci_revision < FALCON_REV_B0 ) + return 1; + /* The ISR latches, so clear it and re-read */ + falcon_xmac_readl ( efab, ®, FCN_XM_MGT_INT_REG_MAC_B0 ); + falcon_xmac_readl ( efab, ®, FCN_XM_MGT_INT_REG_MAC_B0 ); + + if ( EFAB_DWORD_FIELD ( reg, FCN_XM_LCLFLT ) || + EFAB_DWORD_FIELD ( reg, FCN_XM_RMTFLT ) ) { + EFAB_TRACE ( "MGT_INT: "EFAB_DWORD_FMT"\n", + EFAB_DWORD_VAL ( reg ) ); + return 0; + } + + return 1; +} + +static void +falcon_mask_status_intr ( struct efab_nic *efab, int enable ) +{ + efab_dword_t reg; + + if ( efab->pci_revision < FALCON_REV_B0 ) + return; + + /* Flush the ISR */ + if ( enable ) + falcon_xmac_readl ( efab, ®, FCN_XM_MGT_INT_REG_MAC_B0 ); + + EFAB_POPULATE_DWORD_2 ( reg, + FCN_XM_MSK_RMTFLT, !enable, + FCN_XM_MSK_LCLFLT, !enable); + falcon_xmac_readl ( efab, ®, FCN_XM_MGT_INT_MSK_REG_MAC_B0 ); +} + +/** + * Reset 10G MAC connected to port + * + */ +static int +falcon_reset_xmac ( struct efab_nic *efab ) +{ + efab_dword_t reg; + int count; + + EFAB_POPULATE_DWORD_1 ( reg, FCN_XM_CORE_RST, 1 ); + falcon_xmac_writel ( efab, ®, FCN_XM_GLB_CFG_REG_MAC ); + + for ( count = 0 ; count < 1000 ; count++ ) { + udelay ( 10 ); + falcon_xmac_readl ( efab, ®, + FCN_XM_GLB_CFG_REG_MAC ); + if ( EFAB_DWORD_FIELD ( reg, FCN_XM_CORE_RST ) == 0 ) + return 0; + } + return -ETIMEDOUT; +} + + +static int +falcon_reset_xaui ( struct efab_nic *efab ) +{ + efab_dword_t reg; + int count; + + if (!efab->is_asic) + return 0; + + EFAB_POPULATE_DWORD_1 ( reg, FCN_XX_RST_XX_EN, 1 ); + falcon_xmac_writel ( efab, ®, FCN_XX_PWR_RST_REG_MAC ); + + /* Give some time for the link to establish */ + for (count = 0; count < 1000; count++) { /* wait upto 10ms */ + falcon_xmac_readl ( efab, ®, FCN_XX_PWR_RST_REG_MAC ); + if ( EFAB_DWORD_FIELD ( reg, FCN_XX_RST_XX_EN ) == 0 ) { + falcon_setup_xaui ( efab ); + return 0; + } + udelay(10); + } + EFAB_ERR ( "timed out waiting for XAUI/XGXS reset\n" ); + return -ETIMEDOUT; +} + +static int +falcon_xaui_link_ok ( struct efab_nic *efab ) +{ + efab_dword_t reg; + int align_done, lane_status, sync; + int has_phyxs; + int link_ok = 1; + + /* Read Falcon XAUI side */ + if ( efab->is_asic ) { + /* Read link status */ + falcon_xmac_readl ( efab, ®, FCN_XX_CORE_STAT_REG_MAC ); + align_done = EFAB_DWORD_FIELD ( reg, FCN_XX_ALIGN_DONE ); + + sync = EFAB_DWORD_FIELD ( reg, FCN_XX_SYNC_STAT ); + sync = ( sync == FCN_XX_SYNC_STAT_DECODE_SYNCED ); + + link_ok = align_done && sync; + } + + /* Clear link status ready for next read */ + EFAB_SET_DWORD_FIELD ( reg, FCN_XX_COMMA_DET, FCN_XX_COMMA_DET_RESET ); + EFAB_SET_DWORD_FIELD ( reg, FCN_XX_CHARERR, FCN_XX_CHARERR_RESET); + EFAB_SET_DWORD_FIELD ( reg, FCN_XX_DISPERR, FCN_XX_DISPERR_RESET); + falcon_xmac_writel ( efab, ®, FCN_XX_CORE_STAT_REG_MAC ); + + has_phyxs = ( efab->phy_op->mmds & ( 1 << MDIO_MMD_PHYXS ) ); + if ( link_ok && has_phyxs ) { + lane_status = falcon_mdio_read ( efab, MDIO_MMD_PHYXS, + MDIO_PHYXS_LANE_STATE ); + link_ok = ( lane_status & ( 1 << MDIO_PHYXS_LANE_ALIGNED_LBN ) ); + + if (!link_ok ) + EFAB_LOG ( "XGXS lane status: %x\n", lane_status ); + } + + return link_ok; +} + +/** + * Initialise XMAC + * + */ +static void +falcon_reconfigure_xmac ( struct efab_nic *efab ) +{ + efab_dword_t reg; + int max_frame_len; + + /* Configure MAC - cut-thru mode is hard wired on */ + EFAB_POPULATE_DWORD_3 ( reg, + FCN_XM_RX_JUMBO_MODE, 1, + FCN_XM_TX_STAT_EN, 1, + FCN_XM_RX_STAT_EN, 1); + falcon_xmac_writel ( efab, ®, FCN_XM_GLB_CFG_REG_MAC ); + + /* Configure TX */ + EFAB_POPULATE_DWORD_6 ( reg, + FCN_XM_TXEN, 1, + FCN_XM_TX_PRMBL, 1, + FCN_XM_AUTO_PAD, 1, + FCN_XM_TXCRC, 1, + FCN_XM_FCNTL, 1, + FCN_XM_IPG, 0x3 ); + falcon_xmac_writel ( efab, ®, FCN_XM_TX_CFG_REG_MAC ); + + /* Configure RX */ + EFAB_POPULATE_DWORD_4 ( reg, + FCN_XM_RXEN, 1, + FCN_XM_AUTO_DEPAD, 0, + FCN_XM_ACPT_ALL_MCAST, 1, + FCN_XM_PASS_CRC_ERR, 1 ); + falcon_xmac_writel ( efab, ®, FCN_XM_RX_CFG_REG_MAC ); + + /* Set frame length */ + max_frame_len = EFAB_MAX_FRAME_LEN ( ETH_FRAME_LEN ); + EFAB_POPULATE_DWORD_1 ( reg, + FCN_XM_MAX_RX_FRM_SIZE, max_frame_len ); + falcon_xmac_writel ( efab, ®, FCN_XM_RX_PARAM_REG_MAC ); + EFAB_POPULATE_DWORD_2 ( reg, + FCN_XM_MAX_TX_FRM_SIZE, max_frame_len, + FCN_XM_TX_JUMBO_MODE, 1 ); + falcon_xmac_writel ( efab, ®, FCN_XM_TX_PARAM_REG_MAC ); + + /* Enable flow control receipt */ + EFAB_POPULATE_DWORD_2 ( reg, + FCN_XM_PAUSE_TIME, 0xfffe, + FCN_XM_DIS_FCNTL, 0 ); + falcon_xmac_writel ( efab, ®, FCN_XM_FC_REG_MAC ); + + /* Set MAC address */ + EFAB_POPULATE_DWORD_4 ( reg, + FCN_XM_ADR_0, efab->mac_addr[0], + FCN_XM_ADR_1, efab->mac_addr[1], + FCN_XM_ADR_2, efab->mac_addr[2], + FCN_XM_ADR_3, efab->mac_addr[3] ); + falcon_xmac_writel ( efab, ®, FCN_XM_ADR_LO_REG_MAC ); + EFAB_POPULATE_DWORD_2 ( reg, + FCN_XM_ADR_4, efab->mac_addr[4], + FCN_XM_ADR_5, efab->mac_addr[5] ); + falcon_xmac_writel ( efab, ®, FCN_XM_ADR_HI_REG_MAC ); +} + +static int +falcon_init_xmac ( struct efab_nic *efab ) +{ + int count, rc; + + /* Mask the PHY management interrupt */ + falcon_mask_status_intr ( efab, 0 ); + + /* Initialise the PHY to instantiate the clock. */ + rc = efab->phy_op->init ( efab ); + if ( rc ) { + EFAB_ERR ( "unable to initialise PHY\n" ); + goto fail1; + } + + falcon_reset_xaui ( efab ); + + /* Give the PHY and MAC time to faff */ + mdelay ( 100 ); + + /* Reset and reconfigure the XMAC */ + rc = falcon_reset_xmac ( efab ); + if ( rc ) + goto fail2; + falcon_reconfigure_xmac ( efab ); + falcon_reconfigure_mac_wrapper ( efab ); + /** + * Now wait for the link to come up. This may take a while + * for some slower PHY's. + */ + for (count=0; count<50; count++) { + int link_ok = 1; + + /* Wait a while for the link to come up. */ + mdelay ( 100 ); + if ((count % 5) == 0) + putchar ( '.' ); + + /* Does the PHY think the wire-side link is up? */ + link_ok = mdio_clause45_links_ok ( efab ); + /* Ensure the XAUI link to the PHY is good */ + if ( link_ok ) { + link_ok = falcon_xaui_link_ok ( efab ); + if ( !link_ok ) + falcon_reset_xaui ( efab ); + } + + /* Check fault indication */ + if ( link_ok ) + link_ok = falcon_xgmii_status ( efab ); + + efab->link_up = link_ok; + if ( link_ok ) { + /* unmask the status interrupt */ + falcon_mask_status_intr ( efab, 1 ); + return 0; + } + } + + /* Link failed to come up, but initialisation was fine. */ + rc = -ETIMEDOUT; + +fail2: +fail1: + return rc; +} + +static struct efab_mac_operations falcon_xmac_operations = { + .init = falcon_init_xmac, +}; + +/******************************************************************************* + * + * + * Null PHY handling + * + * + *******************************************************************************/ + +static int +falcon_xaui_phy_init ( struct efab_nic *efab ) +{ + /* CX4 is always 10000FD only */ + efab->link_options = LPA_EF_10000FULL; + + /* There is no PHY! */ + return 0; +} + +static struct efab_phy_operations falcon_xaui_phy_ops = { + .init = falcon_xaui_phy_init, + .mmds = 0, +}; + + +/******************************************************************************* + * + * + * Alaska PHY + * + * + *******************************************************************************/ + +/** + * Initialise Alaska PHY + * + */ +static int +alaska_init ( struct efab_nic *efab ) +{ + unsigned int advertised, lpa; + + /* Read link up status */ + efab->link_up = gmii_link_ok ( efab ); + + if ( ! efab->link_up ) + return -EIO; + + /* Determine link options from PHY. */ + advertised = gmii_autoneg_advertised ( efab ); + lpa = gmii_autoneg_lpa ( efab ); + efab->link_options = gmii_nway_result ( advertised & lpa ); + + return 0; +} + +static struct efab_phy_operations falcon_alaska_phy_ops = { + .init = alaska_init, +}; + +/******************************************************************************* + * + * + * xfp + * + * + *******************************************************************************/ + +#define XFP_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PCS | \ + MDIO_MMDREG_DEVS0_PMAPMD | \ + MDIO_MMDREG_DEVS0_PHYXS ) + +static int +falcon_xfp_phy_init ( struct efab_nic *efab ) +{ + int rc; + + /* Optical link is always 10000FD only */ + efab->link_options = LPA_EF_10000FULL; + + /* Reset the PHY */ + rc = mdio_clause45_reset_mmd ( efab, MDIO_MMD_PHYXS ); + if ( rc ) + return rc; + + return 0; +} + +static struct efab_phy_operations falcon_xfp_phy_ops = { + .init = falcon_xfp_phy_init, + .mmds = XFP_REQUIRED_DEVS, +}; + +/******************************************************************************* + * + * + * txc43128 + * + * + *******************************************************************************/ + +/* Command register */ +#define TXC_GLRGS_GLCMD (0xc004) +#define TXC_GLCMD_LMTSWRST_LBN (14) + +/* Amplitude on lanes 0+1, 2+3 */ +#define TXC_ALRGS_ATXAMP0 (0xc041) +#define TXC_ALRGS_ATXAMP1 (0xc042) +/* Bit position of value for lane 0+2, 1+3 */ +#define TXC_ATXAMP_LANE02_LBN (3) +#define TXC_ATXAMP_LANE13_LBN (11) + +#define TXC_ATXAMP_1280_mV (0) +#define TXC_ATXAMP_1200_mV (8) +#define TXC_ATXAMP_1120_mV (12) +#define TXC_ATXAMP_1060_mV (14) +#define TXC_ATXAMP_0820_mV (25) +#define TXC_ATXAMP_0720_mV (26) +#define TXC_ATXAMP_0580_mV (27) +#define TXC_ATXAMP_0440_mV (28) + +#define TXC_ATXAMP_0820_BOTH ( (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE02_LBN) | \ + (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE13_LBN) ) + +#define TXC_ATXAMP_DEFAULT (0x6060) /* From databook */ + +/* Preemphasis on lanes 0+1, 2+3 */ +#define TXC_ALRGS_ATXPRE0 (0xc043) +#define TXC_ALRGS_ATXPRE1 (0xc044) + +#define TXC_ATXPRE_NONE (0) +#define TXC_ATXPRE_DEFAULT (0x1010) /* From databook */ + +#define TXC_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PCS | \ + MDIO_MMDREG_DEVS0_PMAPMD | \ + MDIO_MMDREG_DEVS0_PHYXS ) + +static int +falcon_txc_logic_reset ( struct efab_nic *efab ) +{ + int val; + int tries = 50; + + val = falcon_mdio_read ( efab, MDIO_MMD_PCS, TXC_GLRGS_GLCMD ); + val |= (1 << TXC_GLCMD_LMTSWRST_LBN); + falcon_mdio_write ( efab, MDIO_MMD_PCS, TXC_GLRGS_GLCMD, val ); + + while ( tries--) { + val = falcon_mdio_read ( efab, MDIO_MMD_PCS, TXC_GLRGS_GLCMD ); + if ( ~val & ( 1 << TXC_GLCMD_LMTSWRST_LBN ) ) + return 0; + udelay(1); + } + + EFAB_ERR ( "logic reset failed\n" ); + + return -ETIMEDOUT; +} + +static int +falcon_txc_phy_init ( struct efab_nic *efab ) +{ + int rc; + + /* CX4 is always 10000FD only */ + efab->link_options = LPA_EF_10000FULL; + + /* reset the phy */ + rc = mdio_clause45_reset_mmd ( efab, MDIO_MMD_PMAPMD ); + if ( rc ) + goto fail1; + + rc = mdio_clause45_check_mmds ( efab ); + if ( rc ) + goto fail2; + + /* Turn amplitude down and preemphasis off on the host side + * (PHY<->MAC) as this is believed less likely to upset falcon + * and no adverse effects have been noted. It probably also + * saves a picowatt or two */ + + /* Turn off preemphasis */ + falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE0, + TXC_ATXPRE_NONE ); + falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE1, + TXC_ATXPRE_NONE ); + + /* Turn down the amplitude */ + falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXAMP0, + TXC_ATXAMP_0820_BOTH ); + falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXAMP1, + TXC_ATXAMP_0820_BOTH ); + + /* Set the line side amplitude and preemphasis to the databook + * defaults as an erratum causes them to be 0 on at least some + * PHY rev.s */ + falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXPRE0, + TXC_ATXPRE_DEFAULT ); + falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXPRE1, + TXC_ATXPRE_DEFAULT ); + falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXAMP0, + TXC_ATXAMP_DEFAULT ); + falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXAMP1, + TXC_ATXAMP_DEFAULT ); + + rc = falcon_txc_logic_reset ( efab ); + if ( rc ) + goto fail3; + + return 0; + +fail3: +fail2: +fail1: + return rc; +} + +static struct efab_phy_operations falcon_txc_phy_ops = { + .init = falcon_txc_phy_init, + .mmds = TXC_REQUIRED_DEVS, +}; + +/******************************************************************************* + * + * + * tenxpress + * + * + *******************************************************************************/ + + +#define TENXPRESS_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PMAPMD | \ + MDIO_MMDREG_DEVS0_PCS | \ + MDIO_MMDREG_DEVS0_PHYXS ) + +#define PCS_TEST_SELECT_REG 0xd807 /* PRM 10.5.8 */ +#define CLK312_EN_LBN 3 +#define CLK312_EN_WIDTH 1 + +#define PCS_CLOCK_CTRL_REG 0xd801 +#define PLL312_RST_N_LBN 2 + +/* Special Software reset register */ +#define PMA_PMD_EXT_CTRL_REG 49152 +#define PMA_PMD_EXT_SSR_LBN 15 + +/* Boot status register */ +#define PCS_BOOT_STATUS_REG 0xd000 +#define PCS_BOOT_FATAL_ERR_LBN 0 +#define PCS_BOOT_PROGRESS_LBN 1 +#define PCS_BOOT_PROGRESS_WIDTH 2 +#define PCS_BOOT_COMPLETE_LBN 3 + +#define PCS_SOFT_RST2_REG 0xd806 +#define SERDES_RST_N_LBN 13 +#define XGXS_RST_N_LBN 12 + +static int +falcon_tenxpress_check_c11 ( struct efab_nic *efab ) +{ + int count; + uint32_t boot_stat; + + /* Check that the C11 CPU has booted */ + for (count=0; count<10; count++) { + boot_stat = falcon_mdio_read ( efab, MDIO_MMD_PCS, + PCS_BOOT_STATUS_REG ); + if ( boot_stat & ( 1 << PCS_BOOT_COMPLETE_LBN ) ) + return 0; + + udelay(10); + } + + EFAB_ERR ( "C11 failed to boot\n" ); + return -ETIMEDOUT; +} + +static int +falcon_tenxpress_phy_init ( struct efab_nic *efab ) +{ + int rc, reg; + + /* 10XPRESS is always 10000FD (at the moment) */ + efab->link_options = LPA_EF_10000FULL; + + /* Wait for the blocks to come out of reset */ + rc = mdio_clause45_wait_reset_mmds ( efab ); + if ( rc ) + goto fail1; + + rc = mdio_clause45_check_mmds ( efab ); + if ( rc ) + goto fail2; + + /* Turn on the clock */ + reg = (1 << CLK312_EN_LBN); + falcon_mdio_write ( efab, MDIO_MMD_PCS, PCS_TEST_SELECT_REG, reg); + + /* Wait 200ms for the PHY to boot */ + mdelay(200); + + rc = falcon_tenxpress_check_c11 ( efab ); + if ( rc ) + goto fail3; + + return 0; + +fail3: +fail2: +fail1: + return rc; +} + +static struct efab_phy_operations falcon_tenxpress_phy_ops = { + .init = falcon_tenxpress_phy_init, + .mmds = TENXPRESS_REQUIRED_DEVS, +}; + +/******************************************************************************* + * + * + * PM8358 + * + * + *******************************************************************************/ + +/* The PM8358 just presents a DTE XS */ +#define PM8358_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_DTEXS) + +/* PHY-specific definitions */ +/* Master ID and Global Performance Monitor Update */ +#define PMC_MASTER_REG (0xd000) +/* Analog Tx Rx settings under software control */ +#define PMC_MASTER_ANLG_CTRL (1<< 11) + +/* Master Configuration register 2 */ +#define PMC_MCONF2_REG (0xd002) +/* Drive Tx off centre of data eye (1) vs. clock edge (0) */ +#define PMC_MCONF2_TEDGE (1 << 2) +/* Drive Rx off centre of data eye (1) vs. clock edge (0) */ +#define PMC_MCONF2_REDGE (1 << 3) + +/* Analog Rx settings */ +#define PMC_ANALOG_RX_CFG0 (0xd025) +#define PMC_ANALOG_RX_CFG1 (0xd02d) +#define PMC_ANALOG_RX_CFG2 (0xd035) +#define PMC_ANALOG_RX_CFG3 (0xd03d) + + +#define PMC_ANALOG_RX_TERM (1 << 15) /* Bit 15 of RX CFG: 0 for 100 ohms float, + 1 for 50 to 1.2V */ +#define PMC_ANALOG_RX_EQ_MASK (3 << 8) +#define PMC_ANALOG_RX_EQ_NONE (0 << 8) +#define PMC_ANALOG_RX_EQ_HALF (1 << 8) +#define PMC_ANALOG_RX_EQ_FULL (2 << 8) +#define PMC_ANALOG_RX_EQ_RSVD (3 << 8) + +static int +falcon_pm8358_phy_init ( struct efab_nic *efab ) +{ + int rc, reg, i; + + /* This is a XAUI retimer part */ + efab->link_options = LPA_EF_10000FULL; + + rc = mdio_clause45_reset_mmd ( efab, MDIO_MMDREG_DEVS0_DTEXS ); + if ( rc ) + return rc; + + /* Enable software control of analogue settings */ + reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS, PMC_MASTER_REG ); + reg |= PMC_MASTER_ANLG_CTRL; + falcon_mdio_write ( efab, MDIO_MMD_DTEXS, PMC_MASTER_REG, reg ); + + /* Turn rx eq on for all channels */ + for (i=0; i< 3; i++) { + /* The analog CFG registers are evenly spaced 8 apart */ + uint16_t addr = PMC_ANALOG_RX_CFG0 + 8*i; + reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS, addr ); + reg = ( reg & ~PMC_ANALOG_RX_EQ_MASK ) | PMC_ANALOG_RX_EQ_FULL; + falcon_mdio_write ( efab, MDIO_MMD_DTEXS, addr, reg ); + } + + /* Set TEDGE, clear REDGE */ + reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS, PMC_MCONF2_REG ); + reg = ( reg & ~PMC_MCONF2_REDGE) | PMC_MCONF2_TEDGE; + falcon_mdio_write ( efab, MDIO_MMD_DTEXS, PMC_MCONF2_REG, reg ); + + return 0; +} + +static struct efab_phy_operations falcon_pm8358_phy_ops = { + .init = falcon_pm8358_phy_init, + .mmds = PM8358_REQUIRED_DEVS, +}; + +/******************************************************************************* + * + * + * SFE4001 support + * + * + *******************************************************************************/ + +#define MAX_TEMP_THRESH 90 + +/* I2C Expander */ +#define PCA9539 0x74 + +#define P0_IN 0x00 +#define P0_OUT 0x02 +#define P0_CONFIG 0x06 + +#define P0_EN_1V0X_LBN 0 +#define P0_EN_1V0X_WIDTH 1 +#define P0_EN_1V2_LBN 1 +#define P0_EN_1V2_WIDTH 1 +#define P0_EN_2V5_LBN 2 +#define P0_EN_2V5_WIDTH 1 +#define P0_EN_3V3X_LBN 3 +#define P0_EN_3V3X_WIDTH 1 +#define P0_EN_5V_LBN 4 +#define P0_EN_5V_WIDTH 1 +#define P0_X_TRST_LBN 6 +#define P0_X_TRST_WIDTH 1 + +#define P1_IN 0x01 +#define P1_CONFIG 0x07 + +#define P1_AFE_PWD_LBN 0 +#define P1_AFE_PWD_WIDTH 1 +#define P1_DSP_PWD25_LBN 1 +#define P1_DSP_PWD25_WIDTH 1 +#define P1_SPARE_LBN 4 +#define P1_SPARE_WIDTH 4 + +/* Temperature Sensor */ +#define MAX6647 0x4e + +#define RSL 0x02 +#define RLHN 0x05 +#define WLHO 0x0b + +static struct i2c_device i2c_pca9539 = { + .dev_addr = PCA9539, + .dev_addr_len = 1, + .word_addr_len = 1, +}; + + +static struct i2c_device i2c_max6647 = { + .dev_addr = MAX6647, + .dev_addr_len = 1, + .word_addr_len = 1, +}; + +static int +sfe4001_init ( struct efab_nic *efab ) +{ + struct i2c_interface *i2c = &efab->i2c_bb.i2c; + efab_dword_t reg; + uint8_t in, cfg, out; + int count, rc; + + EFAB_LOG ( "Initialise SFE4001 board\n" ); + + /* Ensure XGXS and XAUI SerDes are held in reset */ + EFAB_POPULATE_DWORD_7 ( reg, + FCN_XX_PWRDNA_EN, 1, + FCN_XX_PWRDNB_EN, 1, + FCN_XX_RSTPLLAB_EN, 1, + FCN_XX_RESETA_EN, 1, + FCN_XX_RESETB_EN, 1, + FCN_XX_RSTXGXSRX_EN, 1, + FCN_XX_RSTXGXSTX_EN, 1 ); + falcon_xmac_writel ( efab, ®, FCN_XX_PWR_RST_REG_MAC); + udelay(10); + + /* Set DSP over-temperature alert threshold */ + cfg = MAX_TEMP_THRESH; + rc = i2c->write ( i2c, &i2c_max6647, WLHO, &cfg, EFAB_BYTE ); + if ( rc ) + goto fail1; + + /* Read it back and verify */ + rc = i2c->read ( i2c, &i2c_max6647, RLHN, &in, EFAB_BYTE ); + if ( rc ) + goto fail2; + + if ( in != MAX_TEMP_THRESH ) { + EFAB_ERR ( "Unable to verify MAX6647 limit (requested=%d " + "confirmed=%d)\n", cfg, in ); + rc = -EIO; + goto fail3; + } + + /* Clear any previous over-temperature alert */ + rc = i2c->read ( i2c, &i2c_max6647, RSL, &in, EFAB_BYTE ); + if ( rc ) + goto fail4; + + /* Enable port 0 and 1 outputs on IO expander */ + cfg = 0x00; + rc = i2c->write ( i2c, &i2c_pca9539, P0_CONFIG, &cfg, EFAB_BYTE ); + if ( rc ) + goto fail5; + cfg = 0xff & ~(1 << P1_SPARE_LBN); + rc = i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &cfg, EFAB_BYTE ); + if ( rc ) + goto fail6; + + /* Turn all power off then wait 1 sec. This ensures PHY is reset */ + out = 0xff & ~((0 << P0_EN_1V2_LBN) | (0 << P0_EN_2V5_LBN) | + (0 << P0_EN_3V3X_LBN) | (0 << P0_EN_5V_LBN) | + (0 << P0_EN_1V0X_LBN)); + + rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE ); + if ( rc ) + goto fail7; + + mdelay(1000); + + for (count=0; count<20; count++) { + /* Turn on 1.2V, 2.5V, 3.3V and 5V power rails */ + out = 0xff & ~( (1 << P0_EN_1V2_LBN) | (1 << P0_EN_2V5_LBN) | + (1 << P0_EN_3V3X_LBN) | (1 << P0_EN_5V_LBN) | + (1 << P0_X_TRST_LBN) ); + + rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE ); + if ( rc ) + goto fail8; + + mdelay ( 10 ); + + /* Turn on the 1V power rail */ + out &= ~( 1 << P0_EN_1V0X_LBN ); + rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE ); + if ( rc ) + goto fail9; + + EFAB_LOG ( "Waiting for power...(attempt %d)\n", count); + mdelay ( 1000 ); + + /* Check DSP is powered */ + rc = i2c->read ( i2c, &i2c_pca9539, P1_IN, &in, EFAB_BYTE ); + if ( rc ) + goto fail10; + + if ( in & ( 1 << P1_AFE_PWD_LBN ) ) + return 0; + } + + rc = -ETIMEDOUT; + +fail10: +fail9: +fail8: +fail7: + /* Turn off power rails */ + out = 0xff; + (void) i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE ); + /* Disable port 1 outputs on IO expander */ + out = 0xff; + (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &out, EFAB_BYTE ); +fail6: + /* Disable port 0 outputs */ + out = 0xff; + (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &out, EFAB_BYTE ); +fail5: +fail4: +fail3: +fail2: +fail1: + EFAB_ERR ( "Failed initialising SFE4001 board\n" ); + return rc; +} + +static void +sfe4001_fini ( struct efab_nic *efab ) +{ + struct i2c_interface *i2c = &efab->i2c_bb.i2c; + uint8_t in, cfg, out; + + EFAB_ERR ( "Turning off SFE4001\n" ); + + /* Turn off all power rails */ + out = 0xff; + (void) i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE ); + + /* Disable port 1 outputs on IO expander */ + cfg = 0xff; + (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &cfg, EFAB_BYTE ); + + /* Disable port 0 outputs on IO expander */ + cfg = 0xff; + (void) i2c->write ( i2c, &i2c_pca9539, P0_CONFIG, &cfg, EFAB_BYTE ); + + /* Clear any over-temperature alert */ + (void) i2c->read ( i2c, &i2c_max6647, RSL, &in, EFAB_BYTE ); +} + +struct efab_board_operations sfe4001_ops = { + .init = sfe4001_init, + .fini = sfe4001_fini, +}; + +static int sfe4002_init ( struct efab_nic *efab __attribute__((unused)) ) +{ + return 0; +} +static void sfe4002_fini ( struct efab_nic *efab __attribute__((unused)) ) +{ +} + +struct efab_board_operations sfe4002_ops = { + .init = sfe4002_init, + .fini = sfe4002_fini, +}; + +static int sfe4003_init ( struct efab_nic *efab __attribute__((unused)) ) +{ + return 0; +} +static void sfe4003_fini ( struct efab_nic *efab __attribute__((unused)) ) +{ +} + +struct efab_board_operations sfe4003_ops = { + .init = sfe4003_init, + .fini = sfe4003_fini, +}; + +/******************************************************************************* + * + * + * Hardware initialisation + * + * + *******************************************************************************/ + +static void +falcon_free_special_buffer ( void *p ) +{ + /* We don't bother cleaning up the buffer table entries - + * we're hardly limited */ + free_dma ( p, EFAB_BUF_ALIGN ); +} + +static void* +falcon_alloc_special_buffer ( struct efab_nic *efab, int bytes, + struct efab_special_buffer *entry ) +{ + void* buffer; + int remaining; + efab_qword_t buf_desc; + unsigned long dma_addr; + + /* Allocate the buffer, aligned on a buffer address boundary */ + buffer = malloc_dma ( bytes, EFAB_BUF_ALIGN ); + if ( ! buffer ) + return NULL; + + /* Push buffer table entries to back the buffer */ + entry->id = efab->buffer_head; + entry->dma_addr = dma_addr = virt_to_bus ( buffer ); + assert ( ( dma_addr & ( EFAB_BUF_ALIGN - 1 ) ) == 0 ); + + remaining = bytes; + while ( remaining > 0 ) { + EFAB_POPULATE_QWORD_3 ( buf_desc, + FCN_IP_DAT_BUF_SIZE, FCN_IP_DAT_BUF_SIZE_4K, + FCN_BUF_ADR_FBUF, ( dma_addr >> 12 ), + FCN_BUF_OWNER_ID_FBUF, 0 ); + + falcon_write_sram ( efab, &buf_desc, efab->buffer_head ); + + ++efab->buffer_head; + dma_addr += EFAB_BUF_ALIGN; + remaining -= EFAB_BUF_ALIGN; + } + + EFAB_TRACE ( "Allocated 0x%x bytes at %p backed by buffer table " + "entries 0x%x..0x%x\n", bytes, buffer, entry->id, + efab->buffer_head - 1 ); + + return buffer; +} + +static void +clear_b0_fpga_memories ( struct efab_nic *efab) +{ + efab_oword_t blanko, temp; + efab_dword_t blankd; + int offset; + + EFAB_ZERO_OWORD ( blanko ); + EFAB_ZERO_DWORD ( blankd ); + + /* Clear the address region register */ + EFAB_POPULATE_OWORD_4 ( temp, + FCN_ADR_REGION0, 0, + FCN_ADR_REGION1, ( 1 << 16 ), + FCN_ADR_REGION2, ( 2 << 16 ), + FCN_ADR_REGION3, ( 3 << 16 ) ); + falcon_write ( efab, &temp, FCN_ADR_REGION_REG_KER ); + + EFAB_TRACE ( "Clearing filter and RSS tables\n" ); + + for ( offset = FCN_RX_FILTER_TBL0 ; + offset < FCN_RX_RSS_INDIR_TBL_B0+0x800 ; + offset += 0x10 ) { + falcon_write ( efab, &blanko, offset ); + } + + EFAB_TRACE ( "Wiping buffer tables\n" ); + + /* Notice the 8 byte access mode */ + for ( offset = 0x2800000 ; + offset < 0x3000000 ; + offset += 0x8) { + _falcon_writel ( efab, 0, offset ); + _falcon_writel ( efab, 0, offset + 4 ); + wmb(); + } +} + +static int +falcon_reset ( struct efab_nic *efab ) +{ + efab_oword_t glb_ctl_reg_ker; + + /* Initiate software reset */ + EFAB_POPULATE_OWORD_6 ( glb_ctl_reg_ker, + FCN_PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET, + FCN_PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET, + FCN_PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET, + FCN_EE_RST_CTL, EXCLUDE_FROM_RESET, + FCN_EXT_PHY_RST_DUR, 0x7, /* 10ms */ + FCN_SWRST, 1 ); + + falcon_write ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER ); + + /* Allow 50ms for reset */ + mdelay ( 50 ); + + /* Check for device reset complete */ + falcon_read ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER ); + if ( EFAB_OWORD_FIELD ( glb_ctl_reg_ker, FCN_SWRST ) != 0 ) { + EFAB_ERR ( "Reset failed\n" ); + return -ETIMEDOUT; + } + + if ( ( efab->pci_revision == FALCON_REV_B0 ) && !efab->is_asic ) { + clear_b0_fpga_memories ( efab ); + } + + return 0; +} + +/** Offset of MAC address within EEPROM or Flash */ +#define FALCON_MAC_ADDRESS_OFFSET 0x310 + +/* + * Falcon EEPROM structure + */ +#define SF_NV_CONFIG_BASE 0x300 +#define SF_NV_CONFIG_EXTRA 0xA0 + +struct falcon_nv_config_ver2 { + uint16_t nports; + uint8_t port0_phy_addr; + uint8_t port0_phy_type; + uint8_t port1_phy_addr; + uint8_t port1_phy_type; + uint16_t asic_sub_revision; + uint16_t board_revision; + uint8_t mac_location; +}; + +struct falcon_nv_extra { + uint16_t magicnumber; + uint16_t structure_version; + uint16_t checksum; + union { + struct falcon_nv_config_ver2 ver2; + } ver_specific; +}; + +#define BOARD_TYPE(_rev) (_rev >> 8) + +static void +falcon_probe_nic_variant ( struct efab_nic *efab, struct pci_device *pci ) +{ + efab_oword_t altera_build, nic_stat; + int is_pcie, fpga_version; + uint8_t revision; + + /* PCI revision */ + pci_read_config_byte ( pci, PCI_CLASS_REVISION, &revision ); + efab->pci_revision = revision; + + /* Asic vs FPGA */ + falcon_read ( efab, &altera_build, FCN_ALTERA_BUILD_REG_KER ); + fpga_version = EFAB_OWORD_FIELD ( altera_build, FCN_VER_ALL ); + efab->is_asic = (fpga_version == 0); + + /* MAC and PCI type */ + falcon_read ( efab, &nic_stat, FCN_NIC_STAT_REG ); + if ( efab->pci_revision == FALCON_REV_B0 ) { + is_pcie = 1; + efab->phy_10g = EFAB_OWORD_FIELD ( nic_stat, FCN_STRAP_10G ); + } + else if ( efab->is_asic ) { + is_pcie = EFAB_OWORD_FIELD ( nic_stat, FCN_STRAP_PCIE ); + efab->phy_10g = EFAB_OWORD_FIELD ( nic_stat, FCN_STRAP_10G ); + } + else { + int minor = EFAB_OWORD_FIELD ( altera_build, FCN_VER_MINOR ); + is_pcie = 0; + efab->phy_10g = ( minor == 0x14 ); + } +} + +static void +falcon_init_spi_device ( struct efab_nic *efab, struct spi_device *spi ) +{ + /* Falcon's SPI interface only supports reads/writes of up to 16 bytes. + * Reduce the nvs block size down to satisfy this - which means callers + * should use the nvs_* functions rather than spi_*. */ + if ( spi->nvs.block_size > FALCON_SPI_MAX_LEN ) + spi->nvs.block_size = FALCON_SPI_MAX_LEN; + + spi->bus = &efab->spi_bus; + efab->spi = spi; +} + +static int +falcon_probe_spi ( struct efab_nic *efab ) +{ + efab_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; + int has_flash, has_eeprom, ad9bit; + + falcon_read ( efab, &nic_stat, FCN_NIC_STAT_REG ); + falcon_read ( efab, &gpio_ctl, FCN_GPIO_CTL_REG_KER ); + falcon_read ( efab, &ee_vpd_cfg, FCN_EE_VPD_CFG_REG ); + + /* determine if FLASH / EEPROM is present */ + if ( ( efab->pci_revision >= FALCON_REV_B0 ) || efab->is_asic ) { + has_flash = EFAB_OWORD_FIELD ( nic_stat, FCN_SF_PRST ); + has_eeprom = EFAB_OWORD_FIELD ( nic_stat, FCN_EE_PRST ); + } else { + has_flash = EFAB_OWORD_FIELD ( gpio_ctl, FCN_FLASH_PRESENT ); + has_eeprom = EFAB_OWORD_FIELD ( gpio_ctl, FCN_EEPROM_PRESENT ); + } + ad9bit = EFAB_OWORD_FIELD ( ee_vpd_cfg, FCN_EE_VPD_EN_AD9_MODE ); + + /* Configure the SPI and I2C bus */ + efab->spi_bus.rw = falcon_spi_rw; + init_i2c_bit_basher ( &efab->i2c_bb, &falcon_i2c_bit_ops ); + + /* Configure the EEPROM SPI device. Generally, an Atmel 25040 + * (or similar) is used, but this is only possible if there is also + * a flash device present to store the boot-time chip configuration. + */ + if ( has_eeprom ) { + if ( has_flash && ad9bit ) + init_at25040 ( &efab->spi_eeprom ); + else + init_mc25xx640 ( &efab->spi_eeprom ); + falcon_init_spi_device ( efab, &efab->spi_eeprom ); + } + + /* Configure the FLASH SPI device */ + if ( has_flash ) { + init_at25f1024 ( &efab->spi_flash ); + falcon_init_spi_device ( efab, &efab->spi_flash ); + } + + EFAB_LOG ( "flash is %s, EEPROM is %s%s\n", + ( has_flash ? "present" : "absent" ), + ( has_eeprom ? "present " : "absent" ), + ( has_eeprom ? (ad9bit ? "(9bit)" : "(16bit)") : "") ); + + /* The device MUST have flash or eeprom */ + if ( ! efab->spi ) { + EFAB_ERR ( "Device appears to have no flash or eeprom\n" ); + return -EIO; + } + + /* If the device has EEPROM attached, then advertise NVO space */ + if ( has_eeprom ) + nvo_init ( &efab->nvo, &efab->spi_eeprom.nvs, falcon_nvo_fragments, + &efab->netdev->refcnt ); + + return 0; +} + +static int +falcon_probe_nvram ( struct efab_nic *efab ) +{ + struct nvs_device *nvs = &efab->spi->nvs; + struct falcon_nv_extra nv; + int rc, board_revision; + + /* Read the MAC address */ + rc = nvs_read ( nvs, FALCON_MAC_ADDRESS_OFFSET, + efab->mac_addr, ETH_ALEN ); + if ( rc ) + return rc; + + /* Poke through the NVRAM structure for the PHY type. */ + rc = nvs_read ( nvs, SF_NV_CONFIG_BASE + SF_NV_CONFIG_EXTRA, + &nv, sizeof ( nv ) ); + if ( rc ) + return rc; + + /* Handle each supported NVRAM version */ + if ( ( le16_to_cpu ( nv.magicnumber ) == FCN_NV_MAGIC_NUMBER ) && + ( le16_to_cpu ( nv.structure_version ) >= 2 ) ) { + struct falcon_nv_config_ver2* ver2 = &nv.ver_specific.ver2; + + /* Get the PHY type */ + efab->phy_addr = le16_to_cpu ( ver2->port0_phy_addr ); + efab->phy_type = le16_to_cpu ( ver2->port0_phy_type ); + board_revision = le16_to_cpu ( ver2->board_revision ); + } + else { + EFAB_ERR ( "NVram is not recognised\n" ); + return -EINVAL; + } + + efab->board_type = BOARD_TYPE ( board_revision ); + + EFAB_TRACE ( "Falcon board %d phy %d @ addr %d\n", + efab->board_type, efab->phy_type, efab->phy_addr ); + + /* Patch in the board operations */ + switch ( efab->board_type ) { + case EFAB_BOARD_SFE4001: + efab->board_op = &sfe4001_ops; + break; + case EFAB_BOARD_SFE4002: + efab->board_op = &sfe4002_ops; + break; + case EFAB_BOARD_SFE4003: + efab->board_op = &sfe4003_ops; + break; + default: + EFAB_ERR ( "Unrecognised board type\n" ); + return -EINVAL; + } + + /* Patch in MAC operations */ + if ( efab->phy_10g ) + efab->mac_op = &falcon_xmac_operations; + else + efab->mac_op = &falcon_gmac_operations; + + /* Hook in the PHY ops */ + switch ( efab->phy_type ) { + case PHY_TYPE_10XPRESS: + efab->phy_op = &falcon_tenxpress_phy_ops; + break; + case PHY_TYPE_CX4: + efab->phy_op = &falcon_xaui_phy_ops; + break; + case PHY_TYPE_XFP: + efab->phy_op = &falcon_xfp_phy_ops; + break; + case PHY_TYPE_CX4_RTMR: + efab->phy_op = &falcon_txc_phy_ops; + break; + case PHY_TYPE_PM8358: + efab->phy_op = &falcon_pm8358_phy_ops; + break; + case PHY_TYPE_1GIG_ALASKA: + efab->phy_op = &falcon_alaska_phy_ops; + break; + default: + EFAB_ERR ( "Unknown PHY type: %d\n", efab->phy_type ); + return -EINVAL; + } + + return 0; +} + +static int +falcon_init_sram ( struct efab_nic *efab ) +{ + efab_oword_t reg; + int count; + + /* use card in internal SRAM mode */ + falcon_read ( efab, ®, FCN_NIC_STAT_REG ); + EFAB_SET_OWORD_FIELD ( reg, FCN_ONCHIP_SRAM, 1 ); + falcon_write ( efab, ®, FCN_NIC_STAT_REG ); + + /* Deactivate any external SRAM that might be present */ + EFAB_POPULATE_OWORD_2 ( reg, + FCN_GPIO1_OEN, 1, + FCN_GPIO1_OUT, 1 ); + falcon_write ( efab, ®, FCN_GPIO_CTL_REG_KER ); + + /* Initiate SRAM reset */ + EFAB_POPULATE_OWORD_2 ( reg, + FCN_SRAM_OOB_BT_INIT_EN, 1, + FCN_SRM_NUM_BANKS_AND_BANK_SIZE, 0 ); + falcon_write ( efab, ®, FCN_SRM_CFG_REG_KER ); + + /* Wait for SRAM reset to complete */ + count = 0; + do { + /* SRAM reset is slow; expect around 16ms */ + mdelay ( 20 ); + + /* Check for reset complete */ + falcon_read ( efab, ®, FCN_SRM_CFG_REG_KER ); + if ( !EFAB_OWORD_FIELD ( reg, FCN_SRAM_OOB_BT_INIT_EN ) ) + return 0; + } while (++count < 20); /* wait upto 0.4 sec */ + + EFAB_ERR ( "timed out waiting for SRAM reset\n"); + return -ETIMEDOUT; +} + +static void +falcon_setup_nic ( struct efab_nic *efab ) +{ + efab_dword_t timer_cmd; + efab_oword_t reg; + int tx_fc, xoff_thresh, xon_thresh; + + /* bug5129: Clear the parity enables on the TX data fifos as + * they produce false parity errors because of timing issues + */ + falcon_read ( efab, ®, FCN_SPARE_REG_KER ); + EFAB_SET_OWORD_FIELD ( reg, FCN_MEM_PERR_EN_TX_DATA, 0 ); + falcon_write ( efab, ®, FCN_SPARE_REG_KER ); + + /* Set up TX and RX descriptor caches in SRAM */ + EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_TX_DC_BASE_ADR, 0x130000 ); + falcon_write ( efab, ®, FCN_SRM_TX_DC_CFG_REG_KER ); + EFAB_POPULATE_OWORD_1 ( reg, FCN_TX_DC_SIZE, 1 /* 16 descriptors */ ); + falcon_write ( efab, ®, FCN_TX_DC_CFG_REG_KER ); + EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_RX_DC_BASE_ADR, 0x100000 ); + falcon_write ( efab, ®, FCN_SRM_RX_DC_CFG_REG_KER ); + EFAB_POPULATE_OWORD_1 ( reg, FCN_RX_DC_SIZE, 2 /* 32 descriptors */ ); + falcon_write ( efab, ®, FCN_RX_DC_CFG_REG_KER ); + + /* Set number of RSS CPUs + * bug7244: Increase filter depth to reduce RX_RESET likelyhood + */ + EFAB_POPULATE_OWORD_5 ( reg, + FCN_NUM_KER, 0, + FCN_UDP_FULL_SRCH_LIMIT, 8, + FCN_UDP_WILD_SRCH_LIMIT, 8, + FCN_TCP_WILD_SRCH_LIMIT, 8, + FCN_TCP_FULL_SRCH_LIMIT, 8); + falcon_write ( efab, ®, FCN_RX_FILTER_CTL_REG_KER ); + udelay ( 1000 ); + + /* Setup RX. Wait for descriptor is broken and must + * be disabled. RXDP recovery shouldn't be needed, but is. + * disable ISCSI parsing because we don't need it + */ + falcon_read ( efab, ®, FCN_RX_SELF_RST_REG_KER ); + EFAB_SET_OWORD_FIELD ( reg, FCN_RX_NODESC_WAIT_DIS, 1 ); + EFAB_SET_OWORD_FIELD ( reg, FCN_RX_RECOVERY_EN, 1 ); + EFAB_SET_OWORD_FIELD ( reg, FCN_RX_ISCSI_DIS, 1 ); + falcon_write ( efab, ®, FCN_RX_SELF_RST_REG_KER ); + + /* Determine recommended flow control settings. * + * Flow control is qualified on B0 and A1/1G, not on A1/10G */ + if ( efab->pci_revision == FALCON_REV_B0 ) { + tx_fc = 1; + xoff_thresh = 54272; /* ~80Kb - 3*max MTU */ + xon_thresh = 27648; /* ~3*max MTU */ + } + else if ( !efab->phy_10g ) { + tx_fc = 1; + xoff_thresh = 2048; + xon_thresh = 512; + } + else { + tx_fc = xoff_thresh = xon_thresh = 0; + } + + /* Setup TX and RX */ + falcon_read ( efab, ®, FCN_TX_CFG2_REG_KER ); + EFAB_SET_OWORD_FIELD ( reg, FCN_TX_DIS_NON_IP_EV, 1 ); + falcon_write ( efab, ®, FCN_TX_CFG2_REG_KER ); + + falcon_read ( efab, ®, FCN_RX_CFG_REG_KER ); + EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_USR_BUF_SIZE, + (3*4096) / 32 ); + if ( efab->pci_revision == FALCON_REV_B0) + EFAB_SET_OWORD_FIELD ( reg, FCN_RX_INGR_EN_B0, 1 ); + EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XON_MAC_TH, + xon_thresh / 256); + EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XOFF_MAC_TH, + xoff_thresh / 256); + EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XOFF_MAC_EN, tx_fc); + falcon_write ( efab, ®, FCN_RX_CFG_REG_KER ); + + /* Set timer register */ + EFAB_POPULATE_DWORD_2 ( timer_cmd, + FCN_TIMER_MODE, FCN_TIMER_MODE_DIS, + FCN_TIMER_VAL, 0 ); + falcon_writel ( efab, &timer_cmd, FCN_TIMER_CMD_REG_KER ); +} + +static void +falcon_init_resources ( struct efab_nic *efab ) +{ + struct efab_ev_queue *ev_queue = &efab->ev_queue; + struct efab_rx_queue *rx_queue = &efab->rx_queue; + struct efab_tx_queue *tx_queue = &efab->tx_queue; + + efab_oword_t reg; + int jumbo; + + /* Initialise the ptrs */ + tx_queue->read_ptr = tx_queue->write_ptr = 0; + rx_queue->read_ptr = rx_queue->write_ptr = 0; + ev_queue->read_ptr = 0; + + /* Push the event queue to the hardware */ + EFAB_POPULATE_OWORD_3 ( reg, + FCN_EVQ_EN, 1, + FCN_EVQ_SIZE, FQS(FCN_EVQ, EFAB_EVQ_SIZE), + FCN_EVQ_BUF_BASE_ID, ev_queue->entry.id ); + falcon_write ( efab, ®, + FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) ); + + /* Push the tx queue to the hardware */ + EFAB_POPULATE_OWORD_8 ( reg, + FCN_TX_DESCQ_EN, 1, + FCN_TX_ISCSI_DDIG_EN, 0, + FCN_TX_ISCSI_DDIG_EN, 0, + FCN_TX_DESCQ_BUF_BASE_ID, tx_queue->entry.id, + FCN_TX_DESCQ_EVQ_ID, 0, + FCN_TX_DESCQ_SIZE, FQS(FCN_TX_DESCQ, EFAB_TXD_SIZE), + FCN_TX_DESCQ_TYPE, 0 /* kernel queue */, + FCN_TX_NON_IP_DROP_DIS_B0, 1 ); + falcon_write ( efab, ®, + FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) ); + + /* Push the rx queue to the hardware */ + jumbo = ( efab->pci_revision == FALCON_REV_B0 ) ? 0 : 1; + EFAB_POPULATE_OWORD_8 ( reg, + FCN_RX_ISCSI_DDIG_EN, 0, + FCN_RX_ISCSI_HDIG_EN, 0, + FCN_RX_DESCQ_BUF_BASE_ID, rx_queue->entry.id, + FCN_RX_DESCQ_EVQ_ID, 0, + FCN_RX_DESCQ_SIZE, FQS(FCN_RX_DESCQ, EFAB_RXD_SIZE), + FCN_RX_DESCQ_TYPE, 0 /* kernel queue */, + FCN_RX_DESCQ_JUMBO, jumbo, + FCN_RX_DESCQ_EN, 1 ); + falcon_write ( efab, ®, + FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) ); + + /* Program INT_ADR_REG_KER */ + EFAB_POPULATE_OWORD_1 ( reg, + FCN_INT_ADR_KER, virt_to_bus ( &efab->int_ker ) ); + falcon_write ( efab, ®, FCN_INT_ADR_REG_KER ); + + /* Ack the event queue */ + falcon_eventq_read_ack ( efab, ev_queue ); +} + +static void +falcon_fini_resources ( struct efab_nic *efab ) +{ + efab_oword_t cmd; + + /* Disable interrupts */ + falcon_interrupts ( efab, 0, 0 ); + + /* Flush the dma queues */ + EFAB_POPULATE_OWORD_2 ( cmd, + FCN_TX_FLUSH_DESCQ_CMD, 1, + FCN_TX_FLUSH_DESCQ, 0 ); + falcon_write ( efab, &cmd, + FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) ); + + EFAB_POPULATE_OWORD_2 ( cmd, + FCN_RX_FLUSH_DESCQ_CMD, 1, + FCN_RX_FLUSH_DESCQ, 0 ); + falcon_write ( efab, &cmd, + FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) ); + + mdelay ( 100 ); + + /* Remove descriptor rings from card */ + EFAB_ZERO_OWORD ( cmd ); + falcon_write ( efab, &cmd, + FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) ); + falcon_write ( efab, &cmd, + FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) ); + falcon_write ( efab, &cmd, + FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) ); +} + +/******************************************************************************* + * + * + * Hardware rx path + * + * + *******************************************************************************/ + +static void +falcon_build_rx_desc ( falcon_rx_desc_t *rxd, struct io_buffer *iob ) +{ + EFAB_POPULATE_QWORD_2 ( *rxd, + FCN_RX_KER_BUF_SIZE, EFAB_RX_BUF_SIZE, + FCN_RX_KER_BUF_ADR, virt_to_bus ( iob->data ) ); +} + +static void +falcon_notify_rx_desc ( struct efab_nic *efab, struct efab_rx_queue *rx_queue ) +{ + efab_dword_t reg; + int ptr = rx_queue->write_ptr % EFAB_RXD_SIZE; + + EFAB_POPULATE_DWORD_1 ( reg, FCN_RX_DESC_WPTR_DWORD, ptr ); + falcon_writel ( efab, ®, FCN_RX_DESC_UPD_REG_KER_DWORD ); +} + + +/******************************************************************************* + * + * + * Hardware tx path + * + * + *******************************************************************************/ + +static void +falcon_build_tx_desc ( falcon_tx_desc_t *txd, struct io_buffer *iob ) +{ + EFAB_POPULATE_QWORD_2 ( *txd, + FCN_TX_KER_BYTE_CNT, iob_len ( iob ), + FCN_TX_KER_BUF_ADR, virt_to_bus ( iob->data ) ); +} + +static void +falcon_notify_tx_desc ( struct efab_nic *efab, + struct efab_tx_queue *tx_queue ) +{ + efab_dword_t reg; + int ptr = tx_queue->write_ptr % EFAB_TXD_SIZE; + + EFAB_POPULATE_DWORD_1 ( reg, FCN_TX_DESC_WPTR_DWORD, ptr ); + falcon_writel ( efab, ®, FCN_TX_DESC_UPD_REG_KER_DWORD ); +} + + +/******************************************************************************* + * + * + * Software receive interface + * + * + *******************************************************************************/ + +static int +efab_fill_rx_queue ( struct efab_nic *efab, + struct efab_rx_queue *rx_queue ) +{ + int fill_level = rx_queue->write_ptr - rx_queue->read_ptr; + int space = EFAB_NUM_RX_DESC - fill_level - 1; + int pushed = 0; + + while ( space ) { + int buf_id = rx_queue->write_ptr % EFAB_NUM_RX_DESC; + int desc_id = rx_queue->write_ptr % EFAB_RXD_SIZE; + struct io_buffer *iob; + falcon_rx_desc_t *rxd; + + assert ( rx_queue->buf[buf_id] == NULL ); + iob = alloc_iob ( EFAB_RX_BUF_SIZE ); + if ( !iob ) + break; + + EFAB_TRACE ( "pushing rx_buf[%d] iob %p data %p\n", + buf_id, iob, iob->data ); + + rx_queue->buf[buf_id] = iob; + rxd = rx_queue->ring + desc_id; + falcon_build_rx_desc ( rxd, iob ); + ++rx_queue->write_ptr; + ++pushed; + --space; + } + + if ( pushed ) { + /* Push the ptr to hardware */ + falcon_notify_rx_desc ( efab, rx_queue ); + + fill_level = rx_queue->write_ptr - rx_queue->read_ptr; + EFAB_TRACE ( "pushed %d rx buffers to fill level %d\n", + pushed, fill_level ); + } + + if ( fill_level == 0 ) + return -ENOMEM; + return 0; +} + +static void +efab_receive ( struct efab_nic *efab, unsigned int id, int len, int drop ) +{ + struct efab_rx_queue *rx_queue = &efab->rx_queue; + struct io_buffer *iob; + unsigned int read_ptr = rx_queue->read_ptr % EFAB_RXD_SIZE; + unsigned int buf_ptr = rx_queue->read_ptr % EFAB_NUM_RX_DESC; + + assert ( id == read_ptr ); + + /* Pop this rx buffer out of the software ring */ + iob = rx_queue->buf[buf_ptr]; + rx_queue->buf[buf_ptr] = NULL; + + EFAB_TRACE ( "popping rx_buf[%d] iob %p data %p with %d bytes %s\n", + id, iob, iob->data, len, drop ? "bad" : "ok" ); + + /* Pass the packet up if required */ + if ( drop ) + free_iob ( iob ); + else { + iob_put ( iob, len ); + netdev_rx ( efab->netdev, iob ); + } + + ++rx_queue->read_ptr; +} + +/******************************************************************************* + * + * + * Software transmit interface + * + * + *******************************************************************************/ + +static int +efab_transmit ( struct net_device *netdev, struct io_buffer *iob ) +{ + struct efab_nic *efab = netdev_priv ( netdev ); + struct efab_tx_queue *tx_queue = &efab->tx_queue; + int fill_level, space; + falcon_tx_desc_t *txd; + int buf_id; + + fill_level = tx_queue->write_ptr - tx_queue->read_ptr; + space = EFAB_TXD_SIZE - fill_level - 1; + if ( space < 1 ) + return -ENOBUFS; + + /* Save the iobuffer for later completion */ + buf_id = tx_queue->write_ptr % EFAB_TXD_SIZE; + assert ( tx_queue->buf[buf_id] == NULL ); + tx_queue->buf[buf_id] = iob; + + EFAB_TRACE ( "tx_buf[%d] for iob %p data %p len %zd\n", + buf_id, iob, iob->data, iob_len ( iob ) ); + + /* Form the descriptor, and push it to hardware */ + txd = tx_queue->ring + buf_id; + falcon_build_tx_desc ( txd, iob ); + ++tx_queue->write_ptr; + falcon_notify_tx_desc ( efab, tx_queue ); + + return 0; +} + +static int +efab_transmit_done ( struct efab_nic *efab, int id ) +{ + struct efab_tx_queue *tx_queue = &efab->tx_queue; + unsigned int read_ptr, stop; + + /* Complete all buffers from read_ptr up to and including id */ + read_ptr = tx_queue->read_ptr % EFAB_TXD_SIZE; + stop = ( id + 1 ) % EFAB_TXD_SIZE; + + while ( read_ptr != stop ) { + struct io_buffer *iob = tx_queue->buf[read_ptr]; + assert ( iob ); + + /* Complete the tx buffer */ + if ( iob ) + netdev_tx_complete ( efab->netdev, iob ); + tx_queue->buf[read_ptr] = NULL; + + ++tx_queue->read_ptr; + read_ptr = tx_queue->read_ptr % EFAB_TXD_SIZE; + } + + return 0; +} + +/******************************************************************************* + * + * + * Hardware event path + * + * + *******************************************************************************/ + +static void +falcon_clear_interrupts ( struct efab_nic *efab ) +{ + efab_dword_t reg; + + if ( efab->pci_revision == FALCON_REV_B0 ) { + /* read the ISR */ + falcon_readl( efab, ®, INT_ISR0_B0 ); + } + else { + /* write to the INT_ACK register */ + falcon_writel ( efab, 0, FCN_INT_ACK_KER_REG_A1 ); + mb(); + falcon_readl ( efab, ®, + WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 ); + } +} + +static void +falcon_handle_event ( struct efab_nic *efab, falcon_event_t *evt ) +{ + int ev_code, desc_ptr, len, drop; + + /* Decode event */ + ev_code = EFAB_QWORD_FIELD ( *evt, FCN_EV_CODE ); + switch ( ev_code ) { + case FCN_TX_IP_EV_DECODE: + desc_ptr = EFAB_QWORD_FIELD ( *evt, FCN_TX_EV_DESC_PTR ); + efab_transmit_done ( efab, desc_ptr ); + break; + + case FCN_RX_IP_EV_DECODE: + desc_ptr = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_DESC_PTR ); + len = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_BYTE_CNT ); + drop = !EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_PKT_OK ); + + efab_receive ( efab, desc_ptr, len, drop ); + break; + + default: + EFAB_TRACE ( "Unknown event type %d\n", ev_code ); + break; + } +} + +/******************************************************************************* + * + * + * Software (polling) interrupt handler + * + * + *******************************************************************************/ + +static void +efab_poll ( struct net_device *netdev ) +{ + struct efab_nic *efab = netdev_priv ( netdev ); + struct efab_ev_queue *ev_queue = &efab->ev_queue; + struct efab_rx_queue *rx_queue = &efab->rx_queue; + falcon_event_t *evt; + + /* Read the event queue by directly looking for events + * (we don't even bother to read the eventq write ptr) */ + evt = ev_queue->ring + ev_queue->read_ptr; + while ( falcon_event_present ( evt ) ) { + + EFAB_TRACE ( "Event at index 0x%x address %p is " + EFAB_QWORD_FMT "\n", ev_queue->read_ptr, + evt, EFAB_QWORD_VAL ( *evt ) ); + + falcon_handle_event ( efab, evt ); + + /* Clear the event */ + EFAB_SET_QWORD ( *evt ); + + /* Move to the next event. We don't ack the event + * queue until the end */ + ev_queue->read_ptr = ( ( ev_queue->read_ptr + 1 ) % + EFAB_EVQ_SIZE ); + evt = ev_queue->ring + ev_queue->read_ptr; + } + + /* Push more buffers if needed */ + (void) efab_fill_rx_queue ( efab, rx_queue ); + + /* Clear any pending interrupts */ + falcon_clear_interrupts ( efab ); + + /* Ack the event queue */ + falcon_eventq_read_ack ( efab, ev_queue ); +} + +static void +efab_irq ( struct net_device *netdev, int enable ) +{ + struct efab_nic *efab = netdev_priv ( netdev ); + struct efab_ev_queue *ev_queue = &efab->ev_queue; + + switch ( enable ) { + case 0: + falcon_interrupts ( efab, 0, 0 ); + break; + case 1: + falcon_interrupts ( efab, 1, 0 ); + falcon_eventq_read_ack ( efab, ev_queue ); + break; + case 2: + falcon_interrupts ( efab, 1, 1 ); + break; + } +} + +/******************************************************************************* + * + * + * Software open/close + * + * + *******************************************************************************/ + +static void +efab_free_resources ( struct efab_nic *efab ) +{ + struct efab_ev_queue *ev_queue = &efab->ev_queue; + struct efab_rx_queue *rx_queue = &efab->rx_queue; + struct efab_tx_queue *tx_queue = &efab->tx_queue; + int i; + + for ( i = 0; i < EFAB_NUM_RX_DESC; i++ ) { + if ( rx_queue->buf[i] ) + free_iob ( rx_queue->buf[i] ); + } + + for ( i = 0; i < EFAB_TXD_SIZE; i++ ) { + if ( tx_queue->buf[i] ) + netdev_tx_complete ( efab->netdev, tx_queue->buf[i] ); + } + + if ( rx_queue->ring ) + falcon_free_special_buffer ( rx_queue->ring ); + + if ( tx_queue->ring ) + falcon_free_special_buffer ( tx_queue->ring ); + + if ( ev_queue->ring ) + falcon_free_special_buffer ( ev_queue->ring ); + + memset ( rx_queue, 0, sizeof ( *rx_queue ) ); + memset ( tx_queue, 0, sizeof ( *tx_queue ) ); + memset ( ev_queue, 0, sizeof ( *ev_queue ) ); + + /* Ensure subsequent buffer allocations start at id 0 */ + efab->buffer_head = 0; +} + +static int +efab_alloc_resources ( struct efab_nic *efab ) +{ + struct efab_ev_queue *ev_queue = &efab->ev_queue; + struct efab_rx_queue *rx_queue = &efab->rx_queue; + struct efab_tx_queue *tx_queue = &efab->tx_queue; + size_t bytes; + + /* Allocate the hardware event queue */ + bytes = sizeof ( falcon_event_t ) * EFAB_TXD_SIZE; + ev_queue->ring = falcon_alloc_special_buffer ( efab, bytes, + &ev_queue->entry ); + if ( !ev_queue->ring ) + goto fail1; + + /* Initialise the hardware event queue */ + memset ( ev_queue->ring, 0xff, bytes ); + + /* Allocate the hardware tx queue */ + bytes = sizeof ( falcon_tx_desc_t ) * EFAB_TXD_SIZE; + tx_queue->ring = falcon_alloc_special_buffer ( efab, bytes, + &tx_queue->entry ); + if ( ! tx_queue->ring ) + goto fail2; + + /* Allocate the hardware rx queue */ + bytes = sizeof ( falcon_rx_desc_t ) * EFAB_RXD_SIZE; + rx_queue->ring = falcon_alloc_special_buffer ( efab, bytes, + &rx_queue->entry ); + if ( ! rx_queue->ring ) + goto fail3; + + return 0; + +fail3: + falcon_free_special_buffer ( tx_queue->ring ); + tx_queue->ring = NULL; +fail2: + falcon_free_special_buffer ( ev_queue->ring ); + ev_queue->ring = NULL; +fail1: + return -ENOMEM; +} + +static int +efab_init_mac ( struct efab_nic *efab ) +{ + int count, rc; + + /* This can take several seconds */ + EFAB_LOG ( "Waiting for link..\n" ); + for ( count=0; count<5; count++ ) { + rc = efab->mac_op->init ( efab ); + if ( rc ) { + EFAB_ERR ( "Failed reinitialising MAC, error %s\n", + strerror ( rc )); + return rc; + } + + /* Sleep for 2s to wait for the link to settle, either + * because we want to use it, or because we're about + * to reset the mac anyway + */ + sleep ( 2 ); + + if ( ! efab->link_up ) { + EFAB_ERR ( "!\n" ); + continue; + } + + EFAB_LOG ( "\n%dMbps %s-duplex\n", + ( efab->link_options & LPA_EF_10000 ? 10000 : + ( efab->link_options & LPA_EF_1000 ? 1000 : + ( efab->link_options & LPA_100 ? 100 : 10 ) ) ), + ( efab->link_options & LPA_EF_DUPLEX ? + "full" : "half" ) ); + + /* TODO: Move link state handling to the poll() routine */ + netdev_link_up ( efab->netdev ); + return 0; + } + + EFAB_ERR ( "timed initialising MAC\n" ); + return -ETIMEDOUT; +} + +static void +efab_close ( struct net_device *netdev ) +{ + struct efab_nic *efab = netdev_priv ( netdev ); + + falcon_fini_resources ( efab ); + efab_free_resources ( efab ); + efab->board_op->fini ( efab ); + falcon_reset ( efab ); +} + +static int +efab_open ( struct net_device *netdev ) +{ + struct efab_nic *efab = netdev_priv ( netdev ); + struct efab_rx_queue *rx_queue = &efab->rx_queue; + int rc; + + rc = falcon_reset ( efab ); + if ( rc ) + goto fail1; + + rc = efab->board_op->init ( efab ); + if ( rc ) + goto fail2; + + rc = falcon_init_sram ( efab ); + if ( rc ) + goto fail3; + + /* Configure descriptor caches before pushing hardware queues */ + falcon_setup_nic ( efab ); + + rc = efab_alloc_resources ( efab ); + if ( rc ) + goto fail4; + + falcon_init_resources ( efab ); + + /* Push rx buffers */ + rc = efab_fill_rx_queue ( efab, rx_queue ); + if ( rc ) + goto fail5; + + /* Try and bring the interface up */ + rc = efab_init_mac ( efab ); + if ( rc ) + goto fail6; + + return 0; + +fail6: +fail5: + efab_free_resources ( efab ); +fail4: +fail3: + efab->board_op->fini ( efab ); +fail2: + falcon_reset ( efab ); +fail1: + return rc; +} + +static struct net_device_operations efab_operations = { + .open = efab_open, + .close = efab_close, + .transmit = efab_transmit, + .poll = efab_poll, + .irq = efab_irq, +}; + +static void +efab_remove ( struct pci_device *pci ) +{ + struct net_device *netdev = pci_get_drvdata ( pci ); + struct efab_nic *efab = netdev_priv ( netdev ); + + if ( efab->membase ) { + falcon_reset ( efab ); + + iounmap ( efab->membase ); + efab->membase = NULL; + } + + if ( efab->nvo.nvs ) { + unregister_nvo ( &efab->nvo ); + efab->nvo.nvs = NULL; + } + + unregister_netdev ( netdev ); + netdev_nullify ( netdev ); + netdev_put ( netdev ); +} + +static int +efab_probe ( struct pci_device *pci, + const struct pci_device_id *id ) +{ + struct net_device *netdev; + struct efab_nic *efab; + unsigned long mmio_start, mmio_len; + int rc; + + /* Create the network adapter */ + netdev = alloc_etherdev ( sizeof ( struct efab_nic ) ); + if ( ! netdev ) { + rc = -ENOMEM; + goto fail1; + } + + /* Initialise the network adapter, and initialise private storage */ + netdev_init ( netdev, &efab_operations ); + pci_set_drvdata ( pci, netdev ); + netdev->dev = &pci->dev; + + efab = netdev_priv ( netdev ); + memset ( efab, 0, sizeof ( *efab ) ); + efab->netdev = netdev; + + /* Get iobase/membase */ + mmio_start = pci_bar_start ( pci, PCI_BASE_ADDRESS_2 ); + mmio_len = pci_bar_size ( pci, PCI_BASE_ADDRESS_2 ); + efab->membase = ioremap ( mmio_start, mmio_len ); + EFAB_TRACE ( "BAR of %lx bytes at phys %lx mapped at %p\n", + mmio_len, mmio_start, efab->membase ); + + /* Enable the PCI device */ + adjust_pci_device ( pci ); + efab->iobase = pci->ioaddr & ~3; + + /* Determine the NIC variant */ + falcon_probe_nic_variant ( efab, pci ); + + /* Read the SPI interface and determine the MAC address, + * and the board and phy variant. Hook in the op tables */ + rc = falcon_probe_spi ( efab ); + if ( rc ) + goto fail2; + rc = falcon_probe_nvram ( efab ); + if ( rc ) + goto fail3; + + memcpy ( netdev->hw_addr, efab->mac_addr, ETH_ALEN ); + + netdev_link_up ( netdev ); + rc = register_netdev ( netdev ); + if ( rc ) + goto fail4; + + /* Advertise non-volatile storage */ + if ( efab->nvo.nvs ) { + rc = register_nvo ( &efab->nvo, netdev_settings ( netdev ) ); + if ( rc ) + goto fail5; + } + + EFAB_LOG ( "Found %s EtherFabric %s %s revision %d\n", id->name, + efab->is_asic ? "ASIC" : "FPGA", + efab->phy_10g ? "10G" : "1G", + efab->pci_revision ); + + return 0; + +fail5: + unregister_netdev ( netdev ); +fail4: +fail3: +fail2: + iounmap ( efab->membase ); + efab->membase = NULL; + netdev_put ( netdev ); +fail1: + return rc; +} + + +static struct pci_device_id efab_nics[] = { + PCI_ROM(0x1924, 0x0703, "falcon", "EtherFabric Falcon", 0), + PCI_ROM(0x1924, 0x0710, "falconb0", "EtherFabric FalconB0", 0), +}; + +struct pci_driver etherfabric_driver __pci_driver = { + .ids = efab_nics, + .id_count = sizeof ( efab_nics ) / sizeof ( efab_nics[0] ), + .probe = efab_probe, + .remove = efab_remove, +}; + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/etherfabric.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/etherfabric.h new file mode 100644 index 0000000..9657eb7 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/etherfabric.h @@ -0,0 +1,553 @@ +/************************************************************************** + * + * GPL net driver for Level 5 Etherfabric network cards + * + * Written by Michael Brown <mbrown@fensystems.co.uk> + * + * Copyright Fen Systems Ltd. 2005 + * Copyright Level 5 Networks Inc. 2005 + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL), incorporated herein by + * reference. Drivers based on or derived from this code fall under + * the GPL and must retain the authorship, copyright and license + * notice. This file is not a complete program and may only be used + * when the entire operating system is licensed under the GPL. + * + ************************************************************************** + */ + +FILE_LICENCE ( GPL_ANY ); + +#ifndef EFAB_BITFIELD_H +#define EFAB_BITFIELD_H + +/** @file + * + * Etherfabric bitfield access + * + * Etherfabric NICs make extensive use of bitfields up to 128 bits + * wide. Since there is no native 128-bit datatype on most systems, + * and since 64-bit datatypes are inefficient on 32-bit systems and + * vice versa, we wrap accesses in a way that uses the most efficient + * datatype. + * + * The NICs are PCI devices and therefore little-endian. Since most + * of the quantities that we deal with are DMAed to/from host memory, + * we define our datatypes (efab_oword_t, efab_qword_t and + * efab_dword_t) to be little-endian. + * + * In the less common case of using PIO for individual register + * writes, we construct the little-endian datatype in host memory and + * then use non-swapping equivalents of writel/writeq, rather than + * constructing a native-endian datatype and relying on the implicit + * byte-swapping done by writel/writeq. (We use a similar strategy + * for register reads.) + */ + +/** Dummy field low bit number */ +#define EFAB_DUMMY_FIELD_LBN 0 +/** Dummy field width */ +#define EFAB_DUMMY_FIELD_WIDTH 0 +/** Dword 0 low bit number */ +#define EFAB_DWORD_0_LBN 0 +/** Dword 0 width */ +#define EFAB_DWORD_0_WIDTH 32 +/** Dword 1 low bit number */ +#define EFAB_DWORD_1_LBN 32 +/** Dword 1 width */ +#define EFAB_DWORD_1_WIDTH 32 +/** Dword 2 low bit number */ +#define EFAB_DWORD_2_LBN 64 +/** Dword 2 width */ +#define EFAB_DWORD_2_WIDTH 32 +/** Dword 3 low bit number */ +#define EFAB_DWORD_3_LBN 96 +/** Dword 3 width */ +#define EFAB_DWORD_3_WIDTH 32 + +/** Specified attribute (e.g. LBN) of the specified field */ +#define EFAB_VAL(field,attribute) field ## _ ## attribute +/** Low bit number of the specified field */ +#define EFAB_LOW_BIT( field ) EFAB_VAL ( field, LBN ) +/** Bit width of the specified field */ +#define EFAB_WIDTH( field ) EFAB_VAL ( field, WIDTH ) +/** High bit number of the specified field */ +#define EFAB_HIGH_BIT(field) ( EFAB_LOW_BIT(field) + EFAB_WIDTH(field) - 1 ) +/** Mask equal in width to the specified field. + * + * For example, a field with width 5 would have a mask of 0x1f. + * + * The maximum width mask that can be generated is 64 bits. + */ +#define EFAB_MASK64( field ) \ + ( EFAB_WIDTH(field) == 64 ? ~( ( uint64_t ) 0 ) : \ + ( ( ( ( ( uint64_t ) 1 ) << EFAB_WIDTH(field) ) ) - 1 ) ) + +/** Mask equal in width to the specified field. + * + * For example, a field with width 5 would have a mask of 0x1f. + * + * The maximum width mask that can be generated is 32 bits. Use + * EFAB_MASK64 for higher width fields. + */ +#define EFAB_MASK32( field ) \ + ( EFAB_WIDTH(field) == 32 ? ~( ( uint32_t ) 0 ) : \ + ( ( ( ( ( uint32_t ) 1 ) << EFAB_WIDTH(field) ) ) - 1 ) ) + +/** A doubleword (i.e. 4 byte) datatype + * + * This datatype is defined to be little-endian. + */ +typedef union efab_dword { + uint32_t u32[1]; + uint32_t opaque; /* For bitwise operations between two efab_dwords */ +} efab_dword_t; + +/** A quadword (i.e. 8 byte) datatype + * + * This datatype is defined to be little-endian. + */ +typedef union efab_qword { + uint64_t u64[1]; + uint32_t u32[2]; + efab_dword_t dword[2]; +} efab_qword_t; + +/** + * An octword (eight-word, i.e. 16 byte) datatype + * + * This datatype is defined to be little-endian. + */ +typedef union efab_oword { + uint64_t u64[2]; + efab_qword_t qword[2]; + uint32_t u32[4]; + efab_dword_t dword[4]; +} efab_oword_t; + +/** Format string for printing an efab_dword_t */ +#define EFAB_DWORD_FMT "%08x" + +/** Format string for printing an efab_qword_t */ +#define EFAB_QWORD_FMT "%08x:%08x" + +/** Format string for printing an efab_oword_t */ +#define EFAB_OWORD_FMT "%08x:%08x:%08x:%08x" + +/** printk parameters for printing an efab_dword_t */ +#define EFAB_DWORD_VAL(dword) \ + ( ( unsigned int ) le32_to_cpu ( (dword).u32[0] ) ) + +/** printk parameters for printing an efab_qword_t */ +#define EFAB_QWORD_VAL(qword) \ + ( ( unsigned int ) le32_to_cpu ( (qword).u32[1] ) ), \ + ( ( unsigned int ) le32_to_cpu ( (qword).u32[0] ) ) + +/** printk parameters for printing an efab_oword_t */ +#define EFAB_OWORD_VAL(oword) \ + ( ( unsigned int ) le32_to_cpu ( (oword).u32[3] ) ), \ + ( ( unsigned int ) le32_to_cpu ( (oword).u32[2] ) ), \ + ( ( unsigned int ) le32_to_cpu ( (oword).u32[1] ) ), \ + ( ( unsigned int ) le32_to_cpu ( (oword).u32[0] ) ) + +/** + * Extract bit field portion [low,high) from the native-endian element + * which contains bits [min,max). + * + * For example, suppose "element" represents the high 32 bits of a + * 64-bit value, and we wish to extract the bits belonging to the bit + * field occupying bits 28-45 of this 64-bit value. + * + * Then EFAB_EXTRACT ( element, 32, 63, 28, 45 ) would give + * + * ( element ) << 4 + * + * The result will contain the relevant bits filled in in the range + * [0,high-low), with garbage in bits [high-low+1,...). + */ +#define EFAB_EXTRACT_NATIVE( native_element, min ,max ,low ,high ) \ + ( ( ( low > max ) || ( high < min ) ) ? 0 : \ + ( ( low > min ) ? \ + ( (native_element) >> ( low - min ) ) : \ + ( (native_element) << ( min - low ) ) ) ) + +/** + * Extract bit field portion [low,high) from the 64-bit little-endian + * element which contains bits [min,max) + */ +#define EFAB_EXTRACT64( element, min, max, low, high ) \ + EFAB_EXTRACT_NATIVE ( le64_to_cpu(element), min, max, low, high ) + +/** + * Extract bit field portion [low,high) from the 32-bit little-endian + * element which contains bits [min,max) + */ +#define EFAB_EXTRACT32( element, min, max, low, high ) \ + EFAB_EXTRACT_NATIVE ( le32_to_cpu(element), min, max, low, high ) + +#define EFAB_EXTRACT_OWORD64( oword, low, high ) \ + ( EFAB_EXTRACT64 ( (oword).u64[0], 0, 63, low, high ) | \ + EFAB_EXTRACT64 ( (oword).u64[1], 64, 127, low, high ) ) + +#define EFAB_EXTRACT_QWORD64( qword, low, high ) \ + ( EFAB_EXTRACT64 ( (qword).u64[0], 0, 63, low, high ) ) + +#define EFAB_EXTRACT_OWORD32( oword, low, high ) \ + ( EFAB_EXTRACT32 ( (oword).u32[0], 0, 31, low, high ) | \ + EFAB_EXTRACT32 ( (oword).u32[1], 32, 63, low, high ) | \ + EFAB_EXTRACT32 ( (oword).u32[2], 64, 95, low, high ) | \ + EFAB_EXTRACT32 ( (oword).u32[3], 96, 127, low, high ) ) + +#define EFAB_EXTRACT_QWORD32( qword, low, high ) \ + ( EFAB_EXTRACT32 ( (qword).u32[0], 0, 31, low, high ) | \ + EFAB_EXTRACT32 ( (qword).u32[1], 32, 63, low, high ) ) + +#define EFAB_EXTRACT_DWORD( dword, low, high ) \ + ( EFAB_EXTRACT32 ( (dword).u32[0], 0, 31, low, high ) ) + +#define EFAB_OWORD_FIELD64( oword, field ) \ + ( EFAB_EXTRACT_OWORD64 ( oword, EFAB_LOW_BIT ( field ), \ + EFAB_HIGH_BIT ( field ) ) & \ + EFAB_MASK64 ( field ) ) + +#define EFAB_QWORD_FIELD64( qword, field ) \ + ( EFAB_EXTRACT_QWORD64 ( qword, EFAB_LOW_BIT ( field ), \ + EFAB_HIGH_BIT ( field ) ) & \ + EFAB_MASK64 ( field ) ) + +#define EFAB_OWORD_FIELD32( oword, field ) \ + ( EFAB_EXTRACT_OWORD32 ( oword, EFAB_LOW_BIT ( field ), \ + EFAB_HIGH_BIT ( field ) ) & \ + EFAB_MASK32 ( field ) ) + +#define EFAB_QWORD_FIELD32( qword, field ) \ + ( EFAB_EXTRACT_QWORD32 ( qword, EFAB_LOW_BIT ( field ), \ + EFAB_HIGH_BIT ( field ) ) & \ + EFAB_MASK32 ( field ) ) + +#define EFAB_DWORD_FIELD( dword, field ) \ + ( EFAB_EXTRACT_DWORD ( dword, EFAB_LOW_BIT ( field ), \ + EFAB_HIGH_BIT ( field ) ) & \ + EFAB_MASK32 ( field ) ) + +#define EFAB_OWORD_IS_ZERO64( oword ) \ + ( ! ( (oword).u64[0] || (oword).u64[1] ) ) + +#define EFAB_QWORD_IS_ZERO64( qword ) \ + ( ! ( (qword).u64[0] ) ) + +#define EFAB_OWORD_IS_ZERO32( oword ) \ + ( ! ( (oword).u32[0] || (oword).u32[1] || \ + (oword).u32[2] || (oword).u32[3] ) ) + +#define EFAB_QWORD_IS_ZERO32( qword ) \ + ( ! ( (qword).u32[0] || (qword).u32[1] ) ) + +#define EFAB_DWORD_IS_ZERO( dword ) \ + ( ! ( (dword).u32[0] ) ) + +#define EFAB_OWORD_IS_ALL_ONES64( oword ) \ + ( ( (oword).u64[0] & (oword).u64[1] ) == ~( ( uint64_t ) 0 ) ) + +#define EFAB_QWORD_IS_ALL_ONES64( qword ) \ + ( (qword).u64[0] == ~( ( uint64_t ) 0 ) ) + +#define EFAB_OWORD_IS_ALL_ONES32( oword ) \ + ( ( (oword).u32[0] & (oword).u32[1] & \ + (oword).u32[2] & (oword).u32[3] ) == ~( ( uint32_t ) 0 ) ) + +#define EFAB_QWORD_IS_ALL_ONES32( qword ) \ + ( ( (qword).u32[0] & (qword).u32[1] ) == ~( ( uint32_t ) 0 ) ) + +#define EFAB_DWORD_IS_ALL_ONES( dword ) \ + ( (dword).u32[0] == ~( ( uint32_t ) 0 ) ) + +#if ( BITS_PER_LONG == 64 ) +#define EFAB_OWORD_FIELD EFAB_OWORD_FIELD64 +#define EFAB_QWORD_FIELD EFAB_QWORD_FIELD64 +#define EFAB_OWORD_IS_ZERO EFAB_OWORD_IS_ZERO64 +#define EFAB_QWORD_IS_ZERO EFAB_QWORD_IS_ZERO64 +#define EFAB_OWORD_IS_ALL_ONES EFAB_OWORD_IS_ALL_ONES64 +#define EFAB_QWORD_IS_ALL_ONES EFAB_QWORD_IS_ALL_ONES64 +#else +#define EFAB_OWORD_FIELD EFAB_OWORD_FIELD32 +#define EFAB_QWORD_FIELD EFAB_QWORD_FIELD32 +#define EFAB_OWORD_IS_ZERO EFAB_OWORD_IS_ZERO32 +#define EFAB_QWORD_IS_ZERO EFAB_QWORD_IS_ZERO32 +#define EFAB_OWORD_IS_ALL_ONES EFAB_OWORD_IS_ALL_ONES32 +#define EFAB_QWORD_IS_ALL_ONES EFAB_QWORD_IS_ALL_ONES32 +#endif + +/** + * Construct bit field portion + * + * Creates the portion of the bit field [low,high) that lies within + * the range [min,max). + */ +#define EFAB_INSERT_NATIVE64( min, max, low, high, value ) \ + ( ( ( low > max ) || ( high < min ) ) ? 0 : \ + ( ( low > min ) ? \ + ( ( ( uint64_t ) (value) ) << ( low - min ) ) : \ + ( ( ( uint64_t ) (value) ) >> ( min - low ) ) ) ) + +#define EFAB_INSERT_NATIVE32( min, max, low, high, value ) \ + ( ( ( low > max ) || ( high < min ) ) ? 0 : \ + ( ( low > min ) ? \ + ( ( ( uint32_t ) (value) ) << ( low - min ) ) : \ + ( ( ( uint32_t ) (value) ) >> ( min - low ) ) ) ) + +#define EFAB_INSERT_NATIVE( min, max, low, high, value ) \ + ( ( ( ( max - min ) >= 32 ) || \ + ( ( high - low ) >= 32 ) ) \ + ? EFAB_INSERT_NATIVE64 ( min, max, low, high, value ) \ + : EFAB_INSERT_NATIVE32 ( min, max, low, high, value ) ) + +/** + * Construct bit field portion + * + * Creates the portion of the named bit field that lies within the + * range [min,max). + */ +#define EFAB_INSERT_FIELD_NATIVE( min, max, field, value ) \ + EFAB_INSERT_NATIVE ( min, max, EFAB_LOW_BIT ( field ), \ + EFAB_HIGH_BIT ( field ), value ) + +/** + * Construct bit field + * + * Creates the portion of the named bit fields that lie within the + * range [min,max). + */ +#define EFAB_INSERT_FIELDS_NATIVE( min, max, \ + field1, value1, \ + field2, value2, \ + field3, value3, \ + field4, value4, \ + field5, value5, \ + field6, value6, \ + field7, value7, \ + field8, value8, \ + field9, value9, \ + field10, value10 ) \ + ( EFAB_INSERT_FIELD_NATIVE ( min, max, field1, value1 ) | \ + EFAB_INSERT_FIELD_NATIVE ( min, max, field2, value2 ) | \ + EFAB_INSERT_FIELD_NATIVE ( min, max, field3, value3 ) | \ + EFAB_INSERT_FIELD_NATIVE ( min, max, field4, value4 ) | \ + EFAB_INSERT_FIELD_NATIVE ( min, max, field5, value5 ) | \ + EFAB_INSERT_FIELD_NATIVE ( min, max, field6, value6 ) | \ + EFAB_INSERT_FIELD_NATIVE ( min, max, field7, value7 ) | \ + EFAB_INSERT_FIELD_NATIVE ( min, max, field8, value8 ) | \ + EFAB_INSERT_FIELD_NATIVE ( min, max, field9, value9 ) | \ + EFAB_INSERT_FIELD_NATIVE ( min, max, field10, value10 ) ) + +#define EFAB_INSERT_FIELDS64( ... ) \ + cpu_to_le64 ( EFAB_INSERT_FIELDS_NATIVE ( __VA_ARGS__ ) ) + +#define EFAB_INSERT_FIELDS32( ... ) \ + cpu_to_le32 ( EFAB_INSERT_FIELDS_NATIVE ( __VA_ARGS__ ) ) + +#define EFAB_POPULATE_OWORD64( oword, ... ) do { \ + (oword).u64[0] = EFAB_INSERT_FIELDS64 ( 0, 63, __VA_ARGS__ );\ + (oword).u64[1] = EFAB_INSERT_FIELDS64 ( 64, 127, __VA_ARGS__ );\ + } while ( 0 ) + +#define EFAB_POPULATE_QWORD64( qword, ... ) do { \ + (qword).u64[0] = EFAB_INSERT_FIELDS64 ( 0, 63, __VA_ARGS__ );\ + } while ( 0 ) + +#define EFAB_POPULATE_OWORD32( oword, ... ) do { \ + (oword).u32[0] = EFAB_INSERT_FIELDS32 ( 0, 31, __VA_ARGS__ );\ + (oword).u32[1] = EFAB_INSERT_FIELDS32 ( 32, 63, __VA_ARGS__ );\ + (oword).u32[2] = EFAB_INSERT_FIELDS32 ( 64, 95, __VA_ARGS__ );\ + (oword).u32[3] = EFAB_INSERT_FIELDS32 ( 96, 127, __VA_ARGS__ );\ + } while ( 0 ) + +#define EFAB_POPULATE_QWORD32( qword, ... ) do { \ + (qword).u32[0] = EFAB_INSERT_FIELDS32 ( 0, 31, __VA_ARGS__ );\ + (qword).u32[1] = EFAB_INSERT_FIELDS32 ( 32, 63, __VA_ARGS__ );\ + } while ( 0 ) + +#define EFAB_POPULATE_DWORD( dword, ... ) do { \ + (dword).u32[0] = EFAB_INSERT_FIELDS32 ( 0, 31, __VA_ARGS__ );\ + } while ( 0 ) + +#if ( BITS_PER_LONG == 64 ) +#define EFAB_POPULATE_OWORD EFAB_POPULATE_OWORD64 +#define EFAB_POPULATE_QWORD EFAB_POPULATE_QWORD64 +#else +#define EFAB_POPULATE_OWORD EFAB_POPULATE_OWORD32 +#define EFAB_POPULATE_QWORD EFAB_POPULATE_QWORD32 +#endif + +/* Populate an octword field with various numbers of arguments */ +#define EFAB_POPULATE_OWORD_10 EFAB_POPULATE_OWORD +#define EFAB_POPULATE_OWORD_9( oword, ... ) \ + EFAB_POPULATE_OWORD_10 ( oword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_OWORD_8( oword, ... ) \ + EFAB_POPULATE_OWORD_9 ( oword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_OWORD_7( oword, ... ) \ + EFAB_POPULATE_OWORD_8 ( oword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_OWORD_6( oword, ... ) \ + EFAB_POPULATE_OWORD_7 ( oword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_OWORD_5( oword, ... ) \ + EFAB_POPULATE_OWORD_6 ( oword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_OWORD_4( oword, ... ) \ + EFAB_POPULATE_OWORD_5 ( oword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_OWORD_3( oword, ... ) \ + EFAB_POPULATE_OWORD_4 ( oword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_OWORD_2( oword, ... ) \ + EFAB_POPULATE_OWORD_3 ( oword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_OWORD_1( oword, ... ) \ + EFAB_POPULATE_OWORD_2 ( oword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_ZERO_OWORD( oword ) \ + EFAB_POPULATE_OWORD_1 ( oword, EFAB_DUMMY_FIELD, 0 ) +#define EFAB_SET_OWORD( oword ) \ + EFAB_POPULATE_OWORD_4 ( oword, \ + EFAB_DWORD_0, 0xffffffff, \ + EFAB_DWORD_1, 0xffffffff, \ + EFAB_DWORD_2, 0xffffffff, \ + EFAB_DWORD_3, 0xffffffff ) + +/* Populate a quadword field with various numbers of arguments */ +#define EFAB_POPULATE_QWORD_10 EFAB_POPULATE_QWORD +#define EFAB_POPULATE_QWORD_9( qword, ... ) \ + EFAB_POPULATE_QWORD_10 ( qword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_QWORD_8( qword, ... ) \ + EFAB_POPULATE_QWORD_9 ( qword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_QWORD_7( qword, ... ) \ + EFAB_POPULATE_QWORD_8 ( qword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_QWORD_6( qword, ... ) \ + EFAB_POPULATE_QWORD_7 ( qword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_QWORD_5( qword, ... ) \ + EFAB_POPULATE_QWORD_6 ( qword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_QWORD_4( qword, ... ) \ + EFAB_POPULATE_QWORD_5 ( qword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_QWORD_3( qword, ... ) \ + EFAB_POPULATE_QWORD_4 ( qword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_QWORD_2( qword, ... ) \ + EFAB_POPULATE_QWORD_3 ( qword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_QWORD_1( qword, ... ) \ + EFAB_POPULATE_QWORD_2 ( qword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_ZERO_QWORD( qword ) \ + EFAB_POPULATE_QWORD_1 ( qword, EFAB_DUMMY_FIELD, 0 ) +#define EFAB_SET_QWORD( qword ) \ + EFAB_POPULATE_QWORD_2 ( qword, \ + EFAB_DWORD_0, 0xffffffff, \ + EFAB_DWORD_1, 0xffffffff ) + +/* Populate a dword field with various numbers of arguments */ +#define EFAB_POPULATE_DWORD_10 EFAB_POPULATE_DWORD +#define EFAB_POPULATE_DWORD_9( dword, ... ) \ + EFAB_POPULATE_DWORD_10 ( dword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_DWORD_8( dword, ... ) \ + EFAB_POPULATE_DWORD_9 ( dword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_DWORD_7( dword, ... ) \ + EFAB_POPULATE_DWORD_8 ( dword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_DWORD_6( dword, ... ) \ + EFAB_POPULATE_DWORD_7 ( dword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_DWORD_5( dword, ... ) \ + EFAB_POPULATE_DWORD_6 ( dword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_DWORD_4( dword, ... ) \ + EFAB_POPULATE_DWORD_5 ( dword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_DWORD_3( dword, ... ) \ + EFAB_POPULATE_DWORD_4 ( dword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_DWORD_2( dword, ... ) \ + EFAB_POPULATE_DWORD_3 ( dword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_POPULATE_DWORD_1( dword, ... ) \ + EFAB_POPULATE_DWORD_2 ( dword, EFAB_DUMMY_FIELD, 0, __VA_ARGS__ ) +#define EFAB_ZERO_DWORD( dword ) \ + EFAB_POPULATE_DWORD_1 ( dword, EFAB_DUMMY_FIELD, 0 ) +#define EFAB_SET_DWORD( dword ) \ + EFAB_POPULATE_DWORD_1 ( dword, EFAB_DWORD_0, 0xffffffff ) + +/* + * Modify a named field within an already-populated structure. Used + * for read-modify-write operations. + * + */ + +#define EFAB_INSERT_FIELD64( ... ) \ + cpu_to_le64 ( EFAB_INSERT_FIELD_NATIVE ( __VA_ARGS__ ) ) + +#define EFAB_INSERT_FIELD32( ... ) \ + cpu_to_le32 ( EFAB_INSERT_FIELD_NATIVE ( __VA_ARGS__ ) ) + +#define EFAB_INPLACE_MASK64( min, max, field ) \ + EFAB_INSERT_FIELD64 ( min, max, field, EFAB_MASK64 ( field ) ) + +#define EFAB_INPLACE_MASK32( min, max, field ) \ + EFAB_INSERT_FIELD32 ( min, max, field, EFAB_MASK32 ( field ) ) + +#define EFAB_SET_OWORD_FIELD64( oword, field, value ) do { \ + (oword).u64[0] = ( ( (oword).u64[0] \ + & ~EFAB_INPLACE_MASK64 ( 0, 63, field ) ) \ + | EFAB_INSERT_FIELD64 ( 0, 63, field, value ) ); \ + (oword).u64[1] = ( ( (oword).u64[1] \ + & ~EFAB_INPLACE_MASK64 ( 64, 127, field ) ) \ + | EFAB_INSERT_FIELD64 ( 64, 127, field, value ) ); \ + } while ( 0 ) + +#define EFAB_SET_QWORD_FIELD64( qword, field, value ) do { \ + (qword).u64[0] = ( ( (qword).u64[0] \ + & ~EFAB_INPLACE_MASK64 ( 0, 63, field ) ) \ + | EFAB_INSERT_FIELD64 ( 0, 63, field, value ) ); \ + } while ( 0 ) + +#define EFAB_SET_OWORD_FIELD32( oword, field, value ) do { \ + (oword).u32[0] = ( ( (oword).u32[0] \ + & ~EFAB_INPLACE_MASK32 ( 0, 31, field ) ) \ + | EFAB_INSERT_FIELD32 ( 0, 31, field, value ) ); \ + (oword).u32[1] = ( ( (oword).u32[1] \ + & ~EFAB_INPLACE_MASK32 ( 32, 63, field ) ) \ + | EFAB_INSERT_FIELD32 ( 32, 63, field, value ) ); \ + (oword).u32[2] = ( ( (oword).u32[2] \ + & ~EFAB_INPLACE_MASK32 ( 64, 95, field ) ) \ + | EFAB_INSERT_FIELD32 ( 64, 95, field, value ) ); \ + (oword).u32[3] = ( ( (oword).u32[3] \ + & ~EFAB_INPLACE_MASK32 ( 96, 127, field ) ) \ + | EFAB_INSERT_FIELD32 ( 96, 127, field, value ) ); \ + } while ( 0 ) + +#define EFAB_SET_QWORD_FIELD32( qword, field, value ) do { \ + (qword).u32[0] = ( ( (qword).u32[0] \ + & ~EFAB_INPLACE_MASK32 ( 0, 31, field ) ) \ + | EFAB_INSERT_FIELD32 ( 0, 31, field, value ) ); \ + (qword).u32[1] = ( ( (qword).u32[1] \ + & ~EFAB_INPLACE_MASK32 ( 32, 63, field ) ) \ + | EFAB_INSERT_FIELD32 ( 32, 63, field, value ) ); \ + } while ( 0 ) + +#define EFAB_SET_DWORD_FIELD( dword, field, value ) do { \ + (dword).u32[0] = ( ( (dword).u32[0] \ + & ~EFAB_INPLACE_MASK32 ( 0, 31, field ) ) \ + | EFAB_INSERT_FIELD32 ( 0, 31, field, value ) ); \ + } while ( 0 ) + +#if ( BITS_PER_LONG == 64 ) +#define EFAB_SET_OWORD_FIELD EFAB_SET_OWORD_FIELD64 +#define EFAB_SET_QWORD_FIELD EFAB_SET_QWORD_FIELD64 +#else +#define EFAB_SET_OWORD_FIELD EFAB_SET_OWORD_FIELD32 +#define EFAB_SET_QWORD_FIELD EFAB_SET_QWORD_FIELD32 +#endif + +/* Used to avoid compiler warnings about shift range exceeding width + * of the data types when dma_addr_t is only 32 bits wide. + */ +#define DMA_ADDR_T_WIDTH ( 8 * sizeof ( dma_addr_t ) ) +#define EFAB_DMA_TYPE_WIDTH( width ) \ + ( ( (width) < DMA_ADDR_T_WIDTH ) ? (width) : DMA_ADDR_T_WIDTH ) +#define EFAB_DMA_MAX_MASK ( ( DMA_ADDR_T_WIDTH == 64 ) ? \ + ~( ( uint64_t ) 0 ) : ~( ( uint32_t ) 0 ) ) +#define EFAB_DMA_MASK(mask) ( (mask) & EFAB_DMA_MAX_MASK ) + +#endif /* EFAB_BITFIELD_H */ + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/etherfabric_nic.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/etherfabric_nic.h new file mode 100644 index 0000000..fe94d80 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/etherfabric_nic.h @@ -0,0 +1,204 @@ +/************************************************************************** + * + * Etherboot driver for Level 5 Etherfabric network cards + * + * Written by Michael Brown <mbrown@fensystems.co.uk> + * + * Copyright Fen Systems Ltd. 2005 + * Copyright Level 5 Networks Inc. 2005 + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL), incorporated herein by + * reference. Drivers based on or derived from this code fall under + * the GPL and must retain the authorship, copyright and license + * notice. + * + ************************************************************************** + */ + +FILE_LICENCE ( GPL_ANY ); + +#ifndef EFAB_NIC_H +#define EFAB_NIC_H +#include <gpxe/bitbash.h> +#include <gpxe/i2c.h> +#include <gpxe/spi.h> +#include <gpxe/nvo.h> +#include <gpxe/if_ether.h> +/************************************************************************** + * + * Constants and macros + * + ************************************************************************** + */ +/* Board IDs. Early boards have no board_type, (e.g. EF1002 and 401/403) + * But newer boards are getting bigger... + */ +typedef enum { + EFAB_BOARD_INVALID = 0, /* Early boards do not have board rev. info. */ + EFAB_BOARD_SFE4001 = 1, + EFAB_BOARD_SFE4002 = 2, + EFAB_BOARD_SFE4003 = 3, + /* Insert new types before here */ + EFAB_BOARD_MAX +} efab_board_type; + +/* PHY types. */ +typedef enum { + PHY_TYPE_AUTO = 0, /* on development board detect between CX4 & alaska */ + PHY_TYPE_CX4_RTMR = 1, + PHY_TYPE_1GIG_ALASKA = 2, + PHY_TYPE_10XPRESS = 3, + PHY_TYPE_XFP = 4, + PHY_TYPE_CX4 = 5, + PHY_TYPE_PM8358 = 6, +} phy_type_t; + +/************************************************************************** + * + * Hardware data structures and sizing + * + ************************************************************************** + */ + +#define dma_addr_t unsigned long +typedef efab_qword_t falcon_rx_desc_t; +typedef efab_qword_t falcon_tx_desc_t; +typedef efab_qword_t falcon_event_t; + +#define EFAB_BUF_ALIGN 4096 +#define EFAB_RXD_SIZE 512 +#define EFAB_TXD_SIZE 512 +#define EFAB_EVQ_SIZE 512 + +#define EFAB_NUM_RX_DESC 16 +#define EFAB_RX_BUF_SIZE 1600 + +/************************************************************************** + * + * Data structures + * + ************************************************************************** + */ + +struct efab_nic; + +/* A buffer table allocation backing a tx dma, rx dma or eventq */ +struct efab_special_buffer { + dma_addr_t dma_addr; + int id; +}; + +/* A TX queue */ +struct efab_tx_queue { + /* The hardware ring */ + falcon_tx_desc_t *ring; + + /* The software ring storing io_buffers. */ + struct io_buffer *buf[EFAB_TXD_SIZE]; + + /* The buffer table reservation pushed to hardware */ + struct efab_special_buffer entry; + + /* Software descriptor write ptr */ + unsigned int write_ptr; + + /* Hardware descriptor read ptr */ + unsigned int read_ptr; +}; + +/* An RX queue */ +struct efab_rx_queue { + /* The hardware ring */ + falcon_rx_desc_t *ring; + + /* The software ring storing io_buffers */ + struct io_buffer *buf[EFAB_NUM_RX_DESC]; + + /* The buffer table reservation pushed to hardware */ + struct efab_special_buffer entry; + + /* Descriptor write ptr, into both the hardware and software rings */ + unsigned int write_ptr; + + /* Hardware completion ptr */ + unsigned int read_ptr; +}; + +/* An event queue */ +struct efab_ev_queue { + /* The hardware ring to push to hardware. + * Must be the first entry in the structure */ + falcon_event_t *ring; + + /* The buffer table reservation pushed to hardware */ + struct efab_special_buffer entry; + + /* Pointers into the ring */ + unsigned int read_ptr; +}; + +struct efab_mac_operations { + int ( * init ) ( struct efab_nic *efab ); +}; + +struct efab_phy_operations { + int ( * init ) ( struct efab_nic *efab ); + unsigned int mmds; +}; + +struct efab_board_operations { + int ( * init ) ( struct efab_nic *efab ); + void ( * fini ) ( struct efab_nic *efab ); +}; + +struct efab_nic { + struct net_device *netdev; + int pci_revision; + int is_asic; + + /* I2C bit-bashed interface */ + struct i2c_bit_basher i2c_bb; + + /** SPI bus and devices, and the user visible NVO area */ + struct spi_bus spi_bus; + struct spi_device spi_flash; + struct spi_device spi_eeprom; + struct spi_device *spi; + struct nvo_block nvo; + + /** Board, MAC, and PHY operations tables */ + struct efab_board_operations *board_op; + struct efab_mac_operations *mac_op; + struct efab_phy_operations *phy_op; + + /* PHY and board types */ + int phy_addr; + int phy_type; + int phy_10g; + int board_type; + + /** Memory and IO base */ + void *membase; + unsigned int iobase; + + /* Buffer table allocation head */ + int buffer_head; + + /* Queues */ + struct efab_rx_queue rx_queue; + struct efab_tx_queue tx_queue; + struct efab_ev_queue ev_queue; + + /** MAC address */ + uint8_t mac_addr[ETH_ALEN]; + /** GMII link options */ + unsigned int link_options; + /** Link status */ + int link_up; + + /** INT_REG_KER */ + efab_oword_t int_ker __attribute__ (( aligned ( 16 ) )); +}; +#endif /* EFAB_NIC_H */ + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/forcedeth.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/forcedeth.c new file mode 100644 index 0000000..73c44c4 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/forcedeth.c @@ -0,0 +1,1442 @@ +/************************************************************************** +* forcedeth.c -- Etherboot device driver for the NVIDIA nForce +* media access controllers. +* +* Note: This driver is based on the Linux driver that was based on +* a cleanroom reimplementation which was based on reverse +* engineered documentation written by Carl-Daniel Hailfinger +* and Andrew de Quincey. It's neither supported nor endorsed +* by NVIDIA Corp. Use at your own risk. +* +* Written 2004 by Timothy Legge <tlegge@rogers.com> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +* +* Portions of this code based on: +* forcedeth: Ethernet driver for NVIDIA nForce media access controllers: +* +* (C) 2003 Manfred Spraul +* See Linux Driver for full information +* +* Linux Driver Version 0.30, 25 Sep 2004 +* Linux Kernel 2.6.10 +* +* +* REVISION HISTORY: +* ================ +* v1.0 01-31-2004 timlegge Initial port of Linux driver +* v1.1 02-03-2004 timlegge Large Clean up, first release +* v1.2 05-14-2005 timlegge Add Linux 0.22 to .030 features +* +* Indent Options: indent -kr -i8 +***************************************************************************/ + +FILE_LICENCE ( GPL2_OR_LATER ); + +/* to get some global routines like printf */ +#include "etherboot.h" +/* to get the interface to the body of the program */ +#include "nic.h" +/* to get the PCI support functions, if this is a PCI NIC */ +#include <gpxe/pci.h> +/* Include timer support functions */ +#include <gpxe/ethernet.h> +#include "mii.h" + +#define drv_version "v1.2" +#define drv_date "05-14-2005" + +//#define TFTM_DEBUG +#ifdef TFTM_DEBUG +#define dprintf(x) printf x +#else +#define dprintf(x) +#endif + +#define ETH_DATA_LEN 1500 + +/* Condensed operations for readability. */ +#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) +#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) + +static unsigned long BASE; +/* NIC specific static variables go here */ +#define PCI_DEVICE_ID_NVIDIA_NVENET_1 0x01c3 +#define PCI_DEVICE_ID_NVIDIA_NVENET_2 0x0066 +#define PCI_DEVICE_ID_NVIDIA_NVENET_4 0x0086 +#define PCI_DEVICE_ID_NVIDIA_NVENET_5 0x008c +#define PCI_DEVICE_ID_NVIDIA_NVENET_3 0x00d6 +#define PCI_DEVICE_ID_NVIDIA_NVENET_7 0x00df +#define PCI_DEVICE_ID_NVIDIA_NVENET_6 0x00e6 +#define PCI_DEVICE_ID_NVIDIA_NVENET_8 0x0056 +#define PCI_DEVICE_ID_NVIDIA_NVENET_9 0x0057 +#define PCI_DEVICE_ID_NVIDIA_NVENET_10 0x0037 +#define PCI_DEVICE_ID_NVIDIA_NVENET_11 0x0038 +#define PCI_DEVICE_ID_NVIDIA_NVENET_15 0x0373 + + +/* + * Hardware access: + */ + +#define DEV_NEED_LASTPACKET1 0x0001 /* set LASTPACKET1 in tx flags */ +#define DEV_IRQMASK_1 0x0002 /* use NVREG_IRQMASK_WANTED_1 for irq mask */ +#define DEV_IRQMASK_2 0x0004 /* use NVREG_IRQMASK_WANTED_2 for irq mask */ +#define DEV_NEED_TIMERIRQ 0x0008 /* set the timer irq flag in the irq mask */ +#define DEV_NEED_LINKTIMER 0x0010 /* poll link settings. Relies on the timer irq */ + +enum { + NvRegIrqStatus = 0x000, +#define NVREG_IRQSTAT_MIIEVENT 0040 +#define NVREG_IRQSTAT_MASK 0x1ff + NvRegIrqMask = 0x004, +#define NVREG_IRQ_RX_ERROR 0x0001 +#define NVREG_IRQ_RX 0x0002 +#define NVREG_IRQ_RX_NOBUF 0x0004 +#define NVREG_IRQ_TX_ERR 0x0008 +#define NVREG_IRQ_TX2 0x0010 +#define NVREG_IRQ_TIMER 0x0020 +#define NVREG_IRQ_LINK 0x0040 +#define NVREG_IRQ_TX1 0x0100 +#define NVREG_IRQMASK_WANTED_1 0x005f +#define NVREG_IRQMASK_WANTED_2 0x0147 +#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1)) + + NvRegUnknownSetupReg6 = 0x008, +#define NVREG_UNKSETUP6_VAL 3 + +/* + * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic + * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms + */ + NvRegPollingInterval = 0x00c, +#define NVREG_POLL_DEFAULT 970 + NvRegMisc1 = 0x080, +#define NVREG_MISC1_HD 0x02 +#define NVREG_MISC1_FORCE 0x3b0f3c + + NvRegTransmitterControl = 0x084, +#define NVREG_XMITCTL_START 0x01 + NvRegTransmitterStatus = 0x088, +#define NVREG_XMITSTAT_BUSY 0x01 + + NvRegPacketFilterFlags = 0x8c, +#define NVREG_PFF_ALWAYS 0x7F0008 +#define NVREG_PFF_PROMISC 0x80 +#define NVREG_PFF_MYADDR 0x20 + + NvRegOffloadConfig = 0x90, +#define NVREG_OFFLOAD_HOMEPHY 0x601 +#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE + NvRegReceiverControl = 0x094, +#define NVREG_RCVCTL_START 0x01 + NvRegReceiverStatus = 0x98, +#define NVREG_RCVSTAT_BUSY 0x01 + + NvRegRandomSeed = 0x9c, +#define NVREG_RNDSEED_MASK 0x00ff +#define NVREG_RNDSEED_FORCE 0x7f00 +#define NVREG_RNDSEED_FORCE2 0x2d00 +#define NVREG_RNDSEED_FORCE3 0x7400 + + NvRegUnknownSetupReg1 = 0xA0, +#define NVREG_UNKSETUP1_VAL 0x16070f + NvRegUnknownSetupReg2 = 0xA4, +#define NVREG_UNKSETUP2_VAL 0x16 + NvRegMacAddrA = 0xA8, + NvRegMacAddrB = 0xAC, + NvRegMulticastAddrA = 0xB0, +#define NVREG_MCASTADDRA_FORCE 0x01 + NvRegMulticastAddrB = 0xB4, + NvRegMulticastMaskA = 0xB8, + NvRegMulticastMaskB = 0xBC, + + NvRegPhyInterface = 0xC0, +#define PHY_RGMII 0x10000000 + + NvRegTxRingPhysAddr = 0x100, + NvRegRxRingPhysAddr = 0x104, + NvRegRingSizes = 0x108, +#define NVREG_RINGSZ_TXSHIFT 0 +#define NVREG_RINGSZ_RXSHIFT 16 + NvRegUnknownTransmitterReg = 0x10c, + NvRegLinkSpeed = 0x110, +#define NVREG_LINKSPEED_FORCE 0x10000 +#define NVREG_LINKSPEED_10 1000 +#define NVREG_LINKSPEED_100 100 +#define NVREG_LINKSPEED_1000 50 + NvRegUnknownSetupReg5 = 0x130, +#define NVREG_UNKSETUP5_BIT31 (1<<31) + NvRegUnknownSetupReg3 = 0x13c, +#define NVREG_UNKSETUP3_VAL1 0x200010 + NvRegTxRxControl = 0x144, +#define NVREG_TXRXCTL_KICK 0x0001 +#define NVREG_TXRXCTL_BIT1 0x0002 +#define NVREG_TXRXCTL_BIT2 0x0004 +#define NVREG_TXRXCTL_IDLE 0x0008 +#define NVREG_TXRXCTL_RESET 0x0010 +#define NVREG_TXRXCTL_RXCHECK 0x0400 + NvRegMIIStatus = 0x180, +#define NVREG_MIISTAT_ERROR 0x0001 +#define NVREG_MIISTAT_LINKCHANGE 0x0008 +#define NVREG_MIISTAT_MASK 0x000f +#define NVREG_MIISTAT_MASK2 0x000f + NvRegUnknownSetupReg4 = 0x184, +#define NVREG_UNKSETUP4_VAL 8 + + NvRegAdapterControl = 0x188, +#define NVREG_ADAPTCTL_START 0x02 +#define NVREG_ADAPTCTL_LINKUP 0x04 +#define NVREG_ADAPTCTL_PHYVALID 0x40000 +#define NVREG_ADAPTCTL_RUNNING 0x100000 +#define NVREG_ADAPTCTL_PHYSHIFT 24 + NvRegMIISpeed = 0x18c, +#define NVREG_MIISPEED_BIT8 (1<<8) +#define NVREG_MIIDELAY 5 + NvRegMIIControl = 0x190, +#define NVREG_MIICTL_INUSE 0x08000 +#define NVREG_MIICTL_WRITE 0x00400 +#define NVREG_MIICTL_ADDRSHIFT 5 + NvRegMIIData = 0x194, + NvRegWakeUpFlags = 0x200, +#define NVREG_WAKEUPFLAGS_VAL 0x7770 +#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 +#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 +#define NVREG_WAKEUPFLAGS_D3SHIFT 12 +#define NVREG_WAKEUPFLAGS_D2SHIFT 8 +#define NVREG_WAKEUPFLAGS_D1SHIFT 4 +#define NVREG_WAKEUPFLAGS_D0SHIFT 0 +#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 +#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 +#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 +#define NVREG_WAKEUPFLAGS_ENABLE 0x1111 + + NvRegPatternCRC = 0x204, + NvRegPatternMask = 0x208, + NvRegPowerCap = 0x268, +#define NVREG_POWERCAP_D3SUPP (1<<30) +#define NVREG_POWERCAP_D2SUPP (1<<26) +#define NVREG_POWERCAP_D1SUPP (1<<25) + NvRegPowerState = 0x26c, +#define NVREG_POWERSTATE_POWEREDUP 0x8000 +#define NVREG_POWERSTATE_VALID 0x0100 +#define NVREG_POWERSTATE_MASK 0x0003 +#define NVREG_POWERSTATE_D0 0x0000 +#define NVREG_POWERSTATE_D1 0x0001 +#define NVREG_POWERSTATE_D2 0x0002 +#define NVREG_POWERSTATE_D3 0x0003 +}; + +#define FLAG_MASK_V1 0xffff0000 +#define FLAG_MASK_V2 0xffffc000 +#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) +#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) + +#define NV_TX_LASTPACKET (1<<16) +#define NV_TX_RETRYERROR (1<<19) +#define NV_TX_LASTPACKET1 (1<<24) +#define NV_TX_DEFERRED (1<<26) +#define NV_TX_CARRIERLOST (1<<27) +#define NV_TX_LATECOLLISION (1<<28) +#define NV_TX_UNDERFLOW (1<<29) +#define NV_TX_ERROR (1<<30) +#define NV_TX_VALID (1<<31) + +#define NV_TX2_LASTPACKET (1<<29) +#define NV_TX2_RETRYERROR (1<<18) +#define NV_TX2_LASTPACKET1 (1<<23) +#define NV_TX2_DEFERRED (1<<25) +#define NV_TX2_CARRIERLOST (1<<26) +#define NV_TX2_LATECOLLISION (1<<27) +#define NV_TX2_UNDERFLOW (1<<28) +/* error and valid are the same for both */ +#define NV_TX2_ERROR (1<<30) +#define NV_TX2_VALID (1<<31) + +#define NV_RX_DESCRIPTORVALID (1<<16) +#define NV_RX_MISSEDFRAME (1<<17) +#define NV_RX_SUBSTRACT1 (1<<18) +#define NV_RX_ERROR1 (1<<23) +#define NV_RX_ERROR2 (1<<24) +#define NV_RX_ERROR3 (1<<25) +#define NV_RX_ERROR4 (1<<26) +#define NV_RX_CRCERR (1<<27) +#define NV_RX_OVERFLOW (1<<28) +#define NV_RX_FRAMINGERR (1<<29) +#define NV_RX_ERROR (1<<30) +#define NV_RX_AVAIL (1<<31) + +#define NV_RX2_CHECKSUMMASK (0x1C000000) +#define NV_RX2_CHECKSUMOK1 (0x10000000) +#define NV_RX2_CHECKSUMOK2 (0x14000000) +#define NV_RX2_CHECKSUMOK3 (0x18000000) +#define NV_RX2_DESCRIPTORVALID (1<<29) +#define NV_RX2_SUBSTRACT1 (1<<25) +#define NV_RX2_ERROR1 (1<<18) +#define NV_RX2_ERROR2 (1<<19) +#define NV_RX2_ERROR3 (1<<20) +#define NV_RX2_ERROR4 (1<<21) +#define NV_RX2_CRCERR (1<<22) +#define NV_RX2_OVERFLOW (1<<23) +#define NV_RX2_FRAMINGERR (1<<24) +/* error and avail are the same for both */ +#define NV_RX2_ERROR (1<<30) +#define NV_RX2_AVAIL (1<<31) + +/* Miscelaneous hardware related defines: */ +#define NV_PCI_REGSZ 0x270 + +/* various timeout delays: all in usec */ +#define NV_TXRX_RESET_DELAY 4 +#define NV_TXSTOP_DELAY1 10 +#define NV_TXSTOP_DELAY1MAX 500000 +#define NV_TXSTOP_DELAY2 100 +#define NV_RXSTOP_DELAY1 10 +#define NV_RXSTOP_DELAY1MAX 500000 +#define NV_RXSTOP_DELAY2 100 +#define NV_SETUP5_DELAY 5 +#define NV_SETUP5_DELAYMAX 50000 +#define NV_POWERUP_DELAY 5 +#define NV_POWERUP_DELAYMAX 5000 +#define NV_MIIBUSY_DELAY 50 +#define NV_MIIPHY_DELAY 10 +#define NV_MIIPHY_DELAYMAX 10000 + +#define NV_WAKEUPPATTERNS 5 +#define NV_WAKEUPMASKENTRIES 4 + +/* General driver defaults */ +#define NV_WATCHDOG_TIMEO (5*HZ) + +#define RX_RING 4 +#define TX_RING 2 + +/* + * If your nic mysteriously hangs then try to reduce the limits + * to 1/0: It might be required to set NV_TX_LASTPACKET in the + * last valid ring entry. But this would be impossible to + * implement - probably a disassembly error. + */ +#define TX_LIMIT_STOP 63 +#define TX_LIMIT_START 62 + +/* rx/tx mac addr + type + vlan + align + slack*/ +#define RX_NIC_BUFSIZE (ETH_DATA_LEN + 64) +/* even more slack */ +#define RX_ALLOC_BUFSIZE (ETH_DATA_LEN + 128) + +#define OOM_REFILL (1+HZ/20) +#define POLL_WAIT (1+HZ/100) +#define LINK_TIMEOUT (3*HZ) + +/* + * desc_ver values: + * This field has two purposes: + * - Newer nics uses a different ring layout. The layout is selected by + * comparing np->desc_ver with DESC_VER_xy. + * - It contains bits that are forced on when writing to NvRegTxRxControl. + */ +#define DESC_VER_1 0x0 +#define DESC_VER_2 (0x02100|NVREG_TXRXCTL_RXCHECK) + +/* PHY defines */ +#define PHY_OUI_MARVELL 0x5043 +#define PHY_OUI_CICADA 0x03f1 +#define PHYID1_OUI_MASK 0x03ff +#define PHYID1_OUI_SHFT 6 +#define PHYID2_OUI_MASK 0xfc00 +#define PHYID2_OUI_SHFT 10 +#define PHY_INIT1 0x0f000 +#define PHY_INIT2 0x0e00 +#define PHY_INIT3 0x01000 +#define PHY_INIT4 0x0200 +#define PHY_INIT5 0x0004 +#define PHY_INIT6 0x02000 +#define PHY_GIGABIT 0x0100 + +#define PHY_TIMEOUT 0x1 +#define PHY_ERROR 0x2 + +#define PHY_100 0x1 +#define PHY_1000 0x2 +#define PHY_HALF 0x100 + + +/* Bit to know if MAC addr is stored in correct order */ +#define MAC_ADDR_CORRECT 0x01 + +/* Big endian: should work, but is untested */ +struct ring_desc { + u32 PacketBuffer; + u32 FlagLen; +}; + + +/* Define the TX and RX Descriptor and Buffers */ +struct { + struct ring_desc tx_ring[TX_RING]; + unsigned char txb[TX_RING * RX_NIC_BUFSIZE]; + struct ring_desc rx_ring[RX_RING]; + unsigned char rxb[RX_RING * RX_NIC_BUFSIZE]; +} forcedeth_bufs __shared; +#define tx_ring forcedeth_bufs.tx_ring +#define rx_ring forcedeth_bufs.rx_ring +#define txb forcedeth_bufs.txb +#define rxb forcedeth_bufs.rxb + +/* Private Storage for the NIC */ +static struct forcedeth_private { + /* General data: + * Locking: spin_lock(&np->lock); */ + int in_shutdown; + u32 linkspeed; + int duplex; + int phyaddr; + int wolenabled; + unsigned int phy_oui; + u16 gigabit; + + /* General data: RO fields */ + u8 *ring_addr; + u32 orig_mac[2]; + u32 irqmask; + u32 desc_ver; + /* rx specific fields. + * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); + */ + unsigned int cur_rx, refill_rx; + + /* + * tx specific fields. + */ + unsigned int next_tx, nic_tx; + u32 tx_flags; +} npx; + +static struct forcedeth_private *np; + +static inline void pci_push(u8 * base) +{ + /* force out pending posted writes */ + readl(base); +} + +static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v) +{ + return le32_to_cpu(prd->FlagLen) + & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2); +} + +static int reg_delay(int offset, u32 mask, + u32 target, int delay, int delaymax, const char *msg) +{ + u8 *base = (u8 *) BASE; + + pci_push(base); + do { + udelay(delay); + delaymax -= delay; + if (delaymax < 0) { + if (msg) + printf("%s", msg); + return 1; + } + } while ((readl(base + offset) & mask) != target); + return 0; +} + +#define MII_READ (-1) + +/* mii_rw: read/write a register on the PHY. + * + * Caller must guarantee serialization + */ +static int mii_rw(struct nic *nic __unused, int addr, int miireg, + int value) +{ + u8 *base = (u8 *) BASE; + u32 reg; + int retval; + + writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); + + reg = readl(base + NvRegMIIControl); + if (reg & NVREG_MIICTL_INUSE) { + writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); + udelay(NV_MIIBUSY_DELAY); + } + + reg = + (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; + if (value != MII_READ) { + writel(value, base + NvRegMIIData); + reg |= NVREG_MIICTL_WRITE; + } + writel(reg, base + NvRegMIIControl); + + if (reg_delay(NvRegMIIControl, NVREG_MIICTL_INUSE, 0, + NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) { + dprintf(("mii_rw of reg %d at PHY %d timed out.\n", + miireg, addr)); + retval = -1; + } else if (value != MII_READ) { + /* it was a write operation - fewer failures are detectable */ + dprintf(("mii_rw wrote 0x%x to reg %d at PHY %d\n", + value, miireg, addr)); + retval = 0; + } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { + dprintf(("mii_rw of reg %d at PHY %d failed.\n", + miireg, addr)); + retval = -1; + } else { + retval = readl(base + NvRegMIIData); + dprintf(("mii_rw read from reg %d at PHY %d: 0x%x.\n", + miireg, addr, retval)); + } + return retval; +} + +static int phy_reset(struct nic *nic) +{ + + u32 miicontrol; + unsigned int tries = 0; + + miicontrol = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ); + miicontrol |= BMCR_RESET; + if (mii_rw(nic, np->phyaddr, MII_BMCR, miicontrol)) { + return -1; + } + + /* wait for 500ms */ + mdelay(500); + + /* must wait till reset is deasserted */ + while (miicontrol & BMCR_RESET) { + mdelay(10); + miicontrol = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ); + /* FIXME: 100 tries seem excessive */ + if (tries++ > 100) + return -1; + } + return 0; +} + +static int phy_init(struct nic *nic) +{ + u8 *base = (u8 *) BASE; + u32 phyinterface, phy_reserved, mii_status, mii_control, + mii_control_1000, reg; + + /* set advertise register */ + reg = mii_rw(nic, np->phyaddr, MII_ADVERTISE, MII_READ); + reg |= + (ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF | + ADVERTISE_100FULL | 0x800 | 0x400); + if (mii_rw(nic, np->phyaddr, MII_ADVERTISE, reg)) { + printf("phy write to advertise failed.\n"); + return PHY_ERROR; + } + + /* get phy interface type */ + phyinterface = readl(base + NvRegPhyInterface); + + /* see if gigabit phy */ + mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ); + + if (mii_status & PHY_GIGABIT) { + np->gigabit = PHY_GIGABIT; + mii_control_1000 = + mii_rw(nic, np->phyaddr, MII_CTRL1000, MII_READ); + mii_control_1000 &= ~ADVERTISE_1000HALF; + if (phyinterface & PHY_RGMII) + mii_control_1000 |= ADVERTISE_1000FULL; + else + mii_control_1000 &= ~ADVERTISE_1000FULL; + + if (mii_rw + (nic, np->phyaddr, MII_CTRL1000, mii_control_1000)) { + printf("phy init failed.\n"); + return PHY_ERROR; + } + } else + np->gigabit = 0; + + /* reset the phy */ + if (phy_reset(nic)) { + printf("phy reset failed\n"); + return PHY_ERROR; + } + + /* phy vendor specific configuration */ + if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII)) { + phy_reserved = + mii_rw(nic, np->phyaddr, MII_RESV1, MII_READ); + phy_reserved &= ~(PHY_INIT1 | PHY_INIT2); + phy_reserved |= (PHY_INIT3 | PHY_INIT4); + if (mii_rw(nic, np->phyaddr, MII_RESV1, phy_reserved)) { + printf("phy init failed.\n"); + return PHY_ERROR; + } + phy_reserved = + mii_rw(nic, np->phyaddr, MII_NCONFIG, MII_READ); + phy_reserved |= PHY_INIT5; + if (mii_rw(nic, np->phyaddr, MII_NCONFIG, phy_reserved)) { + printf("phy init failed.\n"); + return PHY_ERROR; + } + } + if (np->phy_oui == PHY_OUI_CICADA) { + phy_reserved = + mii_rw(nic, np->phyaddr, MII_SREVISION, MII_READ); + phy_reserved |= PHY_INIT6; + if (mii_rw(nic, np->phyaddr, MII_SREVISION, phy_reserved)) { + printf("phy init failed.\n"); + return PHY_ERROR; + } + } + + /* restart auto negotiation */ + mii_control = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ); + mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); + if (mii_rw(nic, np->phyaddr, MII_BMCR, mii_control)) { + return PHY_ERROR; + } + + return 0; +} + +static void start_rx(struct nic *nic __unused) +{ + u8 *base = (u8 *) BASE; + + dprintf(("start_rx\n")); + /* Already running? Stop it. */ + if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { + writel(0, base + NvRegReceiverControl); + pci_push(base); + } + writel(np->linkspeed, base + NvRegLinkSpeed); + pci_push(base); + writel(NVREG_RCVCTL_START, base + NvRegReceiverControl); + pci_push(base); +} + +static void stop_rx(void) +{ + u8 *base = (u8 *) BASE; + + dprintf(("stop_rx\n")); + writel(0, base + NvRegReceiverControl); + reg_delay(NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, + NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, + "stop_rx: ReceiverStatus remained busy"); + + udelay(NV_RXSTOP_DELAY2); + writel(0, base + NvRegLinkSpeed); +} + +static void start_tx(struct nic *nic __unused) +{ + u8 *base = (u8 *) BASE; + + dprintf(("start_tx\n")); + writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl); + pci_push(base); +} + +static void stop_tx(void) +{ + u8 *base = (u8 *) BASE; + + dprintf(("stop_tx\n")); + writel(0, base + NvRegTransmitterControl); + reg_delay(NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, + NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, + "stop_tx: TransmitterStatus remained busy"); + + udelay(NV_TXSTOP_DELAY2); + writel(0, base + NvRegUnknownTransmitterReg); +} + + +static void txrx_reset(struct nic *nic __unused) +{ + u8 *base = (u8 *) BASE; + + dprintf(("txrx_reset\n")); + writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver, + base + NvRegTxRxControl); + + pci_push(base); + udelay(NV_TXRX_RESET_DELAY); + writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl); + pci_push(base); +} + +/* + * alloc_rx: fill rx ring entries. + * Return 1 if the allocations for the skbs failed and the + * rx engine is without Available descriptors + */ +static int alloc_rx(struct nic *nic __unused) +{ + unsigned int refill_rx = np->refill_rx; + int i; + //while (np->cur_rx != refill_rx) { + for (i = 0; i < RX_RING; i++) { + //int nr = refill_rx % RX_RING; + rx_ring[i].PacketBuffer = + virt_to_le32desc(&rxb[i * RX_NIC_BUFSIZE]); + wmb(); + rx_ring[i].FlagLen = + cpu_to_le32(RX_NIC_BUFSIZE | NV_RX_AVAIL); + /* printf("alloc_rx: Packet %d marked as Available\n", + refill_rx); */ + refill_rx++; + } + np->refill_rx = refill_rx; + if (np->cur_rx - refill_rx == RX_RING) + return 1; + return 0; +} + +static int update_linkspeed(struct nic *nic) +{ + int adv, lpa; + u32 newls; + int newdup = np->duplex; + u32 mii_status; + int retval = 0; + u32 control_1000, status_1000, phyreg; + u8 *base = (u8 *) BASE; + int i; + + /* BMSR_LSTATUS is latched, read it twice: + * we want the current value. + */ + mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ); + mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ); + +#if 1 + //yhlu + for(i=0;i<30;i++) { + mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ); + if((mii_status & BMSR_LSTATUS) && (mii_status & BMSR_ANEGCOMPLETE)) break; + mdelay(100); + } +#endif + + if (!(mii_status & BMSR_LSTATUS)) { + printf + ("no link detected by phy - falling back to 10HD.\n"); + newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10; + newdup = 0; + retval = 0; + goto set_speed; + } + + /* check auto negotiation is complete */ + if (!(mii_status & BMSR_ANEGCOMPLETE)) { + /* still in autonegotiation - configure nic for 10 MBit HD and wait. */ + newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10; + newdup = 0; + retval = 0; + printf("autoneg not completed - falling back to 10HD.\n"); + goto set_speed; + } + + retval = 1; + if (np->gigabit == PHY_GIGABIT) { + control_1000 = + mii_rw(nic, np->phyaddr, MII_CTRL1000, MII_READ); + status_1000 = + mii_rw(nic, np->phyaddr, MII_STAT1000, MII_READ); + + if ((control_1000 & ADVERTISE_1000FULL) && + (status_1000 & LPA_1000FULL)) { + printf + ("update_linkspeed: GBit ethernet detected.\n"); + newls = + NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_1000; + newdup = 1; + goto set_speed; + } + } + + adv = mii_rw(nic, np->phyaddr, MII_ADVERTISE, MII_READ); + lpa = mii_rw(nic, np->phyaddr, MII_LPA, MII_READ); + dprintf(("update_linkspeed: PHY advertises 0x%hX, lpa 0x%hX.\n", + adv, lpa)); + + /* FIXME: handle parallel detection properly, handle gigabit ethernet */ + lpa = lpa & adv; + if (lpa & LPA_100FULL) { + newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_100; + newdup = 1; + } else if (lpa & LPA_100HALF) { + newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_100; + newdup = 0; + } else if (lpa & LPA_10FULL) { + newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10; + newdup = 1; + } else if (lpa & LPA_10HALF) { + newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10; + newdup = 0; + } else { + printf("bad ability %hX - falling back to 10HD.\n", lpa); + newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10; + newdup = 0; + } + + set_speed: + if (np->duplex == newdup && np->linkspeed == newls) + return retval; + + dprintf(("changing link setting from %d/%s to %d/%s.\n", + np->linkspeed, np->duplex ? "Full-Duplex": "Half-Duplex", newls, newdup ? "Full-Duplex": "Half-Duplex")); + + np->duplex = newdup; + np->linkspeed = newls; + + if (np->gigabit == PHY_GIGABIT) { + phyreg = readl(base + NvRegRandomSeed); + phyreg &= ~(0x3FF00); + if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) + phyreg |= NVREG_RNDSEED_FORCE3; + else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) + phyreg |= NVREG_RNDSEED_FORCE2; + else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) + phyreg |= NVREG_RNDSEED_FORCE; + writel(phyreg, base + NvRegRandomSeed); + } + + phyreg = readl(base + NvRegPhyInterface); + phyreg &= ~(PHY_HALF | PHY_100 | PHY_1000); + if (np->duplex == 0) + phyreg |= PHY_HALF; + if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) + phyreg |= PHY_100; + else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) + phyreg |= PHY_1000; + writel(phyreg, base + NvRegPhyInterface); + + writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), + base + NvRegMisc1); + pci_push(base); + writel(np->linkspeed, base + NvRegLinkSpeed); + pci_push(base); + + return retval; +} + +#if 0 /* Not used */ +static void nv_linkchange(struct nic *nic) +{ + if (update_linkspeed(nic)) { +// if (netif_carrier_ok(nic)) { + stop_rx(); +//= } else { + // netif_carrier_on(dev); + // printk(KERN_INFO "%s: link up.\n", dev->name); + // } + start_rx(nic); + } else { + // if (netif_carrier_ok(dev)) { + // netif_carrier_off(dev); + // printk(KERN_INFO "%s: link down.\n", dev->name); + stop_rx(); + // } + } +} +#endif + +static int init_ring(struct nic *nic) +{ + int i; + + np->next_tx = np->nic_tx = 0; + for (i = 0; i < TX_RING; i++) + tx_ring[i].FlagLen = 0; + + np->cur_rx = 0; + np->refill_rx = 0; + for (i = 0; i < RX_RING; i++) + rx_ring[i].FlagLen = 0; + return alloc_rx(nic); +} + +static void set_multicast(struct nic *nic) +{ + + u8 *base = (u8 *) BASE; + u32 addr[2]; + u32 mask[2]; + u32 pff; + u32 alwaysOff[2]; + u32 alwaysOn[2]; + + memset(addr, 0, sizeof(addr)); + memset(mask, 0, sizeof(mask)); + + pff = NVREG_PFF_MYADDR; + + alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0; + + addr[0] = alwaysOn[0]; + addr[1] = alwaysOn[1]; + mask[0] = alwaysOn[0] | alwaysOff[0]; + mask[1] = alwaysOn[1] | alwaysOff[1]; + + addr[0] |= NVREG_MCASTADDRA_FORCE; + pff |= NVREG_PFF_ALWAYS; + stop_rx(); + writel(addr[0], base + NvRegMulticastAddrA); + writel(addr[1], base + NvRegMulticastAddrB); + writel(mask[0], base + NvRegMulticastMaskA); + writel(mask[1], base + NvRegMulticastMaskB); + writel(pff, base + NvRegPacketFilterFlags); + start_rx(nic); +} + +/************************************************************************** +RESET - Reset the NIC to prepare for use +***************************************************************************/ +static int forcedeth_reset(struct nic *nic) +{ + u8 *base = (u8 *) BASE; + int ret, oom, i; + ret = 0; + dprintf(("forcedeth: open\n")); + + /* 1) erase previous misconfiguration */ + /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */ + writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); + writel(0, base + NvRegMulticastAddrB); + writel(0, base + NvRegMulticastMaskA); + writel(0, base + NvRegMulticastMaskB); + writel(0, base + NvRegPacketFilterFlags); + + writel(0, base + NvRegTransmitterControl); + writel(0, base + NvRegReceiverControl); + + writel(0, base + NvRegAdapterControl); + + /* 2) initialize descriptor rings */ + oom = init_ring(nic); + + writel(0, base + NvRegLinkSpeed); + writel(0, base + NvRegUnknownTransmitterReg); + txrx_reset(nic); + writel(0, base + NvRegUnknownSetupReg6); + + np->in_shutdown = 0; + + /* 3) set mac address */ + { + u32 mac[2]; + + mac[0] = + (nic->node_addr[0] << 0) + (nic->node_addr[1] << 8) + + (nic->node_addr[2] << 16) + (nic->node_addr[3] << 24); + mac[1] = + (nic->node_addr[4] << 0) + (nic->node_addr[5] << 8); + + writel(mac[0], base + NvRegMacAddrA); + writel(mac[1], base + NvRegMacAddrB); + } + + /* 4) give hw rings */ + writel((u32) virt_to_le32desc(&rx_ring[0]), + base + NvRegRxRingPhysAddr); + writel((u32) virt_to_le32desc(&tx_ring[0]), + base + NvRegTxRingPhysAddr); + + writel(((RX_RING - 1) << NVREG_RINGSZ_RXSHIFT) + + ((TX_RING - 1) << NVREG_RINGSZ_TXSHIFT), + base + NvRegRingSizes); + + /* 5) continue setup */ + np->linkspeed = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10; + np->duplex = 0; + writel(np->linkspeed, base + NvRegLinkSpeed); + writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3); + writel(np->desc_ver, base + NvRegTxRxControl); + pci_push(base); + writel(NVREG_TXRXCTL_BIT1 | np->desc_ver, base + NvRegTxRxControl); + reg_delay(NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, + NVREG_UNKSETUP5_BIT31, NV_SETUP5_DELAY, + NV_SETUP5_DELAYMAX, + "open: SetupReg5, Bit 31 remained off\n"); + + writel(0, base + NvRegUnknownSetupReg4); +// writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); + writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); +#if 0 + printf("%d-Mbs Link, %s-Duplex\n", + np->linkspeed & NVREG_LINKSPEED_10 ? 10 : 100, + np->duplex ? "Full" : "Half"); +#endif + + /* 6) continue setup */ + writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); + writel(readl(base + NvRegTransmitterStatus), + base + NvRegTransmitterStatus); + writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); + writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig); + + writel(readl(base + NvRegReceiverStatus), + base + NvRegReceiverStatus); + + /* Get a random number */ + i = random(); + writel(NVREG_RNDSEED_FORCE | (i & NVREG_RNDSEED_MASK), + base + NvRegRandomSeed); + writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1); + writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2); + writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval); + writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); + writel((np-> + phyaddr << NVREG_ADAPTCTL_PHYSHIFT) | + NVREG_ADAPTCTL_PHYVALID | NVREG_ADAPTCTL_RUNNING, + base + NvRegAdapterControl); + writel(NVREG_MIISPEED_BIT8 | NVREG_MIIDELAY, base + NvRegMIISpeed); + writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4); + writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags); + + i = readl(base + NvRegPowerState); + if ((i & NVREG_POWERSTATE_POWEREDUP) == 0) + writel(NVREG_POWERSTATE_POWEREDUP | i, + base + NvRegPowerState); + + pci_push(base); + udelay(10); + writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, + base + NvRegPowerState); + + writel(0, base + NvRegIrqMask); + pci_push(base); + writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); + writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); + pci_push(base); +/* + writel(np->irqmask, base + NvRegIrqMask); +*/ + writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); + writel(0, base + NvRegMulticastAddrB); + writel(0, base + NvRegMulticastMaskA); + writel(0, base + NvRegMulticastMaskB); + writel(NVREG_PFF_ALWAYS | NVREG_PFF_MYADDR, + base + NvRegPacketFilterFlags); + + set_multicast(nic); + /* One manual link speed update: Interrupts are enabled, future link + * speed changes cause interrupts and are handled by nv_link_irq(). + */ + { + u32 miistat; + miistat = readl(base + NvRegMIIStatus); + writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); + dprintf(("startup: got 0x%hX.\n", miistat)); + } + ret = update_linkspeed(nic); + + //start_rx(nic); + start_tx(nic); + + if (ret) { + //Start Connection netif_carrier_on(dev); + } else { + printf("no link during initialization.\n"); + } + + return ret; +} + +/* + * extern void hex_dump(const char *data, const unsigned int len); +*/ +/************************************************************************** +POLL - Wait for a frame +***************************************************************************/ +static int forcedeth_poll(struct nic *nic, int retrieve) +{ + /* return true if there's an ethernet packet ready to read */ + /* nic->packet should contain data on return */ + /* nic->packetlen should contain length of data */ + + int len; + int i; + u32 Flags; + + i = np->cur_rx % RX_RING; + + Flags = le32_to_cpu(rx_ring[i].FlagLen); + len = nv_descr_getlength(&rx_ring[i], np->desc_ver); + + if (Flags & NV_RX_AVAIL) + return 0; /* still owned by hardware, */ + + if (np->desc_ver == DESC_VER_1) { + if (!(Flags & NV_RX_DESCRIPTORVALID)) + return 0; + } else { + if (!(Flags & NV_RX2_DESCRIPTORVALID)) + return 0; + } + + if (!retrieve) + return 1; + + /* got a valid packet - forward it to the network core */ + nic->packetlen = len; + memcpy(nic->packet, rxb + (i * RX_NIC_BUFSIZE), nic->packetlen); +/* + * hex_dump(rxb + (i * RX_NIC_BUFSIZE), len); +*/ + wmb(); + np->cur_rx++; + alloc_rx(nic); + return 1; +} + + +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static void forcedeth_transmit(struct nic *nic, const char *d, /* Destination */ + unsigned int t, /* Type */ + unsigned int s, /* size */ + const char *p) +{ /* Packet */ + /* send the packet to destination */ + u8 *ptxb; + u16 nstype; + u8 *base = (u8 *) BASE; + int nr = np->next_tx % TX_RING; + + /* point to the current txb incase multiple tx_rings are used */ + ptxb = txb + (nr * RX_NIC_BUFSIZE); + //np->tx_skbuff[nr] = ptxb; + + /* copy the packet to ring buffer */ + memcpy(ptxb, d, ETH_ALEN); /* dst */ + memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */ + nstype = htons((u16) t); /* type */ + memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2); /* type */ + memcpy(ptxb + ETH_HLEN, p, s); + + s += ETH_HLEN; + while (s < ETH_ZLEN) /* pad to min length */ + ptxb[s++] = '\0'; + + tx_ring[nr].PacketBuffer = (u32) virt_to_le32desc(ptxb); + + wmb(); + tx_ring[nr].FlagLen = cpu_to_le32((s - 1) | np->tx_flags); + + writel(NVREG_TXRXCTL_KICK | np->desc_ver, base + NvRegTxRxControl); + pci_push(base); + np->next_tx++; +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void forcedeth_disable ( struct nic *nic __unused ) { + /* put the card in its initial state */ + /* This function serves 3 purposes. + * This disables DMA and interrupts so we don't receive + * unexpected packets or interrupts from the card after + * etherboot has finished. + * This frees resources so etherboot may use + * this driver on another interface + * This allows etherboot to reinitialize the interface + * if something is something goes wrong. + */ + u8 *base = (u8 *) BASE; + np->in_shutdown = 1; + stop_tx(); + stop_rx(); + + /* disable interrupts on the nic or we will lock up */ + writel(0, base + NvRegIrqMask); + pci_push(base); + dprintf(("Irqmask is zero again\n")); + + /* specia op:o write back the misordered MAC address - otherwise + * the next probe_nic would see a wrong address. + */ + writel(np->orig_mac[0], base + NvRegMacAddrA); + writel(np->orig_mac[1], base + NvRegMacAddrB); +} + +/************************************************************************** +IRQ - Enable, Disable, or Force interrupts +***************************************************************************/ +static void forcedeth_irq(struct nic *nic __unused, + irq_action_t action __unused) +{ + switch (action) { + case DISABLE: + break; + case ENABLE: + break; + case FORCE: + break; + } +} + +static struct nic_operations forcedeth_operations = { + .connect = dummy_connect, + .poll = forcedeth_poll, + .transmit = forcedeth_transmit, + .irq = forcedeth_irq, + +}; + +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +***************************************************************************/ +#define IORESOURCE_MEM 0x00000200 +#define board_found 1 +#define valid_link 0 +static int forcedeth_probe ( struct nic *nic, struct pci_device *pci ) { + + unsigned long addr; + int sz; + u8 *base; + int i; + struct pci_device_id *ids = pci->driver->ids; + int id_count = pci->driver->id_count; + unsigned int flags = 0; + + if (pci->ioaddr == 0) + return 0; + + printf("forcedeth.c: Found %s, vendor=0x%hX, device=0x%hX\n", + pci->driver_name, pci->vendor, pci->device); + + nic->ioaddr = pci->ioaddr; + nic->irqno = 0; + + /* point to private storage */ + np = &npx; + + adjust_pci_device(pci); + + addr = pci_bar_start(pci, PCI_BASE_ADDRESS_0); + sz = pci_bar_size(pci, PCI_BASE_ADDRESS_0); + + /* BASE is used throughout to address the card */ + BASE = (unsigned long) ioremap(addr, sz); + if (!BASE) + return 0; + + /* handle different descriptor versions */ + if (pci->device == PCI_DEVICE_ID_NVIDIA_NVENET_1 || + pci->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 || + pci->device == PCI_DEVICE_ID_NVIDIA_NVENET_3) + np->desc_ver = DESC_VER_1; + else + np->desc_ver = DESC_VER_2; + + //rx_ring[0] = rx_ring; + //tx_ring[0] = tx_ring; + + /* read the mac address */ + base = (u8 *) BASE; + np->orig_mac[0] = readl(base + NvRegMacAddrA); + np->orig_mac[1] = readl(base + NvRegMacAddrB); + + /* lookup the flags from pci_device_id */ + for(i = 0; i < id_count; i++) { + if(pci->vendor == ids[i].vendor && + pci->device == ids[i].device) { + flags = ids[i].driver_data; + break; + } + } + + /* read MAC address */ + if(flags & MAC_ADDR_CORRECT) { + nic->node_addr[0] = (np->orig_mac[0] >> 0) & 0xff; + nic->node_addr[1] = (np->orig_mac[0] >> 8) & 0xff; + nic->node_addr[2] = (np->orig_mac[0] >> 16) & 0xff; + nic->node_addr[3] = (np->orig_mac[0] >> 24) & 0xff; + nic->node_addr[4] = (np->orig_mac[1] >> 0) & 0xff; + nic->node_addr[5] = (np->orig_mac[1] >> 8) & 0xff; + } else { + nic->node_addr[0] = (np->orig_mac[1] >> 8) & 0xff; + nic->node_addr[1] = (np->orig_mac[1] >> 0) & 0xff; + nic->node_addr[2] = (np->orig_mac[0] >> 24) & 0xff; + nic->node_addr[3] = (np->orig_mac[0] >> 16) & 0xff; + nic->node_addr[4] = (np->orig_mac[0] >> 8) & 0xff; + nic->node_addr[5] = (np->orig_mac[0] >> 0) & 0xff; + } +#ifdef LINUX + if (!is_valid_ether_addr(dev->dev_addr)) { + /* + * Bad mac address. At least one bios sets the mac address + * to 01:23:45:67:89:ab + */ + printk(KERN_ERR + "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n", + pci_name(pci_dev), dev->dev_addr[0], + dev->dev_addr[1], dev->dev_addr[2], + dev->dev_addr[3], dev->dev_addr[4], + dev->dev_addr[5]); + printk(KERN_ERR + "Please complain to your hardware vendor. Switching to a random MAC.\n"); + dev->dev_addr[0] = 0x00; + dev->dev_addr[1] = 0x00; + dev->dev_addr[2] = 0x6c; + get_random_bytes(&dev->dev_addr[3], 3); + } +#endif + + DBG ( "%s: MAC Address %s\n", pci->driver_name, eth_ntoa ( nic->node_addr ) ); + + /* disable WOL */ + writel(0, base + NvRegWakeUpFlags); + np->wolenabled = 0; + + if (np->desc_ver == DESC_VER_1) { + np->tx_flags = NV_TX_LASTPACKET | NV_TX_VALID; + } else { + np->tx_flags = NV_TX2_LASTPACKET | NV_TX2_VALID; + } + + switch (pci->device) { + case 0x01C3: // nforce + // DEV_IRQMASK_1|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, + np->irqmask = NVREG_IRQMASK_WANTED_2 | NVREG_IRQ_TIMER; + // np->need_linktimer = 1; + // np->link_timeout = jiffies + LINK_TIMEOUT; + break; + case 0x0066: + /* Fall Through */ + case 0x00D6: + // DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER + np->irqmask = NVREG_IRQMASK_WANTED_2; + np->irqmask |= NVREG_IRQ_TIMER; + // np->need_linktimer = 1; + // np->link_timeout = jiffies + LINK_TIMEOUT; + if (np->desc_ver == DESC_VER_1) + np->tx_flags |= NV_TX_LASTPACKET1; + else + np->tx_flags |= NV_TX2_LASTPACKET1; + break; + case 0x0373: + /* Fall Through */ + case 0x0086: + /* Fall Through */ + case 0x008c: + /* Fall Through */ + case 0x00e6: + /* Fall Through */ + case 0x00df: + /* Fall Through */ + case 0x0056: + /* Fall Through */ + case 0x0057: + /* Fall Through */ + case 0x0037: + /* Fall Through */ + case 0x0038: + //DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ + np->irqmask = NVREG_IRQMASK_WANTED_2; + np->irqmask |= NVREG_IRQ_TIMER; + // np->need_linktimer = 1; + // np->link_timeout = jiffies + LINK_TIMEOUT; + if (np->desc_ver == DESC_VER_1) + np->tx_flags |= NV_TX_LASTPACKET1; + else + np->tx_flags |= NV_TX2_LASTPACKET1; + break; + default: + printf + ("Your card was undefined in this driver. Review driver_data in Linux driver and send a patch\n"); + } + + /* find a suitable phy */ + for (i = 1; i < 32; i++) { + int id1, id2; + id1 = mii_rw(nic, i, MII_PHYSID1, MII_READ); + if (id1 < 0 || id1 == 0xffff) + continue; + id2 = mii_rw(nic, i, MII_PHYSID2, MII_READ); + if (id2 < 0 || id2 == 0xffff) + continue; + id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; + id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; + dprintf + (("%s: open: Found PHY %hX:%hX at address %d.\n", + pci->driver_name, id1, id2, i)); + np->phyaddr = i; + np->phy_oui = id1 | id2; + break; + } + if (i == 32) { + /* PHY in isolate mode? No phy attached and user wants to + * test loopback? Very odd, but can be correct. + */ + printf + ("%s: open: Could not find a valid PHY.\n", pci->driver_name); + } + + if (i != 32) { + /* reset it */ + phy_init(nic); + } + + dprintf(("%s: forcedeth.c: subsystem: %hX:%hX bound to %s\n", + pci->driver_name, pci->vendor, pci->dev_id, pci->driver_name)); + if(!forcedeth_reset(nic)) return 0; // no valid link + + /* point to NIC specific routines */ + nic->nic_op = &forcedeth_operations; + return 1; +} + +static struct pci_device_id forcedeth_nics[] = { +PCI_ROM(0x10de, 0x01C3, "nforce", "nForce NVENET_1 Ethernet Controller", 0), +PCI_ROM(0x10de, 0x0066, "nforce2", "nForce NVENET_2 Ethernet Controller", 0), +PCI_ROM(0x10de, 0x00D6, "nforce3", "nForce NVENET_3 Ethernet Controller", 0), +PCI_ROM(0x10de, 0x0086, "nforce4", "nForce NVENET_4 Ethernet Controller", 0), +PCI_ROM(0x10de, 0x008c, "nforce5", "nForce NVENET_5 Ethernet Controller", 0), +PCI_ROM(0x10de, 0x00e6, "nforce6", "nForce NVENET_6 Ethernet Controller", 0), +PCI_ROM(0x10de, 0x00df, "nforce7", "nForce NVENET_7 Ethernet Controller", 0), +PCI_ROM(0x10de, 0x0056, "nforce8", "nForce NVENET_8 Ethernet Controller", 0), +PCI_ROM(0x10de, 0x0057, "nforce9", "nForce NVENET_9 Ethernet Controller", 0), +PCI_ROM(0x10de, 0x0037, "nforce10", "nForce NVENET_10 Ethernet Controller", 0), +PCI_ROM(0x10de, 0x0038, "nforce11", "nForce NVENET_11 Ethernet Controller", 0), +PCI_ROM(0x10de, 0x0373, "nforce15", "nForce NVENET_15 Ethernet Controller", 0), +PCI_ROM(0x10de, 0x0269, "nforce16", "nForce NVENET_16 Ethernet Controller", 0), +PCI_ROM(0x10de, 0x0760, "nforce17", "nForce NVENET_17 Ethernet Controller", MAC_ADDR_CORRECT), +}; + +PCI_DRIVER ( forcedeth_driver, forcedeth_nics, PCI_NO_CLASS ); + +DRIVER ( "forcedeth", nic_driver, pci_driver, forcedeth_driver, + forcedeth_probe, forcedeth_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ipoib.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ipoib.c new file mode 100644 index 0000000..dde4ee5 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ipoib.c @@ -0,0 +1,718 @@ +/* + * Copyright (C) 2007 Michael Brown <mbrown@fensystems.co.uk>. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <stdint.h> +#include <stdio.h> +#include <unistd.h> +#include <string.h> +#include <byteswap.h> +#include <errno.h> +#include <gpxe/if_arp.h> +#include <gpxe/iobuf.h> +#include <gpxe/netdevice.h> +#include <gpxe/infiniband.h> +#include <gpxe/ib_pathrec.h> +#include <gpxe/ib_mcast.h> +#include <gpxe/ipoib.h> + +/** @file + * + * IP over Infiniband + */ + +/** Number of IPoIB send work queue entries */ +#define IPOIB_NUM_SEND_WQES 2 + +/** Number of IPoIB receive work queue entries */ +#define IPOIB_NUM_RECV_WQES 4 + +/** Number of IPoIB completion entries */ +#define IPOIB_NUM_CQES 8 + +/** An IPoIB device */ +struct ipoib_device { + /** Network device */ + struct net_device *netdev; + /** Underlying Infiniband device */ + struct ib_device *ibdev; + /** Completion queue */ + struct ib_completion_queue *cq; + /** Queue pair */ + struct ib_queue_pair *qp; + /** Broadcast MAC */ + struct ipoib_mac broadcast; + /** Joined to IPv4 broadcast multicast group + * + * This flag indicates whether or not we have initiated the + * join to the IPv4 broadcast multicast group. + */ + int broadcast_joined; + /** IPv4 broadcast multicast group membership */ + struct ib_mc_membership broadcast_membership; +}; + +/** Broadcast IPoIB address */ +static struct ipoib_mac ipoib_broadcast = { + .qpn = htonl ( IB_QPN_BROADCAST ), + .gid.u.bytes = { 0xff, 0x12, 0x40, 0x1b, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff }, +}; + +/**************************************************************************** + * + * IPoIB peer cache + * + **************************************************************************** + */ + +/** + * IPoIB peer address + * + * The IPoIB link-layer header is only four bytes long and so does not + * have sufficient room to store IPoIB MAC address(es). We therefore + * maintain a cache of MAC addresses identified by a single-byte key, + * and abuse the spare two bytes within the link-layer header to + * communicate these MAC addresses between the link-layer code and the + * netdevice driver. + */ +struct ipoib_peer { + /** Key */ + uint8_t key; + /** MAC address */ + struct ipoib_mac mac; +}; + +/** Number of IPoIB peer cache entries + * + * Must be a power of two. + */ +#define IPOIB_NUM_CACHED_PEERS 4 + +/** IPoIB peer address cache */ +static struct ipoib_peer ipoib_peer_cache[IPOIB_NUM_CACHED_PEERS]; + +/** Oldest IPoIB peer cache entry index */ +static unsigned int ipoib_peer_cache_idx = 1; + +/** + * Look up cached peer by key + * + * @v key Peer cache key + * @ret peer Peer cache entry, or NULL + */ +static struct ipoib_peer * ipoib_lookup_peer_by_key ( unsigned int key ) { + struct ipoib_peer *peer; + unsigned int i; + + for ( i = 0 ; i < IPOIB_NUM_CACHED_PEERS ; i++ ) { + peer = &ipoib_peer_cache[i]; + if ( peer->key == key ) + return peer; + } + + if ( key != 0 ) { + DBG ( "IPoIB warning: peer cache lost track of key %x while " + "still in use\n", key ); + } + return NULL; +} + +/** + * Store GID and QPN in peer cache + * + * @v gid Peer GID + * @v qpn Peer QPN + * @ret peer Peer cache entry + */ +static struct ipoib_peer * ipoib_cache_peer ( const struct ipoib_mac *mac ) { + struct ipoib_peer *peer; + unsigned int key; + unsigned int i; + + /* Look for existing cache entry */ + for ( i = 0 ; i < IPOIB_NUM_CACHED_PEERS ; i++ ) { + peer = &ipoib_peer_cache[i]; + if ( memcmp ( &peer->mac, mac, sizeof ( peer->mac ) ) == 0 ) + return peer; + } + + /* No entry found: create a new one */ + key = ipoib_peer_cache_idx++; + peer = &ipoib_peer_cache[ key % IPOIB_NUM_CACHED_PEERS ]; + if ( peer->key ) + DBG ( "IPoIB peer %x evicted from cache\n", peer->key ); + + memset ( peer, 0, sizeof ( *peer ) ); + peer->key = key; + memcpy ( &peer->mac, mac, sizeof ( peer->mac ) ); + DBG ( "IPoIB peer %x has MAC %s\n", + peer->key, ipoib_ntoa ( &peer->mac ) ); + return peer; +} + +/**************************************************************************** + * + * IPoIB link layer + * + **************************************************************************** + */ + +/** + * Add IPoIB link-layer header + * + * @v netdev Network device + * @v iobuf I/O buffer + * @v ll_dest Link-layer destination address + * @v ll_source Source link-layer address + * @v net_proto Network-layer protocol, in network-byte order + * @ret rc Return status code + */ +static int ipoib_push ( struct net_device *netdev __unused, + struct io_buffer *iobuf, const void *ll_dest, + const void *ll_source __unused, uint16_t net_proto ) { + struct ipoib_hdr *ipoib_hdr = + iob_push ( iobuf, sizeof ( *ipoib_hdr ) ); + const struct ipoib_mac *dest_mac = ll_dest; + const struct ipoib_mac *src_mac = ll_source; + struct ipoib_peer *dest; + struct ipoib_peer *src; + + /* Add link-layer addresses to cache */ + dest = ipoib_cache_peer ( dest_mac ); + src = ipoib_cache_peer ( src_mac ); + + /* Build IPoIB header */ + ipoib_hdr->proto = net_proto; + ipoib_hdr->u.peer.dest = dest->key; + ipoib_hdr->u.peer.src = src->key; + + return 0; +} + +/** + * Remove IPoIB link-layer header + * + * @v netdev Network device + * @v iobuf I/O buffer + * @ret ll_dest Link-layer destination address + * @ret ll_source Source link-layer address + * @ret net_proto Network-layer protocol, in network-byte order + * @ret rc Return status code + */ +static int ipoib_pull ( struct net_device *netdev, + struct io_buffer *iobuf, const void **ll_dest, + const void **ll_source, uint16_t *net_proto ) { + struct ipoib_device *ipoib = netdev->priv; + struct ipoib_hdr *ipoib_hdr = iobuf->data; + struct ipoib_peer *dest; + struct ipoib_peer *source; + + /* Sanity check */ + if ( iob_len ( iobuf ) < sizeof ( *ipoib_hdr ) ) { + DBG ( "IPoIB packet too short for link-layer header\n" ); + DBG_HD ( iobuf->data, iob_len ( iobuf ) ); + return -EINVAL; + } + + /* Strip off IPoIB header */ + iob_pull ( iobuf, sizeof ( *ipoib_hdr ) ); + + /* Identify source and destination addresses, and clear + * reserved word in IPoIB header + */ + dest = ipoib_lookup_peer_by_key ( ipoib_hdr->u.peer.dest ); + source = ipoib_lookup_peer_by_key ( ipoib_hdr->u.peer.src ); + ipoib_hdr->u.reserved = 0; + + /* Fill in required fields */ + *ll_dest = ( dest ? &dest->mac : &ipoib->broadcast ); + *ll_source = ( source ? &source->mac : &ipoib->broadcast ); + *net_proto = ipoib_hdr->proto; + + return 0; +} + +/** + * Initialise IPoIB link-layer address + * + * @v hw_addr Hardware address + * @v ll_addr Link-layer address + */ +static void ipoib_init_addr ( const void *hw_addr, void *ll_addr ) { + const struct ib_gid_half *guid = hw_addr; + struct ipoib_mac *mac = ll_addr; + + memset ( mac, 0, sizeof ( *mac ) ); + memcpy ( &mac->gid.u.half[1], guid, sizeof ( mac->gid.u.half[1] ) ); +} + +/** + * Transcribe IPoIB link-layer address + * + * @v ll_addr Link-layer address + * @ret string Link-layer address in human-readable format + */ +const char * ipoib_ntoa ( const void *ll_addr ) { + static char buf[45]; + const struct ipoib_mac *mac = ll_addr; + + snprintf ( buf, sizeof ( buf ), "%08x:%08x:%08x:%08x:%08x", + htonl ( mac->qpn ), htonl ( mac->gid.u.dwords[0] ), + htonl ( mac->gid.u.dwords[1] ), + htonl ( mac->gid.u.dwords[2] ), + htonl ( mac->gid.u.dwords[3] ) ); + return buf; +} + +/** + * Hash multicast address + * + * @v af Address family + * @v net_addr Network-layer address + * @v ll_addr Link-layer address to fill in + * @ret rc Return status code + */ +static int ipoib_mc_hash ( unsigned int af __unused, + const void *net_addr __unused, + void *ll_addr __unused ) { + + return -ENOTSUP; +} + +/** IPoIB protocol */ +struct ll_protocol ipoib_protocol __ll_protocol = { + .name = "IPoIB", + .ll_proto = htons ( ARPHRD_INFINIBAND ), + .hw_addr_len = sizeof ( struct ib_gid_half ), + .ll_addr_len = IPOIB_ALEN, + .ll_header_len = IPOIB_HLEN, + .push = ipoib_push, + .pull = ipoib_pull, + .init_addr = ipoib_init_addr, + .ntoa = ipoib_ntoa, + .mc_hash = ipoib_mc_hash, +}; + +/** + * Allocate IPoIB device + * + * @v priv_size Size of driver private data + * @ret netdev Network device, or NULL + */ +struct net_device * alloc_ipoibdev ( size_t priv_size ) { + struct net_device *netdev; + + netdev = alloc_netdev ( priv_size ); + if ( netdev ) { + netdev->ll_protocol = &ipoib_protocol; + netdev->ll_broadcast = ( uint8_t * ) &ipoib_broadcast; + netdev->max_pkt_len = IB_MAX_PAYLOAD_SIZE; + } + return netdev; +} + +/**************************************************************************** + * + * IPoIB network device + * + **************************************************************************** + */ + +/** + * Transmit packet via IPoIB network device + * + * @v netdev Network device + * @v iobuf I/O buffer + * @ret rc Return status code + */ +static int ipoib_transmit ( struct net_device *netdev, + struct io_buffer *iobuf ) { + struct ipoib_device *ipoib = netdev->priv; + struct ib_device *ibdev = ipoib->ibdev; + struct ipoib_hdr *ipoib_hdr; + struct ipoib_peer *dest; + struct ib_address_vector av; + int rc; + + /* Sanity check */ + if ( iob_len ( iobuf ) < sizeof ( *ipoib_hdr ) ) { + DBGC ( ipoib, "IPoIB %p buffer too short\n", ipoib ); + return -EINVAL; + } + ipoib_hdr = iobuf->data; + + /* Attempting transmission while link is down will put the + * queue pair into an error state, so don't try it. + */ + if ( ! ib_link_ok ( ibdev ) ) + return -ENETUNREACH; + + /* Identify destination address */ + dest = ipoib_lookup_peer_by_key ( ipoib_hdr->u.peer.dest ); + if ( ! dest ) + return -ENXIO; + ipoib_hdr->u.reserved = 0; + + /* Construct address vector */ + memset ( &av, 0, sizeof ( av ) ); + av.qpn = ntohl ( dest->mac.qpn ); + av.gid_present = 1; + memcpy ( &av.gid, &dest->mac.gid, sizeof ( av.gid ) ); + if ( ( rc = ib_resolve_path ( ibdev, &av ) ) != 0 ) { + /* Path not resolved yet */ + return rc; + } + + return ib_post_send ( ibdev, ipoib->qp, &av, iobuf ); +} + +/** + * Handle IPoIB send completion + * + * @v ibdev Infiniband device + * @v qp Queue pair + * @v iobuf I/O buffer + * @v rc Completion status code + */ +static void ipoib_complete_send ( struct ib_device *ibdev __unused, + struct ib_queue_pair *qp, + struct io_buffer *iobuf, int rc ) { + struct ipoib_device *ipoib = ib_qp_get_ownerdata ( qp ); + + netdev_tx_complete_err ( ipoib->netdev, iobuf, rc ); +} + +/** + * Handle IPoIB receive completion + * + * @v ibdev Infiniband device + * @v qp Queue pair + * @v av Address vector, or NULL + * @v iobuf I/O buffer + * @v rc Completion status code + */ +static void ipoib_complete_recv ( struct ib_device *ibdev __unused, + struct ib_queue_pair *qp, + struct ib_address_vector *av, + struct io_buffer *iobuf, int rc ) { + struct ipoib_device *ipoib = ib_qp_get_ownerdata ( qp ); + struct net_device *netdev = ipoib->netdev; + struct ipoib_hdr *ipoib_hdr; + struct ipoib_mac ll_src; + struct ipoib_peer *src; + + if ( rc != 0 ) { + netdev_rx_err ( netdev, iobuf, rc ); + return; + } + + /* Sanity check */ + if ( iob_len ( iobuf ) < sizeof ( struct ipoib_hdr ) ) { + DBGC ( ipoib, "IPoIB %p received packet too short to " + "contain IPoIB header\n", ipoib ); + DBGC_HD ( ipoib, iobuf->data, iob_len ( iobuf ) ); + netdev_rx_err ( netdev, iobuf, -EIO ); + return; + } + ipoib_hdr = iobuf->data; + + /* Parse source address */ + if ( av->gid_present ) { + ll_src.qpn = htonl ( av->qpn ); + memcpy ( &ll_src.gid, &av->gid, sizeof ( ll_src.gid ) ); + src = ipoib_cache_peer ( &ll_src ); + ipoib_hdr->u.peer.src = src->key; + } + + /* Hand off to network layer */ + netdev_rx ( netdev, iobuf ); +} + +/** IPoIB completion operations */ +static struct ib_completion_queue_operations ipoib_cq_op = { + .complete_send = ipoib_complete_send, + .complete_recv = ipoib_complete_recv, +}; + +/** + * Poll IPoIB network device + * + * @v netdev Network device + */ +static void ipoib_poll ( struct net_device *netdev ) { + struct ipoib_device *ipoib = netdev->priv; + struct ib_device *ibdev = ipoib->ibdev; + + ib_poll_eq ( ibdev ); +} + +/** + * Enable/disable interrupts on IPoIB network device + * + * @v netdev Network device + * @v enable Interrupts should be enabled + */ +static void ipoib_irq ( struct net_device *netdev __unused, + int enable __unused ) { + /* No implementation */ +} + +/** + * Handle IPv4 broadcast multicast group join completion + * + * @v ibdev Infiniband device + * @v qp Queue pair + * @v membership Multicast group membership + * @v rc Status code + * @v mad Response MAD (or NULL on error) + */ +void ipoib_join_complete ( struct ib_device *ibdev __unused, + struct ib_queue_pair *qp __unused, + struct ib_mc_membership *membership, int rc, + union ib_mad *mad __unused ) { + struct ipoib_device *ipoib = container_of ( membership, + struct ipoib_device, broadcast_membership ); + + /* Record join status as link status */ + netdev_link_err ( ipoib->netdev, rc ); +} + +/** + * Join IPv4 broadcast multicast group + * + * @v ipoib IPoIB device + * @ret rc Return status code + */ +static int ipoib_join_broadcast_group ( struct ipoib_device *ipoib ) { + int rc; + + if ( ( rc = ib_mcast_join ( ipoib->ibdev, ipoib->qp, + &ipoib->broadcast_membership, + &ipoib->broadcast.gid, + ipoib_join_complete ) ) != 0 ) { + DBGC ( ipoib, "IPoIB %p could not join broadcast group: %s\n", + ipoib, strerror ( rc ) ); + return rc; + } + ipoib->broadcast_joined = 1; + + return 0; +} + +/** + * Leave IPv4 broadcast multicast group + * + * @v ipoib IPoIB device + */ +static void ipoib_leave_broadcast_group ( struct ipoib_device *ipoib ) { + + if ( ipoib->broadcast_joined ) { + ib_mcast_leave ( ipoib->ibdev, ipoib->qp, + &ipoib->broadcast_membership ); + ipoib->broadcast_joined = 0; + } +} + +/** + * Open IPoIB network device + * + * @v netdev Network device + * @ret rc Return status code + */ +static int ipoib_open ( struct net_device *netdev ) { + struct ipoib_device *ipoib = netdev->priv; + struct ib_device *ibdev = ipoib->ibdev; + struct ipoib_mac *mac = ( ( struct ipoib_mac * ) netdev->ll_addr ); + int rc; + + /* Open IB device */ + if ( ( rc = ib_open ( ibdev ) ) != 0 ) { + DBGC ( ipoib, "IPoIB %p could not open device: %s\n", + ipoib, strerror ( rc ) ); + goto err_ib_open; + } + + /* Allocate completion queue */ + ipoib->cq = ib_create_cq ( ibdev, IPOIB_NUM_CQES, &ipoib_cq_op ); + if ( ! ipoib->cq ) { + DBGC ( ipoib, "IPoIB %p could not allocate completion queue\n", + ipoib ); + rc = -ENOMEM; + goto err_create_cq; + } + + /* Allocate queue pair */ + ipoib->qp = ib_create_qp ( ibdev, IB_QPT_UD, + IPOIB_NUM_SEND_WQES, ipoib->cq, + IPOIB_NUM_RECV_WQES, ipoib->cq ); + if ( ! ipoib->qp ) { + DBGC ( ipoib, "IPoIB %p could not allocate queue pair\n", + ipoib ); + rc = -ENOMEM; + goto err_create_qp; + } + ib_qp_set_ownerdata ( ipoib->qp, ipoib ); + + /* Update MAC address with QPN */ + mac->qpn = htonl ( ipoib->qp->qpn ); + + /* Fill receive rings */ + ib_refill_recv ( ibdev, ipoib->qp ); + + /* Fake a link status change to join the broadcast group */ + ipoib_link_state_changed ( ibdev ); + + return 0; + + ib_destroy_qp ( ibdev, ipoib->qp ); + err_create_qp: + ib_destroy_cq ( ibdev, ipoib->cq ); + err_create_cq: + ib_close ( ibdev ); + err_ib_open: + return rc; +} + +/** + * Close IPoIB network device + * + * @v netdev Network device + */ +static void ipoib_close ( struct net_device *netdev ) { + struct ipoib_device *ipoib = netdev->priv; + struct ib_device *ibdev = ipoib->ibdev; + struct ipoib_mac *mac = ( ( struct ipoib_mac * ) netdev->ll_addr ); + + /* Leave broadcast group */ + ipoib_leave_broadcast_group ( ipoib ); + + /* Remove QPN from MAC address */ + mac->qpn = 0; + + /* Tear down the queues */ + ib_destroy_qp ( ibdev, ipoib->qp ); + ib_destroy_cq ( ibdev, ipoib->cq ); + + /* Close IB device */ + ib_close ( ibdev ); +} + +/** IPoIB network device operations */ +static struct net_device_operations ipoib_operations = { + .open = ipoib_open, + .close = ipoib_close, + .transmit = ipoib_transmit, + .poll = ipoib_poll, + .irq = ipoib_irq, +}; + +/** + * Handle link status change + * + * @v ibdev Infiniband device + */ +void ipoib_link_state_changed ( struct ib_device *ibdev ) { + struct net_device *netdev = ib_get_ownerdata ( ibdev ); + struct ipoib_device *ipoib = netdev->priv; + struct ipoib_mac *mac = ( ( struct ipoib_mac * ) netdev->ll_addr ); + int rc; + + /* Leave existing broadcast group */ + ipoib_leave_broadcast_group ( ipoib ); + + /* Update MAC address based on potentially-new GID prefix */ + memcpy ( &mac->gid.u.half[0], &ibdev->gid.u.half[0], + sizeof ( mac->gid.u.half[0] ) ); + + /* Update broadcast GID based on potentially-new partition key */ + ipoib->broadcast.gid.u.words[2] = htons ( ibdev->pkey ); + + /* Set net device link state to reflect Infiniband link state */ + if ( ib_link_ok ( ibdev ) ) { + netdev_link_up ( netdev ); + } else { + netdev_link_down ( netdev ); + } + + /* Join new broadcast group */ + if ( ib_link_ok ( ibdev ) && + ( ( rc = ipoib_join_broadcast_group ( ipoib ) ) != 0 ) ) { + DBGC ( ipoib, "IPoIB %p could not rejoin broadcast group: " + "%s\n", ipoib, strerror ( rc ) ); + return; + } +} + +/** + * Probe IPoIB device + * + * @v ibdev Infiniband device + * @ret rc Return status code + */ +int ipoib_probe ( struct ib_device *ibdev ) { + struct net_device *netdev; + struct ipoib_device *ipoib; + int rc; + + /* Allocate network device */ + netdev = alloc_ipoibdev ( sizeof ( *ipoib ) ); + if ( ! netdev ) + return -ENOMEM; + netdev_init ( netdev, &ipoib_operations ); + ipoib = netdev->priv; + ib_set_ownerdata ( ibdev, netdev ); + netdev->dev = ibdev->dev; + memset ( ipoib, 0, sizeof ( *ipoib ) ); + ipoib->netdev = netdev; + ipoib->ibdev = ibdev; + + /* Extract hardware address */ + memcpy ( netdev->hw_addr, &ibdev->gid.u.half[1], + sizeof ( ibdev->gid.u.half[1] ) ); + + /* Set default broadcast address */ + memcpy ( &ipoib->broadcast, &ipoib_broadcast, + sizeof ( ipoib->broadcast ) ); + netdev->ll_broadcast = ( ( uint8_t * ) &ipoib->broadcast ); + + /* Register network device */ + if ( ( rc = register_netdev ( netdev ) ) != 0 ) + goto err_register_netdev; + + return 0; + + err_register_netdev: + netdev_nullify ( netdev ); + netdev_put ( netdev ); + return rc; +} + +/** + * Remove IPoIB device + * + * @v ibdev Infiniband device + */ +void ipoib_remove ( struct ib_device *ibdev ) { + struct net_device *netdev = ib_get_ownerdata ( ibdev ); + + unregister_netdev ( netdev ); + netdev_nullify ( netdev ); + netdev_put ( netdev ); +} diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/legacy.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/legacy.c new file mode 100644 index 0000000..4a77c27 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/legacy.c @@ -0,0 +1,157 @@ +#include <stdint.h> +#include <stdio.h> +#include <errno.h> +#include <gpxe/if_ether.h> +#include <gpxe/netdevice.h> +#include <gpxe/ethernet.h> +#include <gpxe/iobuf.h> +#include <nic.h> + +/* + * Quick and dirty compatibility layer + * + * This should allow old-API PCI drivers to at least function until + * they are updated. It will not help non-PCI drivers. + * + * No drivers should rely on this code. It will be removed asap. + * + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +struct nic nic; + +static int legacy_registered = 0; + +static int legacy_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) { + struct nic *nic = netdev->priv; + struct ethhdr *ethhdr; + + DBG ( "Transmitting %zd bytes\n", iob_len ( iobuf ) ); + iob_pad ( iobuf, ETH_ZLEN ); + ethhdr = iobuf->data; + iob_pull ( iobuf, sizeof ( *ethhdr ) ); + nic->nic_op->transmit ( nic, ( const char * ) ethhdr->h_dest, + ntohs ( ethhdr->h_protocol ), + iob_len ( iobuf ), iobuf->data ); + netdev_tx_complete ( netdev, iobuf ); + return 0; +} + +static void legacy_poll ( struct net_device *netdev ) { + struct nic *nic = netdev->priv; + struct io_buffer *iobuf; + + iobuf = alloc_iob ( ETH_FRAME_LEN ); + if ( ! iobuf ) + return; + + nic->packet = iobuf->data; + if ( nic->nic_op->poll ( nic, 1 ) ) { + DBG ( "Received %d bytes\n", nic->packetlen ); + iob_put ( iobuf, nic->packetlen ); + netdev_rx ( netdev, iobuf ); + } else { + free_iob ( iobuf ); + } +} + +static int legacy_open ( struct net_device *netdev __unused ) { + /* Nothing to do */ + return 0; +} + +static void legacy_close ( struct net_device *netdev __unused ) { + /* Nothing to do */ +} + +static void legacy_irq ( struct net_device *netdev __unused, int enable ) { + struct nic *nic = netdev->priv; + + nic->nic_op->irq ( nic, ( enable ? ENABLE : DISABLE ) ); +} + +static struct net_device_operations legacy_operations = { + .open = legacy_open, + .close = legacy_close, + .transmit = legacy_transmit, + .poll = legacy_poll, + .irq = legacy_irq, +}; + +int legacy_probe ( void *hwdev, + void ( * set_drvdata ) ( void *hwdev, void *priv ), + struct device *dev, + int ( * probe ) ( struct nic *nic, void *hwdev ), + void ( * disable ) ( struct nic *nic, void *hwdev ) ) { + struct net_device *netdev; + int rc; + + if ( legacy_registered ) + return -EBUSY; + + netdev = alloc_etherdev ( 0 ); + if ( ! netdev ) + return -ENOMEM; + netdev_init ( netdev, &legacy_operations ); + netdev->priv = &nic; + memset ( &nic, 0, sizeof ( nic ) ); + set_drvdata ( hwdev, netdev ); + netdev->dev = dev; + + nic.node_addr = netdev->hw_addr; + // nic.irqno = dev->desc.irq; + + if ( ! probe ( &nic, hwdev ) ) { + rc = -ENODEV; + goto err_probe; + } + + /* Overwrite the IRQ number. Some legacy devices set + * nic->irqno to 0 in the probe routine to indicate that they + * don't support interrupts; doing this allows the timer + * interrupt to be used instead. + */ + // dev->desc.irq = nic.irqno; + + /* Mark as link up; legacy devices don't handle link state */ + netdev_link_up ( netdev ); + + if ( ( rc = register_netdev ( netdev ) ) != 0 ) + goto err_register; + + /* Do not remove this message */ + printf ( "WARNING: Using legacy NIC wrapper on %s\n", + netdev->ll_protocol->ntoa ( nic.node_addr ) ); + + legacy_registered = 1; + return 0; + + err_register: + disable ( &nic, hwdev ); + err_probe: + netdev_nullify ( netdev ); + netdev_put ( netdev ); + return rc; +} + +void legacy_remove ( void *hwdev, + void * ( * get_drvdata ) ( void *hwdev ), + void ( * disable ) ( struct nic *nic, void *hwdev ) ) { + struct net_device *netdev = get_drvdata ( hwdev ); + struct nic *nic = netdev->priv; + + unregister_netdev ( netdev ); + disable ( nic, hwdev ); + netdev_nullify ( netdev ); + netdev_put ( netdev ); + legacy_registered = 0; +} + +int dummy_connect ( struct nic *nic __unused ) { + return 1; +} + +void dummy_irq ( struct nic *nic __unused, irq_action_t irq_action __unused ) { + return; +} diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/mtd80x.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/mtd80x.c new file mode 100644 index 0000000..7cf59b0 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/mtd80x.c @@ -0,0 +1,1022 @@ +/************************************************************************** +* +* mtd80x.c: Etherboot device driver for the mtd80x Ethernet chip. +* Written 2004-2004 by Erdem Güven <zuencap@yahoo.com> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +* +* Portions of this code based on: +* fealnx.c: A Linux device driver for the mtd80x Ethernet chip +* Written 1998-2000 by Donald Becker +* +***************************************************************************/ + +FILE_LICENCE ( GPL2_OR_LATER ); + +/* to get some global routines like printf */ +#include "etherboot.h" +/* to get the interface to the body of the program */ +#include "nic.h" +/* to get the PCI support functions, if this is a PCI NIC */ +#include <gpxe/pci.h> +#include <gpxe/ethernet.h> +#include <mii.h> + +/* Condensed operations for readability. */ +#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) +#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) +#define get_unaligned(ptr) (*(ptr)) + + +/* Operational parameters that are set at compile time. */ + +/* Keep the ring sizes a power of two for compile efficiency. */ +/* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */ +/* Making the Tx ring too large decreases the effectiveness of channel */ +/* bonding and packet priority. */ +/* There are no ill effects from too-large receive rings. */ +#define TX_RING_SIZE 2 +#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */ +#define RX_RING_SIZE 4 + +/* Operational parameters that usually are not changed. */ +/* Time in jiffies before concluding the transmitter is hung. */ +#define HZ 100 +#define TX_TIME_OUT (6*HZ) + +/* Allocation size of Rx buffers with normal sized Ethernet frames. + Do not change this value without good reason. This is not a limit, + but a way to keep a consistent allocation size among drivers. + */ +#define PKT_BUF_SZ 1536 + +/* for different PHY */ +enum phy_type_flags { + MysonPHY = 1, + AhdocPHY = 2, + SeeqPHY = 3, + MarvellPHY = 4, + Myson981 = 5, + LevelOnePHY = 6, + OtherPHY = 10, +}; + +/* A chip capabilities table*/ +enum chip_capability_flags { + HAS_MII_XCVR, + HAS_CHIP_XCVR, +}; + +#if 0 /* not used */ +static +struct chip_info +{ + u16 dev_id; + int flag; +} +mtd80x_chips[] = { + {0x0800, HAS_MII_XCVR}, + {0x0803, HAS_CHIP_XCVR}, + {0x0891, HAS_MII_XCVR} + }; +static int chip_cnt = sizeof( mtd80x_chips ) / sizeof( struct chip_info ); +#endif + +/* Offsets to the Command and Status Registers. */ +enum mtd_offsets { + PAR0 = 0x0, /* physical address 0-3 */ + PAR1 = 0x04, /* physical address 4-5 */ + MAR0 = 0x08, /* multicast address 0-3 */ + MAR1 = 0x0C, /* multicast address 4-7 */ + FAR0 = 0x10, /* flow-control address 0-3 */ + FAR1 = 0x14, /* flow-control address 4-5 */ + TCRRCR = 0x18, /* receive & transmit configuration */ + BCR = 0x1C, /* bus command */ + TXPDR = 0x20, /* transmit polling demand */ + RXPDR = 0x24, /* receive polling demand */ + RXCWP = 0x28, /* receive current word pointer */ + TXLBA = 0x2C, /* transmit list base address */ + RXLBA = 0x30, /* receive list base address */ + ISR = 0x34, /* interrupt status */ + IMR = 0x38, /* interrupt mask */ + FTH = 0x3C, /* flow control high/low threshold */ + MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */ + TALLY = 0x44, /* tally counters for crc and mpa */ + TSR = 0x48, /* tally counter for transmit status */ + BMCRSR = 0x4c, /* basic mode control and status */ + PHYIDENTIFIER = 0x50, /* phy identifier */ + ANARANLPAR = 0x54, /* auto-negotiation advertisement and link + partner ability */ + ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */ + BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */ +}; + +/* Bits in the interrupt status/enable registers. */ +/* The bits in the Intr Status/Enable registers, mostly interrupt sources. */ +enum intr_status_bits { + RFCON = 0x00020000, /* receive flow control xon packet */ + RFCOFF = 0x00010000, /* receive flow control xoff packet */ + LSCStatus = 0x00008000, /* link status change */ + ANCStatus = 0x00004000, /* autonegotiation completed */ + FBE = 0x00002000, /* fatal bus error */ + FBEMask = 0x00001800, /* mask bit12-11 */ + ParityErr = 0x00000000, /* parity error */ + TargetErr = 0x00001000, /* target abort */ + MasterErr = 0x00000800, /* master error */ + TUNF = 0x00000400, /* transmit underflow */ + ROVF = 0x00000200, /* receive overflow */ + ETI = 0x00000100, /* transmit early int */ + ERI = 0x00000080, /* receive early int */ + CNTOVF = 0x00000040, /* counter overflow */ + RBU = 0x00000020, /* receive buffer unavailable */ + TBU = 0x00000010, /* transmit buffer unavilable */ + TI = 0x00000008, /* transmit interrupt */ + RI = 0x00000004, /* receive interrupt */ + RxErr = 0x00000002, /* receive error */ +}; + +/* Bits in the NetworkConfig register. */ +enum rx_mode_bits { + RxModeMask = 0xe0, + AcceptAllPhys = 0x80, /* promiscuous mode */ + AcceptBroadcast = 0x40, /* accept broadcast */ + AcceptMulticast = 0x20, /* accept mutlicast */ + AcceptRunt = 0x08, /* receive runt pkt */ + ALP = 0x04, /* receive long pkt */ + AcceptErr = 0x02, /* receive error pkt */ + + AcceptMyPhys = 0x00000000, + RxEnable = 0x00000001, + RxFlowCtrl = 0x00002000, + TxEnable = 0x00040000, + TxModeFDX = 0x00100000, + TxThreshold = 0x00e00000, + + PS1000 = 0x00010000, + PS10 = 0x00080000, + FD = 0x00100000, +}; + +/* Bits in network_desc.status */ +enum rx_desc_status_bits { + RXOWN = 0x80000000, /* own bit */ + FLNGMASK = 0x0fff0000, /* frame length */ + FLNGShift = 16, + MARSTATUS = 0x00004000, /* multicast address received */ + BARSTATUS = 0x00002000, /* broadcast address received */ + PHYSTATUS = 0x00001000, /* physical address received */ + RXFSD = 0x00000800, /* first descriptor */ + RXLSD = 0x00000400, /* last descriptor */ + ErrorSummary = 0x80, /* error summary */ + RUNT = 0x40, /* runt packet received */ + LONG = 0x20, /* long packet received */ + FAE = 0x10, /* frame align error */ + CRC = 0x08, /* crc error */ + RXER = 0x04, /* receive error */ +}; + +enum rx_desc_control_bits { + RXIC = 0x00800000, /* interrupt control */ + RBSShift = 0, +}; + +enum tx_desc_status_bits { + TXOWN = 0x80000000, /* own bit */ + JABTO = 0x00004000, /* jabber timeout */ + CSL = 0x00002000, /* carrier sense lost */ + LC = 0x00001000, /* late collision */ + EC = 0x00000800, /* excessive collision */ + UDF = 0x00000400, /* fifo underflow */ + DFR = 0x00000200, /* deferred */ + HF = 0x00000100, /* heartbeat fail */ + NCRMask = 0x000000ff, /* collision retry count */ + NCRShift = 0, +}; + +enum tx_desc_control_bits { + TXIC = 0x80000000, /* interrupt control */ + ETIControl = 0x40000000, /* early transmit interrupt */ + TXLD = 0x20000000, /* last descriptor */ + TXFD = 0x10000000, /* first descriptor */ + CRCEnable = 0x08000000, /* crc control */ + PADEnable = 0x04000000, /* padding control */ + RetryTxLC = 0x02000000, /* retry late collision */ + PKTSMask = 0x3ff800, /* packet size bit21-11 */ + PKTSShift = 11, + TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */ + TBSShift = 0, +}; + +/* BootROM/EEPROM/MII Management Register */ +#define MASK_MIIR_MII_READ 0x00000000 +#define MASK_MIIR_MII_WRITE 0x00000008 +#define MASK_MIIR_MII_MDO 0x00000004 +#define MASK_MIIR_MII_MDI 0x00000002 +#define MASK_MIIR_MII_MDC 0x00000001 + +/* ST+OP+PHYAD+REGAD+TA */ +#define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */ +#define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */ + +/* ------------------------------------------------------------------------- */ +/* Constants for Myson PHY */ +/* ------------------------------------------------------------------------- */ +#define MysonPHYID 0xd0000302 +/* 89-7-27 add, (begin) */ +#define MysonPHYID0 0x0302 +#define StatusRegister 18 +#define SPEED100 0x0400 // bit10 +#define FULLMODE 0x0800 // bit11 +/* 89-7-27 add, (end) */ + +/* ------------------------------------------------------------------------- */ +/* Constants for Seeq 80225 PHY */ +/* ------------------------------------------------------------------------- */ +#define SeeqPHYID0 0x0016 + +#define MIIRegister18 18 +#define SPD_DET_100 0x80 +#define DPLX_DET_FULL 0x40 + +/* ------------------------------------------------------------------------- */ +/* Constants for Ahdoc 101 PHY */ +/* ------------------------------------------------------------------------- */ +#define AhdocPHYID0 0x0022 + +#define DiagnosticReg 18 +#define DPLX_FULL 0x0800 +#define Speed_100 0x0400 + +/* 89/6/13 add, */ +/* -------------------------------------------------------------------------- */ +/* Constants */ +/* -------------------------------------------------------------------------- */ +#define MarvellPHYID0 0x0141 +#define LevelOnePHYID0 0x0013 + +#define MII1000BaseTControlReg 9 +#define MII1000BaseTStatusReg 10 +#define SpecificReg 17 + +/* for 1000BaseT Control Register */ +#define PHYAbletoPerform1000FullDuplex 0x0200 +#define PHYAbletoPerform1000HalfDuplex 0x0100 +#define PHY1000AbilityMask 0x300 + +// for phy specific status register, marvell phy. +#define SpeedMask 0x0c000 +#define Speed_1000M 0x08000 +#define Speed_100M 0x4000 +#define Speed_10M 0 +#define Full_Duplex 0x2000 + +// 89/12/29 add, for phy specific status register, levelone phy, (begin) +#define LXT1000_100M 0x08000 +#define LXT1000_1000M 0x0c000 +#define LXT1000_Full 0x200 +// 89/12/29 add, for phy specific status register, levelone phy, (end) + +#if 0 +/* for 3-in-1 case */ +#define PS10 0x00080000 +#define FD 0x00100000 +#define PS1000 0x00010000 +#endif + +/* for PHY */ +#define LinkIsUp 0x0004 +#define LinkIsUp2 0x00040000 + +/* Create a static buffer of size PKT_BUF_SZ for each +RX and TX Descriptor. All descriptors point to a +part of this buffer */ +struct { + u8 txb[PKT_BUF_SZ * TX_RING_SIZE] __attribute__ ((aligned(8))); + u8 rxb[PKT_BUF_SZ * RX_RING_SIZE] __attribute__ ((aligned(8))); +} mtd80x_bufs __shared; +#define txb mtd80x_bufs.txb +#define rxb mtd80x_bufs.rxb + +/* The Tulip Rx and Tx buffer descriptors. */ +struct mtd_desc +{ + s32 status; + s32 control; + u32 buffer; + u32 next_desc; + struct mtd_desc *next_desc_logical; + u8* skbuff; + u32 reserved1; + u32 reserved2; +}; + +struct mtd_private +{ + struct mtd_desc rx_ring[RX_RING_SIZE]; + struct mtd_desc tx_ring[TX_RING_SIZE]; + + /* Frequently used values: keep some adjacent for cache effect. */ + int flags; + struct pci_dev *pci_dev; + unsigned long crvalue; + unsigned long bcrvalue; + /*unsigned long imrvalue;*/ + struct mtd_desc *cur_rx; + struct mtd_desc *lack_rxbuf; + int really_rx_count; + struct mtd_desc *cur_tx; + struct mtd_desc *cur_tx_copy; + int really_tx_count; + int free_tx_count; + unsigned int rx_buf_sz; /* Based on MTU+slack. */ + + /* These values are keep track of the transceiver/media in use. */ + unsigned int linkok; + unsigned int line_speed; + unsigned int duplexmode; + unsigned int default_port: + 4; /* Last dev->if_port value. */ + unsigned int PHYType; + + /* MII transceiver section. */ + int mii_cnt; /* MII device addresses. */ + unsigned char phys[1]; /* MII device addresses. */ + + /*other*/ + const char *nic_name; + int ioaddr; + u16 dev_id; +}; + +static struct mtd_private mtdx; + +static int mdio_read(struct nic * , int phy_id, int location); +static void getlinktype(struct nic * ); +static void getlinkstatus(struct nic * ); +static void set_rx_mode(struct nic *); + +/************************************************************************** + * init_ring - setup the tx and rx descriptors + *************************************************************************/ +static void init_ring(struct nic *nic __unused) +{ + int i; + + mtdx.cur_rx = &mtdx.rx_ring[0]; + + mtdx.rx_buf_sz = PKT_BUF_SZ; + /*mtdx.rx_head_desc = &mtdx.rx_ring[0];*/ + + /* Initialize all Rx descriptors. */ + /* Fill in the Rx buffers. Handle allocation failure gracefully. */ + for (i = 0; i < RX_RING_SIZE; i++) + { + mtdx.rx_ring[i].status = RXOWN; + mtdx.rx_ring[i].control = mtdx.rx_buf_sz << RBSShift; + mtdx.rx_ring[i].next_desc = virt_to_le32desc(&mtdx.rx_ring[i+1]); + mtdx.rx_ring[i].next_desc_logical = &mtdx.rx_ring[i+1]; + mtdx.rx_ring[i].buffer = virt_to_le32desc(&rxb[i * PKT_BUF_SZ]); + mtdx.rx_ring[i].skbuff = &rxb[i * PKT_BUF_SZ]; + } + /* Mark the last entry as wrapping the ring. */ + mtdx.rx_ring[i-1].next_desc = virt_to_le32desc(&mtdx.rx_ring[0]); + mtdx.rx_ring[i-1].next_desc_logical = &mtdx.rx_ring[0]; + + /* We only use one transmit buffer, but two + * descriptors so transmit engines have somewhere + * to point should they feel the need */ + mtdx.tx_ring[0].status = 0x00000000; + mtdx.tx_ring[0].buffer = virt_to_bus(&txb[0]); + mtdx.tx_ring[0].next_desc = virt_to_le32desc(&mtdx.tx_ring[1]); + + /* This descriptor is never used */ + mtdx.tx_ring[1].status = 0x00000000; + mtdx.tx_ring[1].buffer = 0; /*virt_to_bus(&txb[1]); */ + mtdx.tx_ring[1].next_desc = virt_to_le32desc(&mtdx.tx_ring[0]); + + return; +} + +/************************************************************************** +RESET - Reset Adapter +***************************************************************************/ +static void mtd_reset( struct nic *nic ) +{ + /* Reset the chip to erase previous misconfiguration. */ + outl(0x00000001, mtdx.ioaddr + BCR); + + init_ring(nic); + + outl(virt_to_bus(mtdx.rx_ring), mtdx.ioaddr + RXLBA); + outl(virt_to_bus(mtdx.tx_ring), mtdx.ioaddr + TXLBA); + + /* Initialize other registers. */ + /* Configure the PCI bus bursts and FIFO thresholds. */ + mtdx.bcrvalue = 0x10; /* little-endian, 8 burst length */ + mtdx.crvalue = 0xa00; /* rx 128 burst length */ + + if ( mtdx.dev_id == 0x891 ) { + mtdx.bcrvalue |= 0x200; /* set PROG bit */ + mtdx.crvalue |= 0x02000000; /* set enhanced bit */ + } + + outl( mtdx.bcrvalue, mtdx.ioaddr + BCR); + + /* Restart Rx engine if stopped. */ + outl(0, mtdx.ioaddr + RXPDR); + + getlinkstatus(nic); + if (mtdx.linkok) + { + static const char* texts[]={"half","full","10","100","1000"}; + getlinktype(nic); + DBG ( "Link is OK : %s %s\n", texts[mtdx.duplexmode-1], texts[mtdx.line_speed+1] ); + } else + { + DBG ( "No link!!!\n" ); + } + + mtdx.crvalue |= /*TxEnable |*/ RxEnable | TxThreshold; + set_rx_mode(nic); + + /* Clear interrupts by setting the interrupt mask. */ + outl(FBE | TUNF | CNTOVF | RBU | TI | RI, mtdx.ioaddr + ISR); + outl( 0, mtdx.ioaddr + IMR); +} + +/************************************************************************** +POLL - Wait for a frame +***************************************************************************/ +static int mtd_poll(struct nic *nic, __unused int retrieve) +{ + s32 rx_status = mtdx.cur_rx->status; + int retval = 0; + + if( ( rx_status & RXOWN ) != 0 ) + { + return 0; + } + + if (rx_status & ErrorSummary) + { /* there was a fatal error */ + printf( "%s: Receive error, Rx status %8.8x, Error(s) %s%s%s\n", + mtdx.nic_name, (unsigned int) rx_status, + (rx_status & (LONG | RUNT)) ? "length_error ":"", + (rx_status & RXER) ? "frame_error ":"", + (rx_status & CRC) ? "crc_error ":"" ); + retval = 0; + } else if( !((rx_status & RXFSD) && (rx_status & RXLSD)) ) + { + /* this pkt is too long, over one rx buffer */ + printf("Pkt is too long, over one rx buffer.\n"); + retval = 0; + } else + { /* this received pkt is ok */ + /* Omit the four octet CRC from the length. */ + short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4; + + DBG ( " netdev_rx() normal Rx pkt length %d" + " status %x.\n", pkt_len, (unsigned int) rx_status ); + + nic->packetlen = pkt_len; + memcpy(nic->packet, mtdx.cur_rx->skbuff, pkt_len); + + retval = 1; + } + + while( ( mtdx.cur_rx->status & RXOWN ) == 0 ) + { + mtdx.cur_rx->status = RXOWN; + mtdx.cur_rx = mtdx.cur_rx->next_desc_logical; + } + + /* Restart Rx engine if stopped. */ + outl(0, mtdx.ioaddr + RXPDR); + + return retval; +} + +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static void mtd_transmit( + struct nic *nic, + const char *dest, /* Destination */ + unsigned int type, /* Type */ + unsigned int size, /* size */ + const char *data) /* Packet */ +{ + u32 to; + u32 tx_status; + unsigned int nstype = htons ( type ); + + memcpy( txb, dest, ETH_ALEN ); + memcpy( txb + ETH_ALEN, nic->node_addr, ETH_ALEN ); + memcpy( txb + 2 * ETH_ALEN, &nstype, 2 ); + memcpy( txb + ETH_HLEN, data, size ); + + size += ETH_HLEN; + size &= 0x0FFF; + while( size < ETH_ZLEN ) + { + txb[size++] = '\0'; + } + + mtdx.tx_ring[0].control = TXLD | TXFD | CRCEnable | PADEnable; + mtdx.tx_ring[0].control |= (size << PKTSShift); /* pkt size */ + mtdx.tx_ring[0].control |= (size << TBSShift); /* buffer size */ + mtdx.tx_ring[0].status = TXOWN; + + /* Point to transmit descriptor */ + outl(virt_to_bus(mtdx.tx_ring), mtdx.ioaddr + TXLBA); + /* Enable Tx */ + outl( mtdx.crvalue | TxEnable, mtdx.ioaddr + TCRRCR); + /* Wake the potentially-idle transmit channel. */ + outl(0, mtdx.ioaddr + TXPDR); + + to = currticks() + TX_TIME_OUT; + while(( mtdx.tx_ring[0].status & TXOWN) && (currticks() < to)); + + /* Disable Tx */ + outl( mtdx.crvalue & (~TxEnable), mtdx.ioaddr + TCRRCR); + + tx_status = mtdx.tx_ring[0].status; + if (currticks() >= to){ + DBG ( "TX Time Out" ); + } else if( tx_status & (CSL | LC | EC | UDF | HF)){ + printf( "Transmit error: %8.8x %s %s %s %s %s\n", + (unsigned int) tx_status, + tx_status & EC ? "abort" : "", + tx_status & CSL ? "carrier" : "", + tx_status & LC ? "late" : "", + tx_status & UDF ? "fifo" : "", + tx_status & HF ? "heartbeat" : "" ); + } + + /*hex_dump( txb, size );*/ + /*pause();*/ + + DBG ( "TRANSMIT\n" ); +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void mtd_disable ( struct nic *nic ) { + + /* Disable Tx Rx*/ + outl( mtdx.crvalue & (~TxEnable) & (~RxEnable), mtdx.ioaddr + TCRRCR ); + + /* Reset the chip to erase previous misconfiguration. */ + mtd_reset(nic); + + DBG ( "DISABLE\n" ); +} + +static struct nic_operations mtd_operations = { + .connect = dummy_connect, + .poll = mtd_poll, + .transmit = mtd_transmit, + .irq = dummy_irq, + +}; + +static struct pci_device_id mtd80x_nics[] = { + PCI_ROM(0x1516, 0x0800, "MTD800", "Myson MTD800", 0), + PCI_ROM(0x1516, 0x0803, "MTD803", "Surecom EP-320X", 0), + PCI_ROM(0x1516, 0x0891, "MTD891", "Myson MTD891", 0), +}; + +PCI_DRIVER ( mtd80x_driver, mtd80x_nics, PCI_NO_CLASS ); + +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +***************************************************************************/ + +static int mtd_probe ( struct nic *nic, struct pci_device *pci ) { + + int i; + + if (pci->ioaddr == 0) + return 0; + + adjust_pci_device(pci); + + nic->ioaddr = pci->ioaddr; + nic->irqno = 0; + + mtdx.nic_name = pci->driver_name; + mtdx.dev_id = pci->device; + mtdx.ioaddr = nic->ioaddr; + + /* read ethernet id */ + for (i = 0; i < 6; ++i) + { + nic->node_addr[i] = inb(mtdx.ioaddr + PAR0 + i); + } + + if (memcmp(nic->node_addr, "\0\0\0\0\0\0", 6) == 0) + { + return 0; + } + + DBG ( "%s: ioaddr %4.4x MAC %s\n", mtdx.nic_name, mtdx.ioaddr, eth_ntoa ( nic->node_addr ) ); + + /* Reset the chip to erase previous misconfiguration. */ + outl(0x00000001, mtdx.ioaddr + BCR); + + /* find the connected MII xcvrs */ + + if( mtdx.dev_id != 0x803 ) + { + int phy, phy_idx = 0; + + for (phy = 1; phy < 32 && phy_idx < 1; phy++) { + int mii_status = mdio_read(nic, phy, 1); + + if (mii_status != 0xffff && mii_status != 0x0000) { + mtdx.phys[phy_idx] = phy; + + DBG ( "%s: MII PHY found at address %d, status " + "0x%4.4x.\n", mtdx.nic_name, phy, mii_status ); + /* get phy type */ + { + unsigned int data; + + data = mdio_read(nic, mtdx.phys[phy_idx], 2); + if (data == SeeqPHYID0) + mtdx.PHYType = SeeqPHY; + else if (data == AhdocPHYID0) + mtdx.PHYType = AhdocPHY; + else if (data == MarvellPHYID0) + mtdx.PHYType = MarvellPHY; + else if (data == MysonPHYID0) + mtdx.PHYType = Myson981; + else if (data == LevelOnePHYID0) + mtdx.PHYType = LevelOnePHY; + else + mtdx.PHYType = OtherPHY; + } + phy_idx++; + } + } + + mtdx.mii_cnt = phy_idx; + if (phy_idx == 0) { + printf("%s: MII PHY not found -- this device may " + "not operate correctly.\n", mtdx.nic_name); + } + } else { + mtdx.phys[0] = 32; + /* get phy type */ + if (inl(mtdx.ioaddr + PHYIDENTIFIER) == MysonPHYID ) { + mtdx.PHYType = MysonPHY; + DBG ( "MysonPHY\n" ); + } else { + mtdx.PHYType = OtherPHY; + DBG ( "OtherPHY\n" ); + } + } + + getlinkstatus(nic); + if( !mtdx.linkok ) + { + printf("No link!!!\n"); + return 0; + } + + mtd_reset( nic ); + + /* point to NIC specific routines */ + nic->nic_op = &mtd_operations; + return 1; +} + + +/**************************************************************************/ +static void set_rx_mode(struct nic *nic __unused) +{ + u32 mc_filter[2]; /* Multicast hash filter */ + u32 rx_mode; + + /* Too many to match, or accept all multicasts. */ + mc_filter[1] = mc_filter[0] = ~0; + rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; + + outl(mc_filter[0], mtdx.ioaddr + MAR0); + outl(mc_filter[1], mtdx.ioaddr + MAR1); + + mtdx.crvalue = ( mtdx.crvalue & ~RxModeMask ) | rx_mode; + outb( mtdx.crvalue, mtdx.ioaddr + TCRRCR); +} +/**************************************************************************/ +static unsigned int m80x_read_tick(void) +/* function: Reads the Timer tick count register which decrements by 2 from */ +/* 65536 to 0 every 1/36.414 of a second. Each 2 decrements of the */ +/* count represents 838 nsec's. */ +/* input : none. */ +/* output : none. */ +{ + unsigned char tmp; + int value; + + outb((char) 0x06, 0x43); // Command 8254 to latch T0's count + + // now read the count. + tmp = (unsigned char) inb(0x40); + value = ((int) tmp) << 8; + tmp = (unsigned char) inb(0x40); + value |= (((int) tmp) & 0xff); + return (value); +} + +static void m80x_delay(unsigned int interval) +/* function: to wait for a specified time. */ +/* input : interval ... the specified time. */ +/* output : none. */ +{ + unsigned int interval1, interval2, i = 0; + + interval1 = m80x_read_tick(); // get initial value + do + { + interval2 = m80x_read_tick(); + if (interval1 < interval2) + interval1 += 65536; + ++i; + } while (((interval1 - interval2) < (u16) interval) && (i < 65535)); +} + + +static u32 m80x_send_cmd_to_phy(long miiport, int opcode, int phyad, int regad) +{ + u32 miir; + int i; + unsigned int mask, data; + + /* enable MII output */ + miir = (u32) inl(miiport); + miir &= 0xfffffff0; + + miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO; + + /* send 32 1's preamble */ + for (i = 0; i < 32; i++) { + /* low MDC; MDO is already high (miir) */ + miir &= ~MASK_MIIR_MII_MDC; + outl(miir, miiport); + + /* high MDC */ + miir |= MASK_MIIR_MII_MDC; + outl(miir, miiport); + } + + /* calculate ST+OP+PHYAD+REGAD+TA */ + data = opcode | (phyad << 7) | (regad << 2); + + /* sent out */ + mask = 0x8000; + while (mask) { + /* low MDC, prepare MDO */ + miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO); + if (mask & data) + miir |= MASK_MIIR_MII_MDO; + + outl(miir, miiport); + /* high MDC */ + miir |= MASK_MIIR_MII_MDC; + outl(miir, miiport); + m80x_delay(30); + + /* next */ + mask >>= 1; + if (mask == 0x2 && opcode == OP_READ) + miir &= ~MASK_MIIR_MII_WRITE; + } + return miir; +} + +static int mdio_read(struct nic *nic __unused, int phyad, int regad) +{ + long miiport = mtdx.ioaddr + MANAGEMENT; + u32 miir; + unsigned int mask, data; + + miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad); + + /* read data */ + mask = 0x8000; + data = 0; + while (mask) + { + /* low MDC */ + miir &= ~MASK_MIIR_MII_MDC; + outl(miir, miiport); + + /* read MDI */ + miir = inl(miiport); + if (miir & MASK_MIIR_MII_MDI) + data |= mask; + + /* high MDC, and wait */ + miir |= MASK_MIIR_MII_MDC; + outl(miir, miiport); + m80x_delay((int) 30); + + /* next */ + mask >>= 1; + } + + /* low MDC */ + miir &= ~MASK_MIIR_MII_MDC; + outl(miir, miiport); + + return data & 0xffff; +} + +#if 0 /* not used */ +static void mdio_write(struct nic *nic __unused, int phyad, int regad, + int data) +{ + long miiport = mtdx.ioaddr + MANAGEMENT; + u32 miir; + unsigned int mask; + + miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad); + + /* write data */ + mask = 0x8000; + while (mask) + { + /* low MDC, prepare MDO */ + miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO); + if (mask & data) + miir |= MASK_MIIR_MII_MDO; + outl(miir, miiport); + + /* high MDC */ + miir |= MASK_MIIR_MII_MDC; + outl(miir, miiport); + + /* next */ + mask >>= 1; + } + + /* low MDC */ + miir &= ~MASK_MIIR_MII_MDC; + outl(miir, miiport); + + return; +} +#endif + +static void getlinkstatus(struct nic *nic) +/* function: Routine will read MII Status Register to get link status. */ +/* input : dev... pointer to the adapter block. */ +/* output : none. */ +{ + unsigned int i, DelayTime = 0x1000; + + mtdx.linkok = 0; + + if (mtdx.PHYType == MysonPHY) + { + for (i = 0; i < DelayTime; ++i) { + if (inl(mtdx.ioaddr + BMCRSR) & LinkIsUp2) { + mtdx.linkok = 1; + return; + } + // delay + m80x_delay(100); + } + } else + { + for (i = 0; i < DelayTime; ++i) { + if (mdio_read(nic, mtdx.phys[0], MII_BMSR) & BMSR_LSTATUS) { + mtdx.linkok = 1; + return; + } + // delay + m80x_delay(100); + } + } +} + + +static void getlinktype(struct nic *dev) +{ + if (mtdx.PHYType == MysonPHY) + { /* 3-in-1 case */ + if (inl(mtdx.ioaddr + TCRRCR) & FD) + mtdx.duplexmode = 2; /* full duplex */ + else + mtdx.duplexmode = 1; /* half duplex */ + if (inl(mtdx.ioaddr + TCRRCR) & PS10) + mtdx.line_speed = 1; /* 10M */ + else + mtdx.line_speed = 2; /* 100M */ + } else + { + if (mtdx.PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */ + unsigned int data; + + data = mdio_read(dev, mtdx.phys[0], MIIRegister18); + if (data & SPD_DET_100) + mtdx.line_speed = 2; /* 100M */ + else + mtdx.line_speed = 1; /* 10M */ + if (data & DPLX_DET_FULL) + mtdx.duplexmode = 2; /* full duplex mode */ + else + mtdx.duplexmode = 1; /* half duplex mode */ + } else if (mtdx.PHYType == AhdocPHY) { + unsigned int data; + + data = mdio_read(dev, mtdx.phys[0], DiagnosticReg); + if (data & Speed_100) + mtdx.line_speed = 2; /* 100M */ + else + mtdx.line_speed = 1; /* 10M */ + if (data & DPLX_FULL) + mtdx.duplexmode = 2; /* full duplex mode */ + else + mtdx.duplexmode = 1; /* half duplex mode */ + } + /* 89/6/13 add, (begin) */ + else if (mtdx.PHYType == MarvellPHY) { + unsigned int data; + + data = mdio_read(dev, mtdx.phys[0], SpecificReg); + if (data & Full_Duplex) + mtdx.duplexmode = 2; /* full duplex mode */ + else + mtdx.duplexmode = 1; /* half duplex mode */ + data &= SpeedMask; + if (data == Speed_1000M) + mtdx.line_speed = 3; /* 1000M */ + else if (data == Speed_100M) + mtdx.line_speed = 2; /* 100M */ + else + mtdx.line_speed = 1; /* 10M */ + } + /* 89/6/13 add, (end) */ + /* 89/7/27 add, (begin) */ + else if (mtdx.PHYType == Myson981) { + unsigned int data; + + data = mdio_read(dev, mtdx.phys[0], StatusRegister); + + if (data & SPEED100) + mtdx.line_speed = 2; + else + mtdx.line_speed = 1; + + if (data & FULLMODE) + mtdx.duplexmode = 2; + else + mtdx.duplexmode = 1; + } + /* 89/7/27 add, (end) */ + /* 89/12/29 add */ + else if (mtdx.PHYType == LevelOnePHY) { + unsigned int data; + + data = mdio_read(dev, mtdx.phys[0], SpecificReg); + if (data & LXT1000_Full) + mtdx.duplexmode = 2; /* full duplex mode */ + else + mtdx.duplexmode = 1; /* half duplex mode */ + data &= SpeedMask; + if (data == LXT1000_1000M) + mtdx.line_speed = 3; /* 1000M */ + else if (data == LXT1000_100M) + mtdx.line_speed = 2; /* 100M */ + else + mtdx.line_speed = 1; /* 10M */ + } + // chage crvalue + // mtdx.crvalue&=(~PS10)&(~FD); + mtdx.crvalue &= (~PS10) & (~FD) & (~PS1000); + if (mtdx.line_speed == 1) + mtdx.crvalue |= PS10; + else if (mtdx.line_speed == 3) + mtdx.crvalue |= PS1000; + if (mtdx.duplexmode == 2) + mtdx.crvalue |= FD; + } +} + +DRIVER ( "MTD80X", nic_driver, pci_driver, mtd80x_driver, + mtd_probe, mtd_disable ); diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/natsemi.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/natsemi.c new file mode 100644 index 0000000..8ca6271 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/natsemi.c @@ -0,0 +1,609 @@ +/* + natsemi.c - gPXE driver for the NatSemi DP8381x series. + + Based on: + + natsemi.c: An Etherboot driver for the NatSemi DP8381x series. + + Copyright (C) 2001 Entity Cyber, Inc. + + This development of this Etherboot driver was funded by + + Sicom Systems: http://www.sicompos.com/ + + Author: Marty Connor <mdc@etherboot.org> + Adapted from a Linux driver which was written by Donald Becker + + This software may be used and distributed according to the terms + of the GNU Public License (GPL), incorporated herein by reference. + + Original Copyright Notice: + + Written/copyright 1999-2001 by Donald Becker. + + This software may be used and distributed according to the terms of + the GNU General Public License (GPL), incorporated herein by reference. + Drivers based on or derived from this code fall under the GPL and must + retain the authorship, copyright and license notice. This file is not + a complete program and may only be used when the entire operating + system is licensed under the GPL. License for under other terms may be + available. Contact the original author for details. + + The original author may be reached as becker@scyld.com, or at + Scyld Computing Corporation + 410 Severn Ave., Suite 210 + Annapolis MD 21403 + + Support information and updates available at + http://www.scyld.com/network/netsemi.html + + References: + + http://www.scyld.com/expert/100mbps.html + http://www.scyld.com/expert/NWay.html + Datasheet is available from: + http://www.national.com/pf/DP/DP83815.html + +*/ + +FILE_LICENCE ( GPL_ANY ); + +/* Revision History */ + +/* + 02 Jul 2007 Udayan Kumar 1.2 ported the driver from etherboot to gPXE API. + Fully rewritten,adapting the old driver. + Added a circular buffer for transmit and receive. + transmit routine will not wait for transmission to finish. + poll routine deals with it. + 13 Dec 2003 Tim Legge 1.1 Enabled Multicast Support + 29 May 2001 Marty Connor 1.0 Initial Release. Tested with Netgear FA311 and FA312 boards +*/ + +#include <stdint.h> +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <gpxe/io.h> +#include <errno.h> +#include <byteswap.h> +#include <unistd.h> +#include <gpxe/pci.h> +#include <gpxe/if_ether.h> +#include <gpxe/ethernet.h> +#include <gpxe/iobuf.h> +#include <gpxe/netdevice.h> +#include <gpxe/spi_bit.h> +#include <gpxe/threewire.h> +#include <gpxe/nvo.h> +#include "natsemi.h" + +/* Function Prototypes: */ + +static int natsemi_spi_read_bit ( struct bit_basher *, unsigned int ); +static void natsemi_spi_write_bit ( struct bit_basher *,unsigned int, unsigned long ); +static void natsemi_init_eeprom ( struct natsemi_private * ); +static int natsemi_probe (struct pci_device *pci, const struct pci_device_id *id); +static void natsemi_reset (struct net_device *netdev); +static int natsemi_open (struct net_device *netdev); +static int natsemi_transmit (struct net_device *netdev, struct io_buffer *iobuf); +static void natsemi_poll (struct net_device *netdev); +static void natsemi_close (struct net_device *netdev); +static void natsemi_irq (struct net_device *netdev, int enable); +static void natsemi_remove (struct pci_device *pci); + +/** natsemi net device operations */ +static struct net_device_operations natsemi_operations = { + .open = natsemi_open, + .close = natsemi_close, + .transmit = natsemi_transmit, + .poll = natsemi_poll, + .irq = natsemi_irq, +}; + +static int natsemi_spi_read_bit ( struct bit_basher *basher, + unsigned int bit_id ) { + struct natsemi_private *np = container_of ( basher, struct natsemi_private, + spibit.basher ); + uint8_t mask = natsemi_ee_bits[bit_id]; + uint8_t eereg; + + eereg = inb ( np->ioaddr + EE_REG ); + return ( eereg & mask ); +} + +static void natsemi_spi_write_bit ( struct bit_basher *basher, + unsigned int bit_id, unsigned long data ) { + struct natsemi_private *np = container_of ( basher, struct natsemi_private, + spibit.basher ); + uint8_t mask = natsemi_ee_bits[bit_id]; + uint8_t eereg; + + eereg = inb ( np->ioaddr + EE_REG ); + eereg &= ~mask; + eereg |= ( data & mask ); + outb ( eereg, np->ioaddr + EE_REG ); +} + +static struct bit_basher_operations natsemi_basher_ops = { + .read = natsemi_spi_read_bit, + .write = natsemi_spi_write_bit, +}; + +/* It looks that this portion of EEPROM can be used for + * non-volatile stored options. Data sheet does not talk about this region. + * Currently it is not working. But with some efforts it can. + */ +static struct nvo_fragment natsemi_nvo_fragments[] = { + { 0x0c, 0x68 }, + { 0, 0 } +}; + +/* + * Set up for EEPROM access + * + * @v NAT NATSEMI NIC + */ +static void natsemi_init_eeprom ( struct natsemi_private *np ) { + + /* Initialise three-wire bus + */ + np->spibit.basher.op = &natsemi_basher_ops; + np->spibit.bus.mode = SPI_MODE_THREEWIRE; + np->spibit.endianness = SPI_BIT_LITTLE_ENDIAN; + init_spi_bit_basher ( &np->spibit ); + + /*natsemi DP 83815 only supports at93c46 + */ + init_at93c46 ( &np->eeprom, 16 ); + np->eeprom.bus = &np->spibit.bus; + np->nvo.nvs = &np->eeprom.nvs; + np->nvo.fragments = natsemi_nvo_fragments; +} + +/** + * Probe PCI device + * + * @v pci PCI device + * @v id PCI ID + * @ret rc Return status code + */ +static int natsemi_probe (struct pci_device *pci, + const struct pci_device_id *id __unused) { + struct net_device *netdev; + struct natsemi_private *np = NULL; + uint8_t ll_addr_encoded[MAX_LL_ADDR_LEN]; + uint8_t last=0,last1=0; + uint8_t prev_bytes[2]; + int i; + int rc; + + /* Allocate net device + */ + netdev = alloc_etherdev (sizeof (*np)); + if (! netdev) + return -ENOMEM; + + netdev_init (netdev, &natsemi_operations); + np = netdev->priv; + pci_set_drvdata (pci, netdev); + netdev->dev = &pci->dev; + memset (np, 0, sizeof (*np)); + np->ioaddr = pci->ioaddr; + + adjust_pci_device (pci); + + natsemi_reset (netdev); + natsemi_init_eeprom ( np ); + nvs_read ( &np->eeprom.nvs, EE_MAC-1, prev_bytes, 1 ); + nvs_read ( &np->eeprom.nvs, EE_MAC, ll_addr_encoded, ETH_ALEN ); + + /* decoding the MAC address read from NVS + * and save it in netdev->ll_addr + */ + last = prev_bytes[1] >> 7; + for ( i = 0 ; i < ETH_ALEN ; i++ ) { + last1 = ll_addr_encoded[i] >> 7; + netdev->hw_addr[i] = ll_addr_encoded[i] << 1 | last; + last = last1; + } + + /* Mark as link up; we don't yet handle link state */ + netdev_link_up ( netdev ); + + if ((rc = register_netdev (netdev)) != 0) + goto err_register_netdev; + + return 0; + +err_register_netdev: + + natsemi_reset (netdev); + netdev_put (netdev); + return rc; +} + +/** + * Remove PCI device + * + * @v pci PCI device + */ +static void natsemi_remove (struct pci_device *pci) { + struct net_device *netdev = pci_get_drvdata (pci); + + unregister_netdev (netdev); + natsemi_reset (netdev); + netdev_nullify ( netdev ); + netdev_put (netdev); +} + +/** + * Reset NIC + * + * @v NATSEMI NIC + * + * Issues a hardware reset and waits for the reset to complete. + */ +static void natsemi_reset (struct net_device *netdev) +{ + struct natsemi_private *np = netdev->priv; + int i; + u32 cfg; + u32 wcsr; + u32 rfcr; + u16 pmatch[3]; + u16 sopass[3]; + + natsemi_irq (netdev, 0); + + /* + * Resetting the chip causes some registers to be lost. + * Natsemi suggests NOT reloading the EEPROM while live, so instead + * we save the state that would have been loaded from EEPROM + * on a normal power-up (see the spec EEPROM map). + */ + + /* CFG */ + cfg = inl (np->ioaddr + ChipConfig) & CFG_RESET_SAVE; + + /* WCSR */ + wcsr = inl (np->ioaddr + WOLCmd) & WCSR_RESET_SAVE; + + /* RFCR */ + rfcr = readl (np->ioaddr + RxFilterAddr) & RFCR_RESET_SAVE; + + /* PMATCH */ + for (i = 0; i < 3; i++) { + outl(i*2, np->ioaddr + RxFilterAddr); + pmatch[i] = inw(np->ioaddr + RxFilterData); + } + + /* SOPAS */ + for (i = 0; i < 3; i++) { + outl(0xa+(i*2), np->ioaddr + RxFilterAddr); + sopass[i] = inw(np->ioaddr + RxFilterData); + } + + /* now whack the chip */ + outl(ChipReset, np->ioaddr + ChipCmd); + for (i=0; i<NATSEMI_HW_TIMEOUT; i++) { + if (! (inl (np->ioaddr + ChipCmd) & ChipReset)) + break; + udelay(5); + } + if (i == NATSEMI_HW_TIMEOUT) { + DBG ("natsemi_reset: reset did not complete in %d usec.\n", i*5); + } + + /* restore CFG */ + cfg |= inl(np->ioaddr + ChipConfig) & ~CFG_RESET_SAVE; + cfg &= ~(CfgExtPhy | CfgPhyDis); + outl (cfg, np->ioaddr + ChipConfig); + + /* restore WCSR */ + wcsr |= inl (np->ioaddr + WOLCmd) & ~WCSR_RESET_SAVE; + outl (wcsr, np->ioaddr + WOLCmd); + + /* read RFCR */ + rfcr |= inl (np->ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE; + + /* restore PMATCH */ + for (i = 0; i < 3; i++) { + outl (i*2, np->ioaddr + RxFilterAddr); + outw (pmatch[i], np->ioaddr + RxFilterData); + } + for (i = 0; i < 3; i++) { + outl (0xa+(i*2), np->ioaddr + RxFilterAddr); + outw (sopass[i], np->ioaddr + RxFilterData); + } + /* restore RFCR */ + outl (rfcr, np->ioaddr + RxFilterAddr); +} + +/** + * Open NIC + * + * @v netdev Net device + * @ret rc Return status code + */ +static int natsemi_open (struct net_device *netdev) +{ + struct natsemi_private *np = netdev->priv; + uint32_t tx_config, rx_config; + int i; + + /* Disable PME: + * The PME bit is initialized from the EEPROM contents. + * PCI cards probably have PME disabled, but motherboard + * implementations may have PME set to enable WakeOnLan. + * With PME set the chip will scan incoming packets but + * nothing will be written to memory. + */ + outl (inl (np->ioaddr + ClkRun) & ~0x100, np->ioaddr + ClkRun); + + /* Set MAC address in NIC + */ + for (i = 0 ; i < ETH_ALEN ; i+=2) { + outl (i, np->ioaddr + RxFilterAddr); + outw (netdev->ll_addr[i] + (netdev->ll_addr[i + 1] << 8), + np->ioaddr + RxFilterData); + } + + /* Setup Tx Ring + */ + np->tx_cur = 0; + np->tx_dirty = 0; + for (i = 0 ; i < TX_RING_SIZE ; i++) { + np->tx[i].link = virt_to_bus ((i + 1 < TX_RING_SIZE) ? &np->tx[i + 1] : &np->tx[0]); + np->tx[i].cmdsts = 0; + np->tx[i].bufptr = 0; + } + outl (virt_to_bus (&np->tx[0]),np->ioaddr + TxRingPtr); + + DBG ("Natsemi Tx descriptor loaded with: %#08x\n", + inl (np->ioaddr + TxRingPtr)); + + /* Setup RX ring + */ + np->rx_cur = 0; + for (i = 0 ; i < NUM_RX_DESC ; i++) { + np->iobuf[i] = alloc_iob (RX_BUF_SIZE); + if (! np->iobuf[i]) + goto memory_alloc_err; + np->rx[i].link = virt_to_bus ((i + 1 < NUM_RX_DESC) + ? &np->rx[i + 1] : &np->rx[0]); + np->rx[i].cmdsts = RX_BUF_SIZE; + np->rx[i].bufptr = virt_to_bus (np->iobuf[i]->data); + DBG (" Address of iobuf [%d] = %p and iobuf->data = %p \n", i, + &np->iobuf[i], &np->iobuf[i]->data); + } + outl (virt_to_bus (&np->rx[0]), np->ioaddr + RxRingPtr); + + DBG ("Natsemi Rx descriptor loaded with: %#08x\n", + inl (np->ioaddr + RxRingPtr)); + + /* Setup RX Filter + */ + outl (RxFilterEnable | AcceptBroadcast | AcceptAllMulticast | AcceptMyPhys, + np->ioaddr + RxFilterAddr); + + /* Initialize other registers. + * Configure the PCI bus bursts and FIFO thresholds. + * Configure for standard, in-spec Ethernet. + */ + if (inl (np->ioaddr + ChipConfig) & 0x20000000) { /* Full duplex */ + DBG ("Full duplex\n"); + tx_config = 0xD0801002 | 0xC0000000; + rx_config = 0x10000020 | 0x10000000; + } else { + DBG ("Half duplex\n"); + tx_config = 0x10801002 & ~0xC0000000; + rx_config = 0x00000020 & ~0x10000000; + } + outl (tx_config, np->ioaddr + TxConfig); + outl (rx_config, np->ioaddr + RxConfig); + + DBG ("Tx config register = %#08x Rx config register = %#08x\n", + inl (np->ioaddr + TxConfig), + inl (np->ioaddr + RxConfig)); + + /*Set the Interrupt Mask register + */ + outl((RxOk|RxErr|TxOk|TxErr),np->ioaddr + IntrMask); + /*start the receiver + */ + outl (RxOn, np->ioaddr + ChipCmd); + + return 0; + +memory_alloc_err: + + /* Frees any allocated buffers when memory + * for all buffers requested is not available + */ + i = 0; + while (np->rx[i].cmdsts == RX_BUF_SIZE) { + free_iob (np->iobuf[i]); + i++; + } + return -ENOMEM; +} + +/** + * Close NIC + * + * @v netdev Net device + */ +static void natsemi_close (struct net_device *netdev) +{ + struct natsemi_private *np = netdev->priv; + int i; + + natsemi_reset (netdev); + + for (i = 0; i < NUM_RX_DESC ; i++) { + free_iob (np->iobuf[i]); + } +} + +/** + * Transmit packet + * + * @v netdev Network device + * @v iobuf I/O buffer + * @ret rc Return status code + */ +static int natsemi_transmit (struct net_device *netdev, struct io_buffer *iobuf) +{ + struct natsemi_private *np = netdev->priv; + + if (np->tx[np->tx_cur].cmdsts != 0) { + DBG ("TX overflow\n"); + return -ENOBUFS; + } + + /* Used by netdev_tx_complete () + */ + np->tx_iobuf[np->tx_cur] = iobuf; + + /* Pad and align packet has not been used because its not required + * by the hardware. + * iob_pad (iobuf, ETH_ZLEN); + * can be used to achieve it, if required + */ + + /* Add the packet to TX ring + */ + np->tx[np->tx_cur].bufptr = virt_to_bus (iobuf->data); + np->tx[np->tx_cur].cmdsts = iob_len (iobuf) | OWN; + + DBG ("TX id %d at %#08lx + %#08zx\n", np->tx_cur, + virt_to_bus (&iobuf->data), iob_len (iobuf)); + + /* increment the circular buffer pointer to the next buffer location + */ + np->tx_cur = (np->tx_cur + 1) % TX_RING_SIZE; + + /*start the transmitter + */ + outl (TxOn, np->ioaddr + ChipCmd); + + return 0; +} + +/** + * Poll for received packets + * + * @v netdev Network device + */ +static void natsemi_poll (struct net_device *netdev) +{ + struct natsemi_private *np = netdev->priv; + unsigned int tx_status; + unsigned int rx_status; + unsigned int intr_status; + unsigned int rx_len; + struct io_buffer *rx_iob; + int i; + + /* read the interrupt register + */ + intr_status = inl (np->ioaddr + IntrStatus); + + if (!intr_status) + goto end; + + DBG ("natsemi_poll: intr_status = %#08x\n", intr_status); + + /* Check status of transmitted packets + */ + i = np->tx_dirty; + while (i != np->tx_cur) { + tx_status = np->tx[np->tx_dirty].cmdsts; + + DBG ("tx_dirty = %d tx_cur=%d tx_status=%#08x\n", + np->tx_dirty, np->tx_cur, tx_status); + + if (tx_status & OWN) + break; + + if (! (tx_status & DescPktOK)) { + netdev_tx_complete_err (netdev,np->tx_iobuf[np->tx_dirty],-EINVAL); + DBG ("Error transmitting packet, tx_status: %#08x\n", + tx_status); + } else { + netdev_tx_complete (netdev, np->tx_iobuf[np->tx_dirty]); + DBG ("Success transmitting packet\n"); + } + + np->tx[np->tx_dirty].cmdsts = 0; + np->tx_dirty = (np->tx_dirty + 1) % TX_RING_SIZE; + i = (i + 1) % TX_RING_SIZE; + } + + /* Process received packets + */ + rx_status = (unsigned int) np->rx[np->rx_cur].cmdsts; + while ((rx_status & OWN)) { + rx_len = (rx_status & DSIZE) - CRC_SIZE; + + DBG ("Received packet, rx_curr = %d, rx_status = %#08x, rx_len = %d\n", + np->rx_cur, rx_status, rx_len); + + if ((rx_status & (DescMore | DescPktOK | RxTooLong)) != DescPktOK) { + netdev_rx_err (netdev, NULL, -EINVAL); + + DBG ("natsemi_poll: Corrupted packet received!" + " Status = %#08x\n", + np->rx[np->rx_cur].cmdsts); + + } else { + + + /* If unable allocate space for this packet, + * try again next poll + */ + rx_iob = alloc_iob (rx_len); + if (! rx_iob) + goto end; + memcpy (iob_put (rx_iob, rx_len), + np->iobuf[np->rx_cur]->data, rx_len); + /* Add this packet to the receive queue. + */ + netdev_rx (netdev, rx_iob); + } + np->rx[np->rx_cur].cmdsts = RX_BUF_SIZE; + np->rx_cur = (np->rx_cur + 1) % NUM_RX_DESC; + rx_status = np->rx[np->rx_cur].cmdsts; + } +end: + /* re-enable the potentially idle receive state machine + */ + outl (RxOn, np->ioaddr + ChipCmd); +} + +/** + * Enable/disable interrupts + * + * @v netdev Network device + * @v enable Non-zero for enable, zero for disable + */ +static void natsemi_irq (struct net_device *netdev, int enable) +{ + struct natsemi_private *np = netdev->priv; + + outl ((enable ? (RxOk | RxErr | TxOk|TxErr) : 0), + np->ioaddr + IntrMask); + outl ((enable ? 1 : 0), np->ioaddr + IntrEnable); +} + +static struct pci_device_id natsemi_nics[] = { + PCI_ROM(0x100b, 0x0020, "dp83815", "DP83815", 0), +}; + +struct pci_driver natsemi_driver __pci_driver = { + .ids = natsemi_nics, + .id_count = (sizeof (natsemi_nics) / sizeof (natsemi_nics[0])), + .probe = natsemi_probe, + .remove = natsemi_remove, +}; diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/natsemi.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/natsemi.h new file mode 100644 index 0000000..ae827ba --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/natsemi.h @@ -0,0 +1,232 @@ +FILE_LICENCE ( GPL_ANY ); + +#define NATSEMI_HW_TIMEOUT 400 + +#define TX_RING_SIZE 4 +#define NUM_RX_DESC 4 +#define RX_BUF_SIZE 1536 +#define OWN 0x80000000 +#define DSIZE 0x00000FFF +#define CRC_SIZE 4 + +struct natsemi_tx { + uint32_t link; + uint32_t cmdsts; + uint32_t bufptr; +}; + +struct natsemi_rx { + uint32_t link; + uint32_t cmdsts; + uint32_t bufptr; +}; + +struct natsemi_private { + unsigned short ioaddr; + unsigned short tx_cur; + unsigned short tx_dirty; + unsigned short rx_cur; + struct natsemi_tx tx[TX_RING_SIZE]; + struct natsemi_rx rx[NUM_RX_DESC]; + + /* need to add iobuf as we cannot free iobuf->data in close without this + * alternatively substracting sizeof(head) and sizeof(list_head) can also + * give the same. + */ + struct io_buffer *iobuf[NUM_RX_DESC]; + + /* netdev_tx_complete needs pointer to the iobuf of the data so as to free + * it from the memory. + */ + struct io_buffer *tx_iobuf[TX_RING_SIZE]; + struct spi_bit_basher spibit; + struct spi_device eeprom; + struct nvo_block nvo; +}; + +/* + * Support for fibre connections on Am79C874: + * This phy needs a special setup when connected to a fibre cable. + * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf + */ +#define PHYID_AM79C874 0x0022561b + +enum { + MII_MCTRL = 0x15, /* mode control register */ + MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */ + MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */ +}; + + + +/* values we might find in the silicon revision register */ +#define SRR_DP83815_C 0x0302 +#define SRR_DP83815_D 0x0403 +#define SRR_DP83816_A4 0x0504 +#define SRR_DP83816_A5 0x0505 + +/* NATSEMI: Offsets to the device registers. + * Unlike software-only systems, device drivers interact with complex hardware. + * It's not useful to define symbolic names for every register bit in the + * device. + */ +enum register_offsets { + ChipCmd = 0x00, + ChipConfig = 0x04, + EECtrl = 0x08, + PCIBusCfg = 0x0C, + IntrStatus = 0x10, + IntrMask = 0x14, + IntrEnable = 0x18, + TxRingPtr = 0x20, + TxConfig = 0x24, + RxRingPtr = 0x30, + RxConfig = 0x34, + ClkRun = 0x3C, + WOLCmd = 0x40, + PauseCmd = 0x44, + RxFilterAddr = 0x48, + RxFilterData = 0x4C, + BootRomAddr = 0x50, + BootRomData = 0x54, + SiliconRev = 0x58, + StatsCtrl = 0x5C, + StatsData = 0x60, + RxPktErrs = 0x60, + RxMissed = 0x68, + RxCRCErrs = 0x64, + PCIPM = 0x44, + PhyStatus = 0xC0, + MIntrCtrl = 0xC4, + MIntrStatus = 0xC8, + + /* These are from the spec, around page 78... on a separate table. + */ + PGSEL = 0xCC, + PMDCSR = 0xE4, + TSTDAT = 0xFC, + DSPCFG = 0xF4, + SDCFG = 0x8C, + BasicControl = 0x80, + BasicStatus = 0x84 + +}; + +/* the values for the 'magic' registers above (PGSEL=1) */ +#define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */ +#define TSTDAT_VAL 0x0 +#define DSPCFG_VAL 0x5040 +#define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */ +#define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */ +#define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */ +#define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */ + +/* Bit in ChipCmd. + */ +enum ChipCmdBits { + ChipReset = 0x100, + RxReset = 0x20, + TxReset = 0x10, + RxOff = 0x08, + RxOn = 0x04, + TxOff = 0x02, + TxOn = 0x01 +}; + +enum ChipConfig_bits { + CfgPhyDis = 0x200, + CfgPhyRst = 0x400, + CfgExtPhy = 0x1000, + CfgAnegEnable = 0x2000, + CfgAneg100 = 0x4000, + CfgAnegFull = 0x8000, + CfgAnegDone = 0x8000000, + CfgFullDuplex = 0x20000000, + CfgSpeed100 = 0x40000000, + CfgLink = 0x80000000, +}; + + +/* Bits in the RxMode register. + */ +enum rx_mode_bits { + AcceptErr = 0x20, + AcceptRunt = 0x10, + AcceptBroadcast = 0xC0000000, + AcceptMulticast = 0x00200000, + AcceptAllMulticast = 0x20000000, + AcceptAllPhys = 0x10000000, + AcceptMyPhys = 0x08000000, + RxFilterEnable = 0x80000000 +}; + +/* Bits in network_desc.status + */ +enum desc_status_bits { + DescOwn = 0x80000000, + DescMore = 0x40000000, + DescIntr = 0x20000000, + DescNoCRC = 0x10000000, + DescPktOK = 0x08000000, + RxTooLong = 0x00400000 +}; + +/*Bits in Interrupt Mask register + */ +enum Intr_mask_register_bits { + RxOk = 0x001, + RxErr = 0x004, + TxOk = 0x040, + TxErr = 0x100 +}; + +enum MIntrCtrl_bits { + MICRIntEn = 0x2, +}; + +/* CFG bits [13:16] [18:23] */ +#define CFG_RESET_SAVE 0xfde000 +/* WCSR bits [0:4] [9:10] */ +#define WCSR_RESET_SAVE 0x61f +/* RFCR bits [20] [22] [27:31] */ +#define RFCR_RESET_SAVE 0xf8500000; + +/* Delay between EEPROM clock transitions. + No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need + a delay. */ +#define eeprom_delay(ee_addr) inl(ee_addr) + +enum EEPROM_Ctrl_Bits { + EE_ShiftClk = 0x04, + EE_DataIn = 0x01, + EE_ChipSelect = 0x08, + EE_DataOut = 0x02 +}; + +#define EE_Write0 (EE_ChipSelect) +#define EE_Write1 (EE_ChipSelect | EE_DataIn) + +/* The EEPROM commands include the alway-set leading bit. */ +enum EEPROM_Cmds { + EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6), +}; + +/* EEPROM access , values are devices specific + */ +#define EE_CS 0x08 /* EEPROM chip select */ +#define EE_SK 0x04 /* EEPROM shift clock */ +#define EE_DI 0x01 /* Data in */ +#define EE_DO 0x02 /* Data out */ + +/* Offsets within EEPROM (these are word offsets) + */ +#define EE_MAC 7 +#define EE_REG EECtrl + +static const uint8_t natsemi_ee_bits[] = { + [SPI_BIT_SCLK] = EE_SK, + [SPI_BIT_MOSI] = EE_DI, + [SPI_BIT_MISO] = EE_DO, + [SPI_BIT_SS(0)] = EE_CS, +}; + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ne2k_isa.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ne2k_isa.c new file mode 100644 index 0000000..603d1ed --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ne2k_isa.c @@ -0,0 +1,375 @@ +/************************************************************************** + ETHERBOOT - BOOTP/TFTP Bootstrap Program + + Author: Martin Renters + Date: May/94 + + This code is based heavily on David Greenman's if_ed.c driver + + Copyright (C) 1993-1994, David Greenman, Martin Renters. + This software may be used, modified, copied, distributed, and sold, in + both source and binary form provided that the above copyright and these + terms are retained. Under no circumstances are the authors responsible for + the proper functioning of this software, nor do the authors assume any + responsibility for damages incurred with its use. + + Multicast support added by Timothy Legge (timlegge@users.sourceforge.net) 09/28/2003 + Relocation support added by Ken Yap (ken_yap@users.sourceforge.net) 28/12/02 + Card Detect support adapted from the eCos driver (Christian Plessl <cplessl@ee.ethz.ch>) + Extracted from ns8390.c and adapted by Pantelis Koukousoulas <pktoss@gmail.com> + **************************************************************************/ + +FILE_LICENCE ( BSD2 ); + +#include "ns8390.h" +#include "etherboot.h" +#include "nic.h" +#include <gpxe/ethernet.h> +#include <gpxe/isa.h> +#include <errno.h> + +#define ASIC_PIO NE_DATA + +static unsigned char eth_vendor, eth_flags; +static unsigned short eth_nic_base, eth_asic_base; +static unsigned char eth_memsize, eth_rx_start, eth_tx_start; +static Address eth_bmem, eth_rmem; +static unsigned char eth_drain_receiver; + +static struct nic_operations ne_operations; +static void ne_reset(struct nic *nic, struct isa_device *isa); + +static isa_probe_addr_t ne_probe_addrs[] = { 0x300, 0x280, 0x320, 0x340, 0x380, 0x220, }; + +/************************************************************************** + ETH_PIO_READ - Read a frame via Programmed I/O + **************************************************************************/ +static void eth_pio_read(unsigned int src, unsigned char *dst, unsigned int cnt) { + outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + outb(cnt, eth_nic_base + D8390_P0_RBCR0); + outb(cnt >> 8, eth_nic_base + D8390_P0_RBCR1); + outb(src, eth_nic_base + D8390_P0_RSAR0); + outb(src >> 8, eth_nic_base + D8390_P0_RSAR1); + outb(D8390_COMMAND_RD0 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + if (eth_flags & FLAG_16BIT) + cnt = (cnt + 1) >> 1; + + while (cnt--) { + if (eth_flags & FLAG_16BIT) { + *((unsigned short *) dst) = inw(eth_asic_base + ASIC_PIO); + dst += 2; + } else + *(dst++) = inb(eth_asic_base + ASIC_PIO); + } +} + +/************************************************************************** + ETH_PIO_WRITE - Write a frame via Programmed I/O + **************************************************************************/ +static void eth_pio_write(const unsigned char *src, unsigned int dst, + unsigned int cnt) { + outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR); + outb(cnt, eth_nic_base + D8390_P0_RBCR0); + outb(cnt >> 8, eth_nic_base + D8390_P0_RBCR1); + outb(dst, eth_nic_base + D8390_P0_RSAR0); + outb(dst >> 8, eth_nic_base + D8390_P0_RSAR1); + outb(D8390_COMMAND_RD1 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + if (eth_flags & FLAG_16BIT) + cnt = (cnt + 1) >> 1; + + while (cnt--) { + + if (eth_flags & FLAG_16BIT) { + outw(*((unsigned short *) src), eth_asic_base + ASIC_PIO); + src += 2; + } else + outb(*(src++), eth_asic_base + ASIC_PIO); + } +} + +/************************************************************************** + enable_multicast - Enable Multicast + **************************************************************************/ +static void enable_multicast(unsigned short eth_nic_base) { + unsigned char mcfilter[8]; + int i; + + memset(mcfilter, 0xFF, 8); + outb(4, eth_nic_base + D8390_P0_RCR); + outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS1, eth_nic_base + D8390_P0_COMMAND); + for (i = 0; i < 8; i++) { + outb(mcfilter[i], eth_nic_base + 8 + i); + if (inb(eth_nic_base + 8 + i) != mcfilter[i]) + DBG("Error SMC 83C690 Multicast filter read/write mishap %d\n", + i); + } + outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS0, eth_nic_base + D8390_P0_COMMAND); + outb(4 | 0x08, eth_nic_base + D8390_P0_RCR); +} + +/************************************************************************** + NE_PROBE1 - Look for an adapter on the ISA bus + **************************************************************************/ +static int ne_probe1(isa_probe_addr_t ioaddr) { + //From the eCos driver + unsigned int regd; + unsigned int state; + + state = inb(ioaddr); + outb(ioaddr, D8390_COMMAND_RD2 | D8390_COMMAND_PS1 | D8390_COMMAND_STP); + regd = inb(ioaddr + D8390_P0_TCR); + + if (inb(ioaddr + D8390_P0_TCR)) { + outb(ioaddr, state); + outb(ioaddr + 0x0d, regd); + return 0; + } + + return 1; +} + +/************************************************************************** + NE_PROBE - Initialize an adapter ??? + **************************************************************************/ +static int ne_probe(struct nic *nic, struct isa_device *isa) { + int i; + unsigned char c; + unsigned char romdata[16]; + unsigned char testbuf[32]; + + eth_vendor = VENDOR_NONE; + eth_drain_receiver = 0; + + nic->irqno = 0; + nic->ioaddr = isa->ioaddr; + eth_nic_base = isa->ioaddr; + + /****************************************************************** + Search for NE1000/2000 if no WD/SMC or 3com cards + ******************************************************************/ + if (eth_vendor == VENDOR_NONE) { + + static unsigned char test[] = "NE*000 memory"; + + eth_bmem = 0; /* No shared memory */ + + eth_flags = FLAG_PIO; + eth_asic_base = eth_nic_base + NE_ASIC_OFFSET; + eth_memsize = MEM_16384; + eth_tx_start = 32; + eth_rx_start = 32 + D8390_TXBUF_SIZE; + c = inb(eth_asic_base + NE_RESET); + outb(c, eth_asic_base + NE_RESET); + (void) inb(0x84); + outb(D8390_COMMAND_STP | D8390_COMMAND_RD2, eth_nic_base + + D8390_P0_COMMAND); + outb(D8390_RCR_MON, eth_nic_base + D8390_P0_RCR); + outb(D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR); + outb(MEM_8192, eth_nic_base + D8390_P0_PSTART); + outb(MEM_16384, eth_nic_base + D8390_P0_PSTOP); + eth_pio_write((unsigned char *) test, 8192, sizeof(test)); + eth_pio_read(8192, testbuf, sizeof(test)); + if (!memcmp(test, testbuf, sizeof(test))) + goto out; + eth_flags |= FLAG_16BIT; + eth_memsize = MEM_32768; + eth_tx_start = 64; + eth_rx_start = 64 + D8390_TXBUF_SIZE; + outb(D8390_DCR_WTS | D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + + D8390_P0_DCR); + outb(MEM_16384, eth_nic_base + D8390_P0_PSTART); + outb(MEM_32768, eth_nic_base + D8390_P0_PSTOP); + eth_pio_write((unsigned char *) test, 16384, sizeof(test)); + eth_pio_read(16384, testbuf, sizeof(test)); + if (!memcmp(testbuf, test, sizeof(test))) + goto out; + + +out: + if (eth_nic_base == 0) + return (0); + if (eth_nic_base > ISA_MAX_ADDR) /* PCI probably */ + eth_flags |= FLAG_16BIT; + eth_vendor = VENDOR_NOVELL; + eth_pio_read(0, romdata, sizeof(romdata)); + for (i = 0; i < ETH_ALEN; i++) { + nic->node_addr[i] = romdata[i + ((eth_flags & FLAG_16BIT) ? i : 0)]; + } + nic->ioaddr = eth_nic_base; + DBG("\nNE%c000 base %4.4x, MAC Addr %s\n", + (eth_flags & FLAG_16BIT) ? '2' : '1', eth_nic_base, eth_ntoa( + nic->node_addr)); + } + + if (eth_vendor == VENDOR_NONE) + return (0); + + if (eth_vendor != VENDOR_3COM) + eth_rmem = eth_bmem; + + ne_reset(nic, isa); + nic->nic_op = &ne_operations; + return 1; +} + + +/************************************************************************** + NE_DISABLE - Turn off adapter + **************************************************************************/ +static void ne_disable(struct nic *nic, struct isa_device *isa) { + ne_reset(nic, isa); +} + + +/************************************************************************** + NE_RESET - Reset adapter + **************************************************************************/ +static void ne_reset(struct nic *nic, struct isa_device *isa __unused) +{ + int i; + + eth_drain_receiver = 0; + outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | + D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND); + if (eth_flags & FLAG_16BIT) + outb(0x49, eth_nic_base+D8390_P0_DCR); + else + outb(0x48, eth_nic_base+D8390_P0_DCR); + outb(0, eth_nic_base+D8390_P0_RBCR0); + outb(0, eth_nic_base+D8390_P0_RBCR1); + outb(0x20, eth_nic_base+D8390_P0_RCR); /* monitor mode */ + outb(2, eth_nic_base+D8390_P0_TCR); + outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR); + outb(eth_rx_start, eth_nic_base+D8390_P0_PSTART); + + outb(eth_memsize, eth_nic_base+D8390_P0_PSTOP); + outb(eth_memsize - 1, eth_nic_base+D8390_P0_BOUND); + outb(0xFF, eth_nic_base+D8390_P0_ISR); + outb(0, eth_nic_base+D8390_P0_IMR); + outb(D8390_COMMAND_PS1 | + D8390_COMMAND_RD2 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND); + + for (i=0; i<ETH_ALEN; i++) + outb(nic->node_addr[i], eth_nic_base+D8390_P1_PAR0+i); + for (i=0; i<ETH_ALEN; i++) + outb(0xFF, eth_nic_base+D8390_P1_MAR0+i); + outb(eth_rx_start, eth_nic_base+D8390_P1_CURR); + outb(D8390_COMMAND_PS0 | + D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND); + outb(0xFF, eth_nic_base+D8390_P0_ISR); + outb(0, eth_nic_base+D8390_P0_TCR); /* transmitter on */ + outb(4, eth_nic_base+D8390_P0_RCR); /* allow rx broadcast frames */ + + enable_multicast(eth_nic_base); +} + + +/************************************************************************** + NE_POLL - Wait for a frame + **************************************************************************/ +static int ne_poll(struct nic *nic __unused, int retrieve __unused) +{ + int ret = 0; + unsigned char rstat, curr, next; + unsigned short len, frag; + unsigned short pktoff; + unsigned char *p; + struct ringbuffer pkthdr; + + rstat = inb(eth_nic_base+D8390_P0_RSR); + if (!(rstat & D8390_RSTAT_PRX)) return(0); + next = inb(eth_nic_base+D8390_P0_BOUND)+1; + if (next >= eth_memsize) next = eth_rx_start; + outb(D8390_COMMAND_PS1, eth_nic_base+D8390_P0_COMMAND); + curr = inb(eth_nic_base+D8390_P1_CURR); + outb(D8390_COMMAND_PS0, eth_nic_base+D8390_P0_COMMAND); + if (curr >= eth_memsize) curr=eth_rx_start; + if (curr == next) return(0); + + if ( ! retrieve ) return 1; + + pktoff = next << 8; + if (eth_flags & FLAG_PIO) + eth_pio_read(pktoff, (unsigned char *)&pkthdr, 4); + else + memcpy(&pkthdr, bus_to_virt(eth_rmem + pktoff), 4); + pktoff += sizeof(pkthdr); + /* incoming length includes FCS so must sub 4 */ + len = pkthdr.len - 4; + if ((pkthdr.status & D8390_RSTAT_PRX) == 0 || len < ETH_ZLEN + || len> ETH_FRAME_LEN) { + DBG("Bogus packet, ignoring\n"); + return (0); + } + else { + p = nic->packet; + nic->packetlen = len; /* available to caller */ + frag = (eth_memsize << 8) - pktoff; + if (len> frag) { /* We have a wrap-around */ + /* read first part */ + if (eth_flags & FLAG_PIO) + eth_pio_read(pktoff, p, frag); + else + memcpy(p, bus_to_virt(eth_rmem + pktoff), frag); + pktoff = eth_rx_start << 8; + p += frag; + len -= frag; + } + /* read second part */ + if (eth_flags & FLAG_PIO) + eth_pio_read(pktoff, p, len); + else + memcpy(p, bus_to_virt(eth_rmem + pktoff), len); + ret = 1; + } + next = pkthdr.next; /* frame number of next packet */ + if (next == eth_rx_start) + next = eth_memsize; + outb(next-1, eth_nic_base+D8390_P0_BOUND); + return(ret); +} + + +/************************************************************************** + NE_TRANSMIT - Transmit a frame + **************************************************************************/ +static void ne_transmit(struct nic *nic, const char *d, /* Destination */ +unsigned int t, /* Type */ +unsigned int s, /* size */ +const char *p) { /* Packet */ + + /* Programmed I/O */ + unsigned short type; + type = (t >> 8) | (t << 8); + eth_pio_write((unsigned char *) d, eth_tx_start << 8, ETH_ALEN); + eth_pio_write(nic->node_addr, (eth_tx_start << 8) + ETH_ALEN, ETH_ALEN); + /* bcc generates worse code without (const+const) below */ + eth_pio_write((unsigned char *) &type, (eth_tx_start << 8) + (ETH_ALEN + + ETH_ALEN), 2); + eth_pio_write((unsigned char *) p, (eth_tx_start << 8) + ETH_HLEN, s); + s += ETH_HLEN; + if (s < ETH_ZLEN) + s = ETH_ZLEN; + + outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | D8390_COMMAND_STA, + eth_nic_base + D8390_P0_COMMAND); + outb(eth_tx_start, eth_nic_base + D8390_P0_TPSR); + outb(s, eth_nic_base + D8390_P0_TBCR0); + outb(s >> 8, eth_nic_base + D8390_P0_TBCR1); + + outb(D8390_COMMAND_PS0 | D8390_COMMAND_TXP | D8390_COMMAND_RD2 + | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); +} + +static struct nic_operations ne_operations = { .connect = dummy_connect, + .poll = ne_poll, .transmit = ne_transmit, .irq = dummy_irq, +}; + +ISA_DRIVER ( ne_driver, ne_probe_addrs, ne_probe1, + GENERIC_ISAPNP_VENDOR, 0x0600 ); + +DRIVER ( "ne", nic_driver, isapnp_driver, ne_driver, + ne_probe, ne_disable ); + +ISA_ROM("ne","NE1000/2000 and clones"); diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ns83820.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ns83820.c new file mode 100644 index 0000000..d5c6694 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ns83820.c @@ -0,0 +1,1013 @@ +/************************************************************************** +* ns83820.c: Etherboot device driver for the National Semiconductor 83820 +* Written 2004 by Timothy Legge <tlegge@rogers.com> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +* +* Portions of this code based on: +* ns83820.c by Benjamin LaHaise with contributions +* for Linux kernel 2.4.x. +* +* Linux Driver Version 0.20, 20020610 +* +* This development of this Etherboot driver was funded by: +* +* NXTV: http://www.nxtv.com/ +* +* REVISION HISTORY: +* ================ +* +* v1.0 02-16-2004 timlegge Initial port of Linux driver +* v1.1 02-19-2004 timlegge More rohbust transmit and poll +* +* Indent Options: indent -kr -i8 +***************************************************************************/ + +FILE_LICENCE ( GPL2_OR_LATER ); + +/* to get some global routines like printf */ +#include "etherboot.h" +/* to get the interface to the body of the program */ +#include "nic.h" +/* to get the PCI support functions, if this is a PCI NIC */ +#include <gpxe/pci.h> + +#if ARCH == ia64 /* Support 64-bit addressing */ +#define USE_64BIT_ADDR +#endif + +//#define DDEBUG +#ifdef DDEBUG +#define dprintf(x) printf x +#else +#define dprintf(x) +#endif + +#define HZ 100 + +/* Condensed operations for readability. */ +#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) +#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) + +/* NIC specific static variables go here */ + +/* Global parameters. See MODULE_PARM near the bottom. */ +// static int ihr = 2; +static int reset_phy = 0; +static int lnksts = 0; /* CFG_LNKSTS bit polarity */ + +#if defined(CONFIG_HIGHMEM64G) || defined(__ia64__) +#define USE_64BIT_ADDR "+" +#endif + +#if defined(USE_64BIT_ADDR) +#define TRY_DAC 1 +#else +#define TRY_DAC 0 +#endif + +/* tunables */ +#define RX_BUF_SIZE 1500 /* 8192 */ + +/* Must not exceed ~65000. */ +#define NR_RX_DESC 64 +#define NR_TX_DESC 1 + + /* not tunable *//* Extra 6 bytes for 64 bit alignment (divisable by 8) */ +#define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14 + 6) /* rx/tx mac addr + type */ + +#define MIN_TX_DESC_FREE 8 + +/* register defines */ +#define CFGCS 0x04 + +#define CR_TXE 0x00000001 +#define CR_TXD 0x00000002 +/* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE + * The Receive engine skips one descriptor and moves + * onto the next one!! */ +#define CR_RXE 0x00000004 +#define CR_RXD 0x00000008 +#define CR_TXR 0x00000010 +#define CR_RXR 0x00000020 +#define CR_SWI 0x00000080 +#define CR_RST 0x00000100 + +#define PTSCR_EEBIST_FAIL 0x00000001 +#define PTSCR_EEBIST_EN 0x00000002 +#define PTSCR_EELOAD_EN 0x00000004 +#define PTSCR_RBIST_FAIL 0x000001b8 +#define PTSCR_RBIST_DONE 0x00000200 +#define PTSCR_RBIST_EN 0x00000400 +#define PTSCR_RBIST_RST 0x00002000 + +#define MEAR_EEDI 0x00000001 +#define MEAR_EEDO 0x00000002 +#define MEAR_EECLK 0x00000004 +#define MEAR_EESEL 0x00000008 +#define MEAR_MDIO 0x00000010 +#define MEAR_MDDIR 0x00000020 +#define MEAR_MDC 0x00000040 + +#define ISR_TXDESC3 0x40000000 +#define ISR_TXDESC2 0x20000000 +#define ISR_TXDESC1 0x10000000 +#define ISR_TXDESC0 0x08000000 +#define ISR_RXDESC3 0x04000000 +#define ISR_RXDESC2 0x02000000 +#define ISR_RXDESC1 0x01000000 +#define ISR_RXDESC0 0x00800000 +#define ISR_TXRCMP 0x00400000 +#define ISR_RXRCMP 0x00200000 +#define ISR_DPERR 0x00100000 +#define ISR_SSERR 0x00080000 +#define ISR_RMABT 0x00040000 +#define ISR_RTABT 0x00020000 +#define ISR_RXSOVR 0x00010000 +#define ISR_HIBINT 0x00008000 +#define ISR_PHY 0x00004000 +#define ISR_PME 0x00002000 +#define ISR_SWI 0x00001000 +#define ISR_MIB 0x00000800 +#define ISR_TXURN 0x00000400 +#define ISR_TXIDLE 0x00000200 +#define ISR_TXERR 0x00000100 +#define ISR_TXDESC 0x00000080 +#define ISR_TXOK 0x00000040 +#define ISR_RXORN 0x00000020 +#define ISR_RXIDLE 0x00000010 +#define ISR_RXEARLY 0x00000008 +#define ISR_RXERR 0x00000004 +#define ISR_RXDESC 0x00000002 +#define ISR_RXOK 0x00000001 + +#define TXCFG_CSI 0x80000000 +#define TXCFG_HBI 0x40000000 +#define TXCFG_MLB 0x20000000 +#define TXCFG_ATP 0x10000000 +#define TXCFG_ECRETRY 0x00800000 +#define TXCFG_BRST_DIS 0x00080000 +#define TXCFG_MXDMA1024 0x00000000 +#define TXCFG_MXDMA512 0x00700000 +#define TXCFG_MXDMA256 0x00600000 +#define TXCFG_MXDMA128 0x00500000 +#define TXCFG_MXDMA64 0x00400000 +#define TXCFG_MXDMA32 0x00300000 +#define TXCFG_MXDMA16 0x00200000 +#define TXCFG_MXDMA8 0x00100000 + +#define CFG_LNKSTS 0x80000000 +#define CFG_SPDSTS 0x60000000 +#define CFG_SPDSTS1 0x40000000 +#define CFG_SPDSTS0 0x20000000 +#define CFG_DUPSTS 0x10000000 +#define CFG_TBI_EN 0x01000000 +#define CFG_MODE_1000 0x00400000 +/* Ramit : Dont' ever use AUTO_1000, it never works and is buggy. + * Read the Phy response and then configure the MAC accordingly */ +#define CFG_AUTO_1000 0x00200000 +#define CFG_PINT_CTL 0x001c0000 +#define CFG_PINT_DUPSTS 0x00100000 +#define CFG_PINT_LNKSTS 0x00080000 +#define CFG_PINT_SPDSTS 0x00040000 +#define CFG_TMRTEST 0x00020000 +#define CFG_MRM_DIS 0x00010000 +#define CFG_MWI_DIS 0x00008000 +#define CFG_T64ADDR 0x00004000 +#define CFG_PCI64_DET 0x00002000 +#define CFG_DATA64_EN 0x00001000 +#define CFG_M64ADDR 0x00000800 +#define CFG_PHY_RST 0x00000400 +#define CFG_PHY_DIS 0x00000200 +#define CFG_EXTSTS_EN 0x00000100 +#define CFG_REQALG 0x00000080 +#define CFG_SB 0x00000040 +#define CFG_POW 0x00000020 +#define CFG_EXD 0x00000010 +#define CFG_PESEL 0x00000008 +#define CFG_BROM_DIS 0x00000004 +#define CFG_EXT_125 0x00000002 +#define CFG_BEM 0x00000001 + +#define EXTSTS_UDPPKT 0x00200000 +#define EXTSTS_TCPPKT 0x00080000 +#define EXTSTS_IPPKT 0x00020000 + +#define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0)) + +#define MIBC_MIBS 0x00000008 +#define MIBC_ACLR 0x00000004 +#define MIBC_FRZ 0x00000002 +#define MIBC_WRN 0x00000001 + +#define PCR_PSEN (1 << 31) +#define PCR_PS_MCAST (1 << 30) +#define PCR_PS_DA (1 << 29) +#define PCR_STHI_8 (3 << 23) +#define PCR_STLO_4 (1 << 23) +#define PCR_FFHI_8K (3 << 21) +#define PCR_FFLO_4K (1 << 21) +#define PCR_PAUSE_CNT 0xFFFE + +#define RXCFG_AEP 0x80000000 +#define RXCFG_ARP 0x40000000 +#define RXCFG_STRIPCRC 0x20000000 +#define RXCFG_RX_FD 0x10000000 +#define RXCFG_ALP 0x08000000 +#define RXCFG_AIRL 0x04000000 +#define RXCFG_MXDMA512 0x00700000 +#define RXCFG_DRTH 0x0000003e +#define RXCFG_DRTH0 0x00000002 + +#define RFCR_RFEN 0x80000000 +#define RFCR_AAB 0x40000000 +#define RFCR_AAM 0x20000000 +#define RFCR_AAU 0x10000000 +#define RFCR_APM 0x08000000 +#define RFCR_APAT 0x07800000 +#define RFCR_APAT3 0x04000000 +#define RFCR_APAT2 0x02000000 +#define RFCR_APAT1 0x01000000 +#define RFCR_APAT0 0x00800000 +#define RFCR_AARP 0x00400000 +#define RFCR_MHEN 0x00200000 +#define RFCR_UHEN 0x00100000 +#define RFCR_ULM 0x00080000 + +#define VRCR_RUDPE 0x00000080 +#define VRCR_RTCPE 0x00000040 +#define VRCR_RIPE 0x00000020 +#define VRCR_IPEN 0x00000010 +#define VRCR_DUTF 0x00000008 +#define VRCR_DVTF 0x00000004 +#define VRCR_VTREN 0x00000002 +#define VRCR_VTDEN 0x00000001 + +#define VTCR_PPCHK 0x00000008 +#define VTCR_GCHK 0x00000004 +#define VTCR_VPPTI 0x00000002 +#define VTCR_VGTI 0x00000001 + +#define CR 0x00 +#define CFG 0x04 +#define MEAR 0x08 +#define PTSCR 0x0c +#define ISR 0x10 +#define IMR 0x14 +#define IER 0x18 +#define IHR 0x1c +#define TXDP 0x20 +#define TXDP_HI 0x24 +#define TXCFG 0x28 +#define GPIOR 0x2c +#define RXDP 0x30 +#define RXDP_HI 0x34 +#define RXCFG 0x38 +#define PQCR 0x3c +#define WCSR 0x40 +#define PCR 0x44 +#define RFCR 0x48 +#define RFDR 0x4c + +#define SRR 0x58 + +#define VRCR 0xbc +#define VTCR 0xc0 +#define VDR 0xc4 +#define CCSR 0xcc + +#define TBICR 0xe0 +#define TBISR 0xe4 +#define TANAR 0xe8 +#define TANLPAR 0xec +#define TANER 0xf0 +#define TESR 0xf4 + +#define TBICR_MR_AN_ENABLE 0x00001000 +#define TBICR_MR_RESTART_AN 0x00000200 + +#define TBISR_MR_LINK_STATUS 0x00000020 +#define TBISR_MR_AN_COMPLETE 0x00000004 + +#define TANAR_PS2 0x00000100 +#define TANAR_PS1 0x00000080 +#define TANAR_HALF_DUP 0x00000040 +#define TANAR_FULL_DUP 0x00000020 + +#define GPIOR_GP5_OE 0x00000200 +#define GPIOR_GP4_OE 0x00000100 +#define GPIOR_GP3_OE 0x00000080 +#define GPIOR_GP2_OE 0x00000040 +#define GPIOR_GP1_OE 0x00000020 +#define GPIOR_GP3_OUT 0x00000004 +#define GPIOR_GP1_OUT 0x00000001 + +#define LINK_AUTONEGOTIATE 0x01 +#define LINK_DOWN 0x02 +#define LINK_UP 0x04 + + +#define __kick_rx() writel(CR_RXE, ns->base + CR) + +#define kick_rx() do { \ + dprintf(("kick_rx: maybe kicking\n")); \ + writel(virt_to_le32desc(&rx_ring[ns->cur_rx]), ns->base + RXDP); \ + if (ns->next_rx == ns->next_empty) \ + printf("uh-oh: next_rx == next_empty???\n"); \ + __kick_rx(); \ +} while(0) + + +#ifdef USE_64BIT_ADDR +#define HW_ADDR_LEN 8 +#else +#define HW_ADDR_LEN 4 +#endif + +#define CMDSTS_OWN 0x80000000 +#define CMDSTS_MORE 0x40000000 +#define CMDSTS_INTR 0x20000000 +#define CMDSTS_ERR 0x10000000 +#define CMDSTS_OK 0x08000000 +#define CMDSTS_LEN_MASK 0x0000ffff + +#define CMDSTS_DEST_MASK 0x01800000 +#define CMDSTS_DEST_SELF 0x00800000 +#define CMDSTS_DEST_MULTI 0x01000000 + +#define DESC_SIZE 8 /* Should be cache line sized */ + +#ifdef USE_64BIT_ADDR +struct ring_desc { + uint64_t link; + uint64_t bufptr; + u32 cmdsts; + u32 extsts; /* Extended status field */ +}; +#else +struct ring_desc { + u32 link; + u32 bufptr; + u32 cmdsts; + u32 extsts; /* Extended status field */ +}; +#endif + +/* Private Storage for the NIC */ +static struct ns83820_private { + u8 *base; + int up; + long idle; + u32 *next_rx_desc; + u16 next_rx, next_empty; + u32 cur_rx; + u32 *descs; + unsigned ihr; + u32 CFG_cache; + u32 MEAR_cache; + u32 IMR_cache; + int linkstate; + u16 tx_done_idx; + u16 tx_idx; + u16 tx_intr_idx; + u32 phy_descs; + u32 *tx_descs; + +} nsx; +static struct ns83820_private *ns; + +/* Define the TX and RX Descriptor and Buffers */ +struct { + struct ring_desc tx_ring[NR_TX_DESC] __attribute__ ((aligned(8))); + unsigned char txb[NR_TX_DESC * REAL_RX_BUF_SIZE]; + struct ring_desc rx_ring[NR_RX_DESC] __attribute__ ((aligned(8))); + unsigned char rxb[NR_RX_DESC * REAL_RX_BUF_SIZE] + __attribute__ ((aligned(8))); +} ns83820_bufs __shared; +#define tx_ring ns83820_bufs.tx_ring +#define rx_ring ns83820_bufs.rx_ring +#define txb ns83820_bufs.txb +#define rxb ns83820_bufs.rxb + +static void phy_intr(struct nic *nic __unused) +{ + static char *speeds[] = + { "10", "100", "1000", "1000(?)", "1000F" }; + u32 cfg, new_cfg; + u32 tbisr, tanar, tanlpar; + int speed, fullduplex, newlinkstate; + + cfg = readl(ns->base + CFG) ^ SPDSTS_POLARITY; + if (ns->CFG_cache & CFG_TBI_EN) { + /* we have an optical transceiver */ + tbisr = readl(ns->base + TBISR); + tanar = readl(ns->base + TANAR); + tanlpar = readl(ns->base + TANLPAR); + dprintf(("phy_intr: tbisr=%hX, tanar=%hX, tanlpar=%hX\n", + tbisr, tanar, tanlpar)); + + if ((fullduplex = (tanlpar & TANAR_FULL_DUP) + && (tanar & TANAR_FULL_DUP))) { + + /* both of us are full duplex */ + writel(readl(ns->base + TXCFG) + | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP, + ns->base + TXCFG); + writel(readl(ns->base + RXCFG) | RXCFG_RX_FD, + ns->base + RXCFG); + /* Light up full duplex LED */ + writel(readl(ns->base + GPIOR) | GPIOR_GP1_OUT, + ns->base + GPIOR); + + } else if (((tanlpar & TANAR_HALF_DUP) + && (tanar & TANAR_HALF_DUP)) + || ((tanlpar & TANAR_FULL_DUP) + && (tanar & TANAR_HALF_DUP)) + || ((tanlpar & TANAR_HALF_DUP) + && (tanar & TANAR_FULL_DUP))) { + + /* one or both of us are half duplex */ + writel((readl(ns->base + TXCFG) + & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP, + ns->base + TXCFG); + writel(readl(ns->base + RXCFG) & ~RXCFG_RX_FD, + ns->base + RXCFG); + /* Turn off full duplex LED */ + writel(readl(ns->base + GPIOR) & ~GPIOR_GP1_OUT, + ns->base + GPIOR); + } + + speed = 4; /* 1000F */ + + } else { + /* we have a copper transceiver */ + new_cfg = + ns->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS); + + if (cfg & CFG_SPDSTS1) + new_cfg |= CFG_MODE_1000; + else + new_cfg &= ~CFG_MODE_1000; + + speed = ((cfg / CFG_SPDSTS0) & 3); + fullduplex = (cfg & CFG_DUPSTS); + + if (fullduplex) + new_cfg |= CFG_SB; + + if ((cfg & CFG_LNKSTS) && + ((new_cfg ^ ns->CFG_cache) & CFG_MODE_1000)) { + writel(new_cfg, ns->base + CFG); + ns->CFG_cache = new_cfg; + } + + ns->CFG_cache &= ~CFG_SPDSTS; + ns->CFG_cache |= cfg & CFG_SPDSTS; + } + + newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN; + + if (newlinkstate & LINK_UP && ns->linkstate != newlinkstate) { + printf("link now %s mbps, %s duplex and up.\n", + speeds[speed], fullduplex ? "full" : "half"); + } else if (newlinkstate & LINK_DOWN + && ns->linkstate != newlinkstate) { + printf("link now down.\n"); + } + ns->linkstate = newlinkstate; +} +static void ns83820_set_multicast(struct nic *nic __unused); +static void ns83820_setup_rx(struct nic *nic) +{ + unsigned i; + ns->idle = 1; + ns->next_rx = 0; + ns->next_rx_desc = ns->descs; + ns->next_empty = 0; + ns->cur_rx = 0; + + + for (i = 0; i < NR_RX_DESC; i++) { + rx_ring[i].link = virt_to_le32desc(&rx_ring[i + 1]); + rx_ring[i].bufptr = + virt_to_le32desc(&rxb[i * REAL_RX_BUF_SIZE]); + rx_ring[i].cmdsts = cpu_to_le32(REAL_RX_BUF_SIZE); + rx_ring[i].extsts = cpu_to_le32(0); + } +// No need to wrap the ring +// rx_ring[i].link = virt_to_le32desc(&rx_ring[0]); + writel(0, ns->base + RXDP_HI); + writel(virt_to_le32desc(&rx_ring[0]), ns->base + RXDP); + + dprintf(("starting receiver\n")); + + writel(0x0001, ns->base + CCSR); + writel(0, ns->base + RFCR); + writel(0x7fc00000, ns->base + RFCR); + writel(0xffc00000, ns->base + RFCR); + + ns->up = 1; + + phy_intr(nic); + + /* Okay, let it rip */ + ns->IMR_cache |= ISR_PHY; + ns->IMR_cache |= ISR_RXRCMP; + //dev->IMR_cache |= ISR_RXERR; + //dev->IMR_cache |= ISR_RXOK; + ns->IMR_cache |= ISR_RXORN; + ns->IMR_cache |= ISR_RXSOVR; + ns->IMR_cache |= ISR_RXDESC; + ns->IMR_cache |= ISR_RXIDLE; + ns->IMR_cache |= ISR_TXDESC; + ns->IMR_cache |= ISR_TXIDLE; + + // No reason to enable interupts... + // writel(ns->IMR_cache, ns->base + IMR); + // writel(1, ns->base + IER); + ns83820_set_multicast(nic); + kick_rx(); +} + + +static void ns83820_do_reset(struct nic *nic __unused, u32 which) +{ + dprintf(("resetting chip...\n")); + writel(which, ns->base + CR); + do { + + } while (readl(ns->base + CR) & which); + dprintf(("okay!\n")); +} + +static void ns83820_reset(struct nic *nic) +{ + unsigned i; + dprintf(("ns83820_reset\n")); + + writel(0, ns->base + PQCR); + + ns83820_setup_rx(nic); + + for (i = 0; i < NR_TX_DESC; i++) { + tx_ring[i].link = 0; + tx_ring[i].bufptr = 0; + tx_ring[i].cmdsts = cpu_to_le32(0); + tx_ring[i].extsts = cpu_to_le32(0); + } + + ns->tx_idx = 0; + ns->tx_done_idx = 0; + writel(0, ns->base + TXDP_HI); + return; +} +static void ns83820_getmac(struct nic *nic __unused, u8 * mac) +{ + unsigned i; + for (i = 0; i < 3; i++) { + u32 data; + /* Read from the perfect match memory: this is loaded by + * the chip from the EEPROM via the EELOAD self test. + */ + writel(i * 2, ns->base + RFCR); + data = readl(ns->base + RFDR); + *mac++ = data; + *mac++ = data >> 8; + } +} + +static void ns83820_set_multicast(struct nic *nic __unused) +{ + u8 *rfcr = ns->base + RFCR; + u32 and_mask = 0xffffffff; + u32 or_mask = 0; + u32 val; + + /* Support Multicast */ + and_mask &= ~(RFCR_AAU | RFCR_AAM); + or_mask |= RFCR_AAM; + val = (readl(rfcr) & and_mask) | or_mask; + /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */ + writel(val & ~RFCR_RFEN, rfcr); + writel(val, rfcr); + +} +static void ns83820_run_bist(struct nic *nic __unused, const char *name, + u32 enable, u32 done, u32 fail) +{ + int timed_out = 0; + long start; + u32 status; + int loops = 0; + + dprintf(("start %s\n", name)) + + start = currticks(); + + writel(enable, ns->base + PTSCR); + for (;;) { + loops++; + status = readl(ns->base + PTSCR); + if (!(status & enable)) + break; + if (status & done) + break; + if (status & fail) + break; + if ((currticks() - start) >= HZ) { + timed_out = 1; + break; + } + } + + if (status & fail) + printf("%s failed! (0x%hX & 0x%hX)\n", name, (unsigned int) status, + (unsigned int) fail); + else if (timed_out) + printf("run_bist %s timed out! (%hX)\n", name, (unsigned int) status); + dprintf(("done %s in %d loops\n", name, loops)); +} + +/************************************* +Check Link +*************************************/ +static void ns83820_check_intr(struct nic *nic) { + int i; + u32 isr = readl(ns->base + ISR); + if(ISR_PHY & isr) + phy_intr(nic); + if(( ISR_RXIDLE | ISR_RXDESC | ISR_RXERR) & isr) + kick_rx(); + for (i = 0; i < NR_RX_DESC; i++) { + if (rx_ring[i].cmdsts == CMDSTS_OWN) { +// rx_ring[i].link = virt_to_le32desc(&rx_ring[i + 1]); + rx_ring[i].cmdsts = cpu_to_le32(REAL_RX_BUF_SIZE); + } + } +} +/************************************************************************** +POLL - Wait for a frame +***************************************************************************/ +static int ns83820_poll(struct nic *nic, int retrieve) +{ + /* return true if there's an ethernet packet ready to read */ + /* nic->packet should contain data on return */ + /* nic->packetlen should contain length of data */ + u32 cmdsts; + int entry = ns->cur_rx; + + ns83820_check_intr(nic); + + cmdsts = le32_to_cpu(rx_ring[entry].cmdsts); + + if ( ! ( (CMDSTS_OWN & (cmdsts)) && (cmdsts != (CMDSTS_OWN)) ) ) + return 0; + + if ( ! retrieve ) return 1; + + if (! (CMDSTS_OK & cmdsts) ) + return 0; + + nic->packetlen = cmdsts & 0xffff; + memcpy(nic->packet, + rxb + (entry * REAL_RX_BUF_SIZE), + nic->packetlen); + // rx_ring[entry].link = 0; + rx_ring[entry].cmdsts = cpu_to_le32(CMDSTS_OWN); + + ns->cur_rx = ++ns->cur_rx % NR_RX_DESC; + + if (ns->cur_rx == 0) /* We have wrapped the ring */ + kick_rx(); + + return 1; +} + +static inline void kick_tx(struct nic *nic __unused) +{ + dprintf(("kick_tx\n")); + writel(CR_TXE, ns->base + CR); +} + +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static void ns83820_transmit(struct nic *nic, const char *d, /* Destination */ + unsigned int t, /* Type */ + unsigned int s, /* size */ + const char *p) +{ /* Packet */ + /* send the packet to destination */ + + u16 nstype; + u32 cmdsts, extsts; + int cur_tx = 0; + u32 isr = readl(ns->base + ISR); + if (ISR_TXIDLE & isr) + kick_tx(nic); + /* point to the current txb incase multiple tx_rings are used */ + memcpy(txb, d, ETH_ALEN); + memcpy(txb + ETH_ALEN, nic->node_addr, ETH_ALEN); + nstype = htons((u16) t); + memcpy(txb + 2 * ETH_ALEN, (u8 *) & nstype, 2); + memcpy(txb + ETH_HLEN, p, s); + s += ETH_HLEN; + s &= 0x0FFF; + while (s < ETH_ZLEN) + txb[s++] = '\0'; + + /* Setup the transmit descriptor */ + extsts = 0; + extsts |= EXTSTS_UDPPKT; + + tx_ring[cur_tx].bufptr = virt_to_le32desc(&txb); + tx_ring[cur_tx].extsts = cpu_to_le32(extsts); + + cmdsts = cpu_to_le32(0); + cmdsts |= cpu_to_le32(CMDSTS_OWN | s); + tx_ring[cur_tx].cmdsts = cpu_to_le32(cmdsts); + + writel(virt_to_le32desc(&tx_ring[0]), ns->base + TXDP); + kick_tx(nic); +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void ns83820_disable ( struct nic *nic ) { + + /* put the card in its initial state */ + /* This function serves 3 purposes. + * This disables DMA and interrupts so we don't receive + * unexpected packets or interrupts from the card after + * etherboot has finished. + * This frees resources so etherboot may use + * this driver on another interface + * This allows etherboot to reinitialize the interface + * if something is something goes wrong. + */ + /* disable interrupts */ + writel(0, ns->base + IMR); + writel(0, ns->base + IER); + readl(ns->base + IER); + + ns->up = 0; + + ns83820_do_reset(nic, CR_RST); + + ns->IMR_cache &= + ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | + ISR_RXIDLE); + writel(ns->IMR_cache, ns->base + IMR); + + /* touch the pci bus... */ + readl(ns->base + IMR); + + /* assumes the transmitter is already disabled and reset */ + writel(0, ns->base + RXDP_HI); + writel(0, ns->base + RXDP); +} + +/************************************************************************** +IRQ - Enable, Disable, or Force interrupts +***************************************************************************/ +static void ns83820_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + +static struct nic_operations ns83820_operations = { + .connect = dummy_connect, + .poll = ns83820_poll, + .transmit = ns83820_transmit, + .irq = ns83820_irq, + +}; + +static struct pci_device_id ns83820_nics[] = { + PCI_ROM(0x100b, 0x0022, "ns83820", "National Semiconductor 83820", 0), +}; + +PCI_DRIVER ( ns83820_driver, ns83820_nics, PCI_NO_CLASS ); + +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +***************************************************************************/ + +#define board_found 1 +#define valid_link 0 +static int ns83820_probe ( struct nic *nic, struct pci_device *pci ) { + + long addr; + int using_dac = 0; + + if (pci->ioaddr == 0) + return 0; + + printf("ns83820.c: vendor=0x%hX, device=0x%hX\n", + pci->vendor, pci->device); + + /* point to private storage */ + ns = &nsx; + + adjust_pci_device(pci); + + addr = pci_bar_start(pci, PCI_BASE_ADDRESS_1); + + ns->base = ioremap(addr, (1UL << 12)); + + if (!ns->base) + return 0; + + nic->irqno = 0; + nic->ioaddr = pci->ioaddr & ~3; + + /* disable interrupts */ + writel(0, ns->base + IMR); + writel(0, ns->base + IER); + readl(ns->base + IER); + + ns->IMR_cache = 0; + + ns83820_do_reset(nic, CR_RST); + + /* Must reset the ram bist before running it */ + writel(PTSCR_RBIST_RST, ns->base + PTSCR); + ns83820_run_bist(nic, "sram bist", PTSCR_RBIST_EN, + PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL); + ns83820_run_bist(nic, "eeprom bist", PTSCR_EEBIST_EN, 0, + PTSCR_EEBIST_FAIL); + ns83820_run_bist(nic, "eeprom load", PTSCR_EELOAD_EN, 0, 0); + + /* I love config registers */ + ns->CFG_cache = readl(ns->base + CFG); + + if ((ns->CFG_cache & CFG_PCI64_DET)) { + printf("detected 64 bit PCI data bus.\n"); + /*dev->CFG_cache |= CFG_DATA64_EN; */ + if (!(ns->CFG_cache & CFG_DATA64_EN)) + printf + ("EEPROM did not enable 64 bit bus. Disabled.\n"); + } else + ns->CFG_cache &= ~(CFG_DATA64_EN); + + ns->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS | + CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 | + CFG_M64ADDR); + ns->CFG_cache |= + CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS | + CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL; + ns->CFG_cache |= CFG_REQALG; + ns->CFG_cache |= CFG_POW; + ns->CFG_cache |= CFG_TMRTEST; + + /* When compiled with 64 bit addressing, we must always enable + * the 64 bit descriptor format. + */ +#ifdef USE_64BIT_ADDR + ns->CFG_cache |= CFG_M64ADDR; +#endif + +//FIXME: Enable section on dac or remove this + if (using_dac) + ns->CFG_cache |= CFG_T64ADDR; + + /* Big endian mode does not seem to do what the docs suggest */ + ns->CFG_cache &= ~CFG_BEM; + + /* setup optical transceiver if we have one */ + if (ns->CFG_cache & CFG_TBI_EN) { + dprintf(("%s: enabling optical transceiver\n", pci->driver_name)); + writel(readl(ns->base + GPIOR) | 0x3e8, ns->base + GPIOR); + + /* setup auto negotiation feature advertisement */ + writel(readl(ns->base + TANAR) + | TANAR_HALF_DUP | TANAR_FULL_DUP, + ns->base + TANAR); + + /* start auto negotiation */ + writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN, + ns->base + TBICR); + writel(TBICR_MR_AN_ENABLE, ns->base + TBICR); + ns->linkstate = LINK_AUTONEGOTIATE; + + ns->CFG_cache |= CFG_MODE_1000; + } + writel(ns->CFG_cache, ns->base + CFG); + dprintf(("CFG: %hX\n", ns->CFG_cache)); + + /* FIXME: reset_phy is defaulted to 0, should we reset anyway? */ + if (reset_phy) { + dprintf(("%s: resetting phy\n", pci->driver_name)); + writel(ns->CFG_cache | CFG_PHY_RST, ns->base + CFG); + writel(ns->CFG_cache, ns->base + CFG); + } +#if 0 /* Huh? This sets the PCI latency register. Should be done via + * the PCI layer. FIXME. + */ + if (readl(dev->base + SRR)) + writel(readl(dev->base + 0x20c) | 0xfe00, + dev->base + 0x20c); +#endif + + /* Note! The DMA burst size interacts with packet + * transmission, such that the largest packet that + * can be transmitted is 8192 - FLTH - burst size. + * If only the transmit fifo was larger... + */ + /* Ramit : 1024 DMA is not a good idea, it ends up banging + * some DELL and COMPAQ SMP systems */ + writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512 + | ((1600 / 32) * 0x100), ns->base + TXCFG); + + /* Set Rx to full duplex, don't accept runt, errored, long or length + * range errored packets. Use 512 byte DMA. + */ + /* Ramit : 1024 DMA is not a good idea, it ends up banging + * some DELL and COMPAQ SMP systems + * Turn on ALP, only we are accpeting Jumbo Packets */ + writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD + | RXCFG_STRIPCRC + //| RXCFG_ALP + | (RXCFG_MXDMA512) | 0, ns->base + RXCFG); + + /* Disable priority queueing */ + writel(0, ns->base + PQCR); + + /* Enable IP checksum validation and detetion of VLAN headers. + * Note: do not set the reject options as at least the 0x102 + * revision of the chip does not properly accept IP fragments + * at least for UDP. + */ + /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since + * the MAC it calculates the packetsize AFTER stripping the VLAN + * header, and if a VLAN Tagged packet of 64 bytes is received (like + * a ping with a VLAN header) then the card, strips the 4 byte VLAN + * tag and then checks the packet size, so if RXCFG_ARP is not enabled, + * it discrards it!. These guys...... + */ + writel(VRCR_IPEN | VRCR_VTDEN, ns->base + VRCR); + + /* Enable per-packet TCP/UDP/IP checksumming */ + writel(VTCR_PPCHK, ns->base + VTCR); + + /* Ramit : Enable async and sync pause frames */ +// writel(0, ns->base + PCR); + writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K | + PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT), + ns->base + PCR); + + /* Disable Wake On Lan */ + writel(0, ns->base + WCSR); + + ns83820_getmac(nic, nic->node_addr); + + if (using_dac) { + dprintf(("%s: using 64 bit addressing.\n", pci->driver_name)); + } + + dprintf(("%s: DP83820 %d.%d: %! io=0x%hX\n", + pci->driver_name, + (unsigned) readl(ns->base + SRR) >> 8, + (unsigned) readl(ns->base + SRR) & 0xff, + nic->node_addr, pci->ioaddr)); + +#ifdef PHY_CODE_IS_FINISHED + ns83820_probe_phy(dev); +#endif + + ns83820_reset(nic); + /* point to NIC specific routines */ + nic->nic_op = &ns83820_operations; + return 1; +} + +DRIVER ( "NS83820/PCI", nic_driver, pci_driver, ns83820_driver, + ns83820_probe, ns83820_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ns8390.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/ns8390.c new file mode 100644 index 0000000..97f1141 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ns8390.c @@ -0,0 +1,1037 @@ +/************************************************************************** +ETHERBOOT - BOOTP/TFTP Bootstrap Program + +Author: Martin Renters + Date: May/94 + + This code is based heavily on David Greenman's if_ed.c driver + + Copyright (C) 1993-1994, David Greenman, Martin Renters. + This software may be used, modified, copied, distributed, and sold, in + both source and binary form provided that the above copyright and these + terms are retained. Under no circumstances are the authors responsible for + the proper functioning of this software, nor do the authors assume any + responsibility for damages incurred with its use. + +Multicast support added by Timothy Legge (timlegge@users.sourceforge.net) 09/28/2003 +Relocation support added by Ken Yap (ken_yap@users.sourceforge.net) 28/12/02 +3c503 support added by Bill Paul (wpaul@ctr.columbia.edu) on 11/15/94 +SMC8416 support added by Bill Paul (wpaul@ctr.columbia.edu) on 12/25/94 +3c503 PIO support added by Jim Hague (jim.hague@acm.org) on 2/17/98 +RX overrun by Klaus Espenlaub (espenlaub@informatik.uni-ulm.de) on 3/10/99 + parts taken from the Linux 8390 driver (by Donald Becker and Paul Gortmaker) +SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02 + based on the Linux 8390 driver (by Donald Becker and Paul Gortmaker) + +**************************************************************************/ + +FILE_LICENCE ( BSD2 ); + +/* #warning "ns8390.c: FIXME: split ISA and PCI, clean up" */ + +#if 1 + +#if !defined(INCLUDE_NS8390) && !defined(INCLUDE_WD) && \ + !defined(INCLUDE_NE) && !defined(INCLUDE_3C503) + /* The driver named ns8390 is the PCI driver, often called + "PCI ne2000 clones". */ +# define INCLUDE_NS8390 1 +#endif + +#include "etherboot.h" +#include "nic.h" +#include "ns8390.h" +#include <gpxe/ethernet.h> +#ifdef INCLUDE_NS8390 +#include <gpxe/pci.h> +#else +#include <gpxe/isa.h> +#endif + +static unsigned char eth_vendor, eth_flags; +#ifdef INCLUDE_WD +static unsigned char eth_laar; +#endif +static unsigned short eth_nic_base, eth_asic_base; +static unsigned char eth_memsize, eth_rx_start, eth_tx_start; +static Address eth_bmem, eth_rmem; +static unsigned char eth_drain_receiver; + +#ifdef INCLUDE_WD +static struct wd_board { + const char *name; + char id; + char flags; + char memsize; +} wd_boards[] = { + {"WD8003S", TYPE_WD8003S, 0, MEM_8192}, + {"WD8003E", TYPE_WD8003E, 0, MEM_8192}, + {"WD8013EBT", TYPE_WD8013EBT, FLAG_16BIT, MEM_16384}, + {"WD8003W", TYPE_WD8003W, 0, MEM_8192}, + {"WD8003EB", TYPE_WD8003EB, 0, MEM_8192}, + {"WD8013W", TYPE_WD8013W, FLAG_16BIT, MEM_16384}, + {"WD8003EP/WD8013EP", + TYPE_WD8013EP, 0, MEM_8192}, + {"WD8013WC", TYPE_WD8013WC, FLAG_16BIT, MEM_16384}, + {"WD8013EPC", TYPE_WD8013EPC, FLAG_16BIT, MEM_16384}, + {"SMC8216T", TYPE_SMC8216T, FLAG_16BIT | FLAG_790, MEM_16384}, + {"SMC8216C", TYPE_SMC8216C, FLAG_16BIT | FLAG_790, MEM_16384}, + {"SMC8416T", TYPE_SMC8416T, FLAG_16BIT | FLAG_790, MEM_8192}, + {"SMC8416C/BT", TYPE_SMC8416C, FLAG_16BIT | FLAG_790, MEM_8192}, + {"SMC8013EBP", TYPE_SMC8013EBP,FLAG_16BIT, MEM_16384}, + {NULL, 0, 0, 0} +}; +#endif + +#ifdef INCLUDE_3C503 +static unsigned char t503_output; /* AUI or internal xcvr (Thinnet) */ +#endif + +#if defined(INCLUDE_WD) +#define ASIC_PIO WD_IAR +#define eth_probe wd_probe +#if defined(INCLUDE_3C503) || defined(INCLUDE_NE) || defined(INCLUDE_NS8390) +Error you must only define one of INCLUDE_WD, INCLUDE_3C503, INCLUDE_NE, INCLUDE_NS8390 +#endif +#endif + +#if defined(INCLUDE_3C503) +#define eth_probe t503_probe +#if defined(INCLUDE_NE) || defined(INCLUDE_NS8390) || defined(INCLUDE_WD) +Error you must only define one of INCLUDE_WD, INCLUDE_3C503, INCLUDE_NE, INCLUDE_NS8390 +#endif +#endif + +#if defined(INCLUDE_NE) +#define eth_probe ne_probe +#if defined(INCLUDE_NS8390) || defined(INCLUDE_3C503) || defined(INCLUDE_WD) +Error you must only define one of INCLUDE_WD, INCLUDE_3C503, INCLUDE_NE, INCLUDE_NS8390 +#endif +#endif + +#if defined(INCLUDE_NS8390) +#define eth_probe nepci_probe +#if defined(INCLUDE_NE) || defined(INCLUDE_3C503) || defined(INCLUDE_WD) +Error you must only define one of INCLUDE_WD, INCLUDE_3C503, INCLUDE_NE, INCLUDE_NS8390 +#endif +#endif + +#if defined(INCLUDE_3C503) +#define ASIC_PIO _3COM_RFMSB +#else +#if defined(INCLUDE_NE) || defined(INCLUDE_NS8390) +#define ASIC_PIO NE_DATA +#endif +#endif + +#if defined(INCLUDE_NE) || defined(INCLUDE_NS8390) || (defined(INCLUDE_3C503) && !defined(T503_SHMEM)) || (defined(INCLUDE_WD) && defined(WD_790_PIO)) +/************************************************************************** +ETH_PIO_READ - Read a frame via Programmed I/O +**************************************************************************/ +static void eth_pio_read(unsigned int src, unsigned char *dst, unsigned int cnt) +{ +#ifdef INCLUDE_WD + outb(src & 0xff, eth_asic_base + WD_GP2); + outb(src >> 8, eth_asic_base + WD_GP2); +#else + outb(D8390_COMMAND_RD2 | + D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + outb(cnt, eth_nic_base + D8390_P0_RBCR0); + outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1); + outb(src, eth_nic_base + D8390_P0_RSAR0); + outb(src>>8, eth_nic_base + D8390_P0_RSAR1); + outb(D8390_COMMAND_RD0 | + D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + +#ifdef INCLUDE_3C503 + outb(src & 0xff, eth_asic_base + _3COM_DALSB); + outb(src >> 8, eth_asic_base + _3COM_DAMSB); + outb(t503_output | _3COM_CR_START, eth_asic_base + _3COM_CR); +#endif +#endif + + if (eth_flags & FLAG_16BIT) + cnt = (cnt + 1) >> 1; + + while(cnt--) { +#ifdef INCLUDE_3C503 + while((inb(eth_asic_base + _3COM_STREG) & _3COM_STREG_DPRDY) == 0) + ; +#endif + + if (eth_flags & FLAG_16BIT) { + *((unsigned short *)dst) = inw(eth_asic_base + ASIC_PIO); + dst += 2; + } + else + *(dst++) = inb(eth_asic_base + ASIC_PIO); + } + +#ifdef INCLUDE_3C503 + outb(t503_output, eth_asic_base + _3COM_CR); +#endif +} + +/************************************************************************** +ETH_PIO_WRITE - Write a frame via Programmed I/O +**************************************************************************/ +static void eth_pio_write(const unsigned char *src, unsigned int dst, unsigned int cnt) +{ +#ifdef COMPEX_RL2000_FIX + unsigned int x; +#endif /* COMPEX_RL2000_FIX */ +#ifdef INCLUDE_WD + outb(dst & 0xff, eth_asic_base + WD_GP2); + outb(dst >> 8, eth_asic_base + WD_GP2); +#else + outb(D8390_COMMAND_RD2 | + D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR); + outb(cnt, eth_nic_base + D8390_P0_RBCR0); + outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1); + outb(dst, eth_nic_base + D8390_P0_RSAR0); + outb(dst>>8, eth_nic_base + D8390_P0_RSAR1); + outb(D8390_COMMAND_RD1 | + D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + +#ifdef INCLUDE_3C503 + outb(dst & 0xff, eth_asic_base + _3COM_DALSB); + outb(dst >> 8, eth_asic_base + _3COM_DAMSB); + + outb(t503_output | _3COM_CR_DDIR | _3COM_CR_START, eth_asic_base + _3COM_CR); +#endif +#endif + + if (eth_flags & FLAG_16BIT) + cnt = (cnt + 1) >> 1; + + while(cnt--) + { +#ifdef INCLUDE_3C503 + while((inb(eth_asic_base + _3COM_STREG) & _3COM_STREG_DPRDY) == 0) + ; +#endif + + if (eth_flags & FLAG_16BIT) { + outw(*((unsigned short *)src), eth_asic_base + ASIC_PIO); + src += 2; + } + else + outb(*(src++), eth_asic_base + ASIC_PIO); + } + +#ifdef INCLUDE_3C503 + outb(t503_output, eth_asic_base + _3COM_CR); +#else +#ifdef COMPEX_RL2000_FIX + for (x = 0; + x < COMPEX_RL2000_TRIES && + (inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC) + != D8390_ISR_RDC; + ++x); + if (x >= COMPEX_RL2000_TRIES) + printf("Warning: Compex RL2000 aborted wait!\n"); +#endif /* COMPEX_RL2000_FIX */ +#ifndef INCLUDE_WD + while((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC) + != D8390_ISR_RDC); +#endif +#endif +} +#else +/************************************************************************** +ETH_PIO_READ - Dummy routine when NE2000 not compiled in +**************************************************************************/ +static void eth_pio_read(unsigned int src __unused, unsigned char *dst __unused, unsigned int cnt __unused) {} +#endif + + +/************************************************************************** +enable_multycast - Enable Multicast +**************************************************************************/ +static void enable_multicast(unsigned short eth_nic_base) +{ + unsigned char mcfilter[8]; + int i; + memset(mcfilter, 0xFF, 8); + outb(4, eth_nic_base+D8390_P0_RCR); + outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS1, eth_nic_base + D8390_P0_COMMAND); + for(i=0;i<8;i++) + { + outb(mcfilter[i], eth_nic_base + 8 + i); + if(inb(eth_nic_base + 8 + i)!=mcfilter[i]) + printf("Error SMC 83C690 Multicast filter read/write mishap %d\n",i); + } + outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS0, eth_nic_base + D8390_P0_COMMAND); + outb(4 | 0x08, eth_nic_base+D8390_P0_RCR); +} + +/************************************************************************** +NS8390_RESET - Reset adapter +**************************************************************************/ +static void ns8390_reset(struct nic *nic) +{ + int i; + + eth_drain_receiver = 0; +#ifdef INCLUDE_WD + if (eth_flags & FLAG_790) + outb(D8390_COMMAND_PS0 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND); + else +#endif + outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | + D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND); + if (eth_flags & FLAG_16BIT) + outb(0x49, eth_nic_base+D8390_P0_DCR); + else + outb(0x48, eth_nic_base+D8390_P0_DCR); + outb(0, eth_nic_base+D8390_P0_RBCR0); + outb(0, eth_nic_base+D8390_P0_RBCR1); + outb(0x20, eth_nic_base+D8390_P0_RCR); /* monitor mode */ + outb(2, eth_nic_base+D8390_P0_TCR); + outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR); + outb(eth_rx_start, eth_nic_base+D8390_P0_PSTART); +#ifdef INCLUDE_WD + if (eth_flags & FLAG_790) { +#ifdef WD_790_PIO + outb(0x10, eth_asic_base + 0x06); /* disable interrupts, enable PIO */ + outb(0x01, eth_nic_base + 0x09); /* enable ring read auto-wrap */ +#else + outb(0, eth_nic_base + 0x09); +#endif + } +#endif + outb(eth_memsize, eth_nic_base+D8390_P0_PSTOP); + outb(eth_memsize - 1, eth_nic_base+D8390_P0_BOUND); + outb(0xFF, eth_nic_base+D8390_P0_ISR); + outb(0, eth_nic_base+D8390_P0_IMR); +#ifdef INCLUDE_WD + if (eth_flags & FLAG_790) + outb(D8390_COMMAND_PS1 | + D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND); + else +#endif + outb(D8390_COMMAND_PS1 | + D8390_COMMAND_RD2 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND); + for (i=0; i<ETH_ALEN; i++) + outb(nic->node_addr[i], eth_nic_base+D8390_P1_PAR0+i); + for (i=0; i<ETH_ALEN; i++) + outb(0xFF, eth_nic_base+D8390_P1_MAR0+i); + outb(eth_rx_start, eth_nic_base+D8390_P1_CURR); +#ifdef INCLUDE_WD + if (eth_flags & FLAG_790) + outb(D8390_COMMAND_PS0 | + D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND); + else +#endif + outb(D8390_COMMAND_PS0 | + D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND); + outb(0xFF, eth_nic_base+D8390_P0_ISR); + outb(0, eth_nic_base+D8390_P0_TCR); /* transmitter on */ + outb(4, eth_nic_base+D8390_P0_RCR); /* allow rx broadcast frames */ + + enable_multicast(eth_nic_base); + +#ifdef INCLUDE_3C503 + /* + * No way to tell whether or not we're supposed to use + * the 3Com's transceiver unless the user tells us. + * 'flags' should have some compile time default value + * which can be changed from the command menu. + */ + t503_output = (nic->flags) ? 0 : _3COM_CR_XSEL; + outb(t503_output, eth_asic_base + _3COM_CR); +#endif +} + +static int ns8390_poll(struct nic *nic, int retrieve); + +#ifndef INCLUDE_3C503 +/************************************************************************** +ETH_RX_OVERRUN - Bring adapter back to work after an RX overrun +**************************************************************************/ +static void eth_rx_overrun(struct nic *nic) +{ + int start_time; + +#ifdef INCLUDE_WD + if (eth_flags & FLAG_790) + outb(D8390_COMMAND_PS0 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND); + else +#endif + outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | + D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND); + + /* wait for at least 1.6ms - we wait one timer tick */ + start_time = currticks(); + while (currticks() - start_time <= 1) + /* Nothing */; + + outb(0, eth_nic_base+D8390_P0_RBCR0); /* reset byte counter */ + outb(0, eth_nic_base+D8390_P0_RBCR1); + + /* + * Linux driver checks for interrupted TX here. This is not necessary, + * because the transmit routine waits until the frame is sent. + */ + + /* enter loopback mode and restart NIC */ + outb(2, eth_nic_base+D8390_P0_TCR); +#ifdef INCLUDE_WD + if (eth_flags & FLAG_790) + outb(D8390_COMMAND_PS0 | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND); + else +#endif + outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | + D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND); + + /* clear the RX ring, acknowledge overrun interrupt */ + eth_drain_receiver = 1; + while (ns8390_poll(nic, 1)) + /* Nothing */; + eth_drain_receiver = 0; + outb(D8390_ISR_OVW, eth_nic_base+D8390_P0_ISR); + + /* leave loopback mode - no packets to be resent (see Linux driver) */ + outb(0, eth_nic_base+D8390_P0_TCR); +} +#endif /* INCLUDE_3C503 */ + +/************************************************************************** +NS8390_TRANSMIT - Transmit a frame +**************************************************************************/ +static void ns8390_transmit( + struct nic *nic, + const char *d, /* Destination */ + unsigned int t, /* Type */ + unsigned int s, /* size */ + const char *p) /* Packet */ +{ +#if defined(INCLUDE_3C503) || (defined(INCLUDE_WD) && ! defined(WD_790_PIO)) + Address eth_vmem = bus_to_virt(eth_bmem); +#endif +#ifdef INCLUDE_3C503 + if (!(eth_flags & FLAG_PIO)) { + memcpy((char *)eth_vmem, d, ETH_ALEN); /* dst */ + memcpy((char *)eth_vmem+ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */ + *((char *)eth_vmem+12) = t>>8; /* type */ + *((char *)eth_vmem+13) = t; + memcpy((char *)eth_vmem+ETH_HLEN, p, s); + s += ETH_HLEN; + while (s < ETH_ZLEN) *((char *)eth_vmem+(s++)) = 0; + } +#endif + +#ifdef INCLUDE_WD + if (eth_flags & FLAG_16BIT) { + outb(eth_laar | WD_LAAR_M16EN, eth_asic_base + WD_LAAR); + inb(0x84); + } +#ifndef WD_790_PIO + /* Memory interface */ + if (eth_flags & FLAG_790) { + outb(WD_MSR_MENB, eth_asic_base + WD_MSR); + inb(0x84); + } + inb(0x84); + memcpy((char *)eth_vmem, d, ETH_ALEN); /* dst */ + memcpy((char *)eth_vmem+ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */ + *((char *)eth_vmem+12) = t>>8; /* type */ + *((char *)eth_vmem+13) = t; + memcpy((char *)eth_vmem+ETH_HLEN, p, s); + s += ETH_HLEN; + while (s < ETH_ZLEN) *((char *)eth_vmem+(s++)) = 0; + if (eth_flags & FLAG_790) { + outb(0, eth_asic_base + WD_MSR); + inb(0x84); + } +#else + inb(0x84); +#endif +#endif + +#if defined(INCLUDE_3C503) + if (eth_flags & FLAG_PIO) +#endif +#if defined(INCLUDE_NE) || defined(INCLUDE_NS8390) || (defined(INCLUDE_3C503) && !defined(T503_SHMEM)) || (defined(INCLUDE_WD) && defined(WD_790_PIO)) + { + /* Programmed I/O */ + unsigned short type; + type = (t >> 8) | (t << 8); + eth_pio_write( (unsigned char *) d, eth_tx_start<<8, ETH_ALEN); + eth_pio_write(nic->node_addr, (eth_tx_start<<8)+ETH_ALEN, ETH_ALEN); + /* bcc generates worse code without (const+const) below */ + eth_pio_write((unsigned char *)&type, (eth_tx_start<<8)+(ETH_ALEN+ETH_ALEN), 2); + eth_pio_write( (unsigned char *) p, (eth_tx_start<<8)+ETH_HLEN, s); + s += ETH_HLEN; + if (s < ETH_ZLEN) s = ETH_ZLEN; + } +#endif +#if defined(INCLUDE_3C503) +#endif + +#ifdef INCLUDE_WD + if (eth_flags & FLAG_16BIT) { + outb(eth_laar & ~WD_LAAR_M16EN, eth_asic_base + WD_LAAR); + inb(0x84); + } + if (eth_flags & FLAG_790) + outb(D8390_COMMAND_PS0 | + D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND); + else +#endif + outb(D8390_COMMAND_PS0 | + D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND); + outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR); + outb(s, eth_nic_base+D8390_P0_TBCR0); + outb(s>>8, eth_nic_base+D8390_P0_TBCR1); +#ifdef INCLUDE_WD + if (eth_flags & FLAG_790) + outb(D8390_COMMAND_PS0 | + D8390_COMMAND_TXP | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND); + else +#endif + outb(D8390_COMMAND_PS0 | + D8390_COMMAND_TXP | D8390_COMMAND_RD2 | + D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND); +} + +/************************************************************************** +NS8390_POLL - Wait for a frame +**************************************************************************/ +static int ns8390_poll(struct nic *nic, int retrieve) +{ + int ret = 0; + unsigned char rstat, curr, next; + unsigned short len, frag; + unsigned short pktoff; + unsigned char *p; + struct ringbuffer pkthdr; + +#ifndef INCLUDE_3C503 + /* avoid infinite recursion: see eth_rx_overrun() */ + if (!eth_drain_receiver && (inb(eth_nic_base+D8390_P0_ISR) & D8390_ISR_OVW)) { + eth_rx_overrun(nic); + return(0); + } +#endif /* INCLUDE_3C503 */ + rstat = inb(eth_nic_base+D8390_P0_RSR); + if (!(rstat & D8390_RSTAT_PRX)) return(0); + next = inb(eth_nic_base+D8390_P0_BOUND)+1; + if (next >= eth_memsize) next = eth_rx_start; + outb(D8390_COMMAND_PS1, eth_nic_base+D8390_P0_COMMAND); + curr = inb(eth_nic_base+D8390_P1_CURR); + outb(D8390_COMMAND_PS0, eth_nic_base+D8390_P0_COMMAND); + if (curr >= eth_memsize) curr=eth_rx_start; + if (curr == next) return(0); + + if ( ! retrieve ) return 1; + +#ifdef INCLUDE_WD + if (eth_flags & FLAG_16BIT) { + outb(eth_laar | WD_LAAR_M16EN, eth_asic_base + WD_LAAR); + inb(0x84); + } +#ifndef WD_790_PIO + if (eth_flags & FLAG_790) { + outb(WD_MSR_MENB, eth_asic_base + WD_MSR); + inb(0x84); + } +#endif + inb(0x84); +#endif + pktoff = next << 8; + if (eth_flags & FLAG_PIO) + eth_pio_read(pktoff, (unsigned char *)&pkthdr, 4); + else + memcpy(&pkthdr, bus_to_virt(eth_rmem + pktoff), 4); + pktoff += sizeof(pkthdr); + /* incoming length includes FCS so must sub 4 */ + len = pkthdr.len - 4; + if ((pkthdr.status & D8390_RSTAT_PRX) == 0 || len < ETH_ZLEN + || len > ETH_FRAME_LEN) { + printf("Bogus packet, ignoring\n"); + return (0); + } + else { + p = nic->packet; + nic->packetlen = len; /* available to caller */ + frag = (eth_memsize << 8) - pktoff; + if (len > frag) { /* We have a wrap-around */ + /* read first part */ + if (eth_flags & FLAG_PIO) + eth_pio_read(pktoff, p, frag); + else + memcpy(p, bus_to_virt(eth_rmem + pktoff), frag); + pktoff = eth_rx_start << 8; + p += frag; + len -= frag; + } + /* read second part */ + if (eth_flags & FLAG_PIO) + eth_pio_read(pktoff, p, len); + else + memcpy(p, bus_to_virt(eth_rmem + pktoff), len); + ret = 1; + } +#ifdef INCLUDE_WD +#ifndef WD_790_PIO + if (eth_flags & FLAG_790) { + outb(0, eth_asic_base + WD_MSR); + inb(0x84); + } +#endif + if (eth_flags & FLAG_16BIT) { + outb(eth_laar & ~WD_LAAR_M16EN, eth_asic_base + WD_LAAR); + inb(0x84); + } + inb(0x84); +#endif + next = pkthdr.next; /* frame number of next packet */ + if (next == eth_rx_start) + next = eth_memsize; + outb(next-1, eth_nic_base+D8390_P0_BOUND); + return(ret); +} + +/************************************************************************** +NS8390_DISABLE - Turn off adapter +**************************************************************************/ +static void ns8390_disable ( struct nic *nic ) { + ns8390_reset(nic); +} + +/************************************************************************** +NS8390_IRQ - Enable, Disable, or Force interrupts +**************************************************************************/ +static void ns8390_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + +static struct nic_operations ns8390_operations; +static struct nic_operations ns8390_operations = { + .connect = dummy_connect, + .poll = ns8390_poll, + .transmit = ns8390_transmit, + .irq = ns8390_irq, +}; + +/************************************************************************** +ETH_PROBE - Look for an adapter +**************************************************************************/ +#ifdef INCLUDE_NS8390 +static int eth_probe (struct nic *nic, struct pci_device *pci) +#else +static int eth_probe (struct dev *dev, unsigned short *probe_addrs __unused) +#endif +{ + int i; +#ifdef INCLUDE_NS8390 + unsigned short pci_probe_addrs[] = { pci->ioaddr, 0 }; + unsigned short *probe_addrs = pci_probe_addrs; +#endif + eth_vendor = VENDOR_NONE; + eth_drain_receiver = 0; + + nic->irqno = 0; + +#ifdef INCLUDE_WD +{ + /****************************************************************** + Search for WD/SMC cards + ******************************************************************/ + struct wd_board *brd; + unsigned short chksum; + unsigned char c; + for (eth_asic_base = WD_LOW_BASE; eth_asic_base <= WD_HIGH_BASE; + eth_asic_base += 0x20) { + chksum = 0; + for (i=8; i<16; i++) + chksum += inb(eth_asic_base+i); + /* Extra checks to avoid soundcard */ + if ((chksum & 0xFF) == 0xFF && + inb(eth_asic_base+8) != 0xFF && + inb(eth_asic_base+9) != 0xFF) + break; + } + if (eth_asic_base > WD_HIGH_BASE) + return (0); + /* We've found a board */ + eth_vendor = VENDOR_WD; + eth_nic_base = eth_asic_base + WD_NIC_ADDR; + + nic->ioaddr = eth_nic_base; + + c = inb(eth_asic_base+WD_BID); /* Get board id */ + for (brd = wd_boards; brd->name; brd++) + if (brd->id == c) break; + if (!brd->name) { + printf("Unknown WD/SMC NIC type %hhX\n", c); + return (0); /* Unknown type */ + } + eth_flags = brd->flags; + eth_memsize = brd->memsize; + eth_tx_start = 0; + eth_rx_start = D8390_TXBUF_SIZE; + if ((c == TYPE_WD8013EP) && + (inb(eth_asic_base + WD_ICR) & WD_ICR_16BIT)) { + eth_flags = FLAG_16BIT; + eth_memsize = MEM_16384; + } + if ((c & WD_SOFTCONFIG) && (!(eth_flags & FLAG_790))) { + eth_bmem = (0x80000 | + ((inb(eth_asic_base + WD_MSR) & 0x3F) << 13)); + } else + eth_bmem = WD_DEFAULT_MEM; + if (brd->id == TYPE_SMC8216T || brd->id == TYPE_SMC8216C) { + /* from Linux driver, 8416BT detects as 8216 sometimes */ + unsigned int addr = inb(eth_asic_base + 0xb); + if (((addr >> 4) & 3) == 0) { + brd += 2; + eth_memsize = brd->memsize; + } + } + outb(0x80, eth_asic_base + WD_MSR); /* Reset */ + for (i=0; i<ETH_ALEN; i++) { + nic->node_addr[i] = inb(i+eth_asic_base+WD_LAR); + } + DBG ( "\n%s base %4.4x", brd->name, eth_asic_base ); + if (eth_flags & FLAG_790) { +#ifdef WD_790_PIO + DBG ( ", PIO mode, addr %s\n", eth_ntoa ( nic->node_addr ) ); + eth_bmem = 0; + eth_flags |= FLAG_PIO; /* force PIO mode */ + outb(0, eth_asic_base+WD_MSR); +#else + DBG ( ", Memory %x, MAC Addr %s\n", eth_bmem, eth_ntoa ( nic->node_addr) ); + + outb(WD_MSR_MENB, eth_asic_base+WD_MSR); + outb((inb(eth_asic_base+0x04) | + 0x80), eth_asic_base+0x04); + outb(((unsigned)(eth_bmem >> 13) & 0x0F) | + ((unsigned)(eth_bmem >> 11) & 0x40) | + (inb(eth_asic_base+0x0B) & 0xB0), eth_asic_base+0x0B); + outb((inb(eth_asic_base+0x04) & + ~0x80), eth_asic_base+0x04); +#endif + } else { + + DBG (", Memory %x, MAC Addr %s\n", eth_bmem, eth_ntoa ( nic->node_addr) ); + + outb(((unsigned)(eth_bmem >> 13) & 0x3F) | 0x40, eth_asic_base+WD_MSR); + } + if (eth_flags & FLAG_16BIT) { + if (eth_flags & FLAG_790) { + eth_laar = inb(eth_asic_base + WD_LAAR); + outb(WD_LAAR_M16EN, eth_asic_base + WD_LAAR); + } else { + outb((eth_laar = + WD_LAAR_L16EN | 1), eth_asic_base + WD_LAAR); +/* + The previous line used to be + WD_LAAR_M16EN | WD_LAAR_L16EN | 1)); + jluke@deakin.edu.au reported that removing WD_LAAR_M16EN made + it work for WD8013s. This seems to work for my 8013 boards. I + don't know what is really happening. I wish I had data sheets + or more time to decode the Linux driver. - Ken +*/ + } + inb(0x84); + } +} +#endif +#ifdef INCLUDE_3C503 +#ifdef T503_AUI + nic->flags = 1; /* aui */ +#else + nic->flags = 0; /* no aui */ +#endif + /****************************************************************** + Search for 3Com 3c503 if no WD/SMC cards + ******************************************************************/ + if (eth_vendor == VENDOR_NONE) { + int idx; + int iobase_reg, membase_reg; + static unsigned short base[] = { + 0x300, 0x310, 0x330, 0x350, + 0x250, 0x280, 0x2A0, 0x2E0, 0 }; + + /* Loop through possible addresses checking each one */ + + for (idx = 0; (eth_nic_base = base[idx]) != 0; ++idx) { + + eth_asic_base = eth_nic_base + _3COM_ASIC_OFFSET; +/* + * Note that we use the same settings for both 8 and 16 bit cards: + * both have an 8K bank of memory at page 1 while only the 16 bit + * cards have a bank at page 0. + */ + eth_memsize = MEM_16384; + eth_tx_start = 32; + eth_rx_start = 32 + D8390_TXBUF_SIZE; + + /* Check our base address. iobase and membase should */ + /* both have a maximum of 1 bit set or be 0. */ + + iobase_reg = inb(eth_asic_base + _3COM_BCFR); + membase_reg = inb(eth_asic_base + _3COM_PCFR); + + if ((iobase_reg & (iobase_reg - 1)) || + (membase_reg & (membase_reg - 1))) + continue; /* nope */ + + /* Now get the shared memory address */ + + eth_flags = 0; + + switch (membase_reg) { + case _3COM_PCFR_DC000: + eth_bmem = 0xdc000; + break; + case _3COM_PCFR_D8000: + eth_bmem = 0xd8000; + break; + case _3COM_PCFR_CC000: + eth_bmem = 0xcc000; + break; + case _3COM_PCFR_C8000: + eth_bmem = 0xc8000; + break; + case _3COM_PCFR_PIO: + eth_flags |= FLAG_PIO; + eth_bmem = 0; + break; + default: + continue; /* nope */ + } + break; + } + + if (base[idx] == 0) /* not found */ + return (0); +#ifndef T503_SHMEM + eth_flags |= FLAG_PIO; /* force PIO mode */ + eth_bmem = 0; +#endif + eth_vendor = VENDOR_3COM; + + + /* Need this to make ns8390_poll() happy. */ + + eth_rmem = eth_bmem - 0x2000; + + /* Reset NIC and ASIC */ + + outb(_3COM_CR_RST | _3COM_CR_XSEL, eth_asic_base + _3COM_CR ); + outb(_3COM_CR_XSEL, eth_asic_base + _3COM_CR ); + + /* Get our ethernet address */ + + outb(_3COM_CR_EALO | _3COM_CR_XSEL, eth_asic_base + _3COM_CR); + nic->ioaddr = eth_nic_base; + DBG ( "\n3Com 3c503 base %4.4x, ", eth_nic_base ); + if (eth_flags & FLAG_PIO) + DBG ( "PIO mode" ); + else + DBG ( "memory %4.4x", eth_bmem ); + for (i=0; i<ETH_ALEN; i++) { + nic->node_addr[i] = inb(eth_nic_base+i); + } + DBG ( ", %s, MAC Addr %s\n", nic->flags ? "AUI" : "internal xcvr", + eth_ntoa ( nic->node_addr ) ); + + outb(_3COM_CR_XSEL, eth_asic_base + _3COM_CR); + /* + * Initialize GA configuration register. Set bank and enable shared + * mem. We always use bank 1. Disable interrupts. + */ + outb(_3COM_GACFR_RSEL | + _3COM_GACFR_MBS0 | _3COM_GACFR_TCM | _3COM_GACFR_NIM, eth_asic_base + _3COM_GACFR); + + outb(0xff, eth_asic_base + _3COM_VPTR2); + outb(0xff, eth_asic_base + _3COM_VPTR1); + outb(0x00, eth_asic_base + _3COM_VPTR0); + /* + * Clear memory and verify that it worked (we use only 8K) + */ + + if (!(eth_flags & FLAG_PIO)) { + memset(bus_to_virt(eth_bmem), 0, 0x2000); + for(i = 0; i < 0x2000; ++i) + if (*((char *)(bus_to_virt(eth_bmem+i)))) { + printf ("Failed to clear 3c503 shared mem.\n"); + return (0); + } + } + /* + * Initialize GA page/start/stop registers. + */ + outb(eth_tx_start, eth_asic_base + _3COM_PSTR); + outb(eth_memsize, eth_asic_base + _3COM_PSPR); + } +#endif +#if defined(INCLUDE_NE) || defined(INCLUDE_NS8390) +{ + /****************************************************************** + Search for NE1000/2000 if no WD/SMC or 3com cards + ******************************************************************/ + unsigned char c; + if (eth_vendor == VENDOR_NONE) { + unsigned char romdata[16]; + unsigned char testbuf[32]; + int idx; + static unsigned char test[] = "NE*000 memory"; + static unsigned short base[] = { +#ifdef NE_SCAN + NE_SCAN, +#endif + 0 }; + /* if no addresses supplied, fall back on defaults */ + if (probe_addrs == 0 || probe_addrs[0] == 0) + probe_addrs = base; + eth_bmem = 0; /* No shared memory */ + for (idx = 0; (eth_nic_base = probe_addrs[idx]) != 0; ++idx) { + eth_flags = FLAG_PIO; + eth_asic_base = eth_nic_base + NE_ASIC_OFFSET; + eth_memsize = MEM_16384; + eth_tx_start = 32; + eth_rx_start = 32 + D8390_TXBUF_SIZE; + c = inb(eth_asic_base + NE_RESET); + outb(c, eth_asic_base + NE_RESET); + (void) inb(0x84); + outb(D8390_COMMAND_STP | + D8390_COMMAND_RD2, eth_nic_base + D8390_P0_COMMAND); + outb(D8390_RCR_MON, eth_nic_base + D8390_P0_RCR); + outb(D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR); + outb(MEM_8192, eth_nic_base + D8390_P0_PSTART); + outb(MEM_16384, eth_nic_base + D8390_P0_PSTOP); +#ifdef NS8390_FORCE_16BIT + eth_flags |= FLAG_16BIT; /* force 16-bit mode */ +#endif + + eth_pio_write( (unsigned char *) test, 8192, sizeof(test)); + eth_pio_read(8192, testbuf, sizeof(test)); + if (!memcmp(test, testbuf, sizeof(test))) + break; + eth_flags |= FLAG_16BIT; + eth_memsize = MEM_32768; + eth_tx_start = 64; + eth_rx_start = 64 + D8390_TXBUF_SIZE; + outb(D8390_DCR_WTS | + D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR); + outb(MEM_16384, eth_nic_base + D8390_P0_PSTART); + outb(MEM_32768, eth_nic_base + D8390_P0_PSTOP); + eth_pio_write( (unsigned char *) test, 16384, sizeof(test)); + eth_pio_read(16384, testbuf, sizeof(test)); + if (!memcmp(testbuf, test, sizeof(test))) + break; + } + if (eth_nic_base == 0) + return (0); + if (eth_nic_base > ISA_MAX_ADDR) /* PCI probably */ + eth_flags |= FLAG_16BIT; + eth_vendor = VENDOR_NOVELL; + eth_pio_read(0, romdata, sizeof(romdata)); + for (i=0; i<ETH_ALEN; i++) { + nic->node_addr[i] = romdata[i + ((eth_flags & FLAG_16BIT) ? i : 0)]; + } + nic->ioaddr = eth_nic_base; + DBG ( "\nNE%c000 base %4.4x, MAC Addr %s\n", + (eth_flags & FLAG_16BIT) ? '2' : '1', eth_nic_base, + eth_ntoa ( nic->node_addr ) ); + } +} +#endif + if (eth_vendor == VENDOR_NONE) + return(0); + if (eth_vendor != VENDOR_3COM) + eth_rmem = eth_bmem; + ns8390_reset(nic); + nic->nic_op = &ns8390_operations; + + /* Based on PnP ISA map */ +#ifdef INCLUDE_WD + dev->devid.vendor_id = htons(GENERIC_ISAPNP_VENDOR); + dev->devid.device_id = htons(0x812a); +#endif +#ifdef INCLUDE_3C503 + dev->devid.vendor_id = htons(GENERIC_ISAPNP_VENDOR); + dev->devid.device_id = htons(0x80f3); +#endif +#ifdef INCLUDE_NE + dev->devid.vendor_id = htons(GENERIC_ISAPNP_VENDOR); + dev->devid.device_id = htons(0x80d6); +#endif + return 1; +} + +#ifdef INCLUDE_WD +struct isa_driver wd_driver __isa_driver = { + .type = NIC_DRIVER, + .name = "WD", + .probe = wd_probe, + .ioaddrs = 0, +}; +ISA_ROM("wd","WD8003/8013, SMC8216/8416, SMC 83c790 (EtherEZ)"); +#endif + +#ifdef INCLUDE_3C503 +struct isa_driver t503_driver __isa_driver = { + .type = NIC_DRIVER, + .name = "3C503", + .probe = t503_probe, + .ioaddrs = 0, +}; +ISA_ROM("3c503","3Com503, Etherlink II[/16]"); +#endif + +#ifdef INCLUDE_NE +struct isa_driver ne_driver __isa_driver = { + .type = NIC_DRIVER, + .name = "NE*000", + .probe = ne_probe, + .ioaddrs = 0, +}; +ISA_ROM("ne","NE1000/2000 and clones"); +#endif + +#ifdef INCLUDE_NS8390 +static struct pci_device_id nepci_nics[] = { +/* A few NE2000 PCI clones, list not exhaustive */ +PCI_ROM(0x10ec, 0x8029, "rtl8029", "Realtek 8029", 0), +PCI_ROM(0x1186, 0x0300, "dlink-528", "D-Link DE-528", 0), +PCI_ROM(0x1050, 0x0940, "winbond940", "Winbond NE2000-PCI", 0), /* Winbond 86C940 / 89C940 */ +PCI_ROM(0x1050, 0x5a5a, "winbond940f", "Winbond W89c940F", 0), /* Winbond 89C940F */ +PCI_ROM(0x11f6, 0x1401, "compexrl2000", "Compex ReadyLink 2000", 0), +PCI_ROM(0x8e2e, 0x3000, "ktiet32p2", "KTI ET32P2", 0), +PCI_ROM(0x4a14, 0x5000, "nv5000sc", "NetVin NV5000SC", 0), +PCI_ROM(0x12c3, 0x0058, "holtek80232", "Holtek HT80232", 0), +PCI_ROM(0x12c3, 0x5598, "holtek80229", "Holtek HT80229", 0), +PCI_ROM(0x10bd, 0x0e34, "surecom-ne34", "Surecom NE34", 0), +PCI_ROM(0x1106, 0x0926, "via86c926", "Via 86c926", 0), +}; + +PCI_DRIVER ( nepci_driver, nepci_nics, PCI_NO_CLASS ); + +DRIVER ( "NE2000/PCI", nic_driver, pci_driver, nepci_driver, + nepci_probe, ns8390_disable ); + +#endif /* INCLUDE_NS8390 */ + +#endif + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/ns8390.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/ns8390.h new file mode 100644 index 0000000..79728e7 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/ns8390.h @@ -0,0 +1,240 @@ +/************************************************************************** +ETHERBOOT - BOOTP/TFTP Bootstrap Program + +Author: Martin Renters + Date: Jun/94 + +**************************************************************************/ + +FILE_LICENCE ( BSD2 ); + +#define VENDOR_NONE 0 +#define VENDOR_WD 1 +#define VENDOR_NOVELL 2 +#define VENDOR_3COM 3 + +#define FLAG_PIO 0x01 +#define FLAG_16BIT 0x02 +#define FLAG_790 0x04 + +#define MEM_8192 32 +#define MEM_16384 64 +#define MEM_32768 128 + +#define ISA_MAX_ADDR 0x400 + +/************************************************************************** +Western Digital/SMC Board Definitions +**************************************************************************/ +#define WD_LOW_BASE 0x200 +#define WD_HIGH_BASE 0x3e0 +#ifndef WD_DEFAULT_MEM +#define WD_DEFAULT_MEM 0xD0000 +#endif +#define WD_NIC_ADDR 0x10 + +/************************************************************************** +Western Digital/SMC ASIC Addresses +**************************************************************************/ +#define WD_MSR 0x00 +#define WD_ICR 0x01 +#define WD_IAR 0x02 +#define WD_BIO 0x03 +#define WD_IRR 0x04 +#define WD_LAAR 0x05 +#define WD_IJR 0x06 +#define WD_GP2 0x07 +#define WD_LAR 0x08 +#define WD_BID 0x0E + +#define WD_ICR_16BIT 0x01 + +#define WD_MSR_MENB 0x40 + +#define WD_LAAR_L16EN 0x40 +#define WD_LAAR_M16EN 0x80 + +#define WD_SOFTCONFIG 0x20 + +/************************************************************************** +Western Digital/SMC Board Types +**************************************************************************/ +#define TYPE_WD8003S 0x02 +#define TYPE_WD8003E 0x03 +#define TYPE_WD8013EBT 0x05 +#define TYPE_WD8003W 0x24 +#define TYPE_WD8003EB 0x25 +#define TYPE_WD8013W 0x26 +#define TYPE_WD8013EP 0x27 +#define TYPE_WD8013WC 0x28 +#define TYPE_WD8013EPC 0x29 +#define TYPE_SMC8216T 0x2a +#define TYPE_SMC8216C 0x2b +#define TYPE_SMC8416T 0x00 /* Bogus entries: the 8416 generates the */ +#define TYPE_SMC8416C 0x00 /* the same codes as the 8216. */ +#define TYPE_SMC8013EBP 0x2c + +/************************************************************************** +3com 3c503 definitions +**************************************************************************/ + +#ifndef _3COM_BASE +#define _3COM_BASE 0x300 +#endif + +#define _3COM_TX_PAGE_OFFSET_8BIT 0x20 +#define _3COM_TX_PAGE_OFFSET_16BIT 0x0 +#define _3COM_RX_PAGE_OFFSET_16BIT 0x20 + +#define _3COM_ASIC_OFFSET 0x400 +#define _3COM_NIC_OFFSET 0x0 + +#define _3COM_PSTR 0 +#define _3COM_PSPR 1 + +#define _3COM_BCFR 3 +#define _3COM_BCFR_2E0 0x01 +#define _3COM_BCFR_2A0 0x02 +#define _3COM_BCFR_280 0x04 +#define _3COM_BCFR_250 0x08 +#define _3COM_BCFR_350 0x10 +#define _3COM_BCFR_330 0x20 +#define _3COM_BCFR_310 0x40 +#define _3COM_BCFR_300 0x80 +#define _3COM_PCFR 4 +#define _3COM_PCFR_PIO 0 +#define _3COM_PCFR_C8000 0x10 +#define _3COM_PCFR_CC000 0x20 +#define _3COM_PCFR_D8000 0x40 +#define _3COM_PCFR_DC000 0x80 +#define _3COM_CR 6 +#define _3COM_CR_RST 0x01 /* Reset GA and NIC */ +#define _3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ +#define _3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ +#define _3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ +#define _3COM_CR_SHARE 0x10 /* select interrupt sharing option */ +#define _3COM_CR_DBSEL 0x20 /* Double buffer select */ +#define _3COM_CR_DDIR 0x40 /* DMA direction select */ +#define _3COM_CR_START 0x80 /* Start DMA controller */ +#define _3COM_GACFR 5 +#define _3COM_GACFR_MBS0 0x01 +#define _3COM_GACFR_MBS1 0x02 +#define _3COM_GACFR_MBS2 0x04 +#define _3COM_GACFR_RSEL 0x08 /* enable shared memory */ +#define _3COM_GACFR_TEST 0x10 /* for GA testing */ +#define _3COM_GACFR_OWS 0x20 /* select 0WS access to GA */ +#define _3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */ +#define _3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */ +#define _3COM_STREG 7 +#define _3COM_STREG_REV 0x07 /* GA revision */ +#define _3COM_STREG_DIP 0x08 /* DMA in progress */ +#define _3COM_STREG_DTC 0x10 /* DMA terminal count */ +#define _3COM_STREG_OFLW 0x20 /* Overflow */ +#define _3COM_STREG_UFLW 0x40 /* Underflow */ +#define _3COM_STREG_DPRDY 0x80 /* Data port ready */ +#define _3COM_IDCFR 8 +#define _3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */ +#define _3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */ +#define _3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */ +#define _3COM_IDCFR_UNUSED 0x08 /* not used */ +#define _3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ +#define _3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ +#define _3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ +#define _3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ +#define _3COM_IRQ2 2 +#define _3COM_IRQ3 3 +#define _3COM_IRQ4 4 +#define _3COM_IRQ5 5 +#define _3COM_DAMSB 9 +#define _3COM_DALSB 0x0a +#define _3COM_VPTR2 0x0b +#define _3COM_VPTR1 0x0c +#define _3COM_VPTR0 0x0d +#define _3COM_RFMSB 0x0e +#define _3COM_RFLSB 0x0f + +/************************************************************************** +NE1000/2000 definitions +**************************************************************************/ +#define NE_ASIC_OFFSET 0x10 +#define NE_RESET 0x0F /* Used to reset card */ +#define NE_DATA 0x00 /* Used to read/write NIC mem */ + +#define COMPEX_RL2000_TRIES 200 + +/************************************************************************** +8390 Register Definitions +**************************************************************************/ +#define D8390_P0_COMMAND 0x00 +#define D8390_P0_PSTART 0x01 +#define D8390_P0_PSTOP 0x02 +#define D8390_P0_BOUND 0x03 +#define D8390_P0_TSR 0x04 +#define D8390_P0_TPSR 0x04 +#define D8390_P0_TBCR0 0x05 +#define D8390_P0_TBCR1 0x06 +#define D8390_P0_ISR 0x07 +#define D8390_P0_RSAR0 0x08 +#define D8390_P0_RSAR1 0x09 +#define D8390_P0_RBCR0 0x0A +#define D8390_P0_RBCR1 0x0B +#define D8390_P0_RSR 0x0C +#define D8390_P0_RCR 0x0C +#define D8390_P0_TCR 0x0D +#define D8390_P0_DCR 0x0E +#define D8390_P0_IMR 0x0F +#define D8390_P1_COMMAND 0x00 +#define D8390_P1_PAR0 0x01 +#define D8390_P1_PAR1 0x02 +#define D8390_P1_PAR2 0x03 +#define D8390_P1_PAR3 0x04 +#define D8390_P1_PAR4 0x05 +#define D8390_P1_PAR5 0x06 +#define D8390_P1_CURR 0x07 +#define D8390_P1_MAR0 0x08 + +#define D8390_COMMAND_PS0 0x0 /* Page 0 select */ +#define D8390_COMMAND_PS1 0x40 /* Page 1 select */ +#define D8390_COMMAND_PS2 0x80 /* Page 2 select */ +#define D8390_COMMAND_RD2 0x20 /* Remote DMA control */ +#define D8390_COMMAND_RD1 0x10 +#define D8390_COMMAND_RD0 0x08 +#define D8390_COMMAND_TXP 0x04 /* transmit packet */ +#define D8390_COMMAND_STA 0x02 /* start */ +#define D8390_COMMAND_STP 0x01 /* stop */ + +#define D8390_RCR_MON 0x20 /* monitor mode */ + +#define D8390_DCR_FT1 0x40 +#define D8390_DCR_LS 0x08 /* Loopback select */ +#define D8390_DCR_WTS 0x01 /* Word transfer select */ + +#define D8390_ISR_PRX 0x01 /* successful recv */ +#define D8390_ISR_PTX 0x02 /* successful xmit */ +#define D8390_ISR_RXE 0x04 /* receive error */ +#define D8390_ISR_TXE 0x08 /* transmit error */ +#define D8390_ISR_OVW 0x10 /* Overflow */ +#define D8390_ISR_CNT 0x20 /* Counter overflow */ +#define D8390_ISR_RDC 0x40 /* Remote DMA complete */ +#define D8390_ISR_RST 0x80 /* reset */ + +#define D8390_RSTAT_PRX 0x01 /* successful recv */ +#define D8390_RSTAT_CRC 0x02 /* CRC error */ +#define D8390_RSTAT_FAE 0x04 /* Frame alignment error */ +#define D8390_RSTAT_OVER 0x08 /* FIFO overrun */ + +#define D8390_TXBUF_SIZE 6 +#define D8390_RXBUF_END 32 +#define D8390_PAGE_SIZE 256 + +struct ringbuffer { + unsigned char status; + unsigned char next; + unsigned short len; +}; +/* + * Local variables: + * c-basic-offset: 8 + * End: + */ + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/pcnet32.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/pcnet32.c new file mode 100644 index 0000000..223bc1e --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/pcnet32.c @@ -0,0 +1,1021 @@ +/************************************************************************** +* +* pcnet32.c -- Etherboot device driver for the AMD PCnet32 +* Written 2003-2003 by Timothy Legge <tlegge@rogers.com> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +* +* Portions of this code based on: +* pcnet32.c: An AMD PCnet32 ethernet driver for linux: +* +* (C) 1996-1999 Thomas Bogendoerfer +* See Linux Driver for full information +* +* The transmit and poll functions were written with reference to: +* lance.c - LANCE NIC driver for Etherboot written by Ken Yap +* +* Linux Driver Version 1.27a, 10.02.2002 +* +* +* REVISION HISTORY: +* ================ +* v1.0 08-06-2003 timlegge Initial port of Linux driver +* v1.1 08-23-2003 timlegge Add multicast support +* v1.2 01-17-2004 timlegge Initial driver output cleanup +* v1.3 03-29-2004 timlegge More driver cleanup +* +* Indent Options: indent -kr -i8 +***************************************************************************/ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include "etherboot.h" +#include "nic.h" +#include <gpxe/pci.h> +#include <gpxe/ethernet.h> +#include "mii.h" + +/* void hex_dump(const char *data, const unsigned int len); */ + +/* Etherboot Specific definations */ +#define drv_version "v1.3" +#define drv_date "03-29-2004" + +static u32 ioaddr; /* Globally used for the card's io address */ +static struct nic_operations pcnet32_operations; + +#ifdef EDEBUG +#define dprintf(x) printf x +#else +#define dprintf(x) +#endif + +/* Condensed operations for readability. */ +#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) +#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) + +/* End Etherboot Specific */ + +static int cards_found = 0 /* __initdata */ ; + +#ifdef REMOVE +/* FIXME: Remove these they are probably pointless */ + +/* + * VLB I/O addresses + */ +static unsigned int pcnet32_portlist[] /*__initdata */ = +{ 0x300, 0x320, 0x340, 0x360, 0 }; + +static int pcnet32_debug = 1; +static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */ +static int pcnet32vlb; /* check for VLB cards ? */ + +static struct net_device *pcnet32_dev; + +static int max_interrupt_work = 80; +static int rx_copybreak = 200; +#endif +#define PCNET32_PORT_AUI 0x00 +#define PCNET32_PORT_10BT 0x01 +#define PCNET32_PORT_GPSI 0x02 +#define PCNET32_PORT_MII 0x03 + +#define PCNET32_PORT_PORTSEL 0x03 +#define PCNET32_PORT_ASEL 0x04 +#define PCNET32_PORT_100 0x40 +#define PCNET32_PORT_FD 0x80 + +#define PCNET32_DMA_MASK 0xffffffff + +/* + * table to translate option values from tulip + * to internal options + */ +static unsigned char options_mapping[] = { + PCNET32_PORT_ASEL, /* 0 Auto-select */ + PCNET32_PORT_AUI, /* 1 BNC/AUI */ + PCNET32_PORT_AUI, /* 2 AUI/BNC */ + PCNET32_PORT_ASEL, /* 3 not supported */ + PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */ + PCNET32_PORT_ASEL, /* 5 not supported */ + PCNET32_PORT_ASEL, /* 6 not supported */ + PCNET32_PORT_ASEL, /* 7 not supported */ + PCNET32_PORT_ASEL, /* 8 not supported */ + PCNET32_PORT_MII, /* 9 MII 10baseT */ + PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */ + PCNET32_PORT_MII, /* 11 MII (autosel) */ + PCNET32_PORT_10BT, /* 12 10BaseT */ + PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */ + PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, /* 14 MII 100BaseTx-FD */ + PCNET32_PORT_ASEL /* 15 not supported */ +}; + +#define MAX_UNITS 8 /* More are supported, limit only on options */ +static int options[MAX_UNITS]; +static int full_duplex[MAX_UNITS]; + +/* + * Theory of Operation + * + * This driver uses the same software structure as the normal lance + * driver. So look for a verbose description in lance.c. The differences + * to the normal lance driver is the use of the 32bit mode of PCnet32 + * and PCnetPCI chips. Because these chips are 32bit chips, there is no + * 16MB limitation and we don't need bounce buffers. + */ + + + +/* + * Set the number of Tx and Rx buffers, using Log_2(# buffers). + * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. + * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). + */ +#ifndef PCNET32_LOG_TX_BUFFERS +#define PCNET32_LOG_TX_BUFFERS 1 +#define PCNET32_LOG_RX_BUFFERS 2 +#endif + +#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS)) +#define TX_RING_MOD_MASK (TX_RING_SIZE - 1) +/* FIXME: Fix this to allow multiple tx_ring descriptors */ +#define TX_RING_LEN_BITS 0x0000 /*PCNET32_LOG_TX_BUFFERS) << 12) */ + +#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS)) +#define RX_RING_MOD_MASK (RX_RING_SIZE - 1) +#define RX_RING_LEN_BITS ((PCNET32_LOG_RX_BUFFERS) << 4) + +#define PKT_BUF_SZ 1544 + +/* Offsets from base I/O address. */ +#define PCNET32_WIO_RDP 0x10 +#define PCNET32_WIO_RAP 0x12 +#define PCNET32_WIO_RESET 0x14 +#define PCNET32_WIO_BDP 0x16 + +#define PCNET32_DWIO_RDP 0x10 +#define PCNET32_DWIO_RAP 0x14 +#define PCNET32_DWIO_RESET 0x18 +#define PCNET32_DWIO_BDP 0x1C + +#define PCNET32_TOTAL_SIZE 0x20 + +/* The PCNET32 Rx and Tx ring descriptors. */ +struct pcnet32_rx_head { + u32 base; + s16 buf_length; + s16 status; + u32 msg_length; + u32 reserved; +}; + +struct pcnet32_tx_head { + u32 base; + s16 length; + s16 status; + u32 misc; + u32 reserved; +}; + +/* The PCNET32 32-Bit initialization block, described in databook. */ +struct pcnet32_init_block { + u16 mode; + u16 tlen_rlen; + u8 phys_addr[6]; + u16 reserved; + u32 filter[2]; + /* Receive and transmit ring base, along with extra bits. */ + u32 rx_ring; + u32 tx_ring; +}; +/* PCnet32 access functions */ +struct pcnet32_access { + u16(*read_csr) (unsigned long, int); + void (*write_csr) (unsigned long, int, u16); + u16(*read_bcr) (unsigned long, int); + void (*write_bcr) (unsigned long, int, u16); + u16(*read_rap) (unsigned long); + void (*write_rap) (unsigned long, u16); + void (*reset) (unsigned long); +}; + +/* Define the TX and RX Descriptors and Rings */ +struct { + struct pcnet32_tx_head tx_ring[TX_RING_SIZE] + __attribute__ ((aligned(16))); + struct pcnet32_rx_head rx_ring[RX_RING_SIZE] + __attribute__ ((aligned(16))); + unsigned char txb[TX_RING_SIZE][PKT_BUF_SZ]; + unsigned char rxb[RX_RING_SIZE][PKT_BUF_SZ]; +} pcnet32_bufs __shared; + + +/* + * The first three fields of pcnet32_private are read by the ethernet device + * so we allocate the structure should be allocated by pci_alloc_consistent(). + */ +#define MII_CNT 4 +struct pcnet32_private { + struct pcnet32_init_block init_block; + struct pci_dev *pci_dev; /* Pointer to the associated pci device structure */ + const char *name; + /* The saved address of a sent-in-place packet/buffer, for skfree(). */ + struct sk_buff *tx_skbuff[TX_RING_SIZE]; + struct sk_buff *rx_skbuff[RX_RING_SIZE]; + struct pcnet32_access a; + unsigned int cur_rx, cur_tx; /* The next free ring entry */ + char tx_full; + int options; + int shared_irq:1, /* shared irq possible */ + ltint:1, /* enable TxDone-intr inhibitor */ + dxsuflo:1, /* disable transmit stop on uflo */ + mii:1; /* mii port available */ + struct mii_if_info mii_if; + unsigned char phys[MII_CNT]; + struct net_device *next; + int full_duplex:1; +} lpx; + +static struct pcnet32_private *lp; + +static int mdio_read(struct nic *nic __unused, int phy_id, int reg_num); +#if 0 +static void mdio_write(struct nic *nic __unused, int phy_id, int reg_num, + int val); +#endif +enum pci_flags_bit { + PCI_USES_IO = 1, PCI_USES_MEM = 2, PCI_USES_MASTER = 4, + PCI_ADDR0 = 0x10 << 0, PCI_ADDR1 = 0x10 << 1, PCI_ADDR2 = + 0x10 << 2, PCI_ADDR3 = 0x10 << 3, +}; + + +static u16 pcnet32_wio_read_csr(unsigned long addr, int index) +{ + outw(index, addr + PCNET32_WIO_RAP); + return inw(addr + PCNET32_WIO_RDP); +} + +static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val) +{ + outw(index, addr + PCNET32_WIO_RAP); + outw(val, addr + PCNET32_WIO_RDP); +} + +static u16 pcnet32_wio_read_bcr(unsigned long addr, int index) +{ + outw(index, addr + PCNET32_WIO_RAP); + return inw(addr + PCNET32_WIO_BDP); +} + +static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val) +{ + outw(index, addr + PCNET32_WIO_RAP); + outw(val, addr + PCNET32_WIO_BDP); +} + +static u16 pcnet32_wio_read_rap(unsigned long addr) +{ + return inw(addr + PCNET32_WIO_RAP); +} + +static void pcnet32_wio_write_rap(unsigned long addr, u16 val) +{ + outw(val, addr + PCNET32_WIO_RAP); +} + +static void pcnet32_wio_reset(unsigned long addr) +{ + inw(addr + PCNET32_WIO_RESET); +} + +static int pcnet32_wio_check(unsigned long addr) +{ + outw(88, addr + PCNET32_WIO_RAP); + return (inw(addr + PCNET32_WIO_RAP) == 88); +} + +static struct pcnet32_access pcnet32_wio = { + read_csr:pcnet32_wio_read_csr, + write_csr:pcnet32_wio_write_csr, + read_bcr:pcnet32_wio_read_bcr, + write_bcr:pcnet32_wio_write_bcr, + read_rap:pcnet32_wio_read_rap, + write_rap:pcnet32_wio_write_rap, + reset:pcnet32_wio_reset +}; + +static u16 pcnet32_dwio_read_csr(unsigned long addr, int index) +{ + outl(index, addr + PCNET32_DWIO_RAP); + return (inl(addr + PCNET32_DWIO_RDP) & 0xffff); +} + +static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val) +{ + outl(index, addr + PCNET32_DWIO_RAP); + outl(val, addr + PCNET32_DWIO_RDP); +} + +static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index) +{ + outl(index, addr + PCNET32_DWIO_RAP); + return (inl(addr + PCNET32_DWIO_BDP) & 0xffff); +} + +static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val) +{ + outl(index, addr + PCNET32_DWIO_RAP); + outl(val, addr + PCNET32_DWIO_BDP); +} + +static u16 pcnet32_dwio_read_rap(unsigned long addr) +{ + return (inl(addr + PCNET32_DWIO_RAP) & 0xffff); +} + +static void pcnet32_dwio_write_rap(unsigned long addr, u16 val) +{ + outl(val, addr + PCNET32_DWIO_RAP); +} + +static void pcnet32_dwio_reset(unsigned long addr) +{ + inl(addr + PCNET32_DWIO_RESET); +} + +static int pcnet32_dwio_check(unsigned long addr) +{ + outl(88, addr + PCNET32_DWIO_RAP); + return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88); +} + +static struct pcnet32_access pcnet32_dwio = { + read_csr:pcnet32_dwio_read_csr, + write_csr:pcnet32_dwio_write_csr, + read_bcr:pcnet32_dwio_read_bcr, + write_bcr:pcnet32_dwio_write_bcr, + read_rap:pcnet32_dwio_read_rap, + write_rap:pcnet32_dwio_write_rap, + reset:pcnet32_dwio_reset +}; + + +/* Initialize the PCNET32 Rx and Tx rings. */ +static int pcnet32_init_ring(struct nic *nic) +{ + int i; + + lp->tx_full = 0; + lp->cur_rx = lp->cur_tx = 0; + + for (i = 0; i < RX_RING_SIZE; i++) { + pcnet32_bufs.rx_ring[i].base = + virt_to_le32desc(&pcnet32_bufs.rxb[i]); + pcnet32_bufs.rx_ring[i].buf_length = le16_to_cpu(-PKT_BUF_SZ); + pcnet32_bufs.rx_ring[i].status = le16_to_cpu(0x8000); + } + + /* The Tx buffer address is filled in as needed, but we do need to clear + the upper ownership bit. */ + for (i = 0; i < TX_RING_SIZE; i++) { + pcnet32_bufs.tx_ring[i].base = 0; + pcnet32_bufs.tx_ring[i].status = 0; + } + + + lp->init_block.tlen_rlen = + le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS); + for (i = 0; i < 6; i++) + lp->init_block.phys_addr[i] = nic->node_addr[i]; + lp->init_block.rx_ring = virt_to_le32desc(&pcnet32_bufs.rx_ring[0]); + lp->init_block.tx_ring = virt_to_le32desc(&pcnet32_bufs.tx_ring[0]); + return 0; +} + +/************************************************************************** +RESET - Reset adapter +***************************************************************************/ +static void pcnet32_reset(struct nic *nic) +{ + /* put the card in its initial state */ + u16 val; + int i; + + /* Reset the PCNET32 */ + lp->a.reset(ioaddr); + + /* switch pcnet32 to 32bit mode */ + lp->a.write_bcr(ioaddr, 20, 2); + + /* set/reset autoselect bit */ + val = lp->a.read_bcr(ioaddr, 2) & ~2; + if (lp->options & PCNET32_PORT_ASEL) + val |= 2; + lp->a.write_bcr(ioaddr, 2, val); + + /* handle full duplex setting */ + if (lp->full_duplex) { + val = lp->a.read_bcr(ioaddr, 9) & ~3; + if (lp->options & PCNET32_PORT_FD) { + val |= 1; + if (lp->options == + (PCNET32_PORT_FD | PCNET32_PORT_AUI)) + val |= 2; + } else if (lp->options & PCNET32_PORT_ASEL) { + /* workaround of xSeries250, turn on for 79C975 only */ + i = ((lp->a. + read_csr(ioaddr, + 88) | (lp->a.read_csr(ioaddr, + 89) << 16)) >> + 12) & 0xffff; + if (i == 0x2627) + val |= 3; + } + lp->a.write_bcr(ioaddr, 9, val); + } + + /* set/reset GPSI bit in test register */ + val = lp->a.read_csr(ioaddr, 124) & ~0x10; + if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI) + val |= 0x10; + lp->a.write_csr(ioaddr, 124, val); + + if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) { + val = lp->a.read_bcr(ioaddr, 32) & ~0x38; /* disable Auto Negotiation, set 10Mpbs, HD */ + if (lp->options & PCNET32_PORT_FD) + val |= 0x10; + if (lp->options & PCNET32_PORT_100) + val |= 0x08; + lp->a.write_bcr(ioaddr, 32, val); + } else { + if (lp->options & PCNET32_PORT_ASEL) { /* enable auto negotiate, setup, disable fd */ + val = lp->a.read_bcr(ioaddr, 32) & ~0x98; + val |= 0x20; + lp->a.write_bcr(ioaddr, 32, val); + } + } + +#ifdef DO_DXSUFLO + if (lp->dxsuflo) { /* Disable transmit stop on underflow */ + val = lp->a.read_csr(ioaddr, 3); + val |= 0x40; + lp->a.write_csr(ioaddr, 3, val); + } +#endif + if (1) + { + //disable interrupts + val = lp->a.read_csr(ioaddr, 3); + val = val + | (1 << 14) //BABLM intr disabled + | (1 << 12) //MISSM missed frame mask intr disabled + | (1 << 10) //RINTM receive intr disabled + | (1 << 9) //TINTM transmit intr disabled + | (1 << 8) //IDONM init done intr disabled + ; + lp->a.write_csr(ioaddr, 3, val); + } + + if (lp->ltint) { /* Enable TxDone-intr inhibitor */ + val = lp->a.read_csr(ioaddr, 5); + val |= (1 << 14); + lp->a.write_csr(ioaddr, 5, val); + } + lp->init_block.mode = + le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7); + lp->init_block.filter[0] = 0xffffffff; + lp->init_block.filter[1] = 0xffffffff; + + pcnet32_init_ring(nic); + + + /* Re-initialize the PCNET32, and start it when done. */ + lp->a.write_csr(ioaddr, 1, + (virt_to_bus(&lp->init_block)) & 0xffff); + lp->a.write_csr(ioaddr, 2, (virt_to_bus(&lp->init_block)) >> 16); + lp->a.write_csr(ioaddr, 4, 0x0915); + lp->a.write_csr(ioaddr, 0, 0x0001); + + + i = 0; + while (i++ < 100) + if (lp->a.read_csr(ioaddr, 0) & 0x0100) + break; + /* + * We used to clear the InitDone bit, 0x0100, here but Mark Stockton + * reports that doing so triggers a bug in the '974. + */ + lp->a.write_csr(ioaddr, 0, 0x0042); + + dprintf(("pcnet32 open, csr0 %hX.\n", lp->a.read_csr(ioaddr, 0))); + +} + +/************************************************************************** +POLL - Wait for a frame +***************************************************************************/ +static int pcnet32_poll(struct nic *nic __unused, int retrieve) +{ + /* return true if there's an ethernet packet ready to read */ + /* nic->packet should contain data on return */ + /* nic->packetlen should contain length of data */ + + signed char status; + int entry; + + entry = lp->cur_rx & RX_RING_MOD_MASK; + status = (le16_to_cpu(pcnet32_bufs.rx_ring[entry].status) >> 8); + + if (status < 0) + return 0; + + if ( ! retrieve ) return 1; + + if (status == 0x03) { + nic->packetlen = + (le32_to_cpu(pcnet32_bufs.rx_ring[entry].msg_length) + & 0xfff) - 4; + memcpy(nic->packet, &pcnet32_bufs.rxb[entry], nic->packetlen); + + /* Andrew Boyd of QNX reports that some revs of the 79C765 + * clear the buffer length */ + pcnet32_bufs.rx_ring[entry].buf_length + = le16_to_cpu(-PKT_BUF_SZ); + /* prime for next receive */ + pcnet32_bufs.rx_ring[entry].status |= le16_to_cpu(0x8000); + /* Switch to the next Rx ring buffer */ + lp->cur_rx++; + + } else { + return 0; + } + + return 1; +} + +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static void pcnet32_transmit(struct nic *nic __unused, const char *d, /* Destination */ + unsigned int t, /* Type */ + unsigned int s, /* size */ + const char *p) +{ /* Packet */ + /* send the packet to destination */ + unsigned long time; + u8 *ptxb; + u16 nstype; + u16 status; + int entry = 0; /*lp->cur_tx & TX_RING_MOD_MASK; */ + + status = 0x8300; + /* point to the current txb incase multiple tx_rings are used */ + ptxb = pcnet32_bufs.txb[lp->cur_tx]; + + /* copy the packet to ring buffer */ + memcpy(ptxb, d, ETH_ALEN); /* dst */ + memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */ + nstype = htons((u16) t); /* type */ + memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2); /* type */ + memcpy(ptxb + ETH_HLEN, p, s); + + s += ETH_HLEN; + while (s < ETH_ZLEN) /* pad to min length */ + ptxb[s++] = '\0'; + + pcnet32_bufs.tx_ring[entry].length = le16_to_cpu(-s); + pcnet32_bufs.tx_ring[entry].misc = 0x00000000; + pcnet32_bufs.tx_ring[entry].base = (u32) virt_to_le32desc(ptxb); + + /* we set the top byte as the very last thing */ + pcnet32_bufs.tx_ring[entry].status = le16_to_cpu(status); + + + /* Trigger an immediate send poll */ + lp->a.write_csr(ioaddr, 0, 0x0048); + + /* wait for transmit complete */ + lp->cur_tx = 0; /* (lp->cur_tx + 1); */ + time = currticks() + TICKS_PER_SEC; /* wait one second */ + while (currticks() < time && + ((short) le16_to_cpu(pcnet32_bufs.tx_ring[entry].status) < 0)); + + if ((short) le16_to_cpu(pcnet32_bufs.tx_ring[entry].status) < 0) + printf("PCNET32 timed out on transmit\n"); + + /* Stop pointing at the current txb + * otherwise the card continues to send the packet */ + pcnet32_bufs.tx_ring[entry].base = 0; + +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void pcnet32_disable ( struct nic *nic __unused ) { + /* Stop the PCNET32 here -- it ocassionally polls memory if we don't */ + lp->a.write_csr(ioaddr, 0, 0x0004); + + /* + * Switch back to 16-bit mode to avoid problems with dumb + * DOS packet driver after a warm reboot + */ + lp->a.write_bcr(ioaddr, 20, 0); +} + +/************************************************************************** +IRQ - Enable, Disable, or Force interrupts +***************************************************************************/ +static void pcnet32_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + + +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +You should omit the last argument struct pci_device * for a non-PCI NIC +***************************************************************************/ +static int pcnet32_probe ( struct nic *nic, struct pci_device *pci ) { + + int i, media; + int fdx, mii, fset, dxsuflo, ltint; + int chip_version; + struct pcnet32_access *a = NULL; + char *chipname; + u8 promaddr[6]; + int shared = 1; + + if (pci->ioaddr == 0) + return 0; + + /* BASE is used throughout to address the card */ + ioaddr = pci->ioaddr; + printf("pcnet32.c: Found %s, Vendor=0x%hX Device=0x%hX\n", + pci->driver_name, pci->vendor, pci->device); + + nic->irqno = 0; + nic->ioaddr = pci->ioaddr & ~3; + + /* reset the chip */ + pcnet32_wio_reset(ioaddr); + + /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */ + if (pcnet32_wio_read_csr(ioaddr, 0) == 4 + && pcnet32_wio_check(ioaddr)) { + a = &pcnet32_wio; + } else { + pcnet32_dwio_reset(ioaddr); + if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 + && pcnet32_dwio_check(ioaddr)) { + a = &pcnet32_dwio; + } else + return 0; + } + + chip_version = + a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16); + + dprintf(("PCnet chip version is 0x%X\n", chip_version)); + if ((chip_version & 0xfff) != 0x003) + return 0; + + /* initialize variables */ + fdx = mii = fset = dxsuflo = ltint = 0; + chip_version = (chip_version >> 12) & 0xffff; + + switch (chip_version) { + case 0x2420: + chipname = "PCnet/PCI 79C970"; /* PCI */ + break; + case 0x2430: + if (shared) + chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */ + else + chipname = "PCnet/32 79C965"; /* 486/VL bus */ + break; + case 0x2621: + chipname = "PCnet/PCI II 79C970A"; /* PCI */ + fdx = 1; + break; + case 0x2623: + chipname = "PCnet/FAST 79C971"; /* PCI */ + fdx = 1; + mii = 1; + fset = 1; + ltint = 1; + break; + case 0x2624: + chipname = "PCnet/FAST+ 79C972"; /* PCI */ + fdx = 1; + mii = 1; + fset = 1; + break; + case 0x2625: + chipname = "PCnet/FAST III 79C973"; /* PCI */ + fdx = 1; + mii = 1; + break; + case 0x2626: + chipname = "PCnet/Home 79C978"; /* PCI */ + fdx = 1; + /* + * This is based on specs published at www.amd.com. This section + * assumes that a card with a 79C978 wants to go into 1Mb HomePNA + * mode. The 79C978 can also go into standard ethernet, and there + * probably should be some sort of module option to select the + * mode by which the card should operate + */ + /* switch to home wiring mode */ + media = a->read_bcr(ioaddr, 49); + + printf("media reset to %#x.\n", media); + a->write_bcr(ioaddr, 49, media); + break; + case 0x2627: + chipname = "PCnet/FAST III 79C975"; /* PCI */ + fdx = 1; + mii = 1; + break; + default: + chipname = "UNKNOWN"; + printf("PCnet version %#x, no PCnet32 chip.\n", + chip_version); + return 0; + } + + /* + * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit + * starting until the packet is loaded. Strike one for reliability, lose + * one for latency - although on PCI this isnt a big loss. Older chips + * have FIFO's smaller than a packet, so you can't do this. + */ + + if (fset) { + a->write_bcr(ioaddr, 18, + (a->read_bcr(ioaddr, 18) | 0x0800)); + a->write_csr(ioaddr, 80, + (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00); + dxsuflo = 1; + ltint = 1; + } + + DBG ( "%s at %hX,", chipname, (unsigned int) ioaddr ); + + /* read PROM address */ + for (i = 0; i < 6; i++) + promaddr[i] = inb(ioaddr + i); + + /* Update the nic structure with the MAC Address */ + for (i = 0; i < ETH_ALEN; i++) { + nic->node_addr[i] = promaddr[i]; + } + + /* Print out some hardware info */ + DBG ( "%s: IO Addr 0x%hX, MAC Addr %s\n ", chipname, (unsigned int) ioaddr, + eth_ntoa ( nic->node_addr ) ); + + /* Set to pci bus master */ + adjust_pci_device(pci); + + /* point to private storage */ + lp = &lpx; + +#if EBDEBUG + if (((chip_version + 1) & 0xfffe) == 0x2624) { /* Version 0x2623 or 0x2624 */ + i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */ + dprintf((" tx_start_pt(0x%hX):", i)); + switch (i >> 10) { + case 0: + dprintf((" 20 bytes,")); + break; + case 1: + dprintf((" 64 bytes,")); + break; + case 2: + dprintf((" 128 bytes,")); + break; + case 3: + dprintf(("~220 bytes,")); + break; + } + i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */ + dprintf((" BCR18(%hX):", i & 0xffff)); + if (i & (1 << 5)) + dprintf(("BurstWrEn ")); + if (i & (1 << 6)) + dprintf(("BurstRdEn ")); + if (i & (1 << 7)) + dprintf(("DWordIO ")); + if (i & (1 << 11)) + dprintf(("NoUFlow ")); + i = a->read_bcr(ioaddr, 25); + dprintf((" SRAMSIZE=0x%hX,", i << 8)); + i = a->read_bcr(ioaddr, 26); + dprintf((" SRAM_BND=0x%hX,", i << 8)); + i = a->read_bcr(ioaddr, 27); + if (i & (1 << 14)) + dprintf(("LowLatRx")); + } +#endif + lp->name = chipname; + lp->shared_irq = shared; + lp->full_duplex = fdx; + lp->dxsuflo = dxsuflo; + lp->ltint = ltint; + lp->mii = mii; + /* FIXME: Fix Options for only one card */ + if ((cards_found >= MAX_UNITS) + || ((unsigned int) options[cards_found] > sizeof(options_mapping))) + lp->options = PCNET32_PORT_ASEL; + else + lp->options = options_mapping[options[cards_found]]; + + if (fdx && !(lp->options & PCNET32_PORT_ASEL) && + ((cards_found >= MAX_UNITS) || full_duplex[cards_found])) + lp->options |= PCNET32_PORT_FD; + + if (!a) { + printf("No access methods\n"); + return 0; + } + + // lp->a = *a; + // Causes a loader: + // bin/blib.a(pcnet32.o)(.text+0x6b6): In function `pcnet32_probe': + // drivers/net/pcnet32.c:871: undefined reference to `memcpy' + // make: *** [bin/pcnet32.dsk.tmp] Error 1 + // So we do: + memcpy ( &lp->a, a, sizeof ( lp->a ) ); + // To explicity call memcpy. + + /* detect special T1/E1 WAN card by checking for MAC address */ + if (nic->node_addr[0] == 0x00 && nic->node_addr[1] == 0xe0 + && nic->node_addr[2] == 0x75) + lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI; + + lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */ + lp->init_block.tlen_rlen = + le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS); + for (i = 0; i < 6; i++) + lp->init_block.phys_addr[i] = nic->node_addr[i]; + lp->init_block.filter[0] = 0xffffffff; + lp->init_block.filter[1] = 0xffffffff; + lp->init_block.rx_ring = virt_to_bus(&pcnet32_bufs.rx_ring); + lp->init_block.tx_ring = virt_to_bus(&pcnet32_bufs.tx_ring); + + /* switch pcnet32 to 32bit mode */ + a->write_bcr(ioaddr, 20, 2); + + a->write_csr(ioaddr, 1, (virt_to_bus(&lp->init_block)) & 0xffff); + a->write_csr(ioaddr, 2, (virt_to_bus(&lp->init_block)) >> 16); + + /* + * To auto-IRQ we enable the initialization-done and DMA error + * interrupts. For ISA boards we get a DMA error, but VLB and PCI + * boards will work. + */ + /* Trigger an initialization just for the interrupt. */ + + +// a->write_csr(ioaddr, 0, 0x41); +// mdelay(1); + + cards_found++; + + /* point to NIC specific routines */ + pcnet32_reset(nic); + if (mii) { + int tmp; + int phy, phy_idx = 0; + u16 mii_lpa; + lp->phys[0] = 1; /* Default Setting */ + for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) { + int mii_status = mdio_read(nic, phy, MII_BMSR); + if (mii_status != 0xffff && mii_status != 0x0000) { + lp->phys[phy_idx++] = phy; + lp->mii_if.advertising = + mdio_read(nic, phy, MII_ADVERTISE); + if ((mii_status & 0x0040) == 0) { + tmp = phy; + dprintf (("MII PHY found at address %d, status " + "%hX advertising %hX\n", phy, mii_status, + lp->mii_if.advertising)); + } + } + } + if (phy_idx == 0) + printf("No MII transceiver found!\n"); + lp->mii_if.phy_id = lp->phys[0]; + + lp->mii_if.advertising = + mdio_read(nic, lp->phys[0], MII_ADVERTISE); + + mii_lpa = mdio_read(nic, lp->phys[0], MII_LPA); + lp->mii_if.advertising &= mii_lpa; + if (lp->mii_if.advertising & ADVERTISE_100FULL) + printf("100Mbps Full-Duplex\n"); + else if (lp->mii_if.advertising & ADVERTISE_100HALF) + printf("100Mbps Half-Duplex\n"); + else if (lp->mii_if.advertising & ADVERTISE_10FULL) + printf("10Mbps Full-Duplex\n"); + else if (lp->mii_if.advertising & ADVERTISE_10HALF) + printf("10Mbps Half-Duplex\n"); + else + printf("\n"); + } else { + /* The older chips are fixed 10Mbps, and some support full duplex, + * although not via autonegotiation, but only via configuration. */ + if (fdx) + printf("10Mbps Full-Duplex\n"); + else + printf("10Mbps Half-Duplex\n"); + } + + nic->nic_op = &pcnet32_operations; + + return 1; +} +static int mdio_read(struct nic *nic __unused, int phy_id, int reg_num) +{ + u16 val_out; + int phyaddr; + + if (!lp->mii) + return 0; + + phyaddr = lp->a.read_bcr(ioaddr, 33); + + lp->a.write_bcr(ioaddr, 33, + ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); + val_out = lp->a.read_bcr(ioaddr, 34); + lp->a.write_bcr(ioaddr, 33, phyaddr); + + return val_out; +} + +#if 0 +static void mdio_write(struct nic *nic __unused, int phy_id, int reg_num, + int val) +{ + int phyaddr; + + if (!lp->mii) + return; + + phyaddr = lp->a.read_bcr(ioaddr, 33); + + lp->a.write_bcr(ioaddr, 33, + ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); + lp->a.write_bcr(ioaddr, 34, val); + lp->a.write_bcr(ioaddr, 33, phyaddr); +} +#endif + +static struct nic_operations pcnet32_operations = { + .connect = dummy_connect, + .poll = pcnet32_poll, + .transmit = pcnet32_transmit, + .irq = pcnet32_irq, + +}; + +static struct pci_device_id pcnet32_nics[] = { + PCI_ROM(0x1022, 0x2000, "pcnet32", "AMD PCnet/PCI", 0), + PCI_ROM(0x1022, 0x2625, "pcnetfastiii", "AMD PCNet FAST III", 0), + PCI_ROM(0x1022, 0x2001, "amdhomepna", "AMD PCnet/HomePNA", 0), +}; + +PCI_DRIVER ( pcnet32_driver, pcnet32_nics, PCI_NO_CLASS ); + +DRIVER ( "PCNET32/PCI", nic_driver, pci_driver, pcnet32_driver, + pcnet32_probe, pcnet32_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/pnic.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/pnic.c new file mode 100644 index 0000000..cbc6790 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/pnic.c @@ -0,0 +1,281 @@ +/************************************************************************** +Etherboot - BOOTP/TFTP Bootstrap Program +Bochs Pseudo NIC driver for Etherboot +***************************************************************************/ + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2, or (at + * your option) any later version. + * + * See pnic_api.h for an explanation of the Bochs Pseudo NIC. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <stdint.h> +#include <stdio.h> +#include <gpxe/io.h> +#include <errno.h> +#include <gpxe/pci.h> +#include <gpxe/if_ether.h> +#include <gpxe/ethernet.h> +#include <gpxe/iobuf.h> +#include <gpxe/netdevice.h> + +#include "pnic_api.h" + +struct pnic { + unsigned short ioaddr; +}; + +/* + * Utility functions: issue a PNIC command, retrieve result. Use + * pnic_command_quiet if you don't want failure codes to be + * automatically printed. Returns the PNIC status code. + * + * Set output_length to NULL only if you expect to receive exactly + * output_max_length bytes, otherwise it'll complain that you didn't + * get enough data (on the assumption that if you not interested in + * discovering the output length then you're expecting a fixed amount + * of data). + */ + +static uint16_t pnic_command_quiet ( struct pnic *pnic, uint16_t command, + const void *input, uint16_t input_length, + void *output, uint16_t output_max_length, + uint16_t *output_length ) { + uint16_t status; + uint16_t _output_length; + + if ( input != NULL ) { + /* Write input length */ + outw ( input_length, pnic->ioaddr + PNIC_REG_LEN ); + /* Write input data */ + outsb ( pnic->ioaddr + PNIC_REG_DATA, input, input_length ); + } + /* Write command */ + outw ( command, pnic->ioaddr + PNIC_REG_CMD ); + /* Retrieve status */ + status = inw ( pnic->ioaddr + PNIC_REG_STAT ); + /* Retrieve output length */ + _output_length = inw ( pnic->ioaddr + PNIC_REG_LEN ); + if ( output_length == NULL ) { + if ( _output_length != output_max_length ) { + printf ( "pnic_command %#hx: wrong data length " + "returned (expected %d, got %d)\n", command, + output_max_length, _output_length ); + } + } else { + *output_length = _output_length; + } + if ( output != NULL ) { + if ( _output_length > output_max_length ) { + printf ( "pnic_command %#hx: output buffer too small " + "(have %d, need %d)\n", command, + output_max_length, _output_length ); + _output_length = output_max_length; + } + /* Retrieve output data */ + insb ( pnic->ioaddr + PNIC_REG_DATA, output, _output_length ); + } + return status; +} + +static uint16_t pnic_command ( struct pnic *pnic, uint16_t command, + const void *input, uint16_t input_length, + void *output, uint16_t output_max_length, + uint16_t *output_length ) { + uint16_t status = pnic_command_quiet ( pnic, command, + input, input_length, + output, output_max_length, + output_length ); + if ( status == PNIC_STATUS_OK ) return status; + printf ( "PNIC command %#hx (len %#hx) failed with status %#hx\n", + command, input_length, status ); + return status; +} + +/* Check API version matches that of NIC */ +static int pnic_api_check ( uint16_t api_version ) { + if ( api_version != PNIC_API_VERSION ) { + printf ( "Warning: API version mismatch! " + "(NIC's is %d.%d, ours is %d.%d)\n", + api_version >> 8, api_version & 0xff, + PNIC_API_VERSION >> 8, PNIC_API_VERSION & 0xff ); + } + if ( api_version < PNIC_API_VERSION ) { + printf ( "** You may need to update your copy of Bochs **\n" ); + } + return ( api_version == PNIC_API_VERSION ); +} + +/************************************************************************** +POLL - Wait for a frame +***************************************************************************/ +static void pnic_poll ( struct net_device *netdev ) { + struct pnic *pnic = netdev->priv; + struct io_buffer *iobuf; + uint16_t length; + uint16_t qlen; + + /* Fetch all available packets */ + while ( 1 ) { + if ( pnic_command ( pnic, PNIC_CMD_RECV_QLEN, NULL, 0, + &qlen, sizeof ( qlen ), NULL ) + != PNIC_STATUS_OK ) + return; + if ( qlen == 0 ) + return; + iobuf = alloc_iob ( ETH_FRAME_LEN ); + if ( ! iobuf ) { + DBG ( "could not allocate buffer\n" ); + netdev_rx_err ( netdev, NULL, -ENOMEM ); + return; + } + if ( pnic_command ( pnic, PNIC_CMD_RECV, NULL, 0, + iobuf->data, ETH_FRAME_LEN, &length ) + != PNIC_STATUS_OK ) { + netdev_rx_err ( netdev, iobuf, -EIO ); + return; + } + iob_put ( iobuf, length ); + netdev_rx ( netdev, iobuf ); + } +} + +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static int pnic_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) { + struct pnic *pnic = netdev->priv; + + /* Pad the packet */ + iob_pad ( iobuf, ETH_ZLEN ); + + /* Send packet */ + pnic_command ( pnic, PNIC_CMD_XMIT, iobuf->data, iob_len ( iobuf ), + NULL, 0, NULL ); + + netdev_tx_complete ( netdev, iobuf ); + return 0; +} + +/************************************************************************** +OPEN - Open network device +***************************************************************************/ +static int pnic_open ( struct net_device *netdev __unused ) { + /* Nothing to do */ + return 0; +} + +/************************************************************************** +CLOSE - Close network device +***************************************************************************/ +static void pnic_close ( struct net_device *netdev __unused ) { + /* Nothing to do */ +} + +/************************************************************************** +IRQ - Enable/disable interrupts +***************************************************************************/ +static void pnic_irq ( struct net_device *netdev, int enable ) { + struct pnic *pnic = netdev->priv; + uint8_t mask = ( enable ? 1 : 0 ); + + pnic_command ( pnic, PNIC_CMD_MASK_IRQ, &mask, sizeof ( mask ), + NULL, 0, NULL ); +} + +/************************************************************************** +OPERATIONS TABLE +***************************************************************************/ +static struct net_device_operations pnic_operations = { + .open = pnic_open, + .close = pnic_close, + .transmit = pnic_transmit, + .poll = pnic_poll, + .irq = pnic_irq, +}; + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void pnic_remove ( struct pci_device *pci ) { + struct net_device *netdev = pci_get_drvdata ( pci ); + struct pnic *pnic = netdev->priv; + + unregister_netdev ( netdev ); + pnic_command ( pnic, PNIC_CMD_RESET, NULL, 0, NULL, 0, NULL ); + netdev_nullify ( netdev ); + netdev_put ( netdev ); +} + +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +***************************************************************************/ +static int pnic_probe ( struct pci_device *pci, + const struct pci_device_id *id __unused ) { + struct net_device *netdev; + struct pnic *pnic; + uint16_t api_version; + uint16_t status; + int rc; + + /* Allocate net device */ + netdev = alloc_etherdev ( sizeof ( *pnic ) ); + if ( ! netdev ) + return -ENOMEM; + netdev_init ( netdev, &pnic_operations ); + pnic = netdev->priv; + pci_set_drvdata ( pci, netdev ); + netdev->dev = &pci->dev; + pnic->ioaddr = pci->ioaddr; + + /* Fix up PCI device */ + adjust_pci_device ( pci ); + + /* API version check */ + status = pnic_command_quiet ( pnic, PNIC_CMD_API_VER, NULL, 0, + &api_version, + sizeof ( api_version ), NULL ); + if ( status != PNIC_STATUS_OK ) { + printf ( "PNIC failed installation check, code %#hx\n", + status ); + rc = -EIO; + goto err; + } + pnic_api_check ( api_version ); + + /* Get MAC address */ + status = pnic_command ( pnic, PNIC_CMD_READ_MAC, NULL, 0, + netdev->hw_addr, ETH_ALEN, NULL ); + + /* Mark as link up; PNIC has no concept of link state */ + netdev_link_up ( netdev ); + + /* Register network device */ + if ( ( rc = register_netdev ( netdev ) ) != 0 ) + goto err; + + return 0; + + err: + /* Free net device */ + netdev_nullify ( netdev ); + netdev_put ( netdev ); + return rc; +} + +static struct pci_device_id pnic_nics[] = { +/* genrules.pl doesn't let us use macros for PCI IDs...*/ +PCI_ROM ( 0xfefe, 0xefef, "pnic", "Bochs Pseudo NIC Adaptor", 0 ), +}; + +struct pci_driver pnic_driver __pci_driver = { + .ids = pnic_nics, + .id_count = ( sizeof ( pnic_nics ) / sizeof ( pnic_nics[0] ) ), + .probe = pnic_probe, + .remove = pnic_remove, +}; diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/pnic_api.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/pnic_api.h new file mode 100644 index 0000000..27e0236 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/pnic_api.h @@ -0,0 +1,61 @@ +/* + * Constants etc. for the Bochs/Etherboot pseudo-NIC + * + * This header file must be valid C and C++. + * + * Operation of the pseudo-NIC (PNIC) is pretty simple. To write a + * command plus data, first write the length of the data to + * PNIC_REG_LEN, then write the data a byte at a type to + * PNIC_REG_DATA, then write the command code to PNIC_REG_CMD. The + * status will be available from PNIC_REG_STAT. The length of any + * data returned will be in PNIC_REG_LEN and can be read a byte at a + * time from PNIC_REG_DATA. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +/* + * PCI parameters + */ +#define PNIC_PCI_VENDOR 0xfefe /* Hopefully these won't clash with */ +#define PNIC_PCI_DEVICE 0xefef /* any real PCI device IDs. */ + +/* + * 'Hardware' register addresses, offset from io_base + */ +#define PNIC_REG_CMD 0x00 /* Command register, 2 bytes, write only */ +#define PNIC_REG_STAT 0x00 /* Status register, 2 bytes, read only */ +#define PNIC_REG_LEN 0x02 /* Length register, 2 bytes, read-write */ +#define PNIC_REG_DATA 0x04 /* Data port, 1 byte, read-write */ +/* + * PNIC_MAX_REG used in Bochs to claim i/o space + */ +#define PNIC_MAX_REG 0x04 + +/* + * Command code definitions: write these into PNIC_REG_CMD + */ +#define PNIC_CMD_NOOP 0x0000 +#define PNIC_CMD_API_VER 0x0001 +#define PNIC_CMD_READ_MAC 0x0002 +#define PNIC_CMD_RESET 0x0003 +#define PNIC_CMD_XMIT 0x0004 +#define PNIC_CMD_RECV 0x0005 +#define PNIC_CMD_RECV_QLEN 0x0006 +#define PNIC_CMD_MASK_IRQ 0x0007 +#define PNIC_CMD_FORCE_IRQ 0x0008 + +/* + * Status code definitions: read these from PNIC_REG_STAT + * + * We avoid using status codes that might be confused with + * randomly-read data (e.g. 0x0000, 0xffff etc.) + */ +#define PNIC_STATUS_OK 0x4f4b /* 'OK' */ +#define PNIC_STATUS_UNKNOWN_CMD 0x3f3f /* '??' */ + +/* + * Other miscellaneous information + */ + +#define PNIC_API_VERSION 0x0101 /* 1.1 */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/prism2.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/prism2.c new file mode 100644 index 0000000..4c66592 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/prism2.c @@ -0,0 +1,857 @@ +/************************************************************************** +Etherboot - BOOTP/TFTP Bootstrap Program +Prism2 NIC driver for Etherboot + +Written by Michael Brown of Fen Systems Ltd +$Id$ +***************************************************************************/ + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2, or (at + * your option) any later version. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <etherboot.h> +#include <nic.h> +#include <gpxe/pci.h> +#include <gpxe/ethernet.h> + +/* + * Hard-coded SSID + * Leave blank in order to connect to any available SSID + */ + +static const char hardcoded_ssid[] = ""; + +/* + * Maximum number of info packets to wait for on a join attempt. + * Some APs (including the Linksys WAP11) will send a "you are disconnected" packet + * before sending the "you are connected" packet, if the card has previously been + * attached to the AP. + * + * 2 is probably a sensible value, but YMMV. + */ + +#define MAX_JOIN_INFO_COUNT 2 + +/* + * Type of Prism2 interface to support + * If not already defined, select PLX + */ +#ifndef WLAN_HOSTIF +#define WLAN_HOSTIF WLAN_PLX +#endif + +/* + * Include wlan_compat, p80211 and hfa384x header files from Linux Prism2 driver + * We need to hack some defines in order to avoid compiling kernel-specific routines + */ + +#define __LINUX_WLAN__ +#undef __KERNEL__ +#define __I386__ +#include "wlan_compat.h" +#include "p80211hdr.h" +#include "hfa384x.h" +#define BAP_TIMEOUT ( 5000 ) + +/* + * A few hacks to make the coding environment more Linux-like. This makes it somewhat + * quicker to convert code from the Linux Prism2 driver. + */ +#include <errno.h> +#define __le16_to_cpu(x) (x) +#define __le32_to_cpu(x) (x) +#define __cpu_to_le16(x) (x) +#define __cpu_to_le32(x) (x) + +#define hfa384x2host_16(n) (__le16_to_cpu((UINT16)(n))) +#define hfa384x2host_32(n) (__le32_to_cpu((UINT32)(n))) +#define host2hfa384x_16(n) (__cpu_to_le16((UINT16)(n))) +#define host2hfa384x_32(n) (__cpu_to_le32((UINT32)(n))) + +/* + * PLX9052 PCI register offsets + * Taken from PLX9052 datasheet available from http://www.plxtech.com/download/9052/databook/9052db-20.pdf + */ + +#define PLX_LOCAL_CONFIG_REGISTER_BASE ( PCI_BASE_ADDRESS_1 ) +#define PLX_LOCAL_ADDRESS_SPACE_0_BASE ( PCI_BASE_ADDRESS_2 ) +#define PLX_LOCAL_ADDRESS_SPACE_1_BASE ( PCI_BASE_ADDRESS_3 ) +#define PLX_LOCAL_ADDRESS_SPACE_2_BASE ( PCI_BASE_ADDRESS_4 ) +#define PLX_LOCAL_ADDRESS_SPACE_3_BASE ( PCI_BASE_ADDRESS_5 ) + +#define PRISM2_PLX_ATTR_MEM_BASE ( PLX_LOCAL_ADDRESS_SPACE_0_BASE ) +#define PRISM2_PLX_IO_BASE ( PLX_LOCAL_ADDRESS_SPACE_1_BASE ) + +#define PRISM2_PCI_MEM_BASE ( PCI_BASE_ADDRESS_0 ) + +/* + * PCMCIA CIS types + * Taken from cistpl.h in pcmcia-cs + */ + +#define CISTPL_VERS_1 ( 0x15 ) +#define CISTPL_END ( 0xff ) + +#define CIS_STEP ( 2 ) +#define CISTPL_HEADER_LEN ( 2 * CIS_STEP ) +#define CISTPL_LEN_OFF ( 1 * CIS_STEP ) +#define CISTPL_VERS_1_STR_OFF ( 4 * CIS_STEP ) + +/* + * Prism2 constants + * Taken from prism2sta.c in linux-wlan-ng + */ + +#define COR_OFFSET ( 0x3e0 ) /* COR attribute offset of Prism2 PC card */ +#define COR_VALUE ( 0x41 ) /* Enable PC card with irq in level trigger (but interrupts disabled) */ + +/* NIC specific static variables */ + +/* The hfa384x_t structure is used extensively in the Linux driver but is ifdef'd out in our include since __KERNEL__ is not defined. + * This is a dummy version that contains only the fields we are interested in. + */ + +typedef struct hfa384x +{ + UINT32 iobase; + void *membase; + UINT16 lastcmd; + UINT16 status; /* in host order */ + UINT16 resp0; /* in host order */ + UINT16 resp1; /* in host order */ + UINT16 resp2; /* in host order */ + UINT8 bssid[WLAN_BSSID_LEN]; +} hfa384x_t; + +/* The global instance of the hardware (i.e. where we store iobase and membase, in the absence of anywhere better to put them */ +static hfa384x_t hw_global = { + 0, 0, 0, 0, 0, 0, 0, {0,0,0,0,0,0} +}; + +/* + * 802.11 headers in addition to those in hfa384x_tx_frame_t (LLC and SNAP) + * Taken from p80211conv.h + */ + +typedef struct wlan_llc +{ + UINT8 dsap; + UINT8 ssap; + UINT8 ctl; +} wlan_llc_t; + +static const wlan_llc_t wlan_llc_snap = { 0xaa, 0xaa, 0x03 }; /* LLC header indicating SNAP (?) */ + +#define WLAN_IEEE_OUI_LEN 3 +typedef struct wlan_snap +{ + UINT8 oui[WLAN_IEEE_OUI_LEN]; + UINT16 type; +} wlan_snap_t; + +typedef struct wlan_80211hdr +{ + wlan_llc_t llc; + wlan_snap_t snap; +} wlan_80211hdr_t; + +/* + * Function prototypes + */ + +/* + * Hardware-level hfa384x functions + * These are based on the ones in hfa384x.h (which are ifdef'd out since __KERNEL__ is not defined). + * Basically, these functions are the result of hand-evaluating all the ifdefs and defines in the hfa384x.h versions. + */ + +/* Retrieve the value of one of the MAC registers. */ +static inline UINT16 hfa384x_getreg( hfa384x_t *hw, UINT reg ) +{ +#if (WLAN_HOSTIF == WLAN_PLX) + return inw ( hw->iobase + reg ); +#elif (WLAN_HOSTIF == WLAN_PCI) + return readw ( hw->membase + reg ); +#endif +} + +/* Set the value of one of the MAC registers. */ +static inline void hfa384x_setreg( hfa384x_t *hw, UINT16 val, UINT reg ) +{ +#if (WLAN_HOSTIF == WLAN_PLX) + outw ( val, hw->iobase + reg ); +#elif (WLAN_HOSTIF == WLAN_PCI) + writew ( val, hw->membase + reg ); +#endif + return; +} + +/* + * Noswap versions + * Etherboot is i386 only, so swap and noswap are the same... + */ +static inline UINT16 hfa384x_getreg_noswap( hfa384x_t *hw, UINT reg ) +{ + return hfa384x_getreg ( hw, reg ); +} +static inline void hfa384x_setreg_noswap( hfa384x_t *hw, UINT16 val, UINT reg ) +{ + hfa384x_setreg ( hw, val, reg ); +} + +/* + * Low-level hfa384x functions + * These are based on the ones in hfa384x.c, modified to work in the Etherboot environment. + */ + +/* + * hfa384x_docmd_wait + * + * Waits for availability of the Command register, then + * issues the given command. Then polls the Evstat register + * waiting for command completion. + * Arguments: + * hw device structure + * cmd Command in host order + * parm0 Parameter0 in host order + * parm1 Parameter1 in host order + * parm2 Parameter2 in host order + * Returns: + * 0 success + * >0 command indicated error, Status and Resp0-2 are + * in hw structure. + */ +static int hfa384x_docmd_wait( hfa384x_t *hw, UINT16 cmd, UINT16 parm0, UINT16 parm1, UINT16 parm2) +{ + UINT16 reg = 0; + UINT16 counter = 0; + + /* wait for the busy bit to clear */ + counter = 0; + reg = hfa384x_getreg(hw, HFA384x_CMD); + while ( HFA384x_CMD_ISBUSY(reg) && (counter < 10) ) { + reg = hfa384x_getreg(hw, HFA384x_CMD); + counter++; + udelay(10); + } + if (HFA384x_CMD_ISBUSY(reg)) { + printf("hfa384x_cmd timeout(1), reg=0x%0hx.\n", reg); + return -ETIMEDOUT; + } + + /* busy bit clear, write command */ + hfa384x_setreg(hw, parm0, HFA384x_PARAM0); + hfa384x_setreg(hw, parm1, HFA384x_PARAM1); + hfa384x_setreg(hw, parm2, HFA384x_PARAM2); + hw->lastcmd = cmd; + hfa384x_setreg(hw, cmd, HFA384x_CMD); + + /* Now wait for completion */ + counter = 0; + reg = hfa384x_getreg(hw, HFA384x_EVSTAT); + /* Initialization is the problem. It takes about + 100ms. "normal" commands are typically is about + 200-400 us (I've never seen less than 200). Longer + is better so that we're not hammering the bus. */ + while ( !HFA384x_EVSTAT_ISCMD(reg) && (counter < 5000)) { + reg = hfa384x_getreg(hw, HFA384x_EVSTAT); + counter++; + udelay(200); + } + if ( ! HFA384x_EVSTAT_ISCMD(reg) ) { + printf("hfa384x_cmd timeout(2), reg=0x%0hx.\n", reg); + return -ETIMEDOUT; + } + + /* Read status and response */ + hw->status = hfa384x_getreg(hw, HFA384x_STATUS); + hw->resp0 = hfa384x_getreg(hw, HFA384x_RESP0); + hw->resp1 = hfa384x_getreg(hw, HFA384x_RESP1); + hw->resp2 = hfa384x_getreg(hw, HFA384x_RESP2); + hfa384x_setreg(hw, HFA384x_EVACK_CMD, HFA384x_EVACK); + return HFA384x_STATUS_RESULT_GET(hw->status); +} + +/* + * Prepare BAP for access. Assigns FID and RID, sets offset register + * and waits for BAP to become available. + * + * Arguments: + * hw device structure + * id FID or RID, destined for the select register (host order) + * offset An _even_ offset into the buffer for the given FID/RID. + * Returns: + * 0 success + */ +static int hfa384x_prepare_bap(hfa384x_t *hw, UINT16 id, UINT16 offset) +{ + int result = 0; + UINT16 reg; + UINT16 i; + + /* Validate offset, buf, and len */ + if ( (offset > HFA384x_BAP_OFFSET_MAX) || (offset % 2) ) { + result = -EINVAL; + } else { + /* Write fid/rid and offset */ + hfa384x_setreg(hw, id, HFA384x_SELECT0); + udelay(10); + hfa384x_setreg(hw, offset, HFA384x_OFFSET0); + /* Wait for offset[busy] to clear (see BAP_TIMEOUT) */ + i = 0; + do { + reg = hfa384x_getreg(hw, HFA384x_OFFSET0); + if ( i > 0 ) udelay(2); + i++; + } while ( i < BAP_TIMEOUT && HFA384x_OFFSET_ISBUSY(reg)); + if ( i >= BAP_TIMEOUT ) { + /* failure */ + result = reg; + } else if ( HFA384x_OFFSET_ISERR(reg) ){ + /* failure */ + result = reg; + } + } + return result; +} + +/* + * Copy data from BAP to memory. + * + * Arguments: + * hw device structure + * id FID or RID, destined for the select register (host order) + * offset An _even_ offset into the buffer for the given FID/RID. + * buf ptr to array of bytes + * len length of data to transfer in bytes + * Returns: + * 0 success + */ +static int hfa384x_copy_from_bap(hfa384x_t *hw, UINT16 id, UINT16 offset, + void *buf, UINT len) +{ + int result = 0; + UINT8 *d = (UINT8*)buf; + UINT16 i; + UINT16 reg = 0; + + /* Prepare BAP */ + result = hfa384x_prepare_bap ( hw, id, offset ); + if ( result == 0 ) { + /* Read even(len) buf contents from data reg */ + for ( i = 0; i < (len & 0xfffe); i+=2 ) { + *(UINT16*)(&(d[i])) = hfa384x_getreg_noswap(hw, HFA384x_DATA0); + } + /* If len odd, handle last byte */ + if ( len % 2 ){ + reg = hfa384x_getreg_noswap(hw, HFA384x_DATA0); + d[len-1] = ((UINT8*)(®))[0]; + } + } + if (result) { + printf ( "copy_from_bap(%#hx, %#hx, %d) failed, result=%#hx\n", id, offset, len, result); + } + return result; +} + +/* + * Copy data from memory to BAP. + * + * Arguments: + * hw device structure + * id FID or RID, destined for the select register (host order) + * offset An _even_ offset into the buffer for the given FID/RID. + * buf ptr to array of bytes + * len length of data to transfer in bytes + * Returns: + * 0 success + */ +static int hfa384x_copy_to_bap(hfa384x_t *hw, UINT16 id, UINT16 offset, + void *buf, UINT len) +{ + int result = 0; + UINT8 *d = (UINT8*)buf; + UINT16 i; + UINT16 savereg; + + /* Prepare BAP */ + result = hfa384x_prepare_bap ( hw, id, offset ); + if ( result == 0 ) { + /* Write even(len) buf contents to data reg */ + for ( i = 0; i < (len & 0xfffe); i+=2 ) { + hfa384x_setreg_noswap(hw, *(UINT16*)(&(d[i])), HFA384x_DATA0); + } + /* If len odd, handle last byte */ + if ( len % 2 ){ + savereg = hfa384x_getreg_noswap(hw, HFA384x_DATA0); + result = hfa384x_prepare_bap ( hw, id, offset + (len & 0xfffe) ); + if ( result == 0 ) { + ((UINT8*)(&savereg))[0] = d[len-1]; + hfa384x_setreg_noswap(hw, savereg, HFA384x_DATA0); + } + } + } + if (result) { + printf ( "copy_to_bap(%#hx, %#hx, %d) failed, result=%#hx\n", id, offset, len, result); + } + return result; +} + +/* + * Request a given record to be copied to/from the record buffer. + * + * Arguments: + * hw device structure + * write [0|1] copy the record buffer to the given + * configuration record. (host order) + * rid RID of the record to read/write. (host order) + * + * Returns: + * 0 success + */ +static inline int hfa384x_cmd_access(hfa384x_t *hw, UINT16 write, UINT16 rid) +{ + return hfa384x_docmd_wait(hw, HFA384x_CMD_CMDCODE_SET(HFA384x_CMDCODE_ACCESS) | HFA384x_CMD_WRITE_SET(write), rid, 0, 0); +} + +/* + * Performs the sequence necessary to read a config/info item. + * + * Arguments: + * hw device structure + * rid config/info record id (host order) + * buf host side record buffer. Upon return it will + * contain the body portion of the record (minus the + * RID and len). + * len buffer length (in bytes, should match record length) + * + * Returns: + * 0 success + */ +static int hfa384x_drvr_getconfig(hfa384x_t *hw, UINT16 rid, void *buf, UINT16 len) +{ + int result = 0; + hfa384x_rec_t rec; + + /* Request read of RID */ + result = hfa384x_cmd_access( hw, 0, rid); + if ( result ) { + printf("Call to hfa384x_cmd_access failed\n"); + return -1; + } + /* Copy out record length */ + result = hfa384x_copy_from_bap( hw, rid, 0, &rec, sizeof(rec)); + if ( result ) { + return -1; + } + /* Validate the record length */ + if ( ((hfa384x2host_16(rec.reclen)-1)*2) != len ) { /* note body len calculation in bytes */ + printf ( "RID len mismatch, rid=%#hx hlen=%d fwlen=%d\n", rid, len, (hfa384x2host_16(rec.reclen)-1)*2); + return -1; + } + /* Copy out record data */ + result = hfa384x_copy_from_bap( hw, rid, sizeof(rec), buf, len); + return result; +} + +/* + * Performs the sequence necessary to read a 16/32 bit config/info item + * and convert it to host order. + * + * Arguments: + * hw device structure + * rid config/info record id (in host order) + * val ptr to 16/32 bit buffer to receive value (in host order) + * + * Returns: + * 0 success + */ +#if 0 /* Not actually used anywhere */ +static int hfa384x_drvr_getconfig16(hfa384x_t *hw, UINT16 rid, void *val) +{ + int result = 0; + result = hfa384x_drvr_getconfig(hw, rid, val, sizeof(UINT16)); + if ( result == 0 ) { + *((UINT16*)val) = hfa384x2host_16(*((UINT16*)val)); + } + return result; +} +#endif +#if 0 /* Not actually used anywhere */ +static int hfa384x_drvr_getconfig32(hfa384x_t *hw, UINT16 rid, void *val) +{ + int result = 0; + result = hfa384x_drvr_getconfig(hw, rid, val, sizeof(UINT32)); + if ( result == 0 ) { + *((UINT32*)val) = hfa384x2host_32(*((UINT32*)val)); + } + return result; +} +#endif + +/* + * Performs the sequence necessary to write a config/info item. + * + * Arguments: + * hw device structure + * rid config/info record id (in host order) + * buf host side record buffer + * len buffer length (in bytes) + * + * Returns: + * 0 success + */ +static int hfa384x_drvr_setconfig(hfa384x_t *hw, UINT16 rid, void *buf, UINT16 len) +{ + int result = 0; + hfa384x_rec_t rec; + + rec.rid = host2hfa384x_16(rid); + rec.reclen = host2hfa384x_16((len/2) + 1); /* note conversion to words, +1 for rid field */ + /* write the record header */ + result = hfa384x_copy_to_bap( hw, rid, 0, &rec, sizeof(rec)); + if ( result ) { + printf("Failure writing record header\n"); + return -1; + } + /* write the record data (if there is any) */ + if ( len > 0 ) { + result = hfa384x_copy_to_bap( hw, rid, sizeof(rec), buf, len); + if ( result ) { + printf("Failure writing record data\n"); + return -1; + } + } + /* Trigger setting of record */ + result = hfa384x_cmd_access( hw, 1, rid); + return result; +} + +/* + * Performs the sequence necessary to write a 16/32 bit config/info item. + * + * Arguments: + * hw device structure + * rid config/info record id (in host order) + * val 16/32 bit value to store (in host order) + * + * Returns: + * 0 success + */ +static int hfa384x_drvr_setconfig16(hfa384x_t *hw, UINT16 rid, UINT16 *val) +{ + UINT16 value; + value = host2hfa384x_16(*val); + return hfa384x_drvr_setconfig(hw, rid, &value, sizeof(UINT16)); +} +#if 0 /* Not actually used anywhere */ +static int hfa384x_drvr_setconfig32(hfa384x_t *hw, UINT16 rid, UINT32 *val) +{ + UINT32 value; + value = host2hfa384x_32(*val); + return hfa384x_drvr_setconfig(hw, rid, &value, sizeof(UINT32)); +} +#endif + +/* + * Wait for an event, with specified checking interval and timeout. + * Automatically acknolwedges events. + * + * Arguments: + * hw device structure + * event_mask EVSTAT register mask of events to wait for + * event_ack EVACK register set of events to be acknowledged if they happen (can be + * used to acknowledge "ignorable" events in addition to the "main" event) + * wait Time (in us) to wait between each poll of the register + * timeout Maximum number of polls before timing out + * descr Descriptive text string of what is being waited for + * (will be printed out if a timeout happens) + * + * Returns: + * value of EVSTAT register, or 0 on failure + */ +static int hfa384x_wait_for_event(hfa384x_t *hw, UINT16 event_mask, UINT16 event_ack, int wait, int timeout, const char *descr) +{ + UINT16 reg; + int count = 0; + + do { + reg = hfa384x_getreg(hw, HFA384x_EVSTAT); + if ( count > 0 ) udelay(wait); + count++; + } while ( !(reg & event_mask) && count < timeout); + if ( count >= timeout ) { + printf("hfa384x: Timed out waiting for %s\n", descr); + return 0; /* Return failure */ + } + /* Acknowledge all events that we were waiting on */ + hfa384x_setreg(hw, reg & ( event_mask | event_ack ), HFA384x_EVACK); + return reg; +} + +/************************************************************************** +POLL - Wait for a frame +***************************************************************************/ +static int prism2_poll(struct nic *nic, int retrieve) +{ + UINT16 reg; + UINT16 rxfid; + UINT16 result; + hfa384x_rx_frame_t rxdesc; + hfa384x_t *hw = &hw_global; + + /* Check for received packet */ + reg = hfa384x_getreg(hw, HFA384x_EVSTAT); + if ( ! HFA384x_EVSTAT_ISRX(reg) ) { + /* No packet received - return 0 */ + return 0; + } + + if ( ! retrieve ) return 1; + + /* Acknowledge RX event */ + hfa384x_setreg(hw, HFA384x_EVACK_RX_SET(1), HFA384x_EVACK); + /* Get RX FID */ + rxfid = hfa384x_getreg(hw, HFA384x_RXFID); + /* Get the descriptor (including headers) */ + result = hfa384x_copy_from_bap(hw, rxfid, 0, &rxdesc, sizeof(rxdesc)); + if ( result ) { + return 0; /* fail */ + } + /* Byte order convert once up front. */ + rxdesc.status = hfa384x2host_16(rxdesc.status); + rxdesc.time = hfa384x2host_32(rxdesc.time); + rxdesc.data_len = hfa384x2host_16(rxdesc.data_len); + + /* Fill in nic->packetlen */ + nic->packetlen = rxdesc.data_len; + if ( nic->packetlen > 0 ) { + /* Fill in nic->packet */ + /* + * NOTE: Packets as received have an 8-byte header (LLC+SNAP(?)) terminating with the packet type. + * Etherboot expects a 14-byte header terminating with the packet type (it ignores the rest of the + * header), so we use a quick hack to achieve this. + */ + result = hfa384x_copy_from_bap(hw, rxfid, HFA384x_RX_DATA_OFF, + nic->packet + ETH_HLEN - sizeof(wlan_80211hdr_t), nic->packetlen); + if ( result ) { + return 0; /* fail */ + } + } + return 1; /* Packet successfully received */ +} + +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static void prism2_transmit( + struct nic *nic, + const char *d, /* Destination */ + unsigned int t, /* Type */ + unsigned int s, /* size */ + const char *p) /* Packet */ +{ + hfa384x_t *hw = &hw_global; + hfa384x_tx_frame_t txdesc; + wlan_80211hdr_t p80211hdr = { wlan_llc_snap, {{0,0,0},0} }; + UINT16 fid; + UINT16 status; + int result; + + // Request FID allocation + result = hfa384x_docmd_wait(hw, HFA384x_CMD_CMDCODE_SET(HFA384x_CMDCODE_ALLOC), HFA384x_DRVR_TXBUF_MAX, 0, 0); + if (result != 0) { + printf("hfa384x: Tx FID allocate command failed: Aborting transmit..\n"); + return; + } + if ( !hfa384x_wait_for_event(hw, HFA384x_EVSTAT_ALLOC, HFA384x_EVACK_INFO, 10, 50, "Tx FID to be allocated\n" ) ) return; + fid = hfa384x_getreg(hw, HFA384x_ALLOCFID); + + /* Build Tx frame structure */ + memset(&txdesc, 0, sizeof(txdesc)); + txdesc.tx_control = host2hfa384x_16( HFA384x_TX_MACPORT_SET(0) | HFA384x_TX_STRUCTYPE_SET(1) | + HFA384x_TX_TXEX_SET(1) | HFA384x_TX_TXOK_SET(1) ); + txdesc.frame_control = host2ieee16( WLAN_SET_FC_FTYPE(WLAN_FTYPE_DATA) | + WLAN_SET_FC_FSTYPE(WLAN_FSTYPE_DATAONLY) | + WLAN_SET_FC_TODS(1) ); + memcpy(txdesc.address1, hw->bssid, WLAN_ADDR_LEN); + memcpy(txdesc.address2, nic->node_addr, WLAN_ADDR_LEN); + memcpy(txdesc.address3, d, WLAN_ADDR_LEN); + txdesc.data_len = host2hfa384x_16( sizeof(txdesc) + sizeof(p80211hdr) + s ); + /* Set up SNAP header */ + /* Let OUI default to RFC1042 (0x000000) */ + p80211hdr.snap.type = htons(t); + + /* Copy txdesc, p80211hdr and payload parts to FID */ + result = hfa384x_copy_to_bap(hw, fid, 0, &txdesc, sizeof(txdesc)); + if ( result ) return; /* fail */ + result = hfa384x_copy_to_bap( hw, fid, sizeof(txdesc), &p80211hdr, sizeof(p80211hdr) ); + if ( result ) return; /* fail */ + result = hfa384x_copy_to_bap( hw, fid, sizeof(txdesc) + sizeof(p80211hdr), (UINT8*)p, s ); + if ( result ) return; /* fail */ + + /* Issue Tx command */ + result = hfa384x_docmd_wait(hw, HFA384x_CMD_CMDCODE_SET(HFA384x_CMDCODE_TX), fid, 0, 0); + if ( result != 0 ) { + printf("hfa384x: Transmit failed with result %#hx.\n", result); + return; + } + + /* Wait for transmit completion (or exception) */ + result = hfa384x_wait_for_event(hw, HFA384x_EVSTAT_TXEXC | HFA384x_EVSTAT_TX, HFA384x_EVACK_INFO, + 200, 500, "Tx to complete\n" ); + if ( !result ) return; /* timeout failure */ + if ( HFA384x_EVSTAT_ISTXEXC(result) ) { + fid = hfa384x_getreg(hw, HFA384x_TXCOMPLFID); + printf ( "Tx exception occurred with fid %#hx\n", fid ); + result = hfa384x_copy_from_bap(hw, fid, 0, &status, sizeof(status)); + if ( result ) return; /* fail */ + printf("hfa384x: Tx error occurred (status %#hx):\n", status); + if ( HFA384x_TXSTATUS_ISACKERR(status) ) { printf(" ...acknowledgement error\n"); } + if ( HFA384x_TXSTATUS_ISFORMERR(status) ) { printf(" ...format error\n"); } + if ( HFA384x_TXSTATUS_ISDISCON(status) ) { printf(" ...disconnected error\n"); } + if ( HFA384x_TXSTATUS_ISAGEDERR(status) ) { printf(" ...AGED error\n"); } + if ( HFA384x_TXSTATUS_ISRETRYERR(status) ) { printf(" ...retry error\n"); } + return; /* fail */ + } +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void prism2_disable ( struct nic *nic __unused ) { + /* put the card in its initial state */ +} + +/************************************************************************** +IRQ - Enable, Disable, or Force interrupts +***************************************************************************/ +static void prism2_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + +/************************************************************************** +Operations table +***************************************************************************/ +static struct nic_operations prism2_operations = { + .connect = dummy_connect, + .poll = prism2_poll, + .transmit = prism2_transmit, + .irq = prism2_irq, +}; + +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +You should omit the last argument struct pci_device * for a non-PCI NIC +***************************************************************************/ +static int prism2_probe ( struct nic *nic, hfa384x_t *hw ) { + int result; + UINT16 tmp16 = 0; + UINT16 infofid; + hfa384x_InfFrame_t inf; + char ssid[HFA384x_RID_CNFDESIREDSSID_LEN]; + int info_count = 0; + + nic->irqno = 0; + + /* Initialize card */ + result = hfa384x_docmd_wait(hw, HFA384x_CMDCODE_INIT, 0,0,0); /* Send initialize command */ + if ( result ) printf ( "Initialize command returned %#hx\n", result ); + hfa384x_setreg(hw, 0, HFA384x_INTEN); /* Disable interrupts */ + hfa384x_setreg(hw, 0xffff, HFA384x_EVACK); /* Acknowledge any spurious events */ + + DBG ( "MAC address %s\n", eth_ntoa ( nic->node_addr ) ); + + /* Retrieve MAC address (and fill out nic->node_addr) */ + hfa384x_drvr_getconfig ( hw, HFA384x_RID_CNFOWNMACADDR, nic->node_addr, HFA384x_RID_CNFOWNMACADDR_LEN ); + + /* Prepare card for autojoin */ + /* This procedure is reverse-engineered from a register-level trace of the Linux driver's join process */ + tmp16 = WLAN_DATA_MAXLEN; /* Set maximum data length */ + result = hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFMAXDATALEN, &tmp16); + if ( result ) printf ( "Set Max Data Length command returned %#hx\n", result ); + tmp16 = 0x000f; /* Set transmit rate(?) */ + result = hfa384x_drvr_setconfig16(hw, HFA384x_RID_TXRATECNTL, &tmp16); + if ( result ) printf ( "Set Transmit Rate command returned %#hx\n", result ); + tmp16 = HFA384x_CNFAUTHENTICATION_OPENSYSTEM; /* Set authentication type to OpenSystem */ + result = hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFAUTHENTICATION, &tmp16); + if ( result ) printf ( "Set Authentication Type command returned %#hx\n", result ); + /* Set SSID */ + memset(ssid, 0, HFA384x_RID_CNFDESIREDSSID_LEN); + for ( tmp16=0; tmp16<sizeof(hardcoded_ssid); tmp16++ ) { ssid[2+tmp16] = hardcoded_ssid[tmp16]; } + ssid[0] = sizeof(hardcoded_ssid) - 1; /* Ignore terminating zero */ + result = hfa384x_drvr_setconfig(hw, HFA384x_RID_CNFDESIREDSSID, ssid, HFA384x_RID_CNFDESIREDSSID_LEN); /* Set the SSID */ + if ( result ) printf ( "Set SSID command returned %#hx\n", result ); + tmp16 = 1; /* Set port type to ESS port */ + result = hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFPORTTYPE, &tmp16); + if ( result ) printf ( "Set port type command returned %#hx\n", result ); + /* Enable card */ + result = hfa384x_docmd_wait(hw, HFA384x_CMD_CMDCODE_SET(HFA384x_CMDCODE_ENABLE) | HFA384x_CMD_MACPORT_SET(0), 0,0,0); + if ( result ) printf ( "Enable command returned %#hx\n", result ); + + do { + /* Increment info_count, abort if too many attempts. + * See comment next to definition of MAX_JOIN_INFO_COUNT for explanation. + */ + info_count++; + if ( info_count > MAX_JOIN_INFO_COUNT ) { + printf ( "Too many failed attempts - aborting\n" ); + return 0; + } + + /* Wait for info frame to indicate link status */ + if ( sizeof(hardcoded_ssid) == 1 ) { + /* Empty SSID => join to any SSID */ + printf ( "Attempting to autojoin to any available access point (attempt %d)...", info_count ); + } else { + printf ( "Attempting to autojoin to SSID %s (attempt %d)...", &ssid[2], info_count ); + } + + if ( !hfa384x_wait_for_event(hw, HFA384x_EVSTAT_INFO, 0, 1000, 2000, "Info event" ) ) return 0; + printf("done\n"); + infofid = hfa384x_getreg(hw, HFA384x_INFOFID); + /* Retrieve the length */ + result = hfa384x_copy_from_bap( hw, infofid, 0, &inf.framelen, sizeof(UINT16)); + if ( result ) return 0; /* fail */ + inf.framelen = hfa384x2host_16(inf.framelen); + /* Retrieve the rest */ + result = hfa384x_copy_from_bap( hw, infofid, sizeof(UINT16), + &(inf.infotype), inf.framelen * sizeof(UINT16)); + if ( result ) return 0; /* fail */ + if ( inf.infotype != HFA384x_IT_LINKSTATUS ) { + /* Not a Link Status info frame: die */ + printf ( "Unexpected info frame type %#hx (not LinkStatus type)\n", inf.infotype ); + return 0; + } + inf.info.linkstatus.linkstatus = hfa384x2host_16(inf.info.linkstatus.linkstatus); + if ( inf.info.linkstatus.linkstatus != HFA384x_LINK_CONNECTED ) { + /* Link not connected - retry */ + printf ( "Link not connected (status %#hx)\n", inf.info.linkstatus.linkstatus ); + } + } while ( inf.info.linkstatus.linkstatus != HFA384x_LINK_CONNECTED ); + + /* Retrieve BSSID and print Connected message */ + result = hfa384x_drvr_getconfig(hw, HFA384x_RID_CURRENTBSSID, hw->bssid, WLAN_BSSID_LEN); + + DBG ( "Link connected (BSSID %s - ", eth_ntoa ( hw->bssid ) ); + DBG ( " MAC address %s)\n", eth_ntoa (nic->node_addr ) ); + + /* point to NIC specific routines */ + nic->nic_op = &prism2_operations; + return 1; +} + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/prism2_pci.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/prism2_pci.c new file mode 100644 index 0000000..b7c1e6b --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/prism2_pci.c @@ -0,0 +1,58 @@ +/************************************************************************** +Etherboot - BOOTP/TFTP Bootstrap Program +Prism2 NIC driver for Etherboot +Wrapper for prism2_pci + +Written by Michael Brown of Fen Systems Ltd +$Id$ +***************************************************************************/ + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2, or (at + * your option) any later version. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <gpxe/pci.h> +#include <nic.h> + +#define WLAN_HOSTIF WLAN_PCI +#include "prism2.c" + +static int prism2_pci_probe ( struct nic *nic, struct pci_device *pci ) { + hfa384x_t *hw = &hw_global; + + printf ( "Prism2.5 has registers at %#lx\n", pci->membase ); + hw->membase = ioremap ( pci->membase, 0x100 ); + + nic->ioaddr = pci->membase; + nic->irqno = 0; + + return prism2_probe ( nic, hw ); +} + +static void prism2_pci_disable ( struct nic *nic ) { + prism2_disable ( nic ); +} + +static struct pci_device_id prism2_pci_nics[] = { +PCI_ROM(0x1260, 0x3873, "prism2_pci", "Harris Semiconductor Prism2.5 clone", 0), +PCI_ROM(0x1260, 0x3873, "hwp01170", "ActionTec HWP01170", 0), +PCI_ROM(0x1260, 0x3873, "dwl520", "DLink DWL-520", 0), +}; + +PCI_DRIVER ( prism2_pci_driver, prism2_pci_nics, PCI_NO_CLASS ); + +DRIVER ( "Prism2/PCI", nic_driver, pci_driver, prism2_pci_driver, + prism2_pci_probe, prism2_pci_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/prism2_plx.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/prism2_plx.c new file mode 100644 index 0000000..9fb5be2 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/prism2_plx.c @@ -0,0 +1,122 @@ +/************************************************************************** +Etherboot - BOOTP/TFTP Bootstrap Program +Prism2 NIC driver for Etherboot +Wrapper for prism2_plx + +Written by Michael Brown of Fen Systems Ltd +$Id$ +***************************************************************************/ + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2, or (at + * your option) any later version. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <gpxe/pci.h> +#include <nic.h> + +#define WLAN_HOSTIF WLAN_PLX +#include "prism2.c" + +/* + * Find PLX card. Prints out information strings from PCMCIA CIS as visual + * confirmation of presence of card. + * + * Arguments: + * hw device structure to be filled in + * p PCI device structure + * + * Returns: + * 1 Success + */ +static int prism2_find_plx ( hfa384x_t *hw, struct pci_device *p ) +{ + int found = 0; + uint32_t plx_lcr = 0; /* PLX9052 Local Configuration Register Base (I/O) */ + uint32_t attr_mem = 0; /* Prism2 Attribute Memory Base */ + uint32_t iobase = 0; /* Prism2 I/O Base */ + unsigned char *cis_tpl = NULL; + unsigned char *cis_string; + + /* Obtain all memory and IO base addresses */ + pci_read_config_dword( p, PLX_LOCAL_CONFIG_REGISTER_BASE, &plx_lcr); + plx_lcr &= PCI_BASE_ADDRESS_IO_MASK; + pci_read_config_dword( p, PRISM2_PLX_ATTR_MEM_BASE, &attr_mem); + pci_read_config_dword( p, PRISM2_PLX_IO_BASE, &iobase); + iobase &= PCI_BASE_ADDRESS_IO_MASK; + + /* Fill out hw structure */ + hw->iobase = iobase; + printf ( "PLX9052 has local config registers at %#x\n", plx_lcr ); + printf ( "Prism2 has attribute memory at %#x and I/O base at %#x\n", attr_mem, iobase ); + + /* Search for CIS strings */ + printf ( "Searching for PCMCIA card...\n" ); + cis_tpl = bus_to_virt(attr_mem); + while ( *cis_tpl != CISTPL_END ) { + if ( *cis_tpl == CISTPL_VERS_1 ) { + /* CISTPL_VERS_1 contains some nice text strings */ + printf ( "...found " ); + found = 1; + cis_string = cis_tpl + CISTPL_VERS_1_STR_OFF; + while ( ! ( ( *cis_string == 0 ) && ( *(cis_string+CIS_STEP) == 0 ) ) ) { + printf ( "%c", *cis_string == 0 ? ' ' : *cis_string ); + cis_string += CIS_STEP; + } + printf ( "\n" ); + } + /* printf ( "CIS tuple type %#hhx, length %#hhx\n", *cis_tpl, *(cis_tpl+CISTPL_LEN_OFF) ); */ + cis_tpl += CISTPL_HEADER_LEN + CIS_STEP * ( *(cis_tpl+CISTPL_LEN_OFF) ); + } + if ( found == 0 ) { + printf ( "...nothing found\n" ); + } + ((unsigned char *)bus_to_virt(attr_mem))[COR_OFFSET] = COR_VALUE; /* Write COR to enable PC card */ + return found; +} + +static int prism2_plx_probe ( struct nic *nic, struct pci_device *pci ) { + hfa384x_t *hw = &hw_global; + + /* Find and intialise PLX Prism2 card */ + if ( ! prism2_find_plx ( hw, pci ) ) return 0; + nic->ioaddr = hw->iobase; + nic->irqno = 0; + return prism2_probe ( nic, hw ); +} + +static void prism2_plx_disable ( struct nic *nic ) { + prism2_disable ( nic ); +} + +static struct pci_device_id prism2_plx_nics[] = { +PCI_ROM(0x1385, 0x4100, "ma301", "Netgear MA301", 0), +PCI_ROM(0x10b7, 0x7770, "3c-airconnect", "3Com AirConnect", 0), +PCI_ROM(0x111a, 0x1023, "ss1023", "Siemens SpeedStream SS1023", 0), +PCI_ROM(0x15e8, 0x0130, "correga", "Correga", 0), +PCI_ROM(0x1638, 0x1100, "smc2602w", "SMC EZConnect SMC2602W", 0), /* or Eumitcom PCI WL11000, Addtron AWA-100 */ +PCI_ROM(0x16ab, 0x1100, "gl24110p", "Global Sun Tech GL24110P", 0), +PCI_ROM(0x16ab, 0x1101, "16ab-1101", "Unknown", 0), +PCI_ROM(0x16ab, 0x1102, "wdt11", "Linksys WDT11", 0), +PCI_ROM(0x16ec, 0x3685, "usr2415", "USR 2415", 0), +PCI_ROM(0xec80, 0xec00, "f5d6000", "Belkin F5D6000", 0), +PCI_ROM(0x126c, 0x8030, "emobility", "Nortel emobility", 0), +}; + +PCI_DRIVER ( prism2_plx_driver, prism2_plx_nics, PCI_NO_CLASS ); + + +DRIVER ( "Prism2/PLX", nic_driver, pci_driver, prism2_plx_driver, + prism2_plx_probe, prism2_plx_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/r8169.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/r8169.c new file mode 100644 index 0000000..b468782 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/r8169.c @@ -0,0 +1,2285 @@ +/* + * Copyright (c) 2008 Marty Connor <mdc@etherboot.org> + * Copyright (c) 2008 Entity Cyber, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * This driver is based on rtl8169 data sheets and work by: + * + * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> + * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> + * Copyright (c) a lot of people too. Please respect their work. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <stdint.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <assert.h> +#include <byteswap.h> +#include <errno.h> +#include <gpxe/ethernet.h> +#include <gpxe/if_ether.h> +#include <gpxe/io.h> +#include <gpxe/iobuf.h> +#include <gpxe/malloc.h> +#include <gpxe/netdevice.h> +#include <gpxe/pci.h> +#include <gpxe/timer.h> +#include <mii.h> + +#include "r8169.h" + +/*** Low level hardware routines ***/ + +static void mdio_write(void *ioaddr, int reg_addr, int value) +{ + int i; + + DBGP ( "mdio_write\n" ); + + RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); + + for (i = 20; i > 0; i--) { + /* + * Check if the RTL8169 has completed writing to the specified + * MII register. + */ + if (!(RTL_R32(PHYAR) & 0x80000000)) + break; + udelay(25); + } +} + +static int mdio_read(void *ioaddr, int reg_addr) +{ + int i, value = -1; + + DBGP ( "mdio_read\n" ); + + RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); + + for (i = 20; i > 0; i--) { + /* + * Check if the RTL8169 has completed retrieving data from + * the specified MII register. + */ + if (RTL_R32(PHYAR) & 0x80000000) { + value = RTL_R32(PHYAR) & 0xffff; + break; + } + udelay(25); + } + return value; +} + +static void mdio_patch(void *ioaddr, int reg_addr, int value) +{ + DBGP ( "mdio_patch\n" ); + + mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value); +} + +static void rtl_ephy_write(void *ioaddr, int reg_addr, int value) +{ + unsigned int i; + + DBGP ( "rtl_ephy_write\n" ); + + RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | + (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); + + for (i = 0; i < 100; i++) { + if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) + break; + udelay(10); + } +} + +static u16 rtl_ephy_read(void *ioaddr, int reg_addr) +{ + u16 value = 0xffff; + unsigned int i; + + DBGP ( "rtl_ephy_read\n" ); + + RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); + + for (i = 0; i < 100; i++) { + if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { + value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; + break; + } + udelay(10); + } + + return value; +} + +static void rtl_csi_write(void *ioaddr, int addr, int value) +{ + unsigned int i; + + DBGP ( "rtl_csi_write\n" ); + + RTL_W32(CSIDR, value); + RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | + CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); + + for (i = 0; i < 100; i++) { + if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) + break; + udelay(10); + } +} + +static u32 rtl_csi_read(void *ioaddr, int addr) +{ + u32 value = ~0x00; + unsigned int i; + + DBGP ( "rtl_csi_read\n" ); + + RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | + CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); + + for (i = 0; i < 100; i++) { + if (RTL_R32(CSIAR) & CSIAR_FLAG) { + value = RTL_R32(CSIDR); + break; + } + udelay(10); + } + + return value; +} + +static void rtl8169_irq_mask_and_ack(void *ioaddr) +{ + DBGP ( "rtl8169_irq_mask_and_ack\n" ); + + RTL_W16(IntrMask, 0x0000); + + RTL_W16(IntrStatus, 0xffff); +} + +static unsigned int rtl8169_tbi_reset_pending(void *ioaddr) +{ + DBGP ( "rtl8169_tbi_reset_pending\n" ); + + return RTL_R32(TBICSR) & TBIReset; +} + +static unsigned int rtl8169_xmii_reset_pending(void *ioaddr) +{ + DBGP ( "rtl8169_xmii_reset_pending\n" ); + + return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; +} + +static unsigned int rtl8169_tbi_link_ok(void *ioaddr) +{ + DBGP ( "rtl8169_tbi_link_ok\n" ); + + return RTL_R32(TBICSR) & TBILinkOk; +} + +static unsigned int rtl8169_xmii_link_ok(void *ioaddr) +{ + DBGP ( "rtl8169_xmii_link_ok\n" ); + + return RTL_R8(PHYstatus) & LinkStatus; +} + +static void rtl8169_tbi_reset_enable(void *ioaddr) +{ + DBGP ( "rtl8169_tbi_reset_enable\n" ); + + RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); +} + +static void rtl8169_xmii_reset_enable(void *ioaddr) +{ + unsigned int val; + + DBGP ( "rtl8169_xmii_reset_enable\n" ); + + val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; + mdio_write(ioaddr, MII_BMCR, val & 0xffff); +} + +static int rtl8169_set_speed_tbi(struct net_device *dev, + u8 autoneg, u16 speed, u8 duplex) +{ + struct rtl8169_private *tp = netdev_priv(dev); + void *ioaddr = tp->mmio_addr; + int ret = 0; + u32 reg; + + DBGP ( "rtl8169_set_speed_tbi\n" ); + + reg = RTL_R32(TBICSR); + if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && + (duplex == DUPLEX_FULL)) { + RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); + } else if (autoneg == AUTONEG_ENABLE) + RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); + else { + DBG ( "incorrect speed setting refused in TBI mode\n" ); + ret = -EOPNOTSUPP; + } + return ret; +} + +static int rtl8169_set_speed_xmii(struct net_device *dev, + u8 autoneg, u16 speed, u8 duplex) +{ + struct rtl8169_private *tp = netdev_priv(dev); + void *ioaddr = tp->mmio_addr; + int auto_nego, giga_ctrl; + + DBGP ( "rtl8169_set_speed_xmii\n" ); + + auto_nego = mdio_read(ioaddr, MII_ADVERTISE); + auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | + ADVERTISE_100HALF | ADVERTISE_100FULL); + giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); + giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); + + if (autoneg == AUTONEG_ENABLE) { + auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | + ADVERTISE_100HALF | ADVERTISE_100FULL); + giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; + } else { + if (speed == SPEED_10) + auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL; + else if (speed == SPEED_100) + auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL; + else if (speed == SPEED_1000) + giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; + + if (duplex == DUPLEX_HALF) + auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL); + + if (duplex == DUPLEX_FULL) + auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF); + + /* This tweak comes straight from Realtek's driver. */ + if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) && + ((tp->mac_version == RTL_GIGA_MAC_VER_13) || + (tp->mac_version == RTL_GIGA_MAC_VER_16))) { + auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA; + } + } + + /* The 8100e/8101e/8102e do Fast Ethernet only. */ + if ((tp->mac_version == RTL_GIGA_MAC_VER_07) || + (tp->mac_version == RTL_GIGA_MAC_VER_08) || + (tp->mac_version == RTL_GIGA_MAC_VER_09) || + (tp->mac_version == RTL_GIGA_MAC_VER_10) || + (tp->mac_version == RTL_GIGA_MAC_VER_13) || + (tp->mac_version == RTL_GIGA_MAC_VER_14) || + (tp->mac_version == RTL_GIGA_MAC_VER_15) || + (tp->mac_version == RTL_GIGA_MAC_VER_16)) { + if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF))) { + DBG ( "PHY does not support 1000Mbps.\n" ); + } + giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); + } + + auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; + + if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || + (tp->mac_version == RTL_GIGA_MAC_VER_12) || + (tp->mac_version >= RTL_GIGA_MAC_VER_17)) { + /* + * Wake up the PHY. + * Vendor specific (0x1f) and reserved (0x0e) MII registers. + */ + mdio_write(ioaddr, 0x1f, 0x0000); + mdio_write(ioaddr, 0x0e, 0x0000); + } + + tp->phy_auto_nego_reg = auto_nego; + tp->phy_1000_ctrl_reg = giga_ctrl; + + mdio_write(ioaddr, MII_ADVERTISE, auto_nego); + mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); + mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); + return 0; +} + +static int rtl8169_set_speed(struct net_device *dev, + u8 autoneg, u16 speed, u8 duplex) +{ + struct rtl8169_private *tp = netdev_priv(dev); + int ret; + + DBGP ( "rtl8169_set_speed\n" ); + + ret = tp->set_speed(dev, autoneg, speed, duplex); + + return ret; +} + +static void rtl8169_write_gmii_reg_bit(void *ioaddr, int reg, + int bitnum, int bitval) +{ + int val; + + DBGP ( "rtl8169_write_gmii_reg_bit\n" ); + + val = mdio_read(ioaddr, reg); + val = (bitval == 1) ? + val | (bitval << bitnum) : val & ~(0x0001 << bitnum); + mdio_write(ioaddr, reg, val & 0xffff); +} + +static void rtl8169_get_mac_version(struct rtl8169_private *tp, + void *ioaddr) +{ + /* + * The driver currently handles the 8168Bf and the 8168Be identically + * but they can be identified more specifically through the test below + * if needed: + * + * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be + * + * Same thing for the 8101Eb and the 8101Ec: + * + * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec + */ + const struct { + u32 mask; + u32 val; + int mac_version; + } mac_info[] = { + /* 8168D family. */ + { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 }, + + /* 8168C family. */ + { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 }, + { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, + { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, + { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, + { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, + { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, + { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, + { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, + { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, + + /* 8168B family. */ + { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, + { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, + { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, + { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, + + /* 8101 family. */ + { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, + { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, + { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, + { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, + { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, + { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, + { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, + { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, + { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, + { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, + { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, + { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, + /* FIXME: where did these entries come from ? -- FR */ + { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, + { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, + + /* 8110 family. */ + { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, + { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, + { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, + { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, + { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, + { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, + + { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */ + }, *p = mac_info; + u32 reg; + + DBGP ( "rtl8169_get_mac_version\n" ); + + reg = RTL_R32(TxConfig); + while ((reg & p->mask) != p->val) + p++; + tp->mac_version = p->mac_version; + + DBG ( "tp->mac_version = %d\n", tp->mac_version ); + + if (p->mask == 0x00000000) { + DBG ( "unknown MAC (%08x)\n", reg ); + } +} + +struct phy_reg { + u16 reg; + u16 val; +}; + +static void rtl_phy_write(void *ioaddr, struct phy_reg *regs, int len) +{ + DBGP ( "rtl_phy_write\n" ); + + while (len-- > 0) { + mdio_write(ioaddr, regs->reg, regs->val); + regs++; + } +} + +static void rtl8169s_hw_phy_config(void *ioaddr) +{ + struct { + u16 regs[5]; /* Beware of bit-sign propagation */ + } phy_magic[5] = { { + { 0x0000, //w 4 15 12 0 + 0x00a1, //w 3 15 0 00a1 + 0x0008, //w 2 15 0 0008 + 0x1020, //w 1 15 0 1020 + 0x1000 } },{ //w 0 15 0 1000 + { 0x7000, //w 4 15 12 7 + 0xff41, //w 3 15 0 ff41 + 0xde60, //w 2 15 0 de60 + 0x0140, //w 1 15 0 0140 + 0x0077 } },{ //w 0 15 0 0077 + { 0xa000, //w 4 15 12 a + 0xdf01, //w 3 15 0 df01 + 0xdf20, //w 2 15 0 df20 + 0xff95, //w 1 15 0 ff95 + 0xfa00 } },{ //w 0 15 0 fa00 + { 0xb000, //w 4 15 12 b + 0xff41, //w 3 15 0 ff41 + 0xde20, //w 2 15 0 de20 + 0x0140, //w 1 15 0 0140 + 0x00bb } },{ //w 0 15 0 00bb + { 0xf000, //w 4 15 12 f + 0xdf01, //w 3 15 0 df01 + 0xdf20, //w 2 15 0 df20 + 0xff95, //w 1 15 0 ff95 + 0xbf00 } //w 0 15 0 bf00 + } + }, *p = phy_magic; + unsigned int i; + + DBGP ( "rtl8169s_hw_phy_config\n" ); + + mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1 + mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000 + mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7 + rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 + + for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) { + int val, pos = 4; + + val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff); + mdio_write(ioaddr, pos, val); + while (--pos >= 0) + mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff); + rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1 + rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 + } + mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0 +} + +static void rtl8169sb_hw_phy_config(void *ioaddr) +{ + struct phy_reg phy_reg_init[] = { + { 0x1f, 0x0002 }, + { 0x01, 0x90d0 }, + { 0x1f, 0x0000 } + }; + + DBGP ( "rtl8169sb_hw_phy_config\n" ); + + rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); +} + +static void rtl8168bb_hw_phy_config(void *ioaddr) +{ + struct phy_reg phy_reg_init[] = { + { 0x10, 0xf41b }, + { 0x1f, 0x0000 } + }; + + mdio_write(ioaddr, 0x1f, 0x0001); + mdio_patch(ioaddr, 0x16, 1 << 0); + + DBGP ( "rtl8168bb_hw_phy_config\n" ); + + rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); +} + +static void rtl8168bef_hw_phy_config(void *ioaddr) +{ + struct phy_reg phy_reg_init[] = { + { 0x1f, 0x0001 }, + { 0x10, 0xf41b }, + { 0x1f, 0x0000 } + }; + + DBGP ( "rtl8168bef_hw_phy_config\n" ); + + rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); +} + +static void rtl8168cp_1_hw_phy_config(void *ioaddr) +{ + struct phy_reg phy_reg_init[] = { + { 0x1f, 0x0000 }, + { 0x1d, 0x0f00 }, + { 0x1f, 0x0002 }, + { 0x0c, 0x1ec8 }, + { 0x1f, 0x0000 } + }; + + DBGP ( "rtl8168cp_1_hw_phy_config\n" ); + + rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); +} + +static void rtl8168cp_2_hw_phy_config(void *ioaddr) +{ + struct phy_reg phy_reg_init[] = { + { 0x1f, 0x0001 }, + { 0x1d, 0x3d98 }, + { 0x1f, 0x0000 } + }; + + DBGP ( "rtl8168cp_2_hw_phy_config\n" ); + + mdio_write(ioaddr, 0x1f, 0x0000); + mdio_patch(ioaddr, 0x14, 1 << 5); + mdio_patch(ioaddr, 0x0d, 1 << 5); + + rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); +} + +static void rtl8168c_1_hw_phy_config(void *ioaddr) +{ + struct phy_reg phy_reg_init[] = { + { 0x1f, 0x0001 }, + { 0x12, 0x2300 }, + { 0x1f, 0x0002 }, + { 0x00, 0x88d4 }, + { 0x01, 0x82b1 }, + { 0x03, 0x7002 }, + { 0x08, 0x9e30 }, + { 0x09, 0x01f0 }, + { 0x0a, 0x5500 }, + { 0x0c, 0x00c8 }, + { 0x1f, 0x0003 }, + { 0x12, 0xc096 }, + { 0x16, 0x000a }, + { 0x1f, 0x0000 }, + { 0x1f, 0x0000 }, + { 0x09, 0x2000 }, + { 0x09, 0x0000 } + }; + + DBGP ( "rtl8168c_1_hw_phy_config\n" ); + + rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + + mdio_patch(ioaddr, 0x14, 1 << 5); + mdio_patch(ioaddr, 0x0d, 1 << 5); + mdio_write(ioaddr, 0x1f, 0x0000); +} + +static void rtl8168c_2_hw_phy_config(void *ioaddr) +{ + struct phy_reg phy_reg_init[] = { + { 0x1f, 0x0001 }, + { 0x12, 0x2300 }, + { 0x03, 0x802f }, + { 0x02, 0x4f02 }, + { 0x01, 0x0409 }, + { 0x00, 0xf099 }, + { 0x04, 0x9800 }, + { 0x04, 0x9000 }, + { 0x1d, 0x3d98 }, + { 0x1f, 0x0002 }, + { 0x0c, 0x7eb8 }, + { 0x06, 0x0761 }, + { 0x1f, 0x0003 }, + { 0x16, 0x0f0a }, + { 0x1f, 0x0000 } + }; + + DBGP ( "rtl8168c_2_hw_phy_config\n" ); + + rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + + mdio_patch(ioaddr, 0x16, 1 << 0); + mdio_patch(ioaddr, 0x14, 1 << 5); + mdio_patch(ioaddr, 0x0d, 1 << 5); + mdio_write(ioaddr, 0x1f, 0x0000); +} + +static void rtl8168c_3_hw_phy_config(void *ioaddr) +{ + struct phy_reg phy_reg_init[] = { + { 0x1f, 0x0001 }, + { 0x12, 0x2300 }, + { 0x1d, 0x3d98 }, + { 0x1f, 0x0002 }, + { 0x0c, 0x7eb8 }, + { 0x06, 0x5461 }, + { 0x1f, 0x0003 }, + { 0x16, 0x0f0a }, + { 0x1f, 0x0000 } + }; + + DBGP ( "rtl8168c_3_hw_phy_config\n" ); + + rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + + mdio_patch(ioaddr, 0x16, 1 << 0); + mdio_patch(ioaddr, 0x14, 1 << 5); + mdio_patch(ioaddr, 0x0d, 1 << 5); + mdio_write(ioaddr, 0x1f, 0x0000); +} + +static void rtl8168c_4_hw_phy_config(void *ioaddr) +{ + DBGP ( "rtl8168c_4_hw_phy_config\n" ); + + rtl8168c_3_hw_phy_config(ioaddr); +} + +static void rtl8168d_hw_phy_config(void *ioaddr) +{ + struct phy_reg phy_reg_init_0[] = { + { 0x1f, 0x0001 }, + { 0x09, 0x2770 }, + { 0x08, 0x04d0 }, + { 0x0b, 0xad15 }, + { 0x0c, 0x5bf0 }, + { 0x1c, 0xf101 }, + { 0x1f, 0x0003 }, + { 0x14, 0x94d7 }, + { 0x12, 0xf4d6 }, + { 0x09, 0xca0f }, + { 0x1f, 0x0002 }, + { 0x0b, 0x0b10 }, + { 0x0c, 0xd1f7 }, + { 0x1f, 0x0002 }, + { 0x06, 0x5461 }, + { 0x1f, 0x0002 }, + { 0x05, 0x6662 }, + { 0x1f, 0x0000 }, + { 0x14, 0x0060 }, + { 0x1f, 0x0000 }, + { 0x0d, 0xf8a0 }, + { 0x1f, 0x0005 }, + { 0x05, 0xffc2 } + }; + + DBGP ( "rtl8168d_hw_phy_config\n" ); + + rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); + + if (mdio_read(ioaddr, 0x06) == 0xc400) { + struct phy_reg phy_reg_init_1[] = { + { 0x1f, 0x0005 }, + { 0x01, 0x0300 }, + { 0x1f, 0x0000 }, + { 0x11, 0x401c }, + { 0x16, 0x4100 }, + { 0x1f, 0x0005 }, + { 0x07, 0x0010 }, + { 0x05, 0x83dc }, + { 0x06, 0x087d }, + { 0x05, 0x8300 }, + { 0x06, 0x0101 }, + { 0x06, 0x05f8 }, + { 0x06, 0xf9fa }, + { 0x06, 0xfbef }, + { 0x06, 0x79e2 }, + { 0x06, 0x835f }, + { 0x06, 0xe0f8 }, + { 0x06, 0x9ae1 }, + { 0x06, 0xf89b }, + { 0x06, 0xef31 }, + { 0x06, 0x3b65 }, + { 0x06, 0xaa07 }, + { 0x06, 0x81e4 }, + { 0x06, 0xf89a }, + { 0x06, 0xe5f8 }, + { 0x06, 0x9baf }, + { 0x06, 0x06ae }, + { 0x05, 0x83dc }, + { 0x06, 0x8300 }, + }; + + rtl_phy_write(ioaddr, phy_reg_init_1, + ARRAY_SIZE(phy_reg_init_1)); + } + + mdio_write(ioaddr, 0x1f, 0x0000); +} + +static void rtl8102e_hw_phy_config(void *ioaddr) +{ + struct phy_reg phy_reg_init[] = { + { 0x1f, 0x0003 }, + { 0x08, 0x441d }, + { 0x01, 0x9100 }, + { 0x1f, 0x0000 } + }; + + DBGP ( "rtl8102e_hw_phy_config\n" ); + + mdio_write(ioaddr, 0x1f, 0x0000); + mdio_patch(ioaddr, 0x11, 1 << 12); + mdio_patch(ioaddr, 0x19, 1 << 13); + + rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); +} + +static void rtl_hw_phy_config(struct net_device *dev) +{ + struct rtl8169_private *tp = netdev_priv(dev); + void *ioaddr = tp->mmio_addr; + + DBGP ( "rtl_hw_phy_config\n" ); + + DBG ( "mac_version = 0x%02x\n", tp->mac_version ); + + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_01: + break; + case RTL_GIGA_MAC_VER_02: + case RTL_GIGA_MAC_VER_03: + rtl8169s_hw_phy_config(ioaddr); + break; + case RTL_GIGA_MAC_VER_04: + rtl8169sb_hw_phy_config(ioaddr); + break; + case RTL_GIGA_MAC_VER_07: + case RTL_GIGA_MAC_VER_08: + case RTL_GIGA_MAC_VER_09: + rtl8102e_hw_phy_config(ioaddr); + break; + case RTL_GIGA_MAC_VER_11: + rtl8168bb_hw_phy_config(ioaddr); + break; + case RTL_GIGA_MAC_VER_12: + rtl8168bef_hw_phy_config(ioaddr); + break; + case RTL_GIGA_MAC_VER_17: + rtl8168bef_hw_phy_config(ioaddr); + break; + case RTL_GIGA_MAC_VER_18: + rtl8168cp_1_hw_phy_config(ioaddr); + break; + case RTL_GIGA_MAC_VER_19: + rtl8168c_1_hw_phy_config(ioaddr); + break; + case RTL_GIGA_MAC_VER_20: + rtl8168c_2_hw_phy_config(ioaddr); + break; + case RTL_GIGA_MAC_VER_21: + rtl8168c_3_hw_phy_config(ioaddr); + break; + case RTL_GIGA_MAC_VER_22: + rtl8168c_4_hw_phy_config(ioaddr); + break; + case RTL_GIGA_MAC_VER_23: + case RTL_GIGA_MAC_VER_24: + rtl8168cp_2_hw_phy_config(ioaddr); + break; + case RTL_GIGA_MAC_VER_25: + rtl8168d_hw_phy_config(ioaddr); + break; + + default: + break; + } +} + +static void rtl8169_phy_reset(struct net_device *dev __unused, + struct rtl8169_private *tp) +{ + void *ioaddr = tp->mmio_addr; + unsigned int i; + + DBGP ( "rtl8169_phy_reset\n" ); + + tp->phy_reset_enable(ioaddr); + for (i = 0; i < 100; i++) { + if (!tp->phy_reset_pending(ioaddr)) + return; + mdelay ( 1 ); + } + DBG ( "PHY reset failed.\n" ); +} + +static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) +{ + void *ioaddr = tp->mmio_addr; + + DBGP ( "rtl8169_init_phy\n" ); + + rtl_hw_phy_config(dev); + + if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { + DBG ( "Set MAC Reg C+CR Offset 0x82h = 0x01h\n" ); + RTL_W8(0x82, 0x01); + } + + pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); + + if (tp->mac_version <= RTL_GIGA_MAC_VER_06) + pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); + + if (tp->mac_version == RTL_GIGA_MAC_VER_02) { + DBG ( "Set MAC Reg C+CR Offset 0x82h = 0x01h\n" ); + RTL_W8(0x82, 0x01); + DBG ( "Set PHY Reg 0x0bh = 0x00h\n" ); + mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 + } + + rtl8169_phy_reset(dev, tp); + + /* + * rtl8169_set_speed_xmii takes good care of the Fast Ethernet + * only 8101. Don't panic. + */ + rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL); + + if ((RTL_R8(PHYstatus) & TBI_Enable)) + DBG ( "TBI auto-negotiating\n" ); +} + +static const struct rtl_cfg_info { + void (*hw_start)(struct net_device *); + unsigned int region; + unsigned int align; + u16 intr_event; + u16 napi_event; + unsigned features; +} rtl_cfg_infos [] = { + [RTL_CFG_0] = { + .hw_start = rtl_hw_start_8169, + .region = 1, + .align = 0, + .intr_event = SYSErr | LinkChg | RxOverflow | + RxFIFOOver | TxErr | TxOK | RxOK | RxErr, + .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, + .features = RTL_FEATURE_GMII + }, + [RTL_CFG_1] = { + .hw_start = rtl_hw_start_8168, + .region = 2, + .align = 8, + .intr_event = SYSErr | LinkChg | RxOverflow | + TxErr | TxOK | RxOK | RxErr, + .napi_event = TxErr | TxOK | RxOK | RxOverflow, + .features = RTL_FEATURE_GMII + }, + [RTL_CFG_2] = { + .hw_start = rtl_hw_start_8101, + .region = 2, + .align = 8, + .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | + RxFIFOOver | TxErr | TxOK | RxOK | RxErr, + .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, + } +}; + +static void rtl8169_hw_reset(void *ioaddr) +{ + DBGP ( "rtl8169_hw_reset\n" ); + + /* Disable interrupts */ + rtl8169_irq_mask_and_ack(ioaddr); + + /* Reset the chipset */ + RTL_W8(ChipCmd, CmdReset); + + /* PCI commit */ + RTL_R8(ChipCmd); +} + +static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) +{ + void *ioaddr = tp->mmio_addr; + u32 cfg = rtl8169_rx_config; + + DBGP ( "rtl_set_rx_tx_config_registers\n" ); + + cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); + RTL_W32(RxConfig, cfg); + + /* Set DMA burst size and Interframe Gap Time */ + RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | + (InterFrameGap << TxInterFrameGapShift)); +} + +static void rtl_soft_reset ( struct net_device *dev ) +{ + struct rtl8169_private *tp = netdev_priv(dev); + void *ioaddr = tp->mmio_addr; + unsigned int i; + + DBGP ( "rtl_hw_soft_reset\n" ); + + /* Soft reset the chip. */ + RTL_W8(ChipCmd, CmdReset); + + /* Check that the chip has finished the reset. */ + for (i = 0; i < 100; i++) { + if ((RTL_R8(ChipCmd) & CmdReset) == 0) + break; + mdelay ( 1 ); + } + + if ( i == 100 ) { + DBG ( "Reset Failed! (> 100 iterations)\n" ); + } +} + +static void rtl_hw_start ( struct net_device *dev ) +{ + struct rtl8169_private *tp = netdev_priv ( dev ); + + DBGP ( "rtl_hw_start\n" ); + + /* Soft reset NIC */ + rtl_soft_reset ( dev ); + + tp->hw_start ( dev ); +} + +static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, + void *ioaddr) +{ + DBGP ( "rtl_set_rx_tx_desc_registers\n" ); + + /* + * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh + * register to be written before TxDescAddrLow to work. + * Switching from MMIO to I/O access fixes the issue as well. + */ + RTL_W32 ( TxDescStartAddrHigh, 0 ); + RTL_W32 ( TxDescStartAddrLow, virt_to_bus ( tp->tx_base ) ); + RTL_W32 ( RxDescAddrHigh, 0 ); + RTL_W32 ( RxDescAddrLow, virt_to_bus ( tp->rx_base ) ); +} + +static u16 rtl_rw_cpluscmd(void *ioaddr) +{ + u16 cmd; + + DBGP ( "rtl_rw_cpluscmd\n" ); + + cmd = RTL_R16(CPlusCmd); + RTL_W16(CPlusCmd, cmd); + return cmd; +} + +static void rtl_set_rx_max_size(void *ioaddr) +{ + DBGP ( "rtl_set_rx_max_size\n" ); + + RTL_W16 ( RxMaxSize, RX_BUF_SIZE ); +} + +static void rtl8169_set_magic_reg(void *ioaddr, unsigned mac_version) +{ + struct { + u32 mac_version; + u32 clk; + u32 val; + } cfg2_info [] = { + { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd + { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, + { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe + { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } + }, *p = cfg2_info; + unsigned int i; + u32 clk; + + DBGP ( "rtl8169_set_magic_reg\n" ); + + clk = RTL_R8(Config2) & PCI_Clock_66MHz; + for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { + if ((p->mac_version == mac_version) && (p->clk == clk)) { + RTL_W32(0x7c, p->val); + break; + } + } +} + +static void rtl_set_rx_mode ( struct net_device *netdev ) +{ + struct rtl8169_private *tp = netdev_priv ( netdev ); + void *ioaddr = tp->mmio_addr; + u32 tmp; + + DBGP ( "rtl_set_rx_mode\n" ); + + /* Accept all Multicast Packets */ + + RTL_W32 ( MAR0 + 0, 0xffffffff ); + RTL_W32 ( MAR0 + 4, 0xffffffff ); + + tmp = rtl8169_rx_config | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | + ( RTL_R32 ( RxConfig ) & rtl_chip_info[tp->chipset].RxConfigMask ); + + RTL_W32 ( RxConfig, tmp ); +} + +static void rtl_hw_start_8169(struct net_device *dev) +{ + struct rtl8169_private *tp = netdev_priv(dev); + void *ioaddr = tp->mmio_addr; + struct pci_device *pdev = tp->pci_dev; + + DBGP ( "rtl_hw_start_8169\n" ); + + if (tp->mac_version == RTL_GIGA_MAC_VER_05) { + RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); + pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); + } + + RTL_W8(Cfg9346, Cfg9346_Unlock); + + if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || + (tp->mac_version == RTL_GIGA_MAC_VER_02) || + (tp->mac_version == RTL_GIGA_MAC_VER_03) || + (tp->mac_version == RTL_GIGA_MAC_VER_04)) + RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); + + RTL_W8(EarlyTxThres, EarlyTxThld); + + rtl_set_rx_max_size(ioaddr); + + if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || + (tp->mac_version == RTL_GIGA_MAC_VER_02) || + (tp->mac_version == RTL_GIGA_MAC_VER_03) || + (tp->mac_version == RTL_GIGA_MAC_VER_04)) + rtl_set_rx_tx_config_registers(tp); + + tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; + + if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || + (tp->mac_version == RTL_GIGA_MAC_VER_03)) { + DBG ( "Set MAC Reg C+CR Offset 0xE0. " + "Bit-3 and bit-14 MUST be 1\n" ); + tp->cp_cmd |= (1 << 14); + } + + RTL_W16(CPlusCmd, tp->cp_cmd); + + rtl8169_set_magic_reg(ioaddr, tp->mac_version); + + /* + * Undocumented corner. Supposedly: + * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets + */ + RTL_W16(IntrMitigate, 0x0000); + + rtl_set_rx_tx_desc_registers(tp, ioaddr); + + if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && + (tp->mac_version != RTL_GIGA_MAC_VER_02) && + (tp->mac_version != RTL_GIGA_MAC_VER_03) && + (tp->mac_version != RTL_GIGA_MAC_VER_04)) { + RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); + rtl_set_rx_tx_config_registers(tp); + } + + RTL_W8(Cfg9346, Cfg9346_Lock); + + /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ + RTL_R8(IntrMask); + + RTL_W32(RxMissed, 0); + + rtl_set_rx_mode(dev); + + /* no early-rx interrupts */ + RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); + + // RTL_W16(IntrMask, tp->intr_event); +} + +static void rtl_tx_performance_tweak(struct pci_device *pdev, u16 force) +{ + struct net_device *dev = pci_get_drvdata(pdev); + struct rtl8169_private *tp = netdev_priv(dev); + int cap = tp->pcie_cap; + + DBGP ( "rtl_tx_performance_tweak\n" ); + + if (cap) { + u16 ctl; + + pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); + ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; + pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); + } +} + +static void rtl_csi_access_enable(void *ioaddr) +{ + u32 csi; + + DBGP ( "rtl_csi_access_enable\n" ); + + csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; + rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000); +} + +struct ephy_info { + unsigned int offset; + u16 mask; + u16 bits; +}; + +static void rtl_ephy_init(void *ioaddr, struct ephy_info *e, int len) +{ + u16 w; + + DBGP ( "rtl_ephy_init\n" ); + + while (len-- > 0) { + w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; + rtl_ephy_write(ioaddr, e->offset, w); + e++; + } +} + +static void rtl_disable_clock_request(struct pci_device *pdev) +{ + struct net_device *dev = pci_get_drvdata(pdev); + struct rtl8169_private *tp = netdev_priv(dev); + int cap = tp->pcie_cap; + + DBGP ( "rtl_disable_clock_request\n" ); + + if (cap) { + u16 ctl; + + pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); + ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; + pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); + } +} + +#define R8168_CPCMD_QUIRK_MASK (\ + EnableBist | \ + Mac_dbgo_oe | \ + Force_half_dup | \ + Force_rxflow_en | \ + Force_txflow_en | \ + Cxpl_dbg_sel | \ + ASF | \ + PktCntrDisable | \ + Mac_dbgo_sel) + +static void rtl_hw_start_8168bb(void *ioaddr, struct pci_device *pdev) +{ + DBGP ( "rtl_hw_start_8168bb\n" ); + + RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); + + RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); + + rtl_tx_performance_tweak(pdev, + (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); +} + +static void rtl_hw_start_8168bef(void *ioaddr, struct pci_device *pdev) +{ + DBGP ( "rtl_hw_start_8168bef\n" ); + + rtl_hw_start_8168bb(ioaddr, pdev); + + RTL_W8(EarlyTxThres, EarlyTxThld); + + RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); +} + +static void __rtl_hw_start_8168cp(void *ioaddr, struct pci_device *pdev) +{ + DBGP ( "__rtl_hw_start_8168cp\n" ); + + RTL_W8(Config1, RTL_R8(Config1) | Speed_down); + + RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); + + rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); + + rtl_disable_clock_request(pdev); + + RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); +} + +static void rtl_hw_start_8168cp_1(void *ioaddr, struct pci_device *pdev) +{ + static struct ephy_info e_info_8168cp[] = { + { 0x01, 0, 0x0001 }, + { 0x02, 0x0800, 0x1000 }, + { 0x03, 0, 0x0042 }, + { 0x06, 0x0080, 0x0000 }, + { 0x07, 0, 0x2000 } + }; + + DBGP ( "rtl_hw_start_8168cp_1\n" ); + + rtl_csi_access_enable(ioaddr); + + rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); + + __rtl_hw_start_8168cp(ioaddr, pdev); +} + +static void rtl_hw_start_8168cp_2(void *ioaddr, struct pci_device *pdev) +{ + DBGP ( "rtl_hw_start_8168cp_2\n" ); + + rtl_csi_access_enable(ioaddr); + + RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); + + rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); + + RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); +} + +static void rtl_hw_start_8168cp_3(void *ioaddr, struct pci_device *pdev) +{ + DBGP ( "rtl_hw_start_8168cp_3\n" ); + + rtl_csi_access_enable(ioaddr); + + RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); + + /* Magic. */ + RTL_W8(DBG_REG, 0x20); + + RTL_W8(EarlyTxThres, EarlyTxThld); + + rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); + + RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); +} + +static void rtl_hw_start_8168c_1(void *ioaddr, struct pci_device *pdev) +{ + static struct ephy_info e_info_8168c_1[] = { + { 0x02, 0x0800, 0x1000 }, + { 0x03, 0, 0x0002 }, + { 0x06, 0x0080, 0x0000 } + }; + + DBGP ( "rtl_hw_start_8168c_1\n" ); + + rtl_csi_access_enable(ioaddr); + + RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); + + rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); + + __rtl_hw_start_8168cp(ioaddr, pdev); +} + +static void rtl_hw_start_8168c_2(void *ioaddr, struct pci_device *pdev) +{ + static struct ephy_info e_info_8168c_2[] = { + { 0x01, 0, 0x0001 }, + { 0x03, 0x0400, 0x0220 } + }; + + DBGP ( "rtl_hw_start_8168c_2\n" ); + + rtl_csi_access_enable(ioaddr); + + rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); + + __rtl_hw_start_8168cp(ioaddr, pdev); +} + +static void rtl_hw_start_8168c_3(void *ioaddr, struct pci_device *pdev) +{ + DBGP ( "rtl_hw_start_8168c_3\n" ); + + rtl_hw_start_8168c_2(ioaddr, pdev); +} + +static void rtl_hw_start_8168c_4(void *ioaddr, struct pci_device *pdev) +{ + DBGP ( "rtl_hw_start_8168c_4\n" ); + + rtl_csi_access_enable(ioaddr); + + __rtl_hw_start_8168cp(ioaddr, pdev); +} + +static void rtl_hw_start_8168d(void *ioaddr, struct pci_device *pdev) +{ + DBGP ( "rtl_hw_start_8168d\n" ); + + rtl_csi_access_enable(ioaddr); + + rtl_disable_clock_request(pdev); + + RTL_W8(EarlyTxThres, EarlyTxThld); + + rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); + + RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); +} + +static void rtl_hw_start_8168(struct net_device *dev) +{ + struct rtl8169_private *tp = netdev_priv(dev); + void *ioaddr = tp->mmio_addr; + struct pci_device *pdev = tp->pci_dev; + + DBGP ( "rtl_hw_start_8168\n" ); + + RTL_W8(Cfg9346, Cfg9346_Unlock); + + RTL_W8(EarlyTxThres, EarlyTxThld); + + rtl_set_rx_max_size(ioaddr); + + tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; + + RTL_W16(CPlusCmd, tp->cp_cmd); + + RTL_W16(IntrMitigate, 0x5151); + + /* Work around for RxFIFO overflow. */ + if (tp->mac_version == RTL_GIGA_MAC_VER_11) { + tp->intr_event |= RxFIFOOver | PCSTimeout; + tp->intr_event &= ~RxOverflow; + } + + rtl_set_rx_tx_desc_registers(tp, ioaddr); + + rtl_set_rx_mode(dev); + + RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | + (InterFrameGap << TxInterFrameGapShift)); + + RTL_R8(IntrMask); + + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_11: + rtl_hw_start_8168bb(ioaddr, pdev); + break; + + case RTL_GIGA_MAC_VER_12: + case RTL_GIGA_MAC_VER_17: + rtl_hw_start_8168bef(ioaddr, pdev); + break; + + case RTL_GIGA_MAC_VER_18: + rtl_hw_start_8168cp_1(ioaddr, pdev); + break; + + case RTL_GIGA_MAC_VER_19: + rtl_hw_start_8168c_1(ioaddr, pdev); + break; + + case RTL_GIGA_MAC_VER_20: + rtl_hw_start_8168c_2(ioaddr, pdev); + break; + + case RTL_GIGA_MAC_VER_21: + rtl_hw_start_8168c_3(ioaddr, pdev); + break; + + case RTL_GIGA_MAC_VER_22: + rtl_hw_start_8168c_4(ioaddr, pdev); + break; + + case RTL_GIGA_MAC_VER_23: + rtl_hw_start_8168cp_2(ioaddr, pdev); + break; + + case RTL_GIGA_MAC_VER_24: + rtl_hw_start_8168cp_3(ioaddr, pdev); + break; + + case RTL_GIGA_MAC_VER_25: + rtl_hw_start_8168d(ioaddr, pdev); + break; + + default: + DBG ( "Unknown chipset (mac_version = %d).\n", + tp->mac_version ); + break; + } + + RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); + + RTL_W8(Cfg9346, Cfg9346_Lock); + + RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); + + // RTL_W16(IntrMask, tp->intr_event); +} + +#define R810X_CPCMD_QUIRK_MASK (\ + EnableBist | \ + Mac_dbgo_oe | \ + Force_half_dup | \ + Force_half_dup | \ + Force_txflow_en | \ + Cxpl_dbg_sel | \ + ASF | \ + PktCntrDisable | \ + PCIDAC | \ + PCIMulRW) + +static void rtl_hw_start_8102e_1(void *ioaddr, struct pci_device *pdev) +{ + static struct ephy_info e_info_8102e_1[] = { + { 0x01, 0, 0x6e65 }, + { 0x02, 0, 0x091f }, + { 0x03, 0, 0xc2f9 }, + { 0x06, 0, 0xafb5 }, + { 0x07, 0, 0x0e00 }, + { 0x19, 0, 0xec80 }, + { 0x01, 0, 0x2e65 }, + { 0x01, 0, 0x6e65 } + }; + u8 cfg1; + + DBGP ( "rtl_hw_start_8102e_1\n" ); + + rtl_csi_access_enable(ioaddr); + + RTL_W8(DBG_REG, FIX_NAK_1); + + rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); + + RTL_W8(Config1, + LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); + RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); + + cfg1 = RTL_R8(Config1); + if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) + RTL_W8(Config1, cfg1 & ~LEDS0); + + RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); + + rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); +} + +static void rtl_hw_start_8102e_2(void *ioaddr, struct pci_device *pdev) +{ + DBGP ( "rtl_hw_start_8102e_2\n" ); + + rtl_csi_access_enable(ioaddr); + + rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); + + RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); + RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); + + RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); +} + +static void rtl_hw_start_8102e_3(void *ioaddr, struct pci_device *pdev) +{ + DBGP ( "rtl_hw_start_8102e_3\n" ); + + rtl_hw_start_8102e_2(ioaddr, pdev); + + rtl_ephy_write(ioaddr, 0x03, 0xc2f9); +} + +static void rtl_hw_start_8101(struct net_device *dev) +{ + struct rtl8169_private *tp = netdev_priv(dev); + void *ioaddr = tp->mmio_addr; + struct pci_device *pdev = tp->pci_dev; + + DBGP ( "rtl_hw_start_8101\n" ); + + if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || + (tp->mac_version == RTL_GIGA_MAC_VER_16)) { + int cap = tp->pcie_cap; + + if (cap) { + pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, + PCI_EXP_DEVCTL_NOSNOOP_EN); + } + } + + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_07: + rtl_hw_start_8102e_1(ioaddr, pdev); + break; + + case RTL_GIGA_MAC_VER_08: + rtl_hw_start_8102e_3(ioaddr, pdev); + break; + + case RTL_GIGA_MAC_VER_09: + rtl_hw_start_8102e_2(ioaddr, pdev); + break; + } + + RTL_W8(Cfg9346, Cfg9346_Unlock); + + RTL_W8(EarlyTxThres, EarlyTxThld); + + rtl_set_rx_max_size(ioaddr); + + tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; + + RTL_W16(CPlusCmd, tp->cp_cmd); + + RTL_W16(IntrMitigate, 0x0000); + + rtl_set_rx_tx_desc_registers(tp, ioaddr); + + RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); + rtl_set_rx_tx_config_registers(tp); + + RTL_W8(Cfg9346, Cfg9346_Lock); + + RTL_R8(IntrMask); + + rtl_set_rx_mode(dev); + + RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); + + RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); + + // RTL_W16(IntrMask, tp->intr_event); +} + +/*** gPXE API Support Routines ***/ + +/** + * setup_tx_resources - allocate tx resources (descriptors) + * + * @v tp Driver private storage + * + * @ret rc Returns 0 on success, negative on failure + **/ +static int +rtl8169_setup_tx_resources ( struct rtl8169_private *tp ) +{ + DBGP ( "rtl8169_setup_tx_resources\n" ); + + tp->tx_base = malloc_dma ( R8169_TX_RING_BYTES, TX_RING_ALIGN ); + + if ( ! tp->tx_base ) { + return -ENOMEM; + } + + memset ( tp->tx_base, 0, R8169_TX_RING_BYTES ); + + DBG ( "tp->tx_base = %#08lx\n", virt_to_bus ( tp->tx_base ) ); + + tp->tx_fill_ctr = 0; + tp->tx_curr = 0; + tp->tx_tail = 0; + + return 0; +} + +static void +rtl8169_process_tx_packets ( struct net_device *netdev ) +{ + struct rtl8169_private *tp = netdev_priv ( netdev ); + + uint32_t tx_status; + struct TxDesc *tx_curr_desc; + + DBGP ( "rtl8169_process_tx_packets\n" ); + + while ( tp->tx_tail != tp->tx_curr ) { + + tx_curr_desc = tp->tx_base + tp->tx_tail; + + tx_status = tx_curr_desc->opts1; + + DBG2 ( "Before DescOwn check tx_status: %#08x\n", tx_status ); + + /* if the packet at tx_tail is not owned by hardware it is for us */ + if ( tx_status & DescOwn ) + break; + + DBG ( "Transmitted packet.\n" ); + DBG ( "tp->tx_fill_ctr = %d\n", tp->tx_fill_ctr ); + DBG ( "tp->tx_tail = %d\n", tp->tx_tail ); + DBG ( "tp->tx_curr = %d\n", tp->tx_curr ); + DBG ( "tx_status = %d\n", tx_status ); + DBG ( "tx_curr_desc = %#08lx\n", virt_to_bus ( tx_curr_desc ) ); + + /* Pass packet to core for processing */ + netdev_tx_complete ( netdev, tp->tx_iobuf[tp->tx_tail] ); + + memset ( tx_curr_desc, 0, sizeof ( *tx_curr_desc ) ); + + /* Decrement count of used descriptors */ + tp->tx_fill_ctr--; + + /* Increment sent packets index */ + tp->tx_tail = ( tp->tx_tail + 1 ) % NUM_TX_DESC; + } +} + +static void +rtl8169_free_tx_resources ( struct rtl8169_private *tp ) +{ + DBGP ( "rtl8169_free_tx_resources\n" ); + + free_dma ( tp->tx_base, R8169_TX_RING_BYTES ); +} + +static void +rtl8169_populate_rx_descriptor ( struct rtl8169_private *tp, struct RxDesc *rx_desc, uint32_t index ) +{ + DBGP ( "rtl8169_populate_rx_descriptor\n" ); + + DBG ( "Populating rx descriptor %d\n", index ); + + memset ( rx_desc, 0, sizeof ( *rx_desc ) ); + + rx_desc->addr_hi = 0; + rx_desc->addr_lo = virt_to_bus ( tp->rx_iobuf[index]->data ); + rx_desc->opts2 = 0; + rx_desc->opts1 = ( index == ( NUM_RX_DESC - 1 ) ? RingEnd : 0 ) | + RX_BUF_SIZE; + rx_desc->opts1 |= DescOwn; +} + +/** + * Refill descriptor ring + * + * @v netdev Net device + */ +static void rtl8169_refill_rx_ring ( struct rtl8169_private *tp ) +{ + struct RxDesc *rx_curr_desc; + int i; + + DBGP ( "rtl8169_refill_rx_ring\n" ); + + for ( i = 0; i < NUM_RX_DESC; i++ ) { + + rx_curr_desc = ( tp->rx_base ) + i; + + /* Don't touch descriptors owned by the NIC */ + if ( rx_curr_desc->opts1 & DescOwn ) + continue; + + /* Don't touch descriptors with iobufs, they still need to be + processed by the poll routine */ + if ( tp->rx_iobuf[tp->rx_curr] != NULL ) + continue; + + /** If we can't get an iobuf for this descriptor + try again later (next poll). + */ + if ( ! ( tp->rx_iobuf[i] = alloc_iob ( RX_BUF_SIZE ) ) ) { + DBG ( "Refill rx ring failed!!\n" ); + break; + } + + rtl8169_populate_rx_descriptor ( tp, rx_curr_desc, i ); + } +} + +/** + * setup_rx_resources - allocate Rx resources (Descriptors) + * + * @v tp: Driver private structure + * + * @ret rc Returns 0 on success, negative on failure + * + **/ +static int +rtl8169_setup_rx_resources ( struct rtl8169_private *tp ) +{ + DBGP ( "rtl8169_setup_rx_resources\n" ); + + tp->rx_base = malloc_dma ( R8169_RX_RING_BYTES, RX_RING_ALIGN ); + + DBG ( "tp->rx_base = %#08lx\n", virt_to_bus ( tp->rx_base ) ); + + if ( ! tp->rx_base ) { + return -ENOMEM; + } + memset ( tp->rx_base, 0, R8169_RX_RING_BYTES ); + + rtl8169_refill_rx_ring ( tp ); + + tp->rx_curr = 0; + + return 0; +} + +static void +rtl8169_process_rx_packets ( struct net_device *netdev ) +{ + struct rtl8169_private *tp = netdev_priv ( netdev ); + uint32_t rx_status; + uint16_t rx_len; + struct RxDesc *rx_curr_desc; + int i; + + DBGP ( "rtl8169_process_rx_packets\n" ); + + for ( i = 0; i < NUM_RX_DESC; i++ ) { + + rx_curr_desc = tp->rx_base + tp->rx_curr; + + rx_status = rx_curr_desc->opts1; + + DBG2 ( "Before DescOwn check rx_status: %#08x\n", rx_status ); + + /* Hardware still owns the descriptor */ + if ( rx_status & DescOwn ) + break; + + /* We own the descriptor, but it has not been refilled yet */ + if ( tp->rx_iobuf[tp->rx_curr] == NULL ) + break; + + rx_len = rx_status & 0x3fff; + + DBG ( "Received packet.\n" ); + DBG ( "tp->rx_curr = %d\n", tp->rx_curr ); + DBG ( "rx_len = %d\n", rx_len ); + DBG ( "rx_status = %#08x\n", rx_status ); + DBG ( "rx_curr_desc = %#08lx\n", virt_to_bus ( rx_curr_desc ) ); + + if ( rx_status & RxRES ) { + + netdev_rx_err ( netdev, tp->rx_iobuf[tp->rx_curr], -EINVAL ); + + DBG ( "rtl8169_poll: Corrupted packet received!\n" + " rx_status: %#08x\n", rx_status ); + + } else { + + /* Adjust size of the iobuf to reflect received data */ + iob_put ( tp->rx_iobuf[tp->rx_curr], rx_len ); + + /* Add this packet to the receive queue. */ + netdev_rx ( netdev, tp->rx_iobuf[tp->rx_curr] ); + } + + /* Invalidate this iobuf and descriptor */ + tp->rx_iobuf[tp->rx_curr] = NULL; + memset ( rx_curr_desc, 0, sizeof ( *rx_curr_desc ) ); + + /* Update pointer to next available rx descriptor */ + tp->rx_curr = ( tp->rx_curr + 1 ) % NUM_RX_DESC; + } + rtl8169_refill_rx_ring ( tp ); +} + +static void +rtl8169_free_rx_resources ( struct rtl8169_private *tp ) +{ + int i; + + DBGP ( "rtl8169_free_rx_resources\n" ); + + free_dma ( tp->rx_base, R8169_RX_RING_BYTES ); + + for ( i = 0; i < NUM_RX_DESC; i++ ) { + free_iob ( tp->rx_iobuf[i] ); + tp->rx_iobuf[i] = NULL; + } +} + +/** + FIXME: Because gPXE's pci_device_id structure does not contain a + field to contain arbitrary data, we need the following table to + associate PCI IDs with nic variants, because a lot of driver + routines depend on knowing which kind of variant they are dealing + with. --mdc + **/ + +#define _R(VENDOR,DEVICE,INDEX) \ + { .vendor = VENDOR, .device = DEVICE, .index = INDEX } + +static const struct { + uint16_t vendor; + uint16_t device; + int index; +} nic_variant_table[] = { + _R(0x10ec, 0x8129, RTL_CFG_0), + _R(0x10ec, 0x8136, RTL_CFG_2), + _R(0x10ec, 0x8167, RTL_CFG_0), + _R(0x10ec, 0x8168, RTL_CFG_1), + _R(0x10ec, 0x8169, RTL_CFG_0), + _R(0x1186, 0x4300, RTL_CFG_0), + _R(0x1259, 0xc107, RTL_CFG_0), + _R(0x16ec, 0x0116, RTL_CFG_0), + _R(0x1737, 0x1032, RTL_CFG_0), + _R(0x0001, 0x8168, RTL_CFG_2), +}; +#undef _R + +static int +rtl8169_get_nic_variant ( uint16_t vendor, uint16_t device ) +{ + u32 i; + + DBGP ( "rtl8169_get_nic_variant\n" ); + + for (i = 0; i < ARRAY_SIZE(nic_variant_table); i++) { + if ( ( nic_variant_table[i].vendor == vendor ) && + ( nic_variant_table[i].device == device ) ) { + return ( nic_variant_table[i].index ); + } + } + DBG ( "No matching NIC variant found!\n" ); + return ( RTL_CFG_0 ); +} + +static void rtl8169_irq_enable ( struct rtl8169_private *tp ) +{ + void *ioaddr = tp->mmio_addr; + + DBGP ( "rtl8169_irq_enable\n" ); + + RTL_W16 ( IntrMask, tp->intr_event ); +} + +static void rtl8169_irq_disable ( struct rtl8169_private *tp ) +{ + void *ioaddr = tp->mmio_addr; + + DBGP ( "rtl8169_irq_disable\n" ); + + rtl8169_irq_mask_and_ack ( ioaddr ); +} + +/*** gPXE Core API Routines ***/ + +/** + * open - Called when a network interface is made active + * + * @v netdev network interface device structure + * @ret rc Return status code, 0 on success, negative value on failure + * + **/ +static int +rtl8169_open ( struct net_device *netdev ) +{ + struct rtl8169_private *tp = netdev_priv ( netdev ); + void *ioaddr = tp->mmio_addr; + int rc; + + DBGP ( "rtl8169_open\n" ); + + /* allocate transmit descriptors */ + rc = rtl8169_setup_tx_resources ( tp ); + if ( rc ) { + DBG ( "Error setting up TX resources!\n" ); + goto err_setup_tx; + } + + /* allocate receive descriptors */ + rc = rtl8169_setup_rx_resources ( tp ); + if ( rc ) { + DBG ( "Error setting up RX resources!\n" ); + goto err_setup_rx; + } + + rtl_hw_start ( netdev ); + + DBG ( "TxDescStartAddrHigh = %#08lx\n", RTL_R32 ( TxDescStartAddrHigh ) ); + DBG ( "TxDescStartAddrLow = %#08lx\n", RTL_R32 ( TxDescStartAddrLow ) ); + DBG ( "RxDescAddrHigh = %#08lx\n", RTL_R32 ( RxDescAddrHigh ) ); + DBG ( "RxDescAddrLow = %#08lx\n", RTL_R32 ( RxDescAddrLow ) ); + + return 0; + +err_setup_rx: + rtl8169_free_tx_resources ( tp ); +err_setup_tx: + rtl8169_hw_reset ( ioaddr ); + + return rc; +} + +/** + * transmit - Transmit a packet + * + * @v netdev Network device + * @v iobuf I/O buffer + * + * @ret rc Returns 0 on success, negative on failure + */ +static int +rtl8169_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) +{ + struct rtl8169_private *tp = netdev_priv ( netdev ); + void *ioaddr = tp->mmio_addr; + uint32_t tx_len = iob_len ( iobuf ); + + struct TxDesc *tx_curr_desc; + + DBGP ("rtl8169_transmit\n"); + + if ( tp->tx_fill_ctr == NUM_TX_DESC ) { + DBG ("TX overflow\n"); + return -ENOBUFS; + } + + /** + * The rtl8169 family automatically pads short packets to a + * minimum size, but if it did not, like some older cards, + * we could do: + * iob_pad ( iobuf, ETH_ZLEN ); + */ + + /* Save pointer to this iobuf we have been given to transmit so + we can pass it to netdev_tx_complete() later */ + tp->tx_iobuf[tp->tx_curr] = iobuf; + + tx_curr_desc = tp->tx_base + tp->tx_curr; + + DBG ( "tp->tx_fill_ctr = %d\n", tp->tx_fill_ctr ); + DBG ( "tp->tx_curr = %d\n", tp->tx_curr ); + DBG ( "tx_curr_desc = %#08lx\n", virt_to_bus ( tx_curr_desc ) ); + DBG ( "iobuf->data = %#08lx\n", virt_to_bus ( iobuf->data ) ); + DBG ( "tx_len = %d\n", tx_len ); + + /* Configure current descriptor to transmit supplied packet */ + tx_curr_desc->addr_hi = 0; + tx_curr_desc->addr_lo = virt_to_bus ( iobuf->data ); + tx_curr_desc->opts2 = 0; + tx_curr_desc->opts1 = FirstFrag | LastFrag | + ( tp->tx_curr == ( NUM_TX_DESC - 1 ) ? RingEnd : 0 ) | + tx_len; + + /* Mark descriptor as owned by NIC */ + tx_curr_desc->opts1 |= DescOwn; + + DBG ( "tx_curr_desc->opts1 = %#08x\n", tx_curr_desc->opts1 ); + DBG ( "tx_curr_desc->opts2 = %#08x\n", tx_curr_desc->opts2 ); + DBG ( "tx_curr_desc->addr_hi = %#08x\n", tx_curr_desc->addr_hi ); + DBG ( "tx_curr_desc->addr_lo = %#08x\n", tx_curr_desc->addr_lo ); + + RTL_W8 ( TxPoll, NPQ ); /* set polling bit */ + + /* Point to next free descriptor */ + tp->tx_curr = ( tp->tx_curr + 1 ) % NUM_TX_DESC; + + /* Increment number of tx descriptors in use */ + tp->tx_fill_ctr++; + + return 0; +} + +/** + * poll - Poll for received packets + * + * @v netdev Network device + */ +static void +rtl8169_poll ( struct net_device *netdev ) +{ + struct rtl8169_private *tp = netdev_priv ( netdev ); + void *ioaddr = tp->mmio_addr; + + uint16_t intr_status; + uint16_t intr_mask; + + DBGP ( "rtl8169_poll\n" ); + + intr_status = RTL_R16 ( IntrStatus ); + intr_mask = RTL_R16 ( IntrMask ); + + DBG2 ( "rtl8169_poll (before): intr_mask = %#04x intr_status = %#04x\n", + intr_mask, intr_status ); + + RTL_W16 ( IntrStatus, 0xffff ); + + /* hotplug / major error / no more work / shared irq */ + if ( intr_status == 0xffff ) + return; + + /* Process transmitted packets */ + rtl8169_process_tx_packets ( netdev ); + + /* Process received packets */ + rtl8169_process_rx_packets ( netdev ); +} + +/** + * close - Disable network interface + * + * @v netdev network interface device structure + * + **/ +static void +rtl8169_close ( struct net_device *netdev ) +{ + struct rtl8169_private *tp = netdev_priv ( netdev ); + void *ioaddr = tp->mmio_addr; + + DBGP ( "r8169_close\n" ); + + rtl8169_hw_reset ( ioaddr ); + + rtl8169_free_tx_resources ( tp ); + rtl8169_free_rx_resources ( tp ); +} + +/** + * irq - enable or Disable interrupts + * + * @v netdev network adapter + * @v action requested interrupt action + * + **/ +static void +rtl8169_irq ( struct net_device *netdev, int action ) +{ + struct rtl8169_private *tp = netdev_priv ( netdev ); + + DBGP ( "rtl8169_irq\n" ); + + switch ( action ) { + case 0 : + rtl8169_irq_disable ( tp ); + break; + default : + rtl8169_irq_enable ( tp ); + break; + } +} + +static struct net_device_operations rtl8169_operations = { + .open = rtl8169_open, + .transmit = rtl8169_transmit, + .poll = rtl8169_poll, + .close = rtl8169_close, + .irq = rtl8169_irq, +}; + +/** + * probe - Initial configuration of NIC + * + * @v pci PCI device + * @v id PCI IDs + * + * @ret rc Return status code + **/ +static int +rtl8169_probe ( struct pci_device *pdev, const struct pci_device_id *ent ) +{ + int i, rc; + struct net_device *netdev; + struct rtl8169_private *tp; + void *ioaddr; + + /** FIXME: This lookup is necessary because gPXE does not have a "data" + element in the structure pci_device_id which can pass an arbitrary + piece of data to the driver. It might be useful to add it. Then we + could just use ent->data instead of having to look up cfg_index. + **/ + int cfg_index = rtl8169_get_nic_variant ( ent->vendor, ent->device ); + const struct rtl_cfg_info *cfg = rtl_cfg_infos + cfg_index; + + DBGP ( "rtl8169_probe\n" ); + + DBG ( "ent->vendor = %#04x, ent->device = %#04x\n", ent->vendor, ent->device ); + + DBG ( "cfg_index = %d\n", cfg_index ); + DBG ( "cfg->intr_event = %#04x\n", cfg->intr_event ); + + rc = -ENOMEM; + + /* Allocate net device ( also allocates memory for netdev->priv + and makes netdev-priv point to it ) + */ + netdev = alloc_etherdev ( sizeof ( *tp ) ); + + if ( ! netdev ) + goto err_alloc_etherdev; + + /* Associate driver-specific network operations with + generic network device layer + */ + netdev_init ( netdev, &rtl8169_operations ); + + /* Associate this network device with the given PCI device */ + pci_set_drvdata ( pdev, netdev ); + netdev->dev = &pdev->dev; + + /* Initialize driver private storage */ + tp = netdev_priv ( netdev ); + memset ( tp, 0, ( sizeof ( *tp ) ) ); + + tp->pci_dev = pdev; + tp->irqno = pdev->irq; + tp->netdev = netdev; + tp->cfg_index = cfg_index; + tp->intr_event = cfg->intr_event; + tp->cp_cmd = PCIMulRW; + + tp->hw_start = cfg->hw_start; + + rc = -EIO; + + adjust_pci_device ( pdev ); + + /* ioremap MMIO region */ + ioaddr = ioremap ( pdev->membase, R8169_REGS_SIZE ); + + if ( ! ioaddr ) { + DBG ( "cannot remap MMIO\n" ); + rc = -EIO; + goto err_ioremap; + } + + tp->mmio_addr = ioaddr; + + tp->pcie_cap = pci_find_capability ( pdev, PCI_CAP_ID_EXP ); + if ( tp->pcie_cap ) { + DBG ( "PCI Express capability\n" ); + } else { + DBG ( "No PCI Express capability\n" ); + } + + /* Mask interrupts just in case */ + rtl8169_irq_mask_and_ack ( ioaddr ); + + /* Soft reset NIC */ + rtl_soft_reset ( netdev ); + + /* Identify chip attached to board */ + rtl8169_get_mac_version ( tp, ioaddr ); + + for ( i = 0; (u32) i < ARRAY_SIZE ( rtl_chip_info ); i++ ) { + if ( tp->mac_version == rtl_chip_info[i].mac_version ) + break; + } + if ( i == ARRAY_SIZE(rtl_chip_info ) ) { + /* Unknown chip: assume array element #0, original RTL-8169 */ + DBG ( "Unknown chip version, assuming %s\n", rtl_chip_info[0].name ); + i = 0; + } + tp->chipset = i; + + if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) && + (RTL_R8(PHYstatus) & TBI_Enable)) { + tp->set_speed = rtl8169_set_speed_tbi; + tp->phy_reset_enable = rtl8169_tbi_reset_enable; + tp->phy_reset_pending = rtl8169_tbi_reset_pending; + tp->link_ok = rtl8169_tbi_link_ok; + + tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ + } else { + tp->set_speed = rtl8169_set_speed_xmii; + tp->phy_reset_enable = rtl8169_xmii_reset_enable; + tp->phy_reset_pending = rtl8169_xmii_reset_pending; + tp->link_ok = rtl8169_xmii_link_ok; + } + + /* Get MAC address */ + for ( i = 0; i < MAC_ADDR_LEN; i++ ) + netdev->hw_addr[i] = RTL_R8 ( MAC0 + i ); + + DBG ( "%s\n", eth_ntoa ( netdev->hw_addr ) ); + + rtl8169_init_phy ( netdev, tp ); + + if ( ( rc = register_netdev ( netdev ) ) != 0 ) + goto err_register; + + /* Mark as link up; we don't yet handle link state */ + netdev_link_up ( netdev ); + + DBG ( "rtl8169_probe succeeded!\n" ); + + /* No errors, return success */ + return 0; + +/* Error return paths */ +err_register: +err_ioremap: + netdev_put ( netdev ); +err_alloc_etherdev: + return rc; +} + +/** + * remove - Device Removal Routine + * + * @v pdev PCI device information struct + * + **/ +static void +rtl8169_remove ( struct pci_device *pdev ) +{ + struct net_device *netdev = pci_get_drvdata ( pdev ); + struct rtl8169_private *tp = netdev_priv ( netdev ); + void *ioaddr = tp->mmio_addr; + + DBGP ( "rtl8169_remove\n" ); + + rtl8169_hw_reset ( ioaddr ); + + unregister_netdev ( netdev ); + netdev_nullify ( netdev ); + netdev_put ( netdev ); +} + +static struct pci_device_id rtl8169_nics[] = { + PCI_ROM(0x10ec, 0x8129, "rtl8169-0x8129", "rtl8169-0x8129", 0), + PCI_ROM(0x10ec, 0x8136, "rtl8169-0x8136", "rtl8169-0x8136", 0), + PCI_ROM(0x10ec, 0x8167, "rtl8169-0x8167", "rtl8169-0x8167", 0), + PCI_ROM(0x10ec, 0x8168, "rtl8169-0x8168", "rtl8169-0x8168", 0), + PCI_ROM(0x10ec, 0x8169, "rtl8169-0x8169", "rtl8169-0x8169", 0), + PCI_ROM(0x1186, 0x4300, "rtl8169-0x4300", "rtl8169-0x4300", 0), + PCI_ROM(0x1259, 0xc107, "rtl8169-0xc107", "rtl8169-0xc107", 0), + PCI_ROM(0x16ec, 0x0116, "rtl8169-0x0116", "rtl8169-0x0116", 0), + PCI_ROM(0x1737, 0x1032, "rtl8169-0x1032", "rtl8169-0x1032", 0), + PCI_ROM(0x0001, 0x8168, "rtl8169-0x8168", "rtl8169-0x8168", 0), +}; + +struct pci_driver rtl8169_driver __pci_driver = { + .ids = rtl8169_nics, + .id_count = ( sizeof ( rtl8169_nics ) / sizeof ( rtl8169_nics[0] ) ), + .probe = rtl8169_probe, + .remove = rtl8169_remove, +}; + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/r8169.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/r8169.h new file mode 100644 index 0000000..89679b1 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/r8169.h @@ -0,0 +1,487 @@ +/* + * Copyright (c) 2008 Marty Connor <mdc@etherboot.org> + * Copyright (c) 2008 Entity Cyber, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * This driver is based on rtl8169 data sheets and work by: + * + * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> + * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> + * Copyright (c) a lot of people too. Please respect their work. + * + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#ifndef _R8169_H_ +#define _R8169_H_ + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +/** FIXME: include/linux/pci_regs.h has these PCI regs, maybe + we need such a file in gPXE? +**/ +#define PCI_EXP_DEVCTL 8 /* Device Control */ +#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ +#define PCI_EXP_LNKCTL 16 /* Link Control */ +#define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */ +#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ + +/** FIXME: update mii.h in src/include/mii.h from Linux sources + so we don't have to include these definitiions. +**/ +/* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */ +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_10000 10000 + +/* Duplex, half or full. */ +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 + +#define AUTONEG_DISABLE 0x00 +#define AUTONEG_ENABLE 0x01 + +/* MAC address length */ +#define MAC_ADDR_LEN 6 + +#define MAX_READ_REQUEST_SHIFT 12 +#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ +#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ +#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ +#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ +#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */ +#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ +#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ + +#define R8169_REGS_SIZE 256 +#define R8169_NAPI_WEIGHT 64 +#define NUM_TX_DESC 8 /* Number of Tx descriptor registers */ +#define NUM_RX_DESC 8 /* Number of Rx descriptor registers */ +#define RX_BUF_SIZE 1536 /* Rx Buffer size */ +#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) +#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) + +#define TX_RING_ALIGN 256 +#define RX_RING_ALIGN 256 + +#define RTL8169_TX_TIMEOUT (6*HZ) +#define RTL8169_PHY_TIMEOUT (10*HZ) + +#define RTL_EEPROM_SIG cpu_to_le32(0x8129) +#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) +#define RTL_EEPROM_SIG_ADDR 0x0000 + +/* write/read MMIO register */ +#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) +#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) +#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) +#define RTL_R8(reg) readb (ioaddr + (reg)) +#define RTL_R16(reg) readw (ioaddr + (reg)) +#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) + +enum mac_version { + RTL_GIGA_MAC_VER_01 = 0x01, // 8169 + RTL_GIGA_MAC_VER_02 = 0x02, // 8169S + RTL_GIGA_MAC_VER_03 = 0x03, // 8110S + RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB + RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd + RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe + RTL_GIGA_MAC_VER_07 = 0x07, // 8102e + RTL_GIGA_MAC_VER_08 = 0x08, // 8102e + RTL_GIGA_MAC_VER_09 = 0x09, // 8102e + RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e + RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb + RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be + RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb + RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? + RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? + RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec + RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf + RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP + RTL_GIGA_MAC_VER_19 = 0x13, // 8168C + RTL_GIGA_MAC_VER_20 = 0x14, // 8168C + RTL_GIGA_MAC_VER_21 = 0x15, // 8168C + RTL_GIGA_MAC_VER_22 = 0x16, // 8168C + RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP + RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP + RTL_GIGA_MAC_VER_25 = 0x19, // 8168D +}; + +#define _R(NAME,MAC,MASK) \ + { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } + +static const struct { + const char *name; + u8 mac_version; + u32 RxConfigMask; /* Clears the bits supported by this chip */ +} rtl_chip_info[] = { + _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 + _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S + _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S + _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB + _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd + _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe + _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E + _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E + _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E + _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E + _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E + _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E + _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 + _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 + _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139 + _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E + _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E + _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E + _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E + _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E + _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E + _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E + _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E + _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E + _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E +}; +#undef _R + +enum cfg_version { + RTL_CFG_0 = 0x00, + RTL_CFG_1, + RTL_CFG_2 +}; + +#if 0 +/** Device Table from Linux Driver **/ +static struct pci_device_id rtl8169_pci_tbl[] = { + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, + { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, + { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, + { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, + { PCI_VENDOR_ID_LINKSYS, 0x1032, + PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, + { 0x0001, 0x8168, + PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, + {0,}, +}; +#endif + +enum rtl_registers { + MAC0 = 0, /* Ethernet hardware address. */ + MAC4 = 4, + MAR0 = 8, /* Multicast filter. */ + CounterAddrLow = 0x10, + CounterAddrHigh = 0x14, + TxDescStartAddrLow = 0x20, + TxDescStartAddrHigh = 0x24, + TxHDescStartAddrLow = 0x28, + TxHDescStartAddrHigh = 0x2c, + FLASH = 0x30, + ERSR = 0x36, + ChipCmd = 0x37, + TxPoll = 0x38, + IntrMask = 0x3c, + IntrStatus = 0x3e, + TxConfig = 0x40, + RxConfig = 0x44, + RxMissed = 0x4c, + Cfg9346 = 0x50, + Config0 = 0x51, + Config1 = 0x52, + Config2 = 0x53, + Config3 = 0x54, + Config4 = 0x55, + Config5 = 0x56, + MultiIntr = 0x5c, + PHYAR = 0x60, + PHYstatus = 0x6c, + RxMaxSize = 0xda, + CPlusCmd = 0xe0, + IntrMitigate = 0xe2, + RxDescAddrLow = 0xe4, + RxDescAddrHigh = 0xe8, + EarlyTxThres = 0xec, + FuncEvent = 0xf0, + FuncEventMask = 0xf4, + FuncPresetState = 0xf8, + FuncForceEvent = 0xfc, +}; + +enum rtl8110_registers { + TBICSR = 0x64, + TBI_ANAR = 0x68, + TBI_LPAR = 0x6a, +}; + +enum rtl8168_8101_registers { + CSIDR = 0x64, + CSIAR = 0x68, +#define CSIAR_FLAG 0x80000000 +#define CSIAR_WRITE_CMD 0x80000000 +#define CSIAR_BYTE_ENABLE 0x0f +#define CSIAR_BYTE_ENABLE_SHIFT 12 +#define CSIAR_ADDR_MASK 0x0fff + + EPHYAR = 0x80, +#define EPHYAR_FLAG 0x80000000 +#define EPHYAR_WRITE_CMD 0x80000000 +#define EPHYAR_REG_MASK 0x1f +#define EPHYAR_REG_SHIFT 16 +#define EPHYAR_DATA_MASK 0xffff + DBG_REG = 0xd1, +#define FIX_NAK_1 (1 << 4) +#define FIX_NAK_2 (1 << 3) +}; + +enum rtl_register_content { + /* InterruptStatusBits */ + SYSErr = 0x8000, + PCSTimeout = 0x4000, + SWInt = 0x0100, + TxDescUnavail = 0x0080, + RxFIFOOver = 0x0040, + LinkChg = 0x0020, + RxOverflow = 0x0010, + TxErr = 0x0008, + TxOK = 0x0004, + RxErr = 0x0002, + RxOK = 0x0001, + + /* RxStatusDesc */ + RxFOVF = (1 << 23), + RxRWT = (1 << 22), + RxRES = (1 << 21), + RxRUNT = (1 << 20), + RxCRC = (1 << 19), + + /* ChipCmdBits */ + CmdReset = 0x10, + CmdRxEnb = 0x08, + CmdTxEnb = 0x04, + RxBufEmpty = 0x01, + + /* TXPoll register p.5 */ + HPQ = 0x80, /* Poll cmd on the high prio queue */ + NPQ = 0x40, /* Poll cmd on the low prio queue */ + FSWInt = 0x01, /* Forced software interrupt */ + + /* Cfg9346Bits */ + Cfg9346_Lock = 0x00, + Cfg9346_Unlock = 0xc0, + + /* rx_mode_bits */ + AcceptErr = 0x20, + AcceptRunt = 0x10, + AcceptBroadcast = 0x08, + AcceptMulticast = 0x04, + AcceptMyPhys = 0x02, + AcceptAllPhys = 0x01, + + /* RxConfigBits */ + RxCfgFIFOShift = 13, + RxCfgDMAShift = 8, + + /* TxConfigBits */ + TxInterFrameGapShift = 24, + TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ + + /* Config1 register p.24 */ + LEDS1 = (1 << 7), + LEDS0 = (1 << 6), + MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ + Speed_down = (1 << 4), + MEMMAP = (1 << 3), + IOMAP = (1 << 2), + VPD = (1 << 1), + PMEnable = (1 << 0), /* Power Management Enable */ + + /* Config2 register p. 25 */ + PCI_Clock_66MHz = 0x01, + PCI_Clock_33MHz = 0x00, + + /* Config3 register p.25 */ + MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ + LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ + Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ + + /* Config5 register p.27 */ + BWF = (1 << 6), /* Accept Broadcast wakeup frame */ + MWF = (1 << 5), /* Accept Multicast wakeup frame */ + UWF = (1 << 4), /* Accept Unicast wakeup frame */ + LanWake = (1 << 1), /* LanWake enable/disable */ + PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ + + /* TBICSR p.28 */ + TBIReset = 0x80000000, + TBILoopback = 0x40000000, + TBINwEnable = 0x20000000, + TBINwRestart = 0x10000000, + TBILinkOk = 0x02000000, + TBINwComplete = 0x01000000, + + /* CPlusCmd p.31 */ + EnableBist = (1 << 15), // 8168 8101 + Mac_dbgo_oe = (1 << 14), // 8168 8101 + Normal_mode = (1 << 13), // unused + Force_half_dup = (1 << 12), // 8168 8101 + Force_rxflow_en = (1 << 11), // 8168 8101 + Force_txflow_en = (1 << 10), // 8168 8101 + Cxpl_dbg_sel = (1 << 9), // 8168 8101 + ASF = (1 << 8), // 8168 8101 + PktCntrDisable = (1 << 7), // 8168 8101 + Mac_dbgo_sel = 0x001c, // 8168 + RxVlan = (1 << 6), + RxChkSum = (1 << 5), + PCIDAC = (1 << 4), + PCIMulRW = (1 << 3), + INTT_0 = 0x0000, // 8168 + INTT_1 = 0x0001, // 8168 + INTT_2 = 0x0002, // 8168 + INTT_3 = 0x0003, // 8168 + + /* rtl8169_PHYstatus */ + TBI_Enable = 0x80, + TxFlowCtrl = 0x40, + RxFlowCtrl = 0x20, + _1000bpsF = 0x10, + _100bps = 0x08, + _10bps = 0x04, + LinkStatus = 0x02, + FullDup = 0x01, + + /* _TBICSRBit */ + TBILinkOK = 0x02000000, + + /* DumpCounterCommand */ + CounterDump = 0x8, +}; + +enum desc_status_bit { + DescOwn = (1 << 31), /* Descriptor is owned by NIC */ + RingEnd = (1 << 30), /* End of descriptor ring */ + FirstFrag = (1 << 29), /* First segment of a packet */ + LastFrag = (1 << 28), /* Final segment of a packet */ + + /* Tx private */ + LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ + MSSShift = 16, /* MSS value position */ + MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ + IPCS = (1 << 18), /* Calculate IP checksum */ + UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ + TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ + TxVlanTag = (1 << 17), /* Add VLAN tag */ + + /* Rx private */ + PID1 = (1 << 18), /* Protocol ID bit 1/2 */ + PID0 = (1 << 17), /* Protocol ID bit 2/2 */ + +#define RxProtoUDP (PID1) +#define RxProtoTCP (PID0) +#define RxProtoIP (PID1 | PID0) +#define RxProtoMask RxProtoIP + + IPFail = (1 << 16), /* IP checksum failed */ + UDPFail = (1 << 15), /* UDP/IP checksum failed */ + TCPFail = (1 << 14), /* TCP/IP checksum failed */ + RxVlanTag = (1 << 16), /* VLAN tag available */ +}; + +#define RsvdMask 0x3fffc000 + +struct TxDesc { + volatile uint32_t opts1; + volatile uint32_t opts2; + volatile uint32_t addr_lo; + volatile uint32_t addr_hi; +}; + +struct RxDesc { + volatile uint32_t opts1; + volatile uint32_t opts2; + volatile uint32_t addr_lo; + volatile uint32_t addr_hi; +}; + +enum features { + RTL_FEATURE_WOL = (1 << 0), + RTL_FEATURE_MSI = (1 << 1), + RTL_FEATURE_GMII = (1 << 2), +}; + +static void rtl_hw_start_8169(struct net_device *); +static void rtl_hw_start_8168(struct net_device *); +static void rtl_hw_start_8101(struct net_device *); + +struct rtl8169_private { + + struct pci_device *pci_dev; + struct net_device *netdev; + uint8_t *hw_addr; + void *mmio_addr; + uint32_t irqno; + + int chipset; + int mac_version; + int cfg_index; + u16 intr_event; + + struct io_buffer *tx_iobuf[NUM_TX_DESC]; + struct io_buffer *rx_iobuf[NUM_RX_DESC]; + + struct TxDesc *tx_base; + struct RxDesc *rx_base; + + uint32_t tx_curr; + uint32_t rx_curr; + + uint32_t tx_tail; + + uint32_t tx_fill_ctr; + + u16 cp_cmd; + + int phy_auto_nego_reg; + int phy_1000_ctrl_reg; + + int ( *set_speed ) (struct net_device *, u8 autoneg, u16 speed, u8 duplex ); + void ( *phy_reset_enable ) ( void *ioaddr ); + void ( *hw_start ) ( struct net_device * ); + unsigned int ( *phy_reset_pending ) ( void *ioaddr ); + unsigned int ( *link_ok ) ( void *ioaddr ); + + int pcie_cap; + + unsigned features; + +}; + +static const unsigned int rtl8169_rx_config = + (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); + +#endif /* _R8169_H_ */ + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/rtl8139.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/rtl8139.c new file mode 100644 index 0000000..dd35f74 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/rtl8139.c @@ -0,0 +1,606 @@ +/* rtl8139.c - etherboot driver for the Realtek 8139 chipset + + ported from the linux driver written by Donald Becker + by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999 + + This software may be used and distributed according to the terms + of the GNU Public License, incorporated herein by reference. + + changes to the original driver: + - removed support for interrupts, switching to polling mode (yuck!) + - removed support for the 8129 chip (external MII) + +*/ + +FILE_LICENCE ( GPL_ANY ); + +/*********************************************************************/ +/* Revision History */ +/*********************************************************************/ + +/* + 27 May 2006 mcb30@users.sourceforge.net (Michael Brown) + Rewrote to use the new net driver API, the updated PCI API, and + the generic three-wire serial device support for EEPROM access. + + 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap) + Put in virt_to_bus calls to allow Etherboot relocation. + + 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap) + Following email from Hyun-Joon Cha, added a disable routine, otherwise + NIC remains live and can crash the kernel later. + + 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub) + Shuffled things around, removed the leftovers from the 8129 support + that was in the Linux driver and added a bit more 8139 definitions. + Moved the 8K receive buffer to a fixed, available address outside the + 0x98000-0x9ffff range. This is a bit of a hack, but currently the only + way to make room for the Etherboot features that need substantial amounts + of code like the ANSI console support. Currently the buffer is just below + 0x10000, so this even conforms to the tagged boot image specification, + which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My + interpretation of this "reserved" is that Etherboot may do whatever it + likes, as long as its environment is kept intact (like the BIOS + variables). Hopefully fixed rtl_poll() once and for all. The symptoms + were that if Etherboot was left at the boot menu for several minutes, the + first eth_poll failed. Seems like I am the only person who does this. + First of all I fixed the debugging code and then set out for a long bug + hunting session. It took me about a week full time work - poking around + various places in the driver, reading Don Becker's and Jeff Garzik's Linux + driver and even the FreeBSD driver (what a piece of crap!) - and + eventually spotted the nasty thing: the transmit routine was acknowledging + each and every interrupt pending, including the RxOverrun and RxFIFIOver + interrupts. This confused the RTL8139 thoroughly. It destroyed the + Rx ring contents by dumping the 2K FIFO contents right where we wanted to + get the next packet. Oh well, what fun. + + 18 Jan 2000 mdc@etherboot.org (Marty Connor) + Drastically simplified error handling. Basically, if any error + in transmission or reception occurs, the card is reset. + Also, pointed all transmit descriptors to the same buffer to + save buffer space. This should decrease driver size and avoid + corruption because of exceeding 32K during runtime. + + 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de) + rtl_poll was quite broken: it used the RxOK interrupt flag instead + of the RxBufferEmpty flag which often resulted in very bad + transmission performace - below 1kBytes/s. + +*/ + +#include <stdint.h> +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <gpxe/io.h> +#include <errno.h> +#include <unistd.h> +#include <byteswap.h> +#include <gpxe/pci.h> +#include <gpxe/if_ether.h> +#include <gpxe/ethernet.h> +#include <gpxe/iobuf.h> +#include <gpxe/netdevice.h> +#include <gpxe/spi_bit.h> +#include <gpxe/threewire.h> +#include <gpxe/nvo.h> + +#define TX_RING_SIZE 4 + +struct rtl8139_tx { + unsigned int next; + struct io_buffer *iobuf[TX_RING_SIZE]; +}; + +struct rtl8139_rx { + void *ring; + unsigned int offset; +}; + +struct rtl8139_nic { + unsigned short ioaddr; + struct rtl8139_tx tx; + struct rtl8139_rx rx; + struct spi_bit_basher spibit; + struct spi_device eeprom; + struct nvo_block nvo; +}; + +/* Tuning Parameters */ +#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ +#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */ +#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */ +#define TX_DMA_BURST 4 /* Calculate as 16<<val. */ +#define TX_IPG 3 /* This is the only valid value */ +#define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */ +#define RX_BUF_LEN ( (8192 << RX_BUF_LEN_IDX) ) +#define RX_BUF_PAD 4 + +/* Symbolic offsets to registers. */ +enum RTL8139_registers { + MAC0=0, /* Ethernet hardware address. */ + MAR0=8, /* Multicast filter. */ + TxStatus0=0x10, /* Transmit status (four 32bit registers). */ + TxAddr0=0x20, /* Tx descriptors (also four 32bit). */ + RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36, + ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A, + IntrMask=0x3C, IntrStatus=0x3E, + TxConfig=0x40, RxConfig=0x44, + Timer=0x48, /* general-purpose counter. */ + RxMissed=0x4C, /* 24 bits valid, write clears. */ + Cfg9346=0x50, Config0=0x51, Config1=0x52, + TimerIntrReg=0x54, /* intr if gp counter reaches this value */ + MediaStatus=0x58, + Config3=0x59, + MultiIntr=0x5C, + RevisionID=0x5E, /* revision of the RTL8139 chip */ + TxSummary=0x60, + MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68, + NWayExpansion=0x6A, + DisconnectCnt=0x6C, FalseCarrierCnt=0x6E, + NWayTestReg=0x70, + RxCnt=0x72, /* packet received counter */ + CSCR=0x74, /* chip status and configuration register */ + PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */ + /* from 0x84 onwards are a number of power management/wakeup frame + * definitions we will probably never need to know about. */ +}; + +enum RxEarlyStatusBits { + ERGood=0x08, ERBad=0x04, EROVW=0x02, EROK=0x01 +}; + +enum ChipCmdBits { + CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, }; + +enum IntrMaskBits { + SERR=0x8000, TimeOut=0x4000, LenChg=0x2000, + FOVW=0x40, PUN_LinkChg=0x20, RXOVW=0x10, + TER=0x08, TOK=0x04, RER=0x02, ROK=0x01 +}; + +/* Interrupt register bits, using my own meaningful names. */ +enum IntrStatusBits { + PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000, + RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10, + TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01, +}; +enum TxStatusBits { + TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000, + TxOutOfWindow=0x20000000, TxAborted=0x40000000, + TxCarrierLost=0x80000000, +}; +enum RxStatusBits { + RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000, + RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004, + RxBadAlign=0x0002, RxStatusOK=0x0001, +}; + +enum MediaStatusBits { + MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08, + MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01, +}; + +enum MIIBMCRBits { + BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000, + BMCRRestartNWay=0x0200, BMCRDuplex=0x0100, +}; + +enum CSCRBits { + CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800, + CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0, + CSCR_LinkDownCmd=0x0f3c0, +}; + +enum RxConfigBits { + RxCfgWrap=0x80, + Eeprom9356=0x40, + AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08, + AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01, +}; + +enum Config1Bits { + VPDEnable=0x02, +}; + +/* EEPROM access */ +#define EE_M1 0x80 /* Mode select bit 1 */ +#define EE_M0 0x40 /* Mode select bit 0 */ +#define EE_CS 0x08 /* EEPROM chip select */ +#define EE_SK 0x04 /* EEPROM shift clock */ +#define EE_DI 0x02 /* Data in */ +#define EE_DO 0x01 /* Data out */ + +/* Offsets within EEPROM (these are word offsets) */ +#define EE_MAC 7 + +static const uint8_t rtl_ee_bits[] = { + [SPI_BIT_SCLK] = EE_SK, + [SPI_BIT_MOSI] = EE_DI, + [SPI_BIT_MISO] = EE_DO, + [SPI_BIT_SS(0)] = ( EE_CS | EE_M1 ), +}; + +static int rtl_spi_read_bit ( struct bit_basher *basher, + unsigned int bit_id ) { + struct rtl8139_nic *rtl = container_of ( basher, struct rtl8139_nic, + spibit.basher ); + uint8_t mask = rtl_ee_bits[bit_id]; + uint8_t eereg; + + eereg = inb ( rtl->ioaddr + Cfg9346 ); + return ( eereg & mask ); +} + +static void rtl_spi_write_bit ( struct bit_basher *basher, + unsigned int bit_id, unsigned long data ) { + struct rtl8139_nic *rtl = container_of ( basher, struct rtl8139_nic, + spibit.basher ); + uint8_t mask = rtl_ee_bits[bit_id]; + uint8_t eereg; + + eereg = inb ( rtl->ioaddr + Cfg9346 ); + eereg &= ~mask; + eereg |= ( data & mask ); + outb ( eereg, rtl->ioaddr + Cfg9346 ); +} + +static struct bit_basher_operations rtl_basher_ops = { + .read = rtl_spi_read_bit, + .write = rtl_spi_write_bit, +}; + +/** Portion of EEPROM available for non-volatile stored options + * + * We use offset 0x40 (i.e. address 0x20), length 0x40. This block is + * marked as VPD in the rtl8139 datasheets, so we use it only if we + * detect that the card is not supporting VPD. + */ +static struct nvo_fragment rtl_nvo_fragments[] = { + { 0x20, 0x40 }, + { 0, 0 } +}; + +/** + * Set up for EEPROM access + * + * @v netdev Net device + */ +static void rtl_init_eeprom ( struct net_device *netdev ) { + struct rtl8139_nic *rtl = netdev->priv; + int ee9356; + int vpd; + + /* Initialise three-wire bus */ + rtl->spibit.basher.op = &rtl_basher_ops; + rtl->spibit.bus.mode = SPI_MODE_THREEWIRE; + init_spi_bit_basher ( &rtl->spibit ); + + /* Detect EEPROM type and initialise three-wire device */ + ee9356 = ( inw ( rtl->ioaddr + RxConfig ) & Eeprom9356 ); + if ( ee9356 ) { + DBGC ( rtl, "rtl8139 %p EEPROM is an AT93C56\n", rtl ); + init_at93c56 ( &rtl->eeprom, 16 ); + } else { + DBGC ( rtl, "rtl8139 %p EEPROM is an AT93C46\n", rtl ); + init_at93c46 ( &rtl->eeprom, 16 ); + } + rtl->eeprom.bus = &rtl->spibit.bus; + + /* Initialise space for non-volatile options, if available */ + vpd = ( inw ( rtl->ioaddr + Config1 ) & VPDEnable ); + if ( vpd ) { + DBGC ( rtl, "rtl8139 %p EEPROM in use for VPD; cannot use " + "for options\n", rtl ); + } else { + nvo_init ( &rtl->nvo, &rtl->eeprom.nvs, rtl_nvo_fragments, + &netdev->refcnt ); + } +} + +/** + * Reset NIC + * + * @v netdev Net device + * + * Issues a hardware reset and waits for the reset to complete. + */ +static void rtl_reset ( struct net_device *netdev ) { + struct rtl8139_nic *rtl = netdev->priv; + + /* Reset chip */ + outb ( CmdReset, rtl->ioaddr + ChipCmd ); + mdelay ( 10 ); + memset ( &rtl->tx, 0, sizeof ( rtl->tx ) ); + rtl->rx.offset = 0; +} + +/** + * Open NIC + * + * @v netdev Net device + * @ret rc Return status code + */ +static int rtl_open ( struct net_device *netdev ) { + struct rtl8139_nic *rtl = netdev->priv; + int i; + + /* Program the MAC address */ + for ( i = 0 ; i < ETH_ALEN ; i++ ) + outb ( netdev->ll_addr[i], rtl->ioaddr + MAC0 + i ); + + /* Set up RX ring */ + rtl->rx.ring = malloc ( RX_BUF_LEN + RX_BUF_PAD ); + if ( ! rtl->rx.ring ) + return -ENOMEM; + outl ( virt_to_bus ( rtl->rx.ring ), rtl->ioaddr + RxBuf ); + DBGC ( rtl, "rtl8139 %p RX ring at %lx\n", + rtl, virt_to_bus ( rtl->rx.ring ) ); + + /* Enable TX and RX */ + outb ( ( CmdRxEnb | CmdTxEnb ), rtl->ioaddr + ChipCmd ); + outl ( ( ( RX_FIFO_THRESH << 13 ) | ( RX_BUF_LEN_IDX << 11 ) | + ( RX_DMA_BURST << 8 ) | AcceptBroadcast | AcceptMulticast | + AcceptMyPhys ), rtl->ioaddr + RxConfig ); + outl ( 0xffffffffUL, rtl->ioaddr + MAR0 + 0 ); + outl ( 0xffffffffUL, rtl->ioaddr + MAR0 + 4 ); + outl ( ( ( TX_DMA_BURST << 8 ) | ( TX_IPG << 24 ) ), + rtl->ioaddr + TxConfig ); + + return 0; +} + +/** + * Close NIC + * + * @v netdev Net device + */ +static void rtl_close ( struct net_device *netdev ) { + struct rtl8139_nic *rtl = netdev->priv; + + /* Reset the hardware to disable everything in one go */ + rtl_reset ( netdev ); + + /* Free RX ring */ + free ( rtl->rx.ring ); + rtl->rx.ring = NULL; +} + +/** + * Transmit packet + * + * @v netdev Network device + * @v iobuf I/O buffer + * @ret rc Return status code + */ +static int rtl_transmit ( struct net_device *netdev, + struct io_buffer *iobuf ) { + struct rtl8139_nic *rtl = netdev->priv; + + /* Check for space in TX ring */ + if ( rtl->tx.iobuf[rtl->tx.next] != NULL ) { + DBGC ( rtl, "rtl8139 %p TX overflow\n", rtl ); + return -ENOBUFS; + } + + /* Pad and align packet */ + iob_pad ( iobuf, ETH_ZLEN ); + + /* Add to TX ring */ + DBGC2 ( rtl, "rtl8139 %p TX id %d at %lx+%zx\n", rtl, rtl->tx.next, + virt_to_bus ( iobuf->data ), iob_len ( iobuf ) ); + rtl->tx.iobuf[rtl->tx.next] = iobuf; + outl ( virt_to_bus ( iobuf->data ), + rtl->ioaddr + TxAddr0 + 4 * rtl->tx.next ); + outl ( ( ( ( TX_FIFO_THRESH & 0x7e0 ) << 11 ) | iob_len ( iobuf ) ), + rtl->ioaddr + TxStatus0 + 4 * rtl->tx.next ); + rtl->tx.next = ( rtl->tx.next + 1 ) % TX_RING_SIZE; + + return 0; +} + +/** + * Poll for received packets + * + * @v netdev Network device + */ +static void rtl_poll ( struct net_device *netdev ) { + struct rtl8139_nic *rtl = netdev->priv; + unsigned int status; + unsigned int tsad; + unsigned int rx_status; + unsigned int rx_len; + struct io_buffer *rx_iob; + int wrapped_len; + int i; + + /* Acknowledge interrupts */ + status = inw ( rtl->ioaddr + IntrStatus ); + if ( ! status ) + return; + outw ( status, rtl->ioaddr + IntrStatus ); + + /* Handle TX completions */ + tsad = inw ( rtl->ioaddr + TxSummary ); + for ( i = 0 ; i < TX_RING_SIZE ; i++ ) { + if ( ( rtl->tx.iobuf[i] != NULL ) && ( tsad & ( 1 << i ) ) ) { + DBGC2 ( rtl, "rtl8139 %p TX id %d complete\n", + rtl, i ); + netdev_tx_complete ( netdev, rtl->tx.iobuf[i] ); + rtl->tx.iobuf[i] = NULL; + } + } + + /* Handle received packets */ + while ( ! ( inw ( rtl->ioaddr + ChipCmd ) & RxBufEmpty ) ) { + rx_status = * ( ( uint16_t * ) + ( rtl->rx.ring + rtl->rx.offset ) ); + rx_len = * ( ( uint16_t * ) + ( rtl->rx.ring + rtl->rx.offset + 2 ) ); + if ( rx_status & RxOK ) { + DBGC2 ( rtl, "rtl8139 %p RX packet at offset " + "%x+%x\n", rtl, rtl->rx.offset, rx_len ); + + rx_iob = alloc_iob ( rx_len ); + if ( ! rx_iob ) { + netdev_rx_err ( netdev, NULL, -ENOMEM ); + /* Leave packet for next call to poll() */ + break; + } + + wrapped_len = ( ( rtl->rx.offset + 4 + rx_len ) + - RX_BUF_LEN ); + if ( wrapped_len < 0 ) + wrapped_len = 0; + + memcpy ( iob_put ( rx_iob, rx_len - wrapped_len ), + rtl->rx.ring + rtl->rx.offset + 4, + rx_len - wrapped_len ); + memcpy ( iob_put ( rx_iob, wrapped_len ), + rtl->rx.ring, wrapped_len ); + + netdev_rx ( netdev, rx_iob ); + } else { + DBGC ( rtl, "rtl8139 %p RX bad packet (status %#04x " + "len %d)\n", rtl, rx_status, rx_len ); + netdev_rx_err ( netdev, NULL, -EINVAL ); + } + rtl->rx.offset = ( ( ( rtl->rx.offset + 4 + rx_len + 3 ) & ~3 ) + % RX_BUF_LEN ); + outw ( rtl->rx.offset - 16, rtl->ioaddr + RxBufPtr ); + } +} + +/** + * Enable/disable interrupts + * + * @v netdev Network device + * @v enable Interrupts should be enabled + */ +static void rtl_irq ( struct net_device *netdev, int enable ) { + struct rtl8139_nic *rtl = netdev->priv; + + DBGC ( rtl, "rtl8139 %p interrupts %s\n", + rtl, ( enable ? "enabled" : "disabled" ) ); + outw ( ( enable ? ( ROK | RER | TOK | TER ) : 0 ), + rtl->ioaddr + IntrMask ); +} + +/** RTL8139 net device operations */ +static struct net_device_operations rtl_operations = { + .open = rtl_open, + .close = rtl_close, + .transmit = rtl_transmit, + .poll = rtl_poll, + .irq = rtl_irq, +}; + +/** + * Probe PCI device + * + * @v pci PCI device + * @v id PCI ID + * @ret rc Return status code + */ +static int rtl_probe ( struct pci_device *pci, + const struct pci_device_id *id __unused ) { + struct net_device *netdev; + struct rtl8139_nic *rtl; + int rc; + + /* Allocate net device */ + netdev = alloc_etherdev ( sizeof ( *rtl ) ); + if ( ! netdev ) + return -ENOMEM; + netdev_init ( netdev, &rtl_operations ); + rtl = netdev->priv; + pci_set_drvdata ( pci, netdev ); + netdev->dev = &pci->dev; + memset ( rtl, 0, sizeof ( *rtl ) ); + rtl->ioaddr = pci->ioaddr; + + /* Fix up PCI device */ + adjust_pci_device ( pci ); + + /* Reset the NIC, set up EEPROM access and read MAC address */ + rtl_reset ( netdev ); + rtl_init_eeprom ( netdev ); + nvs_read ( &rtl->eeprom.nvs, EE_MAC, netdev->hw_addr, ETH_ALEN ); + + /* Mark as link up; we don't yet handle link state */ + netdev_link_up ( netdev ); + + /* Register network device */ + if ( ( rc = register_netdev ( netdev ) ) != 0 ) + goto err_register_netdev; + + /* Register non-volatile storage */ + if ( rtl->nvo.nvs ) { + if ( ( rc = register_nvo ( &rtl->nvo, + netdev_settings ( netdev ) ) ) != 0) + goto err_register_nvo; + } + + return 0; + + err_register_nvo: + unregister_netdev ( netdev ); + err_register_netdev: + rtl_reset ( netdev ); + netdev_nullify ( netdev ); + netdev_put ( netdev ); + return rc; +} + +/** + * Remove PCI device + * + * @v pci PCI device + */ +static void rtl_remove ( struct pci_device *pci ) { + struct net_device *netdev = pci_get_drvdata ( pci ); + struct rtl8139_nic *rtl = netdev->priv; + + if ( rtl->nvo.nvs ) + unregister_nvo ( &rtl->nvo ); + unregister_netdev ( netdev ); + rtl_reset ( netdev ); + netdev_nullify ( netdev ); + netdev_put ( netdev ); +} + +static struct pci_device_id rtl8139_nics[] = { +PCI_ROM(0x10ec, 0x8129, "rtl8129", "Realtek 8129", 0), +PCI_ROM(0x10ec, 0x8139, "rtl8139", "Realtek 8139", 0), +PCI_ROM(0x10ec, 0x8138, "rtl8139b", "Realtek 8139B", 0), +PCI_ROM(0x1186, 0x1300, "dfe538", "DFE530TX+/DFE538TX", 0), +PCI_ROM(0x1113, 0x1211, "smc1211-1", "SMC EZ10/100", 0), +PCI_ROM(0x1112, 0x1211, "smc1211", "SMC EZ10/100", 0), +PCI_ROM(0x1500, 0x1360, "delta8139", "Delta Electronics 8139", 0), +PCI_ROM(0x4033, 0x1360, "addtron8139", "Addtron Technology 8139", 0), +PCI_ROM(0x1186, 0x1340, "dfe690txd", "D-Link DFE690TXD", 0), +PCI_ROM(0x13d1, 0xab06, "fe2000vx", "AboCom FE2000VX", 0), +PCI_ROM(0x1259, 0xa117, "allied8139", "Allied Telesyn 8139", 0), +PCI_ROM(0x14ea, 0xab06, "fnw3603tx", "Planex FNW-3603-TX", 0), +PCI_ROM(0x14ea, 0xab07, "fnw3800tx", "Planex FNW-3800-TX", 0), +PCI_ROM(0xffff, 0x8139, "clone-rtl8139", "Cloned 8139", 0), +}; + +struct pci_driver rtl8139_driver __pci_driver = { + .ids = rtl8139_nics, + .id_count = ( sizeof ( rtl8139_nics ) / sizeof ( rtl8139_nics[0] ) ), + .probe = rtl_probe, + .remove = rtl_remove, +}; + +GRUB_MOD_LICENSE("GPLv2+"); + +GRUB_MOD_INIT(gpxe_rtl8139) +{ + grub_gpxe_register_pci_nic (&rtl8139_driver); +} + +GRUB_MOD_FINI(gpxe_rtl8139) +{ + grub_gpxe_unregister_pci_nic (&rtl8139_driver); +} diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/sis900.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/sis900.c new file mode 100644 index 0000000..da14a09 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/sis900.c @@ -0,0 +1,1304 @@ +/* -*- Mode:C; c-basic-offset:4; -*- */ + +/* + sis900.c: An SiS 900/7016 PCI Fast Ethernet driver for Etherboot + Copyright (C) 2001 Entity Cyber, Inc. + + Revision: 1.0 March 1, 2001 + + Author: Marty Connor (mdc@etherboot.org) + + Adapted from a Linux driver which was written by Donald Becker + and modified by Ollie Lho and Chin-Shan Li of SiS Corporation. + Rewritten for Etherboot by Marty Connor. + + This software may be used and distributed according to the terms + of the GNU Public License (GPL), incorporated herein by reference. + + References: + SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support, + preliminary Rev. 1.0 Jan. 14, 1998 + SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support, + preliminary Rev. 1.0 Nov. 10, 1998 + SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution, + preliminary Rev. 1.0 Jan. 18, 1998 + http://www.sis.com.tw/support/databook.htm */ + +FILE_LICENCE ( GPL_ANY ); + +/* Revision History */ + +/* + 07 Dec 2003 timlegge - Enabled Multicast Support + 06 Dec 2003 timlegge - Fixed relocation issue in 5.2 + 04 Jan 2002 Chien-Yu Chen, Doug Ambrisko, Marty Connor Patch to Etherboot 5.0.5 + Added support for the SiS 630ET plus various bug fixes from linux kernel + source 2.4.17. + 01 March 2001 mdc 1.0 + Initial Release. Tested with PCI based sis900 card and ThinkNIC + computer. + 20 March 2001 P.Koegel + added support for sis630e and PHY ICS1893 and RTL8201 + Testet with SIS730S chipset + ICS1893 +*/ + + +/* Includes */ + +#include "etherboot.h" +#include <gpxe/pci.h> +#include "nic.h" + +#include "sis900.h" + +/* Globals */ + +static struct nic_operations sis900_operations; + +static int sis900_debug = 0; + +static unsigned short vendor, dev_id; +static unsigned long ioaddr; +static u8 pci_revision; + +static unsigned int cur_phy; + +static unsigned int cur_rx; + +struct { + BufferDesc txd; + BufferDesc rxd[NUM_RX_DESC]; + unsigned char txb[TX_BUF_SIZE]; + unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; +} sis900_bufs __shared; +#define txd sis900_bufs.txd +#define rxd sis900_bufs.rxd +#define txb sis900_bufs.txb +#define rxb sis900_bufs.rxb + +#if 0 +static struct mac_chip_info { + const char *name; + u16 vendor_id, device_id, flags; + int io_size; +} mac_chip_table[] = { + { "SiS 900 PCI Fast Ethernet", PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS900, + PCI_COMMAND_IO|PCI_COMMAND_MASTER, SIS900_TOTAL_SIZE}, + { "SiS 7016 PCI Fast Ethernet",PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS7016, + PCI_COMMAND_IO|PCI_COMMAND_MASTER, SIS900_TOTAL_SIZE}, + {0,0,0,0,0} /* 0 terminated list. */ +}; +#endif + +static void sis900_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex); +static void amd79c901_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex); +static void ics1893_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex); +static void rtl8201_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex); +static void vt6103_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex); + +static struct mii_chip_info { + const char * name; + u16 phy_id0; + u16 phy_id1; + void (*read_mode) (struct nic *nic, int phy_addr, int *speed, int *duplex); +} mii_chip_table[] = { + {"SiS 900 Internal MII PHY", 0x001d, 0x8000, sis900_read_mode}, + {"SiS 7014 Physical Layer Solution", 0x0016, 0xf830,sis900_read_mode}, + {"SiS 900 on Foxconn 661 7MI", 0x0143, 0xBC70, sis900_read_mode}, + {"AMD 79C901 10BASE-T PHY", 0x0000, 0x6B70, amd79c901_read_mode}, + {"AMD 79C901 HomePNA PHY", 0x0000, 0x6B90, amd79c901_read_mode}, + {"ICS 1893 Integrated PHYceiver" , 0x0015, 0xf440,ics1893_read_mode}, +// {"NS 83851 PHY",0x2000, 0x5C20, MIX }, + {"RTL 8201 10/100Mbps Phyceiver" , 0x0000, 0x8200,rtl8201_read_mode}, + {"VIA 6103 10/100Mbps Phyceiver", 0x0101, 0x8f20,vt6103_read_mode}, + {0,0,0,0} +}; + +static struct mii_phy { + struct mii_phy * next; + struct mii_chip_info * chip_info; + int phy_addr; + u16 status; +} mii; + + + +#if 0 +// PCI to ISA bridge for SIS640E access +static struct pci_device_id pci_isa_bridge_list[] = { + { .vendor = 0x1039, .device = 0x0008, + .name = "SIS 85C503/5513 PCI to ISA bridge"}, +}; + +PCI_DRIVER( sis_bridge_pci_driver, pci_isa_bridge_list, PCI_NO_CLASS ); + +static struct device_driver sis_bridge_driver = { + .name = "SIS ISA bridge", + .bus_driver = &pci_driver, + .bus_driver_info = ( struct bus_driver_info * ) &sis_bridge_pci_driver, +}; +#endif + +/* Function Prototypes */ + +static int sis900_probe(struct nic *nic,struct pci_device *pci); + +static u16 sis900_read_eeprom(int location); +static void sis900_mdio_reset(long mdio_addr); +static void sis900_mdio_idle(long mdio_addr); +static u16 sis900_mdio_read(int phy_id, int location); +#if 0 +static void sis900_mdio_write(int phy_id, int location, int val); +#endif +static void sis900_init(struct nic *nic); + +static void sis900_reset(struct nic *nic); + +static void sis900_init_rxfilter(struct nic *nic); +static void sis900_init_txd(struct nic *nic); +static void sis900_init_rxd(struct nic *nic); +static void sis900_set_rx_mode(struct nic *nic); +static void sis900_check_mode(struct nic *nic); + +static void sis900_transmit(struct nic *nic, const char *d, + unsigned int t, unsigned int s, const char *p); +static int sis900_poll(struct nic *nic, int retrieve); + +static void sis900_disable(struct nic *nic); + +static void sis900_irq(struct nic *nic, irq_action_t action); + +/** + * sis900_get_mac_addr: - Get MAC address for stand alone SiS900 model + * @pci_dev: the sis900 pci device + * @net_dev: the net device to get address for + * + * Older SiS900 and friends, use EEPROM to store MAC address. + * MAC address is read from read_eeprom() into @net_dev->dev_addr. + */ + +static int sis900_get_mac_addr(struct pci_device * pci_dev __unused, struct nic *nic) +{ + u16 signature; + int i; + + /* check to see if we have sane EEPROM */ + signature = (u16) sis900_read_eeprom( EEPROMSignature); + if (signature == 0xffff || signature == 0x0000) { + printf ("sis900_probe: Error EERPOM read %hX\n", signature); + return 0; + } + + /* get MAC address from EEPROM */ + for (i = 0; i < 3; i++) + ((u16 *)(nic->node_addr))[i] = sis900_read_eeprom(i+EEPROMMACAddr); + return 1; +} + +/** + * sis96x_get_mac_addr: - Get MAC address for SiS962 or SiS963 model + * @pci_dev: the sis900 pci device + * @net_dev: the net device to get address for + * + * SiS962 or SiS963 model, use EEPROM to store MAC address. And EEPROM + * is shared by + * LAN and 1394. When access EEPROM, send EEREQ signal to hardware first + * and wait for EEGNT. If EEGNT is ON, EEPROM is permitted to be access + * by LAN, otherwise is not. After MAC address is read from EEPROM, send + * EEDONE signal to refuse EEPROM access by LAN. + * The EEPROM map of SiS962 or SiS963 is different to SiS900. + * The signature field in SiS962 or SiS963 spec is meaningless. + * MAC address is read into @net_dev->dev_addr. + */ + +static int sis96x_get_mac_addr(struct pci_device * pci_dev __unused, struct nic *nic) +{ +/* long ioaddr = net_dev->base_addr; */ + long ee_addr = ioaddr + mear; + u32 waittime = 0; + int i; + + printf("Alternate function\n"); + + outl(EEREQ, ee_addr); + while(waittime < 2000) { + if(inl(ee_addr) & EEGNT) { + + /* get MAC address from EEPROM */ + for (i = 0; i < 3; i++) + ((u16 *)(nic->node_addr))[i] = sis900_read_eeprom(i+EEPROMMACAddr); + + outl(EEDONE, ee_addr); + return 1; + } else { + udelay(1); + waittime ++; + } + } + outl(EEDONE, ee_addr); + return 0; +} + +/** + * sis630e_get_mac_addr: - Get MAC address for SiS630E model + * @pci_dev: the sis900 pci device + * @net_dev: the net device to get address for + * + * SiS630E model, use APC CMOS RAM to store MAC address. + * APC CMOS RAM is accessed through ISA bridge. + * MAC address is read into @net_dev->dev_addr. + */ + +static int sis630e_get_mac_addr(struct pci_device * pci_dev __unused, struct nic *nic) +{ +#if 0 + u8 reg; + int i; + struct bus_loc bus_loc; + union { + struct bus_dev bus_dev; + struct pci_device isa_bridge; + } u; + + /* find PCI to ISA bridge */ + memset(&bus_loc, 0, sizeof(bus_loc)); + if ( ! find_by_driver ( &bus_loc, &u.bus_dev, &sis_bridge_driver, 0 ) ) + return 0; + + pci_read_config_byte(&u.isa_bridge, 0x48, ®); + pci_write_config_byte(&u.isa_bridge, 0x48, reg | 0x40); + + for (i = 0; i < ETH_ALEN; i++) + { + outb(0x09 + i, 0x70); + ((u8 *)(nic->node_addr))[i] = inb(0x71); + } + pci_write_config_byte(&u.isa_bridge, 0x48, reg & ~0x40); + + return 1; +#endif + + /* Does not work with current bus/device model */ + memset ( nic->node_addr, 0, sizeof ( nic->node_addr ) ); + return 0; +} + +/** + * sis630e_get_mac_addr: - Get MAC address for SiS630E model + * @pci_dev: the sis900 pci device + * @net_dev: the net device to get address for + * + * SiS630E model, use APC CMOS RAM to store MAC address. + * APC CMOS RAM is accessed through ISA bridge. + * MAC address is read into @net_dev->dev_addr. + */ + +static int sis635_get_mac_addr(struct pci_device * pci_dev __unused, struct nic *nic) +{ + u32 rfcrSave; + u32 i; + + + rfcrSave = inl(rfcr + ioaddr); + + outl(rfcrSave | RELOAD, ioaddr + cr); + outl(0, ioaddr + cr); + + /* disable packet filtering before setting filter */ + outl(rfcrSave & ~RFEN, rfcr + ioaddr); + + /* load MAC addr to filter data register */ + for (i = 0 ; i < 3 ; i++) { + outl((i << RFADDR_shift), ioaddr + rfcr); + *( ((u16 *)nic->node_addr) + i) = inw(ioaddr + rfdr); + } + + /* enable packet filitering */ + outl(rfcrSave | RFEN, rfcr + ioaddr); + + return 1; +} + +/* + * Function: sis900_probe + * + * Description: initializes initializes the NIC, retrieves the + * MAC address of the card, and sets up some globals required by + * other routines. + * + * Side effects: + * leaves the ioaddress of the sis900 chip in the variable ioaddr. + * leaves the sis900 initialized, and ready to recieve packets. + * + * Returns: struct nic *: pointer to NIC data structure + */ + +static int sis900_probe ( struct nic *nic, struct pci_device *pci ) { + + int i; + int found=0; + int phy_addr; + u8 revision; + int ret; + + if (pci->ioaddr == 0) + return 0; + + nic->irqno = 0; + nic->ioaddr = pci->ioaddr; + + ioaddr = pci->ioaddr; + vendor = pci->vendor; + dev_id = pci->device; + + /* wakeup chip */ + pci_write_config_dword(pci, 0x40, 0x00000000); + + adjust_pci_device(pci); + + /* get MAC address */ + ret = 0; + pci_read_config_byte(pci, PCI_REVISION, &revision); + + /* save for use later in sis900_reset() */ + pci_revision = revision; + + if (revision == SIS630E_900_REV) + ret = sis630e_get_mac_addr(pci, nic); + else if ((revision > 0x81) && (revision <= 0x90)) + ret = sis635_get_mac_addr(pci, nic); + else if (revision == SIS96x_900_REV) + ret = sis96x_get_mac_addr(pci, nic); + else + ret = sis900_get_mac_addr(pci, nic); + + if (ret == 0) + { + printf ("sis900_probe: Error MAC address not found\n"); + return 0; + } + + /* 630ET : set the mii access mode as software-mode */ + if (revision == SIS630ET_900_REV) + outl(ACCESSMODE | inl(ioaddr + cr), ioaddr + cr); + + DBG( "sis900_probe: Vendor:%#hX Device:%#hX\n", vendor, dev_id ); + + /* probe for mii transceiver */ + /* search for total of 32 possible mii phy addresses */ + + found = 0; + for (phy_addr = 0; phy_addr < 32; phy_addr++) { + u16 mii_status; + u16 phy_id0, phy_id1; + + mii_status = sis900_mdio_read(phy_addr, MII_STATUS); + if (mii_status == 0xffff || mii_status == 0x0000) + /* the mii is not accessable, try next one */ + continue; + + phy_id0 = sis900_mdio_read(phy_addr, MII_PHY_ID0); + phy_id1 = sis900_mdio_read(phy_addr, MII_PHY_ID1); + + /* search our mii table for the current mii */ + for (i = 0; mii_chip_table[i].phy_id1; i++) { + + if ((phy_id0 == mii_chip_table[i].phy_id0) && + ((phy_id1 & 0xFFF0) == mii_chip_table[i].phy_id1)){ + + printf("sis900_probe: %s transceiver found at address %d.\n", + mii_chip_table[i].name, phy_addr); + + mii.chip_info = &mii_chip_table[i]; + mii.phy_addr = phy_addr; + mii.status = sis900_mdio_read(phy_addr, MII_STATUS); + mii.next = NULL; + + found=1; + break; + } + } + } + + if (found == 0) { + printf("sis900_probe: No MII transceivers found!\n"); + return 0; + } + + /* Arbitrarily select the last PHY found as current PHY */ + cur_phy = mii.phy_addr; + printf("sis900_probe: Using %s as default\n", mii.chip_info->name); + + /* initialize device */ + sis900_init(nic); + nic->nic_op = &sis900_operations; + + return 1; +} + + + + +/* + * EEPROM Routines: These functions read and write to EEPROM for + * retrieving the MAC address and other configuration information about + * the card. + */ + +/* Delay between EEPROM clock transitions. */ +#define eeprom_delay() inl(ee_addr) + + +/* Function: sis900_read_eeprom + * + * Description: reads and returns a given location from EEPROM + * + * Arguments: int location: requested EEPROM location + * + * Returns: u16: contents of requested EEPROM location + * + */ + +/* Read Serial EEPROM through EEPROM Access Register, Note that location is + in word (16 bits) unit */ +static u16 sis900_read_eeprom(int location) +{ + int i; + u16 retval = 0; + long ee_addr = ioaddr + mear; + u32 read_cmd = location | EEread; + + outl(0, ee_addr); + eeprom_delay(); + outl(EECS, ee_addr); + eeprom_delay(); + + /* Shift the read command (9) bits out. */ + for (i = 8; i >= 0; i--) { + u32 dataval = (read_cmd & (1 << i)) ? EEDI | EECS : EECS; + outl(dataval, ee_addr); + eeprom_delay(); + outl(dataval | EECLK, ee_addr); + eeprom_delay(); + } + outl(EECS, ee_addr); + eeprom_delay(); + + /* read the 16-bits data in */ + for (i = 16; i > 0; i--) { + outl(EECS, ee_addr); + eeprom_delay(); + outl(EECS | EECLK, ee_addr); + eeprom_delay(); + retval = (retval << 1) | ((inl(ee_addr) & EEDO) ? 1 : 0); + eeprom_delay(); + } + + /* Terminate the EEPROM access. */ + outl(0, ee_addr); + eeprom_delay(); +// outl(EECLK, ee_addr); + + return (retval); +} + +#define sis900_mdio_delay() inl(mdio_addr) + + +/* + Read and write the MII management registers using software-generated + serial MDIO protocol. Note that the command bits and data bits are + send out seperately +*/ + +static void sis900_mdio_idle(long mdio_addr) +{ + outl(MDIO | MDDIR, mdio_addr); + sis900_mdio_delay(); + outl(MDIO | MDDIR | MDC, mdio_addr); +} + +/* Syncronize the MII management interface by shifting 32 one bits out. */ +static void sis900_mdio_reset(long mdio_addr) +{ + int i; + + for (i = 31; i >= 0; i--) { + outl(MDDIR | MDIO, mdio_addr); + sis900_mdio_delay(); + outl(MDDIR | MDIO | MDC, mdio_addr); + sis900_mdio_delay(); + } + return; +} + +static u16 sis900_mdio_read(int phy_id, int location) +{ + long mdio_addr = ioaddr + mear; + int mii_cmd = MIIread|(phy_id<<MIIpmdShift)|(location<<MIIregShift); + u16 retval = 0; + int i; + + sis900_mdio_reset(mdio_addr); + sis900_mdio_idle(mdio_addr); + + for (i = 15; i >= 0; i--) { + int dataval = (mii_cmd & (1 << i)) ? MDDIR | MDIO : MDDIR; + outl(dataval, mdio_addr); + sis900_mdio_delay(); + outl(dataval | MDC, mdio_addr); + sis900_mdio_delay(); + } + + /* Read the 16 data bits. */ + for (i = 16; i > 0; i--) { + outl(0, mdio_addr); + sis900_mdio_delay(); + retval = (retval << 1) | ((inl(mdio_addr) & MDIO) ? 1 : 0); + outl(MDC, mdio_addr); + sis900_mdio_delay(); + } + outl(0x00, mdio_addr); + return retval; +} + +#if 0 +static void sis900_mdio_write(int phy_id, int location, int value) +{ + long mdio_addr = ioaddr + mear; + int mii_cmd = MIIwrite|(phy_id<<MIIpmdShift)|(location<<MIIregShift); + int i; + + sis900_mdio_reset(mdio_addr); + sis900_mdio_idle(mdio_addr); + + /* Shift the command bits out. */ + for (i = 15; i >= 0; i--) { + int dataval = (mii_cmd & (1 << i)) ? MDDIR | MDIO : MDDIR; + outb(dataval, mdio_addr); + sis900_mdio_delay(); + outb(dataval | MDC, mdio_addr); + sis900_mdio_delay(); + } + sis900_mdio_delay(); + + /* Shift the value bits out. */ + for (i = 15; i >= 0; i--) { + int dataval = (value & (1 << i)) ? MDDIR | MDIO : MDDIR; + outl(dataval, mdio_addr); + sis900_mdio_delay(); + outl(dataval | MDC, mdio_addr); + sis900_mdio_delay(); + } + sis900_mdio_delay(); + + /* Clear out extra bits. */ + for (i = 2; i > 0; i--) { + outb(0, mdio_addr); + sis900_mdio_delay(); + outb(MDC, mdio_addr); + sis900_mdio_delay(); + } + outl(0x00, mdio_addr); + return; +} +#endif + + +/* Function: sis900_init + * + * Description: resets the ethernet controller chip and various + * data structures required for sending and receiving packets. + * + * Arguments: struct nic *nic: NIC data structure + * + * returns: void. + */ + +static void +sis900_init(struct nic *nic) +{ + /* Soft reset the chip. */ + sis900_reset(nic); + + sis900_init_rxfilter(nic); + + sis900_init_txd(nic); + sis900_init_rxd(nic); + + sis900_set_rx_mode(nic); + + sis900_check_mode(nic); + + outl(RxENA| inl(ioaddr + cr), ioaddr + cr); +} + + +/* + * Function: sis900_reset + * + * Description: disables interrupts and soft resets the controller chip + * + * Arguments: struct nic *nic: NIC data structure + * + * Returns: void. + */ + +static void +sis900_reset(struct nic *nic __unused) +{ + int i = 0; + u32 status = TxRCMP | RxRCMP; + + outl(0, ioaddr + ier); + outl(0, ioaddr + imr); + outl(0, ioaddr + rfcr); + + outl(RxRESET | TxRESET | RESET | inl(ioaddr + cr), ioaddr + cr); + + /* Check that the chip has finished the reset. */ + while (status && (i++ < 1000)) { + status ^= (inl(isr + ioaddr) & status); + } + + if( (pci_revision >= SIS635A_900_REV) || (pci_revision == SIS900B_900_REV) ) + outl(PESEL | RND_CNT, ioaddr + cfg); + else + outl(PESEL, ioaddr + cfg); +} + + +/* Function: sis_init_rxfilter + * + * Description: sets receive filter address to our MAC address + * + * Arguments: struct nic *nic: NIC data structure + * + * returns: void. + */ + +static void +sis900_init_rxfilter(struct nic *nic) +{ + u32 rfcrSave; + int i; + + rfcrSave = inl(rfcr + ioaddr); + + /* disable packet filtering before setting filter */ + outl(rfcrSave & ~RFEN, rfcr + ioaddr); + + /* load MAC addr to filter data register */ + for (i = 0 ; i < 3 ; i++) { + u32 w; + + w = (u32) *((u16 *)(nic->node_addr)+i); + outl((i << RFADDR_shift), ioaddr + rfcr); + outl(w, ioaddr + rfdr); + + if (sis900_debug > 0) + printf("sis900_init_rxfilter: Receive Filter Addrss[%d]=%X\n", + i, inl(ioaddr + rfdr)); + } + + /* enable packet filitering */ + outl(rfcrSave | RFEN, rfcr + ioaddr); +} + + +/* + * Function: sis_init_txd + * + * Description: initializes the Tx descriptor + * + * Arguments: struct nic *nic: NIC data structure + * + * returns: void. + */ + +static void +sis900_init_txd(struct nic *nic __unused) +{ + txd.link = (u32) 0; + txd.cmdsts = (u32) 0; + txd.bufptr = virt_to_bus(&txb[0]); + + /* load Transmit Descriptor Register */ + outl(virt_to_bus(&txd), ioaddr + txdp); + if (sis900_debug > 0) + printf("sis900_init_txd: TX descriptor register loaded with: %X\n", + inl(ioaddr + txdp)); +} + + +/* Function: sis_init_rxd + * + * Description: initializes the Rx descriptor ring + * + * Arguments: struct nic *nic: NIC data structure + * + * Returns: void. + */ + +static void +sis900_init_rxd(struct nic *nic __unused) +{ + int i; + + cur_rx = 0; + + /* init RX descriptor */ + for (i = 0; i < NUM_RX_DESC; i++) { + rxd[i].link = virt_to_bus((i+1 < NUM_RX_DESC) ? &rxd[i+1] : &rxd[0]); + rxd[i].cmdsts = (u32) RX_BUF_SIZE; + rxd[i].bufptr = virt_to_bus(&rxb[i*RX_BUF_SIZE]); + if (sis900_debug > 0) + printf("sis900_init_rxd: rxd[%d]=%p link=%X cmdsts=%X bufptr=%X\n", + i, &rxd[i], (unsigned int) rxd[i].link, (unsigned int) rxd[i].cmdsts, + (unsigned int) rxd[i].bufptr); + } + + /* load Receive Descriptor Register */ + outl(virt_to_bus(&rxd[0]), ioaddr + rxdp); + + if (sis900_debug > 0) + printf("sis900_init_rxd: RX descriptor register loaded with: %X\n", + inl(ioaddr + rxdp)); + +} + + +/* Function: sis_init_rxd + * + * Description: + * sets the receive mode to accept all broadcast packets and packets + * with our MAC address, and reject all multicast packets. + * + * Arguments: struct nic *nic: NIC data structure + * + * Returns: void. + */ + +static void sis900_set_rx_mode(struct nic *nic __unused) +{ + int i, table_entries; + u32 rx_mode; + u16 mc_filter[16] = {0}; /* 256/128 bits multicast hash table */ + + if((pci_revision == SIS635A_900_REV) || (pci_revision == SIS900B_900_REV)) + table_entries = 16; + else + table_entries = 8; + + /* accept all multicast packet */ + rx_mode = RFAAB | RFAAM; + for (i = 0; i < table_entries; i++) + mc_filter[i] = 0xffff; + + /* update Multicast Hash Table in Receive Filter */ + for (i = 0; i < table_entries; i++) { + /* why plus 0x04? That makes the correct value for hash table. */ + outl((u32)(0x00000004+i) << RFADDR_shift, ioaddr + rfcr); + outl(mc_filter[i], ioaddr + rfdr); + } + + /* Accept Broadcast and multicast packets, destination addresses that match + our MAC address */ + outl(RFEN | rx_mode, ioaddr + rfcr); + + return; +} + + +/* Function: sis900_check_mode + * + * Description: checks the state of transmit and receive + * parameters on the NIC, and updates NIC registers to match + * + * Arguments: struct nic *nic: NIC data structure + * + * Returns: void. + */ + +static void +sis900_check_mode(struct nic *nic) +{ + int speed, duplex; + u32 tx_flags = 0, rx_flags = 0; + + mii.chip_info->read_mode(nic, cur_phy, &speed, &duplex); + + if( inl(ioaddr + cfg) & EDB_MASTER_EN ) { + tx_flags = TxATP | (DMA_BURST_64 << TxMXDMA_shift) | (TX_FILL_THRESH << TxFILLT_shift); + rx_flags = DMA_BURST_64 << RxMXDMA_shift; + } + else { + tx_flags = TxATP | (DMA_BURST_512 << TxMXDMA_shift) | (TX_FILL_THRESH << TxFILLT_shift); + rx_flags = DMA_BURST_512 << RxMXDMA_shift; + } + + if (speed == HW_SPEED_HOME || speed == HW_SPEED_10_MBPS) { + rx_flags |= (RxDRNT_10 << RxDRNT_shift); + tx_flags |= (TxDRNT_10 << TxDRNT_shift); + } + else { + rx_flags |= (RxDRNT_100 << RxDRNT_shift); + tx_flags |= (TxDRNT_100 << TxDRNT_shift); + } + + if (duplex == FDX_CAPABLE_FULL_SELECTED) { + tx_flags |= (TxCSI | TxHBI); + rx_flags |= RxATX; + } + + outl (tx_flags, ioaddr + txcfg); + outl (rx_flags, ioaddr + rxcfg); +} + + +/* Function: sis900_read_mode + * + * Description: retrieves and displays speed and duplex + * parameters from the NIC + * + * Arguments: struct nic *nic: NIC data structure + * + * Returns: void. + */ + +static void +sis900_read_mode(struct nic *nic __unused, int phy_addr, int *speed, int *duplex) +{ + int i = 0; + u32 status; + u16 phy_id0, phy_id1; + + /* STSOUT register is Latched on Transition, read operation updates it */ + do { + status = sis900_mdio_read(phy_addr, MII_STSOUT); + } while (i++ < 2); + + *speed = HW_SPEED_10_MBPS; + *duplex = FDX_CAPABLE_HALF_SELECTED; + + if (status & (MII_NWAY_TX | MII_NWAY_TX_FDX)) + *speed = HW_SPEED_100_MBPS; + if (status & ( MII_NWAY_TX_FDX | MII_NWAY_T_FDX)) + *duplex = FDX_CAPABLE_FULL_SELECTED; + + /* Workaround for Realtek RTL8201 PHY issue */ + phy_id0 = sis900_mdio_read(phy_addr, MII_PHY_ID0); + phy_id1 = sis900_mdio_read(phy_addr, MII_PHY_ID1); + if((phy_id0 == 0x0000) && ((phy_id1 & 0xFFF0) == 0x8200)){ + if(sis900_mdio_read(phy_addr, MII_CONTROL) & MII_CNTL_FDX) + *duplex = FDX_CAPABLE_FULL_SELECTED; + if(sis900_mdio_read(phy_addr, 0x0019) & 0x01) + *speed = HW_SPEED_100_MBPS; + } + + if (status & MII_STSOUT_LINK_FAIL) + printf("sis900_read_mode: Media Link Off\n"); + else + printf("sis900_read_mode: Media Link On %s %s-duplex \n", + *speed == HW_SPEED_100_MBPS ? + "100mbps" : "10mbps", + *duplex == FDX_CAPABLE_FULL_SELECTED ? + "full" : "half"); +} + + +/* Function: amd79c901_read_mode + * + * Description: retrieves and displays speed and duplex + * parameters from the NIC + * + * Arguments: struct nic *nic: NIC data structure + * + * Returns: void. + */ + +static void +amd79c901_read_mode(struct nic *nic __unused, int phy_addr, int *speed, int *duplex) +{ + int i; + u16 status; + + for (i = 0; i < 2; i++) + status = sis900_mdio_read(phy_addr, MII_STATUS); + + if (status & MII_STAT_CAN_AUTO) { + /* 10BASE-T PHY */ + for (i = 0; i < 2; i++) + status = sis900_mdio_read(phy_addr, MII_STATUS_SUMMARY); + if (status & MII_STSSUM_SPD) + *speed = HW_SPEED_100_MBPS; + else + *speed = HW_SPEED_10_MBPS; + if (status & MII_STSSUM_DPLX) + *duplex = FDX_CAPABLE_FULL_SELECTED; + else + *duplex = FDX_CAPABLE_HALF_SELECTED; + + if (status & MII_STSSUM_LINK) + printf("amd79c901_read_mode: Media Link On %s %s-duplex \n", + *speed == HW_SPEED_100_MBPS ? + "100mbps" : "10mbps", + *duplex == FDX_CAPABLE_FULL_SELECTED ? + "full" : "half"); + else + printf("amd79c901_read_mode: Media Link Off\n"); + } + else { + /* HomePNA */ + *speed = HW_SPEED_HOME; + *duplex = FDX_CAPABLE_HALF_SELECTED; + if (status & MII_STAT_LINK) + printf("amd79c901_read_mode:Media Link On 1mbps half-duplex \n"); + else + printf("amd79c901_read_mode: Media Link Off\n"); + } +} + + +/** + * ics1893_read_mode: - read media mode for ICS1893 PHY + * @net_dev: the net device to read mode for + * @phy_addr: mii phy address + * @speed: the transmit speed to be determined + * @duplex: the duplex mode to be determined + * + * ICS1893 PHY use Quick Poll Detailed Status register + * to determine the speed and duplex mode for sis900 + */ + +static void ics1893_read_mode(struct nic *nic __unused, int phy_addr, int *speed, int *duplex) +{ + int i = 0; + u32 status; + + /* MII_QPDSTS is Latched, read twice in succession will reflect the current state */ + for (i = 0; i < 2; i++) + status = sis900_mdio_read(phy_addr, MII_QPDSTS); + + if (status & MII_STSICS_SPD) + *speed = HW_SPEED_100_MBPS; + else + *speed = HW_SPEED_10_MBPS; + + if (status & MII_STSICS_DPLX) + *duplex = FDX_CAPABLE_FULL_SELECTED; + else + *duplex = FDX_CAPABLE_HALF_SELECTED; + + if (status & MII_STSICS_LINKSTS) + printf("ics1893_read_mode: Media Link On %s %s-duplex \n", + *speed == HW_SPEED_100_MBPS ? + "100mbps" : "10mbps", + *duplex == FDX_CAPABLE_FULL_SELECTED ? + "full" : "half"); + else + printf("ics1893_read_mode: Media Link Off\n"); +} + +/** + * rtl8201_read_mode: - read media mode for rtl8201 phy + * @nic: the net device to read mode for + * @phy_addr: mii phy address + * @speed: the transmit speed to be determined + * @duplex: the duplex mode to be determined + * + * read MII_STATUS register from rtl8201 phy + * to determine the speed and duplex mode for sis900 + */ + +static void rtl8201_read_mode(struct nic *nic __unused, int phy_addr, int *speed, int *duplex) +{ + u32 status; + + status = sis900_mdio_read(phy_addr, MII_STATUS); + + if (status & MII_STAT_CAN_TX_FDX) { + *speed = HW_SPEED_100_MBPS; + *duplex = FDX_CAPABLE_FULL_SELECTED; + } + else if (status & MII_STAT_CAN_TX) { + *speed = HW_SPEED_100_MBPS; + *duplex = FDX_CAPABLE_HALF_SELECTED; + } + else if (status & MII_STAT_CAN_T_FDX) { + *speed = HW_SPEED_10_MBPS; + *duplex = FDX_CAPABLE_FULL_SELECTED; + } + else if (status & MII_STAT_CAN_T) { + *speed = HW_SPEED_10_MBPS; + *duplex = FDX_CAPABLE_HALF_SELECTED; + } + + if (status & MII_STAT_LINK) + printf("rtl8201_read_mode: Media Link On %s %s-duplex \n", + *speed == HW_SPEED_100_MBPS ? + "100mbps" : "10mbps", + *duplex == FDX_CAPABLE_FULL_SELECTED ? + "full" : "half"); + else + printf("rtl8201_read_config_mode: Media Link Off\n"); +} + +/** + * vt6103_read_mode: - read media mode for vt6103 phy + * @nic: the net device to read mode for + * @phy_addr: mii phy address + * @speed: the transmit speed to be determined + * @duplex: the duplex mode to be determined + * + * read MII_STATUS register from rtl8201 phy + * to determine the speed and duplex mode for sis900 + */ + +static void vt6103_read_mode(struct nic *nic __unused, int phy_addr, int *speed, int *duplex) +{ + u32 status; + + status = sis900_mdio_read(phy_addr, MII_STATUS); + + if (status & MII_STAT_CAN_TX_FDX) { + *speed = HW_SPEED_100_MBPS; + *duplex = FDX_CAPABLE_FULL_SELECTED; + } + else if (status & MII_STAT_CAN_TX) { + *speed = HW_SPEED_100_MBPS; + *duplex = FDX_CAPABLE_HALF_SELECTED; + } + else if (status & MII_STAT_CAN_T_FDX) { + *speed = HW_SPEED_10_MBPS; + *duplex = FDX_CAPABLE_FULL_SELECTED; + } + else if (status & MII_STAT_CAN_T) { + *speed = HW_SPEED_10_MBPS; + *duplex = FDX_CAPABLE_HALF_SELECTED; + } + + if (status & MII_STAT_LINK) + printf("vt6103_read_mode: Media Link On %s %s-duplex \n", + *speed == HW_SPEED_100_MBPS ? + "100mbps" : "10mbps", + *duplex == FDX_CAPABLE_FULL_SELECTED ? + "full" : "half"); + else + printf("vt6103_read_config_mode: Media Link Off\n"); +} + +/* Function: sis900_transmit + * + * Description: transmits a packet and waits for completion or timeout. + * + * Arguments: char d[6]: destination ethernet address. + * unsigned short t: ethernet protocol type. + * unsigned short s: size of the data-part of the packet. + * char *p: the data for the packet. + * + * Returns: void. + */ + +static void +sis900_transmit(struct nic *nic, + const char *d, /* Destination */ + unsigned int t, /* Type */ + unsigned int s, /* size */ + const char *p) /* Packet */ +{ + u32 to, nstype; + volatile u32 tx_status; + + /* Stop the transmitter */ + outl(TxDIS | inl(ioaddr + cr), ioaddr + cr); + + /* load Transmit Descriptor Register */ + outl(virt_to_bus(&txd), ioaddr + txdp); + if (sis900_debug > 1) + printf("sis900_transmit: TX descriptor register loaded with: %X\n", + inl(ioaddr + txdp)); + + memcpy(txb, d, ETH_ALEN); + memcpy(txb + ETH_ALEN, nic->node_addr, ETH_ALEN); + nstype = htons(t); + memcpy(txb + 2 * ETH_ALEN, (char*)&nstype, 2); + memcpy(txb + ETH_HLEN, p, s); + + s += ETH_HLEN; + s &= DSIZE; + + if (sis900_debug > 1) + printf("sis900_transmit: sending %d bytes ethtype %hX\n", (int) s, t); + + /* pad to minimum packet size */ + while (s < ETH_ZLEN) + txb[s++] = '\0'; + + /* set the transmit buffer descriptor and enable Transmit State Machine */ + txd.bufptr = virt_to_bus(&txb[0]); + txd.cmdsts = (u32) OWN | s; + + /* restart the transmitter */ + outl(TxENA | inl(ioaddr + cr), ioaddr + cr); + + if (sis900_debug > 1) + printf("sis900_transmit: Queued Tx packet size %d.\n", (int) s); + + to = currticks() + TX_TIMEOUT; + + while (((tx_status=txd.cmdsts) & OWN) && (currticks() < to)) + /* wait */ ; + + if (currticks() >= to) { + printf("sis900_transmit: TX Timeout! Tx status %X.\n", + (unsigned int) tx_status); + } + + if (tx_status & (ABORT | UNDERRUN | OWCOLL)) { + /* packet unsuccessfully transmited */ + printf("sis900_transmit: Transmit error, Tx status %X.\n", + (unsigned int) tx_status); + } + /* Disable interrupts by clearing the interrupt mask. */ + outl(0, ioaddr + imr); +} + + +/* Function: sis900_poll + * + * Description: checks for a received packet and returns it if found. + * + * Arguments: struct nic *nic: NIC data structure + * + * Returns: 1 if a packet was recieved. + * 0 if no pacet was recieved. + * + * Side effects: + * Returns (copies) the packet to the array nic->packet. + * Returns the length of the packet in nic->packetlen. + */ + +static int +sis900_poll(struct nic *nic, int retrieve) +{ + u32 rx_status = rxd[cur_rx].cmdsts; + u32 intr_status; + int retstat = 0; + + /* acknowledge interrupts by reading interrupt status register */ + intr_status = inl(ioaddr + isr); + + if (sis900_debug > 2) + printf("sis900_poll: cur_rx:%d, status:%X\n", cur_rx, + (unsigned int) rx_status); + + if (!(rx_status & OWN)) + return retstat; + + if (sis900_debug > 1) + printf("sis900_poll: got a packet: cur_rx:%d, status:%X\n", + cur_rx, (unsigned int) rx_status); + + if ( ! retrieve ) return 1; + + nic->packetlen = (rx_status & DSIZE) - CRC_SIZE; + + if (rx_status & (ABORT|OVERRUN|TOOLONG|RUNT|RXISERR|CRCERR|FAERR)) { + /* corrupted packet received */ + printf("sis900_poll: Corrupted packet received, buffer status = %X\n", + (unsigned int) rx_status); + retstat = 0; + } else { + /* give packet to higher level routine */ + memcpy(nic->packet, (rxb + cur_rx*RX_BUF_SIZE), nic->packetlen); + retstat = 1; + } + + /* return the descriptor and buffer to receive ring */ + rxd[cur_rx].cmdsts = RX_BUF_SIZE; + rxd[cur_rx].bufptr = virt_to_bus(&rxb[cur_rx*RX_BUF_SIZE]); + + if (++cur_rx == NUM_RX_DESC) + cur_rx = 0; + + /* re-enable the potentially idle receive state machine */ + outl(RxENA | inl(ioaddr + cr), ioaddr + cr); + + return retstat; + +} + + +/* Function: sis900_disable + * + * Description: Turns off interrupts and stops Tx and Rx engines + * + * Arguments: struct nic *nic: NIC data structure + * + * Returns: void. + */ + +static void +sis900_disable ( struct nic *nic ) { + + sis900_init(nic); + + /* Disable interrupts by clearing the interrupt mask. */ + outl(0, ioaddr + imr); + outl(0, ioaddr + ier); + + /* Stop the chip's Tx and Rx Status Machine */ + outl(RxDIS | TxDIS | inl(ioaddr + cr), ioaddr + cr); +} + + +/* Function: sis900_irq + * + * Description: Enable, Disable, or Force, interrupts + * + * Arguments: struct nic *nic: NIC data structure + * irq_action_t action: Requested action + * + * Returns: void. + */ + +static void +sis900_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + outl(0, ioaddr + imr); + break; + case ENABLE : + outl((RxSOVR|RxORN|RxERR|RxOK|TxURN|TxERR|TxIDLE), ioaddr + imr); + break; + case FORCE : + break; + } +} + +static struct nic_operations sis900_operations = { + .connect = dummy_connect, + .poll = sis900_poll, + .transmit = sis900_transmit, + .irq = sis900_irq, +}; + +static struct pci_device_id sis900_nics[] = { +PCI_ROM(0x1039, 0x0900, "sis900", "SIS900", 0), +PCI_ROM(0x1039, 0x7016, "sis7016", "SIS7016", 0), +}; + +PCI_DRIVER ( sis900_driver, sis900_nics, PCI_NO_CLASS ); + +DRIVER ( "SIS900", nic_driver, pci_driver, sis900_driver, + sis900_probe, sis900_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/sis900.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/sis900.h new file mode 100644 index 0000000..7a5c6b5 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/sis900.h @@ -0,0 +1,375 @@ +/* -*- Mode:C; c-basic-offset:4; -*- */ + +/* Definitions for SiS ethernet controllers including 7014/7016 and 900 + * References: + * SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support, + * preliminary Rev. 1.0 Jan. 14, 1998 + * SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support, + * preliminary Rev. 1.0 Nov. 10, 1998 + * SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution, + * preliminary Rev. 1.0 Jan. 18, 1998 + * http://www.sis.com.tw/support/databook.htm + */ + +FILE_LICENCE ( GPL_ANY ); + +/* MAC operationl registers of SiS 7016 and SiS 900 ethernet controller */ +/* The I/O extent, SiS 900 needs 256 bytes of io address */ +#define SIS900_TOTAL_SIZE 0x100 + +/* Symbolic offsets to registers. */ +enum sis900_registers { + cr=0x0, /* Command Register */ + cfg=0x4, /* Configuration Register */ + mear=0x8, /* EEPROM Access Register */ + ptscr=0xc, /* PCI Test Control Register */ + isr=0x10, /* Interrupt Status Register */ + imr=0x14, /* Interrupt Mask Register */ + ier=0x18, /* Interrupt Enable Register */ + epar=0x18, /* Enhanced PHY Access Register */ + txdp=0x20, /* Transmit Descriptor Pointer Register */ + txcfg=0x24, /* Transmit Configuration Register */ + rxdp=0x30, /* Receive Descriptor Pointer Register */ + rxcfg=0x34, /* Receive Configuration Register */ + flctrl=0x38, /* Flow Control Register */ + rxlen=0x3c, /* Receive Packet Length Register */ + rfcr=0x48, /* Receive Filter Control Register */ + rfdr=0x4C, /* Receive Filter Data Register */ + pmctrl=0xB0, /* Power Management Control Register */ + pmer=0xB4 /* Power Management Wake-up Event Register */ +}; + +/* Symbolic names for bits in various registers */ +enum sis900_command_register_bits { + RELOAD = 0x00000400, + ACCESSMODE = 0x00000200, + RESET = 0x00000100, + SWI = 0x00000080, + RxRESET = 0x00000020, + TxRESET = 0x00000010, + RxDIS = 0x00000008, + RxENA = 0x00000004, + TxDIS = 0x00000002, + TxENA = 0x00000001 +}; + +enum sis900_configuration_register_bits { + DESCRFMT = 0x00000100, /* 7016 specific */ + REQALG = 0x00000080, + SB = 0x00000040, + POW = 0x00000020, + EXD = 0x00000010, + PESEL = 0x00000008, + LPM = 0x00000004, + BEM = 0x00000001, + RND_CNT = 0x00000400, + FAIR_BACKOFF = 0x00000200, + EDB_MASTER_EN = 0x00002000 +}; + +enum sis900_eeprom_access_reigster_bits { + MDC = 0x00000040, + MDDIR = 0x00000020, + MDIO = 0x00000010, /* 7016 specific */ + EECS = 0x00000008, + EECLK = 0x00000004, + EEDO = 0x00000002, + EEDI = 0x00000001 +}; + +enum sis900_interrupt_register_bits { + WKEVT = 0x10000000, + TxPAUSEEND = 0x08000000, + TxPAUSE = 0x04000000, + TxRCMP = 0x02000000, + RxRCMP = 0x01000000, + DPERR = 0x00800000, + SSERR = 0x00400000, + RMABT = 0x00200000, + RTABT = 0x00100000, + RxSOVR = 0x00010000, + HIBERR = 0x00008000, + SWINT = 0x00001000, + MIBINT = 0x00000800, + TxURN = 0x00000400, + TxIDLE = 0x00000200, + TxERR = 0x00000100, + TxDESC = 0x00000080, + TxOK = 0x00000040, + RxORN = 0x00000020, + RxIDLE = 0x00000010, + RxEARLY = 0x00000008, + RxERR = 0x00000004, + RxDESC = 0x00000002, + RxOK = 0x00000001 +}; + +enum sis900_interrupt_enable_reigster_bits { + IE = 0x00000001 +}; + +/* maximum dma burst fro transmission and receive*/ +#define MAX_DMA_RANGE 7 /* actually 0 means MAXIMUM !! */ +#define TxMXDMA_shift 20 +#define RxMXDMA_shift 20 +#define TX_DMA_BURST 0 +#define RX_DMA_BURST 0 + +enum sis900_tx_rx_dma{ + DMA_BURST_512 = 0, DMA_BURST_64 = 5 +}; + +/* transmit FIFO threshholds */ +#define TX_FILL_THRESH 16 /* 1/4 FIFO size */ +#define TxFILLT_shift 8 +#define TxDRNT_shift 0 +#define TxDRNT_100 48 /* 3/4 FIFO size */ +#define TxDRNT_10 16 /* 1/2 FIFO size */ + +enum sis900_transmit_config_register_bits { + TxCSI = 0x80000000, + TxHBI = 0x40000000, + TxMLB = 0x20000000, + TxATP = 0x10000000, + TxIFG = 0x0C000000, + TxFILLT = 0x00003F00, + TxDRNT = 0x0000003F +}; + +/* recevie FIFO thresholds */ +#define RxDRNT_shift 1 +#define RxDRNT_100 16 /* 1/2 FIFO size */ +#define RxDRNT_10 24 /* 3/4 FIFO size */ + +enum sis900_reveive_config_register_bits { + RxAEP = 0x80000000, + RxARP = 0x40000000, + RxATX = 0x10000000, + RxAJAB = 0x08000000, + RxDRNT = 0x0000007F +}; + +#define RFAA_shift 28 +#define RFADDR_shift 16 + +enum sis900_receive_filter_control_register_bits { + RFEN = 0x80000000, + RFAAB = 0x40000000, + RFAAM = 0x20000000, + RFAAP = 0x10000000, + RFPromiscuous = (RFAAB|RFAAM|RFAAP) +}; + +enum sis900_reveive_filter_data_mask { + RFDAT = 0x0000FFFF +}; + +/* EEPROM Addresses */ +enum sis900_eeprom_address { + EEPROMSignature = 0x00, + EEPROMVendorID = 0x02, + EEPROMDeviceID = 0x03, + EEPROMMACAddr = 0x08, + EEPROMChecksum = 0x0b +}; + +/* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */ +enum sis900_eeprom_command { + EEread = 0x0180, + EEwrite = 0x0140, + EEerase = 0x01C0, + EEwriteEnable = 0x0130, + EEwriteDisable = 0x0100, + EEeraseAll = 0x0120, + EEwriteAll = 0x0110, + EEaddrMask = 0x013F, + EEcmdShift = 16 +}; +/* For SiS962 or SiS963, request the eeprom software access */ +enum sis96x_eeprom_command { + EEREQ = 0x00000400, EEDONE = 0x00000200, EEGNT = 0x00000100 +}; + +/* Manamgement Data I/O (mdio) frame */ +#define MIIread 0x6000 +#define MIIwrite 0x5002 +#define MIIpmdShift 7 +#define MIIregShift 2 +#define MIIcmdLen 16 +#define MIIcmdShift 16 + +/* Buffer Descriptor Status*/ +enum sis900_buffer_status { + OWN = 0x80000000, + MORE = 0x40000000, + INTR = 0x20000000, + SUPCRC = 0x10000000, + INCCRC = 0x10000000, + OK = 0x08000000, + DSIZE = 0x00000FFF +}; + +/* Status for TX Buffers */ +enum sis900_tx_buffer_status { + ABORT = 0x04000000, + UNDERRUN = 0x02000000, + NOCARRIER = 0x01000000, + DEFERD = 0x00800000, + EXCDEFER = 0x00400000, + OWCOLL = 0x00200000, + EXCCOLL = 0x00100000, + COLCNT = 0x000F0000 +}; + +enum sis900_rx_bufer_status { + OVERRUN = 0x02000000, + DEST = 0x00800000, + BCAST = 0x01800000, + MCAST = 0x01000000, + UNIMATCH = 0x00800000, + TOOLONG = 0x00400000, + RUNT = 0x00200000, + RXISERR = 0x00100000, + CRCERR = 0x00080000, + FAERR = 0x00040000, + LOOPBK = 0x00020000, + RXCOL = 0x00010000 +}; + +/* MII register offsets */ +enum mii_registers { + MII_CONTROL = 0x0000, + MII_STATUS = 0x0001, + MII_PHY_ID0 = 0x0002, + MII_PHY_ID1 = 0x0003, + MII_ANADV = 0x0004, + MII_ANLPAR = 0x0005, + MII_ANEXT = 0x0006 +}; + +/* mii registers specific to SiS 900 */ +enum sis_mii_registers { + MII_CONFIG1 = 0x0010, + MII_CONFIG2 = 0x0011, + MII_STSOUT = 0x0012, + MII_MASK = 0x0013, + MII_RESV = 0x0014 +}; + +/* mii registers specific to AMD 79C901 */ +enum amd_mii_registers { + MII_STATUS_SUMMARY = 0x0018 +}; + +/* mii registers specific to ICS 1893 */ +enum ics_mii_registers { + MII_EXTCTRL = 0x0010, MII_QPDSTS = 0x0011, MII_10BTOP = 0x0012, + MII_EXTCTRL2 = 0x0013 +}; + + + +/* MII Control register bit definitions. */ +enum mii_control_register_bits { + MII_CNTL_FDX = 0x0100, + MII_CNTL_RST_AUTO = 0x0200, + MII_CNTL_ISOLATE = 0x0400, + MII_CNTL_PWRDWN = 0x0800, + MII_CNTL_AUTO = 0x1000, + MII_CNTL_SPEED = 0x2000, + MII_CNTL_LPBK = 0x4000, + MII_CNTL_RESET = 0x8000 +}; + +/* MII Status register bit */ +enum mii_status_register_bits { + MII_STAT_EXT = 0x0001, + MII_STAT_JAB = 0x0002, + MII_STAT_LINK = 0x0004, + MII_STAT_CAN_AUTO = 0x0008, + MII_STAT_FAULT = 0x0010, + MII_STAT_AUTO_DONE = 0x0020, + MII_STAT_CAN_T = 0x0800, + MII_STAT_CAN_T_FDX = 0x1000, + MII_STAT_CAN_TX = 0x2000, + MII_STAT_CAN_TX_FDX = 0x4000, + MII_STAT_CAN_T4 = 0x8000 +}; + +#define MII_ID1_OUI_LO 0xFC00 /* low bits of OUI mask */ +#define MII_ID1_MODEL 0x03F0 /* model number */ +#define MII_ID1_REV 0x000F /* model number */ + +/* MII NWAY Register Bits ... + valid for the ANAR (Auto-Negotiation Advertisement) and + ANLPAR (Auto-Negotiation Link Partner) registers */ +enum mii_nway_register_bits { + MII_NWAY_NODE_SEL = 0x001f, + MII_NWAY_CSMA_CD = 0x0001, + MII_NWAY_T = 0x0020, + MII_NWAY_T_FDX = 0x0040, + MII_NWAY_TX = 0x0080, + MII_NWAY_TX_FDX = 0x0100, + MII_NWAY_T4 = 0x0200, + MII_NWAY_PAUSE = 0x0400, + MII_NWAY_RF = 0x2000, + MII_NWAY_ACK = 0x4000, + MII_NWAY_NP = 0x8000 +}; + +enum mii_stsout_register_bits { + MII_STSOUT_LINK_FAIL = 0x4000, + MII_STSOUT_SPD = 0x0080, + MII_STSOUT_DPLX = 0x0040 +}; + +enum mii_stsics_register_bits { + MII_STSICS_SPD = 0x8000, MII_STSICS_DPLX = 0x4000, + MII_STSICS_LINKSTS = 0x0001 +}; + +enum mii_stssum_register_bits { + MII_STSSUM_LINK = 0x0008, + MII_STSSUM_DPLX = 0x0004, + MII_STSSUM_AUTO = 0x0002, + MII_STSSUM_SPD = 0x0001 +}; + +enum sis900_revision_id { + SIS630A_900_REV = 0x80, SIS630E_900_REV = 0x81, + SIS630S_900_REV = 0x82, SIS630EA1_900_REV = 0x83, + SIS630ET_900_REV = 0x84, SIS635A_900_REV = 0x90, + SIS96x_900_REV = 0X91, SIS900B_900_REV = 0x03 +}; + +enum sis630_revision_id { + SIS630A0 = 0x00, SIS630A1 = 0x01, + SIS630B0 = 0x10, SIS630B1 = 0x11 +}; + +#define FDX_CAPABLE_DUPLEX_UNKNOWN 0 +#define FDX_CAPABLE_HALF_SELECTED 1 +#define FDX_CAPABLE_FULL_SELECTED 2 + +#define HW_SPEED_UNCONFIG 0 +#define HW_SPEED_HOME 1 +#define HW_SPEED_10_MBPS 10 +#define HW_SPEED_100_MBPS 100 +#define HW_SPEED_DEFAULT (HW_SPEED_100_MBPS) + +#define CRC_SIZE 4 +#define MAC_HEADER_SIZE 14 + +#define TX_BUF_SIZE 1536 +#define RX_BUF_SIZE 1536 + +#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */ + +/* Time in ticks before concluding the transmitter is hung. */ +#define TX_TIMEOUT (4*TICKS_PER_SEC) + +typedef struct _BufferDesc { + u32 link; + volatile u32 cmdsts; + u32 bufptr; +} BufferDesc; diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/smc9000.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/smc9000.c new file mode 100644 index 0000000..cfbf104 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/smc9000.c @@ -0,0 +1,955 @@ +#ifdef ALLMULTI +#error multicast support is not yet implemented +#endif + /*------------------------------------------------------------------------ + * smc9000.c + * This is a Etherboot driver for SMC's 9000 series of Ethernet cards. + * + * Copyright (C) 1998 Daniel Engström <daniel.engstrom@riksnett.no> + * Based on the Linux SMC9000 driver, smc9194.c by Eric Stahlman + * Copyright (C) 1996 by Erik Stahlman <eric@vt.edu> + * + * This software may be used and distributed according to the terms + * of the GNU Public License, incorporated herein by reference. + * + * "Features" of the SMC chip: + * 4608 byte packet memory. ( for the 91C92/4. Others have more ) + * EEPROM for configuration + * AUI/TP selection + * + * Authors + * Erik Stahlman <erik@vt.edu> + * Daniel Engström <daniel.engstrom@riksnett.no> + * + * History + * 98-09-25 Daniel Engström Etherboot driver crated from Eric's + * Linux driver. + * + *---------------------------------------------------------------------------*/ + +FILE_LICENCE ( GPL_ANY ); + +#define LINUX_OUT_MACROS 1 +#define SMC9000_DEBUG 0 + +#if SMC9000_DEBUG > 1 +#define PRINTK2 printf +#else +#define PRINTK2(args...) +#endif + +#include <gpxe/ethernet.h> +#include <errno.h> +#include "etherboot.h" +#include "nic.h" +#include <gpxe/isa.h> +#include "smc9000.h" + +# define _outb outb +# define _outw outw + +static const char smc9000_version[] = "Version 0.99 98-09-30"; +static const char *interfaces[ 2 ] = { "TP", "AUI" }; +static const char *chip_ids[ 15 ] = { + NULL, NULL, NULL, + /* 3 */ "SMC91C90/91C92", + /* 4 */ "SMC91C94", + /* 5 */ "SMC91C95", + NULL, + /* 7 */ "SMC91C100", + /* 8 */ "SMC91C100FD", + /* 9 */ "SMC91C11xFD", + NULL, NULL, + NULL, NULL, NULL +}; +static const char smc91c96_id[] = "SMC91C96"; + +/*------------------------------------------------------------ + . Reads a register from the MII Management serial interface + .-------------------------------------------------------------*/ +static word smc_read_phy_register(int ioaddr, byte phyaddr, byte phyreg) +{ + int oldBank; + unsigned int i; + byte mask; + word mii_reg; + byte bits[64]; + int clk_idx = 0; + int input_idx; + word phydata; + + // 32 consecutive ones on MDO to establish sync + for (i = 0; i < 32; ++i) + bits[clk_idx++] = MII_MDOE | MII_MDO; + + // Start code <01> + bits[clk_idx++] = MII_MDOE; + bits[clk_idx++] = MII_MDOE | MII_MDO; + + // Read command <10> + bits[clk_idx++] = MII_MDOE | MII_MDO; + bits[clk_idx++] = MII_MDOE; + + // Output the PHY address, msb first + mask = (byte)0x10; + for (i = 0; i < 5; ++i) + { + if (phyaddr & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + // Shift to next lowest bit + mask >>= 1; + } + + // Output the phy register number, msb first + mask = (byte)0x10; + for (i = 0; i < 5; ++i) + { + if (phyreg & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + // Shift to next lowest bit + mask >>= 1; + } + + // Tristate and turnaround (2 bit times) + bits[clk_idx++] = 0; + //bits[clk_idx++] = 0; + + // Input starts at this bit time + input_idx = clk_idx; + + // Will input 16 bits + for (i = 0; i < 16; ++i) + bits[clk_idx++] = 0; + + // Final clock bit + bits[clk_idx++] = 0; + + // Save the current bank + oldBank = inw( ioaddr+BANK_SELECT ); + + // Select bank 3 + SMC_SELECT_BANK(ioaddr, 3); + + // Get the current MII register value + mii_reg = inw( ioaddr+MII_REG ); + + // Turn off all MII Interface bits + mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO); + + // Clock all 64 cycles + for (i = 0; i < sizeof(bits); ++i) + { + // Clock Low - output data + outw( mii_reg | bits[i], ioaddr+MII_REG ); + udelay(50); + + + // Clock Hi - input data + outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG ); + udelay(50); + bits[i] |= inw( ioaddr+MII_REG ) & MII_MDI; + } + + // Return to idle state + // Set clock to low, data to low, and output tristated + outw( mii_reg, ioaddr+MII_REG ); + udelay(50); + + // Restore original bank select + SMC_SELECT_BANK(ioaddr, oldBank); + + // Recover input data + phydata = 0; + for (i = 0; i < 16; ++i) + { + phydata <<= 1; + + if (bits[input_idx++] & MII_MDI) + phydata |= 0x0001; + } + +#if (SMC_DEBUG > 2 ) + printf("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", + phyaddr, phyreg, phydata); +#endif + + return(phydata); +} + + +/*------------------------------------------------------------ + . Writes a register to the MII Management serial interface + .-------------------------------------------------------------*/ +static void smc_write_phy_register(int ioaddr, + byte phyaddr, byte phyreg, word phydata) +{ + int oldBank; + unsigned int i; + word mask; + word mii_reg; + byte bits[65]; + int clk_idx = 0; + + // 32 consecutive ones on MDO to establish sync + for (i = 0; i < 32; ++i) + bits[clk_idx++] = MII_MDOE | MII_MDO; + + // Start code <01> + bits[clk_idx++] = MII_MDOE; + bits[clk_idx++] = MII_MDOE | MII_MDO; + + // Write command <01> + bits[clk_idx++] = MII_MDOE; + bits[clk_idx++] = MII_MDOE | MII_MDO; + + // Output the PHY address, msb first + mask = (byte)0x10; + for (i = 0; i < 5; ++i) + { + if (phyaddr & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + // Shift to next lowest bit + mask >>= 1; + } + + // Output the phy register number, msb first + mask = (byte)0x10; + for (i = 0; i < 5; ++i) + { + if (phyreg & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + // Shift to next lowest bit + mask >>= 1; + } + + // Tristate and turnaround (2 bit times) + bits[clk_idx++] = 0; + bits[clk_idx++] = 0; + + // Write out 16 bits of data, msb first + mask = 0x8000; + for (i = 0; i < 16; ++i) + { + if (phydata & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + // Shift to next lowest bit + mask >>= 1; + } + + // Final clock bit (tristate) + bits[clk_idx++] = 0; + + // Save the current bank + oldBank = inw( ioaddr+BANK_SELECT ); + + // Select bank 3 + SMC_SELECT_BANK(ioaddr, 3); + + // Get the current MII register value + mii_reg = inw( ioaddr+MII_REG ); + + // Turn off all MII Interface bits + mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO); + + // Clock all cycles + for (i = 0; i < sizeof(bits); ++i) + { + // Clock Low - output data + outw( mii_reg | bits[i], ioaddr+MII_REG ); + udelay(50); + + + // Clock Hi - input data + outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG ); + udelay(50); + bits[i] |= inw( ioaddr+MII_REG ) & MII_MDI; + } + + // Return to idle state + // Set clock to low, data to low, and output tristated + outw( mii_reg, ioaddr+MII_REG ); + udelay(50); + + // Restore original bank select + SMC_SELECT_BANK(ioaddr, oldBank); + +#if (SMC_DEBUG > 2 ) + printf("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", + phyaddr, phyreg, phydata); +#endif +} + + +/*------------------------------------------------------------ + . Finds and reports the PHY address + .-------------------------------------------------------------*/ +static int smc_detect_phy(int ioaddr, byte *pphyaddr) +{ + word phy_id1; + word phy_id2; + int phyaddr; + int found = 0; + + // Scan all 32 PHY addresses if necessary + for (phyaddr = 0; phyaddr < 32; ++phyaddr) + { + // Read the PHY identifiers + phy_id1 = smc_read_phy_register(ioaddr, phyaddr, PHY_ID1_REG); + phy_id2 = smc_read_phy_register(ioaddr, phyaddr, PHY_ID2_REG); + + // Make sure it is a valid identifier + if ((phy_id2 > 0x0000) && (phy_id2 < 0xffff) && + (phy_id1 > 0x0000) && (phy_id1 < 0xffff)) + { + if ((phy_id1 != 0x8000) && (phy_id2 != 0x8000)) + { + // Save the PHY's address + *pphyaddr = phyaddr; + found = 1; + break; + } + } + } + + if (!found) + { + printf("No PHY found\n"); + return(0); + } + + // Set the PHY type + if ( (phy_id1 == 0x0016) && ((phy_id2 & 0xFFF0) == 0xF840 ) ) + { + printf("PHY=LAN83C183 (LAN91C111 Internal)\n"); + } + + if ( (phy_id1 == 0x0282) && ((phy_id2 & 0xFFF0) == 0x1C50) ) + { + printf("PHY=LAN83C180\n"); + } + + return(1); +} + +/*------------------------------------------------------------ + . Configures the specified PHY using Autonegotiation. Calls + . smc_phy_fixed() if the user has requested a certain config. + .-------------------------------------------------------------*/ +static void smc_phy_configure(int ioaddr) +{ + int timeout; + byte phyaddr; + word my_phy_caps; // My PHY capabilities + word my_ad_caps; // My Advertised capabilities + word status; + int failed = 0; + int rpc_cur_mode = RPC_DEFAULT; + int lastPhy18; + + // Find the address and type of our phy + if (!smc_detect_phy(ioaddr, &phyaddr)) + { + return; + } + + // Reset the PHY, setting all other bits to zero + smc_write_phy_register(ioaddr, phyaddr, PHY_CNTL_REG, PHY_CNTL_RST); + + // Wait for the reset to complete, or time out + timeout = 6; // Wait up to 3 seconds + while (timeout--) + { + if (!(smc_read_phy_register(ioaddr, phyaddr, PHY_CNTL_REG) + & PHY_CNTL_RST)) + { + // reset complete + break; + } + + mdelay(500); // wait 500 millisecs + } + + if (timeout < 1) + { + PRINTK2("PHY reset timed out\n"); + return; + } + + // Read PHY Register 18, Status Output + lastPhy18 = smc_read_phy_register(ioaddr, phyaddr, PHY_INT_REG); + + // Enable PHY Interrupts (for register 18) + // Interrupts listed here are disabled + smc_write_phy_register(ioaddr, phyaddr, PHY_MASK_REG, + PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD | + PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB | + PHY_INT_SPDDET | PHY_INT_DPLXDET); + + /* Configure the Receive/Phy Control register */ + SMC_SELECT_BANK(ioaddr, 0); + outw( rpc_cur_mode, ioaddr + RPC_REG ); + + // Copy our capabilities from PHY_STAT_REG to PHY_AD_REG + my_phy_caps = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG); + my_ad_caps = PHY_AD_CSMA; // I am CSMA capable + + if (my_phy_caps & PHY_STAT_CAP_T4) + my_ad_caps |= PHY_AD_T4; + + if (my_phy_caps & PHY_STAT_CAP_TXF) + my_ad_caps |= PHY_AD_TX_FDX; + + if (my_phy_caps & PHY_STAT_CAP_TXH) + my_ad_caps |= PHY_AD_TX_HDX; + + if (my_phy_caps & PHY_STAT_CAP_TF) + my_ad_caps |= PHY_AD_10_FDX; + + if (my_phy_caps & PHY_STAT_CAP_TH) + my_ad_caps |= PHY_AD_10_HDX; + + // Update our Auto-Neg Advertisement Register + smc_write_phy_register(ioaddr, phyaddr, PHY_AD_REG, my_ad_caps); + + PRINTK2("phy caps=%x\n", my_phy_caps); + PRINTK2("phy advertised caps=%x\n", my_ad_caps); + + // Restart auto-negotiation process in order to advertise my caps + smc_write_phy_register( ioaddr, phyaddr, PHY_CNTL_REG, + PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST ); + + // Wait for the auto-negotiation to complete. This may take from + // 2 to 3 seconds. + // Wait for the reset to complete, or time out + timeout = 20; // Wait up to 10 seconds + while (timeout--) + { + status = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG); + if (status & PHY_STAT_ANEG_ACK) + { + // auto-negotiate complete + break; + } + + mdelay(500); // wait 500 millisecs + + // Restart auto-negotiation if remote fault + if (status & PHY_STAT_REM_FLT) + { + PRINTK2("PHY remote fault detected\n"); + + // Restart auto-negotiation + PRINTK2("PHY restarting auto-negotiation\n"); + smc_write_phy_register( ioaddr, phyaddr, PHY_CNTL_REG, + PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST | + PHY_CNTL_SPEED | PHY_CNTL_DPLX); + } + } + + if (timeout < 1) + { + PRINTK2("PHY auto-negotiate timed out\n"); + failed = 1; + } + + // Fail if we detected an auto-negotiate remote fault + if (status & PHY_STAT_REM_FLT) + { + PRINTK2("PHY remote fault detected\n"); + failed = 1; + } + + // Set our sysctl parameters to match auto-negotiation results + if ( lastPhy18 & PHY_INT_SPDDET ) + { + PRINTK2("PHY 100BaseT\n"); + rpc_cur_mode |= RPC_SPEED; + } + else + { + PRINTK2("PHY 10BaseT\n"); + rpc_cur_mode &= ~RPC_SPEED; + } + + if ( lastPhy18 & PHY_INT_DPLXDET ) + { + PRINTK2("PHY Full Duplex\n"); + rpc_cur_mode |= RPC_DPLX; + } + else + { + PRINTK2("PHY Half Duplex\n"); + rpc_cur_mode &= ~RPC_DPLX; + } + + // Re-Configure the Receive/Phy Control register + outw( rpc_cur_mode, ioaddr + RPC_REG ); +} + +/* + * Function: smc_reset( int ioaddr ) + * Purpose: + * This sets the SMC91xx chip to its normal state, hopefully from whatever + * mess that any other DOS driver has put it in. + * + * Maybe I should reset more registers to defaults in here? SOFTRESET should + * do that for me. + * + * Method: + * 1. send a SOFT RESET + * 2. wait for it to finish + * 3. reset the memory management unit + * 4. clear all interrupts + * +*/ +static void smc_reset(int ioaddr) +{ + /* This resets the registers mostly to defaults, but doesn't + * affect EEPROM. That seems unnecessary */ + SMC_SELECT_BANK(ioaddr, 0); + _outw( RCR_SOFTRESET, ioaddr + RCR ); + + /* this should pause enough for the chip to be happy */ + SMC_DELAY(ioaddr); + + /* Set the transmit and receive configuration registers to + * default values */ + _outw(RCR_CLEAR, ioaddr + RCR); + _outw(TCR_CLEAR, ioaddr + TCR); + + /* Reset the MMU */ + SMC_SELECT_BANK(ioaddr, 2); + _outw( MC_RESET, ioaddr + MMU_CMD ); + + /* Note: It doesn't seem that waiting for the MMU busy is needed here, + * but this is a place where future chipsets _COULD_ break. Be wary + * of issuing another MMU command right after this */ + _outb(0, ioaddr + INT_MASK); +} + + +/*---------------------------------------------------------------------- + * Function: smc9000_probe_addr( int ioaddr ) + * + * Purpose: + * Tests to see if a given ioaddr points to an SMC9xxx chip. + * Returns a 1 on success + * + * Algorithm: + * (1) see if the high byte of BANK_SELECT is 0x33 + * (2) compare the ioaddr with the base register's address + * (3) see if I recognize the chip ID in the appropriate register + * + * --------------------------------------------------------------------- + */ +static int smc9000_probe_addr( isa_probe_addr_t ioaddr ) +{ + word bank; + word revision_register; + word base_address_register; + + /* First, see if the high byte is 0x33 */ + bank = inw(ioaddr + BANK_SELECT); + if ((bank & 0xFF00) != 0x3300) { + return 0; + } + /* The above MIGHT indicate a device, but I need to write to further + * test this. */ + _outw(0x0, ioaddr + BANK_SELECT); + bank = inw(ioaddr + BANK_SELECT); + if ((bank & 0xFF00) != 0x3300) { + return 0; + } + + /* well, we've already written once, so hopefully another time won't + * hurt. This time, I need to switch the bank register to bank 1, + * so I can access the base address register */ + SMC_SELECT_BANK(ioaddr, 1); + base_address_register = inw(ioaddr + BASE); + + if (ioaddr != (base_address_register >> 3 & 0x3E0)) { + DBG("SMC9000: IOADDR %hX doesn't match configuration (%hX)." + "Probably not a SMC chip\n", + ioaddr, base_address_register >> 3 & 0x3E0); + /* well, the base address register didn't match. Must not have + * been a SMC chip after all. */ + return 0; + } + + + /* check if the revision register is something that I recognize. + * These might need to be added to later, as future revisions + * could be added. */ + SMC_SELECT_BANK(ioaddr, 3); + revision_register = inw(ioaddr + REVISION); + if (!chip_ids[(revision_register >> 4) & 0xF]) { + /* I don't recognize this chip, so... */ + DBG( "SMC9000: IO %hX: Unrecognized revision register:" + " %hX, Contact author.\n", ioaddr, revision_register ); + return 0; + } + + /* at this point I'll assume that the chip is an SMC9xxx. + * It might be prudent to check a listing of MAC addresses + * against the hardware address, or do some other tests. */ + return 1; +} + + +/************************************************************************** + * ETH_TRANSMIT - Transmit a frame + ***************************************************************************/ +static void smc9000_transmit( + struct nic *nic, + const char *d, /* Destination */ + unsigned int t, /* Type */ + unsigned int s, /* size */ + const char *p) /* Packet */ +{ + word length; /* real, length incl. header */ + word numPages; + unsigned long time_out; + byte packet_no; + word status; + int i; + + /* We dont pad here since we can have the hardware doing it for us */ + length = (s + ETH_HLEN + 1)&~1; + + /* convert to MMU pages */ + numPages = length / 256; + + if (numPages > 7 ) { + DBG("SMC9000: Far too big packet error. \n"); + return; + } + + /* dont try more than, say 30 times */ + for (i=0;i<30;i++) { + /* now, try to allocate the memory */ + SMC_SELECT_BANK(nic->ioaddr, 2); + _outw(MC_ALLOC | numPages, nic->ioaddr + MMU_CMD); + + status = 0; + /* wait for the memory allocation to finnish */ + for (time_out = currticks() + 5*TICKS_PER_SEC; currticks() < time_out; ) { + status = inb(nic->ioaddr + INTERRUPT); + if ( status & IM_ALLOC_INT ) { + /* acknowledge the interrupt */ + _outb(IM_ALLOC_INT, nic->ioaddr + INTERRUPT); + break; + } + } + + if ((status & IM_ALLOC_INT) != 0 ) { + /* We've got the memory */ + break; + } else { + printf("SMC9000: Memory allocation timed out, resetting MMU.\n"); + _outw(MC_RESET, nic->ioaddr + MMU_CMD); + } + } + + /* If I get here, I _know_ there is a packet slot waiting for me */ + packet_no = inb(nic->ioaddr + PNR_ARR + 1); + if (packet_no & 0x80) { + /* or isn't there? BAD CHIP! */ + printf("SMC9000: Memory allocation failed. \n"); + return; + } + + /* we have a packet address, so tell the card to use it */ + _outb(packet_no, nic->ioaddr + PNR_ARR); + + /* point to the beginning of the packet */ + _outw(PTR_AUTOINC, nic->ioaddr + POINTER); + +#if SMC9000_DEBUG > 2 + printf("Trying to xmit packet of length %hX\n", length ); +#endif + + /* send the packet length ( +6 for status, length and ctl byte ) + * and the status word ( set to zeros ) */ + _outw(0, nic->ioaddr + DATA_1 ); + + /* send the packet length ( +6 for status words, length, and ctl) */ + _outb((length+6) & 0xFF, nic->ioaddr + DATA_1); + _outb((length+6) >> 8 , nic->ioaddr + DATA_1); + + /* Write the contents of the packet */ + + /* The ethernet header first... */ + outsw(nic->ioaddr + DATA_1, d, ETH_ALEN >> 1); + outsw(nic->ioaddr + DATA_1, nic->node_addr, ETH_ALEN >> 1); + _outw(htons(t), nic->ioaddr + DATA_1); + + /* ... the data ... */ + outsw(nic->ioaddr + DATA_1 , p, s >> 1); + + /* ... and the last byte, if there is one. */ + if ((s & 1) == 0) { + _outw(0, nic->ioaddr + DATA_1); + } else { + _outb(p[s-1], nic->ioaddr + DATA_1); + _outb(0x20, nic->ioaddr + DATA_1); + } + + /* and let the chipset deal with it */ + _outw(MC_ENQUEUE , nic->ioaddr + MMU_CMD); + + status = 0; time_out = currticks() + 5*TICKS_PER_SEC; + do { + status = inb(nic->ioaddr + INTERRUPT); + + if ((status & IM_TX_INT ) != 0) { + word tx_status; + + /* ack interrupt */ + _outb(IM_TX_INT, nic->ioaddr + INTERRUPT); + + packet_no = inw(nic->ioaddr + FIFO_PORTS); + packet_no &= 0x7F; + + /* select this as the packet to read from */ + _outb( packet_no, nic->ioaddr + PNR_ARR ); + + /* read the first word from this packet */ + _outw( PTR_AUTOINC | PTR_READ, nic->ioaddr + POINTER ); + + tx_status = inw( nic->ioaddr + DATA_1 ); + + if (0 == (tx_status & TS_SUCCESS)) { + DBG("SMC9000: TX FAIL STATUS: %hX \n", tx_status); + /* re-enable transmit */ + SMC_SELECT_BANK(nic->ioaddr, 0); + _outw(inw(nic->ioaddr + TCR ) | TCR_ENABLE, nic->ioaddr + TCR ); + } + + /* kill the packet */ + SMC_SELECT_BANK(nic->ioaddr, 2); + _outw(MC_FREEPKT, nic->ioaddr + MMU_CMD); + + return; + } + }while(currticks() < time_out); + + printf("SMC9000: TX timed out, resetting board\n"); + smc_reset(nic->ioaddr); + return; +} + +/************************************************************************** + * ETH_POLL - Wait for a frame + ***************************************************************************/ +static int smc9000_poll(struct nic *nic, int retrieve) +{ + SMC_SELECT_BANK(nic->ioaddr, 2); + if (inw(nic->ioaddr + FIFO_PORTS) & FP_RXEMPTY) + return 0; + + if ( ! retrieve ) return 1; + + /* start reading from the start of the packet */ + _outw(PTR_READ | PTR_RCV | PTR_AUTOINC, nic->ioaddr + POINTER); + + /* First read the status and check that we're ok */ + if (!(inw(nic->ioaddr + DATA_1) & RS_ERRORS)) { + /* Next: read the packet length and mask off the top bits */ + nic->packetlen = (inw(nic->ioaddr + DATA_1) & 0x07ff); + + /* the packet length includes the 3 extra words */ + nic->packetlen -= 6; +#if SMC9000_DEBUG > 2 + printf(" Reading %d words (and %d byte(s))\n", + (nic->packetlen >> 1), nic->packetlen & 1); +#endif + /* read the packet (and the last "extra" word) */ + insw(nic->ioaddr + DATA_1, nic->packet, (nic->packetlen+2) >> 1); + /* is there an odd last byte ? */ + if (nic->packet[nic->packetlen+1] & 0x20) + nic->packetlen++; + + /* error or good, tell the card to get rid of this packet */ + _outw(MC_RELEASE, nic->ioaddr + MMU_CMD); + return 1; + } + + printf("SMC9000: RX error\n"); + /* error or good, tell the card to get rid of this packet */ + _outw(MC_RELEASE, nic->ioaddr + MMU_CMD); + return 0; +} + +static void smc9000_disable ( struct nic *nic, struct isa_device *isa __unused ) { + + smc_reset(nic->ioaddr); + + /* no more interrupts for me */ + SMC_SELECT_BANK(nic->ioaddr, 2); + _outb( 0, nic->ioaddr + INT_MASK); + + /* and tell the card to stay away from that nasty outside world */ + SMC_SELECT_BANK(nic->ioaddr, 0); + _outb( RCR_CLEAR, nic->ioaddr + RCR ); + _outb( TCR_CLEAR, nic->ioaddr + TCR ); +} + +static void smc9000_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + +static struct nic_operations smc9000_operations = { + .connect = dummy_connect, + .poll = smc9000_poll, + .transmit = smc9000_transmit, + .irq = smc9000_irq, + +}; + +/************************************************************************** + * ETH_PROBE - Look for an adapter + ***************************************************************************/ + +static int smc9000_probe ( struct nic *nic, struct isa_device *isa ) { + + unsigned short revision; + int memory; + int media; + const char * version_string; + const char * if_string; + int i; + + nic->irqno = 0; + nic->ioaddr = isa->ioaddr; + + /* + * Get the MAC address ( bank 1, regs 4 - 9 ) + */ + SMC_SELECT_BANK(nic->ioaddr, 1); + for ( i = 0; i < 6; i += 2 ) { + word address; + + address = inw(nic->ioaddr + ADDR0 + i); + nic->node_addr[i+1] = address >> 8; + nic->node_addr[i] = address & 0xFF; + } + + /* get the memory information */ + SMC_SELECT_BANK(nic->ioaddr, 0); + memory = ( inw(nic->ioaddr + MCR) >> 9 ) & 0x7; /* multiplier */ + memory *= 256 * (inw(nic->ioaddr + MIR) & 0xFF); + + /* + * Now, I want to find out more about the chip. This is sort of + * redundant, but it's cleaner to have it in both, rather than having + * one VERY long probe procedure. + */ + SMC_SELECT_BANK(nic->ioaddr, 3); + revision = inw(nic->ioaddr + REVISION); + version_string = chip_ids[(revision >> 4) & 0xF]; + + if (((revision & 0xF0) >> 4 == CHIP_9196) && + ((revision & 0x0F) >= REV_9196)) { + /* This is a 91c96. 'c96 has the same chip id as 'c94 (4) but + * a revision starting at 6 */ + version_string = smc91c96_id; + } + + if ( !version_string ) { + /* I shouldn't get here because this call was done before.... */ + return 0; + } + + /* is it using AUI or 10BaseT ? */ + SMC_SELECT_BANK(nic->ioaddr, 1); + if (inw(nic->ioaddr + CONFIG) & CFG_AUI_SELECT) + media = 2; + else + media = 1; + + if_string = interfaces[media - 1]; + + /* now, reset the chip, and put it into a known state */ + smc_reset(nic->ioaddr); + + printf("SMC9000 %s\n", smc9000_version); + DBG("Copyright (C) 1998 Daniel Engstr\x94m\n"); + DBG("Copyright (C) 1996 Eric Stahlman\n"); + + printf("%s rev:%d I/O port:%hX Interface:%s RAM:%d bytes \n", + version_string, revision & 0xF, + nic->ioaddr, if_string, memory ); + + DBG ( "Ethernet MAC address: %s\n", eth_ntoa ( nic->node_addr ) ); + + SMC_SELECT_BANK(nic->ioaddr, 0); + + /* see the header file for options in TCR/RCR NORMAL*/ + _outw(TCR_NORMAL, nic->ioaddr + TCR); + _outw(RCR_NORMAL, nic->ioaddr + RCR); + + /* Select which interface to use */ + SMC_SELECT_BANK(nic->ioaddr, 1); + if ( media == 1 ) { + _outw( inw( nic->ioaddr + CONFIG ) & ~CFG_AUI_SELECT, + nic->ioaddr + CONFIG ); + } + else if ( media == 2 ) { + _outw( inw( nic->ioaddr + CONFIG ) | CFG_AUI_SELECT, + nic->ioaddr + CONFIG ); + } + + smc_phy_configure(nic->ioaddr); + + nic->nic_op = &smc9000_operations; + return 1; +} + +/* + * The SMC9000 can be at any of the following port addresses. To + * change for a slightly different card, you can add it to the array. + * + */ +static isa_probe_addr_t smc9000_probe_addrs[] = { + 0x200, 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x2E0, + 0x300, 0x320, 0x340, 0x360, 0x380, 0x3A0, 0x3C0, 0x3E0, +}; + +ISA_DRIVER ( smc9000_driver, smc9000_probe_addrs, smc9000_probe_addr, + GENERIC_ISAPNP_VENDOR, 0x8228 ); + +DRIVER ( "SMC9000", nic_driver, isa_driver, smc9000_driver, + smc9000_probe, smc9000_disable ); + +ISA_ROM ( "smc9000", "SMC9000" ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/smc9000.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/smc9000.h new file mode 100644 index 0000000..22b0e18 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/smc9000.h @@ -0,0 +1,428 @@ +/*------------------------------------------------------------------------ + * smc9000.h + * + * Copyright (C) 1998 by Daniel Engström + * Copyright (C) 1996 by Erik Stahlman + * + * This software may be used and distributed according to the terms + * of the GNU Public License, incorporated herein by reference. + * + * This file contains register information and access macros for + * the SMC91xxx chipset. + * + * Information contained in this file was obtained from the SMC91C94 + * manual from SMC. To get a copy, if you really want one, you can find + * information under www.smsc.com in the components division. + * ( this thanks to advice from Donald Becker ). + * + * Authors + * Daniel Engström <daniel.engstrom@riksnett.no> + * Erik Stahlman <erik@vt.edu> + * + * History + * 96-01-06 Erik Stahlman moved definitions here from main .c + * file + * 96-01-19 Erik Stahlman polished this up some, and added + * better error handling + * 98-09-25 Daniel Engström adjusted for Etherboot + * 98-09-27 Daniel Engström moved some static strings back to the + * main .c file + * --------------------------------------------------------------------------*/ + +FILE_LICENCE ( GPL_ANY ); + +#ifndef _SMC9000_H_ +# define _SMC9000_H_ + +/* I want some simple types */ +typedef unsigned char byte; +typedef unsigned short word; +typedef unsigned long int dword; + +/*--------------------------------------------------------------- + * + * A description of the SMC registers is probably in order here, + * although for details, the SMC datasheet is invaluable. + * + * Basically, the chip has 4 banks of registers ( 0 to 3 ), which + * are accessed by writing a number into the BANK_SELECT register + * ( I also use a SMC_SELECT_BANK macro for this ). + * + * The banks are configured so that for most purposes, bank 2 is all + * that is needed for simple run time tasks. + * ----------------------------------------------------------------------*/ + +/* + * Bank Select Register: + * + * yyyy yyyy 0000 00xx + * xx = bank number + * yyyy yyyy = 0x33, for identification purposes. + */ +#define BANK_SELECT 14 + +/* BANK 0 */ + +#define TCR 0 /* transmit control register */ +#define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */ +#define TCR_FDUPLX 0x0800 /* receive packets sent out */ +#define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */ +#define TCR_MON_CNS 0x0400 /* monitors the carrier status */ +#define TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */ + +#define TCR_CLEAR 0 /* do NOTHING */ +/* the normal settings for the TCR register : */ +#define TCR_NORMAL (TCR_ENABLE | TCR_PAD_ENABLE) + + +#define EPH_STATUS 2 +#define ES_LINK_OK 0x4000 /* is the link integrity ok ? */ + +#define RCR 4 +#define RCR_SOFTRESET 0x8000 /* resets the chip */ +#define RCR_STRIP_CRC 0x200 /* strips CRC */ +#define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */ +#define RCR_ALMUL 0x4 /* receive all multicast packets */ +#define RCR_PROMISC 0x2 /* enable promiscuous mode */ + +/* the normal settings for the RCR register : */ +#define RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE) +#define RCR_CLEAR 0x0 /* set it to a base state */ + +#define COUNTER 6 +#define MIR 8 +#define MCR 10 +/* 12 is reserved */ + +// Receive/Phy Control Register +/* BANK 0 */ +#define RPC_REG 0x000A +#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. +#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode +#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode +#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb +#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb +#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect +#define RPC_LED_RES (0x01) // LED = Reserved +#define RPC_LED_10 (0x02) // LED = 10Mbps link detect +#define RPC_LED_FD (0x03) // LED = Full Duplex Mode +#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred +#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect +#define RPC_LED_TX (0x06) // LED = TX packet occurred +#define RPC_LED_RX (0x07) // LED = RX packet occurred +#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) + +// Receive/Phy Control Register +/* BANK 0 */ +#define RPC_REG 0x000A +#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. +#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode +#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode +#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb +#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb +#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect +#define RPC_LED_RES (0x01) // LED = Reserved +#define RPC_LED_10 (0x02) // LED = 10Mbps link detect +#define RPC_LED_FD (0x03) // LED = Full Duplex Mode +#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred +#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect +#define RPC_LED_TX (0x06) // LED = TX packet occurred +#define RPC_LED_RX (0x07) // LED = RX packet occurred +#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) + +/* BANK 1 */ +#define CONFIG 0 +#define CFG_AUI_SELECT 0x100 +#define BASE 2 +#define ADDR0 4 +#define ADDR1 6 +#define ADDR2 8 +#define GENERAL 10 +#define CONTROL 12 +#define CTL_POWERDOWN 0x2000 +#define CTL_LE_ENABLE 0x80 +#define CTL_CR_ENABLE 0x40 +#define CTL_TE_ENABLE 0x0020 +#define CTL_AUTO_RELEASE 0x0800 +#define CTL_EPROM_ACCESS 0x0003 /* high if Eprom is being read */ + +/* BANK 2 */ +#define MMU_CMD 0 +#define MC_BUSY 1 /* only readable bit in the register */ +#define MC_NOP 0 +#define MC_ALLOC 0x20 /* or with number of 256 byte packets */ +#define MC_RESET 0x40 +#define MC_REMOVE 0x60 /* remove the current rx packet */ +#define MC_RELEASE 0x80 /* remove and release the current rx packet */ +#define MC_FREEPKT 0xA0 /* Release packet in PNR register */ +#define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */ + +#define PNR_ARR 2 +#define FIFO_PORTS 4 + +#define FP_RXEMPTY 0x8000 +#define FP_TXEMPTY 0x80 + +#define POINTER 6 +#define PTR_READ 0x2000 +#define PTR_RCV 0x8000 +#define PTR_AUTOINC 0x4000 +#define PTR_AUTO_INC 0x0040 + +#define DATA_1 8 +#define DATA_2 10 +#define INTERRUPT 12 + +#define INT_MASK 13 +#define IM_RCV_INT 0x1 +#define IM_TX_INT 0x2 +#define IM_TX_EMPTY_INT 0x4 +#define IM_ALLOC_INT 0x8 +#define IM_RX_OVRN_INT 0x10 +#define IM_EPH_INT 0x20 +#define IM_ERCV_INT 0x40 /* not on SMC9192 */ + +/* BANK 3 */ +#define MULTICAST1 0 +#define MULTICAST2 2 +#define MULTICAST3 4 +#define MULTICAST4 6 +#define MGMT 8 +#define REVISION 10 /* ( hi: chip id low: rev # ) */ + +// Management Interface Register (MII) +#define MII_REG 0x0008 +#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup +#define MII_MDOE 0x0008 // MII Output Enable +#define MII_MCLK 0x0004 // MII Clock, pin MDCLK +#define MII_MDI 0x0002 // MII Input, pin MDI +#define MII_MDO 0x0001 // MII Output, pin MDO + +/* this is NOT on SMC9192 */ +#define ERCV 12 + +/* Note that 9194 and 9196 have the smame chip id, + * the 9196 will have revisions starting at 6 */ +#define CHIP_9190 3 +#define CHIP_9194 4 +#define CHIP_9195 5 +#define CHIP_9196 4 +#define CHIP_91100 7 +#define CHIP_91100FD 8 + +#define REV_9196 6 + +/* + * Transmit status bits + */ +#define TS_SUCCESS 0x0001 +#define TS_LOSTCAR 0x0400 +#define TS_LATCOL 0x0200 +#define TS_16COL 0x0010 + +/* + * Receive status bits + */ +#define RS_ALGNERR 0x8000 +#define RS_BADCRC 0x2000 +#define RS_ODDFRAME 0x1000 +#define RS_TOOLONG 0x0800 +#define RS_TOOSHORT 0x0400 +#define RS_MULTICAST 0x0001 +#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) + +// PHY Register Addresses (LAN91C111 Internal PHY) + +// PHY Control Register +#define PHY_CNTL_REG 0x00 +#define PHY_CNTL_RST 0x8000 // 1=PHY Reset +#define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback +#define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs +#define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation +#define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode +#define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled +#define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate +#define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex +#define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test + +// PHY Status Register +#define PHY_STAT_REG 0x01 +#define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable +#define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable +#define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable +#define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable +#define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable +#define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble +#define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed +#define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected +#define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable +#define PHY_STAT_LINK 0x0004 // 1=valid link +#define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition +#define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented + +// PHY Identifier Registers +#define PHY_ID1_REG 0x02 // PHY Identifier 1 +#define PHY_ID2_REG 0x03 // PHY Identifier 2 + +// PHY Auto-Negotiation Advertisement Register +#define PHY_AD_REG 0x04 +#define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page +#define PHY_AD_ACK 0x4000 // 1=got link code word from remote +#define PHY_AD_RF 0x2000 // 1=advertise remote fault +#define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4 +#define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX +#define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX +#define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX +#define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX +#define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA + +// PHY Auto-negotiation Remote End Capability Register +#define PHY_RMT_REG 0x05 +// Uses same bit definitions as PHY_AD_REG + +// PHY Configuration Register 1 +#define PHY_CFG1_REG 0x10 +#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled +#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled +#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down +#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler +#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable +#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled +#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) +#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db +#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust +#define PHY_CFG1_TLVL_MASK 0x003C +#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time + + +// PHY Configuration Register 2 +#define PHY_CFG2_REG 0x11 +#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled +#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled +#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) +#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo + +// PHY Status Output (and Interrupt status) Register +#define PHY_INT_REG 0x12 // Status Output (Interrupt Status) +#define PHY_INT_INT 0x8000 // 1=bits have changed since last read +#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected +#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync +#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx +#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx +#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx +#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected +#define PHY_INT_JAB 0x0100 // 1=Jabber detected +#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode +#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex + +// PHY Interrupt/Status Mask Register +#define PHY_MASK_REG 0x13 // Interrupt Mask +// Uses the same bit definitions as PHY_INT_REG + + +// PHY Register Addresses (LAN91C111 Internal PHY) + +// PHY Control Register +#define PHY_CNTL_REG 0x00 +#define PHY_CNTL_RST 0x8000 // 1=PHY Reset +#define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback +#define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs +#define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation +#define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode +#define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled +#define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate +#define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex +#define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test + +// PHY Status Register +#define PHY_STAT_REG 0x01 +#define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable +#define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable +#define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable +#define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable +#define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable +#define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble +#define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed +#define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected +#define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable +#define PHY_STAT_LINK 0x0004 // 1=valid link +#define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition +#define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented + +// PHY Identifier Registers +#define PHY_ID1_REG 0x02 // PHY Identifier 1 +#define PHY_ID2_REG 0x03 // PHY Identifier 2 + +// PHY Auto-Negotiation Advertisement Register +#define PHY_AD_REG 0x04 +#define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page +#define PHY_AD_ACK 0x4000 // 1=got link code word from remote +#define PHY_AD_RF 0x2000 // 1=advertise remote fault +#define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4 +#define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX +#define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX +#define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX +#define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX +#define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA + +// PHY Auto-negotiation Remote End Capability Register +#define PHY_RMT_REG 0x05 +// Uses same bit definitions as PHY_AD_REG + +// PHY Configuration Register 1 +#define PHY_CFG1_REG 0x10 +#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled +#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled +#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down +#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler +#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable +#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled +#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) +#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db +#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust +#define PHY_CFG1_TLVL_MASK 0x003C +#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time + + +// PHY Configuration Register 2 +#define PHY_CFG2_REG 0x11 +#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled +#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled +#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) +#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo + +// PHY Status Output (and Interrupt status) Register +#define PHY_INT_REG 0x12 // Status Output (Interrupt Status) +#define PHY_INT_INT 0x8000 // 1=bits have changed since last read +#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected +#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync +#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx +#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx +#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx +#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected +#define PHY_INT_JAB 0x0100 // 1=Jabber detected +#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode +#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex + +// PHY Interrupt/Status Mask Register +#define PHY_MASK_REG 0x13 // Interrupt Mask +// Uses the same bit definitions as PHY_INT_REG + + +/*------------------------------------------------------------------------- + * I define some macros to make it easier to do somewhat common + * or slightly complicated, repeated tasks. + --------------------------------------------------------------------------*/ + +/* select a register bank, 0 to 3 */ + +#define SMC_SELECT_BANK(x, y) { _outw( y, x + BANK_SELECT ); } + +/* define a small delay for the reset */ +#define SMC_DELAY(x) { inw( x + RCR );\ + inw( x + RCR );\ + inw( x + RCR ); } + + +#endif /* _SMC_9000_H_ */ + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/sundance.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/sundance.c new file mode 100644 index 0000000..c446ac0 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/sundance.c @@ -0,0 +1,897 @@ +/************************************************************************** +* +* sundance.c -- Etherboot device driver for the Sundance ST201 "Alta". +* Written 2002-2002 by Timothy Legge <tlegge@rogers.com> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +* +* Portions of this code based on: +* sundance.c: A Linux device driver for the Sundance ST201 "Alta" +* Written 1999-2002 by Donald Becker +* +* tulip.c: Tulip and Clone Etherboot Driver +* By Marty Conner +* Copyright (C) 2001 Entity Cyber, Inc. +* +* Linux Driver Version LK1.09a, 10-Jul-2003 (2.4.25) +* +* REVISION HISTORY: +* ================ +* v1.1 01-01-2003 timlegge Initial implementation +* v1.7 04-10-2003 timlegge Transfers Linux Kernel (30 sec) +* v1.8 04-13-2003 timlegge Fix multiple transmission bug +* v1.9 08-19-2003 timlegge Support Multicast +* v1.10 01-17-2004 timlegge Initial driver output cleanup +* v1.11 03-21-2004 timlegge Remove unused variables +* v1.12 03-21-2004 timlegge Remove excess MII defines +* v1.13 03-24-2004 timlegge Update to Linux 2.4.25 driver +* +****************************************************************************/ + +FILE_LICENCE ( GPL2_OR_LATER ); + +/* to get some global routines like printf */ +#include "etherboot.h" +/* to get the interface to the body of the program */ +#include "nic.h" +/* to get the PCI support functions, if this is a PCI NIC */ +#include <gpxe/pci.h> +#include "mii.h" + +#define drv_version "v1.12" +#define drv_date "2004-03-21" + +#define HZ 100 + +/* Condensed operations for readability. */ +#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) +#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) + +/* Set the mtu */ +static int mtu = 1514; + +/* Maximum number of multicast addresses to filter (vs. rx-all-multicast). + The sundance uses a 64 element hash table based on the Ethernet CRC. */ +// static int multicast_filter_limit = 32; + +/* Set the copy breakpoint for the copy-only-tiny-frames scheme. + Setting to > 1518 effectively disables this feature. + This chip can receive into any byte alignment buffers, so word-oriented + archs do not need a copy-align of the IP header. */ +static int rx_copybreak = 0; +static int flowctrl = 1; + +/* Allow forcing the media type */ +/* media[] specifies the media type the NIC operates at. + autosense Autosensing active media. + 10mbps_hd 10Mbps half duplex. + 10mbps_fd 10Mbps full duplex. + 100mbps_hd 100Mbps half duplex. + 100mbps_fd 100Mbps full duplex. +*/ +static char media[] = "autosense"; + +/* Operational parameters that are set at compile time. */ + +/* As Etherboot uses a Polling driver we can keep the number of rings +to the minimum number required. In general that is 1 transmit and 4 receive receive rings. However some cards require that +there be a minimum of 2 rings */ +#define TX_RING_SIZE 2 +#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */ +#define RX_RING_SIZE 4 + + +/* Operational parameters that usually are not changed. */ +/* Time in jiffies before concluding the transmitter is hung. */ +#define TX_TIME_OUT (4*HZ) +#define PKT_BUF_SZ 1536 + +/* Offsets to the device registers. + Unlike software-only systems, device drivers interact with complex hardware. + It's not useful to define symbolic names for every register bit in the + device. The name can only partially document the semantics and make + the driver longer and more difficult to read. + In general, only the important configuration values or bits changed + multiple times should be defined symbolically. +*/ +enum alta_offsets { + DMACtrl = 0x00, + TxListPtr = 0x04, + TxDMABurstThresh = 0x08, + TxDMAUrgentThresh = 0x09, + TxDMAPollPeriod = 0x0a, + RxDMAStatus = 0x0c, + RxListPtr = 0x10, + DebugCtrl0 = 0x1a, + DebugCtrl1 = 0x1c, + RxDMABurstThresh = 0x14, + RxDMAUrgentThresh = 0x15, + RxDMAPollPeriod = 0x16, + LEDCtrl = 0x1a, + ASICCtrl = 0x30, + EEData = 0x34, + EECtrl = 0x36, + TxStartThresh = 0x3c, + RxEarlyThresh = 0x3e, + FlashAddr = 0x40, + FlashData = 0x44, + TxStatus = 0x46, + TxFrameId = 0x47, + DownCounter = 0x18, + IntrClear = 0x4a, + IntrEnable = 0x4c, + IntrStatus = 0x4e, + MACCtrl0 = 0x50, + MACCtrl1 = 0x52, + StationAddr = 0x54, + MaxFrameSize = 0x5A, + RxMode = 0x5c, + MIICtrl = 0x5e, + MulticastFilter0 = 0x60, + MulticastFilter1 = 0x64, + RxOctetsLow = 0x68, + RxOctetsHigh = 0x6a, + TxOctetsLow = 0x6c, + TxOctetsHigh = 0x6e, + TxFramesOK = 0x70, + RxFramesOK = 0x72, + StatsCarrierError = 0x74, + StatsLateColl = 0x75, + StatsMultiColl = 0x76, + StatsOneColl = 0x77, + StatsTxDefer = 0x78, + RxMissed = 0x79, + StatsTxXSDefer = 0x7a, + StatsTxAbort = 0x7b, + StatsBcastTx = 0x7c, + StatsBcastRx = 0x7d, + StatsMcastTx = 0x7e, + StatsMcastRx = 0x7f, + /* Aliased and bogus values! */ + RxStatus = 0x0c, +}; +enum ASICCtrl_HiWord_bit { + GlobalReset = 0x0001, + RxReset = 0x0002, + TxReset = 0x0004, + DMAReset = 0x0008, + FIFOReset = 0x0010, + NetworkReset = 0x0020, + HostReset = 0x0040, + ResetBusy = 0x0400, +}; + +/* Bits in the interrupt status/mask registers. */ +enum intr_status_bits { + IntrSummary = 0x0001, IntrPCIErr = 0x0002, IntrMACCtrl = 0x0008, + IntrTxDone = 0x0004, IntrRxDone = 0x0010, IntrRxStart = 0x0020, + IntrDrvRqst = 0x0040, + StatsMax = 0x0080, LinkChange = 0x0100, + IntrTxDMADone = 0x0200, IntrRxDMADone = 0x0400, +}; + +/* Bits in the RxMode register. */ +enum rx_mode_bits { + AcceptAllIPMulti = 0x20, AcceptMultiHash = 0x10, AcceptAll = 0x08, + AcceptBroadcast = 0x04, AcceptMulticast = 0x02, AcceptMyPhys = + 0x01, +}; +/* Bits in MACCtrl. */ +enum mac_ctrl0_bits { + EnbFullDuplex = 0x20, EnbRcvLargeFrame = 0x40, + EnbFlowCtrl = 0x100, EnbPassRxCRC = 0x200, +}; +enum mac_ctrl1_bits { + StatsEnable = 0x0020, StatsDisable = 0x0040, StatsEnabled = 0x0080, + TxEnable = 0x0100, TxDisable = 0x0200, TxEnabled = 0x0400, + RxEnable = 0x0800, RxDisable = 0x1000, RxEnabled = 0x2000, +}; + +/* The Rx and Tx buffer descriptors. + Using only 32 bit fields simplifies software endian correction. + This structure must be aligned, and should avoid spanning cache lines. +*/ +struct netdev_desc { + u32 next_desc; + u32 status; + u32 addr; + u32 length; +}; + +/* Bits in netdev_desc.status */ +enum desc_status_bits { + DescOwn = 0x8000, + DescEndPacket = 0x4000, + DescEndRing = 0x2000, + LastFrag = 0x80000000, + DescIntrOnTx = 0x8000, + DescIntrOnDMADone = 0x80000000, + DisableAlign = 0x00000001, +}; + +/********************************************** +* Descriptor Ring and Buffer defination +***********************************************/ +/* Define the TX Descriptor */ +static struct netdev_desc tx_ring[TX_RING_SIZE]; + +/* Define the RX Descriptor */ +static struct netdev_desc rx_ring[RX_RING_SIZE]; + +/* Create a static buffer of size PKT_BUF_SZ for each RX and TX descriptor. + All descriptors point to a part of this buffer */ +struct { + unsigned char txb[PKT_BUF_SZ * TX_RING_SIZE]; + unsigned char rxb[RX_RING_SIZE * PKT_BUF_SZ]; +} rx_tx_buf __shared; +#define rxb rx_tx_buf.rxb +#define txb rx_tx_buf.txb + +/* FIXME: Move BASE to the private structure */ +static u32 BASE; +#define EEPROM_SIZE 128 + +enum pci_id_flags_bits { + PCI_USES_IO = 1, PCI_USES_MEM = 2, PCI_USES_MASTER = 4, + PCI_ADDR0 = 0 << 4, PCI_ADDR1 = 1 << 4, PCI_ADDR2 = + 2 << 4, PCI_ADDR3 = 3 << 4, +}; + +enum chip_capability_flags { CanHaveMII = 1, KendinPktDropBug = 2, }; +#define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_IO | PCI_ADDR0) + +#define MII_CNT 4 +static struct sundance_private { + const char *nic_name; + /* Frequently used values */ + + unsigned int cur_rx; /* Producer/consumer ring indicies */ + unsigned int mtu; + + /* These values keep track of the tranceiver/media in use */ + unsigned int flowctrl:1; + unsigned int an_enable:1; + + unsigned int speed; + + /* MII tranceiver section */ + struct mii_if_info mii_if; + int mii_preamble_required; + unsigned char phys[MII_CNT]; + unsigned char pci_rev_id; +} sdx; + +static struct sundance_private *sdc; + +/* Station Address location within the EEPROM */ +#define EEPROM_SA_OFFSET 0x10 +#define DEFAULT_INTR (IntrRxDMADone | IntrPCIErr | \ + IntrDrvRqst | IntrTxDone | StatsMax | \ + LinkChange) + +static int eeprom_read(long ioaddr, int location); +static int mdio_read(struct nic *nic, int phy_id, unsigned int location); +static void mdio_write(struct nic *nic, int phy_id, unsigned int location, + int value); +static void set_rx_mode(struct nic *nic); + +static void check_duplex(struct nic *nic) +{ + int mii_lpa = mdio_read(nic, sdc->phys[0], MII_LPA); + int negotiated = mii_lpa & sdc->mii_if.advertising; + int duplex; + + /* Force media */ + if (!sdc->an_enable || mii_lpa == 0xffff) { + if (sdc->mii_if.full_duplex) + outw(inw(BASE + MACCtrl0) | EnbFullDuplex, + BASE + MACCtrl0); + return; + } + + /* Autonegotiation */ + duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040; + if (sdc->mii_if.full_duplex != duplex) { + sdc->mii_if.full_duplex = duplex; + DBG ("%s: Setting %s-duplex based on MII #%d " + "negotiated capability %4.4x.\n", sdc->nic_name, + duplex ? "full" : "half", sdc->phys[0], + negotiated ); + outw(inw(BASE + MACCtrl0) | duplex ? 0x20 : 0, + BASE + MACCtrl0); + } +} + + +/************************************************************************** + * init_ring - setup the tx and rx descriptors + *************************************************************************/ +static void init_ring(struct nic *nic __unused) +{ + int i; + + sdc->cur_rx = 0; + + /* Initialize all the Rx descriptors */ + for (i = 0; i < RX_RING_SIZE; i++) { + rx_ring[i].next_desc = virt_to_le32desc(&rx_ring[i + 1]); + rx_ring[i].status = 0; + rx_ring[i].length = 0; + rx_ring[i].addr = 0; + } + + /* Mark the last entry as wrapping the ring */ + rx_ring[i - 1].next_desc = virt_to_le32desc(&rx_ring[0]); + + for (i = 0; i < RX_RING_SIZE; i++) { + rx_ring[i].addr = virt_to_le32desc(&rxb[i * PKT_BUF_SZ]); + rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LastFrag); + } + + /* We only use one transmit buffer, but two + * descriptors so transmit engines have somewhere + * to point should they feel the need */ + tx_ring[0].status = 0x00000000; + tx_ring[0].addr = virt_to_bus(&txb[0]); + tx_ring[0].next_desc = 0; /* virt_to_bus(&tx_ring[1]); */ + + /* This descriptor is never used */ + tx_ring[1].status = 0x00000000; + tx_ring[1].addr = 0; /*virt_to_bus(&txb[0]); */ + tx_ring[1].next_desc = 0; + + /* Mark the last entry as wrapping the ring, + * though this should never happen */ + tx_ring[1].length = cpu_to_le32(LastFrag | PKT_BUF_SZ); +} + +/************************************************************************** + * RESET - Reset Adapter + * ***********************************************************************/ +static void sundance_reset(struct nic *nic) +{ + int i; + + init_ring(nic); + + outl(virt_to_le32desc(&rx_ring[0]), BASE + RxListPtr); + /* The Tx List Pointer is written as packets are queued */ + + /* Initialize other registers. */ + /* __set_mac_addr(dev); */ + { + u16 addr16; + + addr16 = (nic->node_addr[0] | (nic->node_addr[1] << 8)); + outw(addr16, BASE + StationAddr); + addr16 = (nic->node_addr[2] | (nic->node_addr[3] << 8)); + outw(addr16, BASE + StationAddr + 2); + addr16 = (nic->node_addr[4] | (nic->node_addr[5] << 8)); + outw(addr16, BASE + StationAddr + 4); + } + + outw(sdc->mtu + 14, BASE + MaxFrameSize); + if (sdc->mtu > 2047) /* this will never happen with default options */ + outl(inl(BASE + ASICCtrl) | 0x0c, BASE + ASICCtrl); + + set_rx_mode(nic); + + outw(0, BASE + DownCounter); + /* Set the chip to poll every N*30nsec */ + outb(100, BASE + RxDMAPollPeriod); + + /* Fix DFE-580TX packet drop issue */ + if (sdc->pci_rev_id >= 0x14) + writeb(0x01, BASE + DebugCtrl1); + + outw(RxEnable | TxEnable, BASE + MACCtrl1); + + /* Construct a perfect filter frame with the mac address as first match + * and broadcast for all others */ + for (i = 0; i < 192; i++) + txb[i] = 0xFF; + + txb[0] = nic->node_addr[0]; + txb[1] = nic->node_addr[1]; + txb[2] = nic->node_addr[2]; + txb[3] = nic->node_addr[3]; + txb[4] = nic->node_addr[4]; + txb[5] = nic->node_addr[5]; + + DBG ( "%s: Done sundance_reset, status: Rx %hX Tx %hX " + "MAC Control %hX, %hX %hX\n", + sdc->nic_name, (int) inl(BASE + RxStatus), + (int) inw(BASE + TxStatus), (int) inl(BASE + MACCtrl0), + (int) inw(BASE + MACCtrl1), (int) inw(BASE + MACCtrl0) ); +} + +/************************************************************************** +IRQ - Wait for a frame +***************************************************************************/ +static void sundance_irq ( struct nic *nic, irq_action_t action ) { + unsigned int intr_status; + + switch ( action ) { + case DISABLE : + case ENABLE : + intr_status = inw(nic->ioaddr + IntrStatus); + intr_status = intr_status & ~DEFAULT_INTR; + if ( action == ENABLE ) + intr_status = intr_status | DEFAULT_INTR; + outw(intr_status, nic->ioaddr + IntrEnable); + break; + case FORCE : + outw(0x0200, BASE + ASICCtrl); + break; + } +} +/************************************************************************** +POLL - Wait for a frame +***************************************************************************/ +static int sundance_poll(struct nic *nic, int retreive) +{ + /* return true if there's an ethernet packet ready to read */ + /* nic->packet should contain data on return */ + /* nic->packetlen should contain length of data */ + int entry = sdc->cur_rx % RX_RING_SIZE; + u32 frame_status = le32_to_cpu(rx_ring[entry].status); + int intr_status; + int pkt_len = 0; + + if (!(frame_status & DescOwn)) + return 0; + + /* There is a packet ready */ + if(!retreive) + return 1; + + intr_status = inw(nic->ioaddr + IntrStatus); + outw(intr_status, nic->ioaddr + IntrStatus); + + pkt_len = frame_status & 0x1fff; + + if (frame_status & 0x001f4000) { + DBG ( "Polling frame_status error\n" ); /* Do we really care about this */ + } else { + if (pkt_len < rx_copybreak) { + /* FIXME: What should happen Will this ever occur */ + printf("Poll Error: pkt_len < rx_copybreak"); + } else { + nic->packetlen = pkt_len; + memcpy(nic->packet, rxb + + (sdc->cur_rx * PKT_BUF_SZ), nic->packetlen); + + } + } + rx_ring[entry].length = cpu_to_le32(PKT_BUF_SZ | LastFrag); + rx_ring[entry].status = 0; + entry++; + sdc->cur_rx = entry % RX_RING_SIZE; + outw(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone), + nic->ioaddr + IntrStatus); + return 1; +} + +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static void sundance_transmit(struct nic *nic, const char *d, /* Destination */ + unsigned int t, /* Type */ + unsigned int s, /* size */ + const char *p) +{ /* Packet */ + u16 nstype; + u32 to; + + /* Disable the Tx */ + outw(TxDisable, BASE + MACCtrl1); + + memcpy(txb, d, ETH_ALEN); + memcpy(txb + ETH_ALEN, nic->node_addr, ETH_ALEN); + nstype = htons((u16) t); + memcpy(txb + 2 * ETH_ALEN, (u8 *) & nstype, 2); + memcpy(txb + ETH_HLEN, p, s); + + s += ETH_HLEN; + s &= 0x0FFF; + while (s < ETH_ZLEN) + txb[s++] = '\0'; + + /* Setup the transmit descriptor */ + tx_ring[0].length = cpu_to_le32(s | LastFrag); + tx_ring[0].status = cpu_to_le32(0x00000001); + + /* Point to transmit descriptor */ + outl(virt_to_le32desc(&tx_ring[0]), BASE + TxListPtr); + + /* Enable Tx */ + outw(TxEnable, BASE + MACCtrl1); + /* Trigger an immediate send */ + outw(0, BASE + TxStatus); + + to = currticks() + TX_TIME_OUT; + while (!(tx_ring[0].status & 0x00010000) && (currticks() < to)); /* wait */ + + if (currticks() >= to) { + printf("TX Time Out"); + } + /* Disable Tx */ + outw(TxDisable, BASE + MACCtrl1); + +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void sundance_disable ( struct nic *nic __unused ) { + /* put the card in its initial state */ + /* This function serves 3 purposes. + * This disables DMA and interrupts so we don't receive + * unexpected packets or interrupts from the card after + * etherboot has finished. + * This frees resources so etherboot may use + * this driver on another interface + * This allows etherboot to reinitialize the interface + * if something is something goes wrong. + */ + outw(0x0000, BASE + IntrEnable); + /* Stop the Chipchips Tx and Rx Status */ + outw(TxDisable | RxDisable | StatsDisable, BASE + MACCtrl1); +} + +static struct nic_operations sundance_operations = { + .connect = dummy_connect, + .poll = sundance_poll, + .transmit = sundance_transmit, + .irq = sundance_irq, + +}; + +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +***************************************************************************/ +static int sundance_probe ( struct nic *nic, struct pci_device *pci ) { + + u8 ee_data[EEPROM_SIZE]; + u16 mii_ctl; + int i; + int speed; + + if (pci->ioaddr == 0) + return 0; + + /* BASE is used throughout to address the card */ + BASE = pci->ioaddr; + printf(" sundance.c: Found %s Vendor=0x%hX Device=0x%hX\n", + pci->driver_name, pci->vendor, pci->device); + + /* Get the MAC Address by reading the EEPROM */ + for (i = 0; i < 3; i++) { + ((u16 *) ee_data)[i] = + le16_to_cpu(eeprom_read(BASE, i + EEPROM_SA_OFFSET)); + } + /* Update the nic structure with the MAC Address */ + for (i = 0; i < ETH_ALEN; i++) { + nic->node_addr[i] = ee_data[i]; + } + + /* Set the card as PCI Bus Master */ + adjust_pci_device(pci); + +// sdc->mii_if.dev = pci; +// sdc->mii_if.phy_id_mask = 0x1f; +// sdc->mii_if.reg_num_mask = 0x1f; + + /* point to private storage */ + sdc = &sdx; + + sdc->nic_name = pci->driver_name; + sdc->mtu = mtu; + + pci_read_config_byte(pci, PCI_REVISION_ID, &sdc->pci_rev_id); + + DBG ( "Device revision id: %hx\n", sdc->pci_rev_id ); + + /* Print out some hardware info */ + DBG ( "%s: %s at ioaddr %hX, ", pci->driver_name, nic->node_addr, (unsigned int) BASE); + + sdc->mii_preamble_required = 0; + if (1) { + int phy, phy_idx = 0; + sdc->phys[0] = 1; /* Default Setting */ + sdc->mii_preamble_required++; + for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) { + int mii_status = mdio_read(nic, phy, MII_BMSR); + if (mii_status != 0xffff && mii_status != 0x0000) { + sdc->phys[phy_idx++] = phy; + sdc->mii_if.advertising = + mdio_read(nic, phy, MII_ADVERTISE); + if ((mii_status & 0x0040) == 0) + sdc->mii_preamble_required++; + DBG + ( "%s: MII PHY found at address %d, status " "%hX advertising %hX\n", sdc->nic_name, phy, mii_status, sdc->mii_if.advertising ); + } + } + sdc->mii_preamble_required--; + if (phy_idx == 0) + printf("%s: No MII transceiver found!\n", + sdc->nic_name); + sdc->mii_if.phy_id = sdc->phys[0]; + } + + /* Parse override configuration */ + sdc->an_enable = 1; + if (strcasecmp(media, "autosense") != 0) { + sdc->an_enable = 0; + if (strcasecmp(media, "100mbps_fd") == 0 || + strcasecmp(media, "4") == 0) { + sdc->speed = 100; + sdc->mii_if.full_duplex = 1; + } else if (strcasecmp(media, "100mbps_hd") == 0 + || strcasecmp(media, "3") == 0) { + sdc->speed = 100; + sdc->mii_if.full_duplex = 0; + } else if (strcasecmp(media, "10mbps_fd") == 0 || + strcasecmp(media, "2") == 0) { + sdc->speed = 10; + sdc->mii_if.full_duplex = 1; + } else if (strcasecmp(media, "10mbps_hd") == 0 || + strcasecmp(media, "1") == 0) { + sdc->speed = 10; + sdc->mii_if.full_duplex = 0; + } else { + sdc->an_enable = 1; + } + } + if (flowctrl == 1) + sdc->flowctrl = 1; + + /* Fibre PHY? */ + if (inl(BASE + ASICCtrl) & 0x80) { + /* Default 100Mbps Full */ + if (sdc->an_enable) { + sdc->speed = 100; + sdc->mii_if.full_duplex = 1; + sdc->an_enable = 0; + } + } + + /* The Linux driver uses flow control and resets the link here. This means the + mii section from above would need to be re done I believe. Since it serves + no real purpose leave it out. */ + + /* Force media type */ + if (!sdc->an_enable) { + mii_ctl = 0; + mii_ctl |= (sdc->speed == 100) ? BMCR_SPEED100 : 0; + mii_ctl |= (sdc->mii_if.full_duplex) ? BMCR_FULLDPLX : 0; + mdio_write(nic, sdc->phys[0], MII_BMCR, mii_ctl); + printf("Override speed=%d, %s duplex\n", + sdc->speed, + sdc->mii_if.full_duplex ? "Full" : "Half"); + } + + /* Reset the chip to erase previous misconfiguration */ + DBG ( "ASIC Control is %#x\n", inl(BASE + ASICCtrl) ); + outw(0x007f, BASE + ASICCtrl + 2); + + /* + * wait for reset to complete + * this is heavily inspired by the linux sundance driver + * according to the linux driver it can take up to 1ms for the reset + * to complete + */ + i = 0; + while(inl(BASE + ASICCtrl) & (ResetBusy << 16)) { + if(i++ >= 10) { + DBG("sundance: NIC reset did not complete.\n"); + break; + } + udelay(100); + } + + DBG ( "ASIC Control is now %#x.\n", inl(BASE + ASICCtrl) ); + + sundance_reset(nic); + if (sdc->an_enable) { + u16 mii_advertise, mii_lpa; + mii_advertise = + mdio_read(nic, sdc->phys[0], MII_ADVERTISE); + mii_lpa = mdio_read(nic, sdc->phys[0], MII_LPA); + mii_advertise &= mii_lpa; + if (mii_advertise & ADVERTISE_100FULL) + sdc->speed = 100; + else if (mii_advertise & ADVERTISE_100HALF) + sdc->speed = 100; + else if (mii_advertise & ADVERTISE_10FULL) + sdc->speed = 10; + else if (mii_advertise & ADVERTISE_10HALF) + sdc->speed = 10; + } else { + mii_ctl = mdio_read(nic, sdc->phys[0], MII_BMCR); + speed = (mii_ctl & BMCR_SPEED100) ? 100 : 10; + sdc->speed = speed; + printf("%s: Link changed: %dMbps ,", sdc->nic_name, speed); + printf("%s duplex.\n", (mii_ctl & BMCR_FULLDPLX) ? + "full" : "half"); + } + check_duplex(nic); + if (sdc->flowctrl && sdc->mii_if.full_duplex) { + outw(inw(BASE + MulticastFilter1 + 2) | 0x0200, + BASE + MulticastFilter1 + 2); + outw(inw(BASE + MACCtrl0) | EnbFlowCtrl, BASE + MACCtrl0); + } + printf("%dMbps, %s-Duplex\n", sdc->speed, + sdc->mii_if.full_duplex ? "Full" : "Half"); + + /* point to NIC specific routines */ + nic->nic_op = &sundance_operations; + + nic->irqno = pci->irq; + nic->ioaddr = BASE; + + return 1; +} + + +/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. */ +static int eeprom_read(long ioaddr, int location) +{ + int boguscnt = 10000; /* Typical 1900 ticks */ + outw(0x0200 | (location & 0xff), ioaddr + EECtrl); + do { + if (!(inw(ioaddr + EECtrl) & 0x8000)) { + return inw(ioaddr + EEData); + } + } + while (--boguscnt > 0); + return 0; +} + +/* MII transceiver control section. + Read and write the MII registers using software-generated serial + MDIO protocol. See the MII specifications or DP83840A data sheet + for details. + + The maximum data clock rate is 2.5 Mhz. + The timing is decoupled from the processor clock by flushing the write + from the CPU write buffer with a following read, and using PCI + transaction time. */ + +#define mdio_in(mdio_addr) inb(mdio_addr) +#define mdio_out(value, mdio_addr) outb(value, mdio_addr) +#define mdio_delay(mdio_addr) inb(mdio_addr) + +enum mii_reg_bits { + MDIO_ShiftClk = 0x0001, MDIO_Data = 0x0002, MDIO_EnbOutput = + 0x0004, +}; +#define MDIO_EnbIn (0) +#define MDIO_WRITE0 (MDIO_EnbOutput) +#define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput) + +/* Generate the preamble required for initial synchronization and + a few older transceivers. */ +static void mdio_sync(long mdio_addr) +{ + int bits = 32; + + /* Establish sync by sending at least 32 logic ones. */ + while (--bits >= 0) { + mdio_out(MDIO_WRITE1, mdio_addr); + mdio_delay(mdio_addr); + mdio_out(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr); + mdio_delay(mdio_addr); + } +} + +static int +mdio_read(struct nic *nic __unused, int phy_id, unsigned int location) +{ + long mdio_addr = BASE + MIICtrl; + int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location; + int i, retval = 0; + + if (sdc->mii_preamble_required) + mdio_sync(mdio_addr); + + /* Shift the read command bits out. */ + for (i = 15; i >= 0; i--) { + int dataval = + (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; + + mdio_out(dataval, mdio_addr); + mdio_delay(mdio_addr); + mdio_out(dataval | MDIO_ShiftClk, mdio_addr); + mdio_delay(mdio_addr); + } + /* Read the two transition, 16 data, and wire-idle bits. */ + for (i = 19; i > 0; i--) { + mdio_out(MDIO_EnbIn, mdio_addr); + mdio_delay(mdio_addr); + retval = (retval << 1) | ((mdio_in(mdio_addr) & MDIO_Data) + ? 1 : 0); + mdio_out(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr); + mdio_delay(mdio_addr); + } + return (retval >> 1) & 0xffff; +} + +static void +mdio_write(struct nic *nic __unused, int phy_id, + unsigned int location, int value) +{ + long mdio_addr = BASE + MIICtrl; + int mii_cmd = + (0x5002 << 16) | (phy_id << 23) | (location << 18) | value; + int i; + + if (sdc->mii_preamble_required) + mdio_sync(mdio_addr); + + /* Shift the command bits out. */ + for (i = 31; i >= 0; i--) { + int dataval = + (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; + mdio_out(dataval, mdio_addr); + mdio_delay(mdio_addr); + mdio_out(dataval | MDIO_ShiftClk, mdio_addr); + mdio_delay(mdio_addr); + } + /* Clear out extra bits. */ + for (i = 2; i > 0; i--) { + mdio_out(MDIO_EnbIn, mdio_addr); + mdio_delay(mdio_addr); + mdio_out(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr); + mdio_delay(mdio_addr); + } + return; +} + +static void set_rx_mode(struct nic *nic __unused) +{ + int i; + u16 mc_filter[4]; /* Multicast hash filter */ + u32 rx_mode; + + memset(mc_filter, 0xff, sizeof(mc_filter)); + rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; + + if (sdc->mii_if.full_duplex && sdc->flowctrl) + mc_filter[3] |= 0x0200; + for (i = 0; i < 4; i++) + outw(mc_filter[i], BASE + MulticastFilter0 + i * 2); + outb(rx_mode, BASE + RxMode); + return; +} + +static struct pci_device_id sundance_nics[] = { + PCI_ROM(0x13f0, 0x0201, "sundance", "ST201 Sundance 'Alta' based Adaptor", 0), + PCI_ROM(0x1186, 0x1002, "dfe530txs", "D-Link DFE530TXS (Sundance ST201 Alta)", 0), + PCI_ROM(0x13f0, 0x0200, "ip100a", "IC+ IP100A", 0), +}; + +PCI_DRIVER ( sundance_driver, sundance_nics, PCI_NO_CLASS ); + +DRIVER ( "SUNDANCE/PCI", nic_driver, pci_driver, sundance_driver, + sundance_probe, sundance_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/tlan.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/tlan.c new file mode 100644 index 0000000..e5f04fa --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/tlan.c @@ -0,0 +1,1723 @@ +/************************************************************************** +* +* tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN +* Written 2003-2003 by Timothy Legge <tlegge@rogers.com> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +* +* Portions of this code based on: +* lan.c: Linux ThunderLan Driver: +* +* by James Banks +* +* (C) 1997-1998 Caldera, Inc. +* (C) 1998 James Banks +* (C) 1999-2001 Torben Mathiasen +* (C) 2002 Samuel Chessman +* +* REVISION HISTORY: +* ================ +* v1.0 07-08-2003 timlegge Initial not quite working version +* v1.1 07-27-2003 timlegge Sync 5.0 and 5.1 versions +* v1.2 08-19-2003 timlegge Implement Multicast Support +* v1.3 08-23-2003 timlegge Fix the transmit Function +* v1.4 01-17-2004 timlegge Initial driver output cleanup +* +* Indent Options: indent -kr -i8 +***************************************************************************/ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include "etherboot.h" +#include "nic.h" +#include <gpxe/pci.h> +#include <gpxe/ethernet.h> +#include <mii.h> +#include "tlan.h" + +#define drv_version "v1.4" +#define drv_date "01-17-2004" + +/* NIC specific static variables go here */ +#define HZ 100 +#define TX_TIME_OUT (6*HZ) + +/* Condensed operations for readability. */ +#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) +#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) + +static void TLan_ResetLists(struct nic *nic __unused); +static void TLan_ResetAdapter(struct nic *nic __unused); +static void TLan_FinishReset(struct nic *nic __unused); + +static void TLan_EeSendStart(u16); +static int TLan_EeSendByte(u16, u8, int); +static void TLan_EeReceiveByte(u16, u8 *, int); +static int TLan_EeReadByte(u16 io_base, u8, u8 *); + +static void TLan_PhyDetect(struct nic *nic); +static void TLan_PhyPowerDown(struct nic *nic); +static void TLan_PhyPowerUp(struct nic *nic); + + +static void TLan_SetMac(struct nic *nic __unused, int areg, unsigned char *mac); + +static void TLan_PhyReset(struct nic *nic); +static void TLan_PhyStartLink(struct nic *nic); +static void TLan_PhyFinishAutoNeg(struct nic *nic); + +#ifdef MONITOR +static void TLan_PhyMonitor(struct nic *nic); +#endif + + +static void refill_rx(struct nic *nic __unused); + +static int TLan_MiiReadReg(struct nic *nic __unused, u16, u16, u16 *); +static void TLan_MiiSendData(u16, u32, unsigned); +static void TLan_MiiSync(u16); +static void TLan_MiiWriteReg(struct nic *nic __unused, u16, u16, u16); + + +static const char *media[] = { + "10BaseT-HD ", "10BaseT-FD ", "100baseTx-HD ", + "100baseTx-FD", "100baseT4", 0 +}; + +/* This much match tlan_pci_tbl[]! */ +enum tlan_nics { + NETEL10 = 0, NETEL100 = 1, NETFLEX3I = 2, THUNDER = 3, NETFLEX3B = + 4, NETEL100PI = 5, + NETEL100D = 6, NETEL100I = 7, OC2183 = 8, OC2325 = 9, OC2326 = + 10, NETELLIGENT_10_100_WS_5100 = 11, + NETELLIGENT_10_T2 = 12 +}; + +struct pci_id_info { + const char *name; + int nic_id; + struct match_info { + u32 pci, pci_mask, subsystem, subsystem_mask; + u32 revision, revision_mask; /* Only 8 bits. */ + } id; + u32 flags; + u16 addrOfs; /* Address Offset */ +}; + +static const struct pci_id_info tlan_pci_tbl[] = { + {"Compaq Netelligent 10 T PCI UTP", NETEL10, + {0xae340e11, 0xffffffff, 0, 0, 0, 0}, + TLAN_ADAPTER_ACTIVITY_LED, 0x83}, + {"Compaq Netelligent 10/100 TX PCI UTP", NETEL100, + {0xae320e11, 0xffffffff, 0, 0, 0, 0}, + TLAN_ADAPTER_ACTIVITY_LED, 0x83}, + {"Compaq Integrated NetFlex-3/P", NETFLEX3I, + {0xae350e11, 0xffffffff, 0, 0, 0, 0}, + TLAN_ADAPTER_NONE, 0x83}, + {"Compaq NetFlex-3/P", THUNDER, + {0xf1300e11, 0xffffffff, 0, 0, 0, 0}, + TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83}, + {"Compaq NetFlex-3/P", NETFLEX3B, + {0xf1500e11, 0xffffffff, 0, 0, 0, 0}, + TLAN_ADAPTER_NONE, 0x83}, + {"Compaq Netelligent Integrated 10/100 TX UTP", NETEL100PI, + {0xae430e11, 0xffffffff, 0, 0, 0, 0}, + TLAN_ADAPTER_ACTIVITY_LED, 0x83}, + {"Compaq Netelligent Dual 10/100 TX PCI UTP", NETEL100D, + {0xae400e11, 0xffffffff, 0, 0, 0, 0}, + TLAN_ADAPTER_NONE, 0x83}, + {"Compaq Netelligent 10/100 TX Embedded UTP", NETEL100I, + {0xb0110e11, 0xffffffff, 0, 0, 0, 0}, + TLAN_ADAPTER_NONE, 0x83}, + {"Olicom OC-2183/2185", OC2183, + {0x0013108d, 0xffffffff, 0, 0, 0, 0}, + TLAN_ADAPTER_USE_INTERN_10, 0x83}, + {"Olicom OC-2325", OC2325, + {0x0012108d, 0xffffffff, 0, 0, 0, 0}, + TLAN_ADAPTER_UNMANAGED_PHY, 0xF8}, + {"Olicom OC-2326", OC2326, + {0x0014108d, 0xffffffff, 0, 0, 0, 0}, + TLAN_ADAPTER_USE_INTERN_10, 0xF8}, + {"Compaq Netelligent 10/100 TX UTP", NETELLIGENT_10_100_WS_5100, + {0xb0300e11, 0xffffffff, 0, 0, 0, 0}, + TLAN_ADAPTER_ACTIVITY_LED, 0x83}, + {"Compaq Netelligent 10 T/2 PCI UTP/Coax", NETELLIGENT_10_T2, + {0xb0120e11, 0xffffffff, 0, 0, 0, 0}, + TLAN_ADAPTER_NONE, 0x83}, + {"Compaq NetFlex-3/E", 0, /* EISA card */ + {0, 0, 0, 0, 0, 0}, + TLAN_ADAPTER_ACTIVITY_LED | TLAN_ADAPTER_UNMANAGED_PHY | + TLAN_ADAPTER_BIT_RATE_PHY, 0x83}, + {"Compaq NetFlex-3/E", 0, /* EISA card */ + {0, 0, 0, 0, 0, 0}, + TLAN_ADAPTER_ACTIVITY_LED, 0x83}, + {0, 0, + {0, 0, 0, 0, 0, 0}, + 0, 0}, +}; + +struct TLanList { + u32 forward; + u16 cStat; + u16 frameSize; + struct { + u32 count; + u32 address; + } buffer[TLAN_BUFFERS_PER_LIST]; +}; + +struct { + struct TLanList tx_ring[TLAN_NUM_TX_LISTS]; + unsigned char txb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_TX_LISTS]; + struct TLanList rx_ring[TLAN_NUM_RX_LISTS]; + unsigned char rxb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_RX_LISTS]; +} tlan_buffers __shared; +#define tx_ring tlan_buffers.tx_ring +#define txb tlan_buffers.txb +#define rx_ring tlan_buffers.rx_ring +#define rxb tlan_buffers.rxb + +typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE]; + +static int chip_idx; + +/***************************************************************** +* TLAN Private Information Structure +* +****************************************************************/ +static struct tlan_private { + unsigned short vendor_id; /* PCI Vendor code */ + unsigned short dev_id; /* PCI Device code */ + const char *nic_name; + unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indicies */ + unsigned rx_buf_sz; /* Based on mtu + Slack */ + struct TLanList *txList; + u32 txHead; + u32 txInProgress; + u32 txTail; + int eoc; + u32 phyOnline; + u32 aui; + u32 duplex; + u32 phy[2]; + u32 phyNum; + u32 speed; + u8 tlanRev; + u8 tlanFullDuplex; + u8 link; + u8 neg_be_verbose; +} TLanPrivateInfo; + +static struct tlan_private *priv; + +static u32 BASE; + +/*************************************************************** +* TLan_ResetLists +* +* Returns: +* Nothing +* Parms: +* dev The device structure with the list +* stuctures to be reset. +* +* This routine sets the variables associated with managing +* the TLAN lists to their initial values. +* +**************************************************************/ + +static void TLan_ResetLists(struct nic *nic __unused) +{ + + int i; + struct TLanList *list; + priv->txHead = 0; + priv->txTail = 0; + + for (i = 0; i < TLAN_NUM_TX_LISTS; i++) { + list = &tx_ring[i]; + list->cStat = TLAN_CSTAT_UNUSED; + list->buffer[0].address = virt_to_bus(txb + + (i * TLAN_MAX_FRAME_SIZE)); + list->buffer[2].count = 0; + list->buffer[2].address = 0; + list->buffer[9].address = 0; + } + + priv->cur_rx = 0; + priv->rx_buf_sz = (TLAN_MAX_FRAME_SIZE); +// priv->rx_head_desc = &rx_ring[0]; + + /* Initialize all the Rx descriptors */ + for (i = 0; i < TLAN_NUM_RX_LISTS; i++) { + rx_ring[i].forward = virt_to_le32desc(&rx_ring[i + 1]); + rx_ring[i].cStat = TLAN_CSTAT_READY; + rx_ring[i].frameSize = TLAN_MAX_FRAME_SIZE; + rx_ring[i].buffer[0].count = + TLAN_MAX_FRAME_SIZE | TLAN_LAST_BUFFER; + rx_ring[i].buffer[0].address = + virt_to_le32desc(&rxb[i * TLAN_MAX_FRAME_SIZE]); + rx_ring[i].buffer[1].count = 0; + rx_ring[i].buffer[1].address = 0; + } + + /* Mark the last entry as wrapping the ring */ + rx_ring[i - 1].forward = virt_to_le32desc(&rx_ring[0]); + priv->dirty_rx = (unsigned int) (i - TLAN_NUM_RX_LISTS); + +} /* TLan_ResetLists */ + +/*************************************************************** +* TLan_Reset +* +* Returns: +* 0 +* Parms: +* dev Pointer to device structure of adapter +* to be reset. +* +* This function resets the adapter and it's physical +* device. See Chap. 3, pp. 9-10 of the "ThunderLAN +* Programmer's Guide" for details. The routine tries to +* implement what is detailed there, though adjustments +* have been made. +* +**************************************************************/ + +void TLan_ResetAdapter(struct nic *nic __unused) +{ + int i; + u32 addr; + u32 data; + u8 data8; + + priv->tlanFullDuplex = FALSE; + priv->phyOnline = 0; +/* 1. Assert reset bit. */ + + data = inl(BASE + TLAN_HOST_CMD); + data |= TLAN_HC_AD_RST; + outl(data, BASE + TLAN_HOST_CMD); + + udelay(1000); + +/* 2. Turn off interrupts. ( Probably isn't necessary ) */ + + data = inl(BASE + TLAN_HOST_CMD); + data |= TLAN_HC_INT_OFF; + outl(data, BASE + TLAN_HOST_CMD); +/* 3. Clear AREGs and HASHs. */ + + for (i = TLAN_AREG_0; i <= TLAN_HASH_2; i += 4) { + TLan_DioWrite32(BASE, (u16) i, 0); + } + +/* 4. Setup NetConfig register. */ + + data = + TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN; + TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data); + +/* 5. Load Ld_Tmr and Ld_Thr in HOST_CMD. */ + + outl(TLAN_HC_LD_TMR | 0x3f, BASE + TLAN_HOST_CMD); + outl(TLAN_HC_LD_THR | 0x0, BASE + TLAN_HOST_CMD); + +/* 6. Unreset the MII by setting NMRST (in NetSio) to 1. */ + + outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR); + addr = BASE + TLAN_DIO_DATA + TLAN_NET_SIO; + TLan_SetBit(TLAN_NET_SIO_NMRST, addr); + +/* 7. Setup the remaining registers. */ + + if (priv->tlanRev >= 0x30) { + data8 = TLAN_ID_TX_EOC | TLAN_ID_RX_EOC; + TLan_DioWrite8(BASE, TLAN_INT_DIS, data8); + } + TLan_PhyDetect(nic); + data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN; + + if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_BIT_RATE_PHY) { + data |= TLAN_NET_CFG_BIT; + if (priv->aui == 1) { + TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x0a); + } else if (priv->duplex == TLAN_DUPLEX_FULL) { + TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x00); + priv->tlanFullDuplex = TRUE; + } else { + TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x08); + } + } + + if (priv->phyNum == 0) { + data |= TLAN_NET_CFG_PHY_EN; + } + TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data); + + if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) { + TLan_FinishReset(nic); + } else { + TLan_PhyPowerDown(nic); + } + +} /* TLan_ResetAdapter */ + +void TLan_FinishReset(struct nic *nic) +{ + + u8 data; + u32 phy; + u8 sio; + u16 status; + u16 partner; + u16 tlphy_ctl; + u16 tlphy_par; + u16 tlphy_id1, tlphy_id2; + int i; + + phy = priv->phy[priv->phyNum]; + + data = TLAN_NET_CMD_NRESET | TLAN_NET_CMD_NWRAP; + if (priv->tlanFullDuplex) { + data |= TLAN_NET_CMD_DUPLEX; + } + TLan_DioWrite8(BASE, TLAN_NET_CMD, data); + data = TLAN_NET_MASK_MASK4 | TLAN_NET_MASK_MASK5; + if (priv->phyNum == 0) { + data |= TLAN_NET_MASK_MASK7; + } + TLan_DioWrite8(BASE, TLAN_NET_MASK, data); + TLan_DioWrite16(BASE, TLAN_MAX_RX, ((1536) + 7) & ~7); + TLan_MiiReadReg(nic, phy, MII_PHYSID1, &tlphy_id1); + TLan_MiiReadReg(nic, phy, MII_PHYSID2, &tlphy_id2); + + if ((tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) + || (priv->aui)) { + status = BMSR_LSTATUS; + DBG ( "TLAN: %s: Link forced.\n", priv->nic_name ); + } else { + TLan_MiiReadReg(nic, phy, MII_BMSR, &status); + udelay(1000); + TLan_MiiReadReg(nic, phy, MII_BMSR, &status); + if ((status & BMSR_LSTATUS) && /* We only support link info on Nat.Sem. PHY's */ + (tlphy_id1 == NAT_SEM_ID1) + && (tlphy_id2 == NAT_SEM_ID2)) { + TLan_MiiReadReg(nic, phy, MII_LPA, &partner); + TLan_MiiReadReg(nic, phy, TLAN_TLPHY_PAR, + &tlphy_par); + + DBG ( "TLAN: %s: Link active with ", + priv->nic_name ); + if (!(tlphy_par & TLAN_PHY_AN_EN_STAT)) { + DBG ( "forced 10%sMbps %s-Duplex\n", + tlphy_par & TLAN_PHY_SPEED_100 ? "" + : "0", + tlphy_par & TLAN_PHY_DUPLEX_FULL ? + "Full" : "Half" ); + } else { + DBG + ( "AutoNegotiation enabled, at 10%sMbps %s-Duplex\n", + tlphy_par & TLAN_PHY_SPEED_100 ? "" : + "0", + tlphy_par & TLAN_PHY_DUPLEX_FULL ? + "Full" : "Half" ); + DBG ( "TLAN: Partner capability: " ); + for (i = 5; i <= 10; i++) + if (partner & (1 << i)) { + DBG ( "%s", media[i - 5] ); + } + DBG ( "\n" ); + } + + TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK); +#ifdef MONITOR + /* We have link beat..for now anyway */ + priv->link = 1; + /*Enabling link beat monitoring */ + /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_LINK_BEAT ); */ + mdelay(10000); + TLan_PhyMonitor(nic); +#endif + } else if (status & BMSR_LSTATUS) { + DBG ( "TLAN: %s: Link active\n", priv->nic_name ); + TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK); + } + } + + if (priv->phyNum == 0) { + TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tlphy_ctl); + tlphy_ctl |= TLAN_TC_INTEN; + TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tlphy_ctl); + sio = TLan_DioRead8(BASE, TLAN_NET_SIO); + sio |= TLAN_NET_SIO_MINTEN; + TLan_DioWrite8(BASE, TLAN_NET_SIO, sio); + } + + if (status & BMSR_LSTATUS) { + TLan_SetMac(nic, 0, nic->node_addr); + priv->phyOnline = 1; + outb((TLAN_HC_INT_ON >> 8), BASE + TLAN_HOST_CMD + 1); + outl(virt_to_bus(&rx_ring), BASE + TLAN_CH_PARM); + outl(TLAN_HC_GO | TLAN_HC_RT, BASE + TLAN_HOST_CMD); + } else { + DBG + ( "TLAN: %s: Link inactive, will retry in 10 secs...\n", + priv->nic_name ); + /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_FINISH_RESET ); */ + mdelay(10000); + TLan_FinishReset(nic); + return; + + } + +} /* TLan_FinishReset */ + +/************************************************************************** +POLL - Wait for a frame +***************************************************************************/ +static int tlan_poll(struct nic *nic, int retrieve) +{ + /* return true if there's an ethernet packet ready to read */ + /* nic->packet should contain data on return */ + /* nic->packetlen should contain length of data */ + u32 framesize; + u32 host_cmd = 0; + u32 ack = 1; + int eoc = 0; + int entry = priv->cur_rx % TLAN_NUM_RX_LISTS; + u16 tmpCStat = le32_to_cpu(rx_ring[entry].cStat); + u16 host_int = inw(BASE + TLAN_HOST_INT); + + if ((tmpCStat & TLAN_CSTAT_FRM_CMP) && !retrieve) + return 1; + + outw(host_int, BASE + TLAN_HOST_INT); + + if (!(tmpCStat & TLAN_CSTAT_FRM_CMP)) + return 0; + + /* printf("PI-1: 0x%hX\n", host_int); */ + if (tmpCStat & TLAN_CSTAT_EOC) + eoc = 1; + + framesize = rx_ring[entry].frameSize; + + nic->packetlen = framesize; + + DBG ( ".%d.", (unsigned int) framesize ); + + memcpy(nic->packet, rxb + + (priv->cur_rx * TLAN_MAX_FRAME_SIZE), nic->packetlen); + + rx_ring[entry].cStat = 0; + + DBG ( "%d", entry ); + + entry = (entry + 1) % TLAN_NUM_RX_LISTS; + priv->cur_rx = entry; + if (eoc) { + if ((rx_ring[entry].cStat & TLAN_CSTAT_READY) == + TLAN_CSTAT_READY) { + ack |= TLAN_HC_GO | TLAN_HC_RT; + host_cmd = TLAN_HC_ACK | ack | 0x001C0000; + outl(host_cmd, BASE + TLAN_HOST_CMD); + } + } else { + host_cmd = TLAN_HC_ACK | ack | (0x000C0000); + outl(host_cmd, BASE + TLAN_HOST_CMD); + + DBG ( "AC: 0x%hX\n", inw(BASE + TLAN_CH_PARM) ); + DBG ( "PI-2: 0x%hX\n", inw(BASE + TLAN_HOST_INT) ); + } + refill_rx(nic); + return (1); /* initially as this is called to flush the input */ +} + +static void refill_rx(struct nic *nic __unused) +{ + int entry = 0; + + for (; + (priv->cur_rx - priv->dirty_rx + + TLAN_NUM_RX_LISTS) % TLAN_NUM_RX_LISTS > 0; + priv->dirty_rx = (priv->dirty_rx + 1) % TLAN_NUM_RX_LISTS) { + entry = priv->dirty_rx % TLAN_NUM_TX_LISTS; + rx_ring[entry].frameSize = TLAN_MAX_FRAME_SIZE; + rx_ring[entry].cStat = TLAN_CSTAT_READY; + } + +} + +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static void tlan_transmit(struct nic *nic, const char *d, /* Destination */ + unsigned int t, /* Type */ + unsigned int s, /* size */ + const char *p) +{ /* Packet */ + u16 nstype; + u32 to; + struct TLanList *tail_list; + struct TLanList *head_list; + u8 *tail_buffer; + u32 ack = 0; + u32 host_cmd; + int eoc = 0; + u16 tmpCStat; + u16 host_int = inw(BASE + TLAN_HOST_INT); + + int entry = 0; + + DBG ( "INT0-0x%hX\n", host_int ); + + if (!priv->phyOnline) { + printf("TRANSMIT: %s PHY is not ready\n", priv->nic_name); + return; + } + + tail_list = priv->txList + priv->txTail; + + if (tail_list->cStat != TLAN_CSTAT_UNUSED) { + printf("TRANSMIT: %s is busy (Head=%p Tail=%x)\n", + priv->nic_name, priv->txList, (unsigned int) priv->txTail); + tx_ring[entry].cStat = TLAN_CSTAT_UNUSED; +// priv->txBusyCount++; + return; + } + + tail_list->forward = 0; + + tail_buffer = txb + (priv->txTail * TLAN_MAX_FRAME_SIZE); + + /* send the packet to destination */ + memcpy(tail_buffer, d, ETH_ALEN); + memcpy(tail_buffer + ETH_ALEN, nic->node_addr, ETH_ALEN); + nstype = htons((u16) t); + memcpy(tail_buffer + 2 * ETH_ALEN, (u8 *) & nstype, 2); + memcpy(tail_buffer + ETH_HLEN, p, s); + + s += ETH_HLEN; + s &= 0x0FFF; + while (s < ETH_ZLEN) + tail_buffer[s++] = '\0'; + + /*=====================================================*/ + /* Receive + * 0000 0000 0001 1100 + * 0000 0000 0000 1100 + * 0000 0000 0000 0011 = 0x0003 + * + * 0000 0000 0000 0000 0000 0000 0000 0011 + * 0000 0000 0000 1100 0000 0000 0000 0000 = 0x000C0000 + * + * Transmit + * 0000 0000 0001 1100 + * 0000 0000 0000 0100 + * 0000 0000 0000 0001 = 0x0001 + * + * 0000 0000 0000 0000 0000 0000 0000 0001 + * 0000 0000 0000 0100 0000 0000 0000 0000 = 0x00040000 + * */ + + /* Setup the transmit descriptor */ + tail_list->frameSize = (u16) s; + tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) s; + tail_list->buffer[1].count = 0; + tail_list->buffer[1].address = 0; + + tail_list->cStat = TLAN_CSTAT_READY; + + DBG ( "INT1-0x%hX\n", inw(BASE + TLAN_HOST_INT) ); + + if (!priv->txInProgress) { + priv->txInProgress = 1; + outl(virt_to_le32desc(tail_list), BASE + TLAN_CH_PARM); + outl(TLAN_HC_GO, BASE + TLAN_HOST_CMD); + } else { + if (priv->txTail == 0) { + DBG ( "Out buffer\n" ); + (priv->txList + (TLAN_NUM_TX_LISTS - 1))->forward = + virt_to_le32desc(tail_list); + } else { + DBG ( "Fix this \n" ); + (priv->txList + (priv->txTail - 1))->forward = + virt_to_le32desc(tail_list); + } + } + + CIRC_INC(priv->txTail, TLAN_NUM_TX_LISTS); + + DBG ( "INT2-0x%hX\n", inw(BASE + TLAN_HOST_INT) ); + + to = currticks() + TX_TIME_OUT; + while ((tail_list->cStat == TLAN_CSTAT_READY) && currticks() < to); + + head_list = priv->txList + priv->txHead; + while (((tmpCStat = head_list->cStat) & TLAN_CSTAT_FRM_CMP) + && (ack < 255)) { + ack++; + if(tmpCStat & TLAN_CSTAT_EOC) + eoc =1; + head_list->cStat = TLAN_CSTAT_UNUSED; + CIRC_INC(priv->txHead, TLAN_NUM_TX_LISTS); + head_list = priv->txList + priv->txHead; + + } + if(!ack) + printf("Incomplete TX Frame\n"); + + if(eoc) { + head_list = priv->txList + priv->txHead; + if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) { + outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM); + ack |= TLAN_HC_GO; + } else { + priv->txInProgress = 0; + } + } + if(ack) { + host_cmd = TLAN_HC_ACK | ack; + outl(host_cmd, BASE + TLAN_HOST_CMD); + } + + if(priv->tlanRev < 0x30 ) { + ack = 1; + head_list = priv->txList + priv->txHead; + if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) { + outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM); + ack |= TLAN_HC_GO; + } else { + priv->txInProgress = 0; + } + host_cmd = TLAN_HC_ACK | ack | 0x00140000; + outl(host_cmd, BASE + TLAN_HOST_CMD); + + } + + if (currticks() >= to) { + printf("TX Time Out"); + } +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void tlan_disable ( struct nic *nic __unused ) { + /* put the card in its initial state */ + /* This function serves 3 purposes. + * This disables DMA and interrupts so we don't receive + * unexpected packets or interrupts from the card after + * etherboot has finished. + * This frees resources so etherboot may use + * this driver on another interface + * This allows etherboot to reinitialize the interface + * if something is something goes wrong. + * + */ + outl(TLAN_HC_AD_RST, BASE + TLAN_HOST_CMD); +} + +/************************************************************************** +IRQ - Enable, Disable, or Force interrupts +***************************************************************************/ +static void tlan_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + +static struct nic_operations tlan_operations = { + .connect = dummy_connect, + .poll = tlan_poll, + .transmit = tlan_transmit, + .irq = tlan_irq, + +}; + +static void TLan_SetMulticastList(struct nic *nic) { + int i; + u8 tmp; + + /* !IFF_PROMISC */ + tmp = TLan_DioRead8(BASE, TLAN_NET_CMD); + TLan_DioWrite8(BASE, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF); + + /* IFF_ALLMULTI */ + for(i = 0; i< 3; i++) + TLan_SetMac(nic, i + 1, NULL); + TLan_DioWrite32(BASE, TLAN_HASH_1, 0xFFFFFFFF); + TLan_DioWrite32(BASE, TLAN_HASH_2, 0xFFFFFFFF); + + +} +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +***************************************************************************/ + +#define board_found 1 +#define valid_link 0 +static int tlan_probe ( struct nic *nic, struct pci_device *pci ) { + + u16 data = 0; + int err; + int i; + + if (pci->ioaddr == 0) + return 0; + + nic->irqno = 0; + nic->ioaddr = pci->ioaddr; + + BASE = pci->ioaddr; + + /* Set nic as PCI bus master */ + adjust_pci_device(pci); + + /* Point to private storage */ + priv = &TLanPrivateInfo; + + /* Figure out which chip we're dealing with */ + i = 0; + chip_idx = -1; + while (tlan_pci_tbl[i].name) { + if ((((u32) pci->device << 16) | pci->vendor) == + (tlan_pci_tbl[i].id.pci & 0xffffffff)) { + chip_idx = i; + break; + } + i++; + } + + priv->vendor_id = pci->vendor; + priv->dev_id = pci->device; + priv->nic_name = pci->driver_name; + priv->eoc = 0; + + err = 0; + for (i = 0; i < 6; i++) + err |= TLan_EeReadByte(BASE, + (u8) tlan_pci_tbl[chip_idx]. + addrOfs + i, + (u8 *) & nic->node_addr[i]); + if (err) { + printf ( "TLAN: %s: Error reading MAC from eeprom: %d\n", + pci->driver_name, err); + } else { + DBG ( "%s: %s at ioaddr %#lX, ", + pci->driver_name, eth_ntoa ( nic->node_addr ), pci->ioaddr ); + } + + priv->tlanRev = TLan_DioRead8(BASE, TLAN_DEF_REVISION); + printf("revision: 0x%hX\n", priv->tlanRev); + + TLan_ResetLists(nic); + TLan_ResetAdapter(nic); + + data = inl(BASE + TLAN_HOST_CMD); + data |= TLAN_HC_INT_OFF; + outw(data, BASE + TLAN_HOST_CMD); + + TLan_SetMulticastList(nic); + udelay(100); + priv->txList = tx_ring; + +/* if (board_found && valid_link) + {*/ + /* point to NIC specific routines */ + nic->nic_op = &tlan_operations; + return 1; +} + + +/***************************************************************************** +****************************************************************************** + + ThunderLAN Driver Eeprom routines + + The Compaq Netelligent 10 and 10/100 cards use a Microchip 24C02A + EEPROM. These functions are based on information in Microchip's + data sheet. I don't know how well this functions will work with + other EEPROMs. + +****************************************************************************** +*****************************************************************************/ + + +/*************************************************************** +* TLan_EeSendStart +* +* Returns: +* Nothing +* Parms: +* io_base The IO port base address for the +* TLAN device with the EEPROM to +* use. +* +* This function sends a start cycle to an EEPROM attached +* to a TLAN chip. +* +**************************************************************/ + +void TLan_EeSendStart(u16 io_base) +{ + u16 sio; + + outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR); + sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO; + + TLan_SetBit(TLAN_NET_SIO_ECLOK, sio); + TLan_SetBit(TLAN_NET_SIO_EDATA, sio); + TLan_SetBit(TLAN_NET_SIO_ETXEN, sio); + TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); + TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio); + +} /* TLan_EeSendStart */ + +/*************************************************************** +* TLan_EeSendByte +* +* Returns: +* If the correct ack was received, 0, otherwise 1 +* Parms: io_base The IO port base address for the +* TLAN device with the EEPROM to +* use. +* data The 8 bits of information to +* send to the EEPROM. +* stop If TLAN_EEPROM_STOP is passed, a +* stop cycle is sent after the +* byte is sent after the ack is +* read. +* +* This function sends a byte on the serial EEPROM line, +* driving the clock to send each bit. The function then +* reverses transmission direction and reads an acknowledge +* bit. +* +**************************************************************/ + +int TLan_EeSendByte(u16 io_base, u8 data, int stop) +{ + int err; + u8 place; + u16 sio; + + outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR); + sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO; + + /* Assume clock is low, tx is enabled; */ + for (place = 0x80; place != 0; place >>= 1) { + if (place & data) + TLan_SetBit(TLAN_NET_SIO_EDATA, sio); + else + TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); + TLan_SetBit(TLAN_NET_SIO_ECLOK, sio); + TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio); + } + TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio); + TLan_SetBit(TLAN_NET_SIO_ECLOK, sio); + err = TLan_GetBit(TLAN_NET_SIO_EDATA, sio); + TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio); + TLan_SetBit(TLAN_NET_SIO_ETXEN, sio); + + if ((!err) && stop) { + TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */ + TLan_SetBit(TLAN_NET_SIO_ECLOK, sio); + TLan_SetBit(TLAN_NET_SIO_EDATA, sio); + } + + return (err); + +} /* TLan_EeSendByte */ + +/*************************************************************** +* TLan_EeReceiveByte +* +* Returns: +* Nothing +* Parms: +* io_base The IO port base address for the +* TLAN device with the EEPROM to +* use. +* data An address to a char to hold the +* data sent from the EEPROM. +* stop If TLAN_EEPROM_STOP is passed, a +* stop cycle is sent after the +* byte is received, and no ack is +* sent. +* +* This function receives 8 bits of data from the EEPROM +* over the serial link. It then sends and ack bit, or no +* ack and a stop bit. This function is used to retrieve +* data after the address of a byte in the EEPROM has been +* sent. +* +**************************************************************/ + +void TLan_EeReceiveByte(u16 io_base, u8 * data, int stop) +{ + u8 place; + u16 sio; + + outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR); + sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO; + *data = 0; + + /* Assume clock is low, tx is enabled; */ + TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio); + for (place = 0x80; place; place >>= 1) { + TLan_SetBit(TLAN_NET_SIO_ECLOK, sio); + if (TLan_GetBit(TLAN_NET_SIO_EDATA, sio)) + *data |= place; + TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio); + } + + TLan_SetBit(TLAN_NET_SIO_ETXEN, sio); + if (!stop) { + TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* Ack = 0 */ + TLan_SetBit(TLAN_NET_SIO_ECLOK, sio); + TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio); + } else { + TLan_SetBit(TLAN_NET_SIO_EDATA, sio); /* No ack = 1 (?) */ + TLan_SetBit(TLAN_NET_SIO_ECLOK, sio); + TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio); + TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */ + TLan_SetBit(TLAN_NET_SIO_ECLOK, sio); + TLan_SetBit(TLAN_NET_SIO_EDATA, sio); + } + +} /* TLan_EeReceiveByte */ + +/*************************************************************** +* TLan_EeReadByte +* +* Returns: +* No error = 0, else, the stage at which the error +* occurred. +* Parms: +* io_base The IO port base address for the +* TLAN device with the EEPROM to +* use. +* ee_addr The address of the byte in the +* EEPROM whose contents are to be +* retrieved. +* data An address to a char to hold the +* data obtained from the EEPROM. +* +* This function reads a byte of information from an byte +* cell in the EEPROM. +* +**************************************************************/ + +int TLan_EeReadByte(u16 io_base, u8 ee_addr, u8 * data) +{ + int err; + int ret = 0; + + + TLan_EeSendStart(io_base); + err = TLan_EeSendByte(io_base, 0xA0, TLAN_EEPROM_ACK); + if (err) { + ret = 1; + goto fail; + } + err = TLan_EeSendByte(io_base, ee_addr, TLAN_EEPROM_ACK); + if (err) { + ret = 2; + goto fail; + } + TLan_EeSendStart(io_base); + err = TLan_EeSendByte(io_base, 0xA1, TLAN_EEPROM_ACK); + if (err) { + ret = 3; + goto fail; + } + TLan_EeReceiveByte(io_base, data, TLAN_EEPROM_STOP); + fail: + + return ret; + +} /* TLan_EeReadByte */ + + +/***************************************************************************** +****************************************************************************** + +ThunderLAN Driver MII Routines + +These routines are based on the information in Chap. 2 of the +"ThunderLAN Programmer's Guide", pp. 15-24. + +****************************************************************************** +*****************************************************************************/ + + +/*************************************************************** +* TLan_MiiReadReg +* +* Returns: +* 0 if ack received ok +* 1 otherwise. +* +* Parms: +* dev The device structure containing +* The io address and interrupt count +* for this device. +* phy The address of the PHY to be queried. +* reg The register whose contents are to be +* retreived. +* val A pointer to a variable to store the +* retrieved value. +* +* This function uses the TLAN's MII bus to retreive the contents +* of a given register on a PHY. It sends the appropriate info +* and then reads the 16-bit register value from the MII bus via +* the TLAN SIO register. +* +**************************************************************/ + +int TLan_MiiReadReg(struct nic *nic __unused, u16 phy, u16 reg, u16 * val) +{ + u8 nack; + u16 sio, tmp; + u32 i; + int err; + int minten; + + err = FALSE; + outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR); + sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO; + + TLan_MiiSync(BASE); + + minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio); + if (minten) + TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio); + + TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */ + TLan_MiiSendData(BASE, 0x2, 2); /* Read ( 10b ) */ + TLan_MiiSendData(BASE, phy, 5); /* Device # */ + TLan_MiiSendData(BASE, reg, 5); /* Register # */ + + + TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio); /* Change direction */ + + TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); /* Clock Idle bit */ + TLan_SetBit(TLAN_NET_SIO_MCLK, sio); + TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); /* Wait 300ns */ + + nack = TLan_GetBit(TLAN_NET_SIO_MDATA, sio); /* Check for ACK */ + TLan_SetBit(TLAN_NET_SIO_MCLK, sio); /* Finish ACK */ + if (nack) { /* No ACK, so fake it */ + for (i = 0; i < 16; i++) { + TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); + TLan_SetBit(TLAN_NET_SIO_MCLK, sio); + } + tmp = 0xffff; + err = TRUE; + } else { /* ACK, so read data */ + for (tmp = 0, i = 0x8000; i; i >>= 1) { + TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); + if (TLan_GetBit(TLAN_NET_SIO_MDATA, sio)) + tmp |= i; + TLan_SetBit(TLAN_NET_SIO_MCLK, sio); + } + } + + + TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); /* Idle cycle */ + TLan_SetBit(TLAN_NET_SIO_MCLK, sio); + + if (minten) + TLan_SetBit(TLAN_NET_SIO_MINTEN, sio); + + *val = tmp; + + return err; + +} /* TLan_MiiReadReg */ + +/*************************************************************** +* TLan_MiiSendData +* +* Returns: +* Nothing +* Parms: +* base_port The base IO port of the adapter in +* question. +* dev The address of the PHY to be queried. +* data The value to be placed on the MII bus. +* num_bits The number of bits in data that are to +* be placed on the MII bus. +* +* This function sends on sequence of bits on the MII +* configuration bus. +* +**************************************************************/ + +void TLan_MiiSendData(u16 base_port, u32 data, unsigned num_bits) +{ + u16 sio; + u32 i; + + if (num_bits == 0) + return; + + outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR); + sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO; + TLan_SetBit(TLAN_NET_SIO_MTXEN, sio); + + for (i = (0x1 << (num_bits - 1)); i; i >>= 1) { + TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); + (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio); + if (data & i) + TLan_SetBit(TLAN_NET_SIO_MDATA, sio); + else + TLan_ClearBit(TLAN_NET_SIO_MDATA, sio); + TLan_SetBit(TLAN_NET_SIO_MCLK, sio); + (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio); + } + +} /* TLan_MiiSendData */ + +/*************************************************************** +* TLan_MiiSync +* +* Returns: +* Nothing +* Parms: +* base_port The base IO port of the adapter in +* question. +* +* This functions syncs all PHYs in terms of the MII configuration +* bus. +* +**************************************************************/ + +void TLan_MiiSync(u16 base_port) +{ + int i; + u16 sio; + + outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR); + sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO; + + TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio); + for (i = 0; i < 32; i++) { + TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); + TLan_SetBit(TLAN_NET_SIO_MCLK, sio); + } + +} /* TLan_MiiSync */ + +/*************************************************************** +* TLan_MiiWriteReg +* +* Returns: +* Nothing +* Parms: +* dev The device structure for the device +* to write to. +* phy The address of the PHY to be written to. +* reg The register whose contents are to be +* written. +* val The value to be written to the register. +* +* This function uses the TLAN's MII bus to write the contents of a +* given register on a PHY. It sends the appropriate info and then +* writes the 16-bit register value from the MII configuration bus +* via the TLAN SIO register. +* +**************************************************************/ + +void TLan_MiiWriteReg(struct nic *nic __unused, u16 phy, u16 reg, u16 val) +{ + u16 sio; + int minten; + + outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR); + sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO; + + TLan_MiiSync(BASE); + + minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio); + if (minten) + TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio); + + TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */ + TLan_MiiSendData(BASE, 0x1, 2); /* Write ( 01b ) */ + TLan_MiiSendData(BASE, phy, 5); /* Device # */ + TLan_MiiSendData(BASE, reg, 5); /* Register # */ + + TLan_MiiSendData(BASE, 0x2, 2); /* Send ACK */ + TLan_MiiSendData(BASE, val, 16); /* Send Data */ + + TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); /* Idle cycle */ + TLan_SetBit(TLAN_NET_SIO_MCLK, sio); + + if (minten) + TLan_SetBit(TLAN_NET_SIO_MINTEN, sio); + + +} /* TLan_MiiWriteReg */ + +/*************************************************************** +* TLan_SetMac +* +* Returns: +* Nothing +* Parms: +* dev Pointer to device structure of adapter +* on which to change the AREG. +* areg The AREG to set the address in (0 - 3). +* mac A pointer to an array of chars. Each +* element stores one byte of the address. +* IE, it isn't in ascii. +* +* This function transfers a MAC address to one of the +* TLAN AREGs (address registers). The TLAN chip locks +* the register on writing to offset 0 and unlocks the +* register after writing to offset 5. If NULL is passed +* in mac, then the AREG is filled with 0's. +* +**************************************************************/ + +void TLan_SetMac(struct nic *nic __unused, int areg, unsigned char *mac) +{ + int i; + + areg *= 6; + + if (mac != NULL) { + for (i = 0; i < 6; i++) + TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i, + mac[i]); + } else { + for (i = 0; i < 6; i++) + TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i, 0); + } + +} /* TLan_SetMac */ + +/********************************************************************* +* TLan_PhyDetect +* +* Returns: +* Nothing +* Parms: +* dev A pointer to the device structure of the adapter +* for which the PHY needs determined. +* +* So far I've found that adapters which have external PHYs +* may also use the internal PHY for part of the functionality. +* (eg, AUI/Thinnet). This function finds out if this TLAN +* chip has an internal PHY, and then finds the first external +* PHY (starting from address 0) if it exists). +* +********************************************************************/ + +void TLan_PhyDetect(struct nic *nic) +{ + u16 control; + u16 hi; + u16 lo; + u32 phy; + + if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) { + priv->phyNum = 0xFFFF; + return; + } + + TLan_MiiReadReg(nic, TLAN_PHY_MAX_ADDR, MII_PHYSID1, &hi); + + if (hi != 0xFFFF) { + priv->phy[0] = TLAN_PHY_MAX_ADDR; + } else { + priv->phy[0] = TLAN_PHY_NONE; + } + + priv->phy[1] = TLAN_PHY_NONE; + for (phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++) { + TLan_MiiReadReg(nic, phy, MII_BMCR, &control); + TLan_MiiReadReg(nic, phy, MII_PHYSID1, &hi); + TLan_MiiReadReg(nic, phy, MII_PHYSID2, &lo); + if ((control != 0xFFFF) || (hi != 0xFFFF) + || (lo != 0xFFFF)) { + printf("PHY found at %hX %hX %hX %hX\n", + (unsigned int) phy, control, hi, lo); + if ((priv->phy[1] == TLAN_PHY_NONE) + && (phy != TLAN_PHY_MAX_ADDR)) { + priv->phy[1] = phy; + } + } + } + + if (priv->phy[1] != TLAN_PHY_NONE) { + priv->phyNum = 1; + } else if (priv->phy[0] != TLAN_PHY_NONE) { + priv->phyNum = 0; + } else { + printf + ("TLAN: Cannot initialize device, no PHY was found!\n"); + } + +} /* TLan_PhyDetect */ + +void TLan_PhyPowerDown(struct nic *nic) +{ + + u16 value; + DBG ( "%s: Powering down PHY(s).\n", priv->nic_name ); + value = BMCR_PDOWN | BMCR_LOOPBACK | BMCR_ISOLATE; + TLan_MiiSync(BASE); + TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_BMCR, value); + if ((priv->phyNum == 0) && (priv->phy[1] != TLAN_PHY_NONE) + && + (!(tlan_pci_tbl[chip_idx]. + flags & TLAN_ADAPTER_USE_INTERN_10))) { + TLan_MiiSync(BASE); + TLan_MiiWriteReg(nic, priv->phy[1], MII_BMCR, value); + } + + /* Wait for 50 ms and powerup + * This is abitrary. It is intended to make sure the + * tranceiver settles. + */ + /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_PUP ); */ + mdelay(50); + TLan_PhyPowerUp(nic); + +} /* TLan_PhyPowerDown */ + + +void TLan_PhyPowerUp(struct nic *nic) +{ + u16 value; + + DBG ( "%s: Powering up PHY.\n", priv->nic_name ); + TLan_MiiSync(BASE); + value = BMCR_LOOPBACK; + TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_BMCR, value); + TLan_MiiSync(BASE); + /* Wait for 500 ms and reset the + * tranceiver. The TLAN docs say both 50 ms and + * 500 ms, so do the longer, just in case. + */ + mdelay(500); + TLan_PhyReset(nic); + /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_RESET ); */ + +} /* TLan_PhyPowerUp */ + +void TLan_PhyReset(struct nic *nic) +{ + u16 phy; + u16 value; + + phy = priv->phy[priv->phyNum]; + + DBG ( "%s: Reseting PHY.\n", priv->nic_name ); + TLan_MiiSync(BASE); + value = BMCR_LOOPBACK | BMCR_RESET; + TLan_MiiWriteReg(nic, phy, MII_BMCR, value); + TLan_MiiReadReg(nic, phy, MII_BMCR, &value); + while (value & BMCR_RESET) { + TLan_MiiReadReg(nic, phy, MII_BMCR, &value); + } + + /* Wait for 500 ms and initialize. + * I don't remember why I wait this long. + * I've changed this to 50ms, as it seems long enough. + */ + /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_START_LINK ); */ + mdelay(50); + TLan_PhyStartLink(nic); + +} /* TLan_PhyReset */ + + +void TLan_PhyStartLink(struct nic *nic) +{ + + u16 ability; + u16 control; + u16 data; + u16 phy; + u16 status; + u16 tctl; + + phy = priv->phy[priv->phyNum]; + DBG ( "%s: Trying to activate link.\n", priv->nic_name ); + TLan_MiiReadReg(nic, phy, MII_BMSR, &status); + TLan_MiiReadReg(nic, phy, MII_BMSR, &ability); + + if ((status & BMSR_ANEGCAPABLE) && (!priv->aui)) { + ability = status >> 11; + if (priv->speed == TLAN_SPEED_10 && + priv->duplex == TLAN_DUPLEX_HALF) { + TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x0000); + } else if (priv->speed == TLAN_SPEED_10 && + priv->duplex == TLAN_DUPLEX_FULL) { + priv->tlanFullDuplex = TRUE; + TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x0100); + } else if (priv->speed == TLAN_SPEED_100 && + priv->duplex == TLAN_DUPLEX_HALF) { + TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x2000); + } else if (priv->speed == TLAN_SPEED_100 && + priv->duplex == TLAN_DUPLEX_FULL) { + priv->tlanFullDuplex = TRUE; + TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x2100); + } else { + + /* Set Auto-Neg advertisement */ + TLan_MiiWriteReg(nic, phy, MII_ADVERTISE, + (ability << 5) | 1); + /* Enablee Auto-Neg */ + TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x1000); + /* Restart Auto-Neg */ + TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x1200); + /* Wait for 4 sec for autonegotiation + * to complete. The max spec time is less than this + * but the card need additional time to start AN. + * .5 sec should be plenty extra. + */ + DBG ( "TLAN: %s: Starting autonegotiation.\n", + priv->nic_name ); + mdelay(4000); + TLan_PhyFinishAutoNeg(nic); + /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_PHY_FINISH_AN ); */ + return; + } + + } + + if ((priv->aui) && (priv->phyNum != 0)) { + priv->phyNum = 0; + data = + TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | + TLAN_NET_CFG_PHY_EN; + TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data); + mdelay(50); + /* TLan_SetTimer( dev, (40*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */ + TLan_PhyPowerDown(nic); + return; + } else if (priv->phyNum == 0) { + control = 0; + TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tctl); + if (priv->aui) { + tctl |= TLAN_TC_AUISEL; + } else { + tctl &= ~TLAN_TC_AUISEL; + if (priv->duplex == TLAN_DUPLEX_FULL) { + control |= BMCR_FULLDPLX; + priv->tlanFullDuplex = TRUE; + } + if (priv->speed == TLAN_SPEED_100) { + control |= BMCR_SPEED100; + } + } + TLan_MiiWriteReg(nic, phy, MII_BMCR, control); + TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tctl); + } + + /* Wait for 2 sec to give the tranceiver time + * to establish link. + */ + /* TLan_SetTimer( dev, (4*HZ), TLAN_TIMER_FINISH_RESET ); */ + mdelay(2000); + TLan_FinishReset(nic); + +} /* TLan_PhyStartLink */ + +void TLan_PhyFinishAutoNeg(struct nic *nic) +{ + + u16 an_adv; + u16 an_lpa; + u16 data; + u16 mode; + u16 phy; + u16 status; + + phy = priv->phy[priv->phyNum]; + + TLan_MiiReadReg(nic, phy, MII_BMSR, &status); + udelay(1000); + TLan_MiiReadReg(nic, phy, MII_BMSR, &status); + + if (!(status & BMSR_ANEGCOMPLETE)) { + /* Wait for 8 sec to give the process + * more time. Perhaps we should fail after a while. + */ + if (!priv->neg_be_verbose++) { + printf + ("TLAN: Giving autonegotiation more time.\n"); + printf + ("TLAN: Please check that your adapter has\n"); + printf + ("TLAN: been properly connected to a HUB or Switch.\n"); + printf + ("TLAN: Trying to establish link in the background...\n"); + } + mdelay(8000); + TLan_PhyFinishAutoNeg(nic); + /* TLan_SetTimer( dev, (8*HZ), TLAN_TIMER_PHY_FINISH_AN ); */ + return; + } + + DBG ( "TLAN: %s: Autonegotiation complete.\n", priv->nic_name ); + TLan_MiiReadReg(nic, phy, MII_ADVERTISE, &an_adv); + TLan_MiiReadReg(nic, phy, MII_LPA, &an_lpa); + mode = an_adv & an_lpa & 0x03E0; + if (mode & 0x0100) { + printf("Full Duplex\n"); + priv->tlanFullDuplex = TRUE; + } else if (!(mode & 0x0080) && (mode & 0x0040)) { + priv->tlanFullDuplex = TRUE; + printf("Full Duplex\n"); + } + + if ((!(mode & 0x0180)) + && (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_USE_INTERN_10) + && (priv->phyNum != 0)) { + priv->phyNum = 0; + data = + TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | + TLAN_NET_CFG_PHY_EN; + TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data); + /* TLan_SetTimer( nic, (400*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */ + mdelay(400); + TLan_PhyPowerDown(nic); + return; + } + + if (priv->phyNum == 0) { + if ((priv->duplex == TLAN_DUPLEX_FULL) + || (an_adv & an_lpa & 0x0040)) { + TLan_MiiWriteReg(nic, phy, MII_BMCR, + BMCR_ANENABLE | BMCR_FULLDPLX); + DBG + ( "TLAN: Starting internal PHY with FULL-DUPLEX\n" ); + } else { + TLan_MiiWriteReg(nic, phy, MII_BMCR, + BMCR_ANENABLE); + DBG + ( "TLAN: Starting internal PHY with HALF-DUPLEX\n" ); + } + } + + /* Wait for 100 ms. No reason in partiticular. + */ + /* TLan_SetTimer( dev, (HZ/10), TLAN_TIMER_FINISH_RESET ); */ + mdelay(100); + TLan_FinishReset(nic); + +} /* TLan_PhyFinishAutoNeg */ + +#ifdef MONITOR + +/********************************************************************* +* +* TLan_phyMonitor +* +* Returns: +* None +* +* Params: +* dev The device structure of this device. +* +* +* This function monitors PHY condition by reading the status +* register via the MII bus. This can be used to give info +* about link changes (up/down), and possible switch to alternate +* media. +* +********************************************************************/ + +void TLan_PhyMonitor(struct net_device *dev) +{ + TLanPrivateInfo *priv = dev->priv; + u16 phy; + u16 phy_status; + + phy = priv->phy[priv->phyNum]; + + /* Get PHY status register */ + TLan_MiiReadReg(nic, phy, MII_BMSR, &phy_status); + + /* Check if link has been lost */ + if (!(phy_status & BMSR_LSTATUS)) { + if (priv->link) { + priv->link = 0; + printf("TLAN: %s has lost link\n", priv->nic_name); + priv->flags &= ~IFF_RUNNING; + mdelay(2000); + TLan_PhyMonitor(nic); + /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */ + return; + } + } + + /* Link restablished? */ + if ((phy_status & BMSR_LSTATUS) && !priv->link) { + priv->link = 1; + printf("TLAN: %s has reestablished link\n", + priv->nic_name); + priv->flags |= IFF_RUNNING; + } + + /* Setup a new monitor */ + /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */ + mdelay(2000); + TLan_PhyMonitor(nic); +} + +#endif /* MONITOR */ + +static struct pci_device_id tlan_nics[] = { + PCI_ROM(0x0e11, 0xae34, "netel10", "Compaq Netelligent 10 T PCI UTP", 0), + PCI_ROM(0x0e11, 0xae32, "netel100","Compaq Netelligent 10/100 TX PCI UTP", 0), + PCI_ROM(0x0e11, 0xae35, "netflex3i", "Compaq Integrated NetFlex-3/P", 0), + PCI_ROM(0x0e11, 0xf130, "thunder", "Compaq NetFlex-3/P", 0), + PCI_ROM(0x0e11, 0xf150, "netflex3b", "Compaq NetFlex-3/P", 0), + PCI_ROM(0x0e11, 0xae43, "netel100pi", "Compaq Netelligent Integrated 10/100 TX UTP", 0), + PCI_ROM(0x0e11, 0xae40, "netel100d", "Compaq Netelligent Dual 10/100 TX PCI UTP", 0), + PCI_ROM(0x0e11, 0xb011, "netel100i", "Compaq Netelligent 10/100 TX Embedded UTP", 0), + PCI_ROM(0x108d, 0x0013, "oc2183", "Olicom OC-2183/2185", 0), + PCI_ROM(0x108d, 0x0012, "oc2325", "Olicom OC-2325", 0), + PCI_ROM(0x108d, 0x0014, "oc2326", "Olicom OC-2326", 0), + PCI_ROM(0x0e11, 0xb030, "netelligent_10_100_ws_5100", "Compaq Netelligent 10/100 TX UTP", 0), + PCI_ROM(0x0e11, 0xb012, "netelligent_10_t2", "Compaq Netelligent 10 T/2 PCI UTP/Coax", 0), +}; + +PCI_DRIVER ( tlan_driver, tlan_nics, PCI_NO_CLASS ); + +DRIVER ( "TLAN/PCI", nic_driver, pci_driver, tlan_driver, + tlan_probe, tlan_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/tlan.h b/debian/grub-extras/disabled/gpxe/src/drivers/net/tlan.h new file mode 100644 index 0000000..31b3c8f --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/tlan.h @@ -0,0 +1,491 @@ +/************************************************************************** +* +* tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN +* Written 2003-2003 by Timothy Legge <tlegge@rogers.com> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +* +* Portions of this code (almost all) based on: +* tlan.c: Linux ThunderLan Driver: +* +* by James Banks +* +* (C) 1997-1998 Caldera, Inc. +* (C) 1998 James Banks +* (C) 1999-2001 Torben Mathiasen +* (C) 2002 Samuel Chessman +* +* REVISION HISTORY: +* ================ +* v1.0 07-08-2003 timlegge Initial not quite working version +* +* Indent Style: indent -kr -i8 +***************************************************************************/ + +FILE_LICENCE ( GPL2_OR_LATER ); + +/***************************************************************** +* TLan Definitions +* +****************************************************************/ + +#define FALSE 0 +#define TRUE 1 + +#define TLAN_MIN_FRAME_SIZE 64 +#define TLAN_MAX_FRAME_SIZE 1600 + +#define TLAN_NUM_RX_LISTS 4 +#define TLAN_NUM_TX_LISTS 2 + +#define TLAN_IGNORE 0 +#define TLAN_RECORD 1 +/* +#define TLAN_DBG(lvl, format, args...) if (debug&lvl) printf("TLAN: " format, ##args ); +*/ +#define TLAN_DEBUG_GNRL 0x0001 +#define TLAN_DEBUG_TX 0x0002 +#define TLAN_DEBUG_RX 0x0004 +#define TLAN_DEBUG_LIST 0x0008 +#define TLAN_DEBUG_PROBE 0x0010 + +#define TX_TIMEOUT (10*HZ) /* We need time for auto-neg */ +#define MAX_TLAN_BOARDS 8 /* Max number of boards installed at a time */ + + + /***************************************************************** + * Device Identification Definitions + * + ****************************************************************/ + +#define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012 +#define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030 +#ifndef PCI_DEVICE_ID_OLICOM_OC2183 +#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 +#endif +#ifndef PCI_DEVICE_ID_OLICOM_OC2325 +#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 +#endif +#ifndef PCI_DEVICE_ID_OLICOM_OC2326 +#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 +#endif + +typedef struct tlan_adapter_entry { + u16 vendorId; + u16 deviceId; + char *deviceLabel; + u32 flags; + u16 addrOfs; +} TLanAdapterEntry; + +#define TLAN_ADAPTER_NONE 0x00000000 +#define TLAN_ADAPTER_UNMANAGED_PHY 0x00000001 +#define TLAN_ADAPTER_BIT_RATE_PHY 0x00000002 +#define TLAN_ADAPTER_USE_INTERN_10 0x00000004 +#define TLAN_ADAPTER_ACTIVITY_LED 0x00000008 + +#define TLAN_SPEED_DEFAULT 0 +#define TLAN_SPEED_10 10 +#define TLAN_SPEED_100 100 + +#define TLAN_DUPLEX_DEFAULT 0 +#define TLAN_DUPLEX_HALF 1 +#define TLAN_DUPLEX_FULL 2 + + + + /***************************************************************** + * EISA Definitions + * + ****************************************************************/ + +#define EISA_ID 0xc80 /* EISA ID Registers */ +#define EISA_ID0 0xc80 /* EISA ID Register 0 */ +#define EISA_ID1 0xc81 /* EISA ID Register 1 */ +#define EISA_ID2 0xc82 /* EISA ID Register 2 */ +#define EISA_ID3 0xc83 /* EISA ID Register 3 */ +#define EISA_CR 0xc84 /* EISA Control Register */ +#define EISA_REG0 0xc88 /* EISA Configuration Register 0 */ +#define EISA_REG1 0xc89 /* EISA Configuration Register 1 */ +#define EISA_REG2 0xc8a /* EISA Configuration Register 2 */ +#define EISA_REG3 0xc8f /* EISA Configuration Register 3 */ +#define EISA_APROM 0xc90 /* Ethernet Address PROM */ + + + + /***************************************************************** + * Rx/Tx List Definitions + * + ****************************************************************/ + +#define TLAN_BUFFERS_PER_LIST 10 +#define TLAN_LAST_BUFFER 0x80000000 +#define TLAN_CSTAT_UNUSED 0x8000 +#define TLAN_CSTAT_FRM_CMP 0x4000 +#define TLAN_CSTAT_READY 0x3000 +#define TLAN_CSTAT_EOC 0x0800 +#define TLAN_CSTAT_RX_ERROR 0x0400 +#define TLAN_CSTAT_PASS_CRC 0x0200 +#define TLAN_CSTAT_DP_PR 0x0100 + + + + + + + /***************************************************************** + * PHY definitions + * + ****************************************************************/ + +#define TLAN_PHY_MAX_ADDR 0x1F +#define TLAN_PHY_NONE 0x20 + + + + /***************************************************************** + * TLan Driver Timer Definitions + * + ****************************************************************/ + +#define TLAN_TIMER_LINK_BEAT 1 +#define TLAN_TIMER_ACTIVITY 2 +#define TLAN_TIMER_PHY_PDOWN 3 +#define TLAN_TIMER_PHY_PUP 4 +#define TLAN_TIMER_PHY_RESET 5 +#define TLAN_TIMER_PHY_START_LINK 6 +#define TLAN_TIMER_PHY_FINISH_AN 7 +#define TLAN_TIMER_FINISH_RESET 8 + +#define TLAN_TIMER_ACT_DELAY (HZ/10) + + + + + /***************************************************************** + * TLan Driver Eeprom Definitions + * + ****************************************************************/ + +#define TLAN_EEPROM_ACK 0 +#define TLAN_EEPROM_STOP 1 + + + + + /***************************************************************** + * Host Register Offsets and Contents + * + ****************************************************************/ + +#define TLAN_HOST_CMD 0x00 +#define TLAN_HC_GO 0x80000000 +#define TLAN_HC_STOP 0x40000000 +#define TLAN_HC_ACK 0x20000000 +#define TLAN_HC_CS_MASK 0x1FE00000 +#define TLAN_HC_EOC 0x00100000 +#define TLAN_HC_RT 0x00080000 +#define TLAN_HC_NES 0x00040000 +#define TLAN_HC_AD_RST 0x00008000 +#define TLAN_HC_LD_TMR 0x00004000 +#define TLAN_HC_LD_THR 0x00002000 +#define TLAN_HC_REQ_INT 0x00001000 +#define TLAN_HC_INT_OFF 0x00000800 +#define TLAN_HC_INT_ON 0x00000400 +#define TLAN_HC_AC_MASK 0x000000FF +#define TLAN_CH_PARM 0x04 +#define TLAN_DIO_ADR 0x08 +#define TLAN_DA_ADR_INC 0x8000 +#define TLAN_DA_RAM_ADR 0x4000 +#define TLAN_HOST_INT 0x0A +#define TLAN_HI_IV_MASK 0x1FE0 +#define TLAN_HI_IT_MASK 0x001C +#define TLAN_DIO_DATA 0x0C + + +/* ThunderLAN Internal Register DIO Offsets */ + +#define TLAN_NET_CMD 0x00 +#define TLAN_NET_CMD_NRESET 0x80 +#define TLAN_NET_CMD_NWRAP 0x40 +#define TLAN_NET_CMD_CSF 0x20 +#define TLAN_NET_CMD_CAF 0x10 +#define TLAN_NET_CMD_NOBRX 0x08 +#define TLAN_NET_CMD_DUPLEX 0x04 +#define TLAN_NET_CMD_TRFRAM 0x02 +#define TLAN_NET_CMD_TXPACE 0x01 +#define TLAN_NET_SIO 0x01 +#define TLAN_NET_SIO_MINTEN 0x80 +#define TLAN_NET_SIO_ECLOK 0x40 +#define TLAN_NET_SIO_ETXEN 0x20 +#define TLAN_NET_SIO_EDATA 0x10 +#define TLAN_NET_SIO_NMRST 0x08 +#define TLAN_NET_SIO_MCLK 0x04 +#define TLAN_NET_SIO_MTXEN 0x02 +#define TLAN_NET_SIO_MDATA 0x01 +#define TLAN_NET_STS 0x02 +#define TLAN_NET_STS_MIRQ 0x80 +#define TLAN_NET_STS_HBEAT 0x40 +#define TLAN_NET_STS_TXSTOP 0x20 +#define TLAN_NET_STS_RXSTOP 0x10 +#define TLAN_NET_STS_RSRVD 0x0F +#define TLAN_NET_MASK 0x03 +#define TLAN_NET_MASK_MASK7 0x80 +#define TLAN_NET_MASK_MASK6 0x40 +#define TLAN_NET_MASK_MASK5 0x20 +#define TLAN_NET_MASK_MASK4 0x10 +#define TLAN_NET_MASK_RSRVD 0x0F +#define TLAN_NET_CONFIG 0x04 +#define TLAN_NET_CFG_RCLK 0x8000 +#define TLAN_NET_CFG_TCLK 0x4000 +#define TLAN_NET_CFG_BIT 0x2000 +#define TLAN_NET_CFG_RXCRC 0x1000 +#define TLAN_NET_CFG_PEF 0x0800 +#define TLAN_NET_CFG_1FRAG 0x0400 +#define TLAN_NET_CFG_1CHAN 0x0200 +#define TLAN_NET_CFG_MTEST 0x0100 +#define TLAN_NET_CFG_PHY_EN 0x0080 +#define TLAN_NET_CFG_MSMASK 0x007F +#define TLAN_MAN_TEST 0x06 +#define TLAN_DEF_VENDOR_ID 0x08 +#define TLAN_DEF_DEVICE_ID 0x0A +#define TLAN_DEF_REVISION 0x0C +#define TLAN_DEF_SUBCLASS 0x0D +#define TLAN_DEF_MIN_LAT 0x0E +#define TLAN_DEF_MAX_LAT 0x0F +#define TLAN_AREG_0 0x10 +#define TLAN_AREG_1 0x16 +#define TLAN_AREG_2 0x1C +#define TLAN_AREG_3 0x22 +#define TLAN_HASH_1 0x28 +#define TLAN_HASH_2 0x2C +#define TLAN_GOOD_TX_FRMS 0x30 +#define TLAN_TX_UNDERUNS 0x33 +#define TLAN_GOOD_RX_FRMS 0x34 +#define TLAN_RX_OVERRUNS 0x37 +#define TLAN_DEFERRED_TX 0x38 +#define TLAN_CRC_ERRORS 0x3A +#define TLAN_CODE_ERRORS 0x3B +#define TLAN_MULTICOL_FRMS 0x3C +#define TLAN_SINGLECOL_FRMS 0x3E +#define TLAN_EXCESSCOL_FRMS 0x40 +#define TLAN_LATE_COLS 0x41 +#define TLAN_CARRIER_LOSS 0x42 +#define TLAN_ACOMMIT 0x43 +#define TLAN_LED_REG 0x44 +#define TLAN_LED_ACT 0x10 +#define TLAN_LED_LINK 0x01 +#define TLAN_BSIZE_REG 0x45 +#define TLAN_MAX_RX 0x46 +#define TLAN_INT_DIS 0x48 +#define TLAN_ID_TX_EOC 0x04 +#define TLAN_ID_RX_EOF 0x02 +#define TLAN_ID_RX_EOC 0x01 + + + +/* ThunderLAN Interrupt Codes */ + +#define TLAN_INT_NUMBER_OF_INTS 8 + +#define TLAN_INT_NONE 0x0000 +#define TLAN_INT_TX_EOF 0x0001 +#define TLAN_INT_STAT_OVERFLOW 0x0002 +#define TLAN_INT_RX_EOF 0x0003 +#define TLAN_INT_DUMMY 0x0004 +#define TLAN_INT_TX_EOC 0x0005 +#define TLAN_INT_STATUS_CHECK 0x0006 +#define TLAN_INT_RX_EOC 0x0007 + + + +/* ThunderLAN MII Registers */ + +/* ThunderLAN Specific MII/PHY Registers */ + +#define TLAN_TLPHY_ID 0x10 +#define TLAN_TLPHY_CTL 0x11 +#define TLAN_TC_IGLINK 0x8000 +#define TLAN_TC_SWAPOL 0x4000 +#define TLAN_TC_AUISEL 0x2000 +#define TLAN_TC_SQEEN 0x1000 +#define TLAN_TC_MTEST 0x0800 +#define TLAN_TC_RESERVED 0x07F8 +#define TLAN_TC_NFEW 0x0004 +#define TLAN_TC_INTEN 0x0002 +#define TLAN_TC_TINT 0x0001 +#define TLAN_TLPHY_STS 0x12 +#define TLAN_TS_MINT 0x8000 +#define TLAN_TS_PHOK 0x4000 +#define TLAN_TS_POLOK 0x2000 +#define TLAN_TS_TPENERGY 0x1000 +#define TLAN_TS_RESERVED 0x0FFF +#define TLAN_TLPHY_PAR 0x19 +#define TLAN_PHY_CIM_STAT 0x0020 +#define TLAN_PHY_SPEED_100 0x0040 +#define TLAN_PHY_DUPLEX_FULL 0x0080 +#define TLAN_PHY_AN_EN_STAT 0x0400 + +/* National Sem. & Level1 PHY id's */ +#define NAT_SEM_ID1 0x2000 +#define NAT_SEM_ID2 0x5C01 +#define LEVEL1_ID1 0x7810 +#define LEVEL1_ID2 0x0000 + +#define CIRC_INC( a, b ) if ( ++a >= b ) a = 0 + +/* Routines to access internal registers. */ + +static inline u8 TLan_DioRead8(u16 base_addr, u16 internal_addr) +{ + outw(internal_addr, base_addr + TLAN_DIO_ADR); + return (inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3))); + +} /* TLan_DioRead8 */ + + + + +static inline u16 TLan_DioRead16(u16 base_addr, u16 internal_addr) +{ + outw(internal_addr, base_addr + TLAN_DIO_ADR); + return (inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2))); + +} /* TLan_DioRead16 */ + + + + +static inline u32 TLan_DioRead32(u16 base_addr, u16 internal_addr) +{ + outw(internal_addr, base_addr + TLAN_DIO_ADR); + return (inl(base_addr + TLAN_DIO_DATA)); + +} /* TLan_DioRead32 */ + + + + +static inline void TLan_DioWrite8(u16 base_addr, u16 internal_addr, u8 data) +{ + outw(internal_addr, base_addr + TLAN_DIO_ADR); + outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3)); + +} + + + + +static inline void TLan_DioWrite16(u16 base_addr, u16 internal_addr, u16 data) +{ + outw(internal_addr, base_addr + TLAN_DIO_ADR); + outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); + +} + + + + +static inline void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data) +{ + outw(internal_addr, base_addr + TLAN_DIO_ADR); + outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); + +} + + + +#if 0 +static inline void TLan_ClearBit(u8 bit, u16 port) +{ + outb_p(inb_p(port) & ~bit, port); +} + + + + +static inline int TLan_GetBit(u8 bit, u16 port) +{ + return ((int) (inb_p(port) & bit)); +} + + + + +static inline void TLan_SetBit(u8 bit, u16 port) +{ + outb_p(inb_p(port) | bit, port); +} +#endif + +#define TLan_ClearBit( bit, port ) outb_p(inb_p(port) & ~bit, port) +#define TLan_GetBit( bit, port ) ((int) (inb_p(port) & bit)) +#define TLan_SetBit( bit, port ) outb_p(inb_p(port) | bit, port) + +#ifdef I_LIKE_A_FAST_HASH_FUNCTION +/* given 6 bytes, view them as 8 6-bit numbers and return the XOR of those */ +/* the code below is about seven times as fast as the original code */ +static inline u32 TLan_HashFunc(u8 * a) +{ + u8 hash; + + hash = (a[0] ^ a[3]); /* & 077 */ + hash ^= ((a[0] ^ a[3]) >> 6); /* & 003 */ + hash ^= ((a[1] ^ a[4]) << 2); /* & 074 */ + hash ^= ((a[1] ^ a[4]) >> 4); /* & 017 */ + hash ^= ((a[2] ^ a[5]) << 4); /* & 060 */ + hash ^= ((a[2] ^ a[5]) >> 2); /* & 077 */ + + return (hash & 077); +} + +#else /* original code */ + +static inline u32 xor(u32 a, u32 b) +{ + return ((a && !b) || (!a && b)); +} + +#define XOR8( a, b, c, d, e, f, g, h ) xor( a, xor( b, xor( c, xor( d, xor( e, xor( f, xor( g, h ) ) ) ) ) ) ) +#define DA( a, bit ) ( ( (u8) a[bit/8] ) & ( (u8) ( 1 << bit%8 ) ) ) + +static inline u32 TLan_HashFunc(u8 * a) +{ + u32 hash; + + hash = + XOR8(DA(a, 0), DA(a, 6), DA(a, 12), DA(a, 18), DA(a, 24), + DA(a, 30), DA(a, 36), DA(a, 42)); + hash |= + XOR8(DA(a, 1), DA(a, 7), DA(a, 13), DA(a, 19), DA(a, 25), + DA(a, 31), DA(a, 37), DA(a, 43)) << 1; + hash |= + XOR8(DA(a, 2), DA(a, 8), DA(a, 14), DA(a, 20), DA(a, 26), + DA(a, 32), DA(a, 38), DA(a, 44)) << 2; + hash |= + XOR8(DA(a, 3), DA(a, 9), DA(a, 15), DA(a, 21), DA(a, 27), + DA(a, 33), DA(a, 39), DA(a, 45)) << 3; + hash |= + XOR8(DA(a, 4), DA(a, 10), DA(a, 16), DA(a, 22), DA(a, 28), + DA(a, 34), DA(a, 40), DA(a, 46)) << 4; + hash |= + XOR8(DA(a, 5), DA(a, 11), DA(a, 17), DA(a, 23), DA(a, 29), + DA(a, 35), DA(a, 41), DA(a, 47)) << 5; + + return hash; + +} + +#endif /* I_LIKE_A_FAST_HASH_FUNCTION */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/tulip.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/tulip.c new file mode 100644 index 0000000..b990586 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/tulip.c @@ -0,0 +1,2098 @@ +/* -*- Mode:C; c-basic-offset:4; -*- */ + +/* + Tulip and clone Etherboot Driver + + By Marty Connor (mdc@etherboot.org) + Copyright (C) 2001 Entity Cyber, Inc. + + This software may be used and distributed according to the terms + of the GNU Public License, incorporated herein by reference. + + As of April 2001 this driver should support most tulip cards that + the Linux tulip driver supports because Donald Becker's Linux media + detection code is now included. + + Based on Ken Yap's Tulip Etherboot Driver and Donald Becker's + Linux Tulip Driver. Supports N-Way speed auto-configuration on + MX98715, MX98715A and MX98725. Support inexpensive PCI 10/100 cards + based on the Macronix MX987x5 chip, such as the SOHOware Fast + model SFA110A, and the LinkSYS model LNE100TX. The NetGear + model FA310X, based on the LC82C168 chip is supported. + The TRENDnet TE100-PCIA NIC which uses a genuine Intel 21143-PD + chipset is supported. Also, Davicom DM9102's. + + Documentation and source code used: + Source for Etherboot driver at + http://etherboot.sourceforge.net/ + MX98715A Data Sheet and MX98715A Application Note + on http://www.macronix.com/ (PDF format files) + Source for Linux tulip driver at + http://cesdis.gsfc.nasa.gov/linux/drivers/tulip.html + + Adapted by Ken Yap from + FreeBSD netboot DEC 21143 driver + Author: David Sharp + date: Nov/98 + + Some code fragments were taken from verious places, Ken Yap's + etherboot, FreeBSD's if_de.c, and various Linux related files. + DEC's manuals for the 21143 and SROM format were very helpful. + The Linux de driver development page has a number of links to + useful related information. Have a look at: + ftp://cesdis.gsfc.nasa.gov/pub/linux/drivers/tulip-devel.html +*/ + +FILE_LICENCE ( GPL_ANY ); + +/*********************************************************************/ +/* Revision History */ +/*********************************************************************/ + +/* + 08 Feb 2005 Ramesh Chander chhabaramesh at yahoo.co.in added table entries + for SGThomson STE10/100A + 07 Sep 2003 timlegge Multicast Support Added + 11 Apr 2001 mdc [patch to etherboot 4.7.24] + Major rewrite to include Linux tulip driver media detection + code. This driver should support a lot more cards now. + 16 Jul 2000 mdc 0.75b11 + Added support for ADMtek 0985 Centaur-P, a "Comet" tulip clone + which is used on the LinkSYS LNE100TX v4.x cards. We already + support LNE100TX v2.0 cards, which use a different controller. + 04 Jul 2000 jam ? + Added test of status after receiving a packet from the card. + Also uncommented the tulip_disable routine. Stray packets + seemed to be causing problems. + 27 Apr 2000 njl ? + 29 Feb 2000 mdc 0.75b7 + Increased reset delay to 3 seconds because Macronix cards seem to + need more reset time before card comes back to a usable state. + 26 Feb 2000 mdc 0.75b6 + Added a 1 second delay after initializing the transmitter because + some cards seem to need the time or they drop the first packet + transmitted. + 23 Feb 2000 mdc 0.75b5 + removed udelay code and used currticks() for more reliable delay + code in reset pause and sanity timeouts. Added function prototypes + and TX debugging code. + 21 Feb 2000 mdc patch to Etherboot 4.4.3 + Incorporated patches from Bob Edwards and Paul Mackerras of + Linuxcare's OZLabs to deal with inefficiencies in tulip_transmit + and udelay. We now wait for packet transmission to complete + (or sanity timeout). + 04 Feb 2000 Robert.Edwards@anu.edu.au patch to Etherboot 4.4.2 + patch to tulip.c that implements the automatic selection of the MII + interface on cards using the Intel/DEC 21143 reference design, in + particular, the TRENDnet TE100-PCIA NIC which uses a genuine Intel + 21143-PD chipset. + 11 Jan 2000 mdc 0.75b4 + Added support for NetGear FA310TX card based on the LC82C168 + chip. This should also support Lite-On LC82C168 boards. + Added simple MII support. Re-arranged code to better modularize + initializations. + 04 Dec 1999 mdc 0.75b3 + Added preliminary support for LNE100TX PCI cards. Should work for + PNIC2 cards. No MII support, but single interface (RJ45) tulip + cards seem to not care. + 03 Dec 1999 mdc 0.75b2 + Renamed from mx987x5 to tulip, merged in original tulip init code + from tulip.c to support other tulip compatible cards. + 02 Dec 1999 mdc 0.75b1 + Released Beta MX987x5 Driver for code review and testing to netboot + and thinguin mailing lists. +*/ + + +/*********************************************************************/ +/* Declarations */ +/*********************************************************************/ + +#include "etherboot.h" +#include "nic.h" + +#include <gpxe/ethernet.h> +#include <gpxe/pci.h> + +/* User settable parameters */ + +#undef TULIP_DEBUG +#undef TULIP_DEBUG_WHERE +#ifdef TULIP_DEBUG +static int tulip_debug = 2; /* 1 normal messages, 0 quiet .. 7 verbose. */ +#endif + +#define TX_TIME_OUT 2*TICKS_PER_SEC + +/* helpful macros if on a big_endian machine for changing byte order. + not strictly needed on Intel */ +#define get_unaligned(ptr) (*(ptr)) +#define put_unaligned(val, ptr) ((void)( *(ptr) = (val) )) +#define get_u16(ptr) (*(u16 *)(ptr)) +#define virt_to_le32desc(addr) virt_to_bus(addr) + +#define TULIP_IOTYPE PCI_USES_MASTER | PCI_USES_IO | PCI_ADDR0 +#define TULIP_SIZE 0x80 + +/* This is a mysterious value that can be written to CSR11 in the 21040 (only) + to support a pre-NWay full-duplex signaling mechanism using short frames. + No one knows what it should be, but if left at its default value some + 10base2(!) packets trigger a full-duplex-request interrupt. */ +#define FULL_DUPLEX_MAGIC 0x6969 + +static const int csr0 = 0x01A00000 | 0x8000; + +/* The possible media types that can be set in options[] are: */ +#define MEDIA_MASK 31 +static const char * const medianame[32] = { + "10baseT", "10base2", "AUI", "100baseTx", + "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx", + "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII", + "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4", + "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19", +}; + +/* This much match tulip_tbl[]! Note 21142 == 21143. */ +enum tulip_chips { + DC21040=0, DC21041=1, DC21140=2, DC21142=3, DC21143=3, + LC82C168, MX98713, MX98715, MX98725, AX88141, AX88140, PNIC2, COMET, + COMPEX9881, I21145, XIRCOM, SGThomson, /*Ramesh Chander*/ +}; + +enum pci_id_flags_bits { + /* Set PCI command register bits before calling probe1(). */ + PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4, + /* Read and map the single following PCI BAR. */ + PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4, + PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400, + PCI_UNUSED_IRQ=0x800, +}; + +struct pci_id_info { + char *name; + struct match_info { + u32 pci, pci_mask, subsystem, subsystem_mask; + u32 revision, revision_mask; /* Only 8 bits. */ + } id; + enum pci_id_flags_bits pci_flags; + int io_size; /* Needed for I/O region check or ioremap(). */ + int drv_flags; /* Driver use, intended as capability flags. */ +}; + +static const struct pci_id_info pci_id_tbl[] = { + { "Digital DC21040 Tulip", { 0x00021011, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 0x80, DC21040 }, + { "Digital DC21041 Tulip", { 0x00141011, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 0x80, DC21041 }, + { "Digital DS21140A Tulip", { 0x00091011, 0xffffffff, 0,0, 0x20,0xf0 }, + TULIP_IOTYPE, 0x80, DC21140 }, + { "Digital DS21140 Tulip", { 0x00091011, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 0x80, DC21140 }, + { "Digital DS21143 Tulip", { 0x00191011, 0xffffffff, 0,0, 65,0xff }, + TULIP_IOTYPE, TULIP_SIZE, DC21142 }, + { "Digital DS21142 Tulip", { 0x00191011, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, TULIP_SIZE, DC21142 }, + { "Kingston KNE110tx (PNIC)", { 0x000211AD, 0xffffffff, 0xf0022646, 0xffffffff, 0, 0 }, + TULIP_IOTYPE, 256, LC82C168 }, + { "Lite-On 82c168 PNIC", { 0x000211AD, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 256, LC82C168 }, + { "Macronix 98713 PMAC", { 0x051210d9, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 256, MX98713 }, + { "Macronix 98715 PMAC", { 0x053110d9, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 256, MX98715 }, + { "Macronix 98725 PMAC", { 0x053110d9, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 256, MX98725 }, + { "ASIX AX88141", { 0x1400125B, 0xffffffff, 0,0, 0x10, 0xf0 }, + TULIP_IOTYPE, 128, AX88141 }, + { "ASIX AX88140", { 0x1400125B, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 128, AX88140 }, + { "Lite-On LC82C115 PNIC-II", { 0xc11511AD, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 256, PNIC2 }, + { "ADMtek AN981 Comet", { 0x09811317, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 256, COMET }, + { "ADMTek AN983 Comet", { 0x12161113, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 256, COMET }, + { "ADMTek Comet AN983b", { 0x95111317, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 256, COMET }, + { "ADMtek Centaur-P", { 0x09851317, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 256, COMET }, + { "ADMtek Centaur-C", { 0x19851317, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 256, COMET }, + { "Compex RL100-TX", { 0x988111F6, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 128, COMPEX9881 }, + { "Intel 21145 Tulip", { 0x00398086, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 128, I21145 }, + { "Xircom Tulip clone", { 0x0003115d, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 128, XIRCOM }, + { "Davicom DM9102", { 0x91021282, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 0x80, DC21140 }, + { "Davicom DM9100", { 0x91001282, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 0x80, DC21140 }, + { "Macronix mxic-98715 (EN1217)", { 0x12171113, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 256, MX98715 }, + { "3Com 3cSOHO100B-TX (ADMtek Centuar)", { 0x930010b7, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, TULIP_SIZE, COMET }, + { "SG Thomson STE10/100A", { 0x2774104a, 0xffffffff, 0, 0, 0, 0 }, + TULIP_IOTYPE, 256, COMET }, /*Ramesh Chander*/ + { 0, { 0, 0, 0, 0, 0, 0 }, 0, 0, 0 }, +}; + +enum tbl_flag { + HAS_MII=1, HAS_MEDIA_TABLE=2, CSR12_IN_SROM=4, ALWAYS_CHECK_MII=8, + HAS_PWRDWN=0x10, MC_HASH_ONLY=0x20, /* Hash-only multicast filter. */ + HAS_PNICNWAY=0x80, HAS_NWAY=0x40, /* Uses internal NWay xcvr. */ + HAS_INTR_MITIGATION=0x100, IS_ASIX=0x200, HAS_8023X=0x400, +}; + +/* Note: this table must match enum tulip_chips above. */ +static struct tulip_chip_table { + char *chip_name; + int flags; +} tulip_tbl[] = { + { "Digital DC21040 Tulip", 0}, + { "Digital DC21041 Tulip", HAS_MEDIA_TABLE | HAS_NWAY }, + { "Digital DS21140 Tulip", HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM }, + { "Digital DS21143 Tulip", HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII + | HAS_PWRDWN | HAS_NWAY | HAS_INTR_MITIGATION }, + { "Lite-On 82c168 PNIC", HAS_MII | HAS_PNICNWAY }, + { "Macronix 98713 PMAC", HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM }, + { "Macronix 98715 PMAC", HAS_MEDIA_TABLE }, + { "Macronix 98725 PMAC", HAS_MEDIA_TABLE }, + { "ASIX AX88140", HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM + | MC_HASH_ONLY | IS_ASIX }, + { "ASIX AX88141", HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY + | IS_ASIX }, + { "Lite-On PNIC-II", HAS_MII | HAS_NWAY | HAS_8023X }, + { "ADMtek Comet", HAS_MII | MC_HASH_ONLY }, + { "Compex 9881 PMAC", HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM }, + { "Intel DS21145 Tulip", HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII + | HAS_PWRDWN | HAS_NWAY }, + { "Xircom tulip work-alike", HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII + | HAS_PWRDWN | HAS_NWAY }, + { "SGThomson STE10/100A", HAS_MII | MC_HASH_ONLY }, /*Ramesh Chander*/ + { 0, 0 }, +}; + +/* A full-duplex map for media types. */ +enum MediaIs { + MediaIsFD = 1, MediaAlwaysFD=2, MediaIsMII=4, MediaIsFx=8, + MediaIs100=16}; + +static const char media_cap[32] = +{0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 20,31,0,0, }; +static u8 t21040_csr13[] = {2,0x0C,8,4, 4,0,0,0, 0,0,0,0, 4,0,0,0}; + +/* 21041 transceiver register settings: 10-T, 10-2, AUI, 10-T, 10T-FD */ +static u16 t21041_csr13[] = { 0xEF01, 0xEF09, 0xEF09, 0xEF01, 0xEF09, }; +static u16 t21041_csr14[] = { 0xFFFF, 0xF7FD, 0xF7FD, 0x7F3F, 0x7F3D, }; +static u16 t21041_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, }; + +/* not used +static u16 t21142_csr13[] = { 0x0001, 0x0009, 0x0009, 0x0000, 0x0001, }; +*/ +static u16 t21142_csr14[] = { 0xFFFF, 0x0705, 0x0705, 0x0000, 0x7F3D, }; +/* not used +static u16 t21142_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, }; +*/ + +/* Offsets to the Command and Status Registers, "CSRs". All accesses + must be longword instructions and quadword aligned. */ +enum tulip_offsets { + CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, + CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58, + CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0 +}; + +/* The bits in the CSR5 status registers, mostly interrupt sources. */ +enum status_bits { + TimerInt=0x800, TPLnkFail=0x1000, TPLnkPass=0x10, + NormalIntr=0x10000, AbnormalIntr=0x8000, + RxJabber=0x200, RxDied=0x100, RxNoBuf=0x80, RxIntr=0x40, + TxFIFOUnderflow=0x20, TxJabber=0x08, TxNoBuf=0x04, TxDied=0x02, TxIntr=0x01, +}; + +/* The configuration bits in CSR6. */ +enum csr6_mode_bits { + TxOn=0x2000, RxOn=0x0002, FullDuplex=0x0200, + AcceptBroadcast=0x0100, AcceptAllMulticast=0x0080, + AcceptAllPhys=0x0040, AcceptRunt=0x0008, +}; + + +enum desc_status_bits { + DescOwnded=0x80000000, RxDescFatalErr=0x8000, RxWholePkt=0x0300, +}; + +struct medialeaf { + u8 type; + u8 media; + unsigned char *leafdata; +}; + +struct mediatable { + u16 defaultmedia; + u8 leafcount, csr12dir; /* General purpose pin directions. */ + unsigned has_mii:1, has_nonmii:1, has_reset:6; + u32 csr15dir, csr15val; /* 21143 NWay setting. */ + struct medialeaf mleaf[0]; +}; + +struct mediainfo { + struct mediainfo *next; + int info_type; + int index; + unsigned char *info; +}; + +/* EEPROM Address width definitions */ +#define EEPROM_ADDRLEN 6 +#define EEPROM_SIZE 128 /* 2 << EEPROM_ADDRLEN */ + +/* The EEPROM commands include the alway-set leading bit. */ +#define EE_WRITE_CMD (5 << addr_len) +#define EE_READ_CMD (6 << addr_len) +#define EE_ERASE_CMD (7 << addr_len) + +/* EEPROM_Ctrl bits. */ +#define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */ +#define EE_CS 0x01 /* EEPROM chip select. */ +#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ +#define EE_WRITE_0 0x01 +#define EE_WRITE_1 0x05 +#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ +#define EE_ENB (0x4800 | EE_CS) + +/* Delay between EEPROM clock transitions. Even at 33Mhz current PCI + implementations don't overrun the EEPROM clock. We add a bus + turn-around to insure that this remains true. */ +#define eeprom_delay() inl(ee_addr) + +/* Size of transmit and receive buffers */ +#define BUFLEN 1536 + +/* Ring-wrap flag in length field, use for last ring entry. + 0x01000000 means chain on buffer2 address, + 0x02000000 means use the ring start address in CSR2/3. + Note: Some work-alike chips do not function correctly in chained mode. + The ASIX chip works only in chained mode. + Thus we indicate ring mode, but always write the 'next' field for + chained mode as well. */ +#define DESC_RING_WRAP 0x02000000 + +/* transmit and receive descriptor format */ +struct tulip_rx_desc { + volatile u32 status; + u32 length; + u32 buffer1, buffer2; +}; + +struct tulip_tx_desc { + volatile u32 status; + u32 length; + u32 buffer1, buffer2; +}; + +/*********************************************************************/ +/* Global Storage */ +/*********************************************************************/ + +static u32 ioaddr; + +struct tulip_private { + int cur_rx; + int chip_id; /* index into tulip_tbl[] */ + int pci_id_idx; /* index into pci_id_tbl[] */ + int revision; + int flags; + unsigned short vendor_id; /* PCI card vendor code */ + unsigned short dev_id; /* PCI card device code */ + unsigned char ehdr[ETH_HLEN]; /* buffer for ethernet header */ + const char *nic_name; + unsigned int csr0, csr6; /* Current CSR0, CSR6 settings. */ + unsigned int if_port; + unsigned int full_duplex; /* Full-duplex operation requested. */ + unsigned int full_duplex_lock; + unsigned int medialock; /* Do not sense media type. */ + unsigned int mediasense; /* Media sensing in progress. */ + unsigned int nway, nwayset; /* 21143 internal NWay. */ + unsigned int default_port; + unsigned char eeprom[EEPROM_SIZE]; /* Serial EEPROM contents. */ + u8 media_table_storage[(sizeof(struct mediatable) + 32*sizeof(struct medialeaf))]; + u16 sym_advertise, mii_advertise; /* NWay to-advertise. */ + struct mediatable *mtable; + u16 lpar; /* 21143 Link partner ability. */ + u16 advertising[4]; /* MII advertise, from SROM table. */ + signed char phys[4], mii_cnt; /* MII device addresses. */ + int cur_index; /* Current media index. */ + int saved_if_port; +}; + +/* Note: transmit and receive buffers must be longword aligned and + longword divisable */ + +#define TX_RING_SIZE 2 +#define RX_RING_SIZE 4 +struct { + struct tulip_tx_desc tx_ring[TX_RING_SIZE]; + unsigned char txb[BUFLEN]; + struct tulip_rx_desc rx_ring[RX_RING_SIZE]; + unsigned char rxb[RX_RING_SIZE * BUFLEN]; + struct tulip_private tpx; +} tulip_bss __shared __attribute__ ((aligned(4))); +#define tx_ring tulip_bss.tx_ring +#define txb tulip_bss.txb +#define rx_ring tulip_bss.rx_ring +#define rxb tulip_bss.rxb + +static struct tulip_private *tp; + +/* Known cards that have old-style EEPROMs. + Writing this table is described at + http://cesdis.gsfc.nasa.gov/linux/drivers/tulip-drivers/tulip-media.html */ +static struct fixups { + char *name; + unsigned char addr0, addr1, addr2; + u16 newtable[32]; /* Max length below. */ +} eeprom_fixups[] = { + {"Asante", 0, 0, 0x94, {0x1e00, 0x0000, 0x0800, 0x0100, 0x018c, + 0x0000, 0x0000, 0xe078, 0x0001, 0x0050, 0x0018 }}, + {"SMC9332DST", 0, 0, 0xC0, { 0x1e00, 0x0000, 0x0800, 0x041f, + 0x0000, 0x009E, /* 10baseT */ + 0x0004, 0x009E, /* 10baseT-FD */ + 0x0903, 0x006D, /* 100baseTx */ + 0x0905, 0x006D, /* 100baseTx-FD */ }}, + {"Cogent EM100", 0, 0, 0x92, { 0x1e00, 0x0000, 0x0800, 0x063f, + 0x0107, 0x8021, /* 100baseFx */ + 0x0108, 0x8021, /* 100baseFx-FD */ + 0x0100, 0x009E, /* 10baseT */ + 0x0104, 0x009E, /* 10baseT-FD */ + 0x0103, 0x006D, /* 100baseTx */ + 0x0105, 0x006D, /* 100baseTx-FD */ }}, + {"Maxtech NX-110", 0, 0, 0xE8, { 0x1e00, 0x0000, 0x0800, 0x0513, + 0x1001, 0x009E, /* 10base2, CSR12 0x10*/ + 0x0000, 0x009E, /* 10baseT */ + 0x0004, 0x009E, /* 10baseT-FD */ + 0x0303, 0x006D, /* 100baseTx, CSR12 0x03 */ + 0x0305, 0x006D, /* 100baseTx-FD CSR12 0x03 */}}, + {"Accton EN1207", 0, 0, 0xE8, { 0x1e00, 0x0000, 0x0800, 0x051F, + 0x1B01, 0x0000, /* 10base2, CSR12 0x1B */ + 0x0B00, 0x009E, /* 10baseT, CSR12 0x0B */ + 0x0B04, 0x009E, /* 10baseT-FD,CSR12 0x0B */ + 0x1B03, 0x006D, /* 100baseTx, CSR12 0x1B */ + 0x1B05, 0x006D, /* 100baseTx-FD CSR12 0x1B */ + }}, + {0, 0, 0, 0, {}}}; + +static const char * block_name[] = {"21140 non-MII", "21140 MII PHY", + "21142 Serial PHY", "21142 MII PHY", "21143 SYM PHY", "21143 reset method"}; + + +/*********************************************************************/ +/* Function Prototypes */ +/*********************************************************************/ +static int mdio_read(struct nic *nic, int phy_id, int location); +static void mdio_write(struct nic *nic, int phy_id, int location, int value); +static int read_eeprom(unsigned long ioaddr, int location, int addr_len); +static void parse_eeprom(struct nic *nic); +static int tulip_probe(struct nic *nic,struct pci_device *pci); +static void tulip_init_ring(struct nic *nic); +static void tulip_reset(struct nic *nic); +static void tulip_transmit(struct nic *nic, const char *d, unsigned int t, + unsigned int s, const char *p); +static int tulip_poll(struct nic *nic, int retrieve); +static void tulip_disable(struct nic *nic); +static void nway_start(struct nic *nic); +static void pnic_do_nway(struct nic *nic); +static void select_media(struct nic *nic, int startup); +static void init_media(struct nic *nic); +static void start_link(struct nic *nic); +static int tulip_check_duplex(struct nic *nic); + +static void tulip_wait(unsigned int nticks); + +#ifdef TULIP_DEBUG_WHERE +static void whereami(const char *str); +#endif + +#ifdef TULIP_DEBUG +static void tulip_more(void); +#endif + + +/*********************************************************************/ +/* Utility Routines */ +/*********************************************************************/ + +#ifdef TULIP_DEBUG_WHERE +static void whereami (const char *str, struct pci_device *pci) +{ + printf("%s: %s\n", tp->nic_name, str); + /* sleep(2); */ +} +#endif + +#ifdef TULIP_DEBUG +static void tulip_more(void) +{ + printf("\n\n-- more --"); + while (!iskey()) + /* wait */; + getchar(); + printf("\n\n"); +} +#endif /* TULIP_DEBUG */ + +static void tulip_wait(unsigned int nticks) +{ + unsigned int to = currticks() + nticks; + while (currticks() < to) + /* wait */ ; +} + + +/*********************************************************************/ +/* Media Descriptor Code */ +/*********************************************************************/ + +/* MII transceiver control section. + Read and write the MII registers using software-generated serial + MDIO protocol. See the MII specifications or DP83840A data sheet + for details. */ + +/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually + met by back-to-back PCI I/O cycles, but we insert a delay to avoid + "overclocking" issues or future 66Mhz PCI. */ +#define mdio_delay() inl(mdio_addr) + +/* Read and write the MII registers using software-generated serial + MDIO protocol. It is just different enough from the EEPROM protocol + to not share code. The maxium data clock rate is 2.5 Mhz. */ +#define MDIO_SHIFT_CLK 0x10000 +#define MDIO_DATA_WRITE0 0x00000 +#define MDIO_DATA_WRITE1 0x20000 +#define MDIO_ENB 0x00000 /* Ignore the 0x02000 databook setting. */ +#define MDIO_ENB_IN 0x40000 +#define MDIO_DATA_READ 0x80000 + +/* MII transceiver control section. + Read and write the MII registers using software-generated serial + MDIO protocol. See the MII specifications or DP83840A data sheet + for details. */ + +int mdio_read(struct nic *nic __unused, int phy_id, int location) +{ + int i; + int read_cmd = (0xf6 << 10) | (phy_id << 5) | location; + int retval = 0; + long mdio_addr = ioaddr + CSR9; + +#ifdef TULIP_DEBUG_WHERE + whereami("mdio_read\n"); +#endif + + if (tp->chip_id == LC82C168) { + int i = 1000; + outl(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0); + inl(ioaddr + 0xA0); + inl(ioaddr + 0xA0); + while (--i > 0) + if ( ! ((retval = inl(ioaddr + 0xA0)) & 0x80000000)) + return retval & 0xffff; + return 0xffff; + } + + if (tp->chip_id == COMET) { + if (phy_id == 1) { + if (location < 7) + return inl(ioaddr + 0xB4 + (location<<2)); + else if (location == 17) + return inl(ioaddr + 0xD0); + else if (location >= 29 && location <= 31) + return inl(ioaddr + 0xD4 + ((location-29)<<2)); + } + return 0xffff; + } + + /* Establish sync by sending at least 32 logic ones. */ + for (i = 32; i >= 0; i--) { + outl(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr); + mdio_delay(); + outl(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr); + mdio_delay(); + } + /* Shift the read command bits out. */ + for (i = 15; i >= 0; i--) { + int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0; + + outl(MDIO_ENB | dataval, mdio_addr); + mdio_delay(); + outl(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr); + mdio_delay(); + } + /* Read the two transition, 16 data, and wire-idle bits. */ + for (i = 19; i > 0; i--) { + outl(MDIO_ENB_IN, mdio_addr); + mdio_delay(); + retval = (retval << 1) | ((inl(mdio_addr) & MDIO_DATA_READ) ? 1 : 0); + outl(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); + mdio_delay(); + } + return (retval>>1) & 0xffff; +} + +void mdio_write(struct nic *nic __unused, int phy_id, int location, int value) +{ + int i; + int cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value; + long mdio_addr = ioaddr + CSR9; + +#ifdef TULIP_DEBUG_WHERE + whereami("mdio_write\n"); +#endif + + if (tp->chip_id == LC82C168) { + int i = 1000; + outl(cmd, ioaddr + 0xA0); + do + if ( ! (inl(ioaddr + 0xA0) & 0x80000000)) + break; + while (--i > 0); + return; + } + + if (tp->chip_id == COMET) { + if (phy_id != 1) + return; + if (location < 7) + outl(value, ioaddr + 0xB4 + (location<<2)); + else if (location == 17) + outl(value, ioaddr + 0xD0); + else if (location >= 29 && location <= 31) + outl(value, ioaddr + 0xD4 + ((location-29)<<2)); + return; + } + + /* Establish sync by sending 32 logic ones. */ + for (i = 32; i >= 0; i--) { + outl(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr); + mdio_delay(); + outl(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr); + mdio_delay(); + } + /* Shift the command bits out. */ + for (i = 31; i >= 0; i--) { + int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0; + outl(MDIO_ENB | dataval, mdio_addr); + mdio_delay(); + outl(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr); + mdio_delay(); + } + /* Clear out extra bits. */ + for (i = 2; i > 0; i--) { + outl(MDIO_ENB_IN, mdio_addr); + mdio_delay(); + outl(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); + mdio_delay(); + } +} + + +/*********************************************************************/ +/* EEPROM Reading Code */ +/*********************************************************************/ +/* EEPROM routines adapted from the Linux Tulip Code */ +/* Reading a serial EEPROM is a "bit" grungy, but we work our way + through:->. +*/ +static int read_eeprom(unsigned long ioaddr, int location, int addr_len) +{ + int i; + unsigned short retval = 0; + long ee_addr = ioaddr + CSR9; + int read_cmd = location | EE_READ_CMD; + +#ifdef TULIP_DEBUG_WHERE + whereami("read_eeprom\n"); +#endif + + outl(EE_ENB & ~EE_CS, ee_addr); + outl(EE_ENB, ee_addr); + + /* Shift the read command bits out. */ + for (i = 4 + addr_len; i >= 0; i--) { + short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + outl(EE_ENB | dataval, ee_addr); + eeprom_delay(); + outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); + eeprom_delay(); + } + outl(EE_ENB, ee_addr); + + for (i = 16; i > 0; i--) { + outl(EE_ENB | EE_SHIFT_CLK, ee_addr); + eeprom_delay(); + retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0); + outl(EE_ENB, ee_addr); + eeprom_delay(); + } + + /* Terminate the EEPROM access. */ + outl(EE_ENB & ~EE_CS, ee_addr); + return retval; +} + + +/*********************************************************************/ +/* EEPROM Parsing Code */ +/*********************************************************************/ +static void parse_eeprom(struct nic *nic) +{ + unsigned char *p, *ee_data = tp->eeprom; + int new_advertise = 0; + int i; + +#ifdef TULIP_DEBUG_WHERE + whereami("parse_eeprom\n"); +#endif + + tp->mtable = 0; + /* Detect an old-style (SA only) EEPROM layout: + memcmp(ee_data, ee_data+16, 8). */ + for (i = 0; i < 8; i ++) + if (ee_data[i] != ee_data[16+i]) + break; + if (i >= 8) { + /* Do a fix-up based on the vendor half of the station address. */ + for (i = 0; eeprom_fixups[i].name; i++) { + if (nic->node_addr[0] == eeprom_fixups[i].addr0 + && nic->node_addr[1] == eeprom_fixups[i].addr1 + && nic->node_addr[2] == eeprom_fixups[i].addr2) { + if (nic->node_addr[2] == 0xE8 && ee_data[0x1a] == 0x55) + i++; /* An Accton EN1207, not an outlaw Maxtech. */ + memcpy(ee_data + 26, eeprom_fixups[i].newtable, + sizeof(eeprom_fixups[i].newtable)); +#ifdef TULIP_DEBUG + printf("%s: Old format EEPROM on '%s' board.\n%s: Using substitute media control info.\n", + tp->nic_name, eeprom_fixups[i].name, tp->nic_name); +#endif + break; + } + } + if (eeprom_fixups[i].name == NULL) { /* No fixup found. */ +#ifdef TULIP_DEBUG + printf("%s: Old style EEPROM with no media selection information.\n", + tp->nic_name); +#endif + return; + } + } + + if (ee_data[19] > 1) { +#ifdef TULIP_DEBUG + printf("%s: Multiport cards (%d ports) may not work correctly.\n", + tp->nic_name, ee_data[19]); +#endif + } + + p = (void *)ee_data + ee_data[27]; + + if (ee_data[27] == 0) { /* No valid media table. */ +#ifdef TULIP_DEBUG + if (tulip_debug > 1) { + printf("%s: No Valid Media Table. ee_data[27] = %hhX\n", + tp->nic_name, ee_data[27]); + } +#endif + } else if (tp->chip_id == DC21041) { + int media = get_u16(p); + int count = p[2]; + p += 3; + + printf("%s: 21041 Media table, default media %hX (%s).\n", + tp->nic_name, media, + media & 0x0800 ? "Autosense" : medianame[media & 15]); + for (i = 0; i < count; i++) { + unsigned char media_block = *p++; + int media_code = media_block & MEDIA_MASK; + if (media_block & 0x40) + p += 6; + switch(media_code) { + case 0: new_advertise |= 0x0020; break; + case 4: new_advertise |= 0x0040; break; + } + printf("%s: 21041 media #%d, %s.\n", + tp->nic_name, media_code, medianame[media_code]); + } + } else { + unsigned char csr12dir = 0; + int count; + struct mediatable *mtable; + u16 media = get_u16(p); + + p += 2; + if (tp->flags & CSR12_IN_SROM) + csr12dir = *p++; + count = *p++; + + tp->mtable = mtable = (struct mediatable *)&tp->media_table_storage[0]; + + mtable->defaultmedia = media; + mtable->leafcount = count; + mtable->csr12dir = csr12dir; + mtable->has_nonmii = mtable->has_mii = mtable->has_reset = 0; + mtable->csr15dir = mtable->csr15val = 0; + + printf("%s: EEPROM default media type %s.\n", tp->nic_name, + media & 0x0800 ? "Autosense" : medianame[media & MEDIA_MASK]); + + for (i = 0; i < count; i++) { + struct medialeaf *leaf = &mtable->mleaf[i]; + + if ((p[0] & 0x80) == 0) { /* 21140 Compact block. */ + leaf->type = 0; + leaf->media = p[0] & 0x3f; + leaf->leafdata = p; + if ((p[2] & 0x61) == 0x01) /* Bogus, but Znyx boards do it. */ + mtable->has_mii = 1; + p += 4; + } else { + switch(leaf->type = p[1]) { + case 5: + mtable->has_reset = i; + leaf->media = p[2] & 0x0f; + break; + case 1: case 3: + mtable->has_mii = 1; + leaf->media = 11; + break; + case 2: + if ((p[2] & 0x3f) == 0) { + u32 base15 = (p[2] & 0x40) ? get_u16(p + 7) : 0x0008; + u16 *p1 = (u16 *)(p + (p[2] & 0x40 ? 9 : 3)); + mtable->csr15dir = (get_unaligned(p1 + 0)<<16) + base15; + mtable->csr15val = (get_unaligned(p1 + 1)<<16) + base15; + } + /* Fall through. */ + case 0: case 4: + mtable->has_nonmii = 1; + leaf->media = p[2] & MEDIA_MASK; + switch (leaf->media) { + case 0: new_advertise |= 0x0020; break; + case 4: new_advertise |= 0x0040; break; + case 3: new_advertise |= 0x0080; break; + case 5: new_advertise |= 0x0100; break; + case 6: new_advertise |= 0x0200; break; + } + break; + default: + leaf->media = 19; + } + leaf->leafdata = p + 2; + p += (p[0] & 0x3f) + 1; + } +#ifdef TULIP_DEBUG + if (tulip_debug > 1 && leaf->media == 11) { + unsigned char *bp = leaf->leafdata; + printf("%s: MII interface PHY %d, setup/reset sequences %d/%d long, capabilities %hhX %hhX.\n", + tp->nic_name, bp[0], bp[1], bp[2 + bp[1]*2], + bp[5 + bp[2 + bp[1]*2]*2], bp[4 + bp[2 + bp[1]*2]*2]); + } +#endif + printf("%s: Index #%d - Media %s (#%d) described " + "by a %s (%d) block.\n", + tp->nic_name, i, medianame[leaf->media], leaf->media, + leaf->type < 6 ? block_name[leaf->type] : "UNKNOWN", + leaf->type); + } + if (new_advertise) + tp->sym_advertise = new_advertise; + } +} + + +/*********************************************************************/ +/* tulip_init_ring - setup the tx and rx descriptors */ +/*********************************************************************/ +static void tulip_init_ring(struct nic *nic __unused) +{ + int i; + +#ifdef TULIP_DEBUG_WHERE + whereami("tulip_init_ring\n"); +#endif + + tp->cur_rx = 0; + + for (i = 0; i < RX_RING_SIZE; i++) { + rx_ring[i].status = cpu_to_le32(0x80000000); + rx_ring[i].length = cpu_to_le32(BUFLEN); + rx_ring[i].buffer1 = virt_to_le32desc(&rxb[i * BUFLEN]); + rx_ring[i].buffer2 = virt_to_le32desc(&rx_ring[i+1]); + } + /* Mark the last entry as wrapping the ring. */ + rx_ring[i-1].length = cpu_to_le32(DESC_RING_WRAP | BUFLEN); + rx_ring[i-1].buffer2 = virt_to_le32desc(&rx_ring[0]); + + /* We only use 1 transmit buffer, but we use 2 descriptors so + transmit engines have somewhere to point to if they feel the need */ + + tx_ring[0].status = 0x00000000; + tx_ring[0].buffer1 = virt_to_le32desc(&txb[0]); + tx_ring[0].buffer2 = virt_to_le32desc(&tx_ring[1]); + + /* this descriptor should never get used, since it will never be owned + by the machine (status will always == 0) */ + tx_ring[1].status = 0x00000000; + tx_ring[1].buffer1 = virt_to_le32desc(&txb[0]); + tx_ring[1].buffer2 = virt_to_le32desc(&tx_ring[0]); + + /* Mark the last entry as wrapping the ring, though this should never happen */ + tx_ring[1].length = cpu_to_le32(DESC_RING_WRAP | BUFLEN); +} + + +static void set_rx_mode(struct nic *nic __unused) { + int csr6 = inl(ioaddr + CSR6) & ~0x00D5; + + tp->csr6 &= ~0x00D5; + + /* !IFF_PROMISC */ + tp->csr6 |= AcceptAllMulticast; + csr6 |= AcceptAllMulticast; + + outl(csr6, ioaddr + CSR6); + + + +} + +/*********************************************************************/ +/* eth_reset - Reset adapter */ +/*********************************************************************/ +static void tulip_reset(struct nic *nic) +{ + int i; + unsigned long to; + +#ifdef TULIP_DEBUG_WHERE + whereami("tulip_reset\n"); +#endif + + /* Stop Tx and RX */ + outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); + + /* On some chip revs we must set the MII/SYM port before the reset!? */ + if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii)) { + outl(0x814C0000, ioaddr + CSR6); + } + + /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ + outl(0x00000001, ioaddr + CSR0); + tulip_wait(1); + + /* turn off reset and set cache align=16lword, burst=unlimit */ + outl(tp->csr0, ioaddr + CSR0); + + /* Wait the specified 50 PCI cycles after a reset */ + tulip_wait(1); + + /* set up transmit and receive descriptors */ + tulip_init_ring(nic); + + if (tp->chip_id == PNIC2) { + u32 addr_high = (nic->node_addr[1]<<8) + (nic->node_addr[0]<<0); + /* This address setting does not appear to impact chip operation?? */ + outl((nic->node_addr[5]<<8) + nic->node_addr[4] + + (nic->node_addr[3]<<24) + (nic->node_addr[2]<<16), + ioaddr + 0xB0); + outl(addr_high + (addr_high<<16), ioaddr + 0xB8); + } + + /* MC_HASH_ONLY boards don't support setup packets */ + if (tp->flags & MC_HASH_ONLY) { + u32 addr_low = cpu_to_le32(get_unaligned((u32 *)nic->node_addr)); + u32 addr_high = cpu_to_le32(get_unaligned((u16 *)(nic->node_addr+4))); + + /* clear multicast hash filters and setup MAC address filters */ + if (tp->flags & IS_ASIX) { + outl(0, ioaddr + CSR13); + outl(addr_low, ioaddr + CSR14); + outl(1, ioaddr + CSR13); + outl(addr_high, ioaddr + CSR14); + outl(2, ioaddr + CSR13); + outl(0, ioaddr + CSR14); + outl(3, ioaddr + CSR13); + outl(0, ioaddr + CSR14); + } else if (tp->chip_id == COMET) { + outl(addr_low, ioaddr + 0xA4); + outl(addr_high, ioaddr + 0xA8); + outl(0, ioaddr + 0xAC); + outl(0, ioaddr + 0xB0); + } + } else { + /* for other boards we send a setup packet to initialize + the filters */ + u32 tx_flags = 0x08000000 | 192; + + /* construct perfect filter frame with mac address as first match + and broadcast address for all others */ + for (i=0; i<192; i++) + txb[i] = 0xFF; + txb[0] = nic->node_addr[0]; + txb[1] = nic->node_addr[1]; + txb[4] = nic->node_addr[2]; + txb[5] = nic->node_addr[3]; + txb[8] = nic->node_addr[4]; + txb[9] = nic->node_addr[5]; + + tx_ring[0].length = cpu_to_le32(tx_flags); + tx_ring[0].buffer1 = virt_to_le32desc(&txb[0]); + tx_ring[0].status = cpu_to_le32(0x80000000); + } + + /* Point to rx and tx descriptors */ + outl(virt_to_le32desc(&rx_ring[0]), ioaddr + CSR3); + outl(virt_to_le32desc(&tx_ring[0]), ioaddr + CSR4); + + init_media(nic); + + /* set the chip's operating mode (but don't turn on xmit and recv yet) */ + outl((tp->csr6 & ~0x00002002), ioaddr + CSR6); + + /* send setup packet for cards that support it */ + if (!(tp->flags & MC_HASH_ONLY)) { + /* enable transmit wait for completion */ + outl(tp->csr6 | 0x00002000, ioaddr + CSR6); + /* immediate transmit demand */ + outl(0, ioaddr + CSR1); + + to = currticks() + TX_TIME_OUT; + while ((tx_ring[0].status & 0x80000000) && (currticks() < to)) + /* wait */ ; + + if (currticks() >= to) { + printf ("%s: TX Setup Timeout.\n", tp->nic_name); + } + } + + if (tp->chip_id == LC82C168) + tulip_check_duplex(nic); + + set_rx_mode(nic); + + /* enable transmit and receive */ + outl(tp->csr6 | 0x00002002, ioaddr + CSR6); +} + + +/*********************************************************************/ +/* eth_transmit - Transmit a frame */ +/*********************************************************************/ +static void tulip_transmit(struct nic *nic, const char *d, unsigned int t, + unsigned int s, const char *p) +{ + u16 nstype; + u32 to; + u32 csr6 = inl(ioaddr + CSR6); + +#ifdef TULIP_DEBUG_WHERE + whereami("tulip_transmit\n"); +#endif + + /* Disable Tx */ + outl(csr6 & ~0x00002000, ioaddr + CSR6); + + memcpy(txb, d, ETH_ALEN); + memcpy(txb + ETH_ALEN, nic->node_addr, ETH_ALEN); + nstype = htons((u16) t); + memcpy(txb + 2 * ETH_ALEN, (u8 *)&nstype, 2); + memcpy(txb + ETH_HLEN, p, s); + + s += ETH_HLEN; + s &= 0x0FFF; + + /* pad to minimum packet size */ + while (s < ETH_ZLEN) + txb[s++] = '\0'; + +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf("%s: sending %d bytes ethtype %hX\n", tp->nic_name, s, t); +#endif + + /* setup the transmit descriptor */ + /* 0x60000000 = no interrupt on completion */ + tx_ring[0].length = cpu_to_le32(0x60000000 | s); + tx_ring[0].status = cpu_to_le32(0x80000000); + + /* Point to transmit descriptor */ + outl(virt_to_le32desc(&tx_ring[0]), ioaddr + CSR4); + + /* Enable Tx */ + outl(csr6 | 0x00002000, ioaddr + CSR6); + /* immediate transmit demand */ + outl(0, ioaddr + CSR1); + + to = currticks() + TX_TIME_OUT; + while ((tx_ring[0].status & 0x80000000) && (currticks() < to)) + /* wait */ ; + + if (currticks() >= to) { + printf ("TX Timeout!\n"); + } + + /* Disable Tx */ + outl(csr6 & ~0x00002000, ioaddr + CSR6); +} + +/*********************************************************************/ +/* eth_poll - Wait for a frame */ +/*********************************************************************/ +static int tulip_poll(struct nic *nic, int retrieve) +{ + +#ifdef TULIP_DEBUG_WHERE + whereami("tulip_poll\n"); +#endif + + /* no packet waiting. packet still owned by NIC */ + if (rx_ring[tp->cur_rx].status & 0x80000000) + return 0; + + if ( ! retrieve ) return 1; + +#ifdef TULIP_DEBUG_WHERE + whereami("tulip_poll got one\n"); +#endif + + nic->packetlen = (rx_ring[tp->cur_rx].status & 0x3FFF0000) >> 16; + + /* if we get a corrupted packet. throw it away and move on */ + if (rx_ring[tp->cur_rx].status & 0x00008000) { + /* return the descriptor and buffer to receive ring */ + rx_ring[tp->cur_rx].status = 0x80000000; + tp->cur_rx = (++tp->cur_rx) % RX_RING_SIZE; + return 0; + } + + /* copy packet to working buffer */ + memcpy(nic->packet, rxb + tp->cur_rx * BUFLEN, nic->packetlen); + + /* return the descriptor and buffer to receive ring */ + rx_ring[tp->cur_rx].status = 0x80000000; + tp->cur_rx = (++tp->cur_rx) % RX_RING_SIZE; + + return 1; +} + +/*********************************************************************/ +/* eth_disable - Disable the interface */ +/*********************************************************************/ +static void tulip_disable ( struct nic *nic ) { + +#ifdef TULIP_DEBUG_WHERE + whereami("tulip_disable\n"); +#endif + + tulip_reset(nic); + + /* disable interrupts */ + outl(0x00000000, ioaddr + CSR7); + + /* Stop the chip's Tx and Rx processes. */ + outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); + + /* Clear the missed-packet counter. */ + inl(ioaddr + CSR8); +} + +/*********************************************************************/ +/*IRQ - Enable, Disable, or Force interrupts */ +/*********************************************************************/ +static void tulip_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + +static struct nic_operations tulip_operations = { + .connect = dummy_connect, + .poll = tulip_poll, + .transmit = tulip_transmit, + .irq = tulip_irq, + +}; + +/*********************************************************************/ +/* eth_probe - Look for an adapter */ +/*********************************************************************/ +static int tulip_probe ( struct nic *nic, struct pci_device *pci ) { + + u32 i; + u8 chip_rev; + u8 ee_data[EEPROM_SIZE]; + unsigned short sum; + int chip_idx; + static unsigned char last_phys_addr[ETH_ALEN] = {0x00, 'L', 'i', 'n', 'u', 'x'}; + + if (pci->ioaddr == 0) + return 0; + + ioaddr = pci->ioaddr; + nic->ioaddr = pci->ioaddr & ~3; + nic->irqno = 0; + + /* point to private storage */ + tp = &tulip_bss.tpx; + + tp->vendor_id = pci->vendor; + tp->dev_id = pci->device; + + tp->if_port = 0; + tp->default_port = 0; + + adjust_pci_device(pci); + + /* disable interrupts */ + outl(0x00000000, ioaddr + CSR7); + + /* Stop the chip's Tx and Rx processes. */ + outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); + + /* Clear the missed-packet counter. */ + inl(ioaddr + CSR8); + + printf("\n"); /* so we start on a fresh line */ +#ifdef TULIP_DEBUG_WHERE + whereami("tulip_probe\n"); +#endif + +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf ("%s: Looking for Tulip Chip: Vendor=%hX Device=%hX\n", tp->nic_name, + tp->vendor, tp->dev_id); +#endif + + /* Figure out which chip we're dealing with */ + i = 0; + chip_idx = -1; + + while (pci_id_tbl[i].name) { + if ( (((u32) tp->dev_id << 16) | tp->vendor_id) == + (pci_id_tbl[i].id.pci & pci_id_tbl[i].id.pci_mask) ) { + chip_idx = pci_id_tbl[i].drv_flags; + break; + } + i++; + } + + if (chip_idx == -1) { + printf ("%s: Unknown Tulip Chip: Vendor=%hX Device=%hX\n", tp->nic_name, + tp->vendor_id, tp->dev_id); + return 0; + } + + tp->pci_id_idx = i; + tp->flags = tulip_tbl[chip_idx].flags; + +#ifdef TULIP_DEBUG + if (tulip_debug > 1) { + printf ("%s: tp->pci_id_idx == %d, name == %s\n", tp->nic_name, + tp->pci_id_idx, pci_id_tbl[tp->pci_id_idx].name); + printf ("%s: chip_idx == %d, name == %s\n", tp->nic_name, chip_idx, + tulip_tbl[chip_idx].chip_name); + } +#endif + + /* Bring the 21041/21143 out of sleep mode. + Caution: Snooze mode does not work with some boards! */ + if (tp->flags & HAS_PWRDWN) + pci_write_config_dword(pci, 0x40, 0x00000000); + + if (inl(ioaddr + CSR5) == 0xFFFFFFFF) { + printf("%s: The Tulip chip at %X is not functioning.\n", + tp->nic_name, (unsigned int) ioaddr); + return 0; + } + + pci_read_config_byte(pci, PCI_REVISION, &chip_rev); + + printf("%s: [chip: %s] rev %d at %hX\n", tp->nic_name, + tulip_tbl[chip_idx].chip_name, chip_rev, (unsigned int) ioaddr); + printf("%s: Vendor=%hX Device=%hX", tp->nic_name, tp->vendor_id, tp->dev_id); + + if (chip_idx == DC21041 && inl(ioaddr + CSR9) & 0x8000) { + printf(" 21040 compatible mode."); + chip_idx = DC21040; + } + + printf("\n"); + + /* The SROM/EEPROM interface varies dramatically. */ + sum = 0; + if (chip_idx == DC21040) { + outl(0, ioaddr + CSR9); /* Reset the pointer with a dummy write. */ + for (i = 0; i < ETH_ALEN; i++) { + int value, boguscnt = 100000; + do + value = inl(ioaddr + CSR9); + while (value < 0 && --boguscnt > 0); + nic->node_addr[i] = value; + sum += value & 0xff; + } + } else if (chip_idx == LC82C168) { + for (i = 0; i < 3; i++) { + int value, boguscnt = 100000; + outl(0x600 | i, ioaddr + 0x98); + do + value = inl(ioaddr + CSR9); + while (value < 0 && --boguscnt > 0); + put_unaligned(le16_to_cpu(value), ((u16*)nic->node_addr) + i); + sum += value & 0xffff; + } + } else if (chip_idx == COMET) { + /* No need to read the EEPROM. */ + put_unaligned(inl(ioaddr + 0xA4), (u32 *)nic->node_addr); + put_unaligned(inl(ioaddr + 0xA8), (u16 *)(nic->node_addr + 4)); + for (i = 0; i < ETH_ALEN; i ++) + sum += nic->node_addr[i]; + } else { + /* A serial EEPROM interface, we read now and sort it out later. */ + int sa_offset = 0; + int ee_addr_size = read_eeprom(ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; + + for (i = 0; i < sizeof(ee_data)/2; i++) + ((u16 *)ee_data)[i] = + le16_to_cpu(read_eeprom(ioaddr, i, ee_addr_size)); + + /* DEC now has a specification (see Notes) but early board makers + just put the address in the first EEPROM locations. */ + /* This does memcmp(eedata, eedata+16, 8) */ + for (i = 0; i < 8; i ++) + if (ee_data[i] != ee_data[16+i]) + sa_offset = 20; + if (ee_data[0] == 0xff && ee_data[1] == 0xff && ee_data[2] == 0) { + sa_offset = 2; /* Grrr, damn Matrox boards. */ + } + for (i = 0; i < ETH_ALEN; i ++) { + nic->node_addr[i] = ee_data[i + sa_offset]; + sum += ee_data[i + sa_offset]; + } + } + /* Lite-On boards have the address byte-swapped. */ + if ((nic->node_addr[0] == 0xA0 || nic->node_addr[0] == 0xC0) + && nic->node_addr[1] == 0x00) + for (i = 0; i < ETH_ALEN; i+=2) { + char tmp = nic->node_addr[i]; + nic->node_addr[i] = nic->node_addr[i+1]; + nic->node_addr[i+1] = tmp; + } + + if (sum == 0 || sum == ETH_ALEN*0xff) { + printf("%s: EEPROM not present!\n", tp->nic_name); + for (i = 0; i < ETH_ALEN-1; i++) + nic->node_addr[i] = last_phys_addr[i]; + nic->node_addr[i] = last_phys_addr[i] + 1; + } + + for (i = 0; i < ETH_ALEN; i++) + last_phys_addr[i] = nic->node_addr[i]; + + DBG ( "%s: %s at ioaddr %hX\n", tp->nic_name, eth_ntoa ( nic->node_addr ), + (unsigned int) ioaddr ); + + tp->chip_id = chip_idx; + tp->revision = chip_rev; + tp->csr0 = csr0; + + /* BugFixes: The 21143-TD hangs with PCI Write-and-Invalidate cycles. + And the ASIX must have a burst limit or horrible things happen. */ + if (chip_idx == DC21143 && chip_rev == 65) + tp->csr0 &= ~0x01000000; + else if (tp->flags & IS_ASIX) + tp->csr0 |= 0x2000; + + if (media_cap[tp->default_port] & MediaIsMII) { + static const u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, + 0x80, 0x100, 0x200 }; + tp->mii_advertise = media2advert[tp->default_port - 9]; + tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */ + } + + /* This is logically part of the probe routine, but too complex + to write inline. */ + if (tp->flags & HAS_MEDIA_TABLE) { + memcpy(tp->eeprom, ee_data, sizeof(tp->eeprom)); + parse_eeprom(nic); + } + + start_link(nic); + + /* reset the device and make ready for tx and rx of packets */ + tulip_reset(nic); + nic->nic_op = &tulip_operations; + + /* give the board a chance to reset before returning */ + tulip_wait(4*TICKS_PER_SEC); + + return 1; +} + +static void start_link(struct nic *nic) +{ + int i; + +#ifdef TULIP_DEBUG_WHERE + whereami("start_link\n"); +#endif + + if ((tp->flags & ALWAYS_CHECK_MII) || + (tp->mtable && tp->mtable->has_mii) || + ( ! tp->mtable && (tp->flags & HAS_MII))) { + unsigned int phy, phy_idx; + if (tp->mtable && tp->mtable->has_mii) { + for (i = 0; i < tp->mtable->leafcount; i++) + if (tp->mtable->mleaf[i].media == 11) { + tp->cur_index = i; + tp->saved_if_port = tp->if_port; + select_media(nic, 2); + tp->if_port = tp->saved_if_port; + break; + } + } + + /* Find the connected MII xcvrs. */ + for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(tp->phys); + phy++) { + int mii_status = mdio_read(nic, phy, 1); + if ((mii_status & 0x8301) == 0x8001 || + ((mii_status & 0x8000) == 0 && (mii_status & 0x7800) != 0)) { + int mii_reg0 = mdio_read(nic, phy, 0); + int mii_advert = mdio_read(nic, phy, 4); + int to_advert; + + if (tp->mii_advertise) + to_advert = tp->mii_advertise; + else if (tp->advertising[phy_idx]) + to_advert = tp->advertising[phy_idx]; + else /* Leave unchanged. */ + tp->mii_advertise = to_advert = mii_advert; + + tp->phys[phy_idx++] = phy; + printf("%s: MII transceiver %d config %hX status %hX advertising %hX.\n", + tp->nic_name, phy, mii_reg0, mii_status, mii_advert); + /* Fixup for DLink with miswired PHY. */ + if (mii_advert != to_advert) { + printf("%s: Advertising %hX on PHY %d previously advertising %hX.\n", + tp->nic_name, to_advert, phy, mii_advert); + mdio_write(nic, phy, 4, to_advert); + } + /* Enable autonegotiation: some boards default to off. */ + mdio_write(nic, phy, 0, mii_reg0 | + (tp->full_duplex ? 0x1100 : 0x1000) | + (media_cap[tp->default_port]&MediaIs100 ? 0x2000:0)); + } + } + tp->mii_cnt = phy_idx; + if (tp->mtable && tp->mtable->has_mii && phy_idx == 0) { + printf("%s: ***WARNING***: No MII transceiver found!\n", + tp->nic_name); + tp->phys[0] = 1; + } + } + + /* Reset the xcvr interface and turn on heartbeat. */ + switch (tp->chip_id) { + case DC21040: + outl(0x00000000, ioaddr + CSR13); + outl(0x00000004, ioaddr + CSR13); + break; + case DC21041: + /* This is nway_start(). */ + if (tp->sym_advertise == 0) + tp->sym_advertise = 0x0061; + outl(0x00000000, ioaddr + CSR13); + outl(0xFFFFFFFF, ioaddr + CSR14); + outl(0x00000008, ioaddr + CSR15); /* Listen on AUI also. */ + outl(inl(ioaddr + CSR6) | 0x0200, ioaddr + CSR6); + outl(0x0000EF01, ioaddr + CSR13); + break; + case DC21140: default: + if (tp->mtable) + outl(tp->mtable->csr12dir | 0x100, ioaddr + CSR12); + break; + case DC21142: + case PNIC2: + if (tp->mii_cnt || media_cap[tp->if_port] & MediaIsMII) { + outl(0x82020000, ioaddr + CSR6); + outl(0x0000, ioaddr + CSR13); + outl(0x0000, ioaddr + CSR14); + outl(0x820E0000, ioaddr + CSR6); + } else + nway_start(nic); + break; + case LC82C168: + if ( ! tp->mii_cnt) { + tp->nway = 1; + tp->nwayset = 0; + outl(0x00420000, ioaddr + CSR6); + outl(0x30, ioaddr + CSR12); + outl(0x0001F078, ioaddr + 0xB8); + outl(0x0201F078, ioaddr + 0xB8); /* Turn on autonegotiation. */ + } + break; + case MX98713: case COMPEX9881: + outl(0x00000000, ioaddr + CSR6); + outl(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */ + outl(0x00000001, ioaddr + CSR13); + break; + case MX98715: case MX98725: + outl(0x01a80000, ioaddr + CSR6); + outl(0xFFFFFFFF, ioaddr + CSR14); + outl(0x00001000, ioaddr + CSR12); + break; + case COMET: + /* No initialization necessary. */ + break; + } +} + +static void nway_start(struct nic *nic __unused) +{ + int csr14 = ((tp->sym_advertise & 0x0780) << 9) | + ((tp->sym_advertise&0x0020)<<1) | 0xffbf; + +#ifdef TULIP_DEBUG_WHERE + whereami("nway_start\n"); +#endif + + tp->if_port = 0; + tp->nway = tp->mediasense = 1; + tp->nwayset = tp->lpar = 0; + if (tp->chip_id == PNIC2) { + tp->csr6 = 0x01000000 | (tp->sym_advertise & 0x0040 ? 0x0200 : 0); + return; + } +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf("%s: Restarting internal NWay autonegotiation, %X.\n", + tp->nic_name, csr14); +#endif + outl(0x0001, ioaddr + CSR13); + outl(csr14, ioaddr + CSR14); + tp->csr6 = 0x82420000 | (tp->sym_advertise & 0x0040 ? 0x0200 : 0); + outl(tp->csr6, ioaddr + CSR6); + if (tp->mtable && tp->mtable->csr15dir) { + outl(tp->mtable->csr15dir, ioaddr + CSR15); + outl(tp->mtable->csr15val, ioaddr + CSR15); + } else if (tp->chip_id != PNIC2) + outw(0x0008, ioaddr + CSR15); + if (tp->chip_id == DC21041) /* Trigger NWAY. */ + outl(0xEF01, ioaddr + CSR12); + else + outl(0x1301, ioaddr + CSR12); +} + +static void init_media(struct nic *nic) +{ + int i; + +#ifdef TULIP_DEBUG_WHERE + whereami("init_media\n"); +#endif + + tp->saved_if_port = tp->if_port; + if (tp->if_port == 0) + tp->if_port = tp->default_port; + + /* Allow selecting a default media. */ + i = 0; + if (tp->mtable == NULL) + goto media_picked; + if (tp->if_port) { + int looking_for = media_cap[tp->if_port] & MediaIsMII ? 11 : + (tp->if_port == 12 ? 0 : tp->if_port); + for (i = 0; i < tp->mtable->leafcount; i++) + if (tp->mtable->mleaf[i].media == looking_for) { + printf("%s: Using user-specified media %s.\n", + tp->nic_name, medianame[tp->if_port]); + goto media_picked; + } + } + if ((tp->mtable->defaultmedia & 0x0800) == 0) { + int looking_for = tp->mtable->defaultmedia & 15; + for (i = 0; i < tp->mtable->leafcount; i++) + if (tp->mtable->mleaf[i].media == looking_for) { + printf("%s: Using EEPROM-set media %s.\n", + tp->nic_name, medianame[looking_for]); + goto media_picked; + } + } + /* Start sensing first non-full-duplex media. */ + for (i = tp->mtable->leafcount - 1; + (media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--) + ; + media_picked: + + tp->csr6 = 0; + tp->cur_index = i; + tp->nwayset = 0; + + if (tp->if_port) { + if (tp->chip_id == DC21143 && media_cap[tp->if_port] & MediaIsMII) { + /* We must reset the media CSRs when we force-select MII mode. */ + outl(0x0000, ioaddr + CSR13); + outl(0x0000, ioaddr + CSR14); + outl(0x0008, ioaddr + CSR15); + } + select_media(nic, 1); + return; + } + switch(tp->chip_id) { + case DC21041: + /* tp->nway = 1;*/ + nway_start(nic); + break; + case DC21142: + if (tp->mii_cnt) { + select_media(nic, 1); +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf("%s: Using MII transceiver %d, status %hX.\n", + tp->nic_name, tp->phys[0], mdio_read(nic, tp->phys[0], 1)); +#endif + outl(0x82020000, ioaddr + CSR6); + tp->csr6 = 0x820E0000; + tp->if_port = 11; + outl(0x0000, ioaddr + CSR13); + outl(0x0000, ioaddr + CSR14); + } else + nway_start(nic); + break; + case PNIC2: + nway_start(nic); + break; + case LC82C168: + if (tp->mii_cnt) { + tp->if_port = 11; + tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0); + outl(0x0001, ioaddr + CSR15); + } else if (inl(ioaddr + CSR5) & TPLnkPass) + pnic_do_nway(nic); + else { + /* Start with 10mbps to do autonegotiation. */ + outl(0x32, ioaddr + CSR12); + tp->csr6 = 0x00420000; + outl(0x0001B078, ioaddr + 0xB8); + outl(0x0201B078, ioaddr + 0xB8); + } + break; + case MX98713: case COMPEX9881: + tp->if_port = 0; + tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0); + outl(0x0f370000 | inw(ioaddr + 0x80), ioaddr + 0x80); + break; + case MX98715: case MX98725: + /* Provided by BOLO, Macronix - 12/10/1998. */ + tp->if_port = 0; + tp->csr6 = 0x01a80200; + outl(0x0f370000 | inw(ioaddr + 0x80), ioaddr + 0x80); + outl(0x11000 | inw(ioaddr + 0xa0), ioaddr + 0xa0); + break; + case COMET: + /* Enable automatic Tx underrun recovery */ + outl(inl(ioaddr + 0x88) | 1, ioaddr + 0x88); + tp->if_port = 0; + tp->csr6 = 0x00040000; + break; + case AX88140: case AX88141: + tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100; + break; + default: + select_media(nic, 1); + } +} + +static void pnic_do_nway(struct nic *nic __unused) +{ + u32 phy_reg = inl(ioaddr + 0xB8); + u32 new_csr6 = tp->csr6 & ~0x40C40200; + +#ifdef TULIP_DEBUG_WHERE + whereami("pnic_do_nway\n"); +#endif + + if (phy_reg & 0x78000000) { /* Ignore baseT4 */ + if (phy_reg & 0x20000000) tp->if_port = 5; + else if (phy_reg & 0x40000000) tp->if_port = 3; + else if (phy_reg & 0x10000000) tp->if_port = 4; + else if (phy_reg & 0x08000000) tp->if_port = 0; + tp->nwayset = 1; + new_csr6 = (tp->if_port & 1) ? 0x01860000 : 0x00420000; + outl(0x32 | (tp->if_port & 1), ioaddr + CSR12); + if (tp->if_port & 1) + outl(0x1F868, ioaddr + 0xB8); + if (phy_reg & 0x30000000) { + tp->full_duplex = 1; + new_csr6 |= 0x00000200; + } +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf("%s: PNIC autonegotiated status %X, %s.\n", + tp->nic_name, phy_reg, medianame[tp->if_port]); +#endif + if (tp->csr6 != new_csr6) { + tp->csr6 = new_csr6; + outl(tp->csr6 | 0x0002, ioaddr + CSR6); /* Restart Tx */ + outl(tp->csr6 | 0x2002, ioaddr + CSR6); + } + } +} + +/* Set up the transceiver control registers for the selected media type. */ +static void select_media(struct nic *nic, int startup) +{ + struct mediatable *mtable = tp->mtable; + u32 new_csr6; + int i; + +#ifdef TULIP_DEBUG_WHERE + whereami("select_media\n"); +#endif + + if (mtable) { + struct medialeaf *mleaf = &mtable->mleaf[tp->cur_index]; + unsigned char *p = mleaf->leafdata; + switch (mleaf->type) { + case 0: /* 21140 non-MII xcvr. */ +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf("%s: Using a 21140 non-MII transceiver" + " with control setting %hhX.\n", + tp->nic_name, p[1]); +#endif + tp->if_port = p[0]; + if (startup) + outl(mtable->csr12dir | 0x100, ioaddr + CSR12); + outl(p[1], ioaddr + CSR12); + new_csr6 = 0x02000000 | ((p[2] & 0x71) << 18); + break; + case 2: case 4: { + u16 setup[5]; + u32 csr13val, csr14val, csr15dir, csr15val; + for (i = 0; i < 5; i++) + setup[i] = get_u16(&p[i*2 + 1]); + + tp->if_port = p[0] & 15; + if (media_cap[tp->if_port] & MediaAlwaysFD) + tp->full_duplex = 1; + + if (startup && mtable->has_reset) { + struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset]; + unsigned char *rst = rleaf->leafdata; +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf("%s: Resetting the transceiver.\n", + tp->nic_name); +#endif + for (i = 0; i < rst[0]; i++) + outl(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15); + } +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf("%s: 21143 non-MII %s transceiver control " + "%hX/%hX.\n", + tp->nic_name, medianame[tp->if_port], setup[0], setup[1]); +#endif + if (p[0] & 0x40) { /* SIA (CSR13-15) setup values are provided. */ + csr13val = setup[0]; + csr14val = setup[1]; + csr15dir = (setup[3]<<16) | setup[2]; + csr15val = (setup[4]<<16) | setup[2]; + outl(0, ioaddr + CSR13); + outl(csr14val, ioaddr + CSR14); + outl(csr15dir, ioaddr + CSR15); /* Direction */ + outl(csr15val, ioaddr + CSR15); /* Data */ + outl(csr13val, ioaddr + CSR13); + } else { + csr13val = 1; + csr14val = 0x0003FF7F; + csr15dir = (setup[0]<<16) | 0x0008; + csr15val = (setup[1]<<16) | 0x0008; + if (tp->if_port <= 4) + csr14val = t21142_csr14[tp->if_port]; + if (startup) { + outl(0, ioaddr + CSR13); + outl(csr14val, ioaddr + CSR14); + } + outl(csr15dir, ioaddr + CSR15); /* Direction */ + outl(csr15val, ioaddr + CSR15); /* Data */ + if (startup) outl(csr13val, ioaddr + CSR13); + } +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf("%s: Setting CSR15 to %X/%X.\n", + tp->nic_name, csr15dir, csr15val); +#endif + if (mleaf->type == 4) + new_csr6 = 0x82020000 | ((setup[2] & 0x71) << 18); + else + new_csr6 = 0x82420000; + break; + } + case 1: case 3: { + int phy_num = p[0]; + int init_length = p[1]; + u16 *misc_info; + + tp->if_port = 11; + new_csr6 = 0x020E0000; + if (mleaf->type == 3) { /* 21142 */ + u16 *init_sequence = (u16*)(p+2); + u16 *reset_sequence = &((u16*)(p+3))[init_length]; + int reset_length = p[2 + init_length*2]; + misc_info = reset_sequence + reset_length; + if (startup) + for (i = 0; i < reset_length; i++) + outl(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15); + for (i = 0; i < init_length; i++) + outl(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15); + } else { + u8 *init_sequence = p + 2; + u8 *reset_sequence = p + 3 + init_length; + int reset_length = p[2 + init_length]; + misc_info = (u16*)(reset_sequence + reset_length); + if (startup) { + outl(mtable->csr12dir | 0x100, ioaddr + CSR12); + for (i = 0; i < reset_length; i++) + outl(reset_sequence[i], ioaddr + CSR12); + } + for (i = 0; i < init_length; i++) + outl(init_sequence[i], ioaddr + CSR12); + } + tp->advertising[phy_num] = get_u16(&misc_info[1]) | 1; + if (startup < 2) { + if (tp->mii_advertise == 0) + tp->mii_advertise = tp->advertising[phy_num]; +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf("%s: Advertising %hX on MII %d.\n", + tp->nic_name, tp->mii_advertise, tp->phys[phy_num]); +#endif + mdio_write(nic, tp->phys[phy_num], 4, tp->mii_advertise); + } + break; + } + default: + printf("%s: Invalid media table selection %d.\n", + tp->nic_name, mleaf->type); + new_csr6 = 0x020E0000; + } +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf("%s: Using media type %s, CSR12 is %hhX.\n", + tp->nic_name, medianame[tp->if_port], + inl(ioaddr + CSR12) & 0xff); +#endif + } else if (tp->chip_id == DC21041) { + int port = tp->if_port <= 4 ? tp->if_port : 0; +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf("%s: 21041 using media %s, CSR12 is %hX.\n", + tp->nic_name, medianame[port == 3 ? 12: port], + inl(ioaddr + CSR12)); +#endif + outl(0x00000000, ioaddr + CSR13); /* Reset the serial interface */ + outl(t21041_csr14[port], ioaddr + CSR14); + outl(t21041_csr15[port], ioaddr + CSR15); + outl(t21041_csr13[port], ioaddr + CSR13); + new_csr6 = 0x80020000; + } else if (tp->chip_id == LC82C168) { + if (startup && ! tp->medialock) + tp->if_port = tp->mii_cnt ? 11 : 0; +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf("%s: PNIC PHY status is %hX, media %s.\n", + tp->nic_name, inl(ioaddr + 0xB8), medianame[tp->if_port]); +#endif + if (tp->mii_cnt) { + new_csr6 = 0x810C0000; + outl(0x0001, ioaddr + CSR15); + outl(0x0201B07A, ioaddr + 0xB8); + } else if (startup) { + /* Start with 10mbps to do autonegotiation. */ + outl(0x32, ioaddr + CSR12); + new_csr6 = 0x00420000; + outl(0x0001B078, ioaddr + 0xB8); + outl(0x0201B078, ioaddr + 0xB8); + } else if (tp->if_port == 3 || tp->if_port == 5) { + outl(0x33, ioaddr + CSR12); + new_csr6 = 0x01860000; + /* Trigger autonegotiation. */ + outl(startup ? 0x0201F868 : 0x0001F868, ioaddr + 0xB8); + } else { + outl(0x32, ioaddr + CSR12); + new_csr6 = 0x00420000; + outl(0x1F078, ioaddr + 0xB8); + } + } else if (tp->chip_id == DC21040) { /* 21040 */ + /* Turn on the xcvr interface. */ +#ifdef TULIP_DEBUG + int csr12 = inl(ioaddr + CSR12); + if (tulip_debug > 1) + printf("%s: 21040 media type is %s, CSR12 is %hhX.\n", + tp->nic_name, medianame[tp->if_port], csr12); +#endif + if (media_cap[tp->if_port] & MediaAlwaysFD) + tp->full_duplex = 1; + new_csr6 = 0x20000; + /* Set the full duplux match frame. */ + outl(FULL_DUPLEX_MAGIC, ioaddr + CSR11); + outl(0x00000000, ioaddr + CSR13); /* Reset the serial interface */ + if (t21040_csr13[tp->if_port] & 8) { + outl(0x0705, ioaddr + CSR14); + outl(0x0006, ioaddr + CSR15); + } else { + outl(0xffff, ioaddr + CSR14); + outl(0x0000, ioaddr + CSR15); + } + outl(0x8f01 | t21040_csr13[tp->if_port], ioaddr + CSR13); + } else { /* Unknown chip type with no media table. */ + if (tp->default_port == 0) + tp->if_port = tp->mii_cnt ? 11 : 3; + if (media_cap[tp->if_port] & MediaIsMII) { + new_csr6 = 0x020E0000; + } else if (media_cap[tp->if_port] & MediaIsFx) { + new_csr6 = 0x028600000; + } else + new_csr6 = 0x038600000; +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf("%s: No media description table, assuming " + "%s transceiver, CSR12 %hhX.\n", + tp->nic_name, medianame[tp->if_port], + inl(ioaddr + CSR12)); +#endif + } + + tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0); + return; +} + +/* + Check the MII negotiated duplex and change the CSR6 setting if + required. + Return 0 if everything is OK. + Return < 0 if the transceiver is missing or has no link beat. +*/ +static int tulip_check_duplex(struct nic *nic) +{ + unsigned int bmsr, lpa, negotiated, new_csr6; + + bmsr = mdio_read(nic, tp->phys[0], 1); + lpa = mdio_read(nic, tp->phys[0], 5); + +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf("%s: MII status %#x, Link partner report " + "%#x.\n", tp->nic_name, bmsr, lpa); +#endif + + if (bmsr == 0xffff) + return -2; + if ((bmsr & 4) == 0) { + int new_bmsr = mdio_read(nic, tp->phys[0], 1); + if ((new_bmsr & 4) == 0) { +#ifdef TULIP_DEBUG + if (tulip_debug > 1) + printf("%s: No link beat on the MII interface," + " status %#x.\n", tp->nic_name, + new_bmsr); +#endif + return -1; + } + } + tp->full_duplex = lpa & 0x140; + + new_csr6 = tp->csr6; + negotiated = lpa & tp->advertising[0]; + + if(negotiated & 0x380) new_csr6 &= ~0x400000; + else new_csr6 |= 0x400000; + if (tp->full_duplex) new_csr6 |= 0x200; + else new_csr6 &= ~0x200; + + if (new_csr6 != tp->csr6) { + tp->csr6 = new_csr6; + +#ifdef TULIP_DEBUG + if (tulip_debug > 0) + printf("%s: Setting %s-duplex based on MII" + "#%d link partner capability of %#x.\n", + tp->nic_name, + tp->full_duplex ? "full" : "half", + tp->phys[0], lpa); +#endif + return 1; + } + + return 0; +} + +static struct pci_device_id tulip_nics[] = { +PCI_ROM(0x1011, 0x0002, "dc21040", "Digital Tulip", 0), +PCI_ROM(0x1011, 0x0009, "ds21140", "Digital Tulip Fast", 0), +PCI_ROM(0x1011, 0x0014, "dc21041", "Digital Tulip+", 0), +PCI_ROM(0x1011, 0x0019, "ds21142", "Digital Tulip 21142", 0), +PCI_ROM(0x10b7, 0x9300, "3csoho100b-tx","3ComSOHO100B-TX", 0), +PCI_ROM(0x10b9, 0x5261, "ali1563", "ALi 1563 integrated ethernet", 0), +PCI_ROM(0x10d9, 0x0512, "mx98713", "Macronix MX987x3", 0), +PCI_ROM(0x10d9, 0x0531, "mx98715", "Macronix MX987x5", 0), +PCI_ROM(0x1113, 0x1217, "mxic-98715", "Macronix MX987x5", 0), +PCI_ROM(0x11ad, 0xc115, "lc82c115", "LinkSys LNE100TX", 0), +PCI_ROM(0x11ad, 0x0002, "82c168", "Netgear FA310TX", 0), +PCI_ROM(0x1282, 0x9100, "dm9100", "Davicom 9100", 0), +PCI_ROM(0x1282, 0x9102, "dm9102", "Davicom 9102", 0), +PCI_ROM(0x1282, 0x9009, "dm9009", "Davicom 9009", 0), +PCI_ROM(0x1282, 0x9132, "dm9132", "Davicom 9132", 0), +PCI_ROM(0x1317, 0x0985, "centaur-p", "ADMtek Centaur-P", 0), +PCI_ROM(0x1317, 0x0981, "an981", "ADMtek AN981 Comet", 0), /* ADMTek Centaur-P (stmicro) */ +PCI_ROM(0x1113, 0x1216, "an983", "ADMTek AN983 Comet", 0), +PCI_ROM(0x1317, 0x9511, "an983b", "ADMTek Comet 983b", 0), +PCI_ROM(0x1317, 0x1985, "centaur-c", "ADMTek Centaur-C", 0), +PCI_ROM(0x8086, 0x0039, "intel21145", "Intel Tulip", 0), +PCI_ROM(0x125b, 0x1400, "ax88140", "ASIX AX88140", 0), +PCI_ROM(0x11f6, 0x9881, "rl100tx", "Compex RL100-TX", 0), +PCI_ROM(0x115d, 0x0003, "xircomtulip", "Xircom Tulip", 0), +PCI_ROM(0x104a, 0x0981, "tulip-0981", "Tulip 0x104a 0x0981", 0), +PCI_ROM(0x104a, 0x2774, "SGThomson-STE10100A", "Tulip 0x104a 0x2774", 0), /*Modified by Ramesh Chander*/ +PCI_ROM(0x1113, 0x9511, "tulip-9511", "Tulip 0x1113 0x9511", 0), +PCI_ROM(0x1186, 0x1561, "tulip-1561", "Tulip 0x1186 0x1561", 0), +PCI_ROM(0x1259, 0xa120, "tulip-a120", "Tulip 0x1259 0xa120", 0), +PCI_ROM(0x13d1, 0xab02, "tulip-ab02", "Tulip 0x13d1 0xab02", 0), +PCI_ROM(0x13d1, 0xab03, "tulip-ab03", "Tulip 0x13d1 0xab03", 0), +PCI_ROM(0x13d1, 0xab08, "tulip-ab08", "Tulip 0x13d1 0xab08", 0), +PCI_ROM(0x14f1, 0x1803, "lanfinity", "Conexant LANfinity", 0), +PCI_ROM(0x1626, 0x8410, "tulip-8410", "Tulip 0x1626 0x8410", 0), +PCI_ROM(0x1737, 0xab08, "tulip-1737-ab08","Tulip 0x1737 0xab08", 0), +PCI_ROM(0x1737, 0xab09, "tulip-ab09", "Tulip 0x1737 0xab09", 0), +}; + +PCI_DRIVER ( tulip_driver, tulip_nics, PCI_NO_CLASS ); + +DRIVER ( "Tulip", nic_driver, pci_driver, tulip_driver, + tulip_probe, tulip_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/net/w89c840.c b/debian/grub-extras/disabled/gpxe/src/drivers/net/w89c840.c new file mode 100644 index 0000000..fa6188a --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/net/w89c840.c @@ -0,0 +1,964 @@ +/* + * Etherboot - BOOTP/TFTP Bootstrap Program + * + * w89c840.c -- This file implements the winbond-840 driver for etherboot. + * + */ + +/* + * Adapted by Igor V. Kovalenko + * -- <garrison@mail.ru> + * OR + * -- <iko@crec.mipt.ru> + * Initial adaptaion stage, including testing, completed 23 August 2000. + */ + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2, or (at + * your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +/* + * date version by what + * Written: Aug 20 2000 V0.10 iko Initial revision. + * changes: Aug 22 2000 V0.90 iko Works! + * Aug 23 2000 V0.91 iko Cleanup, posted to etherboot + * maintainer. + * Aug 26 2000 V0.92 iko Fixed Rx ring handling. + * First Linux Kernel (TM) + * successfully loaded using + * this driver. + * Jan 07 2001 V0.93 iko Transmitter timeouts are handled + * using timer2 routines. Proposed + * by Ken Yap to eliminate CPU speed + * dependency. + * Dec 12 2003 V0.94 timlegge Fixed issues in 5.2, removed + * interrupt usage, enabled + * multicast support + * + * This is the etherboot driver for cards based on Winbond W89c840F chip. + * + * It was written from skeleton source, with Donald Becker's winbond-840.c + * kernel driver as a guideline. Mostly the w89c840 related definitions + * and the lower level routines have been cut-and-pasted into this source. + * + * Frankly speaking, about 90% of the code was obtained using cut'n'paste + * sequence :) while the remainder appeared while brainstorming + * Linux Kernel 2.4.0-testX source code. Thanks, Donald and Linus! + * + * There was a demand for using this card in a rather large + * remote boot environment at MSKP OVTI Lab of + * Moscow Institute for Physics and Technology (MIPT) -- http://www.mipt.ru/ + * so you may count that for motivation. + * + */ + +/* + * If you want to see debugging output then define W89C840_DEBUG + */ + +/* +#define W89C840_DEBUG +*/ + +/* + * Keep using IO_OPS for Etherboot driver! + */ +#define USE_IO_OPS + +#include "etherboot.h" +#include "nic.h" +#include <gpxe/pci.h> +#include <gpxe/ethernet.h> + +static const char *w89c840_version = "driver Version 0.94 - December 12, 2003"; + +/* Linux support functions */ +#define virt_to_le32desc(addr) virt_to_bus(addr) +#define le32desc_to_virt(addr) bus_to_virt(addr) + +/* +#define cpu_to_le32(val) (val) +#define le32_to_cpu(val) (val) +*/ + +/* Operational parameters that are set at compile time. */ + +/* Keep the ring sizes a power of two for compile efficiency. + The compiler will convert <unsigned>'%'<2^N> into a bit mask. + Making the Tx ring too large decreases the effectiveness of channel + bonding and packet priority. + There are no ill effects from too-large receive rings. */ +#define TX_RING_SIZE 2 +#define RX_RING_SIZE 2 + +/* The presumed FIFO size for working around the Tx-FIFO-overflow bug. + To avoid overflowing we don't queue again until we have room for a + full-size packet. + */ +#define TX_FIFO_SIZE (2048) +#define TX_BUG_FIFO_LIMIT (TX_FIFO_SIZE-1514-16) + +/* Operational parameters that usually are not changed. */ +/* Time in jiffies before concluding the transmitter is hung. */ +#define TX_TIMEOUT (10*1000) + +#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ + +/* + * Used to be this much CPU loops on Celeron@400 (?), + * now using real timer and TX_TIMEOUT! + * #define TX_LOOP_COUNT 10000000 + */ + +#if !defined(__OPTIMIZE__) +#warning You must compile this file with the correct options! +#warning See the last lines of the source file. +#error You must compile this driver with "-O". +#endif + +enum chip_capability_flags {CanHaveMII=1, HasBrokenTx=2}; + +#ifdef USE_IO_OPS +#define W840_FLAGS (PCI_USES_IO | PCI_ADDR0 | PCI_USES_MASTER) +#else +#define W840_FLAGS (PCI_USES_MEM | PCI_ADDR1 | PCI_USES_MASTER) +#endif + +static u32 driver_flags = CanHaveMII | HasBrokenTx; + +/* This driver was written to use PCI memory space, however some x86 systems + work only with I/O space accesses. Pass -DUSE_IO_OPS to use PCI I/O space + accesses instead of memory space. */ + +#ifdef USE_IO_OPS +#undef readb +#undef readw +#undef readl +#undef writeb +#undef writew +#undef writel +#define readb inb +#define readw inw +#define readl inl +#define writeb outb +#define writew outw +#define writel outl +#endif + +/* Offsets to the Command and Status Registers, "CSRs". + While similar to the Tulip, these registers are longword aligned. + Note: It's not useful to define symbolic names for every register bit in + the device. The name can only partially document the semantics and make + the driver longer and more difficult to read. +*/ +enum w840_offsets { + PCIBusCfg=0x00, TxStartDemand=0x04, RxStartDemand=0x08, + RxRingPtr=0x0C, TxRingPtr=0x10, + IntrStatus=0x14, NetworkConfig=0x18, IntrEnable=0x1C, + RxMissed=0x20, EECtrl=0x24, MIICtrl=0x24, BootRom=0x28, GPTimer=0x2C, + CurRxDescAddr=0x30, CurRxBufAddr=0x34, /* Debug use */ + MulticastFilter0=0x38, MulticastFilter1=0x3C, StationAddr=0x40, + CurTxDescAddr=0x4C, CurTxBufAddr=0x50, +}; + +/* Bits in the interrupt status/enable registers. */ +/* The bits in the Intr Status/Enable registers, mostly interrupt sources. */ +enum intr_status_bits { + NormalIntr=0x10000, AbnormalIntr=0x8000, + IntrPCIErr=0x2000, TimerInt=0x800, + IntrRxDied=0x100, RxNoBuf=0x80, IntrRxDone=0x40, + TxFIFOUnderflow=0x20, RxErrIntr=0x10, + TxIdle=0x04, IntrTxStopped=0x02, IntrTxDone=0x01, +}; + +/* Bits in the NetworkConfig register. */ +enum rx_mode_bits { + AcceptErr=0x80, AcceptRunt=0x40, + AcceptBroadcast=0x20, AcceptMulticast=0x10, + AcceptAllPhys=0x08, AcceptMyPhys=0x02, +}; + +enum mii_reg_bits { + MDIO_ShiftClk=0x10000, MDIO_DataIn=0x80000, MDIO_DataOut=0x20000, + MDIO_EnbOutput=0x40000, MDIO_EnbIn = 0x00000, +}; + +/* The Tulip Rx and Tx buffer descriptors. */ +struct w840_rx_desc { + s32 status; + s32 length; + u32 buffer1; + u32 next_desc; +}; + +struct w840_tx_desc { + s32 status; + s32 length; + u32 buffer1, buffer2; /* We use only buffer 1. */ +}; + +/* Bits in network_desc.status */ +enum desc_status_bits { + DescOwn=0x80000000, DescEndRing=0x02000000, DescUseLink=0x01000000, + DescWholePkt=0x60000000, DescStartPkt=0x20000000, DescEndPkt=0x40000000, + DescIntr=0x80000000, +}; +#define PRIV_ALIGN 15 /* Required alignment mask */ +#define PRIV_ALIGN_BYTES 32 + +static struct winbond_private +{ + /* Descriptor rings first for alignment. */ + struct w840_rx_desc rx_ring[RX_RING_SIZE]; + struct w840_tx_desc tx_ring[TX_RING_SIZE]; + struct net_device *next_module; /* Link for devices of this type. */ + void *priv_addr; /* Unaligned address for kfree */ + const char *product_name; + /* Frequently used values: keep some adjacent for cache effect. */ + int chip_id, drv_flags; + struct pci_dev *pci_dev; + int csr6; + struct w840_rx_desc *rx_head_desc; + unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */ + unsigned int rx_buf_sz; /* Based on MTU+slack. */ + unsigned int cur_tx, dirty_tx; + int tx_q_bytes; + unsigned int tx_full:1; /* The Tx queue is full. */ + /* These values are keep track of the transceiver/media in use. */ + unsigned int full_duplex:1; /* Full-duplex operation requested. */ + unsigned int duplex_lock:1; + unsigned int medialock:1; /* Do not sense media. */ + unsigned int default_port:4; /* Last dev->if_port value. */ + /* MII transceiver section. */ + int mii_cnt; /* MII device addresses. */ + u16 advertising; /* NWay media advertisement */ + unsigned char phys[2]; /* MII device addresses. */ +} w840private __attribute__ ((aligned (PRIV_ALIGN_BYTES))); + +/* NIC specific static variables go here */ + +static int ioaddr; +static unsigned short eeprom [0x40]; +struct { + char rx_packet[PKT_BUF_SZ * RX_RING_SIZE]; + char tx_packet[PKT_BUF_SZ * TX_RING_SIZE]; +} w89c840_buf __shared; + +static int eeprom_read(long ioaddr, int location); +static int mdio_read(int base_address, int phy_id, int location); +#if 0 +static void mdio_write(int base_address, int phy_id, int location, int value); +#endif + +static void check_duplex(void); +static void set_rx_mode(void); +static void init_ring(void); + +#if defined(W89C840_DEBUG) +static void decode_interrupt(u32 intr_status) +{ + printf("Interrupt status: "); + +#define TRACE_INTR(_intr_) \ + if (intr_status & (_intr_)) { printf (" " #_intr_); } + + TRACE_INTR(NormalIntr); + TRACE_INTR(AbnormalIntr); + TRACE_INTR(IntrPCIErr); + TRACE_INTR(TimerInt); + TRACE_INTR(IntrRxDied); + TRACE_INTR(RxNoBuf); + TRACE_INTR(IntrRxDone); + TRACE_INTR(TxFIFOUnderflow); + TRACE_INTR(RxErrIntr); + TRACE_INTR(TxIdle); + TRACE_INTR(IntrTxStopped); + TRACE_INTR(IntrTxDone); + + printf("\n"); + /*sleep(1);*/ +} +#endif + +/************************************************************************** +w89c840_reset - Reset adapter +***************************************************************************/ +static void w89c840_reset(struct nic *nic) +{ + int i; + + /* Reset the chip to erase previous misconfiguration. + No hold time required! */ + writel(0x00000001, ioaddr + PCIBusCfg); + + init_ring(); + + writel(virt_to_bus(w840private.rx_ring), ioaddr + RxRingPtr); + writel(virt_to_bus(w840private.tx_ring), ioaddr + TxRingPtr); + + for (i = 0; i < ETH_ALEN; i++) + writeb(nic->node_addr[i], ioaddr + StationAddr + i); + + /* Initialize other registers. */ + /* Configure the PCI bus bursts and FIFO thresholds. + 486: Set 8 longword cache alignment, 8 longword burst. + 586: Set 16 longword cache alignment, no burst limit. + Cache alignment bits 15:14 Burst length 13:8 + 0000 <not allowed> 0000 align to cache 0800 8 longwords + 4000 8 longwords 0100 1 longword 1000 16 longwords + 8000 16 longwords 0200 2 longwords 2000 32 longwords + C000 32 longwords 0400 4 longwords + Wait the specified 50 PCI cycles after a reset by initializing + Tx and Rx queues and the address filter list. */ + + writel(0xE010, ioaddr + PCIBusCfg); + + writel(0, ioaddr + RxStartDemand); + w840private.csr6 = 0x20022002; + check_duplex(); + set_rx_mode(); + + /* Do not enable the interrupts Etherboot doesn't need them */ +/* + writel(0x1A0F5, ioaddr + IntrStatus); + writel(0x1A0F5, ioaddr + IntrEnable); +*/ +#if defined(W89C840_DEBUG) + printf("winbond-840 : Done reset.\n"); +#endif +} + +#if 0 +static void handle_intr(u32 intr_stat) +{ + if ((intr_stat & (NormalIntr|AbnormalIntr)) == 0) { + /* we are polling, do not return now */ + /*return 0;*/ + } else { + /* Acknowledge all of the current interrupt sources ASAP. */ + writel(intr_stat & 0x001ffff, ioaddr + IntrStatus); + } + + if (intr_stat & AbnormalIntr) { + /* There was an abnormal interrupt */ + printf("\n-=- Abnormal interrupt.\n"); + +#if defined(W89C840_DEBUG) + decode_interrupt(intr_stat); +#endif + + if (intr_stat & RxNoBuf) { + /* There was an interrupt */ + printf("-=- <=> No receive buffers available.\n"); + writel(0, ioaddr + RxStartDemand); + } + } +} +#endif + +/************************************************************************** +w89c840_poll - Wait for a frame +***************************************************************************/ +static int w89c840_poll(struct nic *nic, int retrieve) +{ + /* return true if there's an ethernet packet ready to read */ + /* nic->packet should contain data on return */ + /* nic->packetlen should contain length of data */ + int packet_received = 0; + +#if defined(W89C840_DEBUG) + u32 intr_status = readl(ioaddr + IntrStatus); +#endif + + do { + /* Code from netdev_rx(dev) */ + + int entry = w840private.cur_rx % RX_RING_SIZE; + + struct w840_rx_desc *desc = w840private.rx_head_desc; + s32 status = desc->status; + + if (status & DescOwn) { + /* DescOwn bit is still set, we should wait for RX to complete */ + packet_received = 0; + break; + } + + if ( !retrieve ) { + packet_received = 1; + break; + } + + if ((status & 0x38008300) != 0x0300) { + if ((status & 0x38000300) != 0x0300) { + /* Ingore earlier buffers. */ + if ((status & 0xffff) != 0x7fff) { + printf("winbond-840 : Oversized Ethernet frame spanned " + "multiple buffers, entry %d status %X !\n", + w840private.cur_rx, (unsigned int) status); + } + } else if (status & 0x8000) { + /* There was a fatal error. */ +#if defined(W89C840_DEBUG) + printf("winbond-840 : Receive error, Rx status %X :", status); + if (status & 0x0890) { + printf(" RXLEN_ERROR"); + } + if (status & 0x004C) { + printf(", FRAME_ERROR"); + } + if (status & 0x0002) { + printf(", CRC_ERROR"); + } + printf("\n"); +#endif + + /* Simpy do a reset now... */ + w89c840_reset(nic); + + packet_received = 0; + break; + } + } else { + /* Omit the four octet CRC from the length. */ + int pkt_len = ((status >> 16) & 0x7ff) - 4; + +#if defined(W89C840_DEBUG) + printf(" netdev_rx() normal Rx pkt ring %d length %d status %X\n", entry, pkt_len, status); +#endif + + nic->packetlen = pkt_len; + + /* Check if the packet is long enough to accept without copying + to a minimally-sized skbuff. */ + + memcpy(nic->packet, le32desc_to_virt(w840private.rx_ring[entry].buffer1), pkt_len); + packet_received = 1; + + /* Release buffer to NIC */ + w840private.rx_ring[entry].status = DescOwn; + +#if defined(W89C840_DEBUG) + /* You will want this info for the initial debug. */ + printf(" Rx data %hhX:%hhX:%hhX:%hhX:%hhX:" + "%hhX %hhX:%hhX:%hhX:%hhX:%hhX:%hhX %hhX%hhX " + "%hhX.%hhX.%hhX.%hhX.\n", + nic->packet[0], nic->packet[1], nic->packet[2], nic->packet[3], + nic->packet[4], nic->packet[5], nic->packet[6], nic->packet[7], + nic->packet[8], nic->packet[9], nic->packet[10], + nic->packet[11], nic->packet[12], nic->packet[13], + nic->packet[14], nic->packet[15], nic->packet[16], + nic->packet[17]); +#endif + + } + + entry = (++w840private.cur_rx) % RX_RING_SIZE; + w840private.rx_head_desc = &w840private.rx_ring[entry]; + } while (0); + + return packet_received; +} + +/************************************************************************** +w89c840_transmit - Transmit a frame +***************************************************************************/ + +static void w89c840_transmit( + struct nic *nic, + const char *d, /* Destination */ + unsigned int t, /* Type */ + unsigned int s, /* size */ + const char *p) /* Packet */ +{ + /* send the packet to destination */ + unsigned entry; + int transmit_status; + unsigned long ct; + + /* Caution: the write order is important here, set the field + with the "ownership" bits last. */ + + /* Fill in our transmit buffer */ + entry = w840private.cur_tx % TX_RING_SIZE; + + memcpy (w89c840_buf.tx_packet, d, ETH_ALEN); /* dst */ + memcpy (w89c840_buf.tx_packet + ETH_ALEN, nic->node_addr, ETH_ALEN);/*src*/ + + *((char *) w89c840_buf.tx_packet + 12) = t >> 8; /* type */ + *((char *) w89c840_buf.tx_packet + 13) = t; + + memcpy (w89c840_buf.tx_packet + ETH_HLEN, p, s); + s += ETH_HLEN; + + while (s < ETH_ZLEN) + *((char *) w89c840_buf.tx_packet + ETH_HLEN + (s++)) = 0; + + w840private.tx_ring[entry].buffer1 + = virt_to_le32desc(w89c840_buf.tx_packet); + + w840private.tx_ring[entry].length = (DescWholePkt | (u32) s); + if (entry >= TX_RING_SIZE-1) /* Wrap ring */ + w840private.tx_ring[entry].length |= (DescIntr | DescEndRing); + w840private.tx_ring[entry].status = (DescOwn); + w840private.cur_tx++; + + w840private.tx_q_bytes = (u16) s; + writel(0, ioaddr + TxStartDemand); + + /* Work around horrible bug in the chip by marking the queue as full + when we do not have FIFO room for a maximum sized packet. */ + + if ((w840private.drv_flags & HasBrokenTx) && w840private.tx_q_bytes > TX_BUG_FIFO_LIMIT) { + /* Actually this is left to help finding error tails later in debugging... + * See Linux kernel driver in winbond-840.c for details. + */ + w840private.tx_full = 1; + } + +#if defined(W89C840_DEBUG) + printf("winbond-840 : Transmit frame # %d size %d queued in slot %d.\n", w840private.cur_tx, s, entry); +#endif + + /* Now wait for TX to complete. */ + transmit_status = w840private.tx_ring[entry].status; + + ct = currticks(); + { +#if defined W89C840_DEBUG + u32 intr_stat = 0; +#endif + while (1) { + +#if defined(W89C840_DEBUG) + decode_interrupt(intr_stat); +#endif + + while ( (transmit_status & DescOwn) && ct + TX_TIMEOUT < currticks()) { + + transmit_status = w840private.tx_ring[entry].status; + } + + break; + } + } + + if ((transmit_status & DescOwn) == 0) { + +#if defined(W89C840_DEBUG) + printf("winbond-840 : transmission complete after wait loop iterations, status %X\n", + w840private.tx_ring[entry].status); +#endif + + return; + } + + /* Transmit timed out... */ + + printf("winbond-840 : transmission TIMEOUT : status %X\n", + (unsigned int) w840private.tx_ring[entry].status); + + return; +} + +/************************************************************************** +w89c840_disable - Turn off ethernet interface +***************************************************************************/ +static void w89c840_disable ( struct nic *nic ) { + + w89c840_reset(nic); + + /* Don't know what to do to disable the board. Is this needed at all? */ + /* Yes, a live NIC can corrupt the loaded memory later [Ken] */ + /* Stop the chip's Tx and Rx processes. */ + writel(w840private.csr6 &= ~0x20FA, ioaddr + NetworkConfig); +} + +/************************************************************************** +w89c840_irq - Enable, Disable, or Force interrupts +***************************************************************************/ +static void w89c840_irq(struct nic *nic __unused, irq_action_t action __unused) +{ + switch ( action ) { + case DISABLE : + break; + case ENABLE : + break; + case FORCE : + break; + } +} + +static struct nic_operations w89c840_operations = { + .connect = dummy_connect, + .poll = w89c840_poll, + .transmit = w89c840_transmit, + .irq = w89c840_irq, + +}; + +static struct pci_device_id w89c840_nics[] = { +PCI_ROM(0x1050, 0x0840, "winbond840", "Winbond W89C840F", 0), +PCI_ROM(0x11f6, 0x2011, "compexrl100atx", "Compex RL100ATX", 0), +}; + +PCI_DRIVER ( w89c840_driver, w89c840_nics, PCI_NO_CLASS ); + +/************************************************************************** +w89c840_probe - Look for an adapter, this routine's visible to the outside +***************************************************************************/ +static int w89c840_probe ( struct nic *nic, struct pci_device *p ) { + + + u16 sum = 0; + int i, j; + unsigned short value; + + if (p->ioaddr == 0) + return 0; + + nic->ioaddr = p->ioaddr; + nic->irqno = 0; + +#if defined(W89C840_DEBUG) + printf("winbond-840: PCI bus %hhX device function %hhX: I/O address: %hX\n", p->bus, p->devfn, ioaddr); +#endif + + ioaddr = ioaddr & ~3; /* Mask the bit that says "this is an io addr" */ + +#define PCI_DEVICE_ID_WINBOND2_89C840 0x0840 +#define PCI_DEVICE_ID_COMPEX_RL100ATX 0x2011 + + /* From Matt Hortman <mbhortman@acpthinclient.com> */ + if (p->vendor == PCI_VENDOR_ID_WINBOND2 + && p->device == PCI_DEVICE_ID_WINBOND2_89C840) { + + /* detected "Winbond W89c840 Fast Ethernet PCI NIC" */ + + } else if ( p->vendor == PCI_VENDOR_ID_COMPEX + && p->device == PCI_DEVICE_ID_COMPEX_RL100ATX) { + + /* detected "Compex RL100ATX Fast Ethernet PCI NIC" */ + + } else { + /* Gee, guess what? They missed again. */ + printf("device ID : %X - is not a Compex RL100ATX NIC.\n", + p->device); + return 0; + } + + printf(" %s\n", w89c840_version); + + adjust_pci_device(p); + + /* Ok. Got one. Read the eeprom. */ + for (j = 0, i = 0; i < 0x40; i++) { + value = eeprom_read(ioaddr, i); + eeprom[i] = value; + sum += value; + } + + for (i=0;i<ETH_ALEN;i++) { + nic->node_addr[i] = (eeprom[i/2] >> (8*(i&1))) & 0xff; + } + + DBG ( "Ethernet addr: %s\n", eth_ntoa ( nic->node_addr ) ); + +#if defined(W89C840_DEBUG) + printf("winbond-840: EEPROM checksum %hX, got eeprom", sum); +#endif + + /* Reset the chip to erase previous misconfiguration. + No hold time required! */ + writel(0x00000001, ioaddr + PCIBusCfg); + + if (driver_flags & CanHaveMII) { + int phy, phy_idx = 0; + for (phy = 1; phy < 32 && phy_idx < 4; phy++) { + int mii_status = mdio_read(ioaddr, phy, 1); + if (mii_status != 0xffff && mii_status != 0x0000) { + w840private.phys[phy_idx++] = phy; + w840private.advertising = mdio_read(ioaddr, phy, 4); + +#if defined(W89C840_DEBUG) + printf("winbond-840 : MII PHY found at address %d, status " + "%X advertising %hX.\n", phy, mii_status, w840private.advertising); +#endif + + } + } + + w840private.mii_cnt = phy_idx; + + if (phy_idx == 0) { + printf("winbond-840 : MII PHY not found -- this device may not operate correctly.\n"); + } + } + + /* point to NIC specific routines */ + nic->nic_op = &w89c840_operations; + + w89c840_reset(nic); + + return 1; +} + +/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. These are + often serial bit streams generated by the host processor. + The example below is for the common 93c46 EEPROM, 64 16 bit words. */ + +/* Delay between EEPROM clock transitions. + No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need + a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that + made udelay() unreliable. + The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is + depricated. +*/ +#define eeprom_delay(ee_addr) readl(ee_addr) + +enum EEPROM_Ctrl_Bits { + EE_ShiftClk=0x02, EE_Write0=0x801, EE_Write1=0x805, + EE_ChipSelect=0x801, EE_DataIn=0x08, +}; + +/* The EEPROM commands include the alway-set leading bit. */ +enum EEPROM_Cmds { + EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6), +}; + +static int eeprom_read(long addr, int location) +{ + int i; + int retval = 0; + int ee_addr = addr + EECtrl; + int read_cmd = location | EE_ReadCmd; + writel(EE_ChipSelect, ee_addr); + + /* Shift the read command bits out. */ + for (i = 10; i >= 0; i--) { + short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0; + writel(dataval, ee_addr); + eeprom_delay(ee_addr); + writel(dataval | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + } + writel(EE_ChipSelect, ee_addr); + + for (i = 16; i > 0; i--) { + writel(EE_ChipSelect | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + retval = (retval << 1) | ((readl(ee_addr) & EE_DataIn) ? 1 : 0); + writel(EE_ChipSelect, ee_addr); + eeprom_delay(ee_addr); + } + + /* Terminate the EEPROM access. */ + writel(0, ee_addr); + return retval; +} + +/* MII transceiver control section. + Read and write the MII registers using software-generated serial + MDIO protocol. See the MII specifications or DP83840A data sheet + for details. + + The maximum data clock rate is 2.5 Mhz. The minimum timing is usually + met by back-to-back 33Mhz PCI cycles. */ +#define mdio_delay(mdio_addr) readl(mdio_addr) + +/* Set iff a MII transceiver on any interface requires mdio preamble. + This only set with older tranceivers, so the extra + code size of a per-interface flag is not worthwhile. */ +static char mii_preamble_required = 1; + +#define MDIO_WRITE0 (MDIO_EnbOutput) +#define MDIO_WRITE1 (MDIO_DataOut | MDIO_EnbOutput) + +/* Generate the preamble required for initial synchronization and + a few older transceivers. */ +static void mdio_sync(long mdio_addr) +{ + int bits = 32; + + /* Establish sync by sending at least 32 logic ones. */ + while (--bits >= 0) { + writel(MDIO_WRITE1, mdio_addr); + mdio_delay(mdio_addr); + writel(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr); + mdio_delay(mdio_addr); + } +} + +static int mdio_read(int base_address, int phy_id, int location) +{ + long mdio_addr = base_address + MIICtrl; + int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location; + int i, retval = 0; + + if (mii_preamble_required) + mdio_sync(mdio_addr); + + /* Shift the read command bits out. */ + for (i = 15; i >= 0; i--) { + int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; + + writel(dataval, mdio_addr); + mdio_delay(mdio_addr); + writel(dataval | MDIO_ShiftClk, mdio_addr); + mdio_delay(mdio_addr); + } + /* Read the two transition, 16 data, and wire-idle bits. */ + for (i = 20; i > 0; i--) { + writel(MDIO_EnbIn, mdio_addr); + mdio_delay(mdio_addr); + retval = (retval << 1) | ((readl(mdio_addr) & MDIO_DataIn) ? 1 : 0); + writel(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr); + mdio_delay(mdio_addr); + } + return (retval>>1) & 0xffff; +} + +#if 0 +static void mdio_write(int base_address, int phy_id, int location, int value) +{ + long mdio_addr = base_address + MIICtrl; + int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value; + int i; + + if (location == 4 && phy_id == w840private.phys[0]) + w840private.advertising = value; + + if (mii_preamble_required) + mdio_sync(mdio_addr); + + /* Shift the command bits out. */ + for (i = 31; i >= 0; i--) { + int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; + + writel(dataval, mdio_addr); + mdio_delay(mdio_addr); + writel(dataval | MDIO_ShiftClk, mdio_addr); + mdio_delay(mdio_addr); + } + /* Clear out extra bits. */ + for (i = 2; i > 0; i--) { + writel(MDIO_EnbIn, mdio_addr); + mdio_delay(mdio_addr); + writel(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr); + mdio_delay(mdio_addr); + } + return; +} +#endif + +static void check_duplex(void) +{ + int mii_reg5 = mdio_read(ioaddr, w840private.phys[0], 5); + int negotiated = mii_reg5 & w840private.advertising; + int duplex; + + if (w840private.duplex_lock || mii_reg5 == 0xffff) + return; + + duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040; + if (w840private.full_duplex != duplex) { + w840private.full_duplex = duplex; + +#if defined(W89C840_DEBUG) + printf("winbond-840 : Setting %s-duplex based on MII # %d negotiated capability %X\n", + duplex ? "full" : "half", w840private.phys[0], negotiated); +#endif + + w840private.csr6 &= ~0x200; + w840private.csr6 |= duplex ? 0x200 : 0; + } +} + +static void set_rx_mode(void) +{ + u32 mc_filter[2]; /* Multicast hash filter */ + u32 rx_mode; + + /* Accept all multicasts from now on. */ + memset(mc_filter, 0xff, sizeof(mc_filter)); + +/* + * works OK with multicast enabled. + */ + + rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; + + writel(mc_filter[0], ioaddr + MulticastFilter0); + writel(mc_filter[1], ioaddr + MulticastFilter1); + w840private.csr6 &= ~0x00F8; + w840private.csr6 |= rx_mode; + writel(w840private.csr6, ioaddr + NetworkConfig); + +#if defined(W89C840_DEBUG) + printf("winbond-840 : Done setting RX mode.\n"); +#endif +} + +/* Initialize the Rx and Tx rings, along with various 'dev' bits. */ +static void init_ring(void) +{ + int i; + char * p; + + w840private.tx_full = 0; + w840private.tx_q_bytes = w840private.cur_rx = w840private.cur_tx = 0; + w840private.dirty_rx = w840private.dirty_tx = 0; + + w840private.rx_buf_sz = PKT_BUF_SZ; + w840private.rx_head_desc = &w840private.rx_ring[0]; + + /* Initial all Rx descriptors. Fill in the Rx buffers. */ + + p = &w89c840_buf.rx_packet[0]; + + for (i = 0; i < RX_RING_SIZE; i++) { + w840private.rx_ring[i].length = w840private.rx_buf_sz; + w840private.rx_ring[i].status = 0; + w840private.rx_ring[i].next_desc = virt_to_le32desc(&w840private.rx_ring[i+1]); + + w840private.rx_ring[i].buffer1 = virt_to_le32desc(p + (PKT_BUF_SZ * i)); + w840private.rx_ring[i].status = DescOwn | DescIntr; + } + + /* Mark the last entry as wrapping the ring. */ + w840private.rx_ring[i-1].length |= DescEndRing; + w840private.rx_ring[i-1].next_desc = virt_to_le32desc(&w840private.rx_ring[0]); + + w840private.dirty_rx = (unsigned int)(i - RX_RING_SIZE); + + for (i = 0; i < TX_RING_SIZE; i++) { + w840private.tx_ring[i].status = 0; + } + return; +} + + +DRIVER ( "W89C840F", nic_driver, pci_driver, w89c840_driver, + w89c840_probe, w89c840_disable ); + +/* + * Local variables: + * c-basic-offset: 8 + * c-indent-level: 8 + * tab-width: 8 + * End: + */ diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/nvs/nvs.c b/debian/grub-extras/disabled/gpxe/src/drivers/nvs/nvs.c new file mode 100644 index 0000000..7252808 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/nvs/nvs.c @@ -0,0 +1,149 @@ +/* + * Copyright (C) 2006 Michael Brown <mbrown@fensystems.co.uk>. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <stdint.h> +#include <string.h> +#include <errno.h> +#include <assert.h> +#include <gpxe/nvs.h> + +/** @file + * + * Non-volatile storage + * + */ + +/** + * Read from non-volatile storage device + * + * @v nvs NVS device + * @v address Address from which to read + * @v data Data buffer + * @v len Length of data buffer + * @ret rc Return status code + */ +int nvs_read ( struct nvs_device *nvs, unsigned int address, + void *data, size_t len ) { + size_t frag_len; + int rc; + + /* We don't even attempt to handle buffer lengths that aren't + * an integral number of words. + */ + assert ( ( len & ( ( 1 << nvs->word_len_log2 ) - 1 ) ) == 0 ); + + while ( len ) { + + /* Calculate space remaining up to next block boundary */ + frag_len = ( ( nvs->block_size - + ( address & ( nvs->block_size - 1 ) ) ) + << nvs->word_len_log2 ); + + /* Limit to space remaining in buffer */ + if ( frag_len > len ) + frag_len = len; + + /* Read this portion of the buffer from the device */ + if ( ( rc = nvs->read ( nvs, address, data, frag_len ) ) != 0 ) + return rc; + + /* Update parameters */ + data += frag_len; + address += ( frag_len >> nvs->word_len_log2 ); + len -= frag_len; + } + + return 0; +} + +/** + * Verify content of non-volatile storage device + * + * @v nvs NVS device + * @v address Address from which to read + * @v data Data to compare against + * @v len Length of data buffer + * @ret rc Return status code + */ +static int nvs_verify ( struct nvs_device *nvs, unsigned int address, + const void *data, size_t len ) { + uint8_t read_data[len]; + int rc; + + /* Read data into temporary buffer */ + if ( ( rc = nvs_read ( nvs, address, read_data, len ) ) != 0 ) + return rc; + + /* Compare data */ + if ( memcmp ( data, read_data, len ) != 0 ) { + DBG ( "NVS %p verification failed at %#04x+%zd\n", + nvs, address, len ); + return -EIO; + } + + return 0; +} + +/** + * Write to non-volatile storage device + * + * @v nvs NVS device + * @v address Address to which to write + * @v data Data buffer + * @v len Length of data buffer + * @ret rc Return status code + */ +int nvs_write ( struct nvs_device *nvs, unsigned int address, + const void *data, size_t len ) { + size_t frag_len; + int rc; + + /* We don't even attempt to handle buffer lengths that aren't + * an integral number of words. + */ + assert ( ( len & ( ( 1 << nvs->word_len_log2 ) - 1 ) ) == 0 ); + + while ( len ) { + + /* Calculate space remaining up to next block boundary */ + frag_len = ( ( nvs->block_size - + ( address & ( nvs->block_size - 1 ) ) ) + << nvs->word_len_log2 ); + + /* Limit to space remaining in buffer */ + if ( frag_len > len ) + frag_len = len; + + /* Write this portion of the buffer to the device */ + if ( ( rc = nvs->write ( nvs, address, data, frag_len ) ) != 0) + return rc; + + /* Read back and verify data */ + if ( ( rc = nvs_verify ( nvs, address, data, frag_len ) ) != 0) + return rc; + + /* Update parameters */ + data += frag_len; + address += ( frag_len >> nvs->word_len_log2 ); + len -= frag_len; + } + + return 0; +} diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/nvs/spi.c b/debian/grub-extras/disabled/gpxe/src/drivers/nvs/spi.c new file mode 100644 index 0000000..793080a --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/nvs/spi.c @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2006 Michael Brown <mbrown@fensystems.co.uk>. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <stddef.h> +#include <errno.h> +#include <unistd.h> +#include <gpxe/spi.h> + +/** @file + * + * SPI devices + * + */ + +/** + * Munge SPI device address into command + * + * @v command SPI command + * @v address Address + * @v munge_address Device requires address munging + * @ret command Actual SPI command to use + * + * Some devices with 9-bit addresses (e.g. AT25040A EEPROM) use bit 3 + * of the command byte as address bit A8, rather than having a + * two-byte address. This function takes care of generating the + * appropriate command. + */ +static inline unsigned int spi_command ( unsigned int command, + unsigned int address, + int munge_address ) { + return ( command | ( ( ( address >> 8 ) & munge_address ) << 3 ) ); +} + +/** + * Wait for SPI device to complete operation + * + * @v device SPI device + * @ret rc Return status code + */ +static int spi_wait ( struct spi_device *device ) { + struct spi_bus *bus = device->bus; + uint8_t status; + int i; + int rc; + + for ( i = 0 ; i < 50 ; i++ ) { + udelay ( 20 ); + if ( ( rc = bus->rw ( bus, device, SPI_RDSR, -1, NULL, + &status, sizeof ( status ) ) ) != 0 ) + return rc; + if ( ! ( status & SPI_STATUS_NRDY ) ) + return 0; + } + DBG ( "SPI %p timed out\n", device ); + return -ETIMEDOUT; +} + +/** + * Read data from SPI device + * + * @v nvs NVS device + * @v address Address from which to read + * @v data Data buffer + * @v len Length of data buffer + * @ret rc Return status code + */ +int spi_read ( struct nvs_device *nvs, unsigned int address, + void *data, size_t len ) { + struct spi_device *device = nvs_to_spi ( nvs ); + struct spi_bus *bus = device->bus; + unsigned int command = spi_command ( SPI_READ, address, + device->munge_address ); + int rc; + + DBG ( "SPI %p reading %zd bytes from %#04x\n", device, len, address ); + if ( ( rc = bus->rw ( bus, device, command, address, + NULL, data, len ) ) != 0 ) { + DBG ( "SPI %p failed to read data from device\n", device ); + return rc; + } + + return 0; +} + +/** + * Write data to SPI device + * + * @v nvs NVS device + * @v address Address from which to read + * @v data Data buffer + * @v len Length of data buffer + * @ret rc Return status code + */ +int spi_write ( struct nvs_device *nvs, unsigned int address, + const void *data, size_t len ) { + struct spi_device *device = nvs_to_spi ( nvs ); + struct spi_bus *bus = device->bus; + unsigned int command = spi_command ( SPI_WRITE, address, + device->munge_address ); + int rc; + + DBG ( "SPI %p writing %zd bytes to %#04x\n", device, len, address ); + + if ( ( rc = bus->rw ( bus, device, SPI_WREN, -1, + NULL, NULL, 0 ) ) != 0 ) { + DBG ( "SPI %p failed to write-enable device\n", device ); + return rc; + } + + if ( ( rc = bus->rw ( bus, device, command, address, + data, NULL, len ) ) != 0 ) { + DBG ( "SPI %p failed to write data to device\n", device ); + return rc; + } + + if ( ( rc = spi_wait ( device ) ) != 0 ) { + DBG ( "SPI %p failed to complete write operation\n", device ); + return rc; + } + + return 0; +} + diff --git a/debian/grub-extras/disabled/gpxe/src/drivers/nvs/threewire.c b/debian/grub-extras/disabled/gpxe/src/drivers/nvs/threewire.c new file mode 100644 index 0000000..8e52138 --- /dev/null +++ b/debian/grub-extras/disabled/gpxe/src/drivers/nvs/threewire.c @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2006 Michael Brown <mbrown@fensystems.co.uk>. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <stddef.h> +#include <string.h> +#include <assert.h> +#include <unistd.h> +#include <gpxe/threewire.h> + +/** @file + * + * Three-wire serial devices + * + */ + +/** + * Read data from three-wire device + * + * @v nvs NVS device + * @v address Address from which to read + * @v data Data buffer + * @v len Length of data buffer + * @ret rc Return status code + */ +int threewire_read ( struct nvs_device *nvs, unsigned int address, + void *data, size_t len ) { + struct spi_device *device = nvs_to_spi ( nvs ); + struct spi_bus *bus = device->bus; + int rc; + + assert ( bus->mode == SPI_MODE_THREEWIRE ); + + DBGC ( device, "3wire %p reading %zd bytes at %04x\n", + device, len, address ); + + if ( ( rc = bus->rw ( bus, device, THREEWIRE_READ, address, + NULL, data, len ) ) != 0 ) { + DBGC ( device, "3wire %p could not read: %s\n", + device, strerror ( rc ) ); + return rc; + } + + return 0; +} + +/** + * Write data to three-wire device + * + * @v nvs NVS device + * @v address Address from which to read + * @v data Data buffer + * @v len Length of data buffer + * @ret rc Return status code + */ +int threewire_write ( struct nvs_device *nvs, unsigned int address, + const void *data, size_t len ) { + struct spi_device *device = nvs_to_spi ( nvs ); + struct spi_bus *bus = device->bus; + int rc; + + assert ( bus->mode == SPI_MODE_THREEWIRE ); + + DBGC ( device, "3wire %p writing %zd bytes at %04x\n", + device, len, address ); + + /* Enable device for writing */ + if ( ( rc = bus->rw ( bus, device, THREEWIRE_EWEN, + THREEWIRE_EWEN_ADDRESS, NULL, NULL, 0 ) ) != 0 ){ + DBGC ( device, "3wire %p could not enable writing: %s\n", + device, strerror ( rc ) ); + return rc; + } + + /* Write data */ + if ( ( rc = bus->rw ( bus, device, THREEWIRE_WRITE, address, + data, NULL, len ) ) != 0 ) { + DBGC ( device, "3wire %p could not write: %s\n", + device, strerror ( rc ) ); + return rc; + } + + /* Our model of an SPI bus doesn't provide a mechanism for + * "assert CS, wait for MISO to become high, so just wait for + * long enough to ensure that the write has completed. + */ + mdelay ( THREEWIRE_WRITE_MDELAY ); + + return 0; +} + +/** + * Autodetect device address length + * + * @v device SPI device + * @ret rc Return status code + */ +int threewire_detect_address_len ( struct spi_device *device ) { + struct nvs_device *nvs = &device->nvs; + int rc; + + DBGC ( device, "3wire %p autodetecting address length\n", device ); + + device->address_len = SPI_AUTODETECT_ADDRESS_LEN; + if ( ( rc = threewire_read ( nvs, 0, NULL, + ( 1 << nvs->word_len_log2 ) ) ) != 0 ) { + DBGC ( device, "3wire %p could not autodetect address " + "length: %s\n", device, strerror ( rc ) ); + return rc; + } + + DBGC ( device, "3wire %p autodetected address length %d\n", + device, device->address_len ); + return 0; +} |